30002-3_DQ130_Magnetic_Tape_Coupler_Jan84.pdf

30002-3_DQ130_Magnetic_Tape_Coupler_Jan84.pdf

MODEL DQ130

MAGNETIC TAPE COUPLER

INSTRUCTION MANUAL

January 1984

DISTRI. BUTEO LOGIC CORPORATION

~5~~ :~xS~~~~ir

Street

O

I

L

I mm

Anaheim. California 92806

Telephone: (714) 937.5700

Telex: 6836051

Part Number 30002·3

Copyright © 1984 by

Distributed Logic Corporation

Printed in the United States of America

TABLE OF CONTENTS

Section

1

Page

DESCRInION ................................................................. 1-1

INTRODUCTION .............................................................. 1-1

COUPLER CHARACTERISTICS ................................................ 1-1

LSI-II

Q

BUS INTERFACE ..................................................... 1-2

FORMATTER INTERFACE .................................................... 1-2

TAPE FORMAT COMPATIBILITY .............................................. 1-2

INTERRUP'f .................................................................. 1-2

COUPLER SPECIFICATIONS ................................................... 1-4

2 INSTALLATION ................................................................ 2-1

INSPECTION ....................

~

............................................ 2-1

PRE-INSTALLATION CHECKS ............................................... , .2-1

INSTALLATION .............................................................. 2-1

3

4

5

OPERATION ................................................................... 3-1

INTRODUCTION .............................................................. 3-1

TAPE FORMAT ............................................................... 3-1

BOOTING FROM MAGNETIC TAPES ........................................... 3-1

PROGRAMMING ............................................................... 4·1

PROG RAMMING DEFINITIONS ................................................ 4-1

TAPE COUPLER FUNCTIONS AND REGISTERS ................................ 4-1

Status Register (MTS) ......................................................... 4·2

Command (MTC) ............................................................. 4-4

Byte Record Counter (MTBRC) .................................................. 4-5

Current Memory Address (MTCMA) ............................................. 4-5

Data Buffer (MTD) ............................................................ 4-6

Tape Read Lines (MTRD) .....................................................

~

.4-6

TROUBLESHOOTING AND THEORY ............................................. 5-1

BASIC SYSTEM TROUBLESHOOTING .......................................... 5-1

COUPLER SYMPTOMS ........................................................ 5·1

PHYSICAL LAYOUT .......................................................... 5-1

TERM LISTING .......................................................... ; .... 5-1

'~

.. ; ... 5-5

Computer Interface ........................................................... 5·5

Microprocessor ............................................................... 5-8

Peripheral Interface .......................................................... 5-12

LOGICS iii

ILLUSTRATIONS

2-1

4-1

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

Figure

I-I

1-2

Page

Tape System With Two Embedded-Formatter Tape Drives ............................... I-I

Tape System (Maximum Configuration) Two Embedded-Formatter Tape Drives With Three

Slave Tape Drives Each ..........................................................

1-2

Coupler Configuration .............................................................

2-2

Controller Register Configurations ..................................................

4-2

Board Layout ...................................................................

5-3

Simplified Block Diagram ..........................................................

5-6

DATI-Slave, Q Bus ..............................................................

5-7

DATO-Slave, Q Bus Transfers .....................................................

5-7

DATO-Q Bus DMA Timing .......................................................

5-9

Microinstruction Word ...........................................................

5-11

TABLES

Table

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

I-I

1-2

1-3

1-4

4-1

Page

Coupler/Q-Bus Interface Lines ......................................................

1-3

Coupler Connector

J1 to Formatter Interface Lines .....................................

1-4

Coupler Connector J2 to Formatter Interface Lines .....................................

1-4

Coupler to Formatter Connector Correlation ...........................................

1-4

Function Codes ..................................................................

4-1

Coupler Symptoms ...............................................................

5-2

Term Listing ....................................................................

5-4

Coupler Buses ..................................................................

5-10

Coupler Register Storage .........................................................

5-10

Control Inputs To

2901 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Status Register Bits .............................................................

5-11

Information Sources to D Bus .....................................................

5-12 iv

SECTION 1

DESCRIPTION

INTRODUCTION

This manual describes the installation. operation. programming. troubleshooting and theory of operation of Distributed Logic Corporation (DILOG)

Model DQ130 Magnetic Tape Coupler. The coupler interfaces DEC· LSI-II based computer systems to

Industry-Standard formatted magnetic tape drives.

The coupler and the drive comprise a complete

LSI -11 compatible 9-track magnetic tape subsystem. Magnetic tape drives from manufacturers other than DEC can be used while still retaining software and format compatibility with the DEC

TM-ll Tape System. Data transfers are via the

DMA facility of the LSI·l1. Transfer rates vary. depending upon the density and speed of the drives included in the system, between 10,000 and 200,000 characters per second. The complete coupler occupies one quad module in the backplane.

COUPLER CHARACTERISTICS

Up to two embedded-formatter tape drives or external stand-alone tape formatters may be connected to the coupler. Each embedded-formatter tape drive is capable of handling an additional three slave drives. All Industry-Standard. external standalone formatters are capable of handling up to four drives. The coupler can accommodate up to eight

-DEC is a registered trademark of Digital Equipment

Corporation. drives. Figures

1-1 and 1-2 illustrate two configura tions.

The optimal usage of the coupler is in situations where 9-track. dual density,

800/1600/3200

bpi tape recording capabilities are required; however, the coupler is compatible with single density 800, 1600 or 3200 bpi embedded-formatter tape drives or stand-alone external formatters.

The primary functions of the coupler in a magnetic tape subsystem are to buffer and interlock data and status transfers between the computer 110 bus and the tape formatter. and to translate CPU commands into tape formatter control signals such as Start, Stop, Rewind, Generate IR Gap, Generate

EOF Gap. The primary function of the formatter is to control tape motion, establish data format, and perform error checking. The overall tape control function is a combination of the coupler functions, which are related to the LSI-II, and the formatter functions, which are related to the tape drives.

A microprocessor is the sequence and timing center of the coupler. The control information is stored as fumware instructions in Programmable

Read-Only Memory (PROM) on the coupler board.

One section of the PROM contains a diagnostic program that tests the functional operation of the coupler. This self-test is performed automatically each time power is applied or whenever an INIT command is issued on the CPU I/O bus. A green

LSI·11 a

BUS

CONTROL 22

DATA ADDRESSl16

EXTENDED ADDRESS/2

POWER·GROUND w o

<I( oLi.

-0::

-w

~

~

0:: o en w o o

0::

Q, o

0:: o

~

TAPE COUPLER

FORMATTER I/O BUS

EMBEDDED

FORMATTER

TAPE DRIVE .1

Figure 1-1. Tape System With Two Embedded-Formatter Tape Drives

EMBEDDED

FORMATTER

TAPE DRIVE

.2

I-I

LSI·l1 a BUS

CONTROL 22 •

%-

~

~

DATA ADDRESS/16

-

~-

~

~

_ EXTENDED ADDRESS/2 •

~

POWER·GROUND

--=.J

J a: o en en

W

U o a:

Cl. o a: u

~ a:w

Wu

I-c(

I-I.L c(a:

~w a:

I-

Oz

I.L-

' - - - _ . _ - - - - - _ .

._--

FORMAnER 110 BUS

,

I

EMBEDDED EMBEDDED

~

FORMAnER FORMAnER

- - - - - - - - -+~ - - - - - - -

MASTER MASTER

TAPE DRIVE TAPE DRIVE

--14-

SLAVE

TAPE

DRIVE

SLAVE

TAPE

DRIVE en

~ g f+-

W

>

Ii

0

W

Cl. c( l -

SLAVE

TAPE

DRIVE

SLAVE

TAPE

DRIVE en

~ g f4-

W

>

Ii

0

W

Cl. c(

I-

SLAVE

TAPE

DRIVE

~

SLAVE

TAPE

DRIVE

4-

Figure 1-2. Tape System (Maximum Configuration) Two Embedded-Formatter Tape

Drives With Three Slave Tape Drives Each diagnostic indicator on the board lights if self-test passes. If self-test fails. the coupler has an automatic data protect feature that stops the CPU from interacting with the tape formatter. and thus prevents writing erroneous information into critical data base areas.

Two additional indicators on the coupler board display dynamic operating conditions to an operator. The conditions displayed are Coupler

Busy and Coupler Transferring Data (DMA Busy).

LSI-II

Q

BUS INTERFACE

Commands. data and status transfers between the coupler and the computer are executed via the parallel 110 bus (Q Bus) of the computer directly to memory. via the DMA facility of the Q Bus.

Coupler/Q Bus interface signals are listed in Table

I-I.

FORMATTER INTERFACE

The coupler interfaces with the formatted tape drives through two 50-pin nat cable connectors at the top of the coupler board. The maximum cable length between coupler and formatter is 25 feet.

Coupler/formatter interface signals are listed in

Tables 1-2 and 1-3.

1·2

Table 1-4 lists some manufacturers and connector correlations.

CAUTION

Cable cunnections and interface signals

.'lhould be checked from the drive manufacturers' manuals to ensure the latest configurations are installed currectly. Incorrect cabling may cause damage to the coupler or the drive.

TAPE FORMAT COMPATIBILITY

The coupler can cause the formatter to create a tape in an IBM format. By cutting an etch. the high byte will be written first followed by the low byte.

With a jumper (etch) installed. the format will be low byte first followed by the high byte. The tape can be created on the DEC system and run and read on another system.

INTERRUPT

The interrupt vector address is factory set to address 224, which is compatible with TM-ll software. Interrupts are generated when processor attention is required or when an error occurs.

Bus Pin

AJ1, AM1, Rn, BJ1, BM1,

BT1, BC2, CJ1. CM1, CT1.

CC2. DJ1, DM1. DT1. DC2

AN1

AP1

AR1

BA1

BB1

BN1

BR1

BV1.AA2.BA2.CA2,DA2

AD2. BD2

AE2

AF2

AH2

AJ2

AK2

AL2

AM2

AN2

CM2

CN2

AT2

AU2. AV2. BE2. BF2. BH2.

BJ2. BK2. BL2, BM2. BN2.

BP2. BR2. BS2. BT2. BU2.

BV2

AR2

AS2

CR2

CS2

AP2

Table 1·1. Coupler/Q·Bus Interface Lines

Mnemonic

GND

Controller

InputJ

Output

0

Description

Signal Ground and DC return.

BWTBT L

BIRO L

BIAK11 L

BIAK10 L

BIAK21 L

BIAK20 L

BINIT L

BDALO L through

BDAL15 L

BDMG11 L

BDMG10 L

BDMG21 L

BDMG20 L

BBS7 L

BDMR L

BHALT L

BREF L

BDCOK H

BPOK H

BSACK L

BEVNT L

+5

+ 12

BDOUT L

BRPLY L

BDIN L

BSYNC L a

N/A

0

I

0

I

0

I

I

0

I

0

I

Direct Memory Access (DMA) request from coupler: active low.

Stops program execution. Refresh and DMA are enabled.

Console operation is enabled.

N/A Memory Refresh.

DC power OK. All DC voltages are normal.

I

N/A

Primary power OK. When low activates power fail trap sequence.

0

Select Acknowledge. Interlocked with BDMGO indicating coupler is bus master in a DMA sequence.

N/A External Event Interrupt Request.

I

+ 5 volt system power.

N/A + 12 volt system power.

110 Data Out. Valid data from bus master is on the bus. Interlocked with BRPLY.

Reply from slave to BDOUT or BDIN and during IAK.

110

110

I/O

Data Input. Input transfer to master (states master is ready for data). Interlocked with BRPLY.

Synchronize: becomes active when master places address on bus: stays active during transfer.

110

110

Write Byte: indicates output sequence to follow (DATa or

DATOB) or marks byte address time during a DATOB.

Interrupt Request.

Serial Interrupt Acknowledge input and output lines routed from o

Bus. through devices, and back to processor to establish an interrupt priority chain.

Initialize. Clears devices on

Data/address lines. 0·15

·110 bus.

DMA Grant Input and Output. Serial DMA priority line from computer. through devices and back to computer.

Bank 7 Select. Asserted by bus master when address in upper

4K bank is placed on the bus.

1·3

Table 1-2. Coupler Connector

Interface Lines

Jl

Formatter

18

20

22

24

26

28

30

32

34

36

10

12

14

16

4

6

8

1

2

3

38

40

42

44

46

48

50

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

J1 J1

Signal

Return

Mnemonic

FRDP

FRDO

FRD1

FLOP

FRD4

FRD7

FRD6

FHER

FFMK

FCC Gil 0

FFEN

FRD5

FEOT

FOFL

FNRZ

FRDY

FRWD

FFPT

FRSTR

FDWDS

FDBY

FCER

FONL

FTAD1

FFAD

FDEN

Description

Read Data Parity

Read Data 0

Read Data 1

Load Point

Read Data 4

Read Data 7

Read Data 6

Hard Error

File Mark

CCG/IDENT

Formatter Enable

Read Data 5

End of Tape

Off Line

NRZI

Ready

Rewinding

File Protect

Read Strobe

Demand Write Data

Strobe

Data Busy

Not Used

Corrected Error

On·Line

Transport Address 1

Formatter Address

Speed/Density Select

Table 1-4. Coupler to Formatter Connection

Correlation

Coupler Connector J1 to:

Manufacturer

Model

CDC

Cipher

Digi·Data lOT

Kennedy

Pertec

9218X

F880

F100X, F900X

(Adapter required)

Formatted

1012

1050

6809 Streamer

Formatted

Formatted

External Formatter

(Adapter required)

Coupler Connector J2 to:

Manufacturer

CDC

Cipher

Oigi·Data lOT

Kennedy

Pcrtec

Model

9218X

F880

F100X. F900X

(Adapter required)

Formatted

1012

1050

6809 Streamer

Formatted

Formatted

External Formatter

(Adapter required)

Connector

J5

P2

P5

JD

J2

J125

J2

J1

P5

P5

Connector

J4

P1

P4

JC

J1

J124

J1

J5

P4

P4

Table 1-3. Coupler Connector J2 to Formatter

Interface Lines

J2

J2

Signal Return Mnemonic

Description

8

10

12

14

16

2

4

6

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

FFBY

FLWD

FWD4

FGO

FWDO

FWD1

FLOL

FREV

FREW

FWDP

FWD7

FWD3

FWD6

FWD2

FWD5

FWRT

FRTH2

FLGAp·

FEDIT

FERASE

FWFM

FRTH1

(SPARE)

FTAOO

FRD2

FR03

Formatter Busy

Last Word

Write Data 4

Initiate Command

Write Data 0

Write Data 1

Not Used

Load on Line

Reverse/Forward

Rewind

Not Used

Write Data 7

Write Data 3

Write Data 6

Write Data 2

Write Data 5

Write/Read

Read Threshold 2

Edit

Erase

Write File Mark

Read Threshold 1

Transport Address 0

Read Data 2

Read Data 3

·Signal applicable to CDC Keystone drives.

1-4

COUPLER SPECIFICATIONS·

Data Format

• Industry-Standard non-return-to-zero (NRZ) or

Phase Encoded (PE) recording.

• 9 tracks

Recording densities:

• 800 characters per inch

• 1600 characters per inch

• 3200 characters per inch

• Interrecord gap 0.60 inch min.

• Tape parity marks: LPC. CRC. LRC

Media Characteristics

Type

• 1/2 " wide mylar base. oxide coated, magnetic tape.

Reel Size

• 7",

Blf2",

or

10lf2"

diameter tape reels containing 600, 1,200 and 2,400 feet of tape respectively.

Data Capacity (megabytes)

• Assumes aproximate

BO%

recording efficiency:

600 Ft.

1.200 Ft.

2.400 Ft.

BOO

CPI 1600 CPI 3200 CPI

5.75

11.5

22.0

11.5

23.0

44.0

23.0

46.0

BB.O

Data Transfer Rate (Characters/Second)

800 CPI 1600 CPI 3200 CPI

12.5 ips

25.0 ips

37.5 ips

45.0 ips

75.0 ips

125.0 ips

=

10,000 20,000 20,000

=

20,000

40,000 40,000

=

30,000 60,000 60,000

=

36,000 72,000 72,000

=

60,000 120,000 120,000

=

100,000 200,000 200,000

Register Address

• Status (MTS) 772 520

• Command (MTC) 772 522

• Byte Record Counter (MTBRC) 772 524

• Current Memory Address (MTCMA) 772 526

• Data Buffer (MTD) 772 530

• Tape Read Lines (MTRD) 772 532

Computer Interface

• Interrupt Vector Address 224. DMA data transfer. 1 bus load all lines.

Coupler/Formatter Interface

• Coupler is compatible with formatters manufactured by Pertec, Kennedy, Tandberg,

Cipher, CDC, Digi-Data.

Packaging

• The coupler is completely containedonone quad module 10.44 inches wide by 8.88 inches deep.

Documentation

• One instruction manual is supplied' with the coupler.

Software

• One diagnostic routine with object listing is supplied with a coupler (or the first of a series of couplers).

Power

• +5, ±0.25 VDC at 3.6 amps, from computer backplane.

Environment

• Operating temperature 40°F to

140°F

• Operating humidity 10% to 95% noncondensing.

Note

The quality of recording and reading information

on

magnetic tape is affected by temperature and humidity. The area where the tape

is

used should be maintained within the following limits:

. Temperature: 60 of to

90

of

Humidity: 20% to 80%

Shipping Weight

• 5 pounds including documentation.

·Specifications subject to change without notice.

1·5

SECTION 2

INSTALLATION

INSPECTION

The padded shipping carton that contains the coupler board also contains an instruction manual and cables to the magnetic tape drives (if this option is exercised). The coupler is completely contained on one quad-size printed circuit board. The drive (or drives). if supplied. is contained in a separate shipping carton. Inspect the coupler and cable(s) for damage.

CAUTION

If damage to any of the components is noted, do not instalL Immediately inform the carrier and DILDO.

Installation instructions for the tape drive are contained in the tape drive manual. Before installing any components of the magnetic tape system. read Sections 1. 2 and 3 of this manual. Figure 2-1 illustrates the configuration of the coupler.

PRE-INSTALLATION CHECKS

There are various LSI-II configurations for

LSI -11 based systems. Certain configurations require minor modifications before operating the magnetic tape system. These modifications are as follows:

A. If the system contains a REVIl-C module. it must be placed closer to the processor module

(higher priority) than the coupler if the DMA refresh logic on the REVll-C is enabled.

B. If the 4K memory on the DKll-F is not used and the memory in the system does not require external refresh. the DMA refresh logic on the REV ll-C should be disabled by removing jumper W2 on the REVll-C module. .

C. If the system contains a REVll-A module. the refresh DMA logic must be disabled since the module must be placed at the end of the bus (REVII-A contains bus terminator).

D.

If the REVll-C module is installed, cut the etch to pin 12 on circuit D30 (top of board) and add a jumper between pin 12 and pin 13 of D30.

E. If the system requires more than one backplane. place the REV-II terminator in the last available location in the last backplane.

INSTALLATION

To install the coupler module. proceed as follows:

CAUTION

Remove DC power from mounting assembly before inserting or removing the coupler module.

Damage to the backplane assembly may occur if the coupler module is plugged in backwards.

1.

Select the backplane location into which the coupler is to be inserted.

There are several backplane assemblies available from DEC and other manufacturers. Figure 2-2 shows typical backplane configurations. Note that the processor module is always installed in the first location of the backplane or in the first location in the first backplane of multiple backplane systems.

It is important that all option slots between the processor and the coupler be filled to ensure that the daisy-chained interrupt

(BIAK) and DMA (BDMG) signals be complete to the coupler slots. If there must be empty slots between the coupler and any option board, the following backplane jumpers must be installed:

FROM TO

CO x NS CO x M2

CO x S2 CO x R2 t t

Last Full Coupler Slot

Option Slot

SIGNAL

BIAKlILO

BDMGlILO

2. Ensure the switch and jumpers are as shown in Figure 2-1.

2-1

PIN 1

A711

...-

NON·STREAM

BUSY~

DIAG

8.9

OE5-

E13 0 E6

_

1

- - - -

1

..... - - - - - - - - - - - - - - 10.5

V1

A1

2·2

-When jumper is installed at E13. coupler writes DEC Format (low byte first. high byte second).

When jumper is removed at E13. coupler writes IBM format (high byte first. low byte second).

LOCATION A7

Logical

Unit

Addressed

5

6

7

0

1

2

3

4

Stream Switch OFF

Formatter

Addressed

1

1

1

0

0

0

0

1

Physical

Drive

Addressed

3

0

1

2

3

0

1

2

Stream Switch ON-

Logical

Unit

Addressed

0

1

2

3

4

5

6

7

Mode

Stop/Start

Stop/Start

Stop/Start

Stop/Start

Streaming

Streaming

Streaming

Streaming

Physical

Drive

Addressed

0

1

2

3

0

1

2

3

- Formatter Addressed Always O.

Older coupler boards (Rev. E and earlier) contain Jumpers El. E2. E3 and E4 at Location A7. rather than the

STREAM switch (Rev. F and later). The older boards operated only in an 18-bit addressing mode: the newer ones are capable of 22-bit addressing. For the older boards to operate in the Streamer mode. the following changes must be made:

Factory Set

Start/Stop

Mode:

To Operate

In Streamer

Mode:

El

0

E2

?

E3

r/

0

E4

Figure 2·1. Coupler ComiguratioD

LOCATION A

B C D

PROCESSOR

MODULE ,.

."

.

2

3

4

E

OPTION 2

OPTION 3

OPTION 6

OPTION 1

OPTION 4

OPTION 5 t

COMPONENT SIDE

SOLDER SIDE

!

PREFERRED

COUPLER LOCATION

H9270 MODULE INSERTION SIDE

A B C

0

V

OPTION 1 OPTION 2

+12V

-

0

-5V

+5V

+5VB

..iL

~-

0

GND g

-:...-

GND

~

-12V

~

POWER

TERMINA

L /

BLOCK

OPTION 3

OPTION 6

OPTION

7

OPTION 10

OPTION 11

OPTION

14

OPTION 15

OPTION

4

OPTION 5

OPTION 8

OPTION 9

OPTION 12

OPTION 13

OPTION 16

"

PREFERRED

COUPLER LOCATION

DDVll . B BACKPLANE MODULE INSERTION SIDE

NOTE

MEMORY CAN BE INSTALLED IN ANY SLOT; IT IS NOT

PRIORITY DEPENDENT AND DOES NOT NEED TO BE

ADJACENT TO THE PROCESSOR.

CONTROLLERS ARE ALSO COMPA TlBLE WITH H9273A

MODULES.

E

/MODUL

E

F

I

USER DEFINED

SLOTS

/

2

3

4

5

6

7

8

9

Figure 2-2. Typical Backplane Configuration

3. If the formatter is equipped with a IOO-pin connector, adapter part number ACC993A must be used to convert the IOO-pin connector to two 50-pin connectors. Adapter part number ACC993B is used for 72-pin connectors.

4.

Ins~r~ the coupler into the selected backplane posItIon. Be sure the coupler is installed with the components facing row one, the processor.

The coupler module is equipped with handles on the side opposite the slot connectors. Gently position the module slot connectors into the backplane then press until the module connectors are firmly seated into the backplane. Both handles must be pressed simultaneously. When removing the module, apply equal pulling pressure to both handles.

5.

Feed the module connector end of the tape drive cable(s) into the coupler module connector(s). Install the cable connector(s) into the module connector(s}. Verify that the connector(s) are fll'mly seated.

6. Connect the drive end of the I/O cables to the drive

110 connectors.

2·3

2-4

7. Apply power to the computer and verify that the green diagnostic LED indicator on the coupler board is lighted. If the DIAG LED is not lighted. either power is not applied to the coupler. the coupler board is bad. or the LED is bad.

8. Refer to the tape drive manual for operating instructions and apply power to the tape drive. Install a known good reel of tape on the tape drive and place the tape drive ON LINE.

9. Place the computer in the HALT mode to enable ODT. Using the computer terminal examine location 772 520. The contents of this location should be 000 141. These are the tape drive status bits signifying: ON LINE.

BEGINNING OF TAPE, and TAPE UNIT

READY.

10. Using the computer console device, deposit

60007 into location 772 522. The tape should move forward approximately 6 inches and stop. A file mark should have been written on the tape. Examine location 772 520. The contents of this location should be 040 101 signifying that a file mark has been written and detected.

11. Refer to the D ILOG software manual and run the diagnostics.

12. The tape system is now ready for data transfer operations.

SECTION 3

OPERATION

INTRODUCTION

Prior to operating the system, the instruction manual sections describing the controls and indicators on the tape drive and procedures for mounting and removing tape reels should be read. To prevent loss of data or damage to the magnetic tape, the following precautions should be observed: a. Always handle a tape reel by the hub hole.

Squeezing the reel flanges can cause damage to the tape edges when winding or unwinding tape. b. N ever touch the portion of tape between the

BOT and EOT markers. Oils from fingers attract dust and dirt. Do not allow the end of the tape to drag on the floor. c. Never use a contaminated reel of tape. This spreads dirt to clean tape reels and can affect tape drive operation. d. Always store tape reels inside their containers. Keep empty containers closed so dust and dirt cannot get inside. e. Inspect tapes, reels, and containers for dust and dirt. Replace take-up reels that are old or damaged. f. Do not smoke near the tape drive or tape storage area. Tobacco smoke and ash are especially damaging to tape. g. Do not place the tape drive near a line printer or other device that produces paper dust. h. Clean the tape path frequently.

Note that tape drives permit off-line or on-line operation. The off-line mode is controlled by switches on the tape drive. The on-line mode is controlled by programmed commands from the computer via the coupler and formatter. When system operation is desired, be sure the tape drive ON-

LINE indicator is lit. On-line operation is a function of program commands described in Section 4 of this manual.

TAPE FORMAT

For detailed information on tape format characteristics see formattter and tape drive manuals.

BOOTING FROM MAGNETIC TAPES

1. Place the tape transport "ON LINE" and position the tape at "Beginning of Tape."

2. Load Register location 772 5228 with 10000

8

,

3. Load Register location 772 5248 with 1777778

(-1).

4. Load Register location 772 5228 with 600118,

The tape will jump forward and halt.

5. Load Register location 772 522

R with 600038,

The tape will jump forward and halt.

6. Load PSW ($S) with 350

8

,

7. Load PC (R7) with

O.

8. Type

"P" to start.

STREAMING TAPE TRANSPORTS

With the STREAMING switch on, the tape drive will function in the low-speed STOP/START mode when addressed as logical unit number 0, when addressed as logical unit number 4, the streamer will function in the high-speed, streaming mode.

3-1

/

SECTION 4

PROGRAMMING

PROGRAMMING DEFINITIONS

FUNCTION:

The expected activity of the tape system (read. write. rewind).

COMMAND:

The instruction which initiates a function.

INSTRUCTION:

One or more orders executed in a prescribed sequence that cause a function to be performed.

ADDRESS:

The binary code placed on the

BDALO-BDAL21 lines by the bus master to select a register in a slave device. Note that "register" can be either discrete elements (flip flops) or memory elements (core. solid state RAM or ROM). When addressing devices other than computer internal memory. i.e .• peripheral device registers. the upper

8K bytes address space is used.

REGISTER:

An associated group of memory elements that react to a single address and store information (status. control. data) for use by other assemblies of the total computer system.

TAPE COUPLER FUNCTIONS AND

REGISTERS

The tape coupler performs eight functions. A function is initiated by a Go command after the processor has issued a series of instructions that store function-control information into coupler registers.

To accept a command. and perform a function. the coupler must be properly addressed and the tape drives must be powered up. at operational speed. and be ready.

All software interaction between the coupler. the processor. and processor memory is accomplished by seven registers in the tape coupler. These registers are assigned memory addresses and can be read or written into (except as noted) by instructions that reference respective register addresses. A summary of the registers, their addresses. mnemonics, and their bit assignments are shown in

Figure

4-1.

Table 4-1. Function Codes

BIT 3 BIT 2 BIT 1 BIT 0(80)

Octal

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

00

Off line

11

Read

05 Write

07 Write EOF

10 Space Forward

13 Space Reverse

15

Write with Extended

Interrecord Gap

17 Rewind

4-1

BIT POSITION

STATUS (MTS)

772520

COMMAND (MTC)

772522

BYTE RECORD COUNTER

(MTBRC)

772524

CURRENT MEMORY

(MTCMA)

772526

DATA BUFFER (MTD)

772530

TAPE READ LINES (MTRD)

772532

MSB

15 14 13 12 11 10 09 08 lSB

I

07

I

06

I

05

I

04 03 02 01 00

15 14 13 12 11

III

COM EOF

10 09

PRE BGl EOT RlE

08 07 06 05 04

NXM SELR BOT 7CH

03 02 01 00

ISONN

WRL RWS TUR

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

DEN DEN PWR

ERR 8 5 CLR PEVN US2 US1

INT XBA XBM

USO CUR ENB 17 16 FU2 FU1 FUO GO

15 00

BYTE COUNT

15 00

MEMORY ADDRESS

15 14

13 12 11 10 09 08

00

DATA BUFFER

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

TIM

Figure 4-1. Register Summary

STATUS REGISTER (MTS)

772520

The address of the MTS register is 772 520. MTS is a read-only register. The functions of the bits of this register are as follows:

BIT(S)

DESCRIPTION

00

01

02

03

TAPE UNIT READY (TUR): This bit is set when the tape unit is ready and is not rewinding. This bit is cleared when the processor sets the GO bit and the operation defined by the function bit occurs.

REWIND STATUS (RWS): This bit is set by the coupler as soon as it receives a Rewind command from the processor. It is cleared by the coupler as soon as the tape arrives at the BOT marker in the forward direction. (It overshoots BOT in the reverse direction.)

WRITE LOCK (WRL): This bit is set to prevent the control unit from writing information on tape.

It is controlled by the presence or absence of the write protect ring on the tape reel.

TAPE SETTLE DOWN (SDWN): This bit is set whenever the tape unit is slowing down. The coupler will accept and execute any new command during the SPWN period except when the new command is to the same tape unit as the one issuing SDWN, and if the direction implied in the new command is opposite to the present direction.

4-2

04

05

06

07

08

09

10

11

12

13

14

15

SEVEN CHANNEL (7CH): This bit is set to indicate a 7 -channel tape unit; cleared. it indicates a

9-channel unit.

BEG INNING OF TAPE (BOT): This bit is set when the BOT marker is read. and cleared when the BOT marker is not read. BOT at a 1 does not produce a 1 in the ERR bit.

SELECT REMOTE (SELR): This bit is cleared when the tape unit addressed does not exist. is offline. or has its power turned off.

NON-EXISTENT MEMORY (NXM): This bit is set during DMA operations when the control unit is bus master, and is performing data transfers into and out of the bus, when the control unit does not receive a slave Sync signal within 10 microseconds after it has issued a master Sync signal. The operations which occur when the error is detected are identical to those indicated for the BGL error.

BAD TAPE ERROR (BTE): NOT USED.

RECORD LENGTH ERROR (RLE): This bit is detected only during a Read operation. It occurs for long records only, and is indicated as soon as MTBRC increments beyond 0, at which time both data transfer into memory and incrementing of the MTCMA and MTBRC stop.

However, the control unit reads the entire record and sets the ERR bit when the LPC character is read. CU Ready remains at 0 until the LPC character is read.

END OF TAPE (EOT): This bit is set when the EOT marker is read while the tape is moving in the forward direction. The bit is cleared as soon as the same point is read while the tape is moving in the reverse direction. The ERR bit, as a result of the EOT bit at a 1, sets only in the tape forward directio!l and coincidentally with the reading of an LPC character.

BUS GRANT LATE (BGL): This bit is set when the control unit, after issuing a request for the bus, does not receive a bus grant before the coupler receives the bus request for the following tape character. The condition is tested only for NPR (Non-Processor Request) operations. The

ERR bit sets simultaneously with BGL, thus terminating the operation. If the BGL occurred during a Write or Write With Extended IRG operation, the control unit does not send the signal

WDS to the master, while the master writes the CRC character (if required) and LPC character onto the tape, terminating the record.

HARD ERROR (HE): This bit is set as the result of an error being detected on tape.

For all errors, the ERR bit sets at the end of the record. Both lateral and longitudinal parity errors are detected during Read, Write, Write EOF and Write With Extended IRG operations. The entire record is checked. including the CRC and LPC characters. During a Write operation a correctable error in the PE (1600 bpi) mode will set this bit.

NOT USED.

END OF FILE (EOF): This bit is set when an EOF character is detected during a Read, Space

Forward, or Space Reverse operation. During the Read or Space Forward operation, the EOF bit is set when the LPC (Longitudinal Parity Check) character following the EOF character is read.

During a Space Reverse operation, the EOF bit is set when the EOF character following its LPC character is read. The ERR bit sets when the LPC character strobe is generated with the File

Mark signal upon EOF detection.

ILLEGAL COMMAND (ILL COM): This bit is set by any of the following illegal commands:

1. Any DATO or DATB to the command register during the tape operation period.

2. A Write, Write EOF, or Write With Extended IRG operation when the File Protect bit is a 1.

3. A command to a tape unit whose Select Remote bit is O.

4. The Select Remote (SELR) bit becomes a 0 during an operation.

In error conditions 1 through 3, the command is loaded into the MTC, but the GO pulse to the tape unit is not generated. In addition, the eu

Ready bit remains set.

4·3

COMMAND (MTC)

772522

,

15 14 13 12 \ 11 10

09

't r

,

08 07

06 i

05

04

03

02 01

00

DEN DEN PWR INT XBA XBM

ERR

8 5 CLR PEVN US2 US1 USO CUR ENB 17

16

FU2 FU1 FUO GO

The address of MTC is 772 522. The functions of the bits of this register are as follows:

BIT(S)

FUNCTION

00

01-03

04-05

06

07

OS-09

10

11

12

13-14

15

GO: When set, this bit begins the operation defined by the function bits.

FUNCTION BITS: Selects I of S functions (programmable commands).

BIT 3 BIT 2 BIT 1

1

1

1 o o o o

I

0

0

1

1

0

0

I

1

1

0

1

0

I

0

1

0

Off-Line/Rewind

Read

Write

Write EOF

Space Forward

Space Reverse

Write With Extended Interrecord Gap

Rewind

ADDRESS BITS: These are extended memory bits for an IS-bit bus address. Bit 5 corresponds to

XBAI7, and bit 4 to XBAI6. They are an extension of the MTCMA, and increment during a tape operation if there is a carry-out of MTCMA.

INTERRUPT ENABLE (lNT ENB): When this bit is set, an interrupt occurs whenever either the

CU Ready bit or the ERR bit changes from 0 to 1, or whenever a tape unit that was set into rewind has arrived at the beginning of the tape. In addition, an interrupt occurs on an instruction that changes the INT ENB from 0 to I and does not set the GO bit, i.e., CU READY or ERROR

=

1.

CU READY (CUR): This bit is cleared at the start of a tape operation, and set at the end of a tape operation. The control unit accepts as legal, all commands it receives while the CU Ready bit is a

1.

UNIT SELECT 1: These bits specify one of the four possible magnetic tape units. All operations defined in the MTC and all status conditions defined in the MTS pertain to the unit indicated by these bits. They are cleared by INIT.

UNIT SELECT 2: This bit specifies one of two possible formatters. When the STREAM switch is

OFF (see Section 2), and the bit is 0, the formatter addressed is unit 0; if the bit is I, the formatter addressed is unit

1.

When the STREAM switch is ON and the bit is

0, the mode is START/STOP; if the bit is 1, the mode is STREAMING. If the switch is ON, the formatter addressed is always unit o.

LATERAL PARITY (PEVN): NOT USED. This bit is not applicable for 9-track tape.

POWER CLEAR (PWRCLR): This bit provides the means for the processor to clear the control unit and tape units without clearing any other device in the system. The PWR CLR bit is always read back by the processor as a o.

DENSITY (DEN S, DEN 5): NOT USED. These bits are not applicable for 9-track tape.

ERROR (ERR): This bit is set as a function of bits 7-15 of the Status Register MTS. It is cleared by INIT or the GO command to the tape unit.

4-4

BYTE RECORD COUNTER (MTBRC)

772524

15

00

The MTBRC is a 15-bit binary counter which is used to count bytes in a Read, Write, or Write With

Extended IRG operation, or records in a Space Forward or Space Reverse operation. When used in a

Write or Write With Extended IRG operation, the

MTBRC is initially set by the program to the 2's complement of the number of bytes to be written on tape. The MTBRC becomes 0 after the last byte of the record has been read from memory. Thus, when the next WDS (Write Data Strobe) signal occurs from the master, the control unit will not send the

WDR (Write Data Request) signal to the master, indicating that there are no more data characters in the record.

When the MTBRC is used in a Read operation, it is set to a number equal to or greater than the 2' s complement of the number of bytes to be loaded into memory. A Record Length Error (RLE) occurs for long records only, and is indicated when a read pulse

BYTE COUNT for data (RDS occurring when CRC's or LPC's do not occur) occurs when the MTBRC is o.

The

MTBRC increments by 1 immediately after each memory access.

When the MTBRC is used in a Space Forward or

Space Reverse operation, it is set to the 2' s complement of the number of records to be spaced. It is incremented by 1 at LPC time, whether the tape is moving in the forward or reverse direction. A new

GO pulse is sent to the tape unit during the SDWN time if the MTBRC is not 0 during that time. When the tape unit is moving in the reverse direction, the

LPC character is detected before SDWN, and before the entire record has been traversed. Thus, both

SDWN and the LPC character appear to be in different positions on the tape from the positions apparent when the tape unit is moving in a forward direction.

CURRENT MEMORY ADDRESS (MTCMA)

772526

00

[

15

MEMORY ADDRESS

The MTCMA contains 16 of the possible 18 memory address bits. It is used in DMA operations to provide the memory address for data transfers in

Read, Write, and Write With Extended IRG operations. Before issuing a command, the MTCMA is set to the memory address into which the first byte is loaded in a Read operation, or from which the first byte is read in a Write, or Write With Extended

IRG operation. The MTCMA is incremented by 2 immediately after each memory access. Thus, at any instant of time, the MTCMA points to the address that is next higher than the one which had been most recently accessed. When the entire record has been transferred, the MTCMA contains the address plus 2 of the last characters in the record. In the error conditions Bus Grant Late (BG L) and N on-

Existent Memory (NXM), the MTCMA contains the address of the location in which the failure occurred.

The MTCMA is available to the processor on a

DATI, except bit 0 which always reads as a zero under program control. Bit 0 can be asserted during

DMA to determine the selected byte. The bits are set or cleared on a processor DA TO. INIT clears all bits in the MTCMA.

4-5

DAT A BUFFER (MTD)

772530

15 14 13 12 11 10 09 08

The data buffer is an 8-bit register which is used during a Read, Write, or Write With Extended IRG operation. In a Read operation, the data buffer is a temporary storage register for characters that are read from tape before being stored in memory. In a processor read. all nine bits are stored in memory.

Bits 0 through 7 in memory correspond to channels

7 through 0, respectively, from tape, and bit 8 corresponds to the parity bit. In a DMA operation only the data bits are read into memory, and are alternately stored in the low and high bytes. In a Write or Write With Extended IRG operation, the data buffer is a temporary storage register for characters that are read from core memory before they are written on tape.

00

DATA BUFFER

In a Read operation, the LPC character enters the data buffer when bit 14 of MTRD is a 1, and is inhibited from doing so when bit 14 is a O. Thus, after reading a nine-channel tape, the data buffer contains the LPC character when bit 14 is a 1, and the CRC character when bit 14 is a O. After reading an EOF character, the data buffer contains all O's when bit 14 is a 1, and the LPC character when bit

14 is a O. The MTD is available to the processor on a

DATI. Bits 9 through 15 are read identically to bits

1 through 7, respectively. Bits 0 through 7 are set or cleared on a processor DATA. Bits 8 through 15 are not affected by a processor DATO. INIT clears all bits in the MTD.

TAPE READ LINES (MTRD)

772532

15 14 13 12 11

CRCI

NOT

TIM LPC USED GS

09

NOT USED

08 07 06 05 04 03 02 01 00

P CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7

The memory locations allocated for the tape read lines are:

BIT(S)

00-07

08

09-11

12

13

14

15

DEFINITION

Channels 7-0 respectively.

Parity Bit.

NOT USED.

Gap Shutdown Bit.

NOT USED.

CRC, LPC Character Selector.

Timer.

For correct longitudinal parity, bits 0-8 are 0 after writing a record or reading a record from tape. For a longitudinal parity error, one or more of the bits 0-8 remain 1 's, indicating the channel(s) containing the error, which sets the CU Ready bit. Thus, if the pulse is set during a tape operation, CU Ready sets prematurely, producing the gap shutdown period while characters are still being read. Bits 0-8 are set and cleared by the tape unit. Bit 14 is set and

4-6 cleared by the processor or cleared by INIT. Bit 15 is uniquely controlled by the 100-microsecond timer.

The MTRD is available to the processor on a DATO, except that bit 13 reads back as a O.

TIM (Timer) is a 10-kHz signal with a 50% duty cycle. The signal is used for diagnostic purposes in measuring the time duration of the tape operations.

The timer is read as bit 15 in the MTRD.

SECTION 5

TROUBLESHOOTING AND THEORY

This section describes troubleshooting procedures at three levels of complexity: basic System9 coupler symptoms and detailed analysis. Basic system troubleshooting procedures are visual checks not requiring test equipment and may be performed by the operator. Coupler symptom procedures may require a SCOpe9 meter, extender board or diagnostics and should be performed by a technician.

Detailed analysis is troubleshooting at the IC level, and is presented for engineers or system analysts for coupler evaluation. The latter method may require the use of test equipment and the material presented here: board layout, term listing, theory of operation and logic diagrams.

CAUTION

Any troubleshooting requires a familiarity with the installation and operation procedures in this manual, the appropriate DEC manual, and the tape drive manufacturer

'$

manuaL Ensure power is off when connecting or disconnecting the board or plugs.

BASIC SYSTEM TROUBLESHOOTING

The following should be checked before power is applied:

1. Verify that all signal and power cables are properly connected. Ribbon cable connectors are not keyed. The arrows on the connectors should be properly aligned.

2. Verify that all modules are properly seated in the computer and are properly oriented.

The following should be checked during or after application of power:

1. Verify that the computer and tape drive generate the proper responses when the system is powered up.

2. Verify that the computer panel switches are set correctly.

3. Verify that the console can be operated in the local mode. If not, the console may be defective.

4. Verify that the green diagnostic, the DMA, and activity lights on the coupler are active.

COUPLER SYMPTOMS

Coupler symptoms, possible causes and checksl corrective action are described in Table 5-1. Voltage checks should be performed before troubleshooting more complex problems. Check the logics for voltage sources.

PHYSICAL LAYOUT

The physical layout of the board is shown in Figure 5-1. Column and row numbers on the layout correspond to the numbers on each IC on the logic diagrams.

TERM LISTING

The input and output terms for each logic diagram are described in Table 5-2. The sources and destinations refer to the sheet numbers on the logic diagrams.

5-1

Table 5-1. Coupler Symptoms

TROUBLE

1. Green DIAGnostic light on coupler is OFF.

2. No communication between console and computer.

3. No data transfers to/from tape. BSY light never lights.

4.

Data transferred tolfrom tape incorrect. DMA and

BSY lights blink to indicate transfers.

POSSIBLE CAUSE

1. Microprocessor section of coupler inoperative.

---'~Crystal not properly seated in socket. b. Short or open on board. c. Bad integrated Circuit.

CHECKIAEPLACE

1. Coupler.

Put board on extender. With scope look at pins of 2901. All pins except power and ground should be switching. Look for "stuck high", or "stuck low", or half·amplitude pulses. If no switching, either power or crystal bad. d. No DC power.

2. 110 section of coupler "hanging up" a

Bus. a.

DEN always low. b. Shorted bus transceiver IC. c. Bad CPU board.

3. Tape not ready or bad cable connection. a. Improper communication with tape registers on coupler or bad IC in register section of coupler.

2. Computer interface logic of coupler.

3. a. Check signal DEN for constant assertion. b. Check 1/0 IC's. Remove coupler board to see if trouble goes away. c. Run CPU diagnostics.

Check tape switches and cable connector. a. load and read tape registers from console with processor halted, I.e., RKDS. RKDA.

RKER. Verify bits loaded can be read.

4. Bad memory board in backplane. 4.

Run memory diagnostics. a. Noise or intermittent source of DC power in computer. a. Check AC and DC power. b. While operating. check lines from coupler to tape with a 'scope for short or open. b. Bad IC in tape 110 section of coupler. c. Run tape diagnostic, set console to make system "Halt

On Error." d. Bad area on tape. c. Analyze error halt. e. Head worn. f. Configuration switch not set properly. d. Errors should always occur in same sector of tape. e. Replace head. f. Check configuration in Installation Section.

5-2

(J)

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5-3

Table 5-2. Term Listing

BIAKOl

BINIT

BIRQl

BOT

BRPFF

BRPlY

BRPLYl

BSACKl

BSTClK

BSY

BSYNCL

BUSDOOl

BUSD01l

BUSD02l

BUSD03l

BUSD04l

BUSD05l

BUSOO6L

BUSD07L

BUSOO8L

BUSD09l

BUSD10l

BUSD11L

BUSD12L

BUSD13L

BUSD14L

BUSD15L

BWTBT

BWTBTl

C

CER-

CLR

CLRB

CN+2

CR1-00

Term

BACTFF

- BBS7

BBS7L

BDIN

BDINl

BDMGll

BDMRl

BDOUT

BDOUTl

BIAKll

Souree

AOO

A01·A03

ACK

ACKFF

ADRA

ADRB

AOOFF

2

3

3

2

ASOO·AS02 2

2

2

2

Desgination Description

2

5

5. Bus (AP2)

5

5. Bus (AH2)

5. Bus (AR2)

5. Bus (AN1)

5

5. Bus (AE2)

5. Bus (AM2)

2. 7

2

2

2

2

2. 7

2

2

7

7

2

2

CR1·011

CR1-03

CR1-04

CR1-051

CR1·07

CR2-OO

CR2-01/

CR2-07

CR3·001

CR3·01

CR3-021

CR3-03

CR3-041

CR3-06

CR3-07

CR3·A01

CR4-OO/

CR4-07

5. Bus (AU2)

5. Bus (AT2)

5. Bus (Al2)

12

2

5

5. Bus (AF2)

5. Bus (BN1)

3

3

5. Bus (AJ2)

4. Bus (AU2)

4. Bus (AV2)

4. Bus (BE2)

4. Bus (BF2)

4. Bus (BH2)

4. Bus (BJ2)

4. Bus (BK2)

4. Bus (Bl2)

4. Bus (BM2)

4. Bus (BN2)

4. Bus (BP2)

4. Bus (BR2)

4. Bus (BS2)

4. Bus (BT2)

4. Bus (BU2)

4. Bus (BV2)

5

5. Bus (AK2)

9

12

2

3

8

10

J1 (4)

2

2

3. 7

3.9

2

8

J1 (42)

3

3. 11

8

3.8.10

10

10

10

10

10

10

10

10

10

3

10

3.8

8

8

3

8.10

3.8

3. 7

8

10

7

9

Bus Address Bit O. lSB

Bus Address Bits 1·3

Acknowledge

Acknowledge Flip·Flop

Address A

Address B

Address Bit 0 Flip·Flop

A State Sequencer Bits

0-2

Bus Activity Flip·Flop

Bank Seven Select

Bank Seven Select

Data In

Data In From Master

DMA Grant In

Bus DMA Request

Bus Data Output

Data Out From Master

Interrupt Acknowledge

Input

Interrupt Acknowledge

Output

Initialize

Interrupt Request

Beginning of Tape Mark

Bus Reply Flip·Flop

Bus Reply

Reply From Slave

Select Knowledge

Clock

Busy

Synchronize

Bus Bit 0

Bus Bit 1

Bus Bit 2

Bus Bit 3

Bus Bit 4

Bus Bit 5

Bus Bit 6

Bus Bit 7

Bus Bit 8

Bus Bit 9

Bus Bit 10

Bus Bit 11

Bus Bit 12

Bus Bit 13

Bus Bit 14

Bus Bit 15

Write Byte

Write Byte

2901 Carry

Corrected Error

Clear

Clear Bus

Carry Output of 2901

Control Register One

Output Bit 0

Control Register One

Output Bits 1·3

Control Register One

Output Bit 4

Control Register One

Output Bits 5-7

Control Register Two

Output Bit 0

Control Register Two

Output Bits 1·7

Control Register Three

Output Bits 0-1

ContrOl Register Three

Output Bits 2·3

Control Register Three

Output Bits 4-6

Control Register Three

Output Bit 7

Control and Address Bit 1

Control Register Four

Output Bits 0-7

Table 5-2. Term Listing (Continued.

Term

CR5-OOI

CR5-07

CS

CSA-OOI

Souree

10

8

9 10

CSA-08

000/007

DA

DA161DA17 3 o

BOO

4

D801/DB12 4

7.9. 10. 12 8

2 4. 7

5

2.3.6

2.6

DB08M 6

DB131DB15 4

DB15M

6

6

6

5. Bus (AC1)

6

DB16l

DB17l 5. Bus (AD1)

DBY

DEN

DEN-

DIN

DINFF

DMGI

DOUT

DOUTFF

DMG

DMGFF

12

2

13

2

2

IDENT

IDENT-

INIT lO

LDADO

LWD

MMBGOl

MRQA

MRQB

MRST

MTC

MTR

MTS

NS

NXM

OFC

ONl

PBSY

PClK

PIAClK

PlB01

PIB05

PIBClK

PICClK

ORQFlG

OWDS

11

12

OWDS

EDUF

EOT

ERAS

12

3

12

13

FAD

FBY

FEN

FlOO/FI15

FLClK

13

12

13

6

3

FL·D

3

FLPT

12

FMK-

12

FQ()().FOO7

7

FOO8·F015 7

FUClK

3

FU·O

FUNC

3

3

GO

IAKI

13

5

2

2

5

2

2

12

3

3

3

13

13

3

3

12

12

5

4

2

2

2

2

13

5. Bus (AS2)

3

3

2

8

3

13

9

9

9

J1 (36)

11

7

12

J2 (40)

J1 (48)

J2 (2)

J1 (18)

7

6

3

J1 (32)

J1 (14)

4. 7

4.6.7

6

3. 7

3

J2 (8)

2

9

J1 (16)

2

5

3.4

J2 (4)

2.9

2.3.9

3. 11

3.6. 11

2.6

2

9

12

J1 (24)

J1 (44)

6

3. 7

11. 13

11

3

13

13

2

2

2

2

2

2

J1 (38)

4.5

J1 (50)

2

Desgtna.lon Description

Control Register Five

Output Bits 0-7

Carry Signal Out of Second

2901

Control Store Address

Bits 0·8

2901 Data Bus Bits 0·7

Data Enable

Data Address Bits 16. 17

Data Bus Bit 0 From A Bus

Data Bus Bits 1·12 From A

Bus

Data Bus Bit 8 From A Bus

Data Bus Address Bits

13·15 From A Bus

Data Bus Bit 15 From A

Bus (MSB)

Data Bus Bit 16 (Address

ExtenSion)

Data Bus Bit 17 (Address

ExtenSion)

Data Busy

Device Enable

Device Enable

Data In

Data In Flip·Flop

Direct Memory Grant In

Data Out

Data Out Flip·Flop

Direct Memory Grant

Delayed

Direct Memory Grant Flip·

Flop

Data Request Flag

Demand Write Data

Demand Write Data

Enable Data File

End of Tape Mark

Erase

Formatter Address

Formatter Busy

Formatter Enable

File In Bits 0·15

File lower Byte Clock

File Lower Data

File Protect

File Mark

File Out Bits 0·7

File Out Bits 8·15

File Upper Byte Clock

File Upper Data

Function

Go

Interrupt Acknowledge

Input

Formatter 10 Burst

Formatter 10 Burst

Initialize

Load Memory Address load Address last Word

Bus Grant Output

Memory Request A

Memory Request B

Master Reset

Magnetic Tape Control

Magnetic Tape Request

Magnetic Tape Status

Sign of AlU MSB

Non Existent Memory

Off·Line Status From Tape

On·line Status From Tape

Peripheral Busy

Peripheral Clock

Peripheral In A Byte Clock

Peripheral In B

Peripheral In B

Peripheral In B Byte Clock

Peripheral In C Byte Clock

5-4

TDOOG

TDOUT

TEST

TlAK

TIMER

TIRO

TO

TOO

TROY

TRPLY

TSACK

TSACK-

TSYNC

TWTBT

WOO

WDl

WD2

WD3

WD4

WD5

WD6

WD7

WFM

RDS-

REV

RSTS

RSTS .-

RSYNC

RSYNC

RWC

RWS

STA

STORL

STORU

TA

TADO

TADl

TD07·

TD07

TD12·

TD12

TD13·

TD13

TD14·

TD15'

TD15

TDIN

TDMG

TDMR

Term

PIDCLK

POA·D

POB·D

POC·D

PPCLK

PPCLK

ROO

RDl

RD2

RD3

RD4

RD5

RD6

RD7

RDP

RDP-

RDP-

ROO

RDS

Table 5-2. Term Listing (Continued)

12

13

13

4

6

4

6

4

6

4

4

6

2

2

13

11

11

3

2

2

2

5

13

12

3

11

2

3

3

12

2

2

2

2

2

2

9

2

13

13

13

13

2

2

13

13

13

13

13

Soure.

3

12

12

12

12

12

12

12

12

12

3

2

3

3

3

12

12

11

12

Desgination Description

11

12

12

12

Peripheral In 0 Byte Clock

Peripheral Out A Byte Data

Peripheral OUt B Byte Data

Peripheral Out C Byte Data

2.3.7.11.12 Processor Clock

8.9.10

Jl (2)

Jl (3)

J2 (48)

J2 (SO)

Processor Clock

Read Data Bit 0 From Tape

Read Data Bit 1 From Tape

Read Data Bit 2 From Tape

Read Data Bit 3 From Tape

Read Data Bit 4 From Tape Jl (6)

Jl (20)

Jl (10)

Jl (8)

Read Data Bit 5 From Tape

Read Data Bit 6 From Tape

Read Data Bit 7 From Tape

Read Data Parity From

Jl (1)

Tape

Read Data Parity From

Tape

12

Read Data Parity From

Tape

9

Jl (34)

Request Data From Bus

Read Data Strobe From

Tape

11

3

3.11

3

Read Data Strobe From

Tape

J2 (18)

3.9

2. 3

2

Tape Reverse

Reset

Reset

Synchronize

2

Synchronize

-

J2 (20)

Rewind Command To Tape

J1 (30)

Rewinding

Status

Store Lower Byte

Store Upper Byte

Tag Clock For Extended

4

5

9

5

J2 (46)

Jl (46)

4.6

4

4.6

4

4.6

4

4

4. 6

4

5

5

5

6

2

3

2. 3

Jl (28)

5

2.3.5

2.5

3.5

2

J2 (10)

J2 (12)

J2 (30)

J2 (26)

J2 (6)

J2 (32)

J2 (28)

J2 (24)

J2 ("2)

Address Bits

Transport Address 0

Transport Address 1

Transmit Bit 07

Transmit Bit 07

Transmit Bit 12

Transmit Bit 12

Transmit Bit 13

Transmit Bit 13

Transmit Bit 14

Transmit Bit 15

Transmit Bit 15

Transmit 0 Bus In

Transmit Direct Memory

Grant

Transmit Direct Memory

Request

Transmit 0 Bus Bit 0 Gated

Transmit 0 Bus Out

Test 2901

Transmit Interrupt

Acknowledge

Tape Time Operations

Transmit Interrupt Request

Time Out

Time Out Delay

Tape Ready From Tape

Transmit Reply

Transmit Select

Acknowledge

Transmit Select

Acknowledge

Transmit Sync

Transmit Write Byte

Write Data Line 0 To Tape

Write Data Line 1 To Tape

Write Data Line 2 To Tape

Write Data Line 3 To Tape

Write Data Line 4 To Tape

Write Data Line 5 To Tape

Write Data Line 6 To Tape

Write Data Line 7 To Tape

Write File Mark

Table 5-2. Term Listing

Term

WRL

WRT

WRT-

WRU

WTBFF

YOON02

Y03IY05

Y06/Y07

ZS

Sourc.

8

8

3

13

13

3

2

8

8

Dngination Description

7

12

J2 (34)

7

2

Write Load

Write/Read Formatter

Write/Read Formatler

Write Unload

Write Byte Flip-Flop

3.6.7.9.13 Write Byte Flip·Flop Y Bus

Bits 0·2

3.6.9.13 Write Byte Flip·Flop Y Bus

6.9.13

Bits 3·5

Write Byte Flip·Flop Y

Bus

9

Bits 6·7

ALU Zero

THEORY

The coupler may be examined as three functions: computer interface, microprocessor and formatter interface. Signals from and to the computer are described in Section 1, Table I-I. Signals from and to the formatter are described in Tables

1-2 and 1-3.

Figure

5-2 is a simplified block diagram illustrating the interfaces and listing the major functional components. Single lines in the illustration represent serial data and the wide lines represent parallel data. A detailed block diagram of the coupler is shown on Sheet

1 of the logic diagrams. The numbers in the blocks on Sheet 1 refer to the sheet numbers of the other logic diagrams.

Computer Interface

The purpose of the computer interface is to

(1) buffer lines between the

Q

Bus of the computer and the coupler and

(2) synchronize information transfers. There are two major classes of lines connected to the computer interface: a. Data/address lines b. Control lines

There are 16 bidirectional data/address lines and six extended address lines. Both device addresses and data are transferred over these lines. Address information is first placed on the lines by a bus master. The bus master then either receives input data from, or outputs data to, the addressed slave device, or memory, over the same lines. During initial control and status-transfer sequences, the coupler is a slave device. During data transfers, the coupler is a bus master and either receives data from, or outputs data to, the processor memory via the DMA facility.

The control lines request information transfers, select the type and direction of transfers, and synchronize the transfers. The control lines are functionally unidirectional and originate either at the processor or at the coupler.

5-5

a:

.-

:::J a..

~ o u

.-

....

..

DA TAl ADDRESs.)

....

~

CONTROL

....

....

CONfROL

"

>

COMPUTER

INTERFACE

K

.....

....

• BUFFER I/O LINES

• BUS SEQUENCE

• ADDRESS DECODE

DATA

DATA

CONTROL

TIMING

~

/ '

~

MICROPROC~S~OR

K

.....

....

DATA

• TIMING SOURCE

• CONTROL CENTER

• ERROR CHECKING

• REGISTER STORAGE

• DATA BUFFERING

DATA

CONTROL

TIMING

~

~

. /

PERIPHERAL

INTERFACE

J"o.

WRITE DATA

~

....

<

READ DATA

_ CONTROL __

-oJ

<t a:

UJ

1:

0..

Ci

W

0.. o

~

STATUS

• BUFFER I/O LINES

• CLOCK SYNCRONIZATION

Figure 5-2. Tape Coupler Simplified Block Diagram

The computer interface controls the synchronization, or "bus arbitration" sequence. Bus synchronization is done by a separate hardware state processor, rather than by the microprocessor, to minimize bus use by the coupler. This permits many other devices to use the DMA channel efficiently on a time multiplexed basis with the tape coupler.

Data/Address Receivers-Both data and device addresses are time multiplexed on a 16 I/O bus line

(BDALOOL-BDALI5L). The tri-state receiverldriver circuits H8, H9, HIO, and HII. shown on Sheet 4, buffer these lines into the coupler. Once buffered, the received lines are identified as DBOO-DBI5 and routed to the bus arbitration sequence logic and the

RAM data file multiplexer in the microprocessor.

Control Receiver/Drivers-The control lines between the

1/0

bus and the coupler are buffered by circuits FII. F12, H12. and H13. shown on Sheet 5.

The receivers are always connected to the bus.

Setting circuit pins 7 and 9 low enables the tri-state drivers to the bus. Two of the circuits are permanently enabled; circuit HI2 is enabled by Transmit

Select Acknowledge (TSACK), and circuit HI3 is enabled by Device Enable (DEN) and TSACK.

Data/Address Drivers-The tn-state drivers in circuits H8. H9, HIO. and HII are enabled by

Device Enable (DEN) to gate addresses and data to the I/O bus. Addresses and data to the

1/0

bus are temporarily stored by register circuits E9 and F9.

Information from the FQ Bus is clocked into the registers either by a Data (DA) signal or by a Load

Address (LDADD) signal. The least significant bit

(DOO) is gated with control term TDOOG to the line drivers.

Bus and Arbitration Sequence (State Processor)-

To ensure the fastest response time. the synchronization of 110 bus transfers is done by hard-wired state logic, illustrated on Sheets 2 and 3. Informa-

5-6 tion transfers are of two kinds; programmed

110 and

Direct Memory Access (DMA). During DMA transfers, the coupler is bus master. Distinguishing between the two· transfer types is the function of the arbitration logic.

The bus sequence logic synchronizes masterlslave transfers over the 110 bus.

Transfers between the

110 bus and the coupler are of two types: a. Register transfers via programmed I/O. b. Data transfers via DMA.

During programmed 110 transfers, the seven coupler registers are accessed; initialization information is transferred to the registers; status information is accessed from the registers. The registers are located in the microdata file. Address information from the processor is decoded by circuits D4 and D5. Circuit D4 decodes the 772 52X portion of the address word. Circuit D5 buffers the four least significant bits, which become AOO-A03.

The bus and sequence arbitration logic primarily comprises PROM's, used as decoders, and flip flops that temporarily store control information. For example, the storage elements for the DMA light, the Busy light, and the Diagnostic light are contained in this logic. Monostable multivibrators F2-5 and F2-13 monitor bus activity to ensure that respoD:s~s to the bus master occur within 10 microseconds. Circuits YI and E I establish the crystalcontrolled time base for the coupler. The 10 mega-

Hertz output of E I is divided by two to generate

200 nanosecond clock PCLK, buffered to become

PPCLK, PPCLK. and CLK-.

Bus Transfer Timing-The two major types of transfers are divided into the following

1/0

operations and an interrupt sequence:

• Data Input Transfer (DAT!) slave

• Data Output Transfer (DATO) slave

• Data Input Transfer (DA Tl) DMA

• Data Output Transfer (DA TO) DMA

• Interrupt Requests

Programmed

110 transfers are initiated with the coupler when the computer places the device address of the coupler on the BDAL04 through

BDAL15lines, sets the BBS7L signal at a low level, and switches signal BSYNCL low. Within the coupler, BSYNCL converts to RSYNC.

Address decoder D4 monitors the address lines.

When the coupler address is decoded and RSYNC is asserted, the Bus Active bit (BACTFF) sets. This sets in motion the transfer sequence.

The sequence for a DATI operation is shown in

Figure 5-3. For a DATI sequence, the state processor steps through states 1, 2" and 7 (see Microprocessor in this section). The coupler responds to input requests by asserting TRPLY within 10 microseconds of a DATI request. DATI operations read status from the coupler.

The sequence for a DATO operation is shown in

Figure 5-4. DATO operations transfer commands to the coupler registers. A DATO is similar to a DATI.

The principle difference is that during a DATO, the

200NS

~ ~

BSTClK

__

~

2

~~

7

RSYNC--'

BACTFF

_.---J

TRPlY ----

OEN------------------------

ClK

OA------

______

~r__l

Figure

5-3.

DATI-Slave, Q Bus Transfers

200NS

~ ~

__

~

2

~

____

RSYNC----....

OOUTFF---------------

~------------------

____________________ _

TRPlY----------------------~

Figure 5-4. DATO-Slave, Q Bus Transfers

5-7

Data Out FF rather than the Data In FF is set, and the Data Available (DA) signal is not generated.

DMA transfers are between the coupler and computer memory. The coupler is always bus master.

There are two transfer types: data in to memory

(DATI) and data out of memory (DATO). Once the coupler has been granted DMA bus control, the transfer sequence is similar to 110 bus transfers.

Figure 5-5 illustrates the DMA DATI timing; Figure 5-6 illustrates the DMA DATO timing.

" Interrupt request timing is illustrated by Figure

5-7. Interrupt requests are originated by Memory

Request A (MRQA), a function of bit YOO and the

FUNe signal. The interrupt vector address is 224

8

Microprocessor

The microprocessor is the timing and control center of the coupler. The microprocessor is controlled by instructions stored in Programmable

Read Only Memory (PROM). These instructions, called firmware, cause the microprocessor to operate in a prescribed manner during each of the computerselected functions. The functions are established by a series of instructions issued by the computer. The instruction operands are stored in registers within the microprocessor.

When a Go command is issued by the computer, the firmware microinstructions cause the registers

200NS l ~

ClK

STATES-------------o--------------------~I

_1 _______

MROB

----.J

TOMR

-----.J

OMGI----'

OMGFF---------r--l~--------­

OMG----------~r--l~---------

TSACK

----------~

~

________________

o~

BRPFF----------------------------~

lOAOO-----------------~r--l~-----------------------------------------------

DEN - - - - - - - - - - - - - - - - - - .

TSYNC----------------------~

5-8

DIN - - - - - - - - - - - - - - - - - - - -

TOIN ----------------------'

ClR--------------------------------------------------~r--l~---------------------

Figure 5-5. DATI-Q Bua DMA Timing

ClK

STATES ______

____

~1~1_L1~2~LI ~3~

MROB

--.J

TDMR

--.J

DMGI-----~L---------------------------------------------­

DMGFF--------~r--l~------

DMG----------~r--l~-------------------

TSACK

~5~~ 6~

BRPFF--------------------------------~

lDADD--------------~~~------

-------------

DEN

~ nNTBT------------------~

DA--------------------~r--l~--------------------------

TSYNC - - - - - - - - - - -

~

DOUT--------------

TDOUT --_.. -------------------------'

ClR------------------------------------~~

Figure 5-6. DA TO-Q Bus DMA Timing to be examined, and either a data transfer sequence or a rewind sequence to be performed.

The microprocessor contains an eight-word Random Access Memory (RAM) dedicated to buffering data between the

Q

Bus and the microprocessor.

This allows several DMA cycle requests to be missed without missing data words being transferred between the tape and computer memory.

The rate and order (format) at which data is transferred to the tape is controlled by the microprocessor. Within the microprocessor, data is handled in 8-bit parallel bytes. Error check bits are calculated (LRCC, CRCC) and supplied to the tape during a write function. During a read function, the microprocessor monitors the error check bits and the data being read. Discrepancies are flagged as errors to the computer. The microprocessor detects other types of errors during the transfer functions (data late, programming error, etc.) and monitors status lines from the tape for malfunctions within this assembly. All errors are assembled into a status word for access by the processor.

The microprocessor comprises the following major elements: a. Microdata File b. Microdata File Address Register

5-9

ClK

STATES

MROA--.J

TIRO

ACKFF

DA

DEN

0

4

I

5 n

6

0

TRPlY----------------------------~

ClR--------------------------------,~

Figure 5-7. Interrupt Sequence Timing c. Microdata File Multiplexer d. 2901A Array and Status Register e. Control Memory and Register f. Control Store Address Programmer and Test

Multiplexer g. D Bus Multiplexer

The preceding elements are interconnected to perform the control, timing, error checking, and data manipulation functions of the coupler. Information is transferred among the elements over internal buses defined in Table 5-3.

To understand the function of a microprocessor, please refer to

The Microprogramming Handbook

from Advanced Micro Devices, Inc. Detailed technical descriptions of the 2901A four-bit bipolar microprocessor slice and of the 2901 microprogram coupler are given in the Advanced Micro Devices

AM2900 Family Data Book. These two elements are the major components of the coupler.

Microdata File-This 16 word, 16-bit-per-word, data file has two functions: a. Storage for the seven coupler registers in locations 10

5-4.

16 through 1All shown in Table b. Buffer storage for data words being transferred via DMA between memory and disc

(locations 0 through 7).

5-10

Table 5-3. Coupler Buses

The following prefixes are used as bus identifiers in the logic diagrams and the tables in Section 1.

Designltion

Function

B

DB

0

P

T y

Fa lSI·11 1/0 bus: Data. Address and

Control lines. bidirectional.

Data bus from 1/0 bus receivers into coupler.

Input Data bus to 2901A.

Peripheral Bus: Data and Control signals.

Transmit data or control signals from coupler to lSI·11 110 bus.

Output data bus from 2901A array.

Output of 16 x 16 Microdata file.

Table 5-4. Coupler Register Storage

Aegilter

MTS

MTC

MTBRC

MTCMA

MTD

MTRD

File Locltion (HEX)

10

12

14

16

18

1A

Sheet 7 shows the data file. Inputs to the data file are from the data file multiplexer on lines FIOO-

FIlS. Outputs from the data file are on lines FOOO-

F015 to the microdata bus. Data file locations are accessed by the address file and by the DS2 portion of the control register word. Note that the data file is separated into 8-bit bytes and that the upper byte

(FX08-FX15), the lower byte (FXOO-FX07), or both bytes can be written into or read from.

lvficrodata File Addressing-The microdata file address logic is shown on Sheet 7. Two sources address the data file: a. The bus and arbitration sequence logic (circuit E5). b. The 4 x 4 address file (circuit F5).

Address control from the bus and arbitration sequence logic 'is address lines A01-A03, which select specific coupler registers.

The 4 x 4 address file can store up to four addresses. The source of address information to the address file is bit 03 of field three of the control register word (CR3-03), and bits 00, 01, and 03 of the

Y Bus. Information can be read from and written into different locations of the address file simultaneously. When addresses are being buffered through circuit E5, circuit F5 is inhibited from supplying addresses. Write and read addresses to the address file are from field three of the control register word directly, and indirectly, via PROM E3

(Sheet 3).

Microdata File Multiplexer-The microdata file multiplexer, shown on Sheet 6, switches the input to the microdata file between two sources; the contents of the Y Bus, and the contents of the Data Bus (DB).

The contents of field three of the control register word control the selection. Note that data bus bits 8 and 15 to the multiplexer can be selected by circuits

EI0 and Ell to be either DB8 and 15 or file output bits 8 and 15 restored in the file.

2901A Array and Status Register-The 2901A array is shown on Sheet 8. The status register is shown on Sheet 9 (circuit C12). The 2901A array comprises two AM2901A four-bit, bipolar microprocessor slice integrated circuits connected in cascade to perform data manipulation on 8-bit bytes. The major sections of the AM2901A are shown within dashed lines on the block diagram. A

CR1 CR2 description of the operation of this device is given in the

AM2900 FC!-,mily Data Book.

The D Bus supplies external data to the 2901A.

Data from the 2901A is on the Y Bus. Control inputs to the 2901A are shown in Table 5-5.

The status register is updated on a coupler dock with the AL U status. The register stores the conditions shown in Table 5-6.

Table

5-5. Control Inputs To 2901A

Signal

Mnemonic Source

A0-3

Definition

Control

Address inputs; selects the A file

Register register contents to be con. nected to the 2901A, A Bus. (51)

B0-3

10-8

Control Address inputs; selects the A file

Register register contents to be connected to the 2901 At B Bus. (52)

Control Instruction control lines; lines 0·2

Register select the data sources to be applied to the ALU; lines

6-8 determine the routing of the output of the ALU within the

ALU. and the source of data supplied to the Y (output) Bus.

CN

CP

Control Carry input of ALU. Used during

Register arithmetic operations.

Crystal

Oscillator

200 nanosecond clock to 2901A.

Table

5-6. Status Register Bits

Mnemonic Definition

Cs

Ns

Vs

Indicates a "carry out" of ALU

The most significant ALU bit (sign of result).

Overflow has occurred.

Control Memory and Register-The control memory stores the firmware that controls the operation of the coupler. It comprises six 512 x 8 bit Programmable Read-Only Memories (PROMs) identified as D9, DlO, D1l, D12, F13, and F14, on Sheet

10. The PROMs have a pipeline register at the output identified as the Control Register (CR). The six

PROMs produce a 48-bit instruction word divided into six 8-bit fields. Figure 5-8 depicts the instruction word.

LITERAL

51

051

52

ALU5 ALU CIN OS2

ADR

Figure

5-8. Microinstruction Word

BRANCH

5-11

The contents of the control memory are accessed by the Control Store Address Processor and strobed into the control register by the PPCLK clock. The contents of the control register (CRI-00-o7 through

CR5-o0-o7 and literal DOO-D07) are routed throughout the logic of the coupler.

Control Store Address Programmer-The

Control

Store Address Programmer (CSAP) is an AM2910 microprogram control circuit and is described in the

AM2900 Family Data Book.

It controls the sequence of execution of microinstructions stored in the control memory. The CSAP is shown on Sheet 9

(circuit DEI4).

Control Store output address lines CSAOO through CSAOS select one of 512 locations in control memory. Inputs to the CSAP are primarily from fields four and five of the Control register and the

TEST output of Test Conditions Multiplexer C13

(shown on Sheet 9). Bits 00 through 07 (LSB) of field five (CR5) supply branch addresses to the CSAP.

Bits 00 through 03 of field four (CR4) supply instruction codes to the CSAP. Anyone of 16 instructions can be selected. The instructions can be modified by the state of the TEST input. The instructions select the next source of addresses to the control memory. The primary sources of addresses are as follows: a. A program counter/register within the CSAP. b. A five-word stack within the CSAP. c. Branch addresses directly from bits 00-07 of field five (CR5).

Note that bits 04 through 06 of field four (CR4) control Test Condition Multiplexer C13. This multiplexer connects one of seven selected conditions to the TEST line when specified by the current microinstruction being executed. The conditions tested for are shown in Table 5-7.

Table 5-7. Address Modification Conditions

Mnemonic Condition

C

Z

C

N

V

INIT

No carry from 2901 A ALU.

ALU result is zero.

Carry from ALU.

ALU sign bit is logical true.

ALU has overflowed.

Initiate

Note that bus signal BDCOKH, if ever low, disables the output of the GSAP and generates a

RESET (RST) signal.

5-12

D Bus Multiple%er-The

D-bus multiplexer, shown on Sheets 7, 9, and 12, is the information source to the 2901A array processor. The multiplexer comprises circuits DS (Sheet 9), ES and FS

(Sheet 7), and B9 (Sheet 12). Circuits B7, BS, and B9 also function as storage registers. One additional information source for the D Bus is PROM D9, shown on Sheet lOt which supplies the Literal (LIT).

Field one CRI-00-o3 and CR2-00 via circuit E12

(Sheet 3) gate the selected source to the D Bus.

Information sources to the D Bus are shown in

Table 5-S.

Table 5-8. Information Sources to D Bus

Circuit

Sh . . Source

D9

E8.F8

08

87

88. 89

10

7

9

12

12

Literal from control memory

RAM File data bus upper and lower bytes

Coupler status

Data from tape

Tape status

Peripheral Interface

The purpose of the peripheral interface is to match the characteristics of the tape formatter to the characteristics of the microprocessor. The peripheral interface: a. Contains line drivers and receivers that buffer the information lines between the coupler and the tape drives over cable lengths up to 25 feet. h. Contains the PROM and jumpers that permit configuring the coupler to match the different tape subsystem configurations.

There are two registers which temporarily store information being transferred between the tape and the other elements of the coupler; an input register and an output register. The input register is shown on Sheet 12, and the output register on Sheet 13.

The input register stores status information and data received from the tape and comprises circuits

B7, BS, and B9. The outputs of these circuits are gated to the

D

Bus. The tape status information originates at the line receivers and is stored in circuit B9; the data from the tape is stored in circuit

B7.

The output register stOres information to be sent to the tape and comprises circuits AS, A9, and AIO on Sheet 13. These circuits make up a 32-bit register that receives information from the Y Bus in S-bit segments. V-bus information is stored in the, register under control of the PIA, PIB, PIC, and

PID clocks. The outputs of the register are routed to the tape formatter.

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