30009-1_DQ215_SMD_RK06_RK07_Controller_Mar84.pdf

30009-1_DQ215_SMD_RK06_RK07_Controller_Mar84.pdf

MODEL DQ215

DISC CONTROLLER

INSTRUCTION MANUAL

DISTRIBUTED·

LOCi II:

[ORP.

MODEL

DQ215

DISC CONTROLLER

INSTRUCTION MANUAL

March 1984

I

mil

DISTRIBUTED LOGIC CORPORATION

~~6~ ~~;~n2~gir

Street

Anaheim. California 92806

Telephone: (714) 937·5700

Telex: 6836051

Part Number 30009·1

Copyright © 1984 by

Distributed Logic Corporation

Printed in the United States of America

TABLE OF CONTENTS

Section

1

Page

DESCRIPTION ....................................... ; ......................... 1-1

INTRODUCTION .............................. ' ................................ 1-1

CONTROLLER CHARACTERISTICS ............................................ 1-1

LSI-II Q-BUS INTERFACE ..................................................... 1-2

INTERRUPT .................................................................. 1-3

DISC INTERFACE ............................................................ 1-3

OPERATING SYSTEM COMPATIBILITY ........................................ 1-3

CONTROLLER SPECIFICATIONS .............................................. 1-4

2

3

INSTALLATION .................................................... , ........... 2-1

INSPECTION ................................................................. 2-1

PRE-INSTALLATION CHECKS ................................................. 2-3

INSTALLATION .............................................................. 2-3

GROUNDING ................................................................. 2-4

OPERATION ............................................. '" .................... 3-1

INTRODUCTION .............................................................. 3·1

PRECAUTIONS AND PREOPERATIONAL CHECKS .............................. 3·1

BOOTSTRAP PROCEDURE .................................................... 3-1

FORMAT AND DIAGNOSTIC TEST PROGRAM ................................... 3-2

Description ..................................................................

3-2

Partitioning Program ..........................................................

3-7

Diagnostic Test Program ...................................................... 3-12

EPROM FORMAT PROGRAM ................................................. 3-12

4 PROGRAMMING ............................................................... 4-1

PROGRAMMING DEFINITIONS ................................................ 4-1

DISC CONTROLLER FUNCTIONS .... ',' ......................................... 4-1

Select Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Pack Acknowledge .............. ' .............................................. 4-1

Drive Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1

Recalibrate .................................................................. 4-1

Offset ............................................. ' ......................... 4-1

Seek ........................................................................ 4-1

Read Data ................................................................... 4-2

Write Data ............... ' ................................................... 4-2

Read Headers ................................................................ 4-2

Write Headers ................................................................ 4-2

Write Check ................................................................. 4-2

Mapping and Map Override ..................................................... 4-2

ENABLE REAL TIME CLOCK CONTROL ........................................ 4-3

REGISTERS .................................................................. 4-3

Control and Status Register 1 ................................................... 4-5

Word Count Register .......................................................... 4-6

Bus Address Register .......................................................... 4-7

Disc Address (Track and Sector) Register .......................................... 4-7

Control and Status Register 2 ................................................... 4-8 iii

TABLE OF CONTENTS (Continued)

Section

5

Page

Drive Status Register .......................................................... 4-9

Error Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Attention Summary and Offset Register ......................................... 4-11

Desired Cylinder Address Register ....................................... ' ....... 4-12

Extended Memory Address Register (22-Bit) ...................................... 4-12

ReadIWrite Buffer Register .................................................... 4-13

Maintenance Register 1 ...................................... , ................ 4-13

ECC Position Register ........................................................ 4-13

ECC Pattern Register ........................................................ 4-14

Maintenance Register 2 ....................................................... 4-14

Maintenance Register 3 ...................................... ; .. , ............. 4-14

Enable Real Time Clock Control Register ......................................... 4-14

TROUBLESHOOTING AND THEORY ............................................. 5-1

BASIC SYSTEM TROUBLESHOOTING .......................................... 5-1

CONTROLLER SYMPTOMS .................................................... 5-1

PHYSICAL LAYOUT .......................................................... 5-1

TERM LISTING ............................................................... 5-1

THEORY ................................................................ " .... 5-5

Computer Interface ......................................... ' ... ; .............. 5-5

Disc Interface . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Controller Internal Functions . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Data Buffer ..................... , ............................................. 5-7

ERROR CORRECTION CODE (ECC) LOGIC ....................................... 5-7

FunctionalOperation .......................................................... 5-7

Component Description ........................................................ 5-7

+12 VOLT TO -5 VOLT POWER SUPPLY ........................................ 5-9

LOGICS iv

ILLUSTRATIONS

1-1

2-1

2-2

3-1

3-2(A)

2-3(B)

4-1

5-1

5-2

5-3

Figure Page

Disc Controller System Simplified Diagram ........................................... I-I

Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 2-1

Typical Backplane Configuration .................................................... 2-4

Partitions ....................................................................... 3-2

Universal Firmware-Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Universal Format-Change Parameters .............................................. 3-9

Controller Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Simplified Block Diagram .......................................................... 5-6

Data Paths ...................................................................... 5-8

TABLES

Table

I-I

1-2

1-3

2-1

2-2

3-1

4-1

5-1

5-2

Page

Controller/Q-Bus Interface Lines .................................................... 1-2

Controller To Drive

1/0

Interface-" A" Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Controller To Drive 110 Interface-"B" Cable ......................................... 1-3

Configuration Switches ............................................................ 2-2

Jumper Installation .............................................................. 2-2

Values for Partitioning with Universal Firmware (DQ215) ............................... 3-3

Function Codes .................................................................. 4-1

Controller Symptoms ............................................................. 5-2

Term Listing .......... ',' ....................... ' ................................. 5-4 v

SECTION 1

DESCRIPTION

INTRODUCTION

This manual describes the installation, operation, programming, troubleshooting, and theory of operation of Distributed Logic Corporation (DILOG)

Model DQ2I5 Disc Controller. The controller interfaces DEC* LSI-II based computer systems to one or two SMD

110 disc drives, including 8- and I4-inch

Winchester, SMD pack and CMD cartridge type drives. The complete controller occupies one quad module in the backplane. Full sector buffering in the controller matches the transfer rate of the disc drive and the CPU. The controller is compatible with

RK06/RK07 software drivers in RT-II, RSX-II and

RSTS.

CONTROLLER CHARACTERISTICS

The disc controller links the LSI-II computer to one or two disc storage units. Commands from the computer are received and interpreted by the controller and translated into a form compatible with the disc units. Buffering and signal timing for data transfers between the computer and the discs are performed by the controller.

A microprocessor is the sequence and timing center of the controller. The control information is stored as firmware instructions in read-onlymemory (ROM) on the controller board. One section of the ROM contains a diagnostic program that tests the functional operation of the controller. This self-test is performed automatically each time power is applied. A green diagnostic indicator on the controller board lights if self-test passes.

Data transfers are directly to and from the computer memory using the DMA facility of the LSI-II

I/O bus. In addition, the controller monitors the status of the disc units and the data being transferred and presents this information to the computer upon request. An error correction code with a

56-bit checkword corrects error bursts up to 11 bits.

To compensate for media errors, bad sectors are skipped and alternates assigned, and there is an automatic retry feature for read errors. The controller is capable of addressing four megabytes and controlling up to two disc drives in various configurations up to a total on-line formatted capacity of

220.32 megabytes. Figure 1-1 is a simplified diagram of a disc system.

*DEC. RSX and RSTS are registered trademarks of Digital

Equipment Corporation.

LSI-11

Q

BUS

CONTROL (14)

CONTROL

(15)

DATA

(16)1

ADDRESS (22)

COMPUTER

INTERFACE

CONTROL

(8)

POWER GROUND

Figure 1·1. Disc Controller System Simplified Diagram

1·1

LSI-II Q BUS INTERFACE

Commands, data and status transfers between the controller and the computer are executed via the parallel 110 bus (Q bus) of the computer. Data transfers are direct to memory via the DMA facility of the Q bus; commands and status are under programmed

1/0.

Controller/Q bus interface lines are listed in Table I-I.

Bus Pin

AC2, AJ1, AM1, AT1, BJ1,

BM1, BT1, BC2, CC2, CJ1,

CM1, cn,

DC2, DJ1, DM1,

DT1

AN1

Table I-I. Controller/Q-Bus Interface Lines

Mnemonic

GND

Controller

Inputl

Output

0

Description

Signal Ground and DC return.

BDMR L

AP1

AR1

BA1

BB1

BN1

BR1

AA2,BA2, BV1,CA2, DA2

AD2, BD2

AE2

AF2

AH2

AJ2

AK2

BHALT L

BREF L

BDCOK H

BPOK H

BSACK L

BEVNT L

+5

+12

BDOUT L

BRPLY L

BDIN L

BSYNC L

BWTBT L

AA1, AB1, AL2, BP1

AM2

AN2

CM2

CN2

AT2

BIRQ4L,5,6,7

BIAK11 L

BIAK10 L

BIAK21 L

BIAK20 L

BINIT L

AU2, AV2, BE2, BF2, BH2, BDALO L

BH2, BK2, BL2, BM2, BN2, through

BP2, BR~ BS~ BT~ BU~

BV2

BDAL15 L

AR2

AS2

CR2

CS2

AP2

BDMG11 L

BDMG10 L

BDMG21 L

BDMG20 L

BBS7 L

AC1, AD1, BC1, BD1, BE1,

BF1

BDAL 16 L

·BDAL 21 L

I

0

I

I

0

I

0

I

0

I

0

I

N/A

110

0 Direct Memory Access (DMA) request from controller: active low.

N/A Stops program execution. Refresh and DMA is enabled.

Console operation is enabled.

N/A

I

Memory Refresh.

DC power ok. All DC voltages are normal.

N/A

0

Primary power ok. When low activates power fail trap sequence.

Select Acknowledge. Interlocked with 'BDMGO indicating controller is bus master in a DMA sequence.

External Event Interrupt Request. Real Time Clock Control.

+ 5 volt system power.

110

110

+ 12 volt system power.

Data Out. Valid data from bus master is on the bus. Interlocked with BRPLY.

Reply from slave to BDOUT or BDIN and during IAK.

Data Input. Input transfer to master (states master is ready for data). Interlocked with BRPLY.

110

110

Synchronize: becomes active when master places address on bus; stays active during transfer.

Write Byte: indicates output sequence to follow (DATO or

DATOB) or marks byte address time during a DATOB.

Interrupt Request.

Serial Interrupt Acknowledge input and output lines routed from

Q·Bus, through devices, and back to processor to establish and interrupt priority chain.

Initialize. Clears devices on 110 bus.

110

0

Data/address lines, 0·15

DMA Grant Input and Output. Serial DMA priority line from comp~ter, through devices and back to computer.

Bank 7 Select. Asserted by bus master when address in upper

4K bank is placed on the bus.

Extended Address Bits 16·21

1-2

INTERRUPT

The interrupt vector address i~t factory set to address 210 (alternate 254). The vector address is programmed in a PROM on the controller, allowing user selection.

Interrupt requests are generated under the following conditions:

1. When the Controller Ready bit is set upon completion of a command.

2. When any drive sets an associated Attention

Flag in the Attention Register and the Controller Ready bit is se,t.

3. When the controller or any drive indicates the presence of an error by setting the combined

Error/Reset bit in the Control and Status

Register.

4. When the Controller Ready bit is set by conventional initialization upon completion of a controller command or when an error condition is detected. For test purposes, a forced interrupt may be generated by the Controller

Ready and Interrupt Enable bits.

DISC INTERFACE

The controller interfaces one or two disc drives through So- and 2S-pin cables. If two drives are used, the SO-pin control cable ("A" cable) is daisy chained to drive 0 and

1.

The 2S-pin cables ("B" cable) are connected separately from the controller to each drive. The maximum length of the SO-pin cable is 100 feet. The maximum length of the 2S-pin cable is 50 feet. Table 1-2 lists the SO-pin interface signals, and Table 1-3 lists the 2S-pin interface signals.

OPERATING SYSTEM COMPATIBILITY

RT-ll: The emulation is transparent to the RT-ll version 4.0 operating system, using the standard device handler supplied by DEC.

RSX-ll: The emulation is transparent to the

RXS-ll version 4.0 operating system, using the standard device handler supplied by DEC.

RSTS: The emulation is transparent to the RSTS version 7.2 operating system, using the standard device handler supplied by DEC.

Table

1-2.

Controller To Drive

1/0

Interface-

"A" Cable

Signal Name

(DILOG Term)

DEVICE' SELECT 0 (USELO)

DEVICE SELECT 1 (USEL 1)

DEVICE SELECT 2 (USEL2)

DEVICE SELECT 3 (USEL3)

SELECT ENABLE (USTAG)

SET CYLINDER TAG (TAG1)

SET HEAD TAG (TAG2)

CONTROL SELECT (TAG3)

BUS OUT 0 (BITO)

BUS OUT 1 (BIT1)

BUS OUT 2 (BIT2)

BUS OUT 3 (BIT3)

BUS OUT 4 (BIT 4)

BUS OUT 5 (BIT5)

BUS OUT 6 (BIT6)

BUS OUT 7 (BIT7)

BUS OUT 8 (BIT8)

BUS OUT 9 (BIT9)

BUS OUT 10 (BlnO)

DEVICE ENABLE (OCD)

INDEX (INDEX)

SECTOR MARK (SEC)

FAULT (FAULT)

SEEK ERROR (SERR) .

ON CYLINDER (ONCYL)

UNIT READY (UN ROY)

WRITE PROTECTED (WPRT)

ADDRESS MARK (AMF)

BUS·DUAL·PORT ONLY

SEQUENCE IN (PICK)

HOLD (HOLD)

Pin Polarity

(Active)

-

+ Source

23

24

26

27

22

1

53

Controller

54 Controller

56 Controller

57 Controller

52

Controller

31 Controller

32 Controller

33 Controller

8

9

10

2

3

4

5

6

7

34 Controller

35

Controller

36 Controller

37

Controller

38 Controller

39 Controller

40

Controller

41 Controller

42 Controller

11

12

13

30

14

18

43 Controller

60 Controller

44

48

Controller

Drive

25

15

16

55 Drive

45

Drive

46 Drive

17

. 47

Drive

19

49

Drive

28

20

21

29

58

Drive

50

Drive

51

Drive

Controller

59 Controller

Table 1-3. Controller To Drive

1/0

Interface-

"8" Cable

Signal

(DILOG Term)

Ground

Servo Clock (SCLOCK)

Ground

Read Data (RDATA)

Ground

Read Clock (RCLOCK)

Ground

Write Clock (WCLOCK)

Ground

Write Data (WDATA)

Ground

Unit Selected (USEL)

Seek End (SEEK)

Ground

Reserved for Index

Ground

Reserved for Sector

Pin Polarity

(Active)

-

+ Ground Source

1

2 14 Drive

15

3 16 Drive

4

5 17 Drive

18

6 19 Controller

7

Controller

8 20

21

22 9

10 23

Drive

Drive

11

12 24

25

13 26

1-3

CONTROLLER SPECIFICATIONS·

Mechanical-The Model DQ215 is completely contained on one quad module 10.44 inches wide by 8.88 inches deep, and plugs into and requires one slot in any DEC LSI-II based backplane.

Computer I/O

Register Addresses (PROM selectable)

-Control/Status Register 1 (RKCSl) 777 440

- Word Count Register (RKWC) 777 442

-Bus Address Register (RKBA) 777 444

-Disc Address Register (RKDA) 777-446

-Control/Status Register 2 (RKCS2) 777 450

-Drive Status Register (RKDS) 777 452

-Error Register (RKER) 777 454

-Attention Summary/Offset Register (RKAS/

OF) 777 456

-Desired Cylinder Register (RKDC) 777 460

-Extended Memory Address Register (RKXMA)

777 462

-Data Buffer Register (RKDB) 777 464

-Maintenance Register 1 (RKMRl) 777 466

-ECC Position Register (RKECPS) 777 470

-ECC Pattern Register (RKECPT) 777 472

- Maintenance Register 2 (RKMR2) 777 474

-Maintenance Register 3 (RKMR3) 777 476

-Enable Real Time Clock Control (RKERTC)

777 546

Data Transfer

-Method: DMA

- Maximum block size transferred in a single operation is 64K words.

Bus Load

-1 std unit load

Address Ranges ..

~

- Disc drive: up to 220.32 megabytes

-Computer Memory: to 2 megawords

Interrupt Vector Address

-PROM selectable, factory set a~

210 (alternate

254) priority level BR5

Disc Drive I/O

Connector-one 60-pin type "A" flat ribbon cable mounted on outer edge of controller module Two 26pin type "B" ribbon cables

(1 for each drive interfaced with). ..

Signal-SMD A/B flat cable compatible

Power-+5' 'Volts at 3.5 amps, +12 volts at 300 milliamps from computer power supply.

Environment-Operating temperature 40°F. to

140°F., humidity 10 to 95,% non-condensing.

Shipping Weight-5 pounds, includes documentation and cables.

*Specifications subject to change without notice.

1-4

SECTION 2

INSTALLATION

INSPECTION

The padded shipping carton that contains the con-

. troller board also contains an instruction manual and cables to the first disc drive if this option is exercised. The controller is completely contained on the quad-size printed circuit board. Disc drives, if supplied, are contained in a separate shipping carton. Inspect the controller and cables for damage.

CAUTION

If damage to any of the components is noted, do not install. Immediately inform the carrier and DILOG .

Installation instructions for the disc drive are contained in the disc drive manual. Before installing any components of the disc system, read Sections 1,

2 and 3 of this manual. Figure 2-1 illustrates the configuration of the controller. Tables 2-1 and 2-2 describe switch and jumper settings.

J2

J3

PIN 1

~ r1 n

017

S1D

0-

S9

0

-C

E16

-A

-e

019 pe K

Re -

S8

C23

S1D

E23

JP

• 3

• 2

• 1 r

Figure 2-1. Controller Configuration r1

2-1

Table 2-1. Configuration Switches

LOCATION D17 SWITCHES

Sl 52 S3

\

(LSB) (M5B)

,

T

Binary Number of the first logical unit of the second physical drive.·

54

ON

=

Bootstrap

OFF enable

=

Bootstrap disable

55

ON

=

Controller error correction

OFF = CPU error correction

,

86

(L5B

57 58

(M5B), y

Binary number of last addressable logical unit.

59

ON = Enable Real Time

Clock Control. When enabled, emulates the real time clock register, address 777 546

OFF= Disables Real Time

Clock Control.

• For example, if there are four logical units (numbered 0-3) in the first drive, set the switches for the fifth logical unit (number 4) as follows:

(LSB)

51 o

52

0

(M5B)

S3

Note

If S1, S2, and

S3

are off (000), the control/er will default to aI/logical units on the first physical drive (drive 0). Because of the characteristics of some operating systems, the switches should be set for two drives even if only one drive is present.

LOCATION C23 SWITCHES

Switch

51

52

S3

S4

55

56

57

58

Position

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

Logical Unit and Emulation

LUO

LUO

LU1

=

RK07

=

RK06

=

RK07

LU1 = RK06

LU2

LU2

=

RK07

=

RK06

LU3 = RK07

LU3 = RK06

LU4

=

RK07

LU4

=

RK06

LU5 = RK07

LU5

LU6

LU6

LU7

LU7

=

RK06

=

RK07

=

RK06

=

RK07

=

RK06

Table 2-2. Jumper Installation

BOOTSTRAP

ADDRES5 JUMPERS E16

INTERRUPT LEVEL

DEVICE

ADDRE55 JUMPERS 019

D.

.C

.A

.B

Jumper Installed

JP1, JP2, JP3

JP2, JP3

JP1, JP3

JP1

• A to B (standard) 773 000

A to C (alternate) 775 000

Level

BR4

BR5 (Factory Set)

BR6

BR7

R to K (standard) 777 440

Interrupt Vector

=

210

R to P (alternate) 776 700

Interrupt Vector

=

254

·On an L51-11/23PLU5 computer, bootstrap address 775000 must be used.

PRE-INSTALLATION CHECKS

There are various LSI -II configurations, many of which were installed before DEC made a hard disc available for LSI-II based systems. Certain configurations require minor modifications before operating the disc system. These modifications are as follows:

A. If the system contains a REV11-C module, it must be placed closer to the processor module

(higher priority) than the controller if the

DMA refresh logic on the REV11-C is enabled.

B. If the 4K memory on the DK11-F is not used and the memory in the system does not require external refresh, the DMA refresh logic on the REV11-C should be disabled by removing jumper W2 on the REV11-C module.

C. If the system contains a REV11-A module, the refresh DMA logic must be disabled since the module must be placed at the end of the bus (REV11-A contains bus terminator).

D. If the REV11-C module is installed, cut the etch to pin 12 on circuit D30 (top of board) and add a jumper between pin 12 and pin 13 of D30.

E. If the system requires more than one backplane, place the REV-II terminator in the last available location in the last backplane.

INSTALLATION

To install the controller module, proceed as follows:

CAUTION

Remove DC power from mounting assembly before inserting or removing the controller module.

Damage to the backplane assembly may occur if the controller module is plugged in backwards.

1. Select the backplane location into which the controller is to be inserted. Be sure that the disc controller is the lowest priority DMA device in the computer except if the DMA refresh/bootstrap ROM option module is installed in the system. The lowest priority device is the device farthest from the processor module. Note that the controller contains a bootstrap ROM.

There are several backplane assemblies available from DEC and other manufacturers. Figure 2-2 shows typical backplane configurations. Note that the processor module is always installed in the first location of the backplane or in the first location in the first backplane of multiple backplane systems.

I t is important that all option slots between the processor and the disc controller be filled to ensure that the daisy-chained interrupt

(BIAK) and DMA (BDMG) signal be complete to the controller slots. If there must be empty slots between the controller and any option board, the following backplane jumpers must be installed:

FROM

CO x NS

CO x S2 t

Last Full

Option Slot

TO

CO x M2

CO x R2 t

Controller

Slot

SIGNAL

BIAK1/l0

BDMG1/LO

2. Insert the controller into the selected backplane position .. Be sure the controller is installed with the components facing row one, the processor.

The controller module is equipped with handles on the side opposite the slot connectors. Gently position the module slot connectors into the backplane then press until the module connectors are firmly seated into the backplane. Both handles must be pressed simultaneously. When removing the module, apply equal pulling pressure to both ha~l(iles.

3. Feed the module connector end of the disc I/O cables into the controller module connectors.

Ensure pin 1 is matched with the triangle on the connector as shown in Figure

2

8

1. Install the cable connectors into the module connectors. Verify that the connectors are firmly seated.

4.

Connect the disc-end of the I/O cables to the disc I/O connectors. Be sure that the bus terminator is installed at the last disc in the system.

5.

Refer to the disc manual for operating instructions and apply power to the disc and computer.

6. Observe that the green DIAGnostic LED on the controller board is lit.

7. . The system is now ready to operate. Refer to

Section 3 for operating instructions, diagnostics, and formatting.

2-3

LOCATION

2

3

4

A

OPTION 2

OPTION 3

OPTION 6

B C

OPTION 1

OPTION 4

OPTION 5

0

PROCESSOR

MODULE t

COMPONENT SIDE

SOLDER SIDE

~

. PREFERRED DISC

CONTROLLER LOCATION

H9270 MODULE INSERTION SIDE

E

A

B C

0

E

[7

OPTION 2 OPTION 1

+12V

~

0

-5V

+5V

+5VB g

0

~-

GND

GND

-12V

0

~---

~

0

OPTION 3

OPTION 6

OPTION 7

OPTION 10

OPTION 11

OPTION 4

OPTION 5

OPTION

OPTION

8

9

OPTION 12

POWER

TERMINA

L /

BLOCK

OPTION 14

OPTION 15

OPTION 13

OPTION .16

PREFERED DISC

CONTROLLER LOCATION

DDV11· B BACKPLANE MODULE INSERTION SIDE

"

NOTE

MEMORY CAN BE INSTALLED IN ANY SLOT; IT IS NOT

PRIORITY DEPENDENT AND DOES NOT NEED TO BE

ADJACENT TO THE PROCESSOR.

CONTROLLERS ARE ALSO COMPA TlBLE WITH H9273A

MODULES.

F i

USER DEFINED

SLOTS

Figure 2·2. Typical Backplane Configuration

8

/

9

4

5

2

3

6

7

GROUNDING

To prevent grounding problems, DILOG recommends standard ground braid be installed from the computer DC ground point to the disc drive DC ground point and also between disc drives at the DC ground points.

2-4

SECTION 3

OPERATION

INTRODUCTION

This section contains procedures for operating the computer system with the controller and a disc drive or drives. An understanding of DEC operating procedures is assumed. The material here is provided for' 'first time users" of disc subsystems and describes procedures for bootstrapping, formatting, and diagnostic testing.

The programs supplied with each controller are on floppy disc or magnetic tape media, depending on what is specified on the sales order. If the user is not able to run floppy disc or magnetic tape media, an

EPROM program may be used for some subsystems to format the disc. Instructions and constraints for the EPROM program are described at the end of this section.

PRECAUTIONS AND PREOPERATIONAL

CHECKS

The following precautions should be observed while operating the system. Failure to observe these precautions could damage the controller, the disc cartridge, the computer, or could erase a portion or all of the stored software.

1. If the controller bootstrap is to be used, set controller switch S4 on, and disable other bootstraps that reside at that address.

2.

See Figure 2-1 for proper positions of the switches and jumpers.

See Tables 2-1 and 2-2 for switch and jumper settings.

3. Do not remove or replace the controller board with power applied to the computer.

4.

If system does not operate properly, check operating procedures and verify that the items in Section 2 have been performed.

Before operation the following checks should be made:

1. Verify that the controller board is firmly seated in backplane connector.

2. Verify that the cables between the controller and the disc drive are installed.

3. Be sure the disc drive cartridge is installed (if it is to be used).

4. Apply power to the computer and the console device.

5. Verify that green DIAG light on front edge of the controller board lights.

6. Be sure power is applied to disc drive and

READY light is on.

BOOTSTRAP PROCEDURE

The following assumes the system is in· ODT mode. Note that the bootstrap can be used under processor Power Up Mode 2 conditions. Refer to the appropriate DEC manual for a discussion of the

Power Up Modes. Further note that the disc drive does not need to be READY to enter the bootstrap.

Reset the system by pressing RESET or enter the following (characters underlined are output by the system; characters not underlined are input by the operator):

@

773000G or 775000G

Depends on jumper configuration above.

*

Enter one of the following: DMO, DPO, DLO,

DRO, MSO, MTO, DYO or FT <CR>.

Definitions are as follows:

DM

=

RK06/07

Disc

DP = RP02/03 Disc

DL

=

RLOl102 Disc

DR

MS

MT

DY

FT

=

RM02/03

Disc

=

TSII Tape

=

Tape

=

RX02 Floppy Disc

=

EPROM Formatter.

Booting can be executed from logical units other than "0" shown above by entering the desired logical unit number, i.e., 1, 2, 3, ... or 7.

3-1

FORMAT AND DIAGNOSTIC TEST PROGRAM

Description

DILOG's Universal Firmware and Diagnostic

Program permits the user to format a disc pack for his particular application; compensate for media errors; and test the controller and drive. When formatted, the disc may be partitioned horizontally or vertically. Either way the pack is divided into logical units which the computer recognizes. The user may select one of three types of partitioning:

I-head, 2-head or vertical.

The constraints for selecting each are:

Subsystem:

• Maximum number of logical units is 8.

I-head:

• Maximum number of heads (surfaces) is 8.

• Maximum size of logical units is 270,336 records.

2-head:

• Maximum number of heads (surfaces) is 16.

• Number of fixed and removable heads (surfaces) must be even.

• Maximum size of logical units is 270,336 records.

Vertical:

• Maximum size of logical units is 270,336 records.

Drive types CMD or DFR are formatted for a

I-head partition. SMD or MMD types are usually formatted vertically.

The disc pack is divided vertically by cylinders and horizontally by heads (or data surfaces). Each head (surface) is further divided into tracks. A track is addressed by cylinder number and head number.

Tracks are further divided into sectors (or records or blocks) which the computer recognizes as increments within a logical unit. Sectors consist of overhead bytes (such as address, sync, error correction) and data bytes. The standard number of data bytes, bytes usable by the computer, is 512 data bytes per sector. Figure 3-1 illustrates vertical and head partitioning.

Table 3-1 is a partial list of disc drives and specifications for partitioning. Column 1 lists the manufacturer. Column 2 lists the model number. Column

3 lists the number of sectors (also called records and blocks) per track. Column 4 lists the number of heads (also called data surfaces) per drive. Column 5 lists the number of cylinders per drive. Columns 6

3-2

HEAD 2

COVER - - - - - ,

HEAD PARTITION

HEADO

DISK SURFACE

- - - M

HEAD 1

DISK SURFACE

--~

HEAD 17

HEAD 18

DISK SURFACE

- - - . n

HEAD 19

VERTICAL PARTITION

*CYLINDER

/ \.

823

000

A TRACK IS ACCESSED

BY SPECIFYING CYLINDER

ADDRESS AND HEAD ADDRESS

*NUMBER OF CYLINDERS AND HEADS

VARIES WITH TYPE OF DRIVE

Figure 3-1. Partitions and 7 list the emulations, the number of megabytes per logical unit, and the number of sectors per logical unit. Column 8 lists the· megabyte capacity and number of sectors of the last logical unit partitioned. For CMD drives (Note c), the value listed is

'for all logical units as well as the last.

To use the table, consider Ampex Capricorn 165 as an example. The drive is efficiently partitioned into five RK07 units with capacity and number of sectors shown at the top of Column 6. The remaining capacity is assigned as one RK06 unit with the capacity and sectors shown at the top of Column 7; however, the RK06 unit is the remainder after partitioning five RK07 units, and as such, this remainder is not a complete RK06 unit. Instead of

13.88 Mbytes with 27,126 sectors, the partial RK06 unit is assigned the remaining 8.78 Mbytes and

17,150 sectors. Notes a and b in Column 8 state

Table 3·1. Values for Partitioning with Universal Firmware (DQ215)

AMPEX

AMPEX

AMPEX

AMPEX

AMPEX

AMPEX

AMPEX

BALL

BALL

BASF

CONTROL DATA CORP. MMD 9730-160

CONTROL DATA CORP. SMD 9762

CONTROL DATA CORP. SMD 9764

FUJITSU

FUJITSU

FUJITSU

FUJITSU

KENNEDY

KENNEDY

(1)

Manufacturer

CENTURY DATA SYS.

CENTURY DATA SYS.

CENTURY DATA SYS.

(2)

Model

Number

Capricorn 165

Scorpio 48

(6) (7)

(3) (4)

Total Logical Units

Sectors Heads

RK07 RK06

(Records)

(Data Surfaces)'

(Blocks)'

Drive

(5)

Units Units

Cylinders' 27.54MB 13.88MB

Track Removable Fixed Drlve*

53,790 27,126

(8)**

Last Log ical Unit

MB Sectors

35

35

0

0

10

3

823

823

5

1

Scorpio 80

DFR-932

DFR-964

DFR-996

DM980

BD50

BD80

6172

M80

M160

Trident T-82RM

CONTROL OAT A CORP. CMD 9448-32

CONTROL OAT A CORP. CMD 9448-64

CONTROL DATA CORP. CMD 9448-96

CONTROL DATA CORP. MMD 9730-24

CONTROL DATA CORP. MMD 9730-80

M-2283

M-2284

2311

2312

5303

5305

35

34

34

34

34

23

34

23

35

35

34

34

34

34

35

35

35

34

34

35

35

35

35

35

35

0

1

1

1

5

5

5

0

0

0

5

1

1

1

0

0

0

5

19

0

0

0

0

0

0

5

1

3

5

0

0

0

3

6

6

0

1

3

5

2(5) = 10

0

0

4

2(5) = 10

4

7

3

5

823

823

823

823

823

815

815

600

650

837

823

823

823

923

2(2)= 4 320

5 823

823

823

411

823

815

589

589

700

700

2

2

1

2

2

5

2

2

5

2

4

2

5

1

2

1

2

8.788 17,150

16.45b

32,130

2.258 4,410

18.18b 35,525

3.498 6,825

14.25

c

14.25

c

14.25

c

27,846

27,846

27,846

16.10b

1.658

20.19b

6.068

31,450

3,230

39,445

11,845

15.40b

30,090

.958 1,870

13,938 7.138

14.86

b

0.1~

29,028

246

3.048 5,940

16.10b

1.658

14.25

c

14.25

c

14.25

c

16.10b

1.658

31,450

3,230

27,846

27,846

27,846

8.748

17,080

18.18b 35,525

3.498 6,825

8.788 17,150

31,450

3,230

23.48b

3.518

3.088

45,866

6,860

6,020

7.348

14,350

14.33b 28,000

0.218

420

18.18b 35,525

3.768 7,350

9.838 19,215

9.568 18,690

7.168 14,000

6.458 12,600

1

1

5

1

1

4

1

6

1

3

1

5

2

4

6

2

1

6

1

1

6

1

6

2

1

6

1

1

6

1

6

1

4

1

6

2

1

1

4

4

6

• For a 1-head partition, the value of cylinders/drive = tracks/surface.

• ·Calculated using 4 alternates. aLess than standard RK06 bGreater than standard RK06 cCMO

3-3

Table 3-1. Values for Partitioning with Universal Firmware (DQ215) (Continued)

NEC

NEC

(1)

Manufacturer

KENNEDY

MITSUBISHI

(2)

Model

Number

5380

NIPPON PERIPHERALS NP30-40

NIPPON PERIPHERALS

NIPPON PERIPHERALS NP30-120

PRIAM

PRIAM

PRIAM

TECSTOR

TECSTOR

2860-2

01220

01240

NP30-80

OISKOS 3350

6650

15450

Sapphire 160

Sapphire 165

(3) (4)

(6) (7)

Total Logical Units

Sectors

(Records)

(Blocks)1

Heads

(Data Surfaces)1

Drive

(5)

Cylinders!

Track Removable Fixed Drlve*

RK07

Units

27.S4MB 13.88MB

53,790

RK06

Units

27,126

Last Log Ical Unit

MB

(8) **

Sectors

35 0 5 823 2

23,

35

35

35

35

35

35

35

35

35

35

0

0

0

0

0

0

0

0

0

0

0

7

4

2(4)=8

5

11

11

3

3

7

12

10

548

530

530

370

370

555

561

1121

1121

700

823

' 1

1

2

1

2

3

1

2

5

5

5

1

8

1

3

1

3

1

6

1

5

1

1

3

1

6

1

6

1

4

1

1

18.18b 35,525

3.49a

6,825

17.22b

3.05a

33,649

5,957

10.10a 19,740

9.89a 19,320

20.07b 39,200

5.87a

11,480

5.19a 10,150

4.03a 9,450

16.95b 33,110

2.16a 4,235

25.82b

50,435

10.64a

20,790

2.36a

2.09a

4.89a

4.35a

4,620

4,095

9,555

8,505

2.38a 4,655

10.96a 21,420

8.78a 17,150

·For a i-head partition, the value of cylinders/drive = tracks/surface.

• ·Calculated using 4 alternates. aLess than standard RK06 bGreater than standard RK06 cCMO whether the last unit is an expanded or a partial unit.

The values in the table are calculated for the most efficient use of the drive; that is, total formatting capacity of the drive with a standard number of spare cylinders. The user may require another type of partitioning for a particular application, in which case the program will prompt and calculate for that application.

Parameters for disc drives not listed in Table 3-1 may be determined from manufacturer's specifications and the following: Determine the number of bytes per track from the manufacturer's specification. The number of bytes per sector (data and overhead) for DILOG controllers is 576. Divide the number of bytes per track by the number of bytes per sector. Drop the remainder. This value is the number of sectors per track. Then, number of sectors per track

X number of heads X number of cylinders per drive

= number of sectors per drive.

The user may require alternate cylinders, or spares, to compensate for media flaws, soft errors, or marginal drive conditions. The values in the table

3-4 provide for four alternate cylinders. All three types of partitioning in the program make provisions for sparing. The program accounts for alternates when calculating the number and size of logical units.

If the number of logical units is to be changed, the configuration switches, shown in Figure 2-1, should also be changed after completion of format and test.

The descriptions below indicate what parameters will be changed as various elements are changed; for example, if the number of logical units is changed, the size of the logical units will change.

I-Head Partition

A I-head partition is used for CMD drives. The column numbers below refer to Table 3-1. Parameters are developed as follows:

1. Determine the number of sectors per track

(Column 3), heads per drive (Column 4), and tracks per surface (Column 5). For a I-head partition, the number of tracks per surface is the same as cylinders per drive in the table.

2. Determine the number of alternate tracks

(cylinders) per drive. The standard number of alternates is four.

3. Subtract the number of alternates from the tracks per surface.

4. The number of heads corresponds to the number of logical units.

5. Then, sectors per track

X heads per drive

X

(tracks per surface minus alternates) sectors per drive.

6. Sectors per drive

X

512

= byte capacity.

For example, an AMPEX DFR-932 has 34 sectors per track, 2 heads per drive and 823 tracks/surface.

If 4 alternates are required, then:

34

X

2

X

(823 - 4) = 55,692 sectors/drive

Because there are two heads, there are two logical units.

55,692 = 27,846 sectors/logical unit

2 and

27,846

X

512

=

14.25 megabytes/logical unit

2-Head Partition

The parameters for 2-head partitioning are the same as for I-head except the number of sectors/ logical unit is multiplied by 2:

1. Determine the number of sectors per track

(Column 3), heads per drive (Column 4), and tracks per surface (Cylinders per Drive,

Column 5).

2. Determine the number of alternate tracks

(cylinders) per drive. The standard number of alternates is four.

3. Subtract the number of alternates from the tracks per surface.

4. Then, sectors per track

X heads per drive

X

(tracks per surface minus alternates)

= sectors per, drive.

5. Sectors per drive X 512

= byte capacity.

For example, a CDC 9730-24 has 35 sectors per track, 4 heads per drive and 320 tracks per surface.

If 4 alternates are required, then:

35

X 4 X

(320-4)

=

44,240 sectors/driv~

Because there are four heads, and two heads comprise one logical unit, there are two logical units.

44,240

=

22,120 sectors/logical unit

2 and

22,120

X

512

=

11.32 megabytes/logical unit

Vertical Partition

With vertical partitioning, the user may select the number of logical units or the size of the logical unit.

If the number of logical units is selected, the logical units will be of equal size. If the size of the logical units is selected, all logical units may not be of equal

. size. For example there may be 2 equal RK07 logical units of 53,790 sectors/logical unit and a partial

RK06 logical unit of 31,450 sectors/logical unit.

Parameters for vertical partitioning are determined as follows:

The user specifies the number of logical units (all logical units are of equal size):

1. Determine the required number of alternate cylinders per drive. Subtract the number of alternates from the number of cylinders per drive (Column 5). This value is the usable cylinders per drive.

2. Determine the number of logical units per drive required. Then,

3. Number of usable cylinders per drive divided by number of logial units required

=

Number of cylinders per logical unit. The remainder is assigned as alternate.

4. Number of cylinders per logical unit

X sectors per track

X number of heads =

Number of sectors per logical unit.

5. Number of sectors per logical unit

X

512

Megabyte capacity per logical unit.

=

For example, if the user has a Century Data drive,

Model T-82RM and 4 alternates (standard) and 3 logical units are required, then

823 - 4

=

819 usable cylinders and

819 = 273

3

If there was a remainder, the number of alternates would be more than initially selected.

3-5

Then,

273 X 34 X 5

=

46,410 sectors per logical unit and

46,410

X

512 = 23.76 Mbytes per logical unit

The user specifies the size of logical units in sectors per logical unit (the last logical unit will be a different size).

1. Determine the required number of alternate cylinders per drive. Subtract the number of alternates from the number of cylinders per drive (Column 5). This value is the usable cylinders per drive.

2. Determine the required number of sectors

(blocks) per logical unit. Then,

3. Sectors per track (Column 3)

X number of heads (Column 4) divided into sectors per logical unit = cylinders per logical unit. If there is a remainder, the number of cylinders per logical unit is rounded off to the next higher number.

4. Number of usable cylinders divided by cylinders per logical unit

= number of logical units. If there is a remainder, the number of logical units is rounded off to the next higher number.

5. Number of cylinders per logical unit

X number of full (equal size) logical units

=

Number of cylinders full (equal size) logical units.

6. Number of usable cylinders per. drive minus number of cylinders in full logical units

=

Number of cylinders in partial logical unit.

For example, if the user has a Century Data drive,

Model T-82RM, and 4 alternates and 53,790 sectors per logical unit (standard RK07) are required, then

823 - 4

=

819 usable cylinders and

53,790 = 316.41

34 X 5 which becomes

317 cylinders per logical unit then,

819

317

=

2.58 logical units per drive or 2 RK07 units and 1 partial RK06 unit.

For the partial logical unit,

317

X

2

=

634

819 - 634

=

185 cylinders per partial logical unit

Sectors per the partial unit are calculated as follows:

185

X

34

X

5

=

31,450 sectors per partial logical unit.

3-6

Partitioning Program

The name of the program is DMXXD, where XX is the revision number of the program.

Figure 3-2 is a flow diagram of the program. The statements in quotes are program prompts. The pentagonoid symbols with a letter and number, such as "AI," are reference points for breaks in the flow.

The "A" designation refers to the first page

(Format) and the "B" designations refer to the second page (Change Parameters). The following descriptions refer to the first (Format) page of the diagrams.

When the program is initialized the following display will appear on the terminal:

DILOG'S UNIVERSAL FIRMWARE AND

DIAGNOSTIC PROGRAM VERIFIES PROP-

ER FUNCTIONING OF THE DILOG RK06/

RK07 EMULATING DISC CONTROLLER

AND FORMATS THE DISC TO YOUR

SPECIFICATIONS.

YOUR DEFAULT PARAMETERS ARE:

SECTORS_

HEADS_

CYLINDERS_

ALTERNATES _

SIZE OF LOGICAL UNIT (RECORDS)_

The parameters displayed are calculated for the efficiency of most applications. The units of measure are as follows: sectors/track; heads/drive; cylinders/drive; alternates/drive; and the size of logical unit in sectors/logical unit.

The next display will be:

***************************************

******: RESTART ADDRESS IS 20001*****

*******II"·X RESTARTS

PROGRAM~******

*****

I\C

RESTARTS CURRENT TEST ****

***************************************

To restart, press the CTRL and X keys. at the same time, or CTRL and C.

The next query is:

ARE YOU RUNNING THE DIAGNOSTIC VIA

A CRT (Y OR N)?

If the answer is no, the CRT will not display the current cylinder address during the test program.

The next prompt is:

ENTER NUMBER OF DRIVES

Enter 1 or 2. If 1 is entered, the next queries will refer only to Drive o.

If 2 drives are selected, the program will prompt for Drive 0 and Drive 1.

The next displays will be:

ENTER DM DEVICE ADDRESS <777440> ?

ENTER DM INTERRUPT VECTOR

<000210> ?

The address is factory set unless the user requested an alternate address (see Section 2).

The next question will be:

LSI (Y OR N)?

If the controller model is DQ215, answer Y. If the model is DU215, answer N.

The menu of drives will appear next, with the following:

***** DRIVE 0 *****

ENTER NUMBER CORRESPONDING TO

DISC DRIVE

OR

SELECT ANOTHER PAGE

N

=

NEXT PAGE P

=

PREVIOUS PAGE E

=

ENTER PARAMETERS

From the menu, the appropriate drive may be selected. If E is pressed, the program will prompt for drives not listed in the menu or will prompt to change parameters in case of conflicts in constraints.

Note

The program responds with the minimum number of inquiries; for example, if a drive is selected from the menu, the program will not prompt for the number of sectors, heads and cylinders, because these responses are predetermined.

If a drive is selected from the menu, the next display' will be:

DO YOU WISH TO CHANGE FORMAT

PARAMETERS (DRIVE O)?

Note

The format parameters are those last entered. Each time there isa change, the program will retain that change.

If the response is No, the next display will show the configuration. An example is as follows:

DISC SUBSYSTEM CONFIGURATION

LOGICAL

UNIT

PHYSICAL RECORD

DRIVE MEGABYTES SIZE

DMO

DMI

DM2

DM3 o o o o

27.59

27.59

27.59

25.82

53900

53900

53900

50435

3-7

3-8

SET CRT

SWITCH

DISPLAY

MENU

SET

HARDCOPY

SWITCH

SET FOR

2 DRIVES

"ENTER DEVICE

ADDRESS OR

RETURN FOR

DEFAULT"

"ENTER INTER-

RUPT VECTOR

OR RETURN

FOR DEFAULT"

SET FOR

1 DRIVE

SET MENU

SWITCH

GET

PARAMETERS

FOR SELECTED

DRIVE

GO TO CHANGE

PARAMETERS

SET PDP

SWITCH

SET LSI

SWITCH

. *TO OR FROM OPPOSITE PAGE

CLEAR MENU

SWITCH

SET FIXED

MEDIA SWITCH

N

DISPLAY

SUBSYSTEM

CONFIGURATION

BEGIN TEST

SET

REMOVABLE

MEDIA switCH

Figure 3-2(A). Universal Formatting

ENTER NEW

VALUE

ENTER NEW

VALUE

ENTER NEW

VALUE

ENTER NEW

VALUE

ENTER NEW

PARTITION

"ENTER

1) RK06

2) RK07"

ENTER NEW

VALUE

ENTER NEW

VALUE

DISPLA Y EXTRA

CYLINDER MESSAGE

AND COLLECT

OPERATOR

RESPONSE

°TO OR FROM OPPOSITE PAGE

Figure 3·2(B). Universal Formatting-Change Parameters

3·9

DM4

DM5

DM6

DM7

1

1

1

1

27.59

27.59

27.59

25.82

53900

53900

53900

50435

PHYSICAL DRIVE 0 HAS 44 ALTERNATE

TRACKS

PHYSICAL DRIVE

1

HAS 44 ALTERNATE

TRACKS

ARE YOU SURE?

If the answer is Yes, the next display will show how the switches should be set:

LOCATION ON

OFF SWITCH

D-17

DESCRIPTION:

9 CLOCK ENABLE

9

8

7

6

5

4

3

2

1

6-8 LAST LOGICAL

UNIT

5 ECC SWITCH

4 BOOTSTRAP

ENABLE

1-3 LOGICAL UNIT

CROSSOVER

DEFINITIONS:

LIU CROSSOVER: 1ST LOGICAL UNIT ON 2ND

DRIVE

BOOTSTRAP ENABLE: ON

=

ENABLED, OFF

=

DISABLED

ECC SWITCH: ON

=

CONTROLLER MODE, OFF

=

SOFTWARE MODE

LAST L/U: LAST LOGICAL UNIT ON SUBSYSTEM

SET SWITCHES 1-3 TO A BINARY WEIGHTED

VALUE OF X.

SET SWITCHES 6-8 TO A BINARY WEIGHTED

VALUE OF X.

USE (C) TO CONTINUE

If the switches are set incorrectly, the message will repeat. Switch settings are described in Section

2.

If the switches are set correctly, the program will skip to the test section.

The following descriptions refer to the second

(Change Parameters) page of the diagram.

If the answer is Yes to the prompt:

DO YOU WISH TO CHANGE FORMAT

PARAMETERS (DRIVE O)? the next prompt will be:

CHANGE NUMBER OF SECTORS (Y OR N)?

CHANGE NUMBER OF HEADS (Y OR N)?

CHANGE NUMBER OF CYLINDERS (Y OR

N)?

These prompts are for adding a drive that is not on the menu. The values (after HOW MANY?) to be entered are in the drive manufacturer's manual. The

3-10 next prompt of change parameters is for drives which are or are not on the menu:

CHANGE NUMBER OF ALTERNATES (Y OR

N) <4> ?

The standard number of alternates selected is

4.

If a CMD drive is selected, there will be no further questions. If Yes, HOW MANY? will appear. The next query is:

CHANGE TYPE OF PARTITION (Y OR N)

<VERTICAL> ?

If the answer is Yes, the program will prompt with I-HEAD, 2-HEAD, OR VERTICAL? If I-head or 2-head is selected there will be no further queries.

Next to appear is:

STANDARD SIZE UNITS (Y OR N)?

If Yes, the program will prompt with selection of

RK07 or RK06. If RK07 is selected, the program will divide the record size into RK07 units, and the remaining records will be an RK06 unit. Standard

,sizes are shown in Table

3-1.

After selection of standard units, the next message will be:

AFTER CALCULATING STANDARD SIZE

CYLINDERS NOT YET ALLOCATED ( _ _

MEGABYTES).

IF YOU WOULD LIKE, I COULD CREATE

ANOTHER UNIT, WHICH WILL BE

SMALLER THAN YOUR STANDARD SIZE

UNITS, OR I COULD ALLOCATE THE

CYLINDERS AS ALTERNATES.

PLEASE ENTER THE NUMBER OF

CYLINDERS YOU WOULD LIKE ME TO

ALLOCATE AS ALTERNATES, ANY RE-

MAINDER WILL BE ALLOCATED AS

ANOTHER UNIT.

If the standard number of alternates previously selected is adequate (default is

4), enter o.

The next display will be:

CHANGE SIZE OF LOGICAL UNIT

(RECORDS)(Y OR N) <XXXXX> ?

CHANGE NUMBER OF LOGICAL UNITS (Y

OR N) <X> ?

If Yes is answered to any of the last three questions, there will be no further questions. The above sequence will repeat for the second drive:

DO YOU WISH TO CHANGE FORMAT

PARAMETERS (DRIVE I)?

If the constraints are not violated, the Disc Subsystem Configuration and ARE YOU SURE? will appear. If the response is Yes, the program will begin the test sequence. If the subsystem constraints are violated, a message similar to the following will appear:

FORMAT PARAMETER CONFLICTS

SUBSYSTEM

DRIVE 0 IS CONFIGURED FOR 8 LOGICAL

UNITS

DRIVE 1 IS CONFIGURED FOR 3 LOGICAL

UNITS

MAXIMUM NUMBER OF LOGICAL UNITS

ALLOWED IS 8

To resolve this conflict, the number of logical units may be changed on Drive o.

To provide logical units of equal size on both drives, the number of logical units may be changed to

4 on each drive.

Restart the current address with AC, repeat the sequence above up to the question CHANGE

NUMBER OF LOGICAL UNITS?, and answer Y.

When HOW MANY? appears, answer

4 •.

Repeat this sequence for Drive

1.

Examples of errors on a single drive when changing the type of partition are as follows:

FORMAT PARAMETER CONFLICTS

DRIVE 0

MAXIMUM NUMBER OF HEADS WITH

I-HEAD PARTITION IS 8 or

FORMAT PARAMETER CONFLICTS

DRIVE 1

MAXIMUM NUMBER OF HEADS WITH

2-HEAD PARTITION IS

16 or

FORMAT PARAMETER CONFLICTS

DRIVE 0

MAXIMUM NUMBER OF HEADS MUST BE

AN EVEN NUMBER WITH 2-HEAD

PARTITION

Examples of errors on a single drive when changing the size of the logical units is as follows:

FORMAT PARAMETER CONFLICTS

DRIVE 0

LOG ICAL UNIT SIZE IS 270, 720

MAXIMUM LOGICAL UNIT SIZE IS 270, 336 or

FORMAT PARAMETER CONFLICTS

DRIVE 0

LOGICAL UNIT SIZE IS BIGGER THAN THE

DISC

The algorithm for mapping, that is, what the controller should map, is as follows:

Record Number

Sector/Cylinder

=

Correct Cylinder Address

+

Remainder

(1)

Remainder

(1)

Sector/Track

=

Correct Head Address

+

Remainder

(2)

Remainder (2)

=

Sector Address

A mapping error is displayed during the Random

Read test as follows:

*****MAPPING ERROR*****

RECORD NUMBER

SECTOR/TRACK

DRIVE NUMBER

=

XXX

SECTOR/CYLINDER

=

XXX

=

XXX

=

XXX

CORRECT ADDRESS

CYLINDER

HEAD

=

XXX

=

XXX

SECTOR

=

XXX

CONTROLLER ADDRESS

CYLINDER

HEAD

=

XXX

=

XXX

SECTOR

=

XXX

3-11

Diagnostic Test Program

The format/test program contains the following:

1.

TEST CONTROLLER

A. Registers

B. Data Buffer

C. DMA

D. ECC

2. TEST DISC DRIVE

A. Disc Ready

B. Disc Restore (seek to cylinder

0)

3. FORMAT

A. Write Headers

B. Read Headers

C. Write Data Test Pattern

D. Read Data Test Pattern

4. SEQUENTIAL READ

5. SELECTED READ

6. RANDOM SEEK, READ

7. RANDOM SEEK, WRITE, READ, AND

COMPARE

8. ASSIGN ALTERNATE TRACK

Test Controller

The program will automatically test the controller registers and data buffer. The program will only display error messages during this test; the display will be:

DATA BUFFER ERROR or the mnemonics of the controller registers and the location and contents (in Octal). The display of the registers is followed by a 4-line message to aid in isolating the specific problem.

Note

Whenever an error occurs and the registers are displayed, an audio alarm signal is generated to notify the operator.

The 4-line message is as follows:

DISC ADDRESS _ _

TYPE OF COMMAND _ _

CONTROL STATUS ERROR _ _

DRIVE STATUS _ _

"DISC" lists the sector, head and cylinder (in decimal) where the error occurred. An example of

Type of Command is Read Data Command. An example of Control Status is Seek Error.

The ECC logic test is as follows: The program selects whether a correctable or noncorrectable error is to be programmed; then the program creates an error; writes the data with an error to the controller; reads to memory; then the program decides whether the error is noncorrectable or correctable.

3-12

If noncorrectable, the program checks to ensure an error has been returned by the controller.

If correctable, the program checks to make sure there has been no error·returned by the controller, and checks to ensure the error was corrected in the proper manner. If this test fails, the message is one or more of the following:

CONTROLLER INDICATES CORRECTABLE

ERROR

CONTROLLER INDICATES NONCORRECT-

ABLE ERROR

ERROR BURST IS CORRECTABLE

ERROR BURST IS NONCORRECTABLE

ERROR BURST WAS NOT CORRECTED

The space character (SP) is used to exit from this test.

The program will next display:

USE C TO CONTINUE

USE 0 TO TRANSFER TO ODT

USE L TO REBOOT YOUR SYSTEM

"c" is used to continue the test. "0" is used for

ODT (on-line debugging technique). "L" is used to initiate the system bootstrap.

Test Disc Drive

After the controller test is performed, the program will automatically test the drive for ready and restore. The disc address is not displayed during this test. If the disc will not restore, the program will display the register for cylinder O.

Format

The operator may either select logical units sequentially or select one or more specific logical units to be formatted. Program messages are presented for formatting in logical unit number sequence:

FORMAT ENTIRE SUBSYSTEM (Y OR N)?

FORMAT ENTIRE DRIVE 0 (Y OR N)?

FORMAT ENTIRE DRIVE 1 (Y OR N)?

FORMAT ALTERNATE CYLINDERS DRIVE o

(Y

OR N)?

FORMAT ALTERNATE CYLINDERS DRIVE

1 (Y OR N)?

FORMAT DLO (Y OR N)?

FORMAT DL1 (Y OR N)?

FORMAT DL2 (Y OR N)?

FORMAT DL3 (Y OR N)?

Note

Before any write operation, the program will display ARE YOU SURE? This aids the operator in preventing reformatting of a previously formatted logical unit (possibly destroying good data).

During formatting, the following messages will appear sequentially:

WRITING HEADERS

CURRENT CYLINDER ADDRESS - - - -

READING HEADERS

CURRENT CYLINDER ADDRESS - - - -

WRITING DATA TEST PATTERN - - - -

CURRENT CYLINDER ADDRESS - - - -

READING DATA TEST PATTERN - - - -

CURRENT CYLINDER ADDRESS ~---

When reading and writing headers, the program will display the cylinder addresses sequentially. The test pattern tests are also sequentially selected, and the cylinder address displayed will correspond to the current address being read.

After each logical unit is formatted, the display will be:

DM_ FORMAT AND VERIFICATION

COMPLETE

Sequential Read

For this test, the display will be:

SEQUENTIAL READ (ALL CYLINDERS AND

HEADS)?

If the response is No, the program will jump to the

Selected Read test.

If the response is Yes, the current cylinder address is displayed as each cylinder is read. If an error is detected, the register contents and location are displayed with the 4-line identification message, and the following:

ASSIGN ALTERNATE TRACK FOR

DEFECTIVE TRACK?

If no alternates (spares) are available, the following will be displayed:

NO ALTERNATE CYLINDER AVAILABLE

When marking or assigning alternate tracks, the following error messages may occur:

TRACK HAS ALREADY BEEN MARKED

DEFECTIVE

TRACK HAS ALREADY BEEN MARKED

ALTERNATE

Selected Read

For this test, the display will be:

READ DMO? (Y OR N)?

If the response is No, the next logical unit will be displayed. If the response is Yes, the current cylinder address is displayed and each cylinder is read. If an error is detected, the register contents and location are displayed with the 4-line identificationmessage. The ASSIGN ALTERNATE TRACK message appears, and error messages if the track has been marked DEFECTIVE or ALTERNATE.

Random Seek, Read

For this test, the display will be:

RANDOM SEEK, READ OF DRIVE (ALL

CYLINDERS AND HEADS)?

This test selects a random cylinder, logical unit, and a sector address within the cylinder. The test then reads data and tests for errors. All logical units are used in this test. Alternate cylinders cannot be assigned during this test. The terminal keyboard space (SP) character is used to exit this test.

If an error is detected, the register content and locations are displayed with the 4-line identification message.

This check also ensures controller mapping is correct. The desired address and the actual address will be displayed with the drive's physical characteristics. .

Random Seek, Write Data, Read Data, Compare

Test

If the response is No, each logical unit will appear in sequence until the response is Yes:

DMO?

DM1?

DM2?

DM3?

This test selects a random cylinder address and random sector address and writes five sectors (2560 bytes) of random data. The data written is then read into CPU memory and compared for read errors.

This test allows logical units to be tested. The terminal keyboard space character (SP) is used to exit from this test.

This test ensures that the controller is executing the write check command correctly and that the controller is zero-filling the disc correctly.

Assign Alternate Track

This test may be used if the disc drive manufacturer provides a map describing defective tracks.

The message is:

ASSIGN ALTERNATE TRACK FOR

DEFECTIVE TRACK (Y OR N)?

If the response is No, the program will revert to:

USE R TO REPEAT

3-13

USE 0 TO TRANSFER TO ODT

USE L TO REBOOT YOUR SYSTEM

If the response is Yes, the display will be:

PHYSICAL DRIVE (0 or 1)1

(only if two drives are present)

Enter the cylinder address, in decimal, of the defective track. If the cylinder address entered is incorrect, the message will be repeated.

The next message will be:

Enter the head address, in decimal, of the defective track. If the head address entered is incorrect, the message will be repeated.

The next message will be:

MAP OUT

CYLINDER - - - - HEAD - -

ARE YOU SURE (Y OR N)?

If No, the program will repeat the first message of this test. If Yes, an alternate cylinder is assigned and the message is:

ALTERNATE CYLINDER ASSIGNED

Other messages to appear may be:

TRACK ALREADY MARKED DEFECTIVE or

TRACK ALREADY MARKED ALTERNATE

The program will then repeat the first message of this test.

EPROM FORMAT PROGRAM

This program is a simple, fast method to format a disc. This program is not a substitute for DILOG's

Universal Firmware and Diagnostic Program which is a complete and extensive program for formatting the disc and testing the controller. The EPROM program does not permit changing the number or size of logical units, ECC test, or alternate track assignments. The EPROM does not support horizontal partitioning; for example, the Format program (FT) will not support a CMD-type drive.

Note

Check the switch settings and jumper locations listed previously before using the

EPROM Program.

Use the boot procedure and enter FT with < CR > .

The program will display:

NUMBER OF SECTORS >

3-14

NUMBER OF HEADS >

NUMBER OF CYLINDERS >

REMOVABLE MEDIA (Y OR N)1

Consult the disc drive manufacturer's specifications and enter the numbers in decimal. After the list questions and < CR >, the following menu will appear:

1 = INTERRUPT TEST

2 = RESTORE

3

= SECTOR TEST

.4

= DMA

5 = WRITE HEADERS

6 = READ HEADERS

7

=

WRITE DATA

8

= READ DATA (1)

<CR> ='ALL THE ABOVE

9 = READ DATA (2)

B = BOOTS

SELECT>

The above tests are selected by the numbers, or B

, or < CR >. The SECTOR TEST compares the sector pulses with Number of Sectors above. The READ

DATA

(1) test checks the mapping algorithm of the controller. READ DATA (2) tests only read data.

READ DATA

(1) verifies the test pattern, and

READ DATA (2) does not. If <CR>·ispressed, the first test to appear on the terminal will be WRIT-

ING HEADERS as the first four tests are completed very quickly.

To restore the program or for an unconditional escape to boot, enter Control C.

If an error occurs, all registers are listed on the terminal with entries such as· 11 SECTOR DIS-

CREPANCY 11 or DRIVE FAULT or DRIVE NOT

READY. The following is an error printout example:

RKSC1

RKWC

RKBA

RKDA

RKCS2

RKDS

RKER

RKAS/OF

RKDC

RKXMA

RKDB

RKMR1

RKECPS

RKECPT

RKMR2

RKMR3

= 177 440 (XXXXXX)

=

= 177 444 (XXXXXX)

= 177 446 (XXXXXX)

=

177 450 (XXXXXX)

= 177 452 (XXXXXX)

= 177 454 (XXXXXX)

=

177 456 (XXXXXX)

= 177 460 (XXXXXX)

=

= 177 464 (XXXXXX)

=

177 466 (XXXXXX)

= 177470 (XXXXXX)

=

177 442 (XXXXXX)

177 462 (XXXXXX)

177472 (XXXXXX)

=

177474 (XXXXXX)

= 177476 (XXXXXX)

Non-Existent Drive

Drive Fault

Drive Not Ready

Selected Unit Seek Error

Use (P) to Continue

i

SECTION 4

PROGRAMMING

PROGRAMMING DEFINITIONS

Function-The expected activity of the disc sys- , tern (write, seek, read, etc.)

Command-To initiate a function (halt, clear, go, etc.)

,

Instruction-One or more orders executed in a prescribed sequence that causes a function to be performed.

Address-The binary code placed in the BDALO-

15 lines by the bus master to select a register in a slave device .. Note memory other than computer internal memory, i.e., peripheral device registers, the upper 4K (28-32K) address space is used.

Register-An associated group of memory elements that react to a single address and store information (status, control, data) for use by other assemblies of the total computer system. Classically, registers have been made up of groups of flipflops. More and more often registers are the contents of addressed locations in solid-state or core memory.

DISC CONTROLLER FUNCTIONS

The disc controller performs 14 functions. A function is initiated by a GO command after the processor has issued a series of instructions that store function-control information into controller registers. To accept a command and perform a function, the controller must be properly addressed and the disc drive(s) must be powered up, be at operational speed, and be ready.

The functions performed by the controller are established by bits 01, 02, 03 and 04 of the control status register (RKCSl). The function and bit codings are given in Table 4-1. Descriptions of the functions are given in the following paragraphs.

Note that the controller automatically performs certain functions during each command. For example, the controller always performs the following steps:

1. Decodes instruction

2. Selects drive

3. Acknowledges pack (tests for RK06/RK07 drive type)

Bit

4321

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

4. Executes one of the remaining nine functions

Select Drive

Performed automatically as part of all functions related to drive selection (connects drive).

Pack Acknowledge

Performed automatically to verify emulation

(RK06/RK07) as part of all functions related to drive selection. Controls bit 08 in RKDS.

Drive Clear

Resets attention status in

RKAS/OF.

Recalibrate

Table 4-1. Function Codes

Command

SELECT DRIVE

PACK ACKNOWLEDGE

DRIVE CLEAR (RESET ATTENTION STATUS)

UNLOAD (NO OP)

START SPINDLE (NO OP)

RECALIBRATE (RESTORE DRIVE AND RESET

FAULT)

OFFSET

SEEK

READ DATA

WRITE DATA

READ HEADERS (1 TRACK OF HEADERS)

WRITE HEADERS (FORMAT TRACK)

WRITE CHECK

Relocates the heads to cylinder zero and clears the cylinder address register. Also resets all fault conditions. Sets attention bit in

RKAS/OF.

Offset

Sets drive attention bit in

RKAS/OF.

Seek

Performed automatically as part of all functions related to drive selection. Sets attention bit in

4-1

RKAS/OF.

During Overlapped Seeks, loads cylinder address into RKMR3 (Maintenance Register 3).

Read Data

Causes the following sequence to be executed: A

Seek to the cylinder in RKDC is performed. Headers are read and compared with the desired disc address until the correct sector is found. Transfer of data through the data buffer to memory is initiated.

When the sector data transfer is complete, the ECC logic is checked to ensure that the data read from the disc was error-free. If a data error occurred, the

ECC correction logic is initiated to determine whether the error is correctable; when finished, the command is terminated to allow software or hardware (as selected) to apply the correction information. Assuming no data errors, the word count. in

RKWC is checked; if non-zero, the data transfer operation is repeated into the next sector. The word count is checked at the end of each sector until it reaches zero, at which time the command is terminated by setting the Ready bit.

Write Data

Causes the following sequence to be executed: A

Seek to the cylinder in RKDC is performed. Transfer of data from memory to the data buffer is begun, and headers are read and compared with the desired disc address until the correct sector is found. Preamble, Data (256 words), and ECC bits (56) are written on the disc. If the word count in RKWC goes to zero during the sector, the rest of the sector is zero-filled. After the sector transfer, the word count is RKWC is checked and, if non-zero, the data transfer operation is continued into the next sector.

The word count in RKWC is checked at the end of each sector and, when it equals zero, the command is terminated by setting the Ready bit.

Read Headers

A Seek to the cylinder in RKDC is performed.

This function causes the controller to read all headers starting at the Index mark. Each 5-word header is read in the order in which it appears on the disc. If an ECC error is detected in the header, the

HRE bit of RKER is set.

Write Headers

A Seek to the cylinder in RKDC is performed. The controller then waits until Index is detected. When detected, zeros are written until Index is again detected. This "cleans" the track of potential spurious signals. After Index is detected a second

4-2 time, 5 header words and a 32-bit ECC are written after each sector pulse. When Index is next detected, the command is terminated and the Ready bit is set.

Note

All five words and the ECC code are prepared by the format routine (software) and treated as data by the controller. Only one complete track can be formatted at a time.

Write Check

Causes the following sequence to be executed: A

Seek to the cylinder in RKDC is performed. The selected drive provides data as in a Read command, and data is obtained from memory as in a Write command. The data are compared on a word-forword basis until the word count reaches zero or until a failure to compare occurs. If the data fails to compare, the command is terminated immediately.

Mapping and Map Override

In a typical DEC disc s\lbsystem, the method by which the disc drive finds the proper location to read data from or write data to is as follows:

1.

The application software program running under the operating system sends a record number to the disc device driver software.

2. The device driver converts this record number into head, sector and cylinder numbers.

3. The driver then sends this information to dedicated hardware registers on the disc controller.

4. The controller in turn passes these parameters on to the disc drive over I/O interface cables.

5. The drive interprets these signals and activates electronics and electromechanics enabling it to seek to the exact physicallocation where information will be recorded or retrieved.

I

In a DEC subsystem which includes a DILOO controller, the above procedure is the same up to step 4. But instead of passing on the head, sector and cylinder information to the drive, the DILOO controller first takes that information sent by the device driver software and reconverts it to the original record number. Then by invoking a special algorithm, the controller develops a new head, sector and cylinder number. This i~ called mapping

and it is a necessary procedure whenever the disc drive that is attached to the CPU does not contain the same specifications as the drive supplied by the

CPU manufacturer.

Map Override is nothing more than a special operating mode of the DILOG disc controller which allows it to transfer the disc address to the drive as described in steps 1-5, bypassing the DILOG mapping procedure. Typically, this feature is only used in an environment in which the user requires the entire disc drive to be formatted as one large logical unit. In other words, one logical unit would equal one physical unit. For example, consider a subsystem consisting of a DQ215 and a Fujitsu

Eagle 474 Mbyte drive. Obviously, the controller is not a good match for a drive that large, considering that one RK07 logical unit equals 27.6 Mbytes. If, however, the user had a definite requirement for running an RK07 instruction set, he could invoke

Map Override and format the Eagle as one very large RK07. One requirement is that the device driver software has to be modified.

ENABLE REAL TIME CLOCK CONTROL

The real time clock line is from the 60-cycle power supply in the LSI. The Operating System uses the clock for time and date. The line on the Q Bus,

BEVNT, can be disabled by a switch on the controller, which when ON enables real time clock control or when OFF disables control. The register, address 777 546, is shown at the end of this section.

REGISTERS

A summary of the registers is shown in Figure 4-1, followed by a description of each register. r;

4-3

BIT POSITION

CONTROL AND STATUS 1

777440(RKCS1)

MSB

1

15

I

14 13 12 11 10 09 08

07 06 05 04 03 02 01 lSB

I

00

I

FUNCTION

WORD COUNT

WORD COUNT

777 442 (RKWC)

BUS ADDRESS

BUS ADDRESS

777444 (RKBA)

HEAD ADDRESS

SECTOR ADDRESS

DISC ADDRESS

777 446 (RKDA)

CONTROL AND STATUS 2

777 450 (RKCS2)

DRIVE STATUS

777452 (RKDS)

0 IweEI o INEDINEMI PE IMDSI 0

0 1

I

SCl IIBA

I

0

OS

I I sc

I

PIP

I

0

I wp

I

SPARES

I

~~ lOR

I

OS

I

SE

I

0

I

OF

I o

I

0

I

]

ERROR REGISTER

777 454 (RKER)

NOT USED

I

ON

I

OP

I

NOT USED ATTENTION SUMMARY AND

OFFSET 777 456 (RKAS/OF)

ATTENTION

CYLINDER ADDRESS

DESIRED CYLINDER

ADDRESS 777 460 (RKDC)

EXTENDED MEMORY

ADDRESS 777 462 (RKXMA)

READ/WRITE BUFFER

777 464 (RKDB)

NOT USED

DATA BUFFER

BITS 16·21

NOT USED FIRMWARE

MODEL

MAINTENANCE 1

777466 (RKMR1)

ECC POSITION

777 470 (RKECPS)

ECC PATTERN

777472 (RKECPT)

MAl NTENANCE 2

777474 (RKMR2)

MAl NTENANCE 3

777476 (RKMR3)

NOT USED

NOT USED

HEAD MAPPED

NOT USED

ERROR POSITION

ERROR PATTERN

SECTOR MAPPED

CYLINDER MAPPED

I

ENABLE REAL TIME CLOCK

CONTROL 777 546 (RKERTC) fERTCI

Figure 4·1. Controller Register Configuration

4·4

CONTROL AND STATUS REGISTER 1

777 440 (RKCSl)

01 00

15 14 13 12 11

10

09 08 07 06 05

04

ERR

RST

01 0

GAP TO

061

07

X MEM

CR IE 0 FUNCTION GO

-- SPARE-ALWAYS 0

-INTERRUPT ENABLE

-CONTROLLER READY

EXTENDED MEMORY (16-17)

..... RK06/RK07 (1

=

RK07)

---OPERATION TIME OUT

LONG/SHORT GAP

"- FMTIDATA COMMANDS

---SPARE-ALWAYS 0

--DRIVE INTERRUPT

...... COMBINED ERROR/RESET

( ,

I

GO

BIT(S) DEFINITION

00 GO-When set this bit causes programmed commands (function codes) to be executed. When set, only two other bits can be set (except in the diagnostic mode); they ~re: Bit 15, CCLR, in RKCS1 and Bit 05, SCLR, in RKCS2.

01-04 FUNCTION CODE-

BIT

4321

O(GO)

OCTAL COMMAND

05

06

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1

1

1

1

1

1

1

1

1

1

1

1

1

21

23

25

27

31

11

13

15

17

01

03

05

07

SELECT DRIVE

PACK ACKNOWLEDGE

DRIVE CLEAR (RESET DRIVE FAULT)

UNLOAD (NO OPERATION)

START SPINDLE

RECALIBRATE (RESTORE DRIVE AND RESET FAULT)

OFFSET

SEEK (NO OPERATION)

READ DATA

WRITE DATA

READ HEADERS

(1

TRACK OF HEADERS)

WRITE HEADERS (FORMAT TRACK)

WRITE CHECK

SPARE-ALWAYS 0

INTERRUPT ENABLE-When this bit is set, the controller is allowed tointerrupt the processor under any of the following conditions:

• .When the Controller Ready bit (bit 07 in RKCS1) is set upon completion of a command.

• When any drive sets an associated Attention flag (ATN7-ATNO) inRKAS/OF, and the Controller

Ready bit is set.

• When the controller or any drive indicates the presence of an error by setting the ERR/RST bit in

RKCSl.

4-5

07

In addition, via program control, an interrupt can be forced by· the simultaneous setting of the IE and RDY bits in RKCSI. The IE bit can be reset via program control as well as by conventional initialization (lNIT, CCLR, SCLR).

CONTROLLER READY -This is a read-only bit. It is set via conventional initialization (lNIT,

CCLR, SCLR) upon completion of a controller command, or when an error condition is detected. The

RDY bit is reset when the GO bit (bit 00 in RKCS1) is set.

08-09 EXTENDED BUS ADDRESS-These bits constitute an extension of the 16-bit Bus Address register (RKBA), which contains the memory address for the current data transfer.

RK06/RK07 SELECT-When set this bit selects RK07. When reset, RK06 is selected. 10

11 OPERATION TIME OUT-When set, this read-only bit indicates that the GO bit has been set for a specified time period and the current command has not been executed within that time period.

*12

13

14

GAP CONTROL-In the Write Header command (or write format) bit 12 will direct the controller to generate a long gap (24 bytes) or a short gap (16 bytes) between sector and header.

Bit 12 1 o

=

Short Gap

=

Long Gap

In the Write·Data or Read Data command bit 12 will direct the controller to Write or Read a sector data field (512 bytes) with or without ECC (7 bytes) to or from memory.

Bit 12 1

=

512 Bytes

DATA

+

7 Bytes

ECC o

=

512 Bytes

SPARE-ALWAYS 0

DRIVE INTERRUPT ENABLE (SEEK OR RESTORE)-This bit is set during a Seek or Restore operation or when any attention bit is set in the RKAS/OF register. The bit is reset by Bus Initialize

(lNIT), Subsystem Clear (SCLR) or by Drive Clear commands asserting attention.

15 COMBINED ERROR/RESET-When reading bit 15 via programmed control, a zero indicates an operation complete with good status; a one indicates an operation complete with an error.

*NOTE: When bit 12 is set, the Word Count Register should be set for 520 bytes.

WORD COUNT REGISTER

777442 (RKWC)

15

WORD COUNT

00

I

This is a ReadlWrite register. The bits of this register contain the 2's complement of the total number of words to be transferred during a Read,

Write, or Write Check operation. The register is incremented by one after each transfer. When the

4-6 register overflows

(all

WC bits go to zero), the transfer is complete and controller action is terminated at end of the present disc sector. Only the number of words specified in the RKWC are transferred. Cleared by INIT or RESET functions.

BUS ADDRESS REGISTER

777 444 (RKBA)

15

BUS ADDRESS

The Bus Address Register is initially loaded with the low-order sixteen bits of the bus address that reflects the main memory start location for a data transfer. With the low-order bit (bit 00) always forced to zero, the Bus Address Register bits are

00 combined with bits 09 and 08 of the RKSCI register

(BAI7, BAI6) to form a complete even-numbered,

18-bit memory address. Following each data transfer bus cycle, the Bus Address Register is incremented to select the next even-numbered location.

DISC ADDRESS (TRACK AND SECTOR) REGISTER

777 446 (RKDA)

15

08 07

HEAD ADDRESS SECTOR ADDRESS

00

BIT(S) DEFINITION

00-04

(00-07)

08-10

(08-15)

SECTOR ADDRESS-In the emulation mode, bits 00-04 select up to 20 sectors of 16-bit words. In the map override mode, bits 15, 14, 13, 12, in the Desired Cylinder Register 777460, are set to 1000, respectively. The Sector Address then uses bits 00-07.

HEAD (TRACK) ADDRESS-hi the emulator mode, bits 08-10 select heads 0, 1,2. In the map override mode, bits 15, 14, 13, 12 and in the Desired Cylinder Address Register 777 460, are set to 1,

0, 0 and 0, respectively. The Head (TRACK) Address then uses bits 08-15.

4-7

CONTROL AND STATUS REGISTER 2

777450 (RKCS2)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 00

OUTPUT READY (ALWAYS 0)

SPARE-ALWAYS 0

MULTIPLE DRIVES SELECTED

PROGRAM ERROR

NONEXISTENT MEMORY

NONEXISTENT DRIVE

SPARE-ALWAYS 0

WRITE CHECK ERROR

SPARE-ALWAYS 0

DRIVE SELECT

SPARE-ALWAYS 0

INHIBIT BUS ADDRESS

SYSTEM CLEAR

INPUT READY (ALWAYS 1)

BIT(S) DEFINITION

00-02 DRIVE SELECT-These bits specify the drive to be selected.

03

04

SPARE-ALWAYS 0

INHIBIT BUS ADDRESS INCREMENT-When this bit is set, the Bus Address register is prevented from incrementing during data transfers.

05

06

07

08

*09

*10

*11

*12

*13

*14

SYSTEM CLEAR-When this bit is set the controller and drive are reset.

INPUT READY-ALWAYS 1

OUTPUT READY-ALWAYS 0

SPARE-ALWAYS 0

MULTIPLE DRIVES SELECTED-This bit is set when more than one drive has been selected at the same time. This bit can only be cleared by INIT or SCLR.

PROGRAM ERROR-This read-only error bit is set if any controller register is written (CCLR and

SCLR excluded) while the GO bit in RKCSI is set.

NONEXISTENT MEMORY -This read-only error bit is set when the controller attempts to execute a bus cycle and SSYN is not returned within the specified time period.

NONEXISTENT DRIVE-When set, this read-only error bit indicates that Select Acknowledge

(SACK) has not been asserted by the selected drive in response to a Select Enable sent to the drive.

SPARE-ALWAYS 0

WRITE CHECK ERROR-When set, this read-only bit indicates that a data word read from the disc (during a Write Check command) did not compare with the data word in main memory. If a

Write Check error is detected and the IBA bit (bit 04 of RKCS2) is cleared, the Bus Address register will contain the memory address of the mis-matched word plus two or plus four.

15 SPARE-ALWAYS 0

*Causes bit 15 in RKCSI to set.

4-8

DRIVE STATUS REGISTER

777 452 (RKDS) Read Only Register

15

~

13 12 11 10

09100

07

04

1 SC PIP 0 WP SPARES

061

DR OS SE 0 OF 0

07

01 00 o

" - SPARE-ALWAYS 0

" - SEEK ERROR

I . -

DRIVE SELECT

I - DRIVE READY

I . -

RK06/RK07

[

LSPARE-ALWAYS 1

SPARE-ALWAYS 0

SPARE-ALWAYS 0

"-DRIVE FAULT

'-WRITE PROTECT

I-SPARE-ALWAYS 0

' - SEEK COMPLETE

'-SPARE-ALWAYS 1

BIT(S) DESCRIPTION

00 SPARE-ALWAYS 1

01

02

03

04

05

SPARE-ALWAYS 0

SPARE-ALWAYS 0

DRIVE FAULT-When set, indicates an error condition is detected within the drive and is prohibiting all operations. This bit is reset manually by clearing the fault condition within the drive.

SPARE-ALWAYS 0

SEEK ERROR-When set, indicates a seek was not completed within a specified time period after it was initiated. .

06 DRIVE SELECTED-When set, the drive is selected and on line.

07 DRIVE READY -Drive Ready is a read-only bit which when set indicates the selected drive is up to speed, the heads are on cylinder and the drive is ready to accept commands. It is reset when these conditions are not met or when driving is seeking.

RK06/RK07 - When set indicates RK07, when reset, RK06. 08

09-10 SPARES-ALWAYS 0

11 WRITE

PROTECT~

12

13

SPARE-ALWAYS 0

POSITIONING IN PROGRESS-When set, the selected disc is write protected.

14

15

SEEK INCOMPLETE-This read-only bit sets when the drive is ON CYLINDER. SEEK or

RESTORE is completed.

ALWAYS 1

4-9

ERROR REGISTER

777 454 (RKER)

13 12 11 10 09 08 07 06 05 04 03

WPE ID COE HRE BSE HEC DTE FE 0

AE

ILLEGAL FUNCTION

SEEK INCOMPLETE

SPARE-ALWAYS 0

SPARE-ALWAYS 0

FORMAT ERROR

DRIVE TYPE ERROR

HARD ECC ERROR

BAD SECTOR ERROR

HEADER READ ERROR

CYLINDER OVERFLOW ERROR

INVALID DISC ADDRESS ERROR .

WRITE PROTECT ERROR

SPARE-ALWAYS 0

OPERATION INCOMPLETE

DRIVE UNSAFE

DATA CHECK

02

M

04

BIT(S) DEFINITION

00 ILLEGAL FUNCTION-When set, this read-only bit indicates that an illegal command has been loaded into the RKCSI register.

01

05

06

07

08

09

10

SEEK INCOMPLETE-When set, this read-only bit indicates that a seek operation has not been completed by the selected drive.

SPARE-ALWAYS 0

SPARE-ALWAYS 0

FORMAT ERROR-When set in conjunction with bit 09, indicates that the sector pulses are too close together. Diagnostic message is "sector size too small."

DRIVE TYPE ERROR-This read-only bit is set when the drive type status does not compare with

Control Drive Type bit (RKCSl, bit 10), i.e., RK06 instead of RK07 or vice versa.

HARD ECC ERROR-When set, this read-only bit indicates that a data error detected by the ECC logic cannot be corrected using ECC.

BAD SECTOR ERROR-When set, this read-only bit indicates that a data transfer was attempted to or from a sector and the sector is bad.

HEADER READ ERROR-When set, this read-only bit indicates that an uncorrectable ECC error was detected on a sector header during a data transfer. If bit 13 is also set, the error indication is header not found.

CYLINDER OVERFLOW ERROR-When set, the word count is not equal to zero and the operation is programmed to continue beyond the last logical sector on the disc. This will occur on a

Read or Write data operation.

INVALID DISC ADDRESS ERROR-When set, this bit indicates that an invalid cylinder address or an invalid head address has ,been detected during a Seek command or Write/Read data command.

4-10

11

12

13

14

15

WRITE PROTECT ERROR-When set, this read-only bit indicates that the drive received assertion of Write Gate while in the write protect mode.

SPARE-ALWAYS 0

OPERATION INCOMPLETE-When set, this read-only bit indicates that during a data transfer, the desired header could not be found .. This error can result from anyone of the following:

• Head Misposition

• Incorrect Head Selection

• Read Channel Failure

• Improper Pack Formatting

DRIVE UNSAFE-When set, this read-only bit indicates that a Read/Write Unsafe condition has been detected.

J

DATA CHECK-When set, this read-only bit indicates that a data error was detected when the current sector was read.

ATTENTION SUMMARY AND OFFSET REGISTER

777 456 (RKAS/OF)

15

ATTENTION

08 07

NOT USED

05 04 03

I

ON

I

OP

I

02

NOT USED

00

BIT(S) DEFINITION

00-02 SPARE-ALWAYS 0

03 OFFSET POSITIVE-Offsets the head in the positive direction from the centerline of the track

(positive is from the lower cylinder number toward the higher cylinder number).

04

05-07

08-15

OFFSET NEGATIVE-Offsets the head in the negative direction from the centerline of the track

(negative is from the higher cylinder number toward the lower cylinder number).

SPARE-ALWAYS 0

ATTENTION-The eight Attention bits, one for each drive, correspond to the logical unit number of each drive. Each bit indicates the state of the Drive Status Change flip-flop in the corresponding drive. All of the A TN bits are continuously scanned and updated (polled).

4-11

DESIRED CYLINDER ADDRESS REGISTER

777 460 (RKDC)

15 12 11 10 09

DIAGNOSTIC MODE' CYLINDER ADDRESS

00

BIT(S) DEFINITION

00-09 CYLINDER ADDRESS-The cylinder address in RKDC is the emulated address. The actual mapped address is contained in RKMR2. The cylinder number is written in octal in the register.

10-11 SPARE-ALWAYS 0

12-15 DIAGNOSTIC MODE-These bits are as follows:

15 14 13 12

0 0 0 0 RK06/RK07 Emulation Mode

1 0 0 0 MAP OVERRIDE MODE-These bits can be set by the programmer to override the mapping algorithm. When set, the head, cylinder, and sector addresses supplied to the controller specify absolute address to the disc. Could be typically used to permit the device handler to be modified to take advantage of the head per track options available in some disc drives.

1 1 0 0 DMA BUFFER TEST MODE-Allows Reading/Writing of the controller data buffer using the computer DMA interface. The controller word count and memory address registers are used to set up the DMA transfer with a maximum transfer of

1024 bytes starting with location 0 of the data buffer. The write command, write from the buffer. The read command, 21

H

,

23

will read from the data buffer.

R

,

will

1 1 1 0 ECC TEST MODE

1

1 0 1 110 BUS INTERFACE TEST MODE

1 1 1 1 110

W/R

INTERFACE TEST MODE

EXTENDED MEMORY ADDRESS REGISTER (22-Bit)

777 462 (RKXMA)

15 14 13 12 11 10 09 06 05 00

BITS 16·21 l

SPARE-ALWAYS 0

SPARE-ALWAYS 0

EXTENDED MEMORY FLAG BITS

SPARE-ALWAYS 0

EXTENDED MEMORY FLAG BITS

BIT(S) DEFINITION

00-05 BITS 16-21- These bits, when set, define bits 16-21 of the 22-bit extended memory.

06-09 SPARE-ALWAYS 0

10, 13 EXTENDED MEMORY -When bits 10 and 13 are set, the 22-bit address is used.

11-12,

14-15 SPARE-ALWAYS 0

4-12

READIWRITE BUFFER REGISTER

777464 (RKDB)

15

DATA BUFFER

00

BIT(S) DEFINITION

00-15 The Data Buffer Register is a Read/Write register. Writing into the register loads data into the controller data buffer, one word at,a time. Reading the register reads data from the controller data buffer. The commands INIT, CLL and SRC clears the Data Buffer address allowing writing or reading of the Data Buffer starting at location o.

Reading from or writing into the buffer will increment the address register.

MAINTENANCE REGISTER 1

777466

02 00

NOT USED

[ FIRMWARE MODEL

BIT(S) DEFINITION

00-02

03-15

FIRMW ARE MODEL-These three bits define the model number of the firmware used in the controller.

SPARE-ALWAYS 0

ECC POSITION REGISTER

777 470 (RKECPS)

15 14 13 12

NOT USED ERROR POSITION

00

BIT(S) DEFINITION

00-12 ERROR POSITION-These read-only bits define the start location of an error burst (containing from one to eleven error bits) within a 256-word data field, sequence. The position is valid if the error is ECC correctable.

13-15 SPARE-ALWAYS 0

4·13

ECC PATTERN REGISTER

777 472 (RKECPT)

15

11 10

NOT USED ERROR PATTERN

00

BIT(S) DEFINITION

00-10 ERROR PATTERN-These are read-only bits that provide an II-bit correction pattern for an error burst that does not exceed 11 error bits in length and is therefore ECC correctable.

11-15 SPARE-ALWAYS 0

MAINTENANCE REGISTER 2

777 474 (RKMR2)

15

HEAD MAPPED

08 07

00

SECTOR MAPPED

BIT(S) DEFINITION

00-07 SECTOR MAPPED-These bits define the actual mapped sector address in the disc as opposed to the emulated address.

08-15 HEAD MAPPED-These bits define the actual mapped head address on the disc as opposed to the emulated address.

MAINTENANCE REGISTER 3

777476

15 11 10

NOT USED

00

CYLINDER MAPPED

BIT(S) DEFINITION

00-10 CYLINDER MAPPED-These bits define the actual mapped cylinder address on the disc as opposed to the emulated address.

11-15 SPARE-ALWAYS 0

ENABLE REAL TIME CLOCK CONTROL REGISTER

777546

15

NOT USED

00 07 06 05

I

ERTel NOT USED

[ ENABLE REAL TIME CLOCK CONTROL

The Enable Real Time Clock Control register performs a separate function from the other registers. During a read operation, bit 06 is always

4-14 reset. During a write operation bit 06 is set enabling the real time clock control. Switch S9 must be ON to enable this function.

SECTION 5

TROUBLESHOOTING AND THEORY

This section describes troubleshooting procedures at three levels of complexity: basic system, controller symptoms and detailed analysis. Basic system troubleshooting procedures are visual checks not requiring test equipment and may be performed by the operator. Controller symptom procedures may require a scope, meter, extender board or diagnostics and should be performed by a technician.

Detailed analysis is troubleshooting at the IC level, and is presented for engineers or system analysts for controller evaluation. The latter method may require the use of test equipment and the material presented here: board layout, term listing, theory of operation and logic diagrams.

CAUTION

Any troubleshooting requires a familiarity with the installation· and operation procedures in this manual, the appropriate DEC manual, and the disc drive manufacturers manual. Ensure power is off when connecting or disconnecting board or plugs.

BASIC SYSTEM TROUBLESHOOTING

The following should be checked before power is applied:

1. Verify that all signal and power cables are properly connected. Ribbon cable connectors are

not keyed. The arrows on the connectors should be properly aligned.

2. Verify that all switches are properly set as described in Sections 2 and 3.

3.

Verify that all modules are properly seated in the computer and properly oriented.

The following should be checked during or after application of power:

1. Verify that the computer and disc drive generate the proper responses when the system is powered up.

2. Verify that the computer panel switches are set correctly.

3. Verify that the console can be operated in the local . mode. If not, the console may be

4. defective.

With the drive power switch on, verify that the drive READY light is on.

5. Verify that the green diagnostic light on the controller is on.

CONTROLLER SYMPTOMS

Controller symptoms, possible causes and checks/ corrective action are described in Table 5-1. Voltage checks should be performed before troubleshooting more complex problems. The +12V and -5V sources are shown on Logic Diagram Sheet 20. The

+5V source may be checked from any component shown on the other logic diagrams.

PHYSICAL LAYOUT

The physical layout of the board is shown in Figure 5-1. Column and row numbers on the layout correspond to the numbers on each IC on the logic diagrams.

TERM LISTING

The input and output terms for each logic diagram are described in Table 5-2. The sources and destinations refer to the sheet numbers on the logic diagrams.

5-1

Table s.;1. Controller Symptoms

Symptom Possible Causes

Check/Corrective Action

1. Green DIAG light on the 1. Microprocessor section of con-

1. Controller/Place controller on extender controller Is OFF. troller inoperative: board. With a scope, check the pins on a. Bad oscillator the 2901. All pins except ppwer and ground should be switching. Check for b. Short or open on board c. Bad IC d. PROMs not properly seated

"stuck high" or "stuck low," or half-amplitude pulses. Check and

+

12V and - 5V power

+

5V at various IC's. Check PROMs

A 1. through A7 for proper seating. Check oscillator.

2. No communication be-

2. I/O section of controller "hang2. Computer interface logic of controllerl tween console and ing" a

Bus: computer. a. DEN always low a. Check signal DEN for constant b. Shorted bus transceiver IC. c. Bad CPU board. assertion. b. Check I/O IC's. Remove controller board to see if trouble goes away.

(Ensure slot is filled or jumpered.) c. Run CPU diagnostics.

3. No data transfers to/ from disc.

3. Disc not ready, bad connectlon, or bad IC In register sectlon of the controller.

3. Disc/Consult the disc manufacturer's manual for proper setting of disc switches, or READY, NO FAULT, or UN-

SAFE lights. Check cable connections.

Controller Registers/Using ODT, examine the Drive Status Register. The DISC

READY and SELECTED must be "one's."

Using ODT, deposit !lones" and !lzeros" in the remaining disc registers and verify proper register data.

4. Data transferred to/from 4. Multiple Causes: from disc incorrect. a. Bad memory in backplane b. Noise or intermittent source of DC power in computer. c. Bad IC in disc I/O section of controller.

4. Computer-controller-disc/ a. Run memory diagnostics. b. Check AC and DC power. d. Bad area on disc. e. Disc heads not properly aligned. c. While operating, check lines from controller to disc with a scope for short or open. d. Run the Format and Diagnostic Test program (Section 3). If errors occur at the same place on the disc, it is probably a bad area on the disc. Assign alternate tracks as specified in Section

3. e. Consult disc dr.ive manufacturer's manual and align heads.

5. Intermittent failure-

Controller runs for a short time after power is applied and then fails.

5. Failure of heat sense component on. controller.

5. Isolate the bad component by using heat and cooling methods (heat gun, freon spray) and replace the bad component.

5-2

Figure

5-1.

Board Layout

Term

AMF

BAOO-BA09+

BBS7L

BBS7+

BC4+

BDALOOL

BDAL01L

BDAL02L

BDAL03L

BDAL04L

BDAL05L

BDAL06L

BDAL07L

BDAL08L

BDAL09L

BDAL10L

BDAL 11L

BDAL12L

BDAL13L

BDAL14L

BDAL15L

BDAL16L

BDAL17L

BDAL18L

BDAl19L

BDAL20L

BDAL21L

BDINL

BDIN+

BDMGIL

BDGOL

BDMRL

BDOUTL

BDOUT+

BEVENT

BFULE+

BFULL-

BIAKIL

BIAKOL

BINITL

BIRQ4L

BIRQ5L

BIRQ6L

BIRQ7L

BITO-BIT10

BIT7+,-

BPOK-H

BPOK-

BRPLYL

BRPLY+

BSACKL

BSYNCL

BTSPF+

BWTBTL

BWTBT+

BYTCK+

COUT+

CP1

CP2

CP3

CP4

Table 5·2. Term Listing

Origin Description

17 Address Mark Found From

Disc

15 Buffer Address Counter Bits

00-09

BUS (AP2) Bus Peripheral Address Select

4 Peripheral Address ·Select

13

Bit Count 4 From Bit Counter

BUS (AW2) Bus Data/Address Line 00

BUS (AV2) Bus Data/Address Line 01

BUS (BE2) Bus Data/Address Line 02

BUS (BF2) Bus Data/Address Line 03

BUS (BH2) Bus Data/Address Line 04

BUS (BI2) Bus Data/Address Line 05

BUS (BK2) Bus Data/Address Line 06

BUS (BL2) Bus Data/Address Line 07

BUS (BM2) Bus Data/Address Line 08

BUS (BN2) Bus Data/Address Line 09

BUS (BP2) Bus Data/Address Line 10

BUS (BR2) Bus Data/Address Line 11

BUS (BS2) Bus Data/Address Line 12

BUS (BT2) Bus Data/Address line 13

BUS (BU2) Bus Data/Address Une 14

BUS (BY2) Bus Data/Address Line 15

BUS (AC1) Bus Address Extension Line

16

BUS (AD1) Bus Address Extension Line

17

BUS (BC1) Bus Address Extension Line

18

BUS (BD1) Bus Address Extension Line

19

BUS (BE1) Bus Address Extension Line

20

BUS (BF1) Bus Address Extension Line

21

BUS (AH2) Bus Data In

4 Data In

BUS (AR2) Bus DMA Grant In

BUS (AS2) Bus DMA Grant Out

BUS (AN1) Bus DMA Request

BUS (AE2) Bus Data Out

4 Data Out

BUS (BR1) Real Time Clock Control

3 Enable Buffer Full

15 Buffer Full

BUS (AM2) Bus Interrupt Acknowledge In

BUS (AN2) Bus I nterrupt Acknowledge

Out

BUS (AT2) Bus Initialize-Clear

BUS (AL2) Bus Interrupt Request Level 4

BUS (AA1) Bus Interrupt Request Level 5

BUS (AB1) Bus Interrupt Request Level 6

BUS (BP1) Bus Interrupt Request Level 7

16 Control Bits to Disc Drives

13 "Complete Byte" Output of

Bit Counter

BUS (BB1) Primary Power O.K.

4 Primary Power O.K.

BUS (AF2) Q Bus Reply

4 Q Bus Reply

BUS (BN1) DMA Select Acknowledge

BUS (AJ2) Bus Synchronize I/O

2 Bootstrap Flag

BUS (AK2) Bus Write Byte

4 Bus Write Byte

13 Byte Clock

10 Carry Out

12 Control Pulse 1

12 Control Pulse 2

12 Control Pulse 3

12 Control Pulse 4

5-4

Table 5·2. Term Listing (Continued)

Term Origin

Description t-

CP5

CP6

CP7

CRCER+

CR1-0/7

CR2-0/7

CR3-0/7

CR4-0/7

·CR5-0/7

CR6-0/7

CSAO + ICSA9 +

DA16+

OA17+

DATO+/DAT7+

DBWC1 +

DBWS-

DBWS1-

DBOO +

IDB07 +

DB08+/DB15+

DEN-

DMGI+

000+1007+

EADD+

EADD-

EBITC+

ECCO+

EDATA+

ENRD-

ENWD-

FAULT

GOATA+

GSCLK-

GTIRQ+

IAKI+

IAKIG-

INDEX

INIT+

LXRO-

LXR1-

LXR2-

LXR3-

LXR4-

LXR5-

LXR6-

LXR7-

LXR9-

LXRA-

LXRB-

LXRC-

LXRDlXRE-

12 Control Pulse 5

12 Control Pulse 6

12 Control Pulse 7

13 Cyclic Redundancy Check

Error

9 Control Register One Bits 0-7

9 Control Register Two Bits 0-7

9 Control Register Three Bits 0-7

9 Control Register Four Bits 0-7

9 Control Register Five Bits 0-7

9 Control Register Six Bits 0-7

8 Control Store Address Bits 0-9

3 Extended Data/Address Bit 16

3 Extended Data/Address Bit 17

14,15 Data Buffer Bits 0-7

13 Data Buffer Write Control In

13 Data Buffer Write Strobe

13

Data Buffer Write Strobe In

6 Data Bus Bits 0-7

7 Data Bus Bits 8-15

6 Data Enable

4 DMA Grant In

2,3,4,9,11, D-Bus Bits 0-7

12,14,17,

18,19

3 Enable Address

6 Enable Address

3 Enable Bit Count

19 Error Correction Code Out

3 E'nable Data

13 Enable Read Data Register

13 Enable Write Data To Buffer

17 Drive Fault

13 Gated Read Data

3 Gated System Clock

5 Gated Transmit Interrupt

Request

4 Interrupt Acknowledge In

2 Interrupt Acknowledge In

Grant

17 Index Pulse From Drive

4 Initialize

11 Load External Register Data

Out MSB

11 Load External Register Data

Out LSB

11 Load External Register DMA

Address MSB

11

Load External Register DMA

Address LSB

11

Load External Register Data

Buffer LSB

11 Load External Register Data

Buffer MSB

11 Load External Register Data

Buffer

11 Load External Register

Extended Address

11 Load External Register Drive

Control Tags

11

Load External Register Drive

Control Bus Bits

11 Load External Register Vector

Address

11 Load External Register

System Control

11 Load External Register

Bootstrap Address

11 Load External Register CPU

Bus Control

Table 5-2. Term Listing (Continued)

SELA/B

SENDA/B

SCLK

SCLOCKA/B

SDB08+

SEEKA/B

SEC+I-

SERR +/-

SLIIN +

TAG1/2/3

TDIN+

TDOUT+

TDMG+

TDMR+

TIAK+

TIRO+

TRPLY

TSACK

Term

LXRF-

MROB+

OCD+I-

ONCYL+I-

PICK

OBUSA

03

RAM3+

RCLOCKA/B +

1-

RDATAA/B +/-

RDATA+

REP

RESET

RMCLK

RSYNC-

R/WCK-

R/WSRE+

Origin

Description

11 Load External Register RAM

Destination

3 Memory Request

a

Bus

16 Open Cable Detect

17

On Cylinder From Drive

16 Power Pick

2

Q

Bus Access

10

a

Register Shift Line

10 Shift Output of ALU RAM

18 Read Clock From Drives A or

B

18 Read Data From Drives A or B

18 Read Data

19 Read Error Pattern

4 Reset Signal to Controller

3 RAM Clock

13 Read Synchronize

18 Read/Write Clock

3 Read/Write Shift Register

Enable

18 Drives A or B Selected

18

Drives A or B Seek End

3 System Clock

18 Servo Clock From Drives

2 Slave Data Bus Bit 8

18 Seek End From Drives

17 Sector Pulse From Drive

17 Seek Error From Drives

2 Slave Interrupt Acknowledge

Request

16 Tag Lines To Drives

3 Transmit Data In

3 Transmit Data Out

2 Transmit Direct Memory Grant

2 Transmit Direct Memory

Request

2 Transmit Interrupt

Acknowledge

3 Transmit Interrupt Request

3 Transmit Reply

2 Transmit Select Acknowledge

Table 5-2. Term Listing (Continued)

XSD3

XSD4

XSD5

XSD6

XSD7

XSD8

XSD9

XSDA

XSDB

XSDF

YOOIY07

ZERO+

1KOV+

Term

TSYNC

TWTBT

UNRDY

USELO/1/2/3

USELA/B

USTAG

VEC-

WDATA+

WCLOCKAIB + /-

WDATAA/B + /-

WPRT

WREN-

XSDO

XSD1

XSD2

Origin Description

3 Transmit Synchronize

3 Transmit Write Byte

17 Drive Unit Ready

16

Drive Unit Select Bits 0, 1, 2, 3

18 Drive Unit Select A, B

16 Drive Unit Select Tag

8 Vector Address Register

Select

14 Write Data Bit Stream

18 Write Clock To Drives A or B

18 Write Data To Drives A or B

17 Drive Write Protect

3 Write Enable

11 External Source Decode Slave

Address

11 External Source Decode Data

Input MSB

11 External Source Decode Data

Input LSB

11

External Source Decode CPU

Bus Status

11 External Source Decode Data

Buffer

11 External Source Decode Disc

Drive Status

11 External Source Decode Seek

End Status

11 External Source Decode Error

Status Register

11 External Source Decode

Bootstrap PROM.

11 External Source Decode

Configuration Switches

11 External Source Decode

Literal PROM

11 External Source Decode RK06

Switches

11 External Source Decode RAM

10 V-Bus Bits 0-7

10 Zero Output of 2901

15 1024 Address Couilter

Overflow

THEORY

The controller may be examined as three parts: computer interface, disc interface and controller internal functions. Signals from and to the computer are described in Section 1, Table 1-1. Signals from and to the disc drive are described in Tables 1-2 and 1-3. Figure 5-2 is a simplified block diagram illustrating the interfaces and some of the functional components. Single lines in the illustration represent serial data and the wider lines represent parallel data. A detailed block diagram of the controllers is shown on Sheet 1 of the logic drawings.

The numbers in the blocks on Sheet 1 refer to the sheet numbers of the other logic diagrams ...

Computer Interface

The purpose of the computer interface is to

(1) buffer lines between the Q Bus of the LSI-II computer and the controller, and

(2) to synchronize information transfers. The controller is a slave device during initialization and status-transfer sequences. The controller is selected by base address 777 440

8

,

The controller is bus master during data transfers and either receives data from or outputs data to the computer memory via the LSI-II DMA facility.

The control lines request information transfers, select the typ~ and direction of transfers, and synchronize the transfers. The control lines are. unidirectional and used for "bus arbitration." Bus synchronization is fully controlled by the controller microprocessor. This allows the computer bus to be used by other devices when the disc controller is busy with internal functions and controller/disc data transfers.

Data bus driver/receiver registers 13H through

I6H (Sheets 6 and 7) buffer the input data and distribute it as DB 00-15 in the controller. The DB

5-5

a:

.--

::l

0-

~ o

()

'-T

.-CONTROL

....

CONTROL

COMPUTER

INTERFACE

DATA

.....

<

DATA

...

CONTROL

TIMING

MICROPROCESSOR

DATA

-

...

')

<

DATA

PERIPHERAL

.....,.-

INTERFACE

CONTROL

TIMING

WRITE DATA

-

READ DATA

CONTROL

STATUS

...J

<t: a: w

I

0cr:

W

0o tsignals are routed to a data input MUX and address decode registers located on Sheets 12 and 2.

Output data and addresses from the microprocessor Y Bus (YOO-Y07) is latched by registers 13G through 16G, and transferred to the Q Bus via bus driver/receivers 13H through I6H.

Note that the Device Enable signal (DEN -) is active when either Address Enable (EADD) or Data

Enable (EDA T A) signal is active. DEN controls the operating mode of all data and address driver/ receivers, under control of the firmware, via the

Y Bus (Sheets 6 and 7).

Disc Interface

XSD5 - is active.

• DATA INPUT REGISTER

• DATA OUTPUT REGISTER

• ADDRESS DECODE DRIVER

• ADDRESS DRIVER

• BUS RECEIVER/DRIVER

• TIMING SOURCE

• CONTROL CENTER

• REGISTER STORAGE

• DATA BUFFERING

• SOURCE/DESTINATION DECODE

• BOOTSTRAP LOADER

Figure 5-2. Simplified Block Diagram

The disc is connected to the controller by separate data and control cables. A common control cable is daisy-chained to both drives in a multiple-drive configuration, while separate data cables are always used.

Serial read data is received by receivers 16C or

15C (Sheet IS) and then converted to parallel data by the read/write shift register 9D (Sheet 14). In the reverse direction, parallel data from the data buffer is converted to serial data by the shift register, then sent to data cable drivers (Sheet IS).

The Control Cable drivers 7B, SB, 9B and lOB

(Sheet 16) are always enabled and are driven by the output of registers 9C and 10C, which act as latches to capture the Y Bus data from the microprocessor.

Control Cable receivers lIB and 12B (Sheet 17) supply data to the disc status register/multiplexer

13C (Sheet 17) at all times. The data is available to the microprocessor via the

Controller Internal Functions

D Bus when signal

The microprocessor is the timing and control center of the controller. The microprocessor is con-

• DATA RECEIVER/DRIVER

• CONTROL DRIVER

• DRIVE STATUS RECEIVER

• ECC LOGIC. trolled by instructions stored in programmable read-only memory (PROM). The instructions, called

"firmware," cause the microprocessor to operate in a prescribed manner during each of the computerselected functions. The functions are established by a series of instructions issued by the LSI-II.

Because the disc and computer transfer data at different rates, it is necessary to buffer data going to and from the disc. High-speed RAM allows a full sector of data to be buffered during read and write operations. .

All data transfer and computer/disc protocol is under microprocessor control. This feature allows modification of controller operating characteristics by making only changes to the firmware. Input/output logic remains essentially unchanged.

The output from the microprocessor is the "Y

Bus". Y Bus instructions govern all controller operations by acting as the controller source for all receivers and drivers either directly or through the source/destinations decode IC's (Sheet 11).

The "D Bus" is the data input to the microprocessor. Tri-state drivers allow many signal sources to be connected to the bus while only one at a time is enabled by the source/destination decode logic on

Sheet 11.

The following list describes D Bus enabling signals:

Function

Component

Term Enabled Sheet

Slave Address

Data Input (MSB)

Data Input (LSB)

XSDO

XSDI

XSD2

16F

14F

15F

Q Bus Status

Data Buffer

Disc Status

Seek End/Unit Select

Error Status

Boot PROM

Switches

Literal

XSD3

XSD4

XSD5

XSD6

XSD7

XSD8

XSD9

XSDA

18F

8F

13C

14C

9F

12F

17F

7H

RK06 Switches

XSDB 21C

Scratch RAM Enable

XSDF 8H, 9H

11

3

9

5

12

2

12

12

12

14

17

18

19

5-6

All data on the D Bus is under control of the firmware as decoded by source PROMs 11H, 15D on

Sheet 11. The microprocessor selects the proper input data by enabling one of the above lines.

The Y Bus is the microprocessor output. Output of the microcode PROM 5H (Sheet 9) is decoded by

12H and 17H (Sheet 11) to select the destination of the data on the Y Bus.

The following list describes Y-Bus enabling signals:

Function

Component

Term

Enabled Sheet

Data Out Register

(MSB)

Data Out Register

(LSB)

DMA Address (MSB)

DMA Address (LSB)

LXRO

LXR1

LXR2

LXR3

13G

15G

14G

16G

Data Buffer Address

(LSB)

LXR4

Data Buffer Address

(MSB)

Data Buffer Load

LXR5

LXR6

Load Extended Address LXR7

11C,12D

12C

7C,8G

13D

Drive Control (Tags) LXR9

Drive Control (Bus 0-7) LXRA

Load Vector Address

System Control

External Event

Q

Bus Control

RAM Destination

LXRB

LXRC

LXRD

LXRE

10C

9C lOG

18G

22D

17G

LXRF 8H,9H

7

6

7

6

15

15, 19

13, 14

7

16

16

8

3

17

3

12

With the single exception of bus reply detector

21E (Sheet 3), all Y Bus data and address activity is controlled by the 15 signals shown above.

Each LXR (Load External Register) signal activates a register which, in conjunction with Y Bus data, latches the appropriate data word.

Control Registers CRI through CR6 are the outputs of the microcode PROMs (Sheet 9). These signals control the microprocessor functions and provide the data to the source/destination decode logic

(Sheet 11).

Data Buffer

The data buffer and associated logic are shown on

Sheets 13, 14 and 15. Data Transfers to and from the buffer are both two-step operations. First, an entire sector of data is loaded into the buffer during either a read or write operation. Once loaded, the buffer contents are then transferred to disc or

LSI -11 memory in a completely separate operation.

Figure 5-3 illustrates read and write operations to and from the RAM data buffer.

During a write operation, parallel data (YOO-Y07) is transferred from LSI-II memory via microprocessor to the write data register SG (Sheet 14). The data

(DATO-DAT7) is then transferred to the buffer 10D and lID (Sheet 15). Parallel data (DATO-DAT7) from the buffer is then transferred to shift register

9D, converted to serial data (W DATA), and transferred to the data cable driver 19A (Sheet IS).

During a read operation, serial read data (R

DATA) from the data cable receivers is ANDED with Enable Bit Count (E BIT C) resulting in the signal

G DATA. This signal enters the shift register

F7 and is transfered as parallel data to the Read

Data register SD, for transfer to the data buffer while the next byte is being shifted through shift register 9D. The read data from the buffer (DATO-

DAT7) is transferred to driver SF (Sheet 14) to the microprocessor for transfer to LSI-II memory.

The counter located at 11C, 12C and 12D (Sheet

15) is used to address the location in the buffer into which data can be written or read from. The counter has the capability of being preset to a specific starting address via the Y Bus of the microprocessor.

ERROR CORRECTION CODE (ECC) LOGIC

. Functional Operation

The ECC Generator does not correct errors; it gen" erates codes during write and read operations and during reading generates a syndrome. A syndrome is the result of merging check characters being read with check characters generated. A zero syndrome indicates no error; a non-zero syndrome indicates an error. This syndrome contains all the information necessary to find the error location and the error pattern, i.e., to allow error correction.

The error location is found by counting the number of clock pulses required to make the E P output go high. The error pattern is then available on the LPO-LP3 and QO-Q7 outputs and can be used to exclusive OR with data. Depending upon the position of switch S5 (location D17), either the computer or the controller corrects the error. Note that some error patterns cannot be corrected. These are flagged to the computer.

Component Description

During a write operation a 32-bit ECC is appended to the header record and a 56-bit ECC is appended to the data record of each sector·of information on the disc. ECC's are also generated while information is being read from the disc. The codes generated during the read operation are compared with the equivalent codes previously written. Discrepancies detected (errors) are signalled to the microprocessor and corrected if possible.

The ECC logic is shown on Sheet 19. The ECC

Generator (7E), also referred to as the Burst Error

5-7

3E, 5E

2901

MICROPROCESSOR

10

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14

Figure 5-3. Data Paths

3E, 5E

2901

MICROPROCESSOR

10 processor, is used in three different types of operations: write,.read, and correct. Detailed information about the ECC generator is given by an AMD,

AM9520/Z8065 product specification.

During writing or reading, information is connected to the DO through D7 inputs of the ECC Generator. Select inputs SO and S1 determine whether a

32- or 56-bit polynomial is being used. The 32-bit polynomial is used for ECC header checks, and the

56-bit polynomial is used for data record check. The

Data Buffer Write Strobe (DBWS) is the source of

Clock Pulses (CP) to the ECC Generator.

Control information for the ECC Generator from the Y Bus is stored by LXR5 into ECC Control

Register 9G.

When MF- is asserted, the logic is initialized.

Asserting REP (Read Error Pattern) makes outputs

LPO-LP3 and QO-Q7 active.

5-8

Control inputs PO-P3 are not used. The ECC Generator functions selected by the CO-C2 inputs are as follows:

C2

L

L

L

H

H

Cl

L

L

H

L

H

CO

L

H

L

L

L

Function

Compute Check Bits

Write Check Bits

Read Normal

Load

Correct Normal

Check bit outputs QO-Q7 are connected to the

DATO-DAT7lines one byte at a time under control of REP and CO-C2. The remaining outputs of the

ECC Generator are stored in ECC Status Register

9F by clock GSCLK. The microprocessor monitors

ECC status on the D Bus during XSD7 time.

Outputs LPO-LP3 (Located Error Pattern), together with outputs QO-Q7, provide the 12-bit

error pattern. Q7 is the MSB and LPO is the LSB of the pattern. Outputs LPO-LP3 are active only when

REP is asserted. Output AE (Alignment Exception) is asserted if the error pattern will not line up automatically during a correction sequence. This can occur because of the method of polynomial division implemented in the ECC generator.

Output EP (Error Pattern) is asserted when the error pattern has been located during the correction sequence. Output ER is asserted if an error was detected after the last check byte had been read during a read function.

+

12 VOLT TO - 5 VOLT POWER SUPPLY

The

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20 is a dc-to-dc converter that produces the -5 volts required for the current mode line driver to the disc(s).

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