30031-1_DU130_Magnetic_Tape_Coupler_Sep83.pdf

30031-1_DU130_Magnetic_Tape_Coupler_Sep83.pdf

Part Number 30031-1

MODEL DU130

MAGNETIC TAPE COUPLER

INSTRUCTION MANUAL

September 1983

D

15TH I B UTED

Distributed Logic Corporation

L D Ii

Ie,

128OC).G Garden

G~ove ~Ivd.

Garden Grove, California 92843

Telephone: (714) 534·8950

TELEX: 881399

FORWARD

SECTIONS 1-4 of this Instruction Manual are intended to assist an operator in installing and operating a magnetic tape subsystem which includes a

Distributed Logic Corporation magnetic tape coupler. The material assumes a knowledge of the instruction set and operating programs for the PDP-II computer being used.

SECTION 5 contains a Theory of Operation. SECTION 6 contains Detailed Logic

Drawings, and a Troubleshooting Guide. A second companion document entitled

"Software Aids and Diagnostic" contains operating instructions and a listing for the DILOG-supplied diagnostic.

Prior to reading this guide, the user should become thoroughly familiar with the PDP-II based hardware/software combination he is using, and be certain he has read the manuals on the tape formatter and transports with which the coupler is to be used.

DEC, PDP-II, PDP-II/03, LSI-II, RXOI, RK05, RT-II, and RSX-II are

Registered Trademarks of the Digital Equipment Corporation.

SECTION

1

1.0

1.1

1.1.1

1.1.2

1.1.3

1.2

2

2.0

2.1

3

3.0

3.1

3.2

4

4.1

4.2

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

4.2.7

5

5.0

5.1

5.1.1

5.1.2

5.1.3

5.2

5.2.1

5.2.1.1

5.1.2.1

5.2.1.3

5.2.1.4

5.2.2

5.2.2.2

5.2.2.3

TABLE OF CONTENTS

TITLE

GENERAL DESCRIPTION

Introduction . . . .

General Description

PDP-II UNIBUS Interface.

Interrupt . . . . . . . . . . . • • .

Formatter Interface . . . • . . .

Tape System General Specifications .

INSTALLATION

Introduction

Installation.

OPERATION

Introduction . . . . . . . . . .

Tape Format . . . . . . . .

Booting from Magnetic Tapes

PROGRAMMING

Programming Definitions . . . • . . •.

Tape Controller Functions and Registers

Status Register (MTS) . . . . . . . . .

Command Register (MTC) . . . . . . . . .

Byte Record Counter (MTBRC) . . . . . .

Current Memory Address Register

(MTCt~)

Data Buffer (MTD)

Tape Read Lines (MTRD) .

Timer. . . . • . . . . .

TECHNICAL DESCRIPTION

Introduction . . . . .

General Description

Computer Interface . .

Microprocessor . . . . .

Peripheral Interface . .

Functional Description

Computer Interface . . .

Data Receiver/Drivers .

Control Receiver/Drivers .

Address Receiver/Drivers . . . . . . .

Bus and Arbitration Sequence

Microprocessor . . . . . . •

Micro Data File Addressing .

Micro Data File Multiplexer . . . .

PAGE

1-1

1-2

1-5

1-5

1-5

1-11

2-1

2-1

3-1

3-2

3-2

4-1

4-1

4-3

4-5

4-6

4-7

4-7

4-8

4-8

5-1

5-1

5-3

5-3

5-4

5-4

5-4

5-6

5-6

5-6

5-6

5-7

5-9

5-9

TABLE OF CONTENTS (continued)

SECTION

5

5.2.2.4

5.2.2.5

5.2.2.6

5.2.2.7

5.2.3

5.2.3.1

6

6.0

6.1

6.2

6.3

APPENDIX A

APPENDIX B

TITLE

TROUBLESHOOTING GUIDE

Introduction . . . . .

General . . . . . . . .

Operating Instructions

Possible Troubles

PAGE

TECHNICAL DESCRIPTION (continued)

2901A Array and Status Register . . . . . . . . .

Control Memory and Register . . . .

Control Store Address Programmer . • • • .

D Bus Multiplexer. . . . . . . . .

Peripheral Interface . . . . . . .

Peripheral Input Output Registers.

. . . . . 5-11

. . . . .

. . . . .

5-9

. . . 5-11

5-13

· 5-14

· . 5-14

· . 6-1

· 6-1

. . . 6-2

· 6-2

CABLE LIST . . . .

· A-I

GLOSSARY OF TERMS .

· . B-1

TABLE

1-1

1-2A

1-28

5-1

5-2

5-3

5-4

5-5

5-6

5-7

LIST OF TABLES

TITLE

Coupler/UNIBUS Interface Lines . . . .

Coupler to Formatter Interface Lines.

Coupler to Formatter Interface Lines.

Controller Buses . . . . . .

Controller Register Storage

Control Inputs to 2901A . . . .

2901 Status Register Bits

Address Modification Conditions

Information Sources to D Bus . . . . . . .

Glossary of Terms . . . . . . .

FIGURE l-la

I-lb

1-2

2-1

4-1

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

LIST OF FIGURES

TITLE PAGE

Tape System (Maximum Configuration) Embedded

Formatter Tape Drives . . . . . . . . . . .

Tape System (Maximum Configuration) Stand Alone

Formatter with Tape Drives . .

Coupler Board Configuration . . . . . . . . . . . . . .

Typical Backplane Configuration . . . . . . .

Coupler Register Configuration . . . . . . . . . .

Simplified Block Diagram Peripheral Controller.

DQ130 Block Diagram.

Slave DATO Transfers . . . . .

Slave DATI Transfers .

NPR DATI . . . .

NPR DATO . . . .

Interrupt

Microinstruction Word

1-3

1-4

1-10

2-2

4-2

5-2

5-5

5-7a

5-7b

5-7c

5-7d

5-7e

5-12

PAGE

1-6

1-8

1-9

5-8

5-8

5-10

5-10

5-13

5-13

5-15

SECTION 1

GENERAL DESCRIPTION

1.0 INTRODUCTION

This material defines the functional characteristics of the Model DUI30 magnetic tape coupler which, when used with any industry standard formatted magnetic tape drive, comprises a complete PDP-II compatible 9 track magnetic tape subsystem. Magnetic tape drives from manufacturers other than DEC can be used while still retaining software and format compatibility with the DEC TM-II tape system. The Model DUI30 is comoletely contained on one quad module that occupy one SPC slot in the backplane.

Data transfers are via the DMA facility of the PDP-II. Transfer rates vary, depending upon the density and speed of the drives included in the system, between 10,000 and 200,000 characters per second.

Up to two embedded-formatter tape drives or external stand-alone tape formatters may be connected to the Model OUI30. Each embedded-formatter tape drive is capable of handling an additional three slave drives. All industry standard external stand alone formatters are capable of handling four drives. The Model OUI30 can accommodate up to eight drives.

The optimal usage of the Model DUI30 is in situations where

9 track, dual density, 800/1600 bpi tape recording capabilities are required; however, the Model DUI30 is compatible with single density 800 or 1600 bpi embedded-formatter tape drives or stand alone external formatters.

In cases where single density 800 bpi NRZI format is the only density required, the Model OU120 magnetic tape coupler should be considered.

The primary functions of the Model OUI30 coupler in a magnetic tape subsystem are to buffer and interlock data and status transfers between the computer I/O bus and the tape formatter, and to translate CPU commands into tape formatter control signals such as START, STOP, REWIND, GENERATE

IR GAP, GENERATE EOF GAP, etc. The primary function of the formatter, is to control tape motion, establish data format, and perform error c.hecking. The overall tape control function is a combination of the coupler functions which are related to the PDP-II and the formatter functions which are related to the tape drives.

A microprocessor is the sequence and timing center of the coupler. The control information is stored as firmware instructions in Read Only Memory

(ROM) on the coupler board. One section of the ROM contains a diagnostic program that tests the functional operation of the coupler. This self test is performed automatically each time power is applied or whenever an

INIT command is issued on the CPU I/O bus.

A green diagnostic indicator on the board lights if self test passes.

1-1

Two additional indicators on the coupler board display dynamic operating conditions to an operator. The conditions displayed are Coupler Busy and Coupler Transferring Data (DMA Busy).

The coupler is connected to a tape formatter via a ribbon cable which plugs into two 50-pin 3M connectors located near the top at the center of the coupler.

1.1 General Description

The DU130 magnetic tape coupler links a PDP-1! computer to one or two tape formatters (embedded or stand alone). The formatter permits information to be read and written on tape between the PDP-11 system and other computers, either small or large scale, and of various manufacturers (DEC, IBM, Data General, Honeywell, etc~).

The coupler performs the following major functions: a. Buffers and interlocks data and status transfers across the computer I/O bus. b. Translates computer command words into single commands or strings of commands to the tape formatter.

The formatter in a system performs the following major functions: a. Controls the timing and the format of data transfers to the tape units. b. Monitors the status of the tape units and the quality of the data transferred onto the tape and presents this information to the coupler. c. Generates all discrete control signals to the tape units.

Each formatter can link up to four tape units to the computer in various configurations. Figure l-la illustrates a simplified system using embeddingformatter tape transports, and Figure 1-lb a system using stand along forma tters.

A high-speed microprocessor is the control and timing center of the coupler. PROMs on the coupler board provide control instructions for the microprocessor, contain configuration-control information, and serve as general purpose logic elements. The microprocessor also permits an automatic self test of the coupler.

1-2

/

>

-

CONTROL 22

'_

...

....

V

V

V

V

~

~

HICROPRO-

CESSOR

-

D~TA

116'

-

INTER-

FACE

~

..ADDRESS -

18

POWER - GROUND l...-l e

TAPE COUPLER

FORMATTER

INTERFACE

'<

PO P-ll

UN

IBUS

FIGURE l-la: Tape System (Maximum Configuration)

Embedded Formatter Tape Drives

,

_

EMBEDDED

E9~T.!~R

~

MASTER.

TAPE DRIVE

SLAVE

TAPE

DRIVE

~ tIj t:J

~

~

0

H

"

SLAVE

TAPE

DRIVE

~

EMBEDDED

I

______

~

MASTER

TAPE DRIVE

SLAVE

TAPE

DRIVE

SLAVE

TAPE

ORIVE

~

H

........ o

D' c en

~

SLAVE

TAPE

DRIVE

If-

SLAVE

TAPE

ORIVE

~

....

·

I

~

~

V

CONTROL 22

V

~

V

:J

I/O

MICROPRO-

CESSOR

INTER-

D~T~

116

V

./

V

,

-ADDRESS

-

18 .

POWER - GROUND

}.

FACE

2

~

TAPE COUPLER

~ p DP-11 u

NIBUS

FORMATTER tNTERF~CE

FIGURE l-lb: Tape System (Maximum Configuration) Stand Alone

Formatter With Tape Drives.

STAND ALONE

FORMATTER

BOS

~

STAND ALONE

FORMATTER

I

TAPE

DRIVE

TAPE

DRIVE

"

~ tf-

0

~ t;j

,

0 til c

'"

TAPE

DRIVE

~

~

TAPE

DRIVE

~

TAPE

DRIVE

H

,

OJ c

(II

TAPE

DRIVE

~

TAPE

DRIVE

~

,TAPE

DRIVE

~

1.1.1 PDP-II UNIBUS Interface

Commands, data, and status transfers between the coupler and the computer are executed via the parallel I/O bus (UNIBUS) of the computer. Data transfers are direct to memory via the NPR facility of the UNIBUS; commands and status are under programmed I/O interrupt control. Data transfer rates are from 5,000 to 100,000 16-bit words per second, depending upon tape packing density and tape drive speed. Coupler/UNIBUS interface lines are listed in Table 1-1.

1.1.2 Interrupt

The interrupt vector address is factory set to address 224, which is compatible with TM-11 software. Interrupts are generated when processor attention is required or when an error occurs.

1.1.3 Formatter Interface

The coupler interfaces with the tape formatter through two 50-pin 3M connectors at the top, center of the coupler board. Two formatters are connected to the coupler in a daisy-chain manner. The maximum cable length from the coupler to the last formatter in a string is 25 feet.

Coupler to formatter interface lines are listed in Table 1-2.

1-5

CP2

CR2

CS2

CT2

CU2

CV2

002

DE2

DF2

DH2

DJ2

DK2

Dl1

Dl2

DM2

DN2

DP2

DR2

DS2

DT2

CH2

CHI

CJ2

CK2

Cl2

CM2

CN2

BUS PIN

CAl

CB1

C02

CE2

CF2

TABLE 1-1: COUPLER/UNIBUS INTERFACE lINES

MNEMONIC

NPG IN

NPG OUT

D15l

D14l

D13l

D12l

DIll

D10l

D09l

D08l

D07l

D04l

D05l

DOll

DOOl

D03l

D02l

D06l

BR7l

BR6l

BR5l

BR4l

BR OUT

BK17 (D01l2)

INIT l

BG07

BG16

BG06

BGI5

BG05

BGI4

BG04

DESCRIPTION

Non processor grant in

Non processor grant out

Data line bit 15

Data line bit 14

Data line bit 13

Data line bit 12

Data line bit 11

Data line bit 10

Data line bit 9

Data line bit 8

Data line bit 7

Data line bit 4

Data line bit 5

Data line bit 1

Data line bit 0

Data line bit 3

Data line bit 2

Data line bit 6

Bus request 7

Bus request 6

Bus request 5

Bus request 4

Bus request out

Bus grant dn 7

Initiate

Bus grant bit 7 out

Bus grant bit 6 in

Bus grant bit 6 out

Bus grant bit 5 in

Bus grant bit 5 out

Bus grant bit 4 in

Bus grant bit 4 out

1-6

TABLE 1-1: COUPLER/UNIBUS INTERFACE LINES (continued)

BUS PIN

FF1

FF2

FH1

FK1

FM1

FT2

EV1

EV2

EJ2

EF2

FD1

FJ1

ELI

EN2

EP1

EP2

ER1

EV1

EV2

EF1

EH1

EH2

EJ1

EK1

EK2

DW2

DV2

EC1

ED2

EDI

EEl

EEl

MNEMONIC

A03L

COL

C1L

BBSY

NPR

1005

1006

1007

1008

INTR

SACK

A13l

A11l

A08l

AI0l

A07l

A09L

A06l

A04L

A05L

BGIN

BGOUT

A12L

A15L

A17L

MSYNL

A16l

A02l

A016

AOOl

SSYNL

A14l

DESCRIPTION

Bus grant in

Bus grant out

Address bit 12

Address bit 15

Address bit 17

Master sync

Address bit 16

Address bit 2

Address bit 1

Address bit a

Slave sync

Address bit 14

Address bit 13

Address bit 11

Address bit 8

Address bit 10

Address bit 7

Address bit 9

Address bit 6

Address bit 4

Address bit

5

Address bit 3

Control bit zero

Control bit one

Bus busy

Non processor request

Interrupt vector bit 5

Interrupt vector bit 6

Interrupt vector bit 7

Interrupt vector bit 8

Interrupt

Select acknowledge

1-7

3-01-82

TABLE 1-2A: COUPLER TO FORMATTER INTERFACE LINES

J4 SIGNAL

2

4

6

8

10

12

14

16

18

20

22

34

36

38

40

42

24

26

28

30

32

44

45*

46

48

50

Coupler Connector J4 to P4 (Cipher, Pertec) to J124 (Tandberg, CDC) to

JC (Digi-Data)9 To PI

(F880). to Jl (Kennedy 6809)

J4GROUND

17

19

1

3

5

7

9

11

13

15

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

MNENONIC

FFBY

FLWD

DWD4

FGO

FWDO

FWD 1

FSGL

FLOL

FREV

FREW

FWDP

FWD7

FWD3

FWD6

FWD2

FWD 5

FWRT

FR1li2

FEDIT

FE RASE

FWFM

FRTHI

FPAR

FTAOO

FRD2

FRD3

DESCRIPTION ..

Fonnatter Busy

Last Word

Write Data 4

Initiate Conmand

Write Data 0

Write Data 1

Not Used

Load on Line

Reverse/Forward.

Rewind

Not Used

Write Data 7

Write Data 3

Write Data 6

Write Data 2

Write Data 5

Write/Read

Read Threshold 2

EDIT

Erase

Write File Mark

Read Threshold 1

Parity Select

Transport Address 0

Read Data 2

Read Data 3

*Grounded except when working with 7 track formatter

1-8

TABLE 1-2B: COUPLER TO FORMATTER INTERFACE LINES

(Ciphe

. Coupler

J5 to P5 (Pertec, cigher) to J125 (Tandberg, CDC)to JD (Digi-Data) t

P2 Fa8t

J2 (Kennedy 6 09)

J5

SIGNAL

~5

GROUND

MNEMONIC DESCRIPTION

1

FROP

Read Data Parity

2

FROO

Read Data 0

3

FROl Read Data 1

4 flOP Loan Point

6

5 FRD4 Read Data 4

8

7

FR07

Read Data 7

10

9

FR06 Read Data 5

12

11

FHER

Hard Error

14

13

FFMK

File Mark

16

15

FCCG/IO

CCG/IDENT

18

17

FFEN

Fonnatter Enable

20

19

FRO

5 Read Data 5

22

21

FEOT End of Tape

24

23

FOFL

Off Line

26

25*

FNRZ

NRZI

25*

F7TR

7 Track

28

27

Ready

30

29

FRWD

Rewinding

32

FFPT

File Protect

34

33

FRSTR

Read Strobe

36

35

FDWDS

Demand Write Data Strobe

38

37

FDBY

Data Busy

40

39

FSPEED Speed

42

41

FCER

Corrected Error

44

43

FONL

On-Line

46

45

FTAD1 Transport Address 1

48

47

FFAO

Formatter Address

50

49

FDEN

Density Select

*Grounded except for 7 track fo~tter

1-9

Pin 1

./

''\. t==:::::jLL-lJ:::==:LI

\7

"Connector J4

Stream

A3

U

Non

LY

Stream

&

E2"

El

r

E3 o~o

~

WI t I o o _ -. .

8.9

INCHES

F

E o

&

Rev F Artwork and Above Only

&.

Rev E Artwork and Below Only

&

WI Jumper Installed

=

Writes/Reads DEC Mode

(Low Byte First, Then High Byte)

Jumper Removed

=

Writes/Reads IBM Mode

(High Byte First, Then Low Byte)

' - - CVI

C

DO

,,~

CAl

" - CBI

Figure 1-2: Coupler

Board

Coilfiguratior~

. 1-10

1.2

Tape System General Specifications

DATA FORMAT Industry standard non-return-to-zero (NRZ) or Phase

Encoded (PE) recording.

9 tracks

Recording densities:

800

1600 characters per inch characters per inch

800/1600 characters per inch

Interrecord gap 0.60 inch min.

Tape parity marks: LPC, CRC, LRC

MEDIA CHARACTERISTICS

TYPE

~" wide mylar base, oxide coated, magnetic tape.

REEL SIZE

7", ~",

1,200 or 1~" diameter tape reels containing 600, and

2,400 feet of tape respectively.

DATA CAPACITY

(megabytes)

Assumes approximate

600 Ft.

1,200 Ft.

2,400

Ft.

=

=

~

80~

800 CPI

5.75

11.5

22.0 recording efficiency:

1600

11.5

23.0

44.0

cpt

DATA TRANSFER RATE

(Characters/Second)

REGISTER ADDRESS

12.5

25.0

37.5

45.0

75.0

125.0 ips ips ips ips ips ips

800 CPI

=

10,000

=

20,000

=

30,000

=

36,000

=

60,000

=

100,000

1600

CPI

20,000

40,000

60,000

72,000

120,000

200,000

Status (MTS)

772 520

Command (MTC) 772 522

Byte Record Counter (MTBRC)

772 524

Current Memory Address (MTCMA) 772 526

Data Buffer (MTD)

772 530

Tape Read Lines (MTRD)

772 532

COMPUTER I/O INTFC.

Interrupt

Vec~or

Address

224.

NPR data transfer.

1 bus load.

1-11

COUPLER/FORMATTER

INTERFACE

PACKAGING

Coupler is compatible with formatters manufactured by Pertec, Kennedy, Tandberg, Cipher, CDC, Digi-Data.

The coupler is completely contained on one quad module 10.44 inches wide by 8.88 inches deep.

DOCUMENTATION

SOFTWARE

One Instruction Manual is supplied with the coupler.

One diagnostic routine with object listing is supplied with a coupler (or the first of a series of couplers).

POWER

ENV IRONMENT

+5, to.25 VDC at 3.6 amps, from computer backplane.

Operating tempErature 50°F to 140

0

F*

Operating humidity 0% to 90% non-condensing.*

*NOTE: The quality of recording and reading information on magnetic tape is affected by temperature and humidity. The area where the tape is used should be maintained within the following limits:

Temperature:

Humidity:

15°C to 32°C

20% to 80%

SHIPPING WEIGHT

5 pounds including documentation.

1-12

SECTION 2

INSTALLATION

2.0 INTRODUCTION

The padded shipping carton that contains the coupler board also contains an instruction manual and cable set to the first formatter

(if this option is exercised). The coupler is completely contained on the quad-size printed circuit board. The formatter and/or tape drive, if supplied, is contained in a separate shipping carton.

CAUTION: IF DAMAGE TO ANY OF THE COMPONENTS IS NOTED, DO NOT INSTALL!

IMMEDIATELY INFORM THE CARRIER AND DILOG.

Installation instructions for the formatter and tape drive are contained in the formatter or tape manuals.

2.1 Installation

To install the coupler module, proceed as follows:

CAUTION: REMOVE DC POWER FROM COMPUTER CHASIS BEFORE INSERTING OR

REMOVING COUPLER MODULE!

DAMAGE TO THE BACKPLANE ASSEMBLY AND THE COUPLER MODULE WILL

OCCUR IF THE COUPLER MODULE IS PLUGGED IN BACKWARDS!

1. Select the backplane Small Peripheral Controller (SPC) location into which the coupler is to be inserted. SPC locations are connectors C, 0, E, and F of slots 1 through 9 of the Unibus backplane assembly.

2. To use the NPR facility required with the coupler, the backplane wiring of the SPC slot must be modified. The modification is as follows:

Remove the wire on the connector C between Al and Bl of the slot into which the coupler is to be plugged. This allows the non-processor grant priority line to be carried through the coupler.

Note that any connector rows which do not have a card installed. must have a bus grant jumper card installed in the 0 slot to continue the bus grants to other devices in the UNIBUS.

2-1

THIS PAGE INTENTIONALLY LEFT BLANK

2-2

On older PDP-II backplanes (DDlI-B,DDll-C), the following additional wiring changes may be necessary if Slot 1 Pin AUI is directly connected to Slot 4 Pin AUI of the system unit into which the coupler is to be installed:

Remove wire between Slot 1 Pin AUI and Slot 4 Pin AUI.

At the coupler slot~ connect Slot 1 Pin AUI to CAl and

Slot 4 Pin AUI and CBl.

3. If the Revision level is E or below and a streamer type tape transport is to be used, cut the etch on the bottom side of the coupler between

El to E2 and E3 to E4. Add a jumper from E2 to E3. If the Revision level is F or above, set the switch,. location A3, to streaming or nonstreaming.

4. If the drive is to read the tape in IBM mode, i.e., high byte read first, then low byte, remove the jumper at location WI.

5. Insert the coupler into the selected backplane position. Be sure the coupler is installed with the components facing Row One (I).

The coupler module is equipped with handles on the side opposite the slot connectors. Gently position the module slot connectors into the backplane, then press until the module connectors are firmly seated into the backplane. Both handles must be pressed simultaneously. When removing the module, apply

~qual pulling pressure to both handles.

6. Feed the module connector end of the formatter I/O ribbon cable set into the computer module area. Install the cable connectors into module connectors J4 and JS. Verify that the connector is firmly seated. NOTE that ribbon cable connectors are not keyed and therefore CAN be plugged in backwards. The connectors have a triangle marked on one end to identify Pin 1. These triangles on the cable and controller connectors MUST be lined up.

7. Connect the tape formatter end of the I/O ribbon cables to the formatter I/O connectors. Refer to Table 1-2.

8. If the formatter is equipped with a IOO-pin connector, adapter

Part No. ACC993A must be used to convert the IOO-pin connector to two 50-pin connectors.

9. Apply power to the computer and verify that the green DIAGnostic

LED indicator on the controller board is lighted. If the DIAG

LED is not lighted, power is not applied to the coupler, the coupler board is bad, or the LED is bad.

2-3

9. Refer to the tape drive manual for operating instructions and apply power to the tape drive. Install a known good reel of tape on the tape drive and place the tape drive ON LINE.

10. Placethecamputer in the HALT mode to enable ODT. Using the computer terminal examine location 772 520. The contents of this location should be 000 141. These are the tape drive status bits signifying: ON LINE, BEGINNING OF TAPE, and TAPE

READY.

11. Using the computer console device, deposit 60007 into location

772 522. The tape should move forward approximately 6 inches and stop. A file mark should have been written on the tape.

Examine location 772 520. The contents of this location should be 040 101 signifying that a file mark has been written and detected.

12. Refer to the DILOG software manual and run the diagnostics.

13. The tape system is now ready for data transfer operations.

2-4

SECTION 3

OPERATION

3.0 INTRODUCTION

Prior to operating the system, the instruction manual sections describing the controls and indicators on the tape drive and procedures for mounting and removing tape reels should be given to handling and magnetic tape to prevent loss of data or damage to the tape handling equipment. The following precautions should be observed. a. Always handle a tape reel by the hub hole. Squeezing the reel flanges can cause damage to the tape edges when winding or unwinding tape. b. Never touch the portion of tape between the BOT and EaT markers.

Oils from fingers attract dust and dirt. Do not allow the end of the tape to drag on the floor. c. Never use a contaminated reel of tape. This spreads dirt to c1€an tape reels and can affect tape drive operation. d. Always store tape reels inside their containers. Keep empty containers closed so dust and dirt cannot get inside. e. Inspect tapes, reels, and containers for dust and dirt. Replace

Take-up reels that are old or damaged. f. Do not smoke near the tape drive or tape storage area. Tobacco smoke and ash are especially damaging to tape. g. Do not place the tape drive near a line printer or other device that produces paper dust. h. Clean the tape path frequently.

Note that tape drives permit off-line or on-line operation. The off-line mode is controlled by switches on the tape drive. The on-line mode is controlled by programmed commands from the computer via the coupler and formatter. When system operation is desired, be sure the tape drive on-line indicator is lit. On-line operation is a function of program commands described in SECTION 4 of this manual.

3-1

3.1 Tape Format

For detailed information on tape format characteristics see formatter and tape drive manuals.

- 3.2 Booting From Magnetic Tapes

1. Place the tape transport liON LINE" and position the tape at

"Beginning of Tape ll

2. If the CPU is equipped with a hardware bootstrap, simply type

IIMTO II CR . If no hardware bootstrap is installed, proceed with the following steps.

3. Load Register location 772522

8 with 10000

8

.

4. Load Register location 772524

8 with 177777

8

.

5. Load Register location 772522 jump forward and halt.

8 with 60011

8

.

The tape will

6. Load Register location 772522 forward and halt.

8 with 60003

8

. The tape will jump

7. Load PC 077707

8

}with O.

8. Start the CPU from location zero.

3-2

SECTION 4

PROGRAMMING

NOTE: For purposes of discussion in this section, whenever the tape

"CONTROllER" or "CONTROL UNIT" is referred to the terms "CONTROLLER" or

"CONTROL UNIT" refer to the coupler/tape formatter functional combination.

4.1 Programming Definitions

FUNCTION: The expected activity of the tape system (read, write, rewind) .

COMMAND: The instruction which initiates a function (GO, Select).

INSTRUCTION: One or more orders executed in a prescribed sequence that'cause a function to be performed.

ADDRESS: The binary code placed on the BDAlO-IS lines by the bus master to select a register in a slave device. Note that·

"register" can be either discrete elements (flip-flops) or memory elements (core, solid state RAM or ROM).

When addressing devices other than computer internal memory, i.e., peripheral device registers, the upper 4K

(28-32K) address space is used.

REGISTER: An associated group of memory elements that react to a singleaddress and store information (status, control, data) for use by other assemblies of the total computer system.

4.2 Tape Controller Functions and Registers

The tape controller performs eight functions. A function is initiated by a GO command after the processor has issued a series of instructions that store function-control information into controller registers. To accept a command, and perform a function, the controller must be properly addressed and the tape drives must be powered up, at 'operational speed, and be ready.

All software interaction between the tape controller, the processor, and processor memory is accomplished by six registers in the tape controller. These registers are assi9ned memory addresses and can be read or written into (except as noted) by instructions that reference respective register addresses. The six controller registers, their addresses, mnemonics, and their bit assignments are shown in Figure 4-1.

4-1

REGISTER

Status

(MTS)

BIT POSITION

HSB

LSE

ADDRESS

772 520 ILL

EOF

COM

PRE BGL

Ear

RLE

NX

SE BOT

7 SO WRL RWS TUR

M LR

CH WN

Command

(MTC)

772 522

Byte Record counter (MTBRC)

772 524

ERR

DEN

DEN

8 5

Pm PE US

US US

CLll

VN

2 1 0

CU

R

INT XBA XBM FU FU FU

GO

ENB 17 16

2 1 0

I

I

I

15

I

I I I I I I I I I I

I

I

I

I

00

I

:urrent Memory

~ddress (MTCMA)

772 526

CM

15

CM CM

CM

14

13 12

CM

CM

CM CM

CM

11 10 09 08 07

CM

CM CM CM

CM CM CM

06 05 04 03 02 01 00

)ata Buffer

(MTD)

772 530

DB DB

08 07

DB DB DB DB DB DB DB

06 05

04 03 02 01 00 rape Read Lines 772 532

(MTRD)

FIGURE 4-1 Coupler

Reqister ConfiquratioD

4-2

4.2.1 Status Register (MTS)

The address of the MTS register is 772 520. MTS is a read only register.

The functions of the bits of this register are as follows:

BIT 15 - ILLEGAL COMMAND: Set by any of the following illegal commands:

1. Any DATO or DATOB to the command register during the tape operation period.

2. A write, write EOF, or write with extended IRG operation when the

File Protect bit is a 1.

3. A command to a tape unit whose Select Remote bit is O.

4. The Select Remote (SELR) bit becoming a 0 during an operation.

In error conditions 1 through 3, the command is loaded into the MTC, but the GO Pulse to the tape unit is not generated. In addition, the

CU ready bit remains set.

BIT 14 - END OF FILE (EOF): Set when an EOF character is detected during a read, space forward, or space reverse operation. During the read or space forward operation, the EOF bit is set when the LPC

(longitudinal parity check) character following the EOF character is read. During a space reverse operation, the EOF bit is set when the

EOF character following its LPC character is read. The ERR bit sets when the LPC character strobe is generated with the File Mark signal upon EOF detection.

BIT 13 - NOT USED

BIT 12 - HARD ERROR (HE): Set as the result of an error being detected on tape.

For all errors, the ERR bit sets at the end of the record. Both lateral and longitudinal parity errors are detected during a read, write, write

EOF and write with extended IRG operations. The entire record is checked including the CRC and LOC characters. During a write operation a correctable error in the PE (1600 bpi) mode will set this bit.

BIT 11 - BUS GRANT LATE (BGL): Set when the control unit, after issuing a request for the bus, does not receive a bus grant before the controller receives the bus request for the following tape character. The condition is tested only for NPR (non-processor request) operations. The ERR bit sets simultaneously with BGL, thus terminating the operation. If the

BGLoccurred during a write or write with extended IRG operation, the control unit does not send the signal WDS to the master, while the master writes the CRC character Eif required) and LPC character onto the tape, terminating the record.

4-3

BIT 10 - END OF TAPE (EOT): Set when the EOT marker is read while the tape is moving in the forward direction. The bit is cleared as soon as the same point is read while the tape is moving in the reverse direction. The ERR bit, as a result of the EOT bit at a 1, sets only in the tape forward direction and coincidentally with the reading of an LPC character.

BIT 9 - RECORD LENGTH ERROR RLE: Detected only during a read operation. t occurs for ong recor s on y and is indicated as soon as MTBRC increments beyond 0, at which time both data transfer into memory and incrementing of the MTCMA and MTBRC stop.

However, the control unit reads the entire record and sets the ERR bit when the LPC character is read. CU ready remains at 0 until the

LPC character is read.

BIT 8 - BAD TAPE ERROR (BTE): NOT USED

BIT 7 - NON-EXISTENT MEMORY (NXMl: Set during NPR operations when the control unit is bus master, and

1S performing data transfers into and out of the bus when the control unit does not receive a slave SYNC signal within 10 microseconds after it had issued a master sync signal.

The operations which occur when the error is detected are identical to those indicated for the BGL error.

BIT 6 - SELECT REMOTE (SELR): Cleared when the tape unit addressed does not exist, is offline, or has its power turned off.

BIT 5 - BEGINNING OF TAPE (BOT): Set when the BOT marker is read, and cleared when the BOT marker is not read. BOT at a 1 does "not produce a 1 in the ERR bit.

BIT 4 - SEVEN CHANNEL c eared to indlcate a

BIT 3

~

TAPE SETTLE DOWN (SOWN): Set whenever the tape unit is slowing down. The master will accept and execute any new command during the

SOWN period except if the new command is to the same tape unit as the one issuing SOWN and if the direction implied in the new command is opposite to the present direction.

BIT 2 - WRITE LOCK (WRL): Set to prevent the control unit from writing information on tape. Controlled by presence or absence of the write protect ring on the tape reel.

BIT 1 - REWIND STATUS (RWS): Set by the master as soon as it receives a rewind command from the control unit. Cleared by the master as soon as the tape arrives at the BOT marker in the forward direction. (It overshoots BOT in the reverse direction)

BIT 0 - TAPE UNIT READY (TUR): Set when the selected tape unit 1s stopped and when the SELECT REMOTE is false. Cleared when the processor sets the

GO bit and the operation defined by the function bit occurs.

4-4

4.2.2 Command Register (MTC)

The address of MTC is 772 522. The functions of the bits of this register are as follows:

BIT 15 - ERROR (ERR): Set as a function of bits 7-15 of the Status Register

MTS. Cleared on INIT or on the GO command to the tape unit.

BITS 14-13 - DENSITY (DEN 8, DEN 5): NOT USED. Not applicable on

9 track tape.

BIT 12 - POWER CLEAR (PCLR): Provides the means for the processor to clear the control unit and tape units without clearing any other device in the system. The PCLR bit is always read back by the processor as o.

BIT 11 - LATERAL PARITY (PEVN): Not applicable for 9 track tape.

BIT 10 - UNIT SELECT

2:

Specifies one of two possible formatters. Selects the high-speed streaming mode on streamer type tape transport.

BITS 9-8 - UNIT SELECT 1: Specifies one of the four possible magnetic tape units.

All operations defined in the MTC and all status conditions defined in the MTS pertain to the unit indicated by these bits. Cleared on INIT.

BIT

7 -

CU READY (CUR): Cleared at start of a tape operation, and set at end of tape operation. The control unit accepts as legal, all commands it receives while the CU Ready bit is 1.

BIT 6 - INTERRUPT ENABLE INT ENB: When set, an interrupt occurs whenever elther the CU ready lt or the ERR bit change from

0 to 1 or whenever a tape unit that was set into rewind has arrived at the beginning of tape. In addition, an interrupt occurs on an instruction that changes the INT ENB from 0 to 1 and does not set the GO bit i.e., CU

READY or ERROR

=

1.

BITS 5-4 - ADDRESS BITS: Extended memory bits for an 18-bit bus address.

Bit 5 corresponds to XBAI7, and bit

4 to XBA16. They are an extension of the MTCMA, and increment during a tape operation if there is a carry out of MTCMA.

4-5

BITS 3-1 - FUNCTION BITS: Selects 1 of 8 functions (programmable commands).

BIT 3 a a a a

1

1

1

1

BIT 2 o a

1

1 a a

1

1

BIT

1 a

1 a

1 a

1 a

1

Off line

Read

Write

Write EOF

Space Forwa rd

Space Reverse

Write with Extended Interrecord Gap

Rewind

BIT

0 -

GO: When set, begins the operation defined by the function bits.

4.2.3 Byte Record Counter (MTBRC) (The address of MTBRC is 722 524)

The MTBRC is a 16-bit binary counter which is used to count bytes in a read, write, or write with extended IRG operation, or records in a space forward of space reverse operation. When used in a write or write with extended IRG Operation, the MTBRC is initially set by the program to the

2's complement of the number of bytes to be written on tape. The MTBRC becomes

0 after the last byte of the record has been read from memory.

Thus, when the next WOS (Write Data Strobe) signal occurs from the master, the control unit will not send the WOR (Write Data Request) to the master indicating that there are no more data characters in the record.

When the MTBRC is used in a read operation, it is set to a number equal or greater than the 2's complement of the number of bytes to be loaded into memory.

A record length error (RLE) occurs for long records only, and is indicated when a read pulse for data (ROS occurring when CRCS or

LPCS does not occur) occurs when the MTBRC is O. The MTBRC increments

. by 1 imnediately after each memory access.

When the MTBRC is used in a space forward or space reverse operation, it is set to the

2

's complement of the number of records to be spaced.

It is incremented by a

1 at LPC time, whether the tape is moving in the forward or reverse direction. A new GO pulse is sent to the tape unit during the SOWN time if the MTBRC is not

0 during that time. When the tape unit is moving in reverse, the LPC character is detected before

SOWN, but before the entire record has been traversed. Thus, both SOWN and LPC character appear to be in different positions on tape from those when the tape unit is moving forward.

4-6

4.2.4 Current Memory Address Register (MTCMA) (The address of MTCMA is 772 526).

The MTCMA contains 16 of the possible 18 memory address bits. It is used in NPR operations to provide the memory address for data transfers in read, write, and write with extended IRG operations. Prior to issuing a command, the MTCMA is set to the memory address into which the first byte is loaded in a read operation, or from which the first byte is read in a write, or write extended IRG operation. The MTCMA is incremented by 2 immediately after each memory access. Thus, at any instant of time, the MTCMA points to the next higher address than the one which had most recently been accessed. When the entire record has been transferred, the MTCMA contains the address plus 2 of the last characters in the record. In the error conditions Bus Grant Late (BGL) and Non-

Existent Memory (NXM) , the MTCMA contains the address of the location in which the failure occurred.

The MTCMA is available to the processor on a DATI except bit a which always reads as a zero under program control. Bit a can be asserted during NPR's to determine the selected byte. The bits are set or cleared on a processor DATa. IN!T clears all bits in the MTCMA.

4.2.5 Data Buffer (MTD) (The address of MTD is 772 530).

The data buffer is an 9-bit register which is used during a read, write, or write with extended IRG operation. In a read operation, the data buffer is a temporary storage register for characters read from tape before being stored into memory. In a processor read, all nine bits are stored into memory. Bits a through 7 in memory correspond to channels 7 through a respectively from tape, and bit 8 corresponds to the parity bit. In a DMA operation only the data bits are read into memory, and are alternately stored into the low and high bytes. In a write or write with extended IRG operation, the data buffer is a temporary storage register for characters read from core memory before they are written on tape.

In a read operation, the LPC character enters the data buffer when bit 14 of MTRD is a 1, and inhibited from doing so when bit 14 is a O.

Thus, after reading a nine-channel tape, the data buffer contains the

LPC character when bit 14 is a 1 and the CRC character when bit 14 is O.

After reading an EOF character, the data buffer contains all a's when bit

14 is a 1 and the LPC character when bit 14 is O. The MTD is available to the processor on a DATI. Bits 9 through 15 are read identically to bits 1 through 8 respectively. Bits 0 through 7 are set or cleared on a processor DATA. Bits 8 through 15 are not affected by a processor

DATa. INIT clears all bits in the MTD.

4-7

4.2.6 Tape Read Lines (MTRD) (The address of MTRD is 772 532)

The memory locations allocated for the tape read lines are:

Bits 0-7 for the channels 7-0 respectively.

Bit 8 for the parity bit.

Bit 12 for the gap shutdown bit.

Bit 13 not used.

Bit 14 for the CRC, LPC character selector.

Bit 15 for the timer.

For correct longitudinal parity, bits 0-8 are 0 after writing a record or reading a record from tape. For a longitudinal parity error, one or more of the bits 0-8 remains at a 1, the bit(s) are at a 1 indicating the channel(s) containing the error which sets the CU ready bit. Thus, if the pulse is set during a tape operation, CU ready sets prematurely thus producing the gap shutdown period when characters are still being read. Bits 0-8 are set and cleared by the tape unit. Bit 14 is set and cleared by the processor and cleared by INIT. Bit 15 is uniquely controlled by the 100 microsecond timer. The MTRD is available to the p~cessor on a DATD except that bit 13 reads back as a O.

4~2.7

Timer

TIMER is a a 10 kHz signal with a 50% duty cycle. The signal is used for diagnostic purposes in measuring the time duration of the tape operations. The timer is read as bit 15 in the MTRD •.

4-8

SECTION 5

TECHNICAL DESCRIPTION

5.0 INTRODUCTION

This section contains the theory of operation of the DUI30 tape coupler

The text references block and timing diagrams interspersed with text, a

Glossary of Terms in Appendix B, and detailed logic diagrams in SECTION 6.

The material begins with a General Description followed by a Functional

Description.

The General Description describes the interconnection of the major logic elements that make up the coupler. The principal reference is the simplified block diagram. The Functional Description describes the individual logic elements within the coupler. The text is referenced to the detailed block diagram. The numbers in the corner of the boxes in the detailed block diagram refer to the schematic sheet showing the circuit.

The description assumes an understanding of the PDP-II I/O bus and a basic understanding of digital computer theory.

5.1 General Description

Figure 5-1 is a simplified block diagram of the coupler. The coupler comprises three logical sections: a. Computer interface b. Microprocessor c. Formatter interface

The three sections function together to transfer data between the I/O bus of the computer and up to eight tape drives. The two interface sections match the voltage levels and load/drive characteristics of the computer I/O bus and tape I/O lines to the logic levels of the coupler. The microprocessor is the control, timing, and data conversion section of the coupler.

The microprocessor functions under control of finmware instructions stored in solid state, programmable, Read Only Memory (PROM). The microprocessor is implemented with AM2900-series bit-slice microprocessor chips. Refer to "MICROPROGRAMMING HANDBOOK" from Advanced Micro Devices,

Inc., 1901 Thompson Place, Sunnyvale, California 94086 for introductory material on microprogramming a bipolar microprocessor.

5-1

Data Data

~ t .....

---.,;;;~

..........

~-~

Q

Control 22

r-------------i

i54

Power

Computer

Interface

Ground

Data

Control

Timing

Microprocessor

• Buffer I/O Lines

· Timing Source

• Bus Sequence (State processor}

· Control Center

• Address Decode

• Error Checking

• Register Storage

• Data Buffering

Data

Control

Timing

Peripheral

Interface

Write Data

Read Data

Control

Status

CD

Co ra

0

E-<

• Buffer I/O Lines

• Set Tape Configuration

• Clock Synchronization

FIGURE 5-1: Simplified Block Oiagram

Peripheral Controller

5.1.1 Computer Interface

The purpose of the computer interface is to (1) buffer 1 i nes between the UNIBUS of the computer and the controller and (2) synchronize information transfers. There are three major classes of lines connected to the computer interface: a. Data lines b. Address lines c. Control lines

There are

16 bidirectional data lines· between the UNIBUS and the controller, and

18 bidirectional address lines between the UNIBUS and the controller. The control lines request information transfers, select the type and direction of transfers, and synchronize the transfers.

The control lines are unidirectional and originate either at the UNIBUS or at the controller.

Information transfers are initiated by a bus master placing an address on the address lines. The bus master then either received data from, or outputs data to, the addressed slave device (controller or memory).

During initialization and status transfer sequences, the controller is a slave and is selected by address 2248. During data transfer sequences, the controller is bus master and either receives data from or outputs data to the processor memory via the NPR facility.

The computer interface controls the synchronization or "bus arbitration" sequence. Bus synchronization is done by a state processor separate from the microprocessor to minimize bus use by the controller. This permits other devices to use the NPR facility on a time multiplexed basis with the tape controller.

5.1.2 Microprocessor

The microprocessor is the timing and control center of the controller.

The microprocessor is controlled by instructions stored in progranmable read only memory (PROM). These instructions, called finmware, cause the microprocessor to operate in a prescribed manner during each of the computer-selected functions. The functions are established by a series of instructions issued by the computer. The instruction operands are stored in registers within the microprocessor.

When a GO command is issued by the computer, the finmware micrpinstructions cause the registers to be examined and either a data transfer sequence or a rewind sequence to be performed. Note that rewind functions can be performed on any tape drive not involved in a data transfer operation simultaneous with data transfers.

5-3

The microprocessor contains an eight word RAM memory dedicated to buffering data between the UNIBUS and the microprocessor. This allows several NPR cycle requests to be missed without missing data words being transferred between the tape and computer memory.

The rate and order (format) at which data is transferred to the tape is controlled by the microprocessor. Within the microprocessor, data is handled in a-bit parallel bytes. Error check bits are calculated (LRCC, CRCC) and supplied to the tape during a write function.

During a read function, the microprocessor monitors the error check bits and the data being read. Discrepancies are flagged as errors to the computer. The microprocessor detects other types of errors during the transfer functions (data late, programming error, etc.) and monitors status lines from the tape for malfunctions within this assembly. All errors are assembled into a status word for access by the processor.

5.1.3 Peripheral Interface

The purpose of the peripheral interface is to match the characteristics of the tape drive to the characteristics of the microprocessor. The peripheral interface: a. Contains 1 ine drivers and receivers that buffer the information lines between the coupler and the tape drives over cable lengths up to 20 feet. b. Contains the PROM and switches that permit configuring the coupler to match the different tape subsystem configurations.

5.2 Functional Description

The detailed block diagram (Figure

~-2) shows the functional elements of the tape controller. A number within the blocks of the diagram references the sheet or the detailed logic drawing represented by the block. The detailed logic drawings are in SECTION 6. A Glossary of

Tenns, in Appendix B, defines the mnemonics used in this text and on the logic drawings.

5.2.1

Computer Interface

The computer interface comprises the following elements: a. Data receiver/drivers b. Control receiver/drivers c. Address receive"/drivers d. Bus and arbitration sequence

The computer interface is a hard-wired logic section that buffers and synchronizes information transfers between the I/O bus and the controller.

5-4

U1

I

U1

CPU t~Te.RFACE.

C.OWtAOl.

~\oI"

1 0 au.

OAooTA

L - ,

~I\lCR.

~

0

0

(

I

II'

4

I.'

2.90'

C~~~

PAT .... v

.u~ vo,

-XOO

PROCE~ORrV~~~&~U~~~~D~IO~)'~-O=-O~O

( ' -

"

I"

til

CSit-JT2AL-

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.. fC •

"c.~" PQOc~Orz. ~ i----4--~

10

"

04""

~

1.0Gt1c:.

T

! . - -

12

TA~

FORMATTE.R

ItJTERs:'AC"

!

>

TA.fiG. a:Jj.JTRo.../ _

"",..A.

~~-

:>

14-

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.r--

--..j.T --..:-_ -_ po-

-_-_

-;-1

T'-'''''

'$TI>Z\J./

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IS

FIGURE 5-2

, lL-______

~~ ~I~

__

~

__

8U~

~ rlc::: _ _ _

J

AO~

I

Al)0IIIrtIa c:&I:SNGS

~

~

(

,

DU 130 B\..OCK. D'AGRA.M

..

D15TR\BUT~D

LOGIC

......

...

",

/

CORP.

LOGIC DIAGRAM

OUI~O ~

14

85~O\q

5.2.1.1 Data Receiver/Drivers

The tristate receiver/driver circuits F15, F16, F17, and FIB, shown on sheet 6, buffer data lines BUS D00L - BUS D15L between the UNIBUS and the controller. Received data lines are identified as DB00-DB15, transmitted data lines are identified as TD00-TD15. The received data lines connect to the microdata file multiplexer (sheet 7).

5.2.1.2 Control Receiver/Drivers

The control lines between the I/O bus and the controller are buffered by circuits E6, E7, F3, F4, and F5 shown on sheet 4. The receivers are always connected to the bus. Most of the circuits are permanently enabled but circuit E7 is enabled by Address Control Enable ACEN.

5.2.1.3 Address Receiver/Drivers (See sheet 5)

Tri-state receiver/driver circuits F6, F7, FB, and F9 buffer addresses between the UNIBUS and the controller. Addresses are enabled to the bus by Address Control Enable (ACEN). Addresses to the bus are from the microdata file output latch (FlO, F11). Addresses from the bus are routed to the bus and arbitration sequence logic on sheets 2 and 3.

5.2.1.4 Bus and Arbitration Sequence

To ensure fastest response time, the synchronization of I/O bus transfers is done by hard-wired state logic illustrated on sheets 2 and 3. Information transfers are of two kinds; programmed I/O and non processor request

(NPR). During programmed I/O transfers, the processor is bus master.

During NPR transfers, the controller is bus master. Distinguishing between the two transfer types is the function of the arbitration logic.

The bus sequence logic synchronizes master/slave transfers over the I/O bus.

Transfers between the I/O bus and the controller are of two types: a. Register transfers via programmed I/O b. Data transfers via NPR

During programmed I/O transfers, the seven controller registers are accessed, initialization information is transferred to the registers, and status information is accessed from the registers. The registers are located in the microdata file on sheet

B.

Address information from the processor is decoded by circuits 010 and 011.

5-6

The bus and arbitration sequence logic comprises PROMs, used as decoders, and flip-flops that temporarily store control information. The storage elements for the DMA light, the BUSY light, and the DIAGNOSTIC light are contained in this logic. Monostable multivibrators in device C3 monitor bus activity to ensure responses to the bus master occur within 10 microseconds. Circuit 02 establishes the crystal-controlled time base for the controller. The 10 megabit output of 02 is divided by two by flipflop 08 to generate 200 nano-second clock PCLK buffered to become PPCLK,

PPCLK, and CLK*. Figures 5-3, 5-4, 5-5, 5-6 and 5-7 are timing diagrams that illustrate bus control sequences.

5.2.2 Microprocessor

The microprocessor comprises the following major elements: a. Data fi

1 e b. Data file address register c. Data file multiplexer d. 2901A array and status register e. Control memory and register f. Control store address programmer and test multiplexer g. 0 bus multiplexer

The preceding elements are interconnected to perform the control, timing, error checking, and data manipulation functions of the controller.

Information is transferred among the elements over internal buses defined by Table 5-1.

A microprocessor functions under control of instructions stored in read only memory (ROM or PROM). These instructions are called microinstructions because most often a series of them is required to perform a function.

All of the microinstructions are called firmware since, once stored in

PROM, they cannot be altered. To understand the function of a microprocessor, please refer to liThe Microprogramming Handbook" from Advanced

Micro Devices, Inc., 901 Thompson Place, Sunnyvale, California 94086.

Detailed technical descriptions of the 2901A four-bit bipolar microprocessor slice and of the 2901 microprogram controller are given in Advanced Micro

Devices "AM2900 Family Data Book". These two elements are the major components of the controller:

5-7

J1

,

.....

~

BSTCLK

AS02

FIGURE

5-3:

SLAVE DATO TRANSFERS "

CCI=I, CO=I)

.J'I

I

...,J

J

BSTCLK

BACTFF

--1

ASOl

--.J

DA

---~

DEN ------'

FIGURE 5-4: SLAVE DATI TRANSFERS (CI, CO=O)

~

BSTCLK

ROB

--1

~

TNPR

NPGI

NPGFFI

NPGFF2

ASXX

TSACK

BBSY

,

'"

SSYN

~ n

LDADD

TMSYN

(.

5

STORU/L

CLR

----------------~,~~---

FIGURE 5-5: NPR DATI

FIGURE 5-6: NPR DATO

VI

.....

"

TSACK

BBSY

DA

DEN

INTR

. SSYN

CLR-

BSTCL'

MRQA..-.J

TBR

BGI

BGFFl

BGFF2

ACK

ASXX

L

I

FIGURE· 5-7: INTERRUPT

I r

DESIGNATION

B

DB

D

P

T y

FO

TABLE 5-1: CONTROLLER BUSES

FUNCTION

PDP-II I/O bus; Data and Address lines are bidirectional, most control lines are unidirectional.

Data bus FROM I/O bus receivers into controller

Input Data bus to 2901A supplied with information from multiplexer 50, 100, lID, 8 bits wide.

Peripheral Bus: Data and Control signals.

Transmit data or control signals from controller to

PDP-II I/O bus.

Output data bus from 2901A array.

Output of 16 x 16 data file.

5.2.2.1 Micro Data File (sheet 8)

This data file stores sixteen 16-bit words (16 x 16) and has two functions: a. Storage for the seven controller registers in locations 9

F

16 as shown in Table 5-2.

16 through b. Buffer storage for data words being transferred via NPR between memory and tape in locations

0

through 7.

TABLE 5-2: CONTROLLER REGISTER STORAGE

REGISTER

FILE LOCATION (HEX)

MTRD

MTD

MTCMA

MTBRC

MTC

MTS

A

8

C o

E

F

5-8

Sheet 8 shows the data file. Data inputs to the file are from the data file multiplexer on lines FI00 - FI15. Outputs from the data file are on lines F000 - F015 to the microdata bus. Data file locations are accessed by the address file and by the OS2 portion of the control register word. Note that the data file is separated into 8-bit bytes and that the upper byte (F008 - F015), the lower byte (F000 - F007), or both bytes can be written into or read from independently.

5.2.2.2 Micro Data File Addressing

The microdata file address logic is shown on sheet 8. Two sources address the data file: a. The bus and arbitration sequence logic (circuit 010). b. The 4 x

4 address file (circuit 011).

Address control from the bus and arbitration sequence logic is address lines A01 - A03, which select specific controller registers.

The 4 x 4 address file is capable of storing up to four addresses. The source of address information to the address file is bit 03 of field three of the control register word and bits 00, 01, and 02 or the

Y bus. Information can be read from and written into different locations of the address file simultaneously. Uhen addresses are being buffered through circuit 010, circuit 011 is disabled from supplying addresses.

Write and read addresses to the address file are from field three of the control register word directly, and indirectly via PROM CIa

(sheet 3).

5.2.2.3 Micro Data File Multiplexer

The microdata file multiplexer, shown on sheet 7, switches the input to the microdata file between two sources: the contents of the

Y bus, and the contents of the data bus (DB). The contents of field three of the control register word control the selection.

5.2.2.4 2901A Array and Status Register

The 2901A array is shown on sheet 10. The 2901A array comprises two

AM2901A four-bit bipolar microprocessor slice integrated circuits connected in cascade to perform data manipulation on 8-bit bytes. The major sections of the AM2901 are shown within dashed lines on the detailed block diagram in Figure 5-2. A description of the operation of this device is given in the "AM2900 Family Data Book".

The 0 bus supplies external data to the 2901A. Data from the 2901A is on the Y bus. Control inputs to the 2901A are given in Table 5-3.

5-9

TABLE 5-3: CONTROL INPUTS TO 2901A

MNEMONIC

A0-3

B0-3

SIGNAL

SOURCE

Control Register

Control Register

DEFINITION

Address inputs: selects the A file register contents to be connected to the 2901A,

A bus (Sl)

Address inputs: selects the A file register contents to be connected to the 2901A,

B bus (S2)

10-8

CN

CP

Control Register Instruction control lines: lines 0-2 select the data sources to be applied to the ALU; lines 3-5 select the ALU function to be performed; lines

6-8 determine the routing of the output of the ALU within the ALU and the source of data supplied to the

Y

(output) bus.

(ALU, ALU SRC, DST)

Control Register

Carry input of ALU. Used during arithmetic operations.

Crystal Oscillator 200 nanosecond clock to 2901A.

The status register is updated on a controller clock with the ALU status. The register stores the conditions shown in Table 5-4.

MNEMONIC

TABLE 5-4: 2901 STATUS REGISTER BITS

DEFINITION

Indicates result of ALU operation is Zero

Indicates a "carry out" of ALU

The most significant ALU bit (sign of result)

5-10

5.2.2.5 Control Memory and Register

The control memory stores the firmware that controls the operation of the controller. It comprises six 512 x 8 bit programmable read-onlymemories (PROMs) identified as B12, B14, B15, B16, B17, and B18 on sheet 11. The PROMs have a pipeline register at the output identified as the Control Register (CR). The six PROMs produce a 48-bit instruction word divided into six 8-bit fields. Figure 5-8 depicts the instruction word.

The contents of the control memory are accessed by the Control Store

Address Processor and strobed into the control register by the PPCLK clock. The contents of the control register (CRl-00-07 through

CR5-00--07 and literal 000-007) are routed throughout the logic of the controller.

5.2.2.6 Control Store Address Programmer

The Control Store Address Programmer (CSAP) is an AM2910 microprogram control circuit and is described in liThe AM2900 Family Data Book". It controls the sequence of execution of microinstructions stored in the control memory. The CSAP is shown on sheet 10.

Control store output address lines CSA00 through CSA08 select one of

512 locations in control memory and are also routed to test five of the control register and the

TEST output of test conditions multiplexer A17

(shown on sheet 10). Bits 00 through 07 (LSB) of field five (CR5) supply instruction codes to the CSAP. Anyone of 16 instructions can be selected.

The instructions can be modified by the state of the TEST input. The instructions select the next source of addresses to the control memory. The primary sources of addresses are as follows: a. A program counter/register within the CSAP. b. A five word stack within the CSAP. c. Branch addresses directly from bits 00-07 of field five (CR-5)

Note that bits 04 through 06 of field four (CR4) control test condition multiplexer A17. This multiplexer connects one of eight selected conditions to the TEST line when specified by the current microinstruction being executed. The conditions tested for are shown in A17, Table 5-5.

5-11

U1

....

N o

Sl

CS1

F1

S2

F2

ALUS

ALU CItI

CS2

F3

CST

F4

ACR TEST

FS

BRANCH

F6

LITERAL

FIGURE 5-8 Microinstruction Word

CIRCUIT

B12

E12, F12

012

B7

B8

TABLE 5-5: ADDRESS MODIFICATION CONDITIONS

MNEMONIC

CONDITION

C

Z

No carry from 2901A ALU

ALU result is zero

C

N

Carry from ALU

ALU sign bit logical true

Parity true

P

0

INIT

T

Data reg flag

System reset

True

Note that bus signal DCL0, if ever low, disables the output of the CSAP and generates a Reset (RST) signal.

5.2.2.7 0 Bus Multiplexer

The 0 bus multiplexer, shown on sheets 8 and 13 is the information source to the 2901A array processor. The multiplexer comprises circuits E12 and

F12 on sheet 8 and circuits B6, B7, and B8 on sheet 13. Circuits E12 and

F12 also function as storage registers. Additional information sources for the 0 bus are PROM B12, shown on sheet 11, which supplies the literal (LIT) and PROM 012 on sheet 10.

Field one, bits 00 through 03, and bit 02 of field two, via circuit B10

(sheet 3) gate the selected source to the 0 bus. Information sources to the 0 bus are as shown in Table 5-6.

TABLE 5-6: INFORMATION SOURCES TO 0 BUS

SHEET

11

8

10

13

13

SOURCE

Literal from control memory

Microdata bus upper and lower bytes

Controller status

Data from tape

Tape status

5-13

5.2.3 Peripheral Interface

The peripheral interface comprises the following elements: a. Peripheral input output registers b. Tape timing and configuration logic c. Cable driver/receivers and control buffers

5.2.3.1 Peripheral Input Output Registers

There are two registers which temporarily store information being transferred between the tape and the other elements of the coupler; an input register shown on sheet 13, and an output register shown on sheet 14.

The input register stores status information and data received from the tape and comprises circuits B6, B7, and B8. The outputs of these circuits are gated to the D bus as described in paragraph 5.2.2.7. Timing is controlled by signals POA, POB, and POC generated on sheet 3.

The output register stores information to be sent to the tape and comprises circuits A13, A14, and A15. These circuits make up a 32-bit register that receives information from tne Y bus in a-bit segments. Y bus information is stored in the register under control of the PIA, PIS and PIC clocks.

5-14

BUSAOOL-

BUSA15L

COC1

COFF/C1FF

CN+2

CLRB

CLR

CR1-07

CR2-00--

CR2-07

CR3-00--

CR3-07

CR4-00--

CR4-07

TERM

AOO-A15

A16, A17

ACEN

ACK

ADRA

ADRB

AOOFF

ASOO

AS01

AS02

BACT FF

BG

BBSY

BGFF1,2

BGO

BOT

BSY

BSYS

BSYFF

TABLE 5-7: GLOSSARY OF TERMS

DESCRIPTION

Address bus bit 0 through bit 15

Address bus bits 16

&

17 (MSB)

Address and control enable

Acknowledge

Address A

Address B

Address bit 0 flip-flop

A sequencer bit 00

A sequencer bit 01

A sequencer bit 02

Bus activity flip-flop

Bus Grant

Bus busy

Bus grant flip-flop

Bus grant out

Beginning of tape mark

Busy

Busy Set

Busy flip-flop

Data address bus lines (16)

Control zero, one

Control zer%ne flip-flops

Carry output of 2901

Clear bus

Clear

Control register one output bits 0-7

Control register two output bits 0-7

Control register three output bits 0-7

Control register four output bits 0-7

ORIGIN SHEET

5

4

4

2

3

2

2

14

3

2

4

4

2

3

2

2

2

2

2

5

11

11

11

4

2

9

3

2

11

5-15

FL-D

FU-D

FLClK

FUClK

INIT

LDADD

LIT

MRST

MRQA

MRQB

MSYN

MTC

MTR

GLOSSARY OF TERMS (continued)

TERM

CRS-OO--

CR5-07

CS

CSA08

DESCRIPTION

Control register five output bits 0-7

Carry signal out of second 2901

Control store address bits 0 through

08 (9 bits)

000--

007

Data bus bits 0-7 to 2901

DA

DA16, DA17

DBOO-

DB15

DB8M

DB1SM

DClO

DEN

EDT

FLPT

DRQFLG

FIOO-FI1S

FUNC

FOO~

F015

Data enable

Data address bits 16 and 17

Data bus bits 00-15 from UNIBUS

Bit 15 is MSB, bit 00 is LSB

Data bit 8, multiplexes

Data bit 15, multiplexed

DC Voltage low

Device enable

End of tape from tape

File protect from tape

Data request flag

File in bits 0-15

Function

File out bits 0-15

File lower data

File upper data

File lower byte clock

File upper byte clock

Initialize

Load address

Literal

Master reset

Memory request A

Memory request B

Master sync

Magnetic tape control

Magnetic tape request

ORIGIN SHEET

11

9

10

8,10,11,12

4

2

14

14

12

7

3

8

3

6

6

7

3

4

2

2

2

3

3

4

2

2

3

3

3

5-16

GLOSSARY OF TERMS (continued)

TERM DESCRIPTION r~TS

NS

Magnetic tape status

Most significant output bit of 2901 ALU

(sign)

Non processor grant

Non processor grant flip-flops

Non existent memory

NPGFFl,2

NXM

OFC

ONL

PARS

PBSY

PIACLK

PIBCLK

PICCLK

PIDCLK

Off line command to tape

On line status from tape

Parity status from tape

Peripheral busy set

Peripheral in A byte clock

Peripheral in B byte clock

Peripheral in C byte clock

P0A-D

P0B-D

P0C-D

P0D-D

PUP

PPCLK

PIAOO-07

Peripheral in D byte clock

Peripheral out

A byte data

Peripheral out

B byte data

Peripheral out C byte data

Peripheral out

0 byte data

Pull up voltage

PIBOO-07

PICOO-07

RDO-RD7

RDP

RDQ

RDS

RSTS

Processor clock (controller clock)

Peripheral

~n

A byte bits

(8)

Peripheral in B byte bits

(8)

Peripheral in C byte bits

(8)

Read data lines from tape

Read data parity from tape

Read data request

RL~C

RWS

7TRK

SELl-SEL4

SFC

SWS

Read data strobe from tape

Reset tape status

Rewind command to tape

Rewind status from tape

7 or 9 track status from tape

Select tapes 1,2,3, or 4

Synchronous forward command to tape

Set write status

ORIGIN SHEET

2

3

3

3

3

3

3

3

3

3

14

14

11

3

9

4

2

14

14

14

14

2

14

14

3

12

12

12

14

14

13

14

5-17

GLOSSARY OF TERMS (continued)

TERM

SRC

STORL ,U

SSYN

STA

SYNFF

DESCRIPTION

Syhchronous reverse command to tape

Store lower, upper byte

Slave sync

Status

TAOO-TAI5

TA

TBBSY

TBR

TDOO-TDI5

TDOOG

Synchronize flip-flop

Transmit address bits 00-15

Transmit address

Transmit bus busy

Transmit bus request

Transmit data bits 00-15

Transmit

Time out

0 bus bit 00 gated

Time out delay

TO

TOD

TINTR

TMSYN

TNPR

TSACK

TSSYN

TRDY

\~ARS

WOS

WOP

Transmit interrupt

Transmit master sync

Transmit non processor request

Transmit select acknowledge

Transmit slave sync

Tape ready from tape

Write amplifier reset to tape

Write data strobe to tape

Write data parity to tape

WOO-W07

WRL

WRU

YOO-

Y07

Write data lines

(8) to tape

Write load

Write unload

Y bus bits a through

7 from 2901

3

3

9

3

3

2

2

2

2

2

14

14

14

14

14

ORIGIN SHEET

14

2

3

2

2

6

2

3

3

2

5

5-18

SECTION 6

TROUBLESHOOTING GUIDE

6.0 INTRODUCTION

The purpose of this section is to assist the maintenance engineer in isolating malfunctions to specific assemblies of the tape based computer system. Normally, once a malfunctioning assembly (tape drive, memory, controller CPU board, etc.) is located, a known good assembly should be substituted while the malfunctioning unit is returned to a repair depot.

Be sure to read this entire section carefully before beginning to troubleshoot the system.

6.1 General

System malfunctions come under two major classifications; intermittent and continuous. Intermittent failures are normally very difficult to isolate and usually require step-by-step substitution of equipment over a period of time until the intermittent assembly is isolated. This section will primarily discuss continuous failure isolation.

When troubleshooting electronic equipment, certain basic items should always be checked: a. Is power properly applied to all system assemblies - switches on, fuses good, AC power cords plugged in, area power circuit breakers on, etc. b. Check DC power at backplane terminals of computer - +5V DC,

+12V DC. If DC voltages are low, verify AC line voltage is within tolerance:

100 - 127 Vrms, 50±1 Hz or 60!1 Hz

200 - 254 Vrms, 50±1 Hz or 60!1 Hz c. Verify system generates proper response when system is powered-up

(refer to operation instructions for the processor). d. Verify all modules are properly plugged in. No empty slots should exist between modules. e. Verify all signal cables (tape, console terminal) are properly plugged in. Check each end of cables. f. Can the console be operated in "Local" mode? If not, console is defective.

6-1

g. Is the tape drive ON LINE light on? h. Are the computer panel switches set correctly (ENA/HALT, LTC, etc.)? i. Is green DIAG light on tape controller board on?

6.2 Operating Instructions

While troubleshooting the system, the engineer should check the following items: a. Is the tape clean? Dirty tape or tape read/write heads cause bit dropouts. b. If tape produces a high-pitched whine or metal-to-metal sound, immediately power down the tape; a bad bearing is possible. c. Was any module pulled out or plugged in while power was applied?

Shorting connector pins together can cause integrated circuit to fa i

1 . d. Has ribbon cable connector been plugged in upside down at controller? This connector is not keyed. Be sure the arrows on the female connector line up with arrows on male connector.

6.3 Possible Troubles

This paragraph provides possible malfunction locations based on either visual indications or tests and assumes the basic items in paragraph 6.2 have been checked and found normal.

NOTE: Before troubleshooting the system be sur~ proper operating procedures are being followed and the system is properly configured. Refer to SECTIONS 2 and 3 of this manual or the the USER'S GUIDE.

The following pages contain a trouble chart. Space is left on the chart for field failures not in the chart to be noted.

6-2

m

I

W

TROUIU

1. GREEN DIAGnostic light on coupler II orr.

2.

No c-.nlcaUon betNeen console and ca.putel·.

3. No data transfers to/fraa tape. never lights.

ISY light

4. Dati transferred to/fra. tape Inccorrect.

DNA and ISY lights blink to Indicate transfers.

POSSiBlE CAUSE

1.

Microprocessor section of coupler Inoperative. a. Crystal not Slated In socket or In wrong. b. Short or open on board. c. lid Integrated Circuit. d.

No

DC power.

Z. I/O section of coupler ·handlng up· Qlus. a.

DrI always low. b. Shorted bus transceiver IC. c. lid CPU boud

3. 'ape not ready or bad clble connection.

•• I.proper comaunlcetlon with tape registers on coupler or bad IC In register section of coupler.

4. lid

~ry e. Nohe or Inter.lttent source of DC poNer In caaputer. b. lad IC In tape I/O section of coupler. c. Run tape diagnostic. set console to .. syst .. ·Hllt On (rror.· d. lad area on tape. e. Head ~rn. f.

Crystll In coupler wrong frequency. g. Conflgurltlon switch J4 not set properly.

CHECK/REPLACE

1. Coupler.

Put board on extend.r. With scope look at pins of

2901.

All pins .xcept power and ground should be switching. look for -stuck htgh-. or ·stuck low·. or hllf-aaplttude pulses. If no switching. either power or cryst.l b4d.

2. Computer Interf.c. logiC of coupler.

•. Check signal DEN for constant .ssertlon. b. Check I/O IC's. ReDDve coupler bOlrd to s •• if trouble goes IWlY. c. Run CPU dllgnostlcs.

3. Check tlpe switches Ind clble connector.

I. lo.d .nd reid tlpe registers fra. console with processor h.lted. I.e .• RKDS. RlGA.

RKER. V.rify bits 10lded cln be reid.

4. Run memory dl.gnostlc.

I. Check AC and

DC power. b. While oper.tlng. check lines fra. coupler to t.pe with. 'scope for short or open. c. An.lyze error hilt. d. Errors should .1wlYs occur In sa.e sector of t.pe. e. Repllce held. f. Check chlr.cterlstlcs of tlpe drive.

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IZ. 1'0 "R)2MA."'\""TS1Z.

S'~A'-'5.

D\5TR\BU1ED LOG\C CORP

D.L-

LOGIC DIAGRAM,

DUI~O

SHT 14 OF \4

8S~019

APPENDIX A

CABLE LIST

TABLE 1-2A: COUPLER TO FORMATTER INTERFACE LINES

Coupler Connector J4 to: A)

B)

C)

D)

E)

F)

Cipher FIOOX, F900X, Pertec; Connector P4

Cipher F880; Connector PI

CDC, Tandberg; Connector J124

,

Digi-Data; Connector J4

Kennedy Streamer; J1

Kennedy Formatted drive;

JS

DESCRIPTION J4 SIGNAL J4 GROUND MNENONIC

2

20

22

24

26

28

30

32

34

4

6

8

10

12

13

16

18

40

42

44

45*

46

48

50

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

FFBY

FLWD

FWD4

FGO

FWDO

FWDI

F5GL

FLOL

FREV

FREW

FWDP

FWD7

FWD 3

FWD6

FWD2

FWD5

FWRT

FRTh2

FEDIT

FERASE

FWFM

FRTHI

FPAR

FTADO

FRD2

FRD3

DIRECTION

IN o o o o o o o o o

o

o o o

OUT

OUT

OUT

IN

IN

Formatter Busy

Last Word

Write Data

4

Initiate Command

Write Data 0

Write Data 1

Not Used

Load on Line

Reverse/Forward

Rewind

Write Data Parity

Write Data

7

Write Data 3

Write Data

6

Write Data 2

Write Data 5

Write/Read

Read Threshold 2

EDIT

Erase

Write File Mark

Not Used

Not Used

Transport Address 0

Read Data 2

Read Data 3

*

Grounded except when working with 7 track formatter.

A-I

TABLE 1-2B: COUPLER TO FORMATTER INTERFACE LINES

Couple~ Connector JS to: A)

B)

C)

D)

E)

F)

J5

SIGNAL

J5

GROUND

Cipher FI00X, F900X, Pertec; Connector P5

Cipher F880; Connector P2

CDC, Tandberg; ConnectorJ125

Digi-Data; Connector J3

Kennedy Streamer; J2

Kennedy Formatted drives;

Jl

MNEMONIC DIRECTION

24

26

25*

28

30

32

34

36

38

40

42

44

47

48

50

1

2

3

4

6

8

10

12

14

16

18

20

22

11

13

15

5

7

9

17

19

21

23

25*

27

29

33

35

37

39

41

43

45

47

49

FRDP

FRDO

FRDI

FLOP

FRD4

FRD7

FROG

FHER

FFMK

FCCG/ID

FFEN

FRD5

FEaT

FOFL

FNRZ

F7TR

FRWD

FFPT

FRSTR

FDWDS

FDBY

FSPEED

FCER

FONL

FTADI

FFAD

FDEN

I

I

I

I

I

I

I

I

I

I o

DESCRIPTION

Read Data Parity

Read Data 0

Read Data 1

Load Point

Read Data 4

Read Data 7

Read Data G

Hard Error

File Mark

CCG/IDENT

Formatter Enable

Read Data 5

End of Tape

Off Line

NRZI

7 Track

Ready

Rewinding

File Protect

Read Strobe

Demand Write Data Strobe

Data Busy

Speed

Corrected Error

On-Line

Transport Address 1

Formatter Address

Density Select

*

Grounded except for

7 track formatter.

A-2

APPENDIX B

GLOSSARY OF TERMS

TERM

AOO

AOl

A02

A03

ACK

ACKFF

ADRA

ADRB

AOOFF

AsOO

ASOl

As02

BACT FF

BBS7 L

BDALOO L-

BDALlS L

BDCOKH

BOOUT

L

BDIN L

BDMGI L

BOMGO L

BIAKI L

BIAKO L

BINIT L

BIRQ L

BOMR L

-aM

BRPLY L

BSACK L

BsTcLK

BSYNK L

BWTBT

L

BRoFF

BSS7

BSY

APPENDIX B: GLOSSARY OF TERMS

DESCRIPTION

Q bus Address bit 0, LSB

Q bus Address bit

1

Q bus Address bit

2

Q bus Address bit

3,

MSB

Acknowledge

Acknowledge Flip-Flop

Address A

Address B

Address bit

0

Flip-Flop

A State Sequencer bit

00

A State Sequencer bit

01

A State Sequencer bit

02

Bus Activity Flip-Flop

Q bus Bank Seven Select

Q bus Data Address Lines

(16)

Q bus DC power OK

Q bus Data Out from master

Q bus Data In from master

Q

bus DHA Grant In

Q bus DMA Grant Out

Q bus Interrupt Acknowledge Input

Q bus Interrupt Acknowledge Output

Q bus Initialize

Q bus Interrupt Request

Q bus Direct Memory Request

Beginning of Tape Mark

Q bus Reply from slave

Q bus Select Acknowledge

Q bus Clock

Q bus Synchronize

Q bus Write Byte

Bus Reply Flip-Flop

Bank 7 Select

Busy

B-1

GLOSSARY OF TERMS, continued ....

TERM

ClKA

ClK 1

CN+2

CLRB

CLR

CRI-00--

CRI-07

CR2-00--

CR2-07

CR3-00--

CR4-07

CR4-00--

CR4-07

CR5-00--

CR5-07

CS

CSAOO--

CSA08

DOO--

007

DA

DAI6,OAI7

OBOO-

OBIS

DBI6~DB17

DEN

DIN

DINFF

DMG

DMGFF

DMGI

+DMR

DOUT

DOUTFF

DRQFLG

DSL toT

DESCRIPTION

Clock 10 megahertz

Clock one to the tape drive

Carry output of 2901

Clear Bus

Clear

Control Register one output bits 0-7

Control Register two output bits 0-7

Control Register three output bits 0-7

Control Register four output bits 0-7

Control Register five output bits 0-7

Carry signal out of second 2901

Control Store Address bits 0 through 08 (9)

2901 Data bus bits 0-7

Data Enable

Data Address bits 15 and 17

Data bus bits 00-15 fram A bus

Bit 15 is MSB, bit 00 is LSB

Data bus bits 16 and 17 (Address extension)

Device Enable

Data In

Data In Flip-Flop

Direct Memory Grant Delayed

Direct Memory Grant Flip-Flop

Direct Memory Grant in from Q bus

Direct Memory Request

Data Out

Data Out Flip-Flop

Data Request Flag

Density Select to Tape

End of Tape from Tape

B-2

GLOSSARY OF TERMS, continued ••.•

TERM

FiJSi

FIOO

FIlS

FUNC

FooO--

FIlS

FL-D

FU-D

FLCLK

MrS

NXM

OFC

ONL

PAUSE

PBSYS

PARS

PIAcLK

PIBCLK

PICCLK

FUCLK

LDADD

LIT

Mim"

MRQA

MRQB

MrC

MTR

P0A-D

P0B-D

PPCLK

PIAOO-07

PIBOO-07

PICOO-07

DESCRIPTION

File Protect from tape

File In bits 0-15

Function

File Out bits 0-15

File Lower Data

File Upper Data

File Lower Byte Clock

File Upper Byte Clock

Load Address

Literal

Master Reset

Memory Request A

Memory Request B

Magnetic Tape Control

Magnetic Tape Request

Magnetic Tape Status

Non Existant Memory

Off Line Command to Tape

On Line Status from Tape

Peripheral Bus Set

Parity Status from Tape

Peripheral In A byte clock

Peripheral In B byte clock

Peripheral 1n C byte clock

Peripheral Out A Byte Data

Peripheral Out B Byte Data

Processor Clock

Peripheral In A

Peripheral In 8

Peripheral In C

8-3

~LOSSARY

OF TERMS, continued •...

VS

WARS

WDS

WOP

WDO-WD7

WRL

WRU

WTBTFF

YOO--

Y07

TERM

PPCLK*

RDO-AD7

RDP

RDS

TIAK

TIRQ

TRPLY

TSACK

TO

TOO

TSYNC

TROY

TWTBT

RSYNC

RWC

7TRK

SELl-SEL4

SFC

SWS

SRC

STA

STORL,U

TA lOIN

TOOUT

TDOOG

TDMR

TOMG

DESCRIPTION

Processor Clock

Read Data bits 0-7 from Tape

Read Data Parity from Tape

Read Data Strobe from Tape

Synchronize From Q bus

Rewind Command to Tape

7 of 9 Track Status from Tape

Select Tapes I, 2, 3, or 4

Synchronou-s F orwa rd Command to Tape

Set Write Status

Synchronous Reverse Command to Tape

Status

Store Lower, Upper Byte

Tag clock fo~ extended address bits

Transmit D Bus In

Transmit

0

Bus Out

Transmit

0

Bus bit

00

Gated

Transmit Direct Memory Request

Transmit Direct Mem.ory Grant

Transmit Interrupt Acknowledge

Transmit Interrupt Request

Transmit Reply

Transmit Select Acknowledge

Time Out

Time Out Delay

Transmit Sync

Tape Ready from Tape

Transmit Write Byte

Overflow from 2901

Write Amplifier Reset to Tape

Write Data Strobe to Tape

Write Data Parity to Tape

Write Data Lines

(8) to Tape

Write Load

Write Unload

Write Byte Flip-Flop

Write Byte Flip-Flop

Y Bus bits 0 through 7 u-4 ..

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