Gimix_6809_CPU.pdf

Gimix_6809_CPU.pdf
The GIMIX 6809+ CPU BOARD is the heatt of the DIMIX 6809
COrrtPlJt€.'r S··I··St€.'rrt.
It is an e::-;tr'emE:<l"," v'2r·£'.atilE' b,:,ar',j that
oi:·fer·s th€.' IJs€.'r· a sr·€.'at man··... featur';?s and optiorls which ITI.:i.ke
it an ideal choice for a vari€.'ty of systems and applications.
FEATURES
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4 PROM/ROM/RAM sockets for monitors and user software ( UP to 32K)
PROM/ROM/RAM sock€.'ts individuallY Jumper selectable for sinsl€.'
or mul tiple supply vol tase and 1,2,4 clr' :.:*~ byte device~
lK bytes of scratchpad RAM (optional)
(CMOS RAM W/Battery backup optional if the 58167 option is installed)
6840 Fr'o9r'amITtable timer' with pr'l)visiol'ls for' e>::ter'nal clock, 9d.te
and output connections •
Time off Da~ Clock (58167) W/Batt€.'ry backup
("ptional)
9511A or 9512 Arithm€.'tic processor W/Jumper selectable 2, 3, or 4 ~iz.
clock spe€.'ds.
(optional)
FPLA addr·€.'ss d€.'codinsf:or th€.' ::::: on car d devices - 4 PROM/
ROM/RAM sock€.'ts, 58167, 9511A/9512. 6840, lK scratchpad RAM
Software .r'e-addr·essins of the 8 (In car·d devices
( allows software switchin9 of on board monitors)
All FPLA decoded devices can be individually enabled/disabled
FPLA decoded devices are available for DMA access}
Extended addressins for the FPLA decoded devices ( can be disabled)
..Jumper· selectable inter'r'IJPts for' the 684(>, 581c..7, and '/51-1~/9512
Anyone of 3 memory manasement technique~ can be used
l
Straisht Bank Select
GIMIX Enhanced DAT w/softwar~ write protect
(optional)
SWTPC compatible OAT (for SBUG-E)
(optional)
Jumper' Se 1 ectab 1 e pr'ocessclr clock speeds ( 1, 1. 5, 2 MHz.)
(2MHz CPU optional)
Separate buffers for the 6809 and the on card devices.
NMI input can be Jumpered to the bus or to an external connector
BA & BS JUITIPer selectabl~ f'jr- independent or sated oper'ation
User defihed latch output
Gold 1'10LEX connectors for' tr'cluble fr'ee cClntact
88-50 at. d SS- -501'; compa t i b 1 e
Full DMA capabilities ( works with anY of the 6809 DMA methods)
Full 810* memory capabilities
Fully assembled, tested and burned in
NOTE:
The GIMIX 6809~ CPU BOARD
does not include a
baud
rate
~hH,erator·.
In·systems that rE'quir'e
a baud rate ~enerator, it must be
provided
elsewhere.
The GIMIX
6800/6809 mainframe includE'S a bau~
rate generator on the mother board.
131 MI X,
-,,2--
INC.
INTRODUCTION
ThE< OIMIX e..::::09+ CPU combinE's orl (.nE' b(.ar'd malY{ fE'atur-E's that
would othE'rwisE< rE'quirE' several diffE'rE'nt boards.
The board is
in
E'f1:ect 2 sE'par'ate boar'ds on one pr'intE'd cil'clJit car·d.
ThE' CPU sE'ction consists of thE' 6809 prOCE<ssor with thE<
necessary data and address buffers, rE'SE<t circuitrY, atc.
plus
the extended address/dynamic address translation features.
The
second section consists of the 8 on card device& ( 4 PROM/ROM/RAM
sockets, 58167 time of day clock, 6840 pro9rammable timer, 9511A or
9512 ar'ithmetic pr'(II:essor',
and lK of scr·atc.h pad RAM) with thto'ir'
own data and address ~uffers
E<xtended address decoder FPLA
addrE<ss dE<codin9 and the necessar'Y suPPor't cir'clJitr'Y to irlti?rface
them to thE< SS50/SS50C bus and the 6809 processor.
This division
of the board into two Si?paratE< sections allows thE< 6809 to oPE<ratE<
with minimal 10adin9 of its output
linE<s and also pE<rmits DMA
dE<vici?s
such as disk controllE<rs to access thE' 8 on board dE'vicE's
directly.
The board can be used with any of the standard 6809 DMA
tE<chniquE's.
Two mE<thods of Dynamic Address Translation (DAT) arE< available
as options,
the onE< is SWTP compatible and allows the :':;;WTP !;:;BUG-E
monitor' to be USE<d without m(.dification, ttli? ottli?r is an enhanc.E<d
DAT
that
allows
fasti?r and E<asier task/usE<r
switchin~
in
multi-taskin9 /lTtulti-user' s·...·stE<rfts.
E>ct'endE<d addr'essifl9
which
E<ffE<ctively extends the memory addressin9 range of the 6809 to 1
MBYTE can be der'ived fr'olT! a bank selE<ct latch in versions with(.ut
DAT or' {r'om either' (;.1: the optional DAT II"IE'thods.
The 4 PROM/ROM/RAM sockets pE<f'mi t avaC" iE<ty of opt i (.Ins f.n· on
board software.
Each of the 4 sockets can be individually Jumper
progralTtmE<d to accept frolTt 1 to 8K byte, sin91e or multiple supply
voltage,
2708 pinout compatible devices.
The FPLA address decoder
is prepro9rammed for several
different combinations of device
sizes. Custom programmin9 of the FPLA can permit other combinations
of device sizes to be used.
The 58167 tirhe of day clock option provides tilTtE<, daY, datE<
daY,
date depenJent programmablE<
information as well
as tim~,
interupt
geni?ration.
The batter'Y back UP feai:ur'e maintaills
accurate time i?ven when the
system power is of for extended
per- i ods of time.
The 6840 programlTtable timer option gives the user 3
har'dwar'e
counter/timers
that can be used independentlY or in c')mb i nat i .)(1
with each other for timing or counting applications a.s well
as
programmable interupt generation.
The optional 9511A or 9512 a.rithmetic processor provides fast,
efficient mathematical
capabilities in hardware.
This can be
i?xtri?mely important ir. real timi? situations or whenever speed is an
important factor •
•
The I/( scra tchpad HAM opt ion pr'ov i deoS space fo:.. r
temporal")'
storage.
pointers.
interuFt vectors,
etc.
The GMXBUG09 monitor
uses some of this area for internal
use.
When the 58167 clock
option is
installed lK of CMOS RAM ma~ be installed to Frovide
battery backup of the scratchpad RAM.
Gnn x,
INC.
---'::'
--'
,-
The GIMIX 6809 CPU is a ver--.,.- co:,rrIPle;:.;: and v€rE-ati 1e boar-d.
Most of the selectable features and options are cont~olled by
DIP-switch and/or solderless programming Jumpers.
In certain cases
options require additional integrated circuits or movins ICs to
different sockets.
The followins sections describe all of the
features of the GIMIX 6809 CPU in detail. Dia9rams are included to
show most of the common Jumper confisurations and software examples
are provided as a 9uide for usin9 the OAT,
clock, arithmetic
pr-ocess(.r-, etc.
NOTE: THIS MANUAL COVERS ALL VEnSIONS AND AVAILAE:LE OPTIONS FOr.: nlE
G I MI X 68(y:~-J cr-'u rAM I LY•
SOME :~;ECT I CrN:; Or- Tl IE MP.tJUAL MAY NOT Ar-'PL '(
TO THE PAF.: I TCULAH BOARD YOU HAVE.
CERrA I N OPT I ON:=; AHE lJNL Y
AVAILABLE
WITH A PARTICULAR VER:::::IOtJ OF THE DOAFm.
Sot1E OPT I CltJ:::;
ARE ONLY AVAILABLE AT THE TIME OF OnIGINAL PURCHA:=;E AND CANNOT BE
ADDED LATER.
PLEASE CONSULT THE GIMIX PRICE LIST/ORDER FORM OR
CONTACT THE FACTORY FOn FUnT~ER INFORM~TION HEGARDING OPTIONS AND
AVAILABILITY.
CPU SECTION
RESET/NMI
CA--1 )
connector
In accordance with theSS50C bus definition the master reset
line,
normally the input from the front panel reset switch, has
been removed from the bus.
The master ~eset connection is
available instead at connector CA-l whi~h is located Just above IC
U-54 toward the left center- (If the cir-clJit bo:.ar-d.
CA--1 €lIse.
pr-ovides an input for- an NMI/ABORT switch. The NtlI inFut at CA--1
is only active when the NMI option ,jumper- ( .JA--1:;: ) is in -the NMI
to reset connector position( See the NMI option J~mper section).
Both inpu-ts ar-e ful h-- buffered and debounced and or.ly ,-e"luir'€ a
sin91e pole normally open switch from the appropriate illPut to
9round. The sround connection is-also available at CA-l.
When purchased as part of a complete s,-stem the appropriate
matins cCofirlector- is pr·.;:.vided pr-e-wir-ed t.) the fr-orlt partel.
CPU
bCoards purchased
separately come with a connector which can be
wir-ed t(. e>dstirl9 systems as r-e"luir·ed.
Fi9ure A
Sheet 1, of the switch Qnd Jumper confi9uration
drawins5 shCows the pinouts of the RESET/tJMI connector (CA-1).
CPU CLOCK SPEED .)Pt i on
j
uITtper· (JA·-!3)
CHMIX,
INC.
. 4-
The GIMIX 6809 CPU sives the use~ the option of selecting
either- a
1,
1.5,
or- 2 MHz.
oper-atin9 speed fl)r- the (:':~:O':;J.
!,lost
standard versions of the 6809 will function at either 1 o~ 1.5 MHz.
The 2 MHz.
6:;::B09 is r-e9uir-ed fClr- oper-ation at 2 I'1Hz.
Note: the
al:tual input to the 6809 is 4 times the oper-atins speed.
Thus a 1
6809 re9uires a 4 MHz.
input clock frequency etc.
CPU speed
MHz.
is selected by -the position one of the Jumper blocks at Jumper
ar-ea ...IA-8.
.....lA-=:;: alsc. deter-milles the clock speed of the clPtic'flal
9511A or 9512 arithmetic processor(see the 9511A/9512 section of
the manual).
Jumper area JA-8 is located to the upper risht of the
cir-cuit boar-d between Ie U-·I0 and U--l1.
Fisur-es A thr-oush H:
Sheet 3 of the swi tch atld juniperconfisur-ati,:.n dr-awinss show the pinouts and -jumper
positions
f.:,rthe CPU and arithmetic processo~ clock speeds.
NMI option Jumper
,..lA-I:;:: )
The GIMIX 6809 CPU sives the user- the option of connectins the
NMI input of the processor to eithe~ the RESET/NMI connector (CA-l)
orto one (If the 1 ines of the Sf:50/SS50C bus.
These opt ions ar-e
selected by the p(lsiti(ln o-F the Jumper- bl.:.ck at Juniper- ar-ea ,...IA··l:].
When the NMI to reset c(lnnector option is selected only a switct, or
device cl:lnnected to the boar-d th,.-oush the RESET/NMI
connectoreCA-l) can sene rate an NMI.
When the NMI to bus option is selected
any of the on card devices that ~enerate interrupts, as well as any
other boards in the system that a~e connected to the proper bus
line, can sener-ate an NMI.
In the NMI
to bus pr)sition ti,e Nl'"lI
input buffer is connected t(l the bus line desisnated NMI on the
8850 blJS and BU:=:Y on the S:;:;50C.
.. Jumper- ar'ea ,...IA-·13 is
1 clcated
at
the lower left of the circuit board near t~immer resistor R-24.
Fisur-e B: Sheet 1, o-F the switch and . jumper
drawinss shows the jumpe~ positi(lns for JA-13.
c,:,nfisur'ati')11
BA/BA-AND-BS option JlJrflPer- ( JA-·14 )
The 6809 CPU has 2 output lines~ BUS AVAILAB~E (BA) and BUS
STATUS (BS) that are used to by other devices in the system to
deter'mir,e the status elf the pr-(tcesse·r-.
(see the 6809 data sheet
for details on decodins BA and BS) Amons other thinss DA and BS
are
us€:'d by DMA devices to deter-mine when thE' pr-ocessor- has
released the bus to them for DMA operations.
To
provide
compatibi 1 ity with cer-tairl €:'xistirls 8::;-50 t..:.ar-ds the GIMIX 6809 CPU
BOARD has provisions
for
gating DA with BS and placing
the
r€:'sultins losical AND of th€:' 2 sisnals on the BA line of the SS-50C
bus.
Th€:' BA AND BS position of JA-14
maich€:'s
the
SWTP
configuration of BAlDS.
Fisure E: sh€:'et 1 of the switch and Jumper
drawinss shows the jumper positions for JA-14
confi9uration
GIMIX,
INC.
EXTENDED ADDRESSING
The 6809 CPU is capable of addressihs a maximum ~f 64K of
memory space directly.
This capability, while sufficient for many
applications,
is
a
limitins factor when
larser,
especiallY
multi-user/multi-taskins, systems are considered.
In order
to
e:o<pand the addr-essins capability (If the 6809 the SS50C ,bus
definition includes 4 extra or extended address
lines.
These
additional lihes sive the bus a total of 20 address lines and allow
for UP to 1 MBYTE of address space.
Since the 6809 senerates only
16 address lines, some combination of hardware and software must be
used to simulate the extra 4 sisnals.
NOTE:
In order
to take
advantase of extended addressins the devices to be addressed must
be capable of decoding all 20 address lines.
Boards such as
the
GIMIX 32K STATIC RAM board.
8 PORT SERIAL I/O board,and 128K
PROM/ROM/RAM board have the capability to decode all
20 Qddress
lines and can
be used with extended addressins.
The GIMIX 6809
CPU also provides extended address
decodins
for
the 8
devices
decoded b~ the FPLA.
The GIMIX 6809 CPU has provisions for
three methods
of
simulatins the 4 extra address
lines.
These methods include
STRAIGHT BANK ::;;ELECT, whict, uses a simple latch, and two differ-ent
methods of Dynamic Address Translation
(DAT)
which can also
senerate the 4 extended address sisnals.
Each
method
has
advantages and disadvantases and it is UP to the user to determine
which method best suits his needs.
In addition,
some software
available from various vendors may require that a particular method
be used.
STRAIGHT BANK SELECT
I n the s tr-a i sht bank se 1 ect methcld of extended add/-ess i ns the
1 MBYTE of available address space is divided into 16 sections or
banks of 64K each.
Any devices in the system that a~e set UP to
decode a
particular bahk address will only appear on the bus when
their bank address apears on the extended address lines of the bus.
For example if a multi-user system were being set UP in which each
of three users was to have 32K of memory dedicated to his use,
three 32K memory boards could be installed in the system.
Each of
the 3 boards could be set to the same base address es.
$0000-$7FFF
but with each set to a different bank.
When a particular user was
to have access to his portion of memor~ the monitor/super~isor
prosram would place the bank address of that user on the extended
addr-t?ss bus and his bank (If IT,E'n,(lr-Y wO'Jl d be enat.led.
Areas elf
memory and devices such as I/O, disk controllers etc., that were to
be sha~ed by all users,
would be set to
ignore the
extended
address lines and would appear at the same address in all banks.
While this m~thod is relativelY simple and straightforward
itl,as
limitations.
For example it requires that eac~ user or task be
permanently assisned a particular amount of dedicated memory.
If .a.
user needs more memory than he is orisinally assig~ed the hardwart?
must be reconfisured to increase his available memory.
If a
ust?r
does not requirt? all
of the memor¥ allocated t6 him the unused
en MI X,
INC:.
-1-::'-
(.::::(>':'-' CTU BOArm
is unavailable to other users unless the hardware confi9uration is
chansed.
Also since it may only be possible to assign an entire
board to a
particular bank, memory may be wasted because a full
32K must be assigned to a UStor- whc, oril--( r-e9IJir-es lc.K.
BANK SELECT LATCH
When using the STRAIGHT BANf< ::ELECT method clf extended
addressing, the data on the extended address lines is Jet e r- In i ned by
the value stored in the BANK SELECT LATCH.
The bank
select latch is a write only device that aFFears at
memor-·...- lClcatiorl $FFFF.
A pr'ocessor- wr·ite to this
1 (lc.ati(ln
stol-es
d a t a i nth e 1 at c h • A r- e a d f r' 0 m t his 1 0 cat ion r' e t u r- ... s d a t a f r- 0 HI an --,-other device addressed at this location.
Normally a read from this
location would
return
the
restart vector
stored in a PROM/ROM
monitor located from SFFFF down.
The
least significant 4
bits
written to the latch are the bank number SO-SF of the bank to be
tonabled.
Any software that
modifies thE; contents of the bank
b--(
latch must be located in an area of memory that is not
applications bank s wit chi n 911) 0 IJ 1 d be
switching banks.
In mClst
done by a monitor/suFervisor pr09ram located in memory shar'ed b-'I'all users and not affected by the extended address lines.
Note: 2 of the remaining bits of the latch are
used to control
the r' fun c t ion 5 ..HI the b (I a r- d •
I f e i the r' (I f the s e fun c t i (I n 5 a r- e i II
use any prosrams that modify
the bank select
latch must
not
inadvertently change these 2 bits.
Since the bank select latch is
a write only device the last data written to the
latch should be
kept in temporarY storage for comparison when new data is to be
written. Bit 5 of the bank select latch is the
software control
latch for
the FPLA address deco~er and bit 4 controls the user
de fin e d 1 at c h 0 u t put at sol de r'
pad " A" •
:::; e e
the a p p r' 0 p ria t e
section of the manual for further information on these features.
(I
DYNAMIC ADDRESS TRANSLATION (DAT)
Dynamic address translation is a method of m~morY management
that allows better utilization of the memory resources within a
system. It overcomes some of the disadvantases of the strai9ht bank
select method of extended addressin9. in that it allows available
memory to be allocated among users as their requirements vary.
It
also allows memory boards that can only be addressed as
lar9~
con tis u 0 usb 1 0 c k s t 0 bee f f e c t i vel Y s p 1 i t i n t (14K s e s rr..", n t E. t t. at can
be addressed as required.
Since this re-location of memory is
under software control
it
can be done at any time and does not
re9uire hardware changes in the system.
DAT breaks the, entire
mefTlor-Y space
irltc. 4K segments.
so m~mor-'{ as'sisflfllt'flt carl IT,or'e
closely fit the requirements of each user/task.
DAT has st'veral
other advantages,
for example,
the system mo~itor/ ,Supervis6r
program could tt'st each 4K segment of ffit'ffiOrY before assisning it to
a
user or task.
I f a bad Segfht'r.t of HIf:'nIOr"',' wer-e fourld it cc.ul d be
(; I MI X7
INC.
-·7·-
(.:::0';;- CPU BOARD
eliminated from the table of available memory and a sood sesment
substituted.
The monitor/supervisor prosram could then set a flas
or indicator to show that the system re9uires maintenance.
In order to understand how dYnamic address translation works
we must first
understand the concept of physical
and
losical
addresses.
A physical address, as the name implies, is the address
at which a device (memory,I/O,etc.)
is set by its hardware
to
respond.
For example the DIP~switches on a memory board determine
its physical addre~s.
A losical address is the address that
the
processor outputs when
it attempts to access a particular memOr'(
location. For example when the processor attempts to write data to
location SOOOO it outputs the losical address SOOOO on its address
lines.
In a system that does not have dynamic address translation
the address lines from the processor are connected directly to the
bus arId the phys i ca 1 and los i ca 1 addr'ess ar'e a 1 wa","s e"lua 1 •
When
the
pr,(.cessc.r· writes tc. 1 (.cati.:.n $0000 the memor·y at $0000
responds.
Dynamic address translation allows
us
to
assisn
different
l09ical address to memory that has a particular physical
address.
For example memory with a physical address of $0000 m~sht
be assi9ned the 109ical address $2000.
When the processor attempts
to access memory at losical address S2000 the memory at
physical
address ~OOOO would respond.
DAT then is a method of translatin9
the l09ical address from the processor to a physical
address that
appears on the bus.
DAT is implemented on the GIMIX 6809 CPU board by insertins a
high speed.
random access memory(the DAT RAM) between the upper 4
address lines of the 6809 and their correspondin9 bus buffers.
A
second identical RAM is used to generate the 4 bi~s of the extended
address.
The 4 address
lines from the processor are used
to
address 1 of 16 locations in the DAT RAM and the data stored in'
these l6cations becomes the phYsical address that appears on the
bus.
The DAT RAM translates the upper 4 bits of the processors
logical address into the upper 4 bit~ of a physical address and 4
bits of extended address.
Since the DAT only translates the upper
4 bits of address it divides the memory space into 16 4K losical
se9ments.
The physical
address space consists of 16 4K physical
address segments in each of 16 possible banks or a
total
of 256
possible 4K physical address segments.
By placing the proper data
in the DAT RAM any of the 256 physical se9ments can appear at any
of
the 16 109ical
address se9ments.
For example 4K of memorY
phys ica 11 Y addr'essed at $OOOO-SOFFF c.)U 1 d appear' to' the pr'ocessor'
to be addressed at SCOOO-SCFFF.
A physical address segment could
also be made to appear at more than one logical address.
For
example a ,4K se9ment phYsically addresed at $EOOO-SEFFF could
appear at SEOOO-SEFFF and SCOOO-$CFFF at the same ti~e.
NOTE:
ON POWER UP THE DATA IN THe DAT RAM AND THEREFORE LOGICAL
ONL Y THE UPPER 256 BYTES OF MEMORY
ADDRES:SES ARE UNDEF I NED.
SFFOO-SFFFF ARE GUARANTEED TO BE AT THEIR PROPER ADDRESS.
IN
SYSTEMS THAT USE DYNAMIC ADDRESS TRANSLATION THESE BYTES MUST
CONTAIN.
IN ADDITION TO THE RESET AND INTERUPT VECTORS SOFTWARE
THAT INITIALIZES THE DAT RAMS TO A
PREDETERMINED
STARTING
THIS HHTIALIZATION MUST TAKE PLACE BEFORE ANY
CONFIGURATION.
MCMilr:;>V
GIMI X,
INC.
AC:CES::;E::; C)UT::: I DE TI-! I!:; 256 BYTE AnEA ARE t1ADE.
For the purpose of writins data to the DAT the DAT RAM shares
the
upper
16 bvtes
of address space $FFFO-SFFFF with the memory
normallv at
these addresses
(
usuallv
the
svstem
monitor
PROM/ROM).
The
DAT RAM is write onlv, a write to these locations
stores data in the DAT RAM~ a read from them returns data from
the
PROM/ROM monitor.
The least sisnificant 4 bits of data written to
the OAT are stored in the RAM that translates the upper
4
address
lines
of
the 6809,
the
upper 4 bits are stored in the RAM that
Benerates the 4 bits of e~tended address.
Two
different methods
of
dvnamic address
translation al-e
available as
options
on
the GIMIX 6809 CPU board.
One
is
cOlTlpatible
with
the
method
used on the ::;;l.JTP MP--09 b(.ar-d and the
SWTP SBUG-E monitor ROM.
When the board is confiBured for this OAT
method
the SWTP SBUG-E ROM can be pluBBed directly into the GIMIX
6809 CPU board.
The GIMIX 6809 can be ~sed as a direct replacenlent
for
the SWTP MP-09 board in svstems where baud rates are available
from a source other than the CPU board.
The GIMIX 6809 CPU does
not
have
an on board
baud rate senerator.
The second OAT method
is an enhanced version
that allows
much
faster
operation when
switchins tasks.
While dynamic address translation lTIay find some use in smaller
svstems
(64K and under).it will probablv be most useful in larser
multi-user multi-taskins applications.
For example, in the
system
described in the section on straisht bank select, with 3 users in a
multi-user application, each user
(task)
could be assisned
the
memorv required from anv of the available memory in the sYsteln.
As
the users memorv requirements chansed memorv could be allocated
or
deallocated as
necessarv.
With the SWTP compatible DAT switchins
users ( tasks> requires writins a new set of 16 values into the DAT
RAM each time the svstem switches between users (tasks).
With the
GIMIX enhanced DAT method the DAT values for UP to
16 different
users
(tasks)
are written
to
the OAT RAM and switchinsbetween
users is done bv writins a sinsle byte to a task
select
resister.
Each
time
the
svstem switches users (tasks) onlv the task select
resister byte need be written.
SWTP compatible DAT
To use this version of DAT the user must write values
to
16
locations
in the DAT RAM.
Each of the 16 locations cor~esponds to
one of the 16 possible 4K
logical
add~ess
segments.
The
first
location SFFFO co~responds to 10sical add~e5s segment $OOOO--$OFFF
the secc.nd SFFF1 to 51000-51FFr and so (·r. UP
te.
thE'
H_.
tho
at
$FFFF which corresFonds
to
l09ical address se~ment SFOOO-SFFFF.
The least sisnificant 4 bits of data written are the COMPLEMENT of
the
UFPer
4
bits
of the desired
Fhysical address.
The UFFe~ 4
bits a~e the desi~ed bank address.
For example if a 4K segment
of
GIMIX,
(:,::::0 '?", CPU BOARD
INC.
memory
located at phYsical address $2000 in Lank 1 is to appear at
losical address SOOOO then the value 51D would be
written
to
the
DAT RAM at
location SFFFO.
The
1
indicates that the d~sired
sesment is phYsically located in bank 1 and the D is the complement
of
the upper 4 bits of its physical address, 52000.
The following
table shows
the
16
losical
address
sesments
with
their
correspondins DAT locations, sample data and the resultins physical
addresses:
LOGICAL
ADDRE:3:3
DAT
LOCATION
DATA
PHYSICAL
ADDRE::;;:=;
BANK
50000-$OFFF
$1000-S1FFF
52000-$2FFF
S:3000-"$~:FFF
$4000--$4FFF
$5000-$5FFF
$6000-$6FFF
S7000-S7FFF
$:3000--$!:::FFF
S-:;'OOO-S9FFF
SAOOO-$AFFF
SBOOO--$BFFF
$COOO-$CFFF
$DOOO-$DFFF
$EOOO-$EFFF
$FOOO-SFFFF
SFFFO
SFFFl
$FFF2
SFFF:3
$FFF4
$FFF5
SFFF¢,
$FFF7
SFFF:::!
SFFF9
$FFFA
SFFFr:
SFFFC
SFFFD
$FFFE
$FFFF
SOP
SOC
SOD
SOC
SlB
S09
SOA
SO:::
S07 "
SOC:'
S05
$04
SO:3
S02
SOl
SOO
o
o
o
o
1
(I
o
o
o
o
(>
o
o
o
o
o
::;EGMENT
$OOOO-SOFFF
t,1000-$lFFF
$2000--S2FFF
$:3000-- !t:::!Frr
S4000--$4rFF
!t600(l-!t6FFF
S5000-$5FFF
57000--$7FFF
S::::OOO- S:]FFF
S9000-S';"FFF
$AOOO--$AFFrS[:OOO: SDFTF
$Coo(J-$Cn:r
SDOOO--SDFFF
SEOOO--- SEr-FF
$rOOO-$FFrT
NOTICE THAT IN THE ABOVE TABLE:
1 TfE FIRST 4 ENTRIES THE LOGICAL AND PHYSICAL ADDRESSES ARE EQUAL
2 THE FIFTH ENTRY THE PHYSICAL SEGMENT IS IN BANK 1
~! THE :::; I XTH AND SEVENTH ENTRY::;; J-:AVE THE I R F'HY::;; I CAL AND LOG I CAL
ADDRESSES REVERSED.
4 n IE REM AI N I NO ENTR I ES ALL HAVE PHYS I CAL AND LOG I CAL ADDRES:::;E::; Ef.!U?
GIMIX enhanced DAT
In this version of DAT the user can write UP to 16 sets of 16
values each to the DAT RAM.
Each
of
these sets
of
values
is
functionally equivalent
to
the
16 values written
to the SWTP
compatible DAT.
Each of
the
16 sets
represents
the
OAT
confisuration for- orle user or task.
Ollce t_he r"e9uired values
for
all the users (tasks) are written to the DAT a sin91e write to
the
task select register
is all
that is re9uired to switch L~tween
users (tasks).
The 16 locations of the DAT RAM appear at the
same
memory
locations as in the SWTP compatible DAT.
Before wr-itin9 to
the DAT. the number ( SO-SF) of the particular user (task)
to
be
written must be stored in the task select resister.
After the task
number is written to the task select register, the
16 DAT values
for
that
user
(task)
can be written to the DAT.
To completelY
.; r. ;
+
oj .:l
1;
7 {~
CHMI X,
INC:.
-10--
the
GIMIX enhanced DAT the software must write each of the 16 task
numbers to the task select re~ister, in turn, followed
by
the
16
DAT values
for that task.
The task select register is located at
SFF7F and like the DAT RAM shares its location with other
devices.
The task select re9ister is a write only device and its 109ical and
physical addresses are always the same.
As in the other version of DAT the least si9nificant 4 bits of
data written to the DAT correspond to the most si9nificant
4
bits
of
the
desired physical address, however in the GIMIX Enhanced DAT
these bits need NOT BE COMPLEMENTED.
They are the true
value
of
the
upper
4 bits of the desired physical
address.
The most
si9nificant 4 bits written to
the
DAT
correspond
to
the
bank
address of the desired phYsical
se9ment (bank numbers SO-SF).
The
least si9nificant 4
bits
written
to
the
task
select
resister
determine which of the 16 tasks ( SO-SF) is active.
Any software that modifies the contents
of
the
task
select
resister
must
reside
in memory that will not be affected by the
switchin9 of tasks.
It is also ilflPortai"lt to nClte
that
:2
of
the
remainin9
4 bits of this resister are
used
to control other
functions on the board.
If these functions are in use any pro~rams
that
modify
the
contents
of
the
task select re9ister must not
inadvertently change these bits.
Since the task select re9ister is
a
write
only device the last value stored should be maintained in
terTIPOf-ar'Y stor-age forcompar-ison pIJr-po!;;-es when new data is
to
be
written
to the re9ister.
Bit 5 of the task select resister is the
software control latch for the
FPLA address
decoder
and
Lit
4
contr'ctls the IJSer' defined
latch .:IIJtPIJt at sa:alder' Fad "A".
See the
appropriate sections of the manual for further information on these
featur·es.
MEMORY MANAGEMENT CONFIGURATION
The
GIMIX
6809+
CPU
can be confi9ured for any of the three
merrle.f··''management
techni"lIJes
::;:TRAIGHT
BANI:::
:::;ELECT,
:3WTF'
compatible
DAT, or the GIMIX enhanced DAT ) by the installation of
the proper inte9rated circuits at specific locations on the
board.
If
the board is ordered with one of the two DAT confi9urations, it
is shipped with only the proper parts for
that
DAT
confi9uration
installed.
If neither DAT is ordered the board
is
shipped
with
only
the
par·ts
for'
the STRAIGHT BANI< SELECT installed.
If the user- wishes
to change the
confi9uration
of
the
board,
he
can
obtain
the
necessary
parts and install them at any time.
The followin9 chart
shows the parts required and their board locations for each
of the
three
confi9urations.
Refer
to the component layout drawin9 for
the locations of the sockets on the board.
LOCATION
U-21
SWTF' COMPo
EMPTY
DAT
GIMIX DAT
93L4:22
BANK SELECT
EtlPTY
en 11 I X ,
I hlC.
-11EMPTY
IJ-22
1)-2:3
74L~;174
8T26 <*>
74:31:39
74S1E:9
EMPTY
1j-37
U-:39
U-40
U--43
U-44
:=:T28
U-45
EMPTY
9::::L422
74L~=;174
::;:T2B
EMPTY
EMPTY
EMPTY
EMPTY
Et1PTY
EMPTY
EMF'TY
74L::;174
EMPTY
EMPTY
*
An BT26 buffer is re~uired for compatibility with
the SWTP DAT and SBUG-E .
NOTE: For proper operation, ICsat locations ~arked EMPTY
must be removed or relocated when changing configurations.
SOFTWARE WRITE PROTECT
The GIl'lIX 6:30';1 CPU gives the u::.er the abi 1 it,' to write Frotect
under'
s(.ftwar-e
cont.-ol
any of the 4:~ Ff",--sical se9rr.ents o-F merr,e·r..space. The software write protect option uses the most
si9nificant
bit
of each location in the DAT RAM and limits the maximum address
space to 1/2 MBYTE.
This
bit which
normally
controls extended
address line A19 is used to inhibit [email protected] writes to selected 41(
sesments.
A Jumper option permits setting address line A19 either
hish
or
low so that either the lower 8 ban~s $0-$7 or the UFPer- 8
banks S8-SF can
be
used.
This
option
can
be
used
only
i~
conjunction
with
1 of
the 2
DAT methods.
To write protect a
sesment a 1 must be written to the most sisnificant bit of the
DAT
when
the
selected
sesments
physical
address
is written.
A 0
written in this
position
indicates memory that
is
not
write
protected.
NOTE:
When
the
board
is
confi9ured
for
the
SWTP
compatible DAT this pattern is inverted i.e.
a
0
is written
to
write
protect
a se9ment and a
1 is written for a segment that is
write enabled.
This feature will write protect any tvpe of
device
including
RAM,
1/0 devices, ETC.
However, it onlv protects these
devices fr'(lm wr·i tes i:r'om the 6809, it dCles not
pr-otect
then, fr'on,
writes
bv other devices that
can take control of the bus such as
DMA disk controllers etc.
CAUTION:
If
the
software
write
protect feature is enabled some
existins software for the SWTP compatible DAT mav accidentallv
write
protect areas of memory.
The software write protect feature
can not be
used with the SWTP SBUG-E monitor.
Software write protect option Jumper
,.JA-10 )
The software write protect option is enabled by
the
position
of
the Jumpers at JA-10.
This Jumper area also selects the upper
or lower 1/2 MBYTE of addr~ss space when Software write protect
is
enabled.
JA-10
is
located
nearthe
center of the board abo~e
DIP-swi tt:h S2.
Figures J
throush M:
sheet
2
of
the
switch and Jumper
confisuration drawin9s show the pinouts and Jumper
positions
for
,-.lA-10.
131 MI X,
INC.
I':.::::(l';J CTtI
-12-
BOARD
USER DEFINED LATCH OUTPUT
Th~
device used for
the TASK SELECT REGISTER or the BANK
SELECT LATCH depending on which memory managemant option
is
installed,
can store 6 bits of data.
Since only 5 of these bits
are used by the board, the sixth bit is available as a user defined
output from the board.
This output is available for external
connection at solder' pad "A", located below the batter·y ( B...:.l
),
b~tween
U-2;;: and U-24.
(see the conlPonent 1 a··... out dr'awi ng) The
output is
IlLS" TTL compatible and
is capable of driving an
equivalent
load.
The status of the user defined output
is
determined by data written to bit 4 of either the TASK SELECT
REGISTER or the BANK SELECT LATCH depending on which is installed.
I f a l i s wr' itt e nth e (. u t put at pad A W ill be h i 9 h , when a (> i s
written it will be l(.w.
Th-e (flJtPUt of the user' d-efirled latch c(luld
t (.
COIJld
b-e us-ed in a variety of ways.
For e~amFle, 1. ....I.
driv-e an ext-ernal indicator ( LED, buzzer',
It
etc.
) to indicate some internal condition of the s·(stefll.
could als~ b-e used,
if wir-ed correctlv,
as a second software
control latch input to the FPLA address decod-er.
II
II
::;:oftIi.1ar·e that uses th-e user defined latch must not modifv the
either bi ts in the TASK SELECT REGISTER,or BANK SELECT LATCH if thev
are being used.
See the appropriate sections of the manual for
details on the bit positions in the TA::::I< !:::ELECT REOI!;::TER and BANI<
SELECT LATCH, and the precautions re9uired for software that writes
to them.
ON CARD DEVICE SECTION
FPLA Address Decoding:
Address
decoding
for
the eight on card devices ( 4
PROM/ROM/RAM sockets, 5::::167 Time oi: Day Clock,
6:340 F'r·c.gammable
Timer,
9511A/9512 Arithmetic Processor and th~ on boafd RAM) is
controlled by a Field Programmable L09ic Array
(FPLA).
The
address~s
occupied by each of the 8 devices are fixed bv the
pro9rammin9 of the FPLA.
The FPLA has sixteen input
lines and
eight output 1 ines arid can be pr'ogr'amrrlE-d for' UP to for·tY-eight
different input to output combinations.
Twelve of the input
lines
ar'e connected to addr'ess 1 irles A4 .- A15 thus E-nabl irlg the FPLA to
decode address ranges as small as 16 bvtes.
The remaining 4 inputs
are connected to DIP-switch S2. sE-ctions 1 though 4.
Sections 1 3 directly control their respective FPLA inputs.
An ON (closed)
switch equals a l09ical 0 to the FPLA. an OFF (open) switch e~uals
a logical 1 to the FPLA.
Section 4 connects the remaining FPLA
input to the output of a softw~re co~trolled l~tch.
The output of
this latch is determined bv the data stored in bit 5 of either task
select re9ister or the bank select resister dependin9 on which
.:.ption is installed.
When 82--4 is ON (clos€:d) the data st(.red ir.
the
latch det€:r·mir.es the
inplJt to thl2 FF'LA when !;;:2-4 is OFF«.pen}
the input rE-mains hish (10g1.:.::;1 1).
This cl:..mbir,ati.HI of switch
..;
~r
GIMIX,
INC.
-1 :;::--
t.::;:09 CPU BC)ARD
latch inputs allows both hardware and software selection of address
decoding for the on card devices.
Each of the 8 FPLA outputs connects to the select logic of one
of the 8 on card devices.
Each device also has a separate disable
switch, DIP-switch S1 sections 1 throush 8. that
can be used
to
disable
that
device
regardless
of the FPLA programming.
When a
device is disabled by these switches its address space is available
for use by other
devices.
The FPLA supplied with the GIMIX 6809 CPU BOARD is
programmed
several
different addressing combinations.
Combinations are
includ~d for several different existins PROM/ROM
monitors.
Other
confisurations
are
included which
may
be
useful
in
special
applications such as
dedicated
systems and
monitor and
system
design.
An
addressing combination is selected by the settings of
the FPLA input switches S2 (1-4) and the software control latch
if
enabled.
A table is included with this manual that lists each of
the addressing combinations available in the FPLA as well - as
the
re~uired switch and latc~ settings for each combination.
Since one
of the inputs to the FPLA can be controlled
by software.
is
it
possible
to
select
between two different monitors under software
control.
It is also possible to install static RAM in one or more
of
the
PROM/ROM/RAM sockets. load a monitor into it from disk and
switch to the RAM monitor from the resident
PROM/ROM monitor. This
feature
is very useful when writing and debugging a custom monitor
or when it is desirable to easily and
rapidly
switch
between a
variety of different monitors.
Since the upper 256 bytes of memory
$FFOO through $FFFF are shared with
the DAT,
RAM addressed
at
between these locations
can not be written to.
with
NOTE:
The FPLA is a fusible link programmed
device and
r- e ~ u i r- e s
program.
Contact GIMIX. INC.
for- i n for- ma t i .:. n
on custom configurations to meet your re~uirements.
speciale~uipmentto
FPLA SOFTWARE CONTROL LATCH
When the board is configured
for
either
of
the 2
dynamic
address translation methods the FPLA latch is controlled by writins
to bit 5 of the
task
select resister
located at $FF7F.
When
configured
for
straight
bank
select
the latch is controlled by
writing to bit 5 of the bank select
latch at
$FF~F.
The FPLA
control
latch
shares
these
locations with the
task/bank select
functions and the user defined latch output.
Programs
that
write
to
the
FPLA latch must not inadvertently modify the other bits at
these locations.
Since the latch is a write only device
the
last
value
written
should
be kept in temporarY storage for comparison
p IJ r- p c. s e s when new d a t a i 5
t c. b"" wr' itt en.
::; e e
t h -;? a p p r- 0 p r- i ate
sections of the manual for more information on the task/bank select
functions and the user defined latch output.
Since
changing
the
FPLA
latch bit when the latch is enabled. DIP-switch 82 section 4
is ON (closed), may change the address of devices
decoded
by
the
FPLA, software that modifies this bit must be located in an area of
memory that is not affected by the"change.
EXTENDED ADDRESS DECODING:
C. I MI X,
I NC •
--14 --
Extended add~ess decoding is provided to allow the eight
FPLA
decoded
devices to respond to va~iou5 combinations of the extended
address lines as well as the ~egula~ address
bus.
An additional
decoding
circuit
called the Fxxx decoder is also available on the
board. The extended add~ess decoder detects
a
match
between
the
address
present
on
the
extended address lines ( A16 - A19 ) and
the extended address set by sections 5 th~ough 8 of
DIP-switch 82
(82 5-8).
The
Fxxx
decode~ detects the presence of an F on the
upper 4 lines of the
add~ess bus ( A12 th~ough A15).
Its
output
is
t~ue any time a
a read o~ write takes place to the upper 4K of
memory
(SFOOO-SFFFF).
The
outputs
of
these
decoders
can
be
combined
in
various
ways
by
the arrangement of the programming
Jumpers at Jumper area JA-l1.
And used to selectively enable
the
FPLA address decoder.
NOTE:
The extended
add~ess
decoding,
with
some exceptions as
descr ibed later, affects all of the devices dec(,ded by the r-PLA.
Figures A through G
sheet
2
of
the
SLui tch
and
diagrams
show the
pinouts of .JA·l1 and the
positions for the various combinations.
confi~uration
.j
.j
umpe r
UITIPer·
The
following
table
lists
the
combinations
that
can
be
selected by the Jumpers at JA-ll.
#1
FPLA always enabled (extended address and Fxxx decoders disabled).
#2
Only devices add~essed by the FPLA between SFOOO and SFFFF are
enabled regardless of extended address.
#3
FPLA only enabled when the extended address p~esented on the bus
matches the address set by the extended
addr·ess swit,:hes <:::;2 5--En. *
#4
Devices add~essed by the FPLA between $FOOO and $FFFF a~e always
enabled.
Devices add~essed below $FOOO respond only when the
extended add~ess matches.
#5
Only devices addressed by the FPLA between $FOOO and $FFFF a~e
enabled only when the extended address matches.
#6
FPLA always disabled.
In a singleuse~ application whe~e extended addressing is not
used
jumpe~ a~ea JA-l1 would no~mallY be set fo~ configuration 1 (
FPLA always
enabled
).
Configuration 2 effectively disables all
devices add~essed by the FPLA below $FOOO.
When configuration 3 is
used
devices
cont~olled by the FPLA only appear· on a single bank
as set by the extended address switches.
ConfigUration 4
allows
devices add~es5ed by the FPLA between $FOOO and $FFFF to appear in
all banks while those
addressed
below SFOOO only appear
in
1
specific
bank.
This configuration could be used fo~ example in a
bank select system whe~e the
system monitor and
scratchpad RAM
would appear in all banks while the othe~ devices would only appea~
in a specific bank.
Configuration 5 effectively
disables
all
devices
addressed by the FPLA below 'FOOO and only enables devices
addressed
between
$FOOO and SFFFF when
the
extended address
matches.
The last cConfiglJr·atior.. 1;.., Fern,anentl'·,·· disables The FPLA.
This configuration would be used if the system monitor
was
to
be
located on a separate board and none of the on card deviCES we~e to
be used.
GIMI X,
-15-
INC.
EXTENDED ADDRESS SELECTION
The extended address
for
the FPLA decoded
devices
is
determined
by the settin9 of DIP-switch S2 sections 5,6,7. and 8 (
825-B).
S2-5 cor-r-esPclnds to the least si9nificant bit
(A16)
clf
the extended address lines and S2-8 to the most si9nificant (AI9).
These switches must be set to the binary equivalent of the desir~d
extended address.
When the board is confi9ured for either STRAIGHT
BANK SELECT or GIMIX ENHANCED OAT a
switch
that
is ON
(closed)
corresponds
to a
1
in the apprropriate
bit
position of the
extended address, a switch that
is OFF (open) corresponds to a
O.
When
the SWTP compatible DAT
is
installed
the
switches are
inverted, ON (closed) corresponds to a 0 and OFF
(open)
to a
1.
The
followin9
dia9ram shows examples of extended address settin9s
for S2 5-8 with both GIMIX ENHANCED DAT / STRAIGHT BANK SELECT and
the SWTP compatible DAT.
SWTP compo
:':;WTP COMPo
GIMIX OAT /
S2
GIMIX DAT /
SECTION
BANK SELECT
DAT
DAT
c-
~I
6
7
,-,
Co
ON
OFF
OFF
OFF
OFF
ON
ON
ON
EXTENDED ADDREES:':; SET
FCm BANI< $01
orF
ON
ON
OFF
ON
OFF
OFF
ON
EXTENDED ADDRESS SET
FOR BANI::: $O.~,
NOTE: The settin9 of the extended address
switches
is
only
necessary
when
Jumper
area JA-ll
is
set
for
one of
the
confi9urations that use extended addressin9.
Configurations 3,4,
and 5 use the extended address decodin9 and DIP-switch 52 sections
5 throu9h 8 must be set to
the
desired address.
Confi9urations
1,2,
and 6
i9nore
the extended address and the switch settin9s.
See the EXTENDED ADDRESS DECODING section
for
details of
these
confi9ur-ations.
PROM/ROM/RAM SOCKETS:
The board has four 24 pin ~ockets ( U-4,5,6, and 7
)that
can
accept
most 2708/2716 pinout compatible, 1 to 8K byte PROM/ROM/RAM
devices.
Either sin9le or multiple supply voltage
parts can
be
used and each of
the
four
soc~ets
can
be individualy Jumper
pro9rammed for device size and type.
Jumper
areas
located above
each socket ( JA-2,3,4.and 5) rearrange the pinouts of the sockets
as required for the various devices.
The device size and address
location for
each socket is determined by the pr09rammin9 of the
FPLA address decoder.
(see the FPLA SEction of the manual and
the
FPLA DATA sheet
for
information on
device
size and address
locations).
Custom programming of
the FPLA allows an ~lmost
unlimited
number of combinations to be used ( please contactGIMIX
for information on custom FPLA programmin9
if your application
requires combinations not available in the standard FPLA sUPFlied).
GIMIX,
INC.
-I/.:.-
The
PROM/ROM/RAM Jumper
configurations
drawing
shows
the
pinouts
of the Jumper areas and 9ives examples of Jumper positions
for the most common devices that can be used.
GIMIX will
provide,
on
re~uest,
information on the suitability and Jumper pro9rammin9
for devices not listed on the drawin9.
Each
of the 4 PROM/ROM/RAM sockets can be individualy enabled
or disabled bv DIP-switch Sl sections 1,2,3, and 4.
When enabled a
socket occupies the address space determined for it by the FPLA and
when disabled that
address
space
is
made
available
for
other
devices
in
the
system.
The
sockets
are
enabled
when
their
associated switch is ON(closed) and disabled when it is
OFF(open).
Sections
1,2,3,
and
4
correspond
to
sockets
U-4,5,6,
and
7
respectively. :3ee fi9ur'e 1-1=
sheet
1 of
the
switch
and
.jumper
confi9uration drawin9s.
The
speed
re~uirements
for
devices
installed
in
the
PROM/ROM/RAM
sockets
depends
on
the
speed
of
the
CPU.
When
operatin9 at 1 MHz.
devices with an access time
of
615
ns.
or
les5 are re~uired.
1.5 and 2 MHz.
operating speeds re9uire 360 ns
or' less and 240 ns.
or' less
devices
r·espectivel··....
NCnE:
Thes<Ec'
fi9ures
take into account d<Ec'lays intrQduced bv the DYnamic Address
Translation RAMs.
In systems that do not use the DAT
the
fi9ur<Ec's
can b<Ec' increased by approximatelv 40 ns.
For example without DAT a
IMHz.
system r<Ec'9uires devices with an
access time of 655 ns.
or
less.
SCRATCH PAD RAM
The
board
has
provisions an optional lK bvtes of scratchpad
RAM. The 2 sockets( U-8 and U-9 } will accept anv 2114
compatible
RAMs
includin9 CMOS types and has provisions for batterv backup of
this RAM when CMOS devices are used and the time of day clock
with
batterv backup option is installed.
The addressin9 of the scratchpa1 RAM is determined bv the FPLA
address
decoder (see the FPLA section of the manual).
The address
at which the RAM appears dep<Ec'nds on the programming of the FPLA and
the
settin9s
of
the
FPLA
input
switches and software control
1 atch.
The
scratchpad RAM can be disabled by DIP-switch SI section 8
(Sl-8).
When this switch is ON(closed}
the
RAM
is
enabled as
determined by the FPLA.
When Sl-8 is OFF(open) the RAM is disabled
and can rl(.t appear in the addr·2ss space.
See figur'e 1-1: sheet 1
of
the switch and Jumper
confi9uration drawin9s.
If 2114 e~uivalent CMOS parts are installed at U-8 and 9,
and
the
battery backup clock option is installed, Data is retained in
th'2
5cratchpad RAM when the
sYsterrl Fower
is
turned
off.
Th.:NMOS/CMOS RAM
option Jumper JA-7 connects the U-8 and 9 to either
the regular +5
volt
supplv or
to
the
batterv backuF
sUFFlv.
CAUTION:
JA-7
MUST NOT BE SET TO THE CMOS POSITION UNLESS CMOS
MEMORYS ARE INSTALLED
When the JA-7 is set for CMOS RAM and
the
batter'Y
on/e.ff JWTlPer ( ..JA-b) is iri the Of, positior.? s(II:Lets UE: arid
CiIMIX,
INC.
-17-
9 ar'e alwa·...·s pOuH:~r'ed, even if the b.;:,ar·d is r'eITI')v<2d fr'om th<2 s··... steHI.
BE SURE THAT THE BATTERY .JUMPER .JA-;~. I:::; IN THE CWr- PC):::;ITIOtJ OR T:lAT
JA-7 IS NOT JUMPERED FOR CMOS RAM BEFORE REMOVING OR
INSTALLING
PARTS ATU-8 and 9.
Jump<2r areas JA-6 and 7 are located in the
upper risht corner of the board to the left of
the
batterv.
See
fisures
C and
F:
sheet 1 of the switch and Jumper confisuration
drawings for the configuration of these Jumpers.
To
insure
data
intesritv,
an unsafe voltage detect circuit
inhibits all write operations to the scratchpad RAM when it
senses
the
loss
of
system power.
This prevents false writes to the RAM
during the transition from svstem to batterv and batterv to
svstem
power, wh<2n the batterv backup option is used.
9511A/9512 Arithmetic Processor:
E i the r' t h <2 9511 A 0 r 95 12 a r' e a va i 1 a b 1 e as 0 p t ion s 0 rl the G I MI, X
6809 CPU board.
The 9511A/9512 are
extr<2melv
fast
and
pow<2rful
devices
for
performing mathematical
calculations.
The 9511A
offers
16 and
32 bit
fixed-point
and 32
bit
floatins-point
arithmetic and
a
varietv of
transcendental
functions.
Thes<2
functions are:
Sine, Cosine, Tansent, Arc Sine,
Arc
Cosine,
Arc
Tansent, Square, Square Root, Common Los, Natural log, Natural Anti
Los, exponentiation, and a 32 bit floating PI.
The 9512 offers
32
and
64
bit
floatins
and
fix<2d
point addition,
subtraction,
multiplication
and
division
but
none
of
th<2
transcend<2ntal
functions.
The use of th<2s<2 devices can take much of the burden of
mathematical calculations off of the processor.
The processor
can
load data into the 9511A/9512, issue th<2 necessarv command and then
either poll the status bit of the part or perform other tasks while
waitins
for
the
part to senerat<2 an interrupt. and then r'<2ad th<2
results from the prOP<2r resist<2r.
The 9511A/9512 occupies 16 bvtes of address spaC<2, its addr<2ss
is d<2termined bv the FPLA prosrammins and FPLA input
switches and
software
control
latch.
The first bvte is th<2 data resister and
the second bvte is the
status
resister,
for
example
if
th<2
9511A/9512 W<2re addressed from $E200 throush SE20F.
Th<2 data
resister would appear at locations SE200, $E202. etc.
and the data
resister would appear at SE201, SE203, etc.
Both d~vices are stack
oriented and have onlv two 8
bit
wide
resisters.
The
data
is
~ritten
to them 1 bvte at a time, a command issued, and the result
is read from them a bvte at a time.
CAUT I ON:
I N ORDER TO MEET THE TIM I NCi F,E()U I F,EMENT::; OF T~ IE
9511A/9512 THE MRDY CIRC::IJITRY OF THE CPU BOARD I:;:; U~::;ED TO ::;TRETCH
THE PROCESSOR CLOCK DURING ACCESSES TO THE DEVICE.
BECAUSE OF THE
WAY 9511A/9512 FUNCTIONS IT IS POSSIBLE IF CERTAIN PRECAUTIONS ARE
NOT OB::;ERVED TO GENERATE A MRDY :::IGNAL THAT I:::; LONGER THAN .THE 6:::09
CAN TOLERATE.
THIS COULD CAUSE UNPREDICTADLE RESULTS AND POSSIBLY
CAUSE THE ENTIRE SYSTEM TO "CRA::::H".
TO AVOID THIS, SOFTWAF'\E THAT
READS THE RESULTS OF A 9511A/9512 OPERATION FROM THE DATA REGISTER
MUST NOT DO SO UNTIL THE DEVICE HAS COMPLETED THE OPERATION.
THIS
CONDITION CAN ALSO OCCUR IF A ==;ECOND COMMAND
I::; l·JRITTEtJ TO THE
DEVICE BEFORE THE PREVIOUS OPERATION IS COMPLETED .
•
GIMIX,
INC.
--1 :::--
(;.::::09 CPU· BOARD
THE COMPLETION OF AN OPERATION CAN BE DETERMINED BY READING THE
STATUS REGISTER OF THE DEVICE OR BY WAITING FOR THE DEVICE TO
GENERATE AN END OF OPERATION INTERRUPT BEFORE ATTEMPTING TO READ
THE RESULT FROM THE DEVICE.
THIS PRECAUTION IS NOT REQUIRED WHEN
WRITING DATA TO THE DEVICE OR WHEN READING THE STATUS REGISTER.
See the manufactu~ers data sheets and the sample program
listings, included when the 9511A/9512 are facto~y installed,
for
info~mation
on
data for~ats and prog~am requi~ements fo~ thes~
devices.
9511A/9512 clock speed
The clock speed of the 9511A/9512 is totallY independent of
the 6809 p~ocessor clock.. They share the same Jumper area (JA-8)
for clock speed selection but there are no rest~ictions other
than
the maximum operating speed of the parts, on 6809 and 951A/9512
clock speed combinations.
For example th~ 6809 can be operated at
1 MHz.
while the 9511A/9512 is r-IJnning at :::: MHz or- -the 6::::0';J at 1.5
MHz.
while the ':;'511A/9512 is set for- 2 1'1Hz.
etc.
Cl cick speeds of
2,3,
and 4 Mhz.
a~e
available at JA-8.
clock speed fo~ the
device.
Various ve~sions of both devices are available with
different makimum operating speeds.
Jumper area JA-8 5hould not be
set fDr a speed hishe~ than the ratins of the part.
Fisures A throush H:
sheet 3
of the switch and JumFer
confisuration drawinss show the pinouts and Jumper positions
for
.JA-8.
9511A/9512 interrupt selection
The 9511A/9512 is capable of seneratins interrupts.
The
interrupt output of the device can be connected.
b~
JumFer area
JA-12, to anYone of the three 6809 hardware inte~rupt lines ( NMI,
FIRQ, and IRQ).
NOTE: The NMI line at JA-12 is only active when
the NMI
option Jumpe~
( JA-13) is in the NMI to bus position.
(See the NMI option Jumpe~ section)
An additional Jumper a~ea JA-9
must be set ~o eithe~ the 9511A or 9512 position depending on which
part is installed.
This jumpe~
is ~equired
because of
a
diffe~ence
in the inte~rupt outputs between the 2 devices.
JA-12
is located in the lower left of the board to the lef~ of U-33.
Fi9u~e
H:
sheet 2 0 f the switch and Jumper confisuration
drawin9s shows th~ pinouts of JA-12.
Jumper area JA-9 is
located
below the 9511A/9512 socket U-3.
Fi9u~~ D: sheet 1 of the switch
and Jumper
confisuration d~awin9s shows the jumpe~ positions
for
,JA-9.
9511A/9512 enable/disable switch
The 9511A/9512 can be disabled by DIP-switch 81 section 7 (
the device
is enabled as
SI-7
)•
When SI-7 is ON(closed)
determined by FPLA.
When 81-7 is OFF(open) the device is disabled
and its memory SFace is available for other devices in the system.
en MI X,
I NC •
6840 Pro9rammable Timer:
The 6840 Pro9rammable Timer has 3
independent.
software
programmable
timers that can be used for
timing,
counting,
freque~cy and period measurement. etc.
The 3 timers can be used
independentlY or they can be cascaded in various ways depending on
the application.
The input. output, and gate connections for all 3
timers are available at a Jumper area (JA-1).
This Jumper area can
be used with Jumper blocks and/or standard wire wrap techniques to
interconnect
the
timers,
or with the appropriate connector (not
supplied) to connect them to external
devices.
A 1MHz.
clock
output is also available at JA-1.
6840 addr-essing
The 6840 occupies sixteen bytes of address space as determined
by the programming in the FPLA and the FPLA input
switches a~d
softwar'e contr'ol
latch.
The following
table ShOliJ5 the
b·,..te
assignment with byte 1 being the lowest address assigned to
the
device.
nead
Wr' i te
No Defined Operation
B··... te 1
Wr' i te CClntr'ol Re9 i ster' #1/#3
Read Status Register
R·,..te 2
Write Contr-o 1 Reg i ster' #2
"':1
B··,..te '-'
Read Timer #1 Counter
Write M:;:;B Buffer' Register
B··,..te 4
Read LSB Buffer Re9ister
Wr' i te T i rr,e r- #1 Latches
,_I
Read Timer #2 Counter
Byte r=
Wr' i te M::::B Buffer- Reg i s ter'
Read LSB Duffer Register
B·'I··te 6
Write Timer' W-:' Latches
B··,..te 7
Read Timer #3 Counter
Wr- i te MSB BIJffer' Register
Read LSB Buffer Register
Byte ,-,
Wr- itt' Timer' #'0'-';;' Latcht's
c'
''':''
The remaining 8
bytes art' a repeat of the first 8 bytes listed
above, i.
e.
Byte 9 is the same as Byte 1, Byte 10 is the same a5 Byte
See the 6840 manual
included with the boa r' d
for'
detailed
information on the functions of these b··,..tes and on programming and using
the 6840 programmable timer.
6:340 i nter-r-upt s
The interrupt output of the 6840 can be Jumpered to anyone of the
three
interrupt lines (NMI,FIRQ, and IRQ) by the programming Jumpers at
Jumper area JA-12.
NOTE: The NMI line at JA-12 is only active when
the
NMI
option Jumper JA-13 is in the NMI to bus position. (see the NMI
option Jumper section) JA-12 is located at the lower left of the
board
to
the
left of U-33.
Figure H:
sheet 2 of the switch and Jumper
configuration drawings shows the pinouts of JA-12.
6840 enable/disable
The 6840 can be disabled by DIP-switch SI section 6 ( 81-/:.. ).
(; I MI X,
INC.
-20-"
81-6 is ONCclosed) the 6840 is enabled a determined by the FPLA.
When
81-6 is OFF(open) the device
is
disabled and
its memory space
IS
available for other devices in the system.
6840 accurac...·
Regardless of whether the 6840 uses the internal clock reference or
an external one, the device uses the
(E)
signal
from
the 6809 for
internal
syncronization.
Since this
eEl
signal is stretched by the
processor during slow memory accesses using the MRDY line
the accuracy
of
the
device may be affected if such accesses (slow memory) are made
while the 6840 is counting.
Under normal circumstances this effect will
be
negligible.
However. in applications where timing is critical and ~
great deal of slow memory accesses are made this should
be ta~en
into
c 0) n sid e r' a t ion.
58167 Time of Day Clock
The 58167 Time of Day Clock option provides the user with any easy
rrleans of keeping time ( secorlds, minutes, l"H.ur=., da:'( (,f week,
day of
month,
month of year)
in
the system.
It also provides pro9rammable
interrupt capability.
The battery backup feature allows
the
clock
to
maintain accurate
timekeeping even when the sYstem power is removed.
The device has its own built in oscillator and a separate crYstal and is
independent of processor clock speed and timing.
5:3167 addr'es s i rig
The 58167 occupies 32 bytes of address space as determined by the
programmin9 of the FPLA,
and the FPLA
input switches and
software
control
latch.
The following table shows the byte assignments for the
58167 with byte 1 being the lowest address assi9ned to the device.
B",··te 1
Byte "'Byte ':'
"-'
B··f··te 4
~,
B ....·te
r:::-
B'...·te
B··..-te
Byte
B'·..-te
B"·(te
B·... te
Byte
Byte
Byte
Byte
B"·{te
B,,·te
1.:..
~I
7
(j
'....
9
10
11
1 .-,
"-
1 ,:.
14
-'
15
1(:,
17
Count'2r' COIJnter' Counter'
(:0 u n te r' Counte r'
Counter'
C:ounte r'
COIJnt<2r Latches Latches
Latches Latches -Latch,2S
Latches Latches Latches I r. t e r' r !j p t
Thousandths of ::;;e c 0 rl ds
Hundr'edt h s and Terlths of :=;(?conds
::;;econds
Mi nute.s
Hour's
Day of the We,::k
[l,a:·,.. (of th\? Month
Mc(nths
Thousandths. ( I f ::;;e c () fa oj s
HlJndr..?dths and T..?nths of 8ec()r.ds
Si!,:ortd~.
Minutes
HOIJr's
Day of the Week
Da"( of the Month
Me.r. t h:s
::;;tatus r';i:'9ist-2r
GH1I X
-21-
INC.
7
B··,··t e
Byte
B ...·te
Byte
Byte
Byt€
B··... te
18
19
20
21
22
-,.-.
L"':'
24
*
*
*
6::::09 CPU BOARD
Int€rrupt Control Register
Coun ter· Re se t
Latch reset
!:;tatus Bit
"GO" CClmmand
Standby Interrupt
Undefined
e9ar·d 1 es
*
*
*Undefined
Test Mode
NOTE: Bytes 24 throu9h 31 ar€ undefin€d and not used. They ar€ decoded
by the board and ar€ not available for other devices when the 58167 is
enabled.
58167 programmin9
is BC:D
The data format of the time counters ( bytes 1 thr·ough ::: )
(binar·y coded decimal), two digits per· byte.
These counters are used to
The remaining bytes
S€t th€
time as well as read time from the device.
use a
binary format and are used to program he devices interrupt output
as well as read status,reset the counters, etc.
Basically, settins
the
clock
requires resettin9 the counters to zero by writin9 to the counter
reset byte (byte 19), storin9 the time in BCD format in the
counters
MINUTE throu9h MONTH), and then writin9 to the GO byte
(byte 22).
The
58167 data sh€et included when the clock option
is
purchased
contains
detailed information on settin9 the the clock and usins the pro9rammable
interrupts.
Sample pr09rams, included with this manual, 9ive examples
of setting and readin9 the clock.
NOTE: THE 58167 HAS A STATUS BIT THAT IS SET WHENEVER THE COUNTERS
CHANGE
(ROLL OVER)
WHILE THE TIME IS BEING READ.
THIS BIT SHOULD BE
TESTED AFTER A HEAD FROM THE DEV I CE AND THE DATA RE·- HEAD I F THE BIT
I:;:;
SET.
THIS IS TO INSURE THAT THE DATA READ IS VALID.
THE STATUS BIT IS
CLEARED BY READING THE STATUS.
58167 interrupts
The int€rrupt output from th€ 58167 can b€ conn€cted to anyone
of
the thr€e 6809 hardware interrupt lines by pro9rammin9 Jumpers at Jumper
ar€a JA-12.
NOTE: The NMI int€rrupt line at JA-12 is only activ€
when
the
NMI
option Jumper JA-13 is in th€ NMI to bus position. (see the NMI
option Jumper section) Fi9ure H:
sheet 2
of
the
switch and
Jump€r
confi9uration drawin9s shows th€ pinouts of JA-12.
Ba tt€r·Y backup
the 58167 time
of
day clock option is a batt€rY
Included with
the
s"{sten, power
is
backup circuit that k€eps the clock rlJnrllf.s wher,
- .-.
~ ..-.
, ...-. .4
13 I MI X,
INC.
-22-
(:,809 CPU BOAr,[I
This battery circuit
can also
be
used
to
retain
data
in
the
lK
is
installed.(see
the
lk
scratchpad RAM
if
the CMOS RAM option
battery backup
system consists
of
a
scratchpad RAM section)
The
rechargeable nickel-cadmium battery and associated char9in9 and unsafe
voltage detect circuitrY.
Batter"", char9in9
The char9in9 circuit charges the battery whenever system power·
is
applied
to
the
board and
the
battery on/off Jumper JA-(:' is in the
battery on position.
The
batterY used
is
desi9ned
for
continuous
chargin9 and can not be overcharged.
CAUTION: When the battery on/off Jumper
is
in
the
battery
on
positiofl
power·
is aFPl ied to the 58167 socket (U·-l) at all tirrtes, even
when the board is r·emoved fr·om the systerrl.
The same is tr·ue fe,r· ttle
1K
scratc~Fad
RAM sockets U-8 and 9, if the CMOS/NMOS RAM option Jumper is
in the CMOS RAM position.
(see
the
1K scratchpad
section)
Before
removing
or installing parts in these sockets the battery on/off JumFer
should be placed in the e,ff positiQn e,r· damage tQ the par·ts may result.
The
batter··...· on/off .jumper· .JA-b is le,cated tel the left of the batter···,··.
Fi9ure F: sheet 1 of the switch and Jumper cQnfi9uration drawin9s shows
the Jumper Fositions for JA-(:'.
Unsafe voltage detector
The unsafe volt~ge detector monitors the unre9ulated +8 volt supply
from the bus.
If the bus voltage
falls
below a
pre-set
level
the
circuit
holds
the
processor in a reset state ( reset line low) places
the 58167 in its PQwer down mode ( PD low> and inhibits writes
to
the
scratchpad RAM.
This
prevents false accesses to these devices durin9
planned or unplanned power losses.
When the voltage returns to a
safe
level
the
reset
state is released ( th~ processor perfo~ms its normal
power on reset sequence) and t~e clock and RAM are
restored
to
normal
c,per·a t i on.
Unsafe voltage threshold adjust
The voltage at which
the
unsafe
voltage detector activates is
determined by the setting of R-24, which is located near the heats ink in
the lower- left cor·ner· of the bc'ar-d.
This adJustnterltis factor'Y set at a
voltage Just above the point where the on board voltage regulators
fall
out
of
re9ul~tion,
approximatelY
7.1
volts and
should not
need
readjustment
under
normal
ci~cumstance5.
NOTE:
In certain
S5-50
systems with mar9inal power supplies. the bus voltage maybe too low to
allow proper operation of the GIMIX 6809 CPU board.
These systems will
require modifications
to
their
power
supplies to provide sufficient
vo 1 tage. The bus vo 1 tage of the s', s telll shou 1 d
be
somewhat abclve
the
settin9 L': of
the
unsafe
voltase
threshOld
to
provide
for
normal
voltage
___
,
•
_.L...
~._
cJa
GIMI X
7
INC.
Normal operation of the GIMIX 6809 CPU board cannot be 9uaranteed if the
udt";::' r e
unsafe voltage threshold is lowered from the factorY setting or
the bus voltage
is
insufficient to
provide proper operation of the
c i r' cu it.
GIMIX 6809 MEMORY MAP
=:::TARTING
ADDRE::::::::
ENDINf3
ADDRE=;::::;;
DESCRIPTION
$F800
$FFFF
'3MXBUG-09
$F400
$F7FF
VIDEO PROt1 OR USER PROM
$FOOO
$F;;:FF
USER PROM ( ... l .... COMMAND)
$E800
$EFFF
VIDEO RAM (80 X 24)
$E400
$E7FF
ON CARD SCRATCH PAD RAM
$E3FC
$E3FF
VIDEO BOARD REGISTERS (80 X 24)
$E3F8
$E3FB
UNDEFINED, AVAILABLE TO USER
$E3BO
$E:3F7
RESERVED FOR FUTURE GIMIX USE
$E:;:A8
$E;::AF
GRAPHIC::: CARD
$E240
$E:3A7
UNDEFINED, AVAILABLE TO USER
$E220
$E2;;:F
58167 ON CARD DEVICE
$E210
$E21F
6840 ON CARD DEVICE
$E200
$E20F
9511A/9512 ON CARD DEVICE
$E100
$E1FF
UNDEFINED. AVAILABLE TO USER
$E070
$E07F
1/0 PORT 7
$E060
$E06F
1/0 PORT 6
$E050
$E05F
1/0 PORT
$E040
$E04F
1/0 PORT 4
$E030
$E03F
I/O PORT
$E020
$E02F
I/O PORT 2
$E010
$E01F
I/O PORT '1
$EOOO
$EOOF
1/0 PORT 0
$COOO
$DFFF
USER RAM (GIMIX FLEX)
$0000
$BFFF
USER RAM
c-
...J
.-.:.
-'
THIS MEMORY MAP IS FOR GMXBUG-09.
THE FOUr< FPLA SWI1CHE.::S
ARE IN THE OFF (OPEN) POSITION AND THE PORTS ARE CONFIGURED
FOR db BYTES PER I/O ADDRESS.
NOTE:
THIS IS A GENERAL MEMORY MAP, SOME DEVICES MAY
NOT BE PRESENT IN YOUR SYSTEM.
GIMIX 6809 CPU BOARD FPLA
GENERAL INFORMATION
The FPLA (Field Programmable Logic Array) provides address decoding for
the
8 memory mapped devices (scratchpad RAM, arithmetic processor, PTM (6840),
time-of-day clock (58167), and PROM/ROM/RAM sockets U-4 through U-7) on the CPU
board. Each FPLA is pre-programmed with several different configurations which
are selected by setting DIP~switch S2 sections 1 through 4 on the CPU board.
Software
selection of FPLA configuration is also provided by the FPLA software
control latch bit on the CPU board. Each configuration places the 8 devices at
specific addresses, as indicated in the FPLA configuration sheet(s). The address
configurations are chosen to provide features such as; compatibility with existing
hardware/software combinations, software
and/or hardware selection between two
different PROM/ROM resident system monitors or operating systems, software
selec'tion between a PROM/ROM resident monitor and a RAM resident monitor (for
monitor developement/debugging), etc.
HARDWARE SELECTION BETWEEN TWO MONITORS
When this type of configuration is used, two different PROM/ROM resident
monitors can be installed on the CPU board. Depending on' the switch settings, the
socket(s) for one or the other of the monitors will always be enabled at
the
appropriate addresses and 'the other socket{s} will be disabled. To switch to the
other monitor, the appropriate switch must be changed and the system reset.
SOFTWARE SELECTION BETWEEN TWO MONITORS
This type of configuration is similar to hardware selection except that the
monitors are switched by writing the appropriate value to the FPLA software
control latch bit on the CPU board. To use this type of configuration, a speCial
program or
operating system utility, that must reside outside the address range
affected by the switch," is used to change the control latch bit and jU1D.P to the
beginning of the new monitor.
Since the control latch bit is set to "0" on
power-up or reset, this type of configuration always defaults to the monitor
selected by "0" on power-up and reset.
SOFTWARW SELECTION BETWEEN PROM AND RAM MONITORS
This type of configuration, like the previous one, switches between two
monitors under software control. Unlike the previous configurations however; when
the primary monitor (selected by setting the control latch bit "0") is active, the
socket(s) for the second monitor are relocated to another area in the address
space instead of being disabled. This permits the second monitor to be loaded
into RAM and then software switched into use.
MISCELLANEOUS CONFIGURATIONS
These configurations provide various combinations of device size and
for special hardware configurations and user-defined applications.
-a. 1-
address
HARDWARE CONSIDERATIONS
After a configuration is chosen, the FPLA switches, S2-1 through 4, should be
set to match the the settings shown on the configuration sheet and the desired
memory devices installed at the locations indicated.
Be sure that the jumper
areas above each PROM/ROM/RAM socket (JA-2 through JA-4) are set for the proper
device size and type. Any unused sockets and devices (9511/9512, scratchpad RAM,
PTM, Time-Of-Day clock) should be disabled by turning OFF (OPEN) the appropriate
section of DIP-switch S~I. Some configurations require other special hardware
considerations. For example, when software selecting between GMXBUG-09 and OS-9
the 74LS174 latch on the CPU board must be installed at location U-23, even if no
DAT is installed on the board. This locates the FPLA SOFTWARE CONTROL LATCH at
the proper address for OS-9. NOTE: when the CPU board is configured this way, and
no DAT is installed, the extended address decoding should be disabled on all
boards in the system.
SOFTWARE CONSIDERATIONS
The program that does the actual switching between two software selected
monitors must reside outside the address range affected by the switch. The
program should first set the FPLA software control latch to the proper value, "I"
or "0" and the jump to the entry point of the new monitor. Some monitors, such as
GMXBUG-09, set the FPLA software control latch bit as part of their normal
initialization proceedure.
GMXBUG-09 sets the bit to a "0". If GMXBUG-09 were
installed as the second monitor (selected by writing "I" to the latch) it would
switch the system back to the primary monitor as soon as its initialization
routine set the bit to "0". GMXBUG-09, unless modified by the user, must be used
as the primary monitor. The secondary monitor must either set the FPLA softwre
control latch bit to a "I" during its initialization or not modify the bit at all.
-a.2-
GIMIX 6809 CPU BOARD FPLA #6
FPLA #6 is primarily intended to be used in systems that require hardware
and/or software switching between the GMXBUG-09/FLEX~
monitor/operating system
combination and the MICROWARE OS-9~ operating system. It also includes several
configurations that are useful for custom monitor developement and debugging.
GMXBUG-09/0S-9~
SWITCHING
The GMXBUG-09 PROM should be installed at location U-4 on the CPU board. The
appropriate BOOT PROM, such as the GIMIX AUTOBOOT or BOOT/VIDEO PROM should be
installed at U-5. The OS-9~ PROMS, P-l and P-2, should be installed at locations
U-6 and U-7 respectively. Interrupts on the CPU board, disk controller, and I/O
boards must be enabled as described in the installation instructions included with
OS-9~
(see the sections below for more information on interrupts). Either
hardware or software switching can be selected by setting DIP-switch S-2 as shown
in the appropriate section of the FPLA #6 configuration sheet. NOTE: Software
selection can only be used in systems that use the GIMIX #58 PIO or #68 DMA disk
controllers. The #28 PIO controller cannot be used for software selection because
it does not have software interrupt enable/disable.
HARDWARE SELECTION
If hardware selection is chosen, the system will default to one of the two
monitors, depending on the setting of S2 section 3. If S2-3 is set OFF (OPEN),
GMXBUG-09 will be selected on power-up and reset. IF S2-3 is ON (CLOSED) OS-9~
will
be
selected on power-up and reset.
When switching from OS-9~ to
GMXBUG-09/FLEX~ the interrupts required by OS-9~ must be disabled or
FLEX~
will
not function properly. In most cases the interrupts can be disabled by turning
the system off when switching to GMXBUG-09.
Turning the system off will not
disable interrupts from the TlME-OF-DAY CLOCK (58167) on the CPU board or from a
#28 DOUBLE DENSITY PIO disk controller. The interrupt output from the 58167 1S
disabled automatically by GIMIX AUTOBOOT versions 1.1 and later. If a different
boot PROM is being used, the interrupt can be disabled manually by using GMXBUG-09
to write $00 to memory location $E23l before attempting to boot FLEXm. The
interrupt output of a #28 disk controller must be disabled by changing the jumper
on the controller board before attempting to boot FLEX~. It is not necessary to
manually disable the interrupts on the GIMIX #68 DMA disk controllers since they
are disabled
automatically when the system is turned off. The #58 PIO disk.
controller version of OS-9~ does not use interrupts from the disk controller.
SOFTWARE SELECTION
If software selection is chosen, and the CPU board does not have a DAT
(Dynamic Address Translator) installed, the 74LS174 latch must be moved from
location U-43 on the CPU board to location U-23. This places the
FPLA software
control latch at the correct address for OS-9~.
NOTE: when the 74LS174 is
installed at U-23 and no DAT is installed, the extended address decoding on all
boards in the system must be disabled.
In the software select configuration the system will always default to
GMXBUG-09· on power-up and reset. The GIMIX FLEX'" utility "0S-9.CMD" is used to
switch fromGMXBUG-09/FLEX~ to OS-9~. To switch from FLEX~ to OS-9~, execute the
utility "OS-9.CMD" from FLEX~. The program will prompt for the insertion of the
OS-9- disk in the proper drive and a carriage return. After the (cr) is entered,
the system will switch monitors and OS-9 m will be initialized.
-a.3-
An OS-9'" program, called "GMXBUG", is provided with OS-9'" for GIMIX systems.
This program is used to switch from OS-9'" back to GMXBUG-09.
When "GMXBUG" is
executed it disables the interrupt output from the 58167 Time-Of-Day clock on the
CPU board and clears the FPLA SOFTWARE CONTROL LATCH, causing the system to switch
back to GMXBUG-09. NOTE: Interrupts from the I/O board normally used by GMXBUG-09
are disabled when GMXBUG-09 re-initializes after the switch. If OS-9'" is using
I/O boards, other than the standard GMXBUG ACIA at port 10, their interrupts
should be disabled before attempting to re-boot FLEX'". This can be done manually,
using GMXBUG-09, or the necessary routines can be .added to the "GMXBUG" program.
The source code for the program "GMXBUG" is provided to permit user modification
if required.
Interrupts from the GIMIX 168 DMA disk controller are disabled··
automatically by the GIMIXbootstrap programs. If a user written boot for the #68
controller is used, it must disable the interrupts from the controller.
CAUTION: The "GMXBUG" switch program does not check the status of OS-9'"
before
switching to GMXBUG-09.
It is up to the user to determine that all active
processes have been completed and that it is "safe" to terminate OS-9'", before
"GMXBUG" is executed. Failure to observe this caution may cause loss of data and
possibly "damage" the OS-9'" disk(s) in use when "GMXBUG" is executed.
-a.4-
GIMIX 6809 CPU BOARD FPLA
CONFIGURATION SHEET FOR FPLA #6
SWITCH S2
SETTINGS
1
2
3
4
STARTING SIZE
ADDRESS (bytes)
DEVICE
Lt
THESE FOUR DEVICES APPEAR AT FIXED ADDRESSES AS SHOWN. THEY CAN BE
ENABLED OR DISABLED, AS REQUIRED, USING THE APPROPRIATE SECTIONS
OF DIP-SWITCH S-1 (SEE THE 6809 CPU BOARD DOCUMENTATION).
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
SCRATCHPAD RAM (2114)
ARITHMETIC PROCESSOR (9511)
PROGRAMMABLE TIMER (6840)
TIME OF DAY CLOCK (58167)
. $E400
$E200
$E210
$E220
lK
16
16
32
HARDWARE SELECT BETWEEN TWO MONITORS (GMXBUG-09 & OS-9)
GMXBUG-09
BOOT/VIDEO
OFF OFF OFF OFF DC
OFF OFF OFF OFF DC
PROM/ROM/RAM SOCKET U-4
PROM/ROM/RAM SOCKET U~5
$F800
$FOOO
2K
2K
OS-9 (P-l)
OS-9 (P-2)
OFF OFF ON
OFF OFF ON
PROM/ROM/RAM SOCKET U-6
PROM/ROM/RAM SOCKET U-7
$F800
$FOOO
2K
2K
OFF DC
OFF DC
SOFTWARE SELECT BETWEEN TWO MONITORS (GMXBUG-09 & OS-9)
GMXBUG-09
BOOT/VIDEO
OFF OFF ON
OFF OFF ON
ON
ON
0
0
PROM/ROM/RAM SOCKET U-4
PROMZROM/RAM SOCKET U-5
$F800
$FOOO
.2K
2K
OS-9 (P-l)
OS-9 (P-2)
OFF OFF ON
OFF OFF ON
ON
ON
1*
1*
PROM/ROM/RAM SOCKET U-6
PROM/ROM/RAM SOCKET U-7
$F800
$FOOO
2K
2K
$F800
$F400
$E800
$D800
2K
1K
2K
2K
\
2K MONITOR + SWTPe DMAF-2 AT $FOOO
MONITOR
USER DEF.
USER DEF.
USER DEF.·
OFF
OFF
OFF
·OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
DC
DC
DC
DC
DC
DC
DC
DC
PROM/ROM/RAM
PROM/ROM/RAM
PROM/ROM/RAM
PROM/ROM/RAM
SOCKET U-4
SOCKET U~5
SOCKET U-6
SOCKET U-7
SOFTWARE SELECT BETWEEN TWO 3KPROM MONITORS
MONITOR ~Fl
MONITOR #1
ON
ON
OFF ON
OFF ON
ON
ON
0
0
PROM/ROM/RAM SOCKET U-4
PROM/ROM/RAM SOCKET U-5
$F800
$F400
2K
lK
MONITOR #2
MONITOR #2
ON
ON
OFF ON
OFF ON
ON
ON
1*
1*
PROM/ROM/RAM SOCKET U-6
PROM/ROM/RAM SOCKET U-7
$F800
$F400
2K
lK
SOFTWARE SELECT BETWEEN 4K PROM AND 4K RAM MONITORS
(TWO 2K PROMs AND TWO 2K RAMs)
PROM MONITOR ON
PROM MONITOR ON
RAM (LOAD)
ON
RAM (LOAD)
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
0
U-4
U-5
U-6
U-7
$F800
$FOOO
$B800
$BOOO
2K
2K
2K
2K
RAM MONITOR
RAM MONITOR
ON
ON
ON
ON
ON
ON
1* PROM/ROM/RAM SOCKET U-6
1* . PROM/ROM/RAM SOCKET U-7
$F800
$FOOO
2K
2K
ON
ON
0
0
0
PROM/ROM/RAM
PROM/ROM/RAM
PROM/ROM/RAM
PROM/ROM/RAM
SOCKET
SOCKET
SOCKET
SOCKET
CONFIGURATION SHEET FOR FPLA #6
6809 CPU CARD FPLA DATA SHEET #FPLA-06
1
SWITCH S2
SETTINGS
4
2
3
DEVICE
Lt
STARTING SIZE
ADDRESS (bytes)
SOFTWARE SELECT BETWEEN 2K PROM AND 2K RAM MONITORS
WITH 2K BOOT PROM AT $FOOO
PROM MONITOR
BOOT/ETC.
RAM (LOAD)
OFF ON
OFF ON
OFF ON
ON
ON
ON
ON
ON
ON
0
0
PROM/ROM/RAM SOCKET U-4
PROM/ROM/RAM SOCKET U-5
PROM/ROM/RAM SOCKET U-6
$F800
$FOOO
$E800
2K
2K
2K
RAM MONITOR
BOOT/ETC.
OFF ON
OFF ON
ON
ON
ON
ON
1*
1*
PROM/ROM/RAM SOCKET U-6
PROM/ROM/RAM SOCKET U-5
$F800
$FOOO
2K
2K
$FCOO
$F800
$F400
$FOOO
IK
IK
IK
lK
$FOOO
$DOOO
$COOO
$BOOO
4K
4K
4K
4K
0
FOUR IK DEVICES FROM $FOOO TO $FFFF
ON
ON
ON
ON
#1
#2
#3
#4
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
DC
DC
DC
DC
DC
DC
DC
DC
PROM/ROM/RAM SOCKET U-4
PROM/ROM/RAM SOCKET U-5
PROM/ROM/RAM SOCKET U-6
PROM/ROM/~ SOCKET U-7
FOUR 4K DEVICES FROM $BOOO TO $FFFF
ON
ON
ON
ON
#1
IF2
#3
#4
ON
ON
ON
ON
OFF
OFF
OFF
OFF
= FPLA
DC
DC
DC
DC
DC
DC
DC
DC
PROM/ROM/RAM
PROM/ROM/RAM
PROM/ROM/RAM
PROM/ROM/RAM
SOCKET U-4
SOCKET U-5
SOCKET U-6
SOCKET U~7
t
L
*
THIS BIT CAN BE SET TO A 111" BY WRITING TO THE
FPLA SOFTWARE CONTROL LATCH (SEE MANUAL) OR BY
SETTING DIP-SWITCH S2 SECTION 4 OFF (OPEN). IF
S2-4 IS OFF (OPEN) THE BIT IS FORCED TO A "111
REGARDLESS OF THE VALUE WRITTEN TO THE LATCH.
DC
= DONIT
SOFTWARE CONTROL LATCH BIT (SEE MANUAL)
CARE
NOTE: UNUSED DEVICES AND SOCKETS SHOULD BE DISABLED,
USING THE APPROPRIATE SECTION OF SWITCH S-I,
TO PREVENT POSSIBLE ADDRESS CONFLICTS WITH
OTHER PARTS OF THE SYSTEM.
BATTERY ON/OFF //NMOS/CMOS RAM OPTION JUMPER
a
TIME OF
DAY CLOCK
OPTION
=
6840
PROGRAMABLE
TIMER
0
9511A OR
9512
ARITHMETIC
PROCESSOR
OPTION
U-4
1-8K
DEVICES
U-5
U-6
U-7
1-8K
DEVICES
1-8K
DEVICES
1-8K
DEVICES
j
~ :~~ O· OIDmD
( XTAL)
LGIMIX ENHANCED DATJ
,OPTION
'l
95='IIA;/;;;95:1;;2r.&JiQJ;;:;;~====~~ PROM/ROM/RAM
L -_ _ _~ SELECT
256x4
RAM
256x4
RAM
SOFTWARE
WRITE PROTECT
OPTION JUMPER
FPLA
o
o 0
CONNECTOR
I
~
-c:=J-
2c::::J
ADDRESS
DECODER
FOR
ON CARD
DEVICES
FPLA
OPTION
SELECT
SWITCHES
[email protected]~-~
o
DDDo
D
-c::::J-
~j .~
SOCKETS - - - - - - 1
JUMPER
(XTAL) JUMPERSII,I.5,2 MHz
6809/2.3,4 MHz 9511A/9512
~
r:J
'1~'4LJ
RAM
@ <;
n
o
6809
CPU
SWTP COMAIITIBLE
OAT OPTION
ON CARD DEVICE EXTENDED ADDRESS SELECT SWITCHES
o
,
I
L-.:>=~-B~A-/B-A~ OPTION JUMPER
O()
0000
20 BIT ADDRESS BUS BUFFERS
I
C D B
~ ~V
I D B
NAU
T T F
AF E A F
B E
B~ R
N UR
~
t
S
L -_ _ _~
GIMIX®
SS50/SS OC GOLD PLATED BUS CONNECTOR
GIMIX 6809+
FUNCTION LAYOUT
6809 CPU
.•
~
(
o
<j> 0
0
6
0
<j> <j> 0
0
0
bb
,
0
r0
0
0
000000 0
o
0
o
0
<j>
0
0
6
~ f - - - <j>, r - -
Q 0
If-6 0
600 6
0
A
,-,
B
~-,
/
\
\
0\0/0 0\0 0
\
o 0 0 o 0 Q
11-- :r-- :
6 0 0 600 6
Q
,
o
0
0
9
0
0
0
6 000
o<?J
..... '--- : rOO~
o
0
6 0
O.~ ?I o
~O
0
0
0
6, 9 0 0 0
l~ --;;-~ 6
r--- '
0
0
6
_.
IKX8
2708
TRIPLE SUPPLY
IKX8
IK X8
TMS2508
SINGLE SUPPLY
TMS2758-*
SINGLE SUPPLY
*
2KX8
2K X8
TMS2716
TRIPLE SUPf'
TI2516
12716
SINGLE SUPPLY
PARTS WITH - 0 SUFFIX
REQUIRE WIRE JUMPER 'A'
PARTS WITH -I SUFFIX
REQUIRE WIRE JUMPER 'B'
FIG. A
-
0
0
FIG.
o 0 0
6 6 Q o 0 Q,
'r---
?, 9,
000
o 0 0 0 0 0
: r--,.'. -- :
6
9, o ' -6- 0' 1---G 0 -0 o 0 6 0 0 0
0
6
0
0
0
6
4KX8
4Kx8
TMS2532
2732
FIG. F
jD
B
FIG. C
-
FIG. G
r r i TT
0
FIG.
o 0
? ? -?r0- -
0
6 6 0 0 6 0
0
o
I
0
6
0
8KX8
68364 (MOT)
68764 (MOT)
FIG.
H
0
0
0
FIG.
E
Q, 0
0
0 0
0
0
0
0
Q 0
Q 2> 0
I-- I
600 6 0 0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
Q 0
6-
2K X8 STATIC RAM
TMS4016 (TI)
6116 (HITACHI)
TC5516P (TOSHIBA)
TMM2016P (TOSHIBA)
2128 (OKI)
FIG.
rO
0- "
"" "
9 9 ,9 9 o 9 9
.1.18119.1. }o 121JIIC
cs
CS'
+12 cs·
FIG.
K
0
SPECIAL
CONFIGURATION
FOR PART
NO.
I
FIG.
J
6 6 olo 6 6 6
0- -0
0
C1980 GIMIX INC.
~
PROM/ROM/RAM SOCKET CONFIGURATION
JUMPER AREA (I PER SOCKET)
GIMIX INC.
1337 W. 37th PLACE CHICAGO IL. 60609
6-12-80
I
I~
6809 + C. P.tJ.
I
I
PROM/ROM/RAM JUMPER CONFIGURATIONS
C24-0043-1
CONNECTOR AREA CA-I
RESETF
JUMPER AREA
JA-9
I 11 cq~I~BORT
OFF (OPEN)
ON (CLOSED)
9511A
FPLA INPUTS
FIGURE A: NMIIR.ESET CONNECTOR
FPLA INPUTISOFTWARE
LATCH· ENABLE
AI6
9512
AI7
JUMPER AREA JA-13
ON CARD DEVICE EXTENDED
ADDRESS SELECT
AI8
FIGURE D: 9511A19512
SELECTION
AI9
TOCA-I NMI
CONNECTOR
JUMPER AREA JA-14
FIGURE G: DIP
SWITCH (52)
TO 6809 NMI
BA
TO SS-50 BUS
. BA TO BUS
ON (CLOSED)
OFF (OPEN)
DISABLE,......._ _ _ _ _ _... ENABLE
BA-BS
NMI TO
BUS
NMI TO
RESET CONNECTION (CA-I)
PROM/ROM/RAM SOCKET (U4)
BA·BS
FIGURE B: NMI OPTION JUMPER
FIGURE E: BA NORMAL
OR GATED TO BS
JUMPER AREA-JA 7
JUMPER AREA JA-6
II r--i I
+5B WITH
BATTERY
I K SCRATCH PAD
RAM (U8 + U9)
PIN 18
ON
+5A
CMOS
RAM
STANDARD (NMOS)
RAM
FIGURE C: CMOS/NMOS
RAM OPTION JUMPER
BATTERY
t
I
BATTERY ON
PROM/ROM/RAM
SOCKET
(U5)
3
PROM/ROM/RAM SOCKET
(U6)
4
PROM/ROM/RAM
5
58167
TIME
6
6840
PROGAMABLE TIMER (U2)
7
9511A19512 ARITHMETIC PROGRAM (U
8
IK SCRATCH PAD RAM (u8and U9)
SOCKET (U7)
OF DAY CLOCK (UI)
FIGURE H: DIP
SWITCH (SI)
OFF
I i I±---~ II
2
@1980 GIMIX INC.
BATTERY OFF
1337
w.
6-16-80
GIMIX INC.
37th PLACE CHICAGO IL. 60609
6809+ C.P.U
~
SWITCH AND JUMPER CONFIGURATIONS
FIGURE F: BATTERY
ON/OFF JUMPER
SHEET I
C24-0043-2
.u.fPER AREA JA-II
CONFIGURATION 2
CONFIGURATION I
Ul8A-PIN2
1
00
UISC-PlN8
U:55-PIN8
o OIQlI
0----0--.1 L<?J
10--01 0
L _____
I I
o 10--01
10-010
r-'I
FIGURE D2 FPLA ONU' ENABLED WITH ON
CARD EXTENDED MIORESS MATCH.
.l,M)ER
IRQ
FIGURE: E FPLA ADDRESSES BETWEEN
IFOOO AND $FFFF ALWAYS ENABLED
OTHER ADDRESSES ONLY ENABLED WITH
ON CARD EXTENDED ADDRESS MATCH.
AREA JA-12
6840(U21
It
0
0
CONFIGURATION 6
,-----,
fC?lOO
0 iO--o1
L _____ J
~Io-DI
0
~O
0
0 --01
10--01
1
FIGURE G: FPLA ALWAYS DISABLED.
0
0
10--01 0
0 1
0 --01
0---0
r--l
0 101
I I 1
tN
0
16
I
I
FIRQ
0
0
NMI
0
0
IRQ
FIGURE C: FPLA ONLY ENABLED FOR
ADDRESSES BETWEEN IFOOO AND IFFFF.
CONFIGURATION 5
FIGURE F: FPLA ONLY ENABLED FOR
ADDRESSES BETWEEN t FOOO AND &FFFF
ONLY WITH ON CARD £XTENDED ADDRESS
MATCH •
I
JUMPER AREA JA-IO
FIRQ
IRQ
61
1L __ J
FIGURE 8: FPLA ALWAYS ENABLED.
CONFIGURATION 4
r----'J
o 10--01
.-_ _....,1
1
o Io--DI
GROlN)
UI6B-PIN 4
FIGURE A: FPLA ENA8L.E OPTION JUMPER JA-l I.
·CONFIGURATION :5
o 0 rQlI
10--ollQJ
o 10--01
10--oliQl
......- -..... 1
SMRE
9511A/9512 (U31
1
L_.J
0--0
58167(UIl
0
FIRQ
U51A
PIN I
AI9
FIGURE J: SOFTWARE WRITE PROTECT
OPTION JUMPER.
FIGURE K: NO SOFTWARE WRITE PROTECT.
10-D 1
Io--DI 0
o 0 fC?l
Io--DI~
FIGURE L: SOFTWARE WRITE PROTECT.
LOWER 1/2 MBYTE.
o
FIGURE M: SOFTWARE WRITE PROTECT
UPPER 1/2 MBYTE.
01980 GlMIX INC.
0
GIMIX INC
1337 W. 37th PLACE, CHICAGO IL. 60609
FIGURE H: INTERRUPT OPTION
JUMPER JA-l2.
r:
FIGURE
SAMPLE INTERRUPT JUMPER
CONFIGURATION.
6840 GENERATES FIRQ
9511A/9512 GENERATES NONE
58167 GENERATES IRQ
6-18-80
6809 + C.P.U
~
SWITCH AND JUMPER CONFIGURATIONS
SHEET 2
C24-0043-3
~
01
....
p---------------------------------------------------------------------------------------------------------------------
t.)
t.)
.i:.
6809 (U47)
o
o
o
o
8.0 MHz
6.0MHz
0
0
I 0-----0 I
0-----0
0
0
0
0
0
0
4.0 MHz
0------0
0
0
0
0
0
0
9511A/9512 (U3)
o
0
0
0
0
0
o
0
0
0
0
0
rn
0
2.0 MHz
FIGURE A: CLOCK SPEED OPTION
JUMPER FOR CPU AND 95l1A/9512.
FIGURE D: 6809 at 2.0 MHz.
FIGURE C: 6809 at 1.5 MHz.
FIGURE 8:6809 at 1.0 MHz.
0
FIGURE E: 9511A19512 at 2.0 MHz.
JA-t
.:.
.:.
0
0
0
0
0
0
0
0
IMHz CLOCK
0
0
0
0
o
0
0
0
0
0
o
0
0
0
0
0
rn
0
0
03
02
01
FIGURE I: 6840 OPTION JUMPER JA-t.
0
·9
I
I
I
o
0
0
9
I
I
I
.----
0
0
9
'--
r---
0
0
I
I
I
61 0--0 161 o--D 16
'--
FIGURE G: 951!A at 4.0 MHz.
0
FIGURE H: 6809 at IMHz and 9511A
at 4MHz.
6840 'JUMPER EXAMPLE
6840 JUMPER EXAMPLE
.----
o
0
0
FIGURE F: 9511A/9512 at 3.0 MHz.
r-:--
w moo
'--
FIGURE J: TIMERS CASCADED-lto2to3.
r---- ....,...--r---·- '1"-'--
o 9 L_____
0--0 0 L_____
0--{) q
I
I
I
I
I
0
0
0
6
l......-
I
I
0
6
I...--
0
0
@1980 GlMIX INC.
I~·-·-
I
I
0
I
I
0
0
6
0
I...--
FIGURE K: TIMERS SET FOR CONTINUOS OPERATION.
0
6809+ C.P.U
SWITCH AND JUMPER CONFIGURATIONS
SHEET 3
C2+0043-4
POWER AND GROUND PINOUTS
* NOTES
-16
'0.
U31
CI91
+
C2J
+
~C28
-5
PIN 16 OF U-3 IS CONNECTED TO +12.
U-4,5,6,and 7 ARE CONNECTED TO
+5C, +12, and -5 AS DETERMINED BY
THEIR ASSOCIATED JUMPER AREASJA-2,3,4,5.
JUMPER AREA JA-7 CONNECTS U-8
AND U-9 TO +5A WHEN THE STANDARD RAM IS INSTAllED OR TO +5B
FOR BATTERY BACKUP WHEN THE
CMOS RAM OPTION IS INSTAllED.
GND
+16
U28
1
C2t
+h
1
c22
+ lC27
U29
)J
+8
+12
,.1+1
CIB+1
+5C
g~6,~~~,~~~C34,C39,
20
RI2
+58
Q~r=9
~
04
~ ~D3
ClOt
CII
17 01
I
+
I T
cI2
+
C25
7
U30
+5A
>
G
h T
+
CI7
51
-=
TT
+
cI6
+
D2~l---
C29,C31-33,C35-38.C41
R24>'
RII
~"
QI
Q2
J-
IC NO. +5A +58
UI
24
U2
*U3
*U4
*U5
*U6
*U7
U8
*18 *18
U9
*113 *..llt
UIO
UII
UI2
UI3
UI4
ule
UI6
UI7
UI8
UI9
U20
14
U21
U22
U23
U24
U25
U26
U27
U:32
14
U33
20
U34
16
U35
14
U36
28
U37
16
U38
16
U39
U40
U41
16
U42
16
U43
U44
16
U4e
16
U46
U47
20
U4B
U49
20
USO
20
uel
U52
U53
U54
14
+5C
GND
12
12
II
12
12
12
12
9
9
13
J4
24
24
24
24
14.
-.lli
16
16
14
14
14
14
14
14
-.L
--.a
8
Ji
22
22
16
7
7
7
7
7
7
7
8
8
8
~
-.!l
~
~
14
~
~4
~
1
.. J(l
8
_1
14
8
8
--.a
--.a
-.!l
--.a
--.a
16
~
-.lli
8
8
~
~
. J_
i
10
~
10
7
7
7
14
14
14
I
GIMIX INC.
1337 W. 37th PLACE, CHICAGO, Il, 60609
6-10-80
I
I
6809 + C.P.U.
I
~
SHEET 2012
p~
lOGIC SUPPLY
PROPRIETARY MAT'L., ALL RIGHTS RESERVED
© 1980 GIMIX INC.
I
L24-0043
GIMIX 6809+ COMPONENT LAYOUT
r0.6II01
VMA
5 IZ
AID
'i""41.8
AI >----~6 z~
A2
A3
7~'i-,'-+-.../1
10
13
-15
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-b
A4
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2~
10
7"""'S:--+-_oJ/
5~
'r"''''':--+_.//~
II~
I
~IS
,....- I
IZ",'::..7:--+-_oJ
/
.I....-
,.
1.7'
~",A",8.,---t-_oJ/
AS ,
A9
AIO >---. I--All
10
13
~IS
.--
L_I~
-
Z~
6
7""A~'_+----,/
S~
U42 ,I.!A!!!IO,,:-+_..//
II~
..,A"-'''.,..--I---'/
IZ A!l'
21
.,
AI3
22 .,4
' - _...
25.... ,S
~
"-. 15
I2.&. •"4 '3'
2~4)O...3 _.....-"'I'41ui',oIXl'--_ _-<R/W
q,-
~
,-_....:'=..' .8
l'-----.l!
•II
20 AIZ
J
~r+_~6~4)O~7_ _-<Q
~:;
~'87
~
RW 3Z
' ' ' - _ - - ' '.... 1.10
•
U41
46122-7
II~
14~
13
~'2
~A3
'>---+--~~;r-4 .4
A5
A6
A7
RESET """,'----'
i"----J!13 •Ae4
IZ..,'",3,.-+-_.//
~"'>..L.
·--+--+----...~(1"m'~':E-T"
EXTAL
,-__'::..0"
5~
U38 8 ~'~Z:--+_../
~
,-__8:::.1'.
U47
n~
~II
I"'" "
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