A&D | EX-3000A | Rabbit 2000/3000 Instruction Reference

Rabbit 2000 /3000 Microprocessor
Instruction Reference Manual
019–0098 F • 040114
This manual (or an even more up-to-date revision) is available for free download
at the Rabbit website: www.rabbitsemiconductor.com
ii
Rabbit 2000/3000 Microprocessor
Table of Contents
1. Alphabetical Listing of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Instructions Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. OpCode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7. Quick Reference Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Notice to Users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Instruction Reference Manual
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iv
Rabbit 2000 Microprocessor
1. Alphabetical Listing of Instructions
A
D
L
ADC A,n ..............................14
ADC A,r ..............................15
ADC A,(HL) .........................13
ADC A,(IX+d) ......................13
ADC A,(IY+d) ......................13
ADC HL,ss ...........................16
ADD A,n ..............................18
ADD A,r ..............................19
ADD A,(HL) .........................17
ADD A,(IX+d) ......................17
ADD A,(IY+d) ......................17
ADD HL,ss ...........................20
ADD IX,xx ...........................21
ADD IY,yy ...........................21
ADD SP,d ............................22
ALTD ..................................23
AND HL,DE .........................25
AND IX,DE ..........................25
AND IY,DE ..........................25
AND n .................................26
AND r .................................27
AND (HL) ............................24
AND (IX+d) .........................24
AND (IY+d) .........................24
DEC IX ................................39
DEC IY ................................39
DEC r ..................................40
DEC ss .................................41
DEC (HL) ............................38
DEC (IX+d) ..........................38
DEC (IY+d) ..........................38
DJNZ e ................................42
LCALL x,mn ........................60
LD A,EIR .............................68
LD A,IIR ..............................68
LD A,XPC ............................69
LD A,(BC) ...........................67
LD A,(DE) ...........................67
LD A,(mn) ............................67
LD dd',BC ............................71
LD dd',DE ............................71
LD dd,mn .............................72
LD dd,(mn) ...........................70
LD EIR,A .............................73
LD HL,IX .............................76
LD HL,IY .............................76
LD HL,(HL+d) ......................74
LD HL,(IX+d) .......................74
LD HL,(IY+d) .......................74
LD HL,(mn) ..........................74
LD HL,(SP+n) .......................75
LD IIR,A ..............................73
LD IX,HL .............................79
LD IX,mn .............................79
LD IX,(mn) ..........................77
LD IX,(SP+n) .......................78
LD IY,HL .............................79
LD IY,mn .............................79
LD IY,(mn) ..........................80
LD IY,(SP+n) .......................81
LD r,g ..................................84
LD r,n ..................................83
LD r,(HL) .............................82
LD r,(IX+d) ..........................82
LD r,(IY+d) ..........................82
LD SP,HL ............................85
LD SP,IX .............................85
LD SP,IY .............................85
LD XPC,A ............................86
LD (BC),A ...........................61
LD (DE),A ...........................61
LD (HL),n ............................61
LD (HL),r .............................61
LD (HL+d),HL ......................62
LD (IX+d),HL .......................63
LD (IX+d),n ..........................63
LD (IX+d),r ..........................63
LD (IY+d),HL .......................64
B
BIT b,r .................................29
BIT b,(HL) ...........................28
BIT b,(IX+d) .........................28
BIT b,(IY+d) .........................28
BOOL HL ............................30
BOOL IX .............................31
BOOL IY .............................31
C
CALL mn .............................32
CCF ....................................33
CP n ....................................35
CP r .....................................36
CP (HL) ...............................34
CP (IX+d) ............................34
CP (IY+d) ............................34
CPL .....................................37
Instruction Reference Manual
E
EX AF,AF' ...........................45
EX DE',HL ...........................46
EX DE,HL ............................46
EX (SP),HL ..........................43
EX (SP),IX ...........................44
EX (SP),IY ...........................44
EXX ....................................47
I
IDET ...................................48
INC IX .................................50
INC IY .................................50
INC r ...................................51
INC ss .................................52
INC (HL) .............................49
INC (IX+d) ...........................49
INC (IY+d) ...........................49
IOE .....................................53
IOI ......................................53
IPRES ..................................55
IPSET 0 ...............................54
IPSET 1 ...............................54
IPSET 2 ...............................54
IPSET 3 ...............................54
J
JP f,mn ................................57
JP mn ..................................56
JP (HL) ................................56
JP (IX) .................................56
JP (IY) .................................56
JR cc,e .................................58
JR e .....................................59
1
LD (IY+d),n ..........................64
LD (IY+d),r ..........................64
LD (mn),A ............................65
LD (mn),HL ..........................65
LD (mn),IX ...........................65
LD (mn),IY ...........................65
LD (mn),ss ...........................65
LD (SP+n),HL .......................66
LD (SP+n),IX ........................66
LD (SP+n),IY ........................66
LDD ....................................87
LDDR ..................................87
LDDSR ................................88
LDI .....................................87
LDIR ...................................87
LDISR .................................88
LDP HL,(HL) ........................91
LDP HL,(IX) .........................91
LDP HL,(IY) .........................91
LDP HL,(mn) ........................92
LDP IX,(mn) .........................92
LDP IY,(mn) .........................92
LDP (HL),HL ........................89
LDP (IX),HL .........................89
LDP (IY),HL .........................89
LDP (mn),HL ........................90
LDP (mn),IX .........................90
LDP (mn),IY .........................90
LJP x,mn ..............................93
LRET ..................................94
LSDDR ................................95
LSDR ..................................95
LSIDR .................................95
LSIR ...................................95
M
MUL
...................................96
N
NEG
NOP
....................................97
....................................98
O
OR HL,DE .........................100
OR IX,DE ..........................101
OR IY,DE ..........................101
OR n ..................................102
OR r ..................................102
2
OR (HL) ...............................99
OR (IX+d) ............................99
OR (IY+d) ............................99
P
POP IP ...............................103
POP IX ..............................103
POP IY ..............................103
POP SU .............................104
POP zz ...............................105
PUSH IP ............................106
PUSH IX ............................106
PUSH IY ............................106
PUSH SU ...........................107
PUSH zz ............................108
R
RA ....................................126
RDMODE ..........................109
RES b,r ..............................111
RES b,(HL) .........................110
RES b,(IX+d) ......................110
RES b,(IY+d) ......................110
RET ..................................112
RET f ................................113
RETI .................................114
RL DE ...............................116
RL r ..................................117
RL (HL) .............................115
RL (IX+d) ..........................115
RL (IY+d) ..........................115
RLA ..................................118
RLC r ................................120
RLC (HL) ...........................119
RLC (IX+d) ........................119
RLC (IY+d) ........................119
RLCA ................................121
RR DE ...............................123
RR HL ...............................123
RR IX ................................124
RR IY ................................124
RR r ..................................125
RR (HL) .............................122
RR (IX+d) ..........................122
RR (IY+d) ..........................122
RRC r ................................128
RRC (HL) ..........................127
RRC (IX+d) ........................127
RRC (IY+d) ........................127
RRCA ................................129
RST v ................................130
S
SBC A,n .............................132
SBC A,r .............................132
SBC A,(HL) ........................131
SBC HL,ss ..........................133
SBC (IX+d) ........................131
SBC (IY+d) ........................131
SCF ...................................134
SET b,r ..............................136
SET b,(HL) .........................135
SET b,(IX+d) ......................135
SET b,(IY+d) ......................135
SETUSR ............................137
SLA r ................................139
SLA (HL) ...........................138
SLA (IX+d) ........................138
SLA (IY+d) ........................138
SRA r ................................141
SRA (HL) ...........................140
SRA (IX+d) ........................140
SRA (IY+d) ........................140
SRL r .................................143
SRL (HL) ...........................142
SRL (IX+d) ........................142
SRL (IY+d) ........................142
SUB n ................................145
SUB r ................................146
SUB (HL) ...........................144
SUB (IX+d) ........................144
SUB (IY+d) ........................144
SURES ..............................147
SYSCALL ..........................148
U
UMA
UMS
.................................149
.................................149
X
XOR n ...............................151
XOR r ................................152
XOR (HL) ..........................150
XOR (IX+d) .......................150
XOR (IY+d) .......................150
Rabbit 2000/3000 Microprocessor
2. Instructions Listed by Group
A. Load Immediate Data
LD dd,mn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LD IX,mn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LD IY,mn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LD r,n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
B. Load and Store to an Immediate Address
LD (mn),A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LD (mn),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LD (mn),IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LD (mn),IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LD (mn),ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LD A,(mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LD dd,(mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LD HL,(mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LD IX,(mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LD IY,(mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
C. 8-bit Indexed Load and Store
LD (BC),A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
LD (DE),A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
LD (HL),n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
LD (HL),r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
LD (IX+d),n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LD (IX+d),r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LD (IY+d),n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LD (IY+d),r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LD A,(BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LD A,(DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LD r,(HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LD r,(IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LD r,(IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
D. 16-bit Indexed Load and Store
LD (HL+d),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
LD (IX+d),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LD (IY+d),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LD (SP+n),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LD (SP+n),IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LD (SP+n),IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LD HL,(HL+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LD HL,(IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LD HL,(IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Instruction Reference Manual
LD HL,(SP+n) . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
LD IX,(SP+n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
LD IY,(SP+n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
E. 16-bit Load and Store to 20-bit Address
LDP (HL),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
LDP (IX),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
LDP (IY),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
LDP (mn),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
LDP (mn),IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
LDP (mn),IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
LDP HL,(HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
LDP HL,(IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
LDP HL,(IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
LDP HL,(mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
LDP IX,(mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
LDP IY,(mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
F. Register to Register Moves
LD A,EIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
LD A,IIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
LD A,XPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
LD dd’,BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
LD dd’,DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
LD EIR,A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
LD HL,IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
LD HL,IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
LD IIR,A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
LD IX,HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
LD IY,HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
LD r,g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
LD SP,HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
LD SP,IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
LD SP,IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
LD XPC,A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
G. Exchange
EX (SP),HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
EX (SP),IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
EX (SP),IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
EX AF,AF’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
EX DE,HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
EX DE’,HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3
EXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
H. Stack Manipulation
ADD SP,d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
POP IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
POP IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
POP IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
POP zz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PUSH IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PUSH IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PUSH IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PUSH zz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
I. 16-bit Arithmetic, Logical, and Rotate
ADC HL,ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ADD HL,ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ADD IX,xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ADD IY,yy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ADD SP,d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AND HL,DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
BOOL HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
BOOL IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
BOOL IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DEC IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DEC IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DEC ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
INC IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
INC IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
INC ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
OR HL,DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
OR IX,DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
OR IY,DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
RL DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
RR DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
RR HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
RR IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
RR IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
SBC HL,ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
I.16-bit Arithmetic, Logical, and Rotate
AND HL,DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AND IX,DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AND IY,DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
J. 8-bit Arithmetic and Logical
ADC A,(HL) . . . . . . . . . . . . . . . . . . . . . . . . 13
ADC A,(IX+d) . . . . . . . . . . . . . . . . . . . . . . . 13
ADC A,(IY+d) . . . . . . . . . . . . . . . . . . . . . . . 13
ADC A,n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ADC A,r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ADD A,(HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ADD A,(IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ADD A,(IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ADD A,n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ADD A,r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AND (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AND (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AND (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AND r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CP (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CP (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CP (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CP n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CP r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
OR (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
OR (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
OR (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
OR n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
OR r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SBC (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SBC (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SBC A,(HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SBC A,n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SBC A,r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SUB (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SUB (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SUB (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SUB n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SUB r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
XOR (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
XOR (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
XOR (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
XOR n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
XOR r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
K. 8-bit Bit Set, Reset, and Test
BIT b,(HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
BIT b,(IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
BIT b,(IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Rabbit 2000/3000 Microprocessor
BIT b,r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RES b,(HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
RES b,(IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
RES b,(IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
RES b,r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SET b,(HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SET b,(IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SET b,(IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SET b,r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
L. 8-bit Increment and Decrement
DEC (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DEC (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DEC (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DEC r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INC (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
INC (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
INC (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
INC r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
M. 8-bit Fast Accumulator
CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
RLCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
RRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
RRCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
N. 8-bit Shift and Rotate
RL (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
RL (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
RL (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
RLC (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
RLC (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
RLC (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
RLC r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
RR (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
RR (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
RR (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
RR r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
RRC (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
RRC (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
RRC (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
RRC r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SLA (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SLA (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SLA (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Instruction Reference Manual
SLA r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
SRA (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
SRA (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
SRA (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
SRA r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
SRL (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
SRL (IX+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
SRL (IY+d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
SRL r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
O. Instruction Prefixes
ALTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
IOE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
IOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
P. Block Moves
LDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
LDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
LDDSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
LDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
LDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
LDISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
LSDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
LSDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
LSIDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
LSIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Q. Control, Jump, and Call
CALL mn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
DJNZ e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
JP (HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
JP (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
JP (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
JP f,mn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
JP mn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
JR cc,e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
JR e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
LCALL x,mn . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
LJP x,mn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
LRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
RET f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
RETI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
RST v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5
R. Miscellaneous
CCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IPSET 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPSET 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPSET 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPSET 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
W. System/User Mode
IDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
POP SU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PUSH SU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
RDMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SETUSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SYSCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
S. Special Arithmetic
UMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
UMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
T. Privileged Instructions
BIT b,(HL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
IPRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
IPSET 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPSET 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPSET 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPSET 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LD A,XPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LD SP,HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LD SP,IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LD SP,IY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LD XPC,A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
POP IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
RETI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
U. Rabbit 3000A Instructions
IDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LDDSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LDISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LSDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LSDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LSIDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LSIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
POP SU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PUSH SU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
RDMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SETUSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SYSCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
UMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
UMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6
Rabbit 2000/3000 Microprocessor
3. Document Conventions
Instruction Table Key
•
Opcode: A hexidecimal representation of the value that the mnemonic instruction represents.
•
Instruction: The mnemonic syntax of the instruction.
•
Clocks: The number of clock cycles it takes to complete this instruction. The numbers in parenthesis
are a breakdown of the total clocks. The number of clocks instructions take follows a general patern.
There are several Rabbit instructions that do not adhere to this pattern. Some instructions take more
clocks and some have been enhanced to take fewer clocks.
Table 1: Typical Clocks Breakdown
Process
•
Clocks
Each byte of the opcode.
2
Each data byte read.
2
Write to memory or external IO.
3
Write to internal IO.
2
Internal operation or computation.
1
Operation: A symbolic representation of the operation performed.
Instruction Reference Manual
7
ALTD, I/O and Flags Table Keys
Table 2: ALTD (“A” Column) Symbol Key
Flag
Description
F
R
SP
ALTD selects alternate flags
•
ALTD selects alternate destination register
•
ALTD operation is a special case
•
Table 3: IOI and IOE (“I” Column) Symbol Key
Flag
S
Description
D
IOI and IOE affect destination
•
IOI and IOE affect source
•
Table 4: Flag Register Key
S
8
Z
L/V
C
Description
•
Sign flag affected
-
Sign flag not affected
•
Zero flag affected
-
Zero flag not affected
L
LV flag contains logical check result
V
LV flag set on arithmetic overflow result
0
LV flag is cleared
•
LV flag is affected
•
Carry flag is affected
-
Carry flag is not affected
0
Carry flag is cleared
1
Carry flag is set
Rabbit 2000/3000 Microprocessor
Document Symbols Key
Table 5: Symbols
Rabbit
Z180
b
b
cc
cc
d
d
dd
ww
dd'
Meaning
Bit select (000 = bit 0, 001 = bit 1, 010 = bit 2, 011 = bit
3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111 = bit 7)
Condition code select (00 = NZ, 01 = Z, 10 = NC, 11 = C)
7-bit (signed) displacement. Expressed in two's complement.
word register select-destination (00 = BC, 01 = DE, 10 =
HL, 11 = SP)
word register select-alternate(00 = BC', 01 = DE', 10 =
HL')
e
j
8-bit (signed) displacement added to PC
f
f
condition code select (000 = NZ, 001 = Z, 010 = NC, 011 = C,
100 = LZ/NV, 101 = LO/V, 110 = P, 111 = M)
m
m
the most significant bits(MSB) of a 16-bit constant
mn
mn
n
n
r, g
g, g'
byte register select (000 = B, 001 = C, 010 = D, 011 = E,
100 = H, 101 = L, 111 = A)
ss
ww
word register select-source ( 00 = BC, 01 = DE, 10 = HL, 11
= SP)
v
v
x
nbr
xx
xx
word register select ( 00 = BC, 01 = DE, 10 = IX, 11 = SP)
yy
yy
word register select (00 = BC, 01 = DE, 10 = IY, 11 = SP)
zz
zz
word register select (00 = BC, 01 = DE, 10 = HL, 11 = AF)
16-bit constant
8-bit constant or the least significant bits(LSB) of a 16bit constant
Restart address select ( 010 = 0020h, 011 = 0030h, 100 =
0040h, 101 = 0050h, 111 = 0070h)
an 8-bit constant to load into the XPC
Instruction Reference Manual
9
Condition Codes
Table 6: Condition Code Description
10
Condition
Flag=Value
Description
NZ
Z=0
Not Zero
Z
Z=1
Zero
NC
C=0
No Carry (C=0)
C
C=1
Carry (C=1)
P
S=0
Positive
M
S=1
Minus
LZ
L/V=0
For logic operations, Logic Zero
(all of the four most significant
bits of the result are zero)
NV
L/V=0
For arithmentic operations,
No Overflow
LO
L/V=1
For logic operations, Logic One
(one or more of the four most significant bits of the result are one)
V
L/V=1
For arithmentic operations,
Overflow
Rabbit 2000/3000 Microprocessor
4. Processor Registers
Logical/
Overflow
Sign Zero
LV
S Z
General Purpose
Accumulator
A
Flags
F
16-bit Accumulator
H
L
D
B
Carry
C
Alternate Registers
Accumulator
A'
Flags
F'
16-bit Accumulator
H'
L'
E
D'
E'
C
B'
C'
Index Register
IX
IP
Interrupt
Priority
Index Register
XPC
Extension of
Program Counter
Stack Pointer
EIR
External
Interrupt
IIR
Internal
Interrupt
IY
SP
Program Counter
PC
Instruction Reference Manual
11
12
Rabbit 2000/3000 Microprocessor
5. OpCode Descriptions
ADC A,(HL)
ADC A,(IX+d)
ADC A,(IY+d)
Opcode
Instruction
Clocks
Operation
8E
ADC A,(HL)
5 (2,1,2)
A = A + (HL) + CF
DD 8E d
ADC A,(IX+d)
9 (2,2,2,1,2)
A = A + (IX+d) + CF
FD 8E d
ADC A,(IY+d)
9 (2,2,2,1,2)
A = A + (IY+d) + CF
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
•
Description
The data in A is summed with the C flag and with the data in memory whose location is:
•
held in HL, or
•
the sum of the data in IX and a displacement value d, or
•
the sum of the data in IY and a displacement value d.
The result is then stored in A.
Instruction Reference Manual
13
ADC A,n
Opcode
CE n
Instruction
ADC A,n
Clocks
Operation
A = A + n + CF
4 (2,2)
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
Description
The 8-bit constant n is summed with the C flag and with the data in A. The sum is then stored in A.
14
Rabbit 2000/3000 Microprocessor
ADC A,r
Opcode
Instruction
Clocks
Operation
——
ADC A,r
2
A = A + r + CF
8F
ADC A,A
2
A = A + A + CF
88
ADC A,B
2
A = A + B + CF
89
ADC A,C
2
A = A + C + CF
8A
ADC A,D
2
A = A + D + CF
8B
ADC A,E
2
A = A + E + CF
8C
ADC A,H
2
A = A + H + CF
8D
ADC A,L
2
A = A + L + CF
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
Description
The data in A is summed with the C flag and with the data in r (any of the registers A, B, C, D, E, H, or L).
The result is stored in A.
Instruction Reference Manual
15
ADC HL,ss
Opcode
Instruction
Clocks
Operation
——
ADC HL,ss
4 (2,2)
HL = HL + ss + CF
ED 4A
ADC HL,BC
4 (2,2)
HL = HL + BC + CF
ED 5A
ADC HL,DE
4 (2,2)
HL = HL + DE + CF
ED 6A
ADC HL,HL
4 (2,2)
HL = HL + HL + CF
ED 7A
ADC HL,SP
4 (2,2)
HL = HL + SP + CF
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
Description
The data in HL is summed with the C flag and with the data in ss (any of BC, DE, HL, or SP). The result is
stored in HL.
16
Rabbit 2000/3000 Microprocessor
ADD A,(HL)
ADD A,(IX+d)
ADD A,(IY+d)
Opcode
Instruction
Clocks
Operation
86
ADD A,(HL)
5 (2,1,2)
A = A + (HL)
DD 86 d
ADD A,(IX+d)
9 (2,2,2,1,2)
A = A + (IX+d)
FD 86 d
ADD A,(IY+d)
9 (2,2,2,1,2)
A = A + (IY+d)
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
•
Description
The data in A is summed with the data in the memory location whose address is:
•
held in HL, or
•
the sum of the data in IX and a displacement value d, or
•
the sum of the data in IY and a displacement value d.
The result is stored in A.
Instruction Reference Manual
17
ADD A,n
Opcode
C6 n
Instruction
ADD A,n
Clocks
Operation
A = A + n
4 (2,2)
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
Description
The data in A is summed with the 8-bit constant n. The result is stored in A.
18
Rabbit 2000/3000 Microprocessor
ADD A,r
Opcode
Instruction
Clocks
Operation
——
ADD A,r
2
A = A + r
87
ADD A,A
2
A = A + A
80
ADD A,B
2
A = A + B
81
ADD A,C
2
A = A + C
82
ADD A,D
2
A = A + D
83
ADD A,E
2
A = A + E
84
ADD A,H
2
A = A + H
85
ADD A,L
2
A = A + L
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
Description
The data in A is summed with the data in r (any of the registers A, B, C, D, E, H, or L). The result is stored in
A.
Instruction Reference Manual
19
ADD HL,ss
Opcode
——
09
19
29
39
Instruction
ADD
ADD
ADD
ADD
ADD
HL,ss
HL,BC
HL,DE
HL,HL
HL,SP
Clocks
Operation
2
2
2
2
2
HL
HL
HL
HL
HL
Flags
ALTD
S
Z
L/V
C
F
R
-
-
-
•
•
•
=
=
=
=
=
HL
HL
HL
HL
HL
+
+
+
+
+
ss
BC
DE
HL
SP
I/O
SP
S
D
Description
The data in HL is summed with the data in the ss (any of BC, DE, HL, or SP). The result is stored in HL.
20
Rabbit 2000/3000 Microprocessor
ADD IX,xx
ADD IY,yy
Opcode
Instruction
Clocks
Operation
——
DD
DD
DD
DD
ADD
ADD
ADD
ADD
ADD
IX,xx
IX,BC
IX,DE
IX,IX
IX,SP
4
4
4
4
4
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
IX
IX
IX
IX
IX
=
=
=
=
=
IX
IX
IX
IX
IX
+
+
+
+
+
xx
09
19
29
39
——
FD
FD
FD
FD
ADD
ADD
ADD
ADD
ADD
IY,yy
IY,BC
IY,DE
IY,IY
IY,SP
4
4
4
4
4
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
IY
IY
IY
IY
IY
=
=
=
=
=
IY
IY
IY
IY
IY
+
+
+
+
+
yy
09
19
29
39
Flags
ALTD
S
Z
L/V
C
F
-
-
-
•
•
R
BC
DE
IX
SP
BC
DE
IY
SP
I/O
SP
S
D
Description
The data in IX is summed with the xx (any of BC, DE, IX, or SP). The result is stored in IX.
The data in IY is summed with the yy (any of BC, DE, IY, or SP). The result is stored in IY.
Instruction Reference Manual
21
ADD SP,d
Opcode
27 d
Instruction
ADD SP,d
Clocks
Z
-
-
SP = SP + d
4 (2,2)
Flags
S
ALTD
-
Operation
C
F
•
•
R
I/O
SP
S
D
Description
The data in the Stack Pointer register (SP) is summed with the 7-bit signed displacement d, and then stored in
SP.
22
Rabbit 2000/3000 Microprocessor
ALTD
Opcode
76
Instruction
ALTD
Clocks
Operation
2
[Sets alternate register
destination for following
instruction.]
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
This is an instruction prefix. Causes the instruction immediately following to affect the alternate flags, or use
the alternate registers for the destination of the data, or both. For some instructions ALTD causes special
alternate register uses, unique to that instruction.
Example
The instruction
ALTD ADD HL,DE
would add the data in DE to the data in HL and store the result in the alternate register HL'.
The instructions
ALTD LD DE,BC
and
LD DE',BC
both load the data in BC into the alternate register DE'.
Instruction Reference Manual
23
AND (HL)
AND (IX+d)
AND (IY+d)
Opcode
Instruction
Clocks
Operation
A6
AND (HL)
5 (2,1,2)
A = A & (HL)
DD A6 d
AND (IX+d)
9 (2,2,2,1,2)
A = A & (IX+d)
FD A6 d
AND (IY+d)
9 (2,2,2,1,2)
A = A & (IY+d)
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
I/O
SP
S
D
•
Description
Performs a logical AND operation between the byte in A and the byte whose address is:
•
in HL, or
•
the sum of the data in IX and a displacement value d, or
•
the sum of the data in IY and a displacement value d.
The relative bits of each byte are compared (i.e., bit 0 of both bytes are compared, bit 1 of both bytes are compared, etc.). The associated bit in the result byte is set only if both the compared bits are set. The result is
stored in A.
Example
If the byte in A contains the value 1011 1100 and the byte at memory location HL contains the value
1101 0101, then the execution of the instruction:
AND (HL)
would result in the byte in A becoming 1001 0100.
24
Rabbit 2000/3000 Microprocessor
AND HL,DE
Opcode
Instruction
DC
AND HL,DE
Clocks
Operation
2
HL = HL & DE
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
I/O
SP
S
D
Description
Performs a logical AND operation between the word in HL and the word in DE. The relative bits of each byte
are compared (i.e., bit 0 of both bytes are compared, bit 1 of both bytes are compared, etc.). The associated bit
in the result byte is set only if both the compared bits are set. The result is stored in HL.
AND IX,DE
AND IY,DE
Opcode
Instruction
Clocks
Operation
DD DC
AND IX,DE
4 (2,2)
IX = IX & DE
FD DC
AND IY,DE
4 (2,2)
IY = IY & DE
Flags
ALTD
S
Z
L/V
C
F
•
•
L
0
•
R
I/O
SP
S
D
Description
•
AND IX,DE performs a logical AND operation between the word in IX and the word in DE.
The result is stored in IX.
•
AND IY,DE performs a logical AND operation between the word in IY and the word in DE.
The result is stored in IY.
The relative bits of each byte are compared (i.e., bit 0 of both bytes are compared, bit 1 of both bytes are compared, etc.). The associated bit in the result byte is set only if both the compared bits are set.
Instruction Reference Manual
25
AND n
Opcode
E6 n
Instruction
AND n
Clocks
Operation
4 (2,2)
Flags
A = A & n
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
I/O
SP
S
D
Description
Performs a logical AND operation between the byte in A and the 8-bit constant n. The relative bits of each
byte are compared (i.e., bit 0 of both bytes are compared, bit 1 of both bytes are compared, etc.). The associated bit in the result byte is set only if both the compared bits are set. The result is stored in A.
26
Rabbit 2000/3000 Microprocessor
AND r
Opcode
——
A7
A0
A1
A2
A3
A4
A5
Instruction
AND
AND
AND
AND
AND
AND
AND
AND
r
A
B
C
D
E
H
L
Clocks
Operation
2
2
2
2
2
2
2
2
A
A
A
A
A
A
A
A
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
=
=
=
=
=
=
=
=
A
A
A
A
A
A
A
A
&
&
&
&
&
&
&
&
r
A
B
C
D
E
H
L
I/O
SP
S
D
Description
Performs a logical AND operation between the byte in A and the byte in r (any of the registers A, B, C, D, E,
H, or L). The relative bits of each byte are compared (i.e., bit 0 of both bytes are compared, bit 1 of both bytes
are compared, etc.). The associated bit in the result byte is set only if both the compared bits are set. The result
is stored in A.
Instruction Reference Manual
27
BIT b,(HL)
BIT b,(IX+d)
BIT b,(IY+d)
Opcode
——
CB
CB
CB
CB
CB
CB
CB
CB
46
4E
56
5E
66
6E
76
7E
——
DD
DD
DD
DD
DD
DD
DD
DD
CB
CB
CB
CB
CB
CB
CB
CB
d
d
d
d
d
d
d
d
——
FD
FD
FD
FD
FD
FD
FD
FD
CB
CB
CB
CB
CB
CB
CB
CB
d
d
d
d
d
d
d
d
Instruction
Clocks
Operation
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
b,(HL)
0,(HL)
1,(HL)
2,(HL)
3,(HL)
4,(HL)
5,(HL)
6,(HL)
7,(HL)
7
7
7
7
7
7
7
7
7
(2,2,1,2)
(2,2,1,2)
(2,2,1,2)
(2,2,1,2)
(2,2,1,2)
(2,2,1,2)
(2,2,1,2)
(2,2,1,2)
(2,2,1,2)
46
4E
56
5E
66
6E
76
7E
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
b,(IX+d)
0,(IX+d)
1,(IX+d)
2,(IX+d)
3,(IX+d)
4,(IX+d)
5,(IX+d)
6,(IX+d)
7,(IX+d)
10
10
10
10
10
10
10
10
10
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(IX+d)
(IX+d)
(IX+d)
(IX+d)
(IX+d)
(IX+d)
(IX+d)
(IX+d)
(IX+d)
&
&
&
&
&
&
&
&
&
bit
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
46
4E
56
5E
66
6E
76
7E
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
b,(IY+d)
0,(IY+d)
1,(IY+d)
2,(IY+d)
3,(IY+d)
4,(IY+d)
5,(IY+d)
6,(IY+d)
7,(IY+d)
10
10
10
10
10
10
10
10
10
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(2,2,2,2,2)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
&
&
&
&
&
&
&
&
&
bit
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
Flags
ALTD
S
Z
L/V
C
F
-
•
-
-
•
R
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
&
&
&
&
&
&
&
&
&
bit
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
I/O
SP
S
D
•
Description
Tests the bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the byte whose address is:
•
contained in HL, or
•
the sum of data in IX plus a displacement value d, or
•
the sum of data in IY plus a displacement value d.
The Z flag is set if the tested bit is 0, reset the bit is 1.
BIT b,(HL) is a privileged instruction.
28
Rabbit 2000/3000 Microprocessor
BIT b,r
Opcode
b,r
A
B
C
D
E
H
L
CB (0)
47
40
41
42
43
44
45
CB (1)
4F
48
49
4A
4B
4C
4D
CB (2)
57
50
51
52
53
54
55
CB (3)
5F
58
59
5A
5B
5C
5D
CB (4)
67
60
61
62
63
64
65
CB (5)
6F
68
69
6A
6B
6C
6D
CB (6)
77
70
71
72
73
74
75
CB (7)
7F
78
79
7A
7B
7C
7D
Flags
ALTD
S
Z
L/V
C
F
-
•
-
-
•
R
Instruction
Clocks
Operation
BIT b,r
4(2,2)
r & bit
I/O
SP
S
D
Description
Tests bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the byte in r (any of the registers A, B, C, D, E, H, or L).
The Z flag is set if the tested bit is 0, reset if the bit is 1.
Instruction Reference Manual
29
BOOL HL
Opcode
CC
Instruction
BOOL HL
Clocks
Operation
2
If (HL != 0) HL = 1
Flags
ALTD
S
Z
L/V
C
F
R
•
•
0
0
•
•
I/O
SP
S
D
Description
If the data in HL does not equal zero, then it is set to 1.
30
Rabbit 2000/3000 Microprocessor
BOOL IX
BOOL IY
Opcode
Instruction
Clocks
Operation
DD CC
BOOL IX
4 (2,2)
If (IX != 0) IX = 1
FD CC
BOOL IY
4 (2,2)
If (IY != 0) IY = 1
Flags
ALTD
S
Z
L/V
C
F
•
•
0
0
•
R
I/O
SP
S
D
Description
If the data in IX or IY does not equal zero, then that register is set to 1.
Instruction Reference Manual
31
CALL mn
Opcode
CD n m
Instruction
CALL mn
Clocks
Operation
12 (2,2,2,3,3)
Flags
(SP - 1) = PC(high);
(SP - 2) = PC(low);
PC = mn; SP = SP - 2
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
This instruction is used to call a subroutine. First the data in PC is pushed onto the stack. The high-order byte
of PC is pushed first, then the low-order byte. PC is then loaded with mn,16-bit address of the first instruction
of the subroutine. SP is updated to reflect the two bytes pushed onto the stack.
The Dynamic C assembler recognizes CALL label, where mn is coded as a label.
32
Rabbit 2000/3000 Microprocessor
CCF
Opcode
3F
Instruction
CCF
Clocks
Operation
2
CF = ~CF
Flags
ALTD
S
Z
L/V
C
F
-
-
-
•
•
R
I/O
SP
S
D
Description
The C flag is inverted: If it is set, it becomes cleared. If it is not set, it becomes set.
Instruction Reference Manual
33
CP (HL)
CP (IX+d)
CP (IY+d)
Opcode
Instruction
Clocks
Operation
BE
CP (HL)
5 (2,1,2)
A - (HL)
DD BE d
CP (IX + d)
9 (2,2,2,1,2)
A - (IX + d)
FE BE d
CP (IY + d)
9 (2,2,2,1,2)
A - (IY + d)
Flags
ALTD
S
Z
L/V
C
F
•
•
V
•
•
R
I/O
SP
S
D
•
Description
Compares the data in A with the data whose address is contained in:
•
HL, or
•
the sum of the data in IX and a displacement value d, or
•
the sum of the data in IY and a displacement value d.
These compares are accomplished by subtracting the appropriate data ((HL), (IX+d), or (IY+d)) from A. The
result is:
A < x : S=1, C=1, Z=0, L/V=V
A = x : S=0, C=0, Z=1, L/V=V
A > x : S=0, C=0, Z=0, L/V=V
Where x is (HL), (IX+d), or (IY+d) and “V” indicates that the overflow flag is set on an arithmetic overflow
result. That is, the overflow flag is set when the operands have different signs and the sign of the result is different from the argument you are subtracting from (A in this case). For example, if A contains 0x80 and
you're comparing it to 0x01 the overflow flag will be set.
This operation does not affect the data in A.
34
Rabbit 2000/3000 Microprocessor
CP n
Opcode
FE n
Instruction
CP n
Clocks
Operation
4 (2,2)
Flags
A - n
ALTD
S
Z
L/V
C
F
•
•
V
•
•
R
I/O
SP
S
D
Description
Compares the data in A with an 8-bit constant n. This compare is accomplished by subtracting n from A. The
result is:
A < n : S=1, C=1, Z=0, L/V=V
A = n : S=0, C=0, Z=1, L/V=V
A > n : S=0, C=0, Z=0, L/V=V
“V” indicates that the overflow flag is set on an arithmetic overflow result. That is, the overflow flag is signalled when the operands have different signs and the sign of the result is different from the argument you are
subtracting from (A in this case). For example if A contains 0x80 and you're comparing it to 0x01 the overflow flag will be set.
This operation does not affect the data in A.
Instruction Reference Manual
35
CP r
Opcode
——
BF
B8
B9
BA
BB
BC
BD
Instruction
CP
CP
CP
CP
CP
CP
CP
CP
r
A
B
C
D
E
H
L
Clocks
Operation
2
2
2
2
2
2
2
2
A
A
A
A
A
A
A
A
Flags
ALTD
S
Z
L/V
C
F
•
•
V
•
•
R
-
r
A
B
C
D
E
H
L
I/O
SP
S
D
Description
Compares the data in A with the data in register r (any of the registers A, B, C, D, E, H, or L). This compare
is accomplished by subtracting the data in register r from A. The result is:
A < x : S=1, C=1, Z=0, L/V=V
A = x : S=0, C=0, Z=1, L/V=V
A > x : S=0, C=0, Z=0, L/V=V
Where “x” is the data in register r and “V” indicates that the overflow flag is set on an arithmetic overflow
result. That is, the overflow flag is signalled when the operands have different signs and the sign of the result
is different from the argument you are subtracting from (A in this case). For example if A contains 0x80 and
you're comparing it to 0x01 the overflow flag will be set.
This operation does not affect the data in A.
36
Rabbit 2000/3000 Microprocessor
CPL
Opcode
2F
Instruction
CPL
Clocks
Operation
2
A = ~A
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
The data in A is inverted (one’s complement).
Example
If the data in A is 1100 0101, after the instruction CPL A will contain 0011 1010.
Instruction Reference Manual
37
DEC (HL)
DEC (IX+d)
DEC (IY+d)
Opcode
Instruction
Clocks
Operation
35
DEC (HL)
8 (2,1,2,3)
(HL) = (HL) - 1
DD 35 d
DEC (IX+D)
12 (2,2,2,1,2,3)
(IX + d) = (IX + d) - 1
FD 35 d
DEC (IY+D)
12 (2,2,2,1,2,3)
(IY + d) = (IY + d) - 1
Flags
ALTD
S
Z
L/V
C
F
•
•
V
-
•
R
I/O
SP
S
D
•
•
Description
Decrements the byte whose address is:
38
•
in HL, or
•
the data in IX plus a displacement value d, or
•
the data in IY plus a displacement value d.
Rabbit 2000/3000 Microprocessor
DEC IX
DEC IY
Opcode
Instruction
Clocks
Operation
DD 2B
DEC IX
4 (2,2)
IX = IX - 1
FD 2B
DEC IY
4(2,2)
IY = IY - 1
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Decrements the data in IX or IY.
Instruction Reference Manual
39
DEC r
Opcode
——
3D
05
0D
15
1D
25
2D
Instruction
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
r
A
B
C
D
E
H
L
Clocks
Operation
2
2
2
2
2
2
2
2
r
A
B
C
D
E
H
L
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
-
•
•
=
=
=
=
=
=
=
=
r
A
B
C
D
E
H
L
-
1
1
1
1
1
1
1
1
I/O
SP
S
D
Description
Decrements the data in r (any of the registers A, B, C, D, E, H, or L).
40
Rabbit 2000/3000 Microprocessor
DEC ss
Opcode
——
0B
1B
2B
3B
Instruction
DEC
DEC
DEC
DEC
DEC
ss
BC
DE
HL
SP
Clocks
Operation
2
2
2
2
2
ss
BC
DE
HL
SP
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
=
=
=
=
=
ss
BC
DE
HL
SP
-
1
1
1
1
1
I/O
SP
S
D
•
Description
Decrements the data in ss (any of BC, DE, HL, or SP).
Instruction Reference Manual
41
DJNZ e
Opcode
Instruction
10 e-2
DJNZ e
Clocks
Operation
5 (2,2,1)
Flags
B = B-1; if {B != 0} PC = PC + e
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
This instruction’s mnemonic stands for Decrement and Jump if Not Zero. It decrements the data in B then, if
the data in B does not equal 0, it adds the 8 bit signed constant e to PC.
2 is subtracted from the value e so the instruction jumps from the current instruction and not the following
instruction.
42
Rabbit 2000/3000 Microprocessor
EX (SP),HL
Opcode
ED 54
Instruction
EX (SP),HL
Clocks
ALTD
Z
L/V
C
-
-
-
-
H <−> (SP+1); L <−> (SP)
15 (2,2,1,2,2,3,3)
Flags
S
Operation
F
R
I/O
SP
S
D
•
Description
Exchanges the byte in H with the data whose address is the data in SP plus 1; and exchanges the byte in L
with the data whose address is the data in SP.
Instruction Reference Manual
43
EX (SP),IX
EX (SP),IY
Opcode
Instruction
Clocks
Operation
DD E3
EX (SP),IX
15 (2,2,1,2,2,3,3)
IX(high) <−> (SP+1);
IX(low) <−> (SP)
FD E3
EX (SP),IY
15 (2,2,1,2,2,3,3)
IY(high) <−> (SP+1);
IY(low) <−> (SP)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
44
•
EX (SP),IX exchanges the high order byte of IX with the data whose address is 1 plus the
data in the Stack Pointer register, and exchanges the low order byte of IX with the data whose
address is the data in the Stack Pointer register, SP.
•
EX (SP),IY exchanges the high order byte of IY with the data whose address is 1 plus the
data in the Stack Pointer register, and exchanges the low order byte of IY with the data whose
address is the data in the Stack Pointer register.
Rabbit 2000/3000 Microprocessor
EX AF,AF'
Opcode
08
Instruction
EX AF,AF'
Clocks
AF <−> AF'
2
Flags
ALTD
S
Z
L/V
C
-
-
-
-
Operation
F
R
I/O
SP
S
D
Description
Exchanges the data in AF with the data in the alternate register AF'.
Instruction Reference Manual
45
EX DE,HL
EX DE',HL
Opcode
Instruction
Clocks
Operation
EB
EX DE,HL
2
if (!ALTD) then DE <−> HL
else DE <−> HL'
E3
EX DE',HL
2
if (!ALTD) then DE' <−> HL
else DE' <−> HL'
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
•
EX DE,HL exchanges the data in DE with the data in HL. If the ALTD instruction is present
then the data in DE is exchanged with the data in the alternate register HL'.
•
EX DE',HL exchanges the data in the alternate register DE' with the data in HL. If the ALTD
instruction is present then the data in DE' is exchanged with the data in the alternate register HL'.
The Dynamic C assembler recognizes the following instructions, which are based on a combination of ALTD
and the above exchange operations:
46
•
EX DE’,HL’ ; equivalent to ALTD EX DE’,HL
•
EX DE,HL’ ; equivalent to ALTD EX DE’,HL’
Rabbit 2000/3000 Microprocessor
EXX
Opcode
D9
Instruction
EXX
Clocks
Operation
BC <−> BC'; DE <−> DE'; HL <−> HL'
2
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Exchanges the data in BC, DE, and HL, with the data in their respective alternate registers BC', DE', and HL'.
Instruction Reference Manual
47
Rabbit 3000A Instruction
IDET
Opcode
5B
Instruction
IDET
Clocks
Operation
2
Performs “LD E,E”, but if (EDMR &&
SU[0]) then the System Violation
interrupt flag is set.
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
The IDET instruction asserts a System Mode Violation interrupt if System/User mode is enabled (by writing
to the Enable dual Mode Register, EDMR) and the processor is currently in user mode.
Note that IDET has the same opcode value as LD E,E, and actually executes that opcode as well as the behavior described above. If IDET is prefixed by ALTD, the opcode LD E’,E is executed and the special System/
User mode behavior does not occur.
This instruction is implemented in the Rabbit 3000A.
48
Rabbit 2000/3000 Microprocessor
INC (HL)
INC (IX+d)
INC (IY+d)
Opcode
Instruction
Clocks
Operation
34
INC (HL)
8 (2,1,2,3)
(HL) = (HL) + 1
DD 34 d
INC (IX+d)
12 (2,2,2,1,2,3)
(IX + d) = (IX + d) + 1
FD 34 d
INC (IY+d)
12 (2,2,2,1,2,3)
(IY + d) = (IY + d) + 1
Flags
ALTD
S
Z
L/V
C
F
•
•
V
-
•
R
I/O
SP
S
D
•
•
Description
Increments the byte whose address is:
•
held in HL, or
•
the sum of the data in IX and a displacement value d, or
•
the sum of the data in IY and a displacement value d.
Instruction Reference Manual
49
INC IX
INC IY
Opcode
Instruction
Clocks
Operation
DD 23
INC IX
4 (2,2)
IX = IX + 1
FD 23
INC IY
4 (2,2)
IY = IY + 1
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
50
•
INC IX increments the data in IX.
•
INC IY increments the data in IY.
Rabbit 2000/3000 Microprocessor
INC r
Opcode
——
3C
04
0C
14
1C
24
2C
Instruction
INC
INC
INC
INC
INC
INC
INC
INC
r
A
B
C
D
E
H
L
Clocks
Operation
2
2
2
2
2
2
2
2
r
A
B
C
D
E
H
L
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
-
•
•
=
=
=
=
=
=
=
=
r
A
B
C
D
E
H
L
+
+
+
+
+
+
+
+
1
1
1
1
1
1
1
1
I/O
SP
S
D
Description
Increments the data in r (any of the registers A, B, C, D, E, H, or L).
Instruction Reference Manual
51
INC ss
Opcode
——
03
13
23
33
Instruction
INC
INC
INC
INC
INC
ss
BC
DE
HL
SP
Clocks
Operation
2
2
2
2
2
Flags
ss
BC
DE
HL
SP
ALTD
S
Z
L/V
C
-
-
-
-
F
R
=
=
=
=
=
ss
BC
DE
HL
SP
+
+
+
+
+
1
1
1
1
1
I/O
SP
S
D
•
Description
Increments the data in ss (any of BC, DE, HL, or SP).
52
Rabbit 2000/3000 Microprocessor
IOE
IOI
Opcode
Instruction
Clocks
Operation
DB
IOE
2
I/O external prefix
D3
IOI
2
I/O internal prefix
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
•
IOI: The IOI prefix allows the use of existing memory access instructions as internal I/O
instructions. When prefixed, a 16-bit memory instruction accesses the I/O space at the address
specified by the lower byte of the 16-bit address. With IOI, the upper byte of a 16-bit address is
ignored since internal I/O peripherals are mapped within the first 256-bytes of the I/O address
space. Writes to internal I/O registers require two clocks rather than the three required for memory write operations.
•
IOE: The IOE prefix allows the use of existing memory access instructions as external I/O
instructions. Unlike internal I/O peripherals, external I/O devices can be mapped within 8K of
the available 64K address space. Therefore, prefixed 16-bit memory access instructions can be
used more appropriately for external I/O operations. By default, writes are inhibited for external
I/O operations and fifteen wait states are added for I/O accesses.
WARNING: If an I/O prefixed instruction is immediately followed by one of these 12 special one byte
memory access instructions, a bug in the Rabbit 2000 causes I/O access to occur instead of memory access:
ADC A,(HL)
ADD A,(HL)
AND (HL)
CP (HL)
OR (HL)
SBC A,(HL)
SUB (HL)
XOR (HL)
DEC (HL)
INC (HL)
LD r,(HL)
LD (HL),r
This bug can be avoided by putting a NOP instruction between an I/O instruction and any of the aforementioned instructions. Dynamic C versions 6.57 and later will automatically compensate for the bug. This bug
is not present in the Rabbit 3000.
Examples
The following instruction loads the contents of A into the internal I/O register at address location 030h:
IOI
LD (030h), A
These next instructions read a word from external I/O address 0A002:
LD IX, 0A000h
IOE LD HL, (IX+2)
Instruction Reference Manual
53
IPSET
IPSET
IPSET
IPSET
0
1
2
3
Opcode
Instruction
Clocks
Operation
ED 46
IPSET 0
4 (2,2)
IP = {IP[5:0], 00}
ED 56
IPSET 1
4 (2,2)
IP = {IP[5:0], 01}
ED 4E
IPSET 2
4 (2,2)
IP = {IP[5:0], 10}
ED 5E
IPSET 3
4 (2,2)
IP = {IP[5:0], 11}
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
The Interrupt Priority Register, IP is an 8-bit register that forms a stack of the current priority and the other
previous 3 priorities. IPSET 0 forms the lowest priority; IPSET 3 forms the highest priority. These instructions are privileged.
•
IPSET 0: The IPSET 0 instruction shifts the contents of the register holding the previous priorities 2 bits to the left, then sets the Interrupt Priority Register (bits 0 and 1) to 00.
•
IPSET 1: The IPSET 1 instruction first shifts the contents of the register holding the previous
priorities 2 bits to the left, then sets the Interrupt Priority Register (bits 0 and 1) to 01.
•
IPSET 2: The IPSET 2 instruction shifts the contents of the register holding the previous priorities 2 bits to the left, then sets the Interrupt Priority Register (bits 0 and 1) to 10.
•
IPSET 3: The IPSET 3 instruction shifts the contents of the register holding the previous priorities 2 bits to the left, then sets the Interrupt Priority Register (bits 0 and 1) to 11.
Processor Priority
54
Effect on Interrupts
0
All interrupts, priority 1,2 and 3 take place after
execution of current non privileged instruction.
1
Only interrupts of priority 2 and 3 take place
after execution of current non privileged
instruction.
2
Only interrupts of priority 3 take place after
execution of current non privileged instruction.
3
All interrupts are suppressed
(except the RST instruction).
Rabbit 2000/3000 Microprocessor
IPRES
Opcode
ED 5D
Instruction
IPRES
Clocks
Operation
4 (2,2)
Flags
IP = {IP[1:0], IP[7:2]}
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
The IPRES instruction rotates the contents of the Interrupt Priority Register 2 bits to the right, replacing the
current priority with the previous priority. It is impossible to interrupt during the execution of this instruction.
This instruction is privileged.
Example
If the Interrupt Priority register contains 00000110, the execution of the instruction
IPRES
would cause the Interrupt Priority register to contain 10000001.
Instruction Reference Manual
55
JP
JP
JP
JP
(HL)
(IX)
(IY)
mn
Opcode
Instruction
Clocks
Operation
E9
JP (HL)
4 (2,2)
PC = HL
DD E9
JP (IX)
6 (2,2,2)
PC = IX
FD E9
JP (IY)
6 (2,2,2)
PC = IY
C3 n m
JP mn
7 (2,2,2,1)
PC = mn
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
56
•
JP (HL): The data in HL is loaded into PC. Thus the address of the next instruction fetched is
the data in HL.
•
JP (IX): The data in IX is loaded into PC. Thus the address of the next instruction fetched is
the data in IX.
•
JP (IY): The data in IY is loaded into PC. Thus the address of the next instruction fetched is
the data in IY.
•
JP mn: The 16-bit constant mn is loaded into PC. Thus the address of the next instruction
fetched is mn. This instruction recognizes labels when used in the Dynamic C assembler.
Rabbit 2000/3000 Microprocessor
JP f,mn
Opcode
——
C2
CA
D2
DA
E2
EA
F2
FA
n
n
n
n
n
n
n
n
m
m
m
m
m
m
m
m
Instruction
JP
JP
JP
JP
JP
JP
JP
JP
JP
f,mn
NZ,mn
Z,mn
NC,mn
C,mn
LZ,mn
LO,mn
P,mn
M,mn
Clocks
7
7
7
7
7
7
7
7
7
(2,2,2,1)
(2,2,2,1)
(2,2,2,1)
(2,2,2,1)
(2,2,2,1)
(2,2,2,1)
(2,2,2,1)
(2,2,2,1)
(2,2,2,1)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
Operation
F
R
if
if
if
if
if
if
if
if
if
{f} PC = mn
{NZ} PC = mn
{Z} PC = mn
{NC} PC = mn
{C} PC = mn
{LZ/NV} PC = mn
{LO/V} PC = mn
{P} PC = mn
{M} PC = mn
I/O
SP
S
D
Description
If the condition f is true then the 16-bit data mn is loaded into PC. If the condition is false then PC increments
normally.
The condition f is one of the following: NZ, Z flag not set; Z, Z flag set; NC, C flag not set; C, C flag set; LZ,
L/V flag is not set; LO, L/V flag is set; P, S flag not set; M, S flag set.
This instruction recognizes labels when used in the Dynamic C assembler.
Instruction Reference Manual
57
JR cc,e
Opcode
——
20
28
30
38
e-2
e-2
e-2
e-2
Instruction
JR
JR
JR
JR
JR
cc,e
NZ,e
Z,e
NC,e
C,e
Clocks
5
5
5
5
5
(2,2,1)
(2,2,1)
(2,2,1)
(2,2,1)
(2,2,1)
Flags
if
if
if
if
if
ALTD
S
Z
L/V
C
-
-
-
-
Operation
F
R
{cc} PC = PC + e
{NZ} PC = PC + e
{Z} PC = PC + e
{NC} PC = PC + e
{C} PC = PC + e
I/O
SP
S
D
Description
If condition cc is true then the 8-bit signed displacement value e is added to PC.
Since the instruction takes two increments of the PC to complete, two is subtracted from the displacement
value so that the displacement takes place from the instruction opcode.
This instruction recognizes labels when used in the Dynamic C assembler.
58
Rabbit 2000/3000 Microprocessor
JR e
Opcode
18 e-2
Instruction
JR e
Clocks
Operation
5 (2,2,1)
Flags
PC = PC + e
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Adds a signed constant e to PC.
Since the instruction takes two increments of PC to complete, two is subtracted from the displacement value
so that the displacement takes place from the instruction opcode.
This instruction recognizes labels when used in the Dynamic C assembler.
Instruction Reference Manual
59
LCALL x,mn
Opcode
Instruction
CF n m x
LCALL x,mn
Clocks
19 (2,2,2,2,1,3,3,3,1)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
Operation
F
R
(SP - 1) = XPC;
(SP - 2) = PC(high);
(SP - 3) = PC(low);
XPC = x;
PC = mn;
SP = SP - 3
I/O
SP
S
D
Description
This instruction is similar to the CALL routine in that it transfers program execution to the subroutine address
specified by the 16-bit operand mn. The LCALL instruction is special in that it allows calls to be made to a
computed address in XMEM. Note that the value of XPC and consequently the address space defined by the
XPC is dynamically changed with the LCALL instructions.
In the LCALL instruction, first XPC is pushed onto the stack. Next PC is pushed onto the stack, the high
order byte first, then the low order byte. Then the XPC is loaded with the 8-bit value x and the PC is loaded
with the 16-bit value, mn. The SP is then updated to reflect the three items pushed onto it.
The value mn must be in the range E000–FFFF.
Alternate Forms
The Dynamic C assembler recognizes several other forms of this instruction.
LCALL label
LCALL x,label
LCALL x:label
LCALL x:mn
The parameter label is a user defined label. The colon is equivalent to the comma as a delimiter.
60
Rabbit 2000/3000 Microprocessor
LD
LD
LD
LD
(BC),A
(DE),A
(HL),n
(HL),r
Opcode
Instruction
Clocks
Operation
02
LD (BC),A
7 (2,2,3)
(BC) = A
12
LD (DE),A
7 (2,2,3)
(DE) = A
36 n
LD (HL),n
7 (2,2,3)
(HL) = n
——
77
70
71
72
73
74
75
LD
LD
LD
LD
LD
LD
LD
LD
6
6
6
6
6
6
6
6
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL),r
(HL),A
(HL),B
(HL),C
(HL),D
(HL),E
(HL),H
(HL),L
(2,1,3)
(2,1,3)
(2,1,3)
(2,1,3)
(2,1,3)
(2,1,3)
(2,1,3)
(2,1,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
=
=
=
=
=
=
=
=
r
A
B
C
D
E
H
L
I/O
SP
S
D
•
Description
•
LD (BC),A: Loads the memory location whose address is the data in BC with the data in A.
•
LD (DE),A: Loads the memory location whose address is the data in DE with the data in A.
•
LD (HL),n: Loads the memory location whose address is the data in HL with the 8-bit constant n.
•
LD (HL),r: Loads the memory location whose address is the data in HL, with the data in r
(any of the registers A, B, C, D, E, H, or L).
Instruction Reference Manual
61
LD (HL+d),HL
Opcode
DD F4 d
Instruction
Clocks
LD (HL+d),HL
13 (2,2,2,1,3,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
Operation
F
R
(HL+d) = L; (HL+d+1) = H
I/O
SP
S
D
•
Description
Loads the data in L into the memory location whose address is the sum of the data in HL and a displacement
value d. Then, loads the data in H into the memory location whose address is the sum of the data in HL and a
displacement value d plus 1.
62
Rabbit 2000/3000 Microprocessor
LD (IX+d),HL
LD (IX+d),n
LD (IX+d),r
Opcode
Instruction
Clocks
Operation
F4 d
LD (IX+d),HL
11 (2,2,1,3,3)
(IX + d) = L; (IX + d + 1) = H
DD 36 d n
LD (IX+d),n
11 (2,2,2,2,3)
(IX + d) = n
——
DD
DD
DD
DD
DD
DD
DD
LD
LD
LD
LD
LD
LD
LD
LD
10
10
10
10
10
10
10
10
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
77
70
71
72
73
74
75
d
d
d
d
d
d
d
(IX+d),r
(IX+d),A
(IX+d),B
(IX+d),C
(IX+d),D
(IX+d),E
(IX+d),H
(IX+d),L
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
=
=
=
=
=
=
=
=
r
A
B
C
D
E
H
L
I/O
SP
S
D
•
Description
•
LD (IX+d),HL: Loads the data in L into the memory location whose address is the sum of
the data in IX and a displacement value d. Then, loads the data in H into the memory location
whose address is the sum of the data in IX and a displacement value d plus 1.
•
LD (IX+d),n: Loads the 8-bit constant n into the memory location whose address is the sum
of IX and a displacement value d.
•
LD (IX+d),r: Loads the data in r (any of the registers A, B, C, D, E, H, or L) into the memory location whose address is the sum of the data in IX plus a displacement value d.
Instruction Reference Manual
63
LD (IY+d),HL
LD (IY+d),n
LD (IY+d),r
Opcode
Instruction
Clocks
Operation
FD F4 d
LD (IY+d),HL
13 (2,2,2,1,3,3)
(IY + d) = L;
(IY + d + 1) = H
FD 36 d n
LD (IY+d),n
11 (2,2,2,2,3)
(IY + d) = n
——
FD
FD
FD
FD
FD
FD
FD
LD
LD
LD
LD
LD
LD
LD
LD
10
10
10
10
10
10
10
10
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
77
70
71
72
73
74
75
d
d
d
d
d
d
d
(IY+d),r
(IY+d),A
(IY+d),B
(IY+d),C
(IY+d),D
(IY+d),E
(IY+d),H
(IY+d),L
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
(2,2,2,1,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
=
=
=
=
=
=
=
=
r
A
B
C
D
E
H
L
I/O
SP
S
D
•
Description
64
•
LD (IY+d),HL: Loads the data in L into the memory location whose address is the sum of
the data in IY and a displacement value d. Then, loads the data in H into the memory location
whose address is the sum of the data in IY and a displacement value d plus 1.
•
LD (IY+d),n: Loads the 8-bit constant n into the memory location whose address is the
sum of the data in IY and a displacement value d.
•
LD (IY+d),r: Loads the data in r (any of the registers A, B, C, D, E, H, or L) into the memory location whose address is the sum of the data in IY plus a displacement value d.
Rabbit 2000/3000 Microprocessor
LD
LD
LD
LD
LD
(mn),A
(mn),HL
(mn),IX
(mn),IY
(mn),ss
Opcode
Instruction
Clocks
Operation
32 n m
LD (mn),A
a
(mn) = A
22 n m
LD (mn),HL
b
(mn) = L; (mn + 1) = H
DD 22 n m
LD (mn),IX
c
(mn) = IX(low); (mn + 1) = IX(high)
FD 22 n m
LD (mn),IY
c
(mn) = IY(low); (mn + 1) = IY(high)
——
ED
ED
ED
ED
LD
LD
LD
LD
LD
c
c
c
c
c
(mn)
(mn)
(mn)
(mn)
(mn)
43
53
63
73
n
n
n
n
m
m
m
m
(mn),ss
(mn),BC
(mn),DE
(mn),HL
(mn),SP
=
=
=
=
=
ss(low); (mn
C; (mn + 1)
E; (mn + 1)
L; (mn + 1)
P; (mn + 1)
+
=
=
=
=
1) = ss(high)
B
D
H
S
Clocking: (a)10 (2,2,2,1,3) (b)13 (2,2,2,1,3,3) (c)15 (2,2,2,2,1,3,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
•
LD (mn),A: Loads the memory location whose address is mn with the data in A.
•
LD (mn),HL: Loads the memory location whose address is mn with the data in L, then loads
the memory location whose address is 1 plus mn with the data in H.
•
LD (mn),IX: Loads the memory location whose address is mn with the low order byte of the
data in IX, and the memory location whose address is 1 plus mn with the high order byte of the
data in IX.
•
LD (mn),IY: Loads the memory location whose address is mn with the low order byte of the
data in IY, the memory location whose address is 1 plus mn with the high order byte of the data
in IY into.
•
LD (mn),ss: Loads the memory location whose address is mn with the low order byte of the
data in ss (any of BC, DE, HL or SP). Then, loads the memory location whose address is 1 plus
mn with the high order byte of the data in ss.
Instruction Reference Manual
65
LD (SP+n),HL
LD (SP+n),IX
LD (SP+n),IY
Opcode
Instruction
Clocks
Operation
D4 n
LD (SP+n),HL
11 (2,2,1,3,3)
(SP + n) = L; (SP + n + 1) = H
DD D4 n
LD (SP+n),IX
13 (2,2,2,1,3,3)
(SP + n) = IX(low);
(SP + n + 1) = IX(high)
FD D4 n
LP (SP+n),IY
13 (2,2,2,1,3,3)
(SP + n) = IY(low);
(SP + n + 1) = IY(high)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
66
•
LD (SP+n),HL: Loads the data in the L into the memory location whose address is the sum
of the data in SP and the displacement n. Then loads the data in the H into the memory location
whose address is the sum of the data in SP, the displacement n, and 1.
•
LD (SP+n),IX: Loads the low order byte of the data in IX into the memory location whose
address is the sum of the data in SP and the displacement n. Then loads the high order byte of the
data in IX into the memory location whose address is the sum of data in SP, the displacement n,
and 1.
•
LD (SP+n),IY: Loads the low order byte of the data in IY into the memory location whose
address is the sum of the data in SP and the displacement n. Then loads the high order byte of the
data in IY into the memory location whose address is the sum of data in SP, the displacement n,
and 1.
Rabbit 2000/3000 Microprocessor
LD A,(BC)
LD A,(DE)
LD A,(mn)
Opcode
Instruction
Clocks
Operation
0A
LD A,(BC)
6 (2,2,2)
A = (BC)
1A
LD A,(DE)
6 (2,2,2)
A = (DE)
3A n m
LD A,(mn)
9 (2,2,2,1,2)
A = (mn)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
•
I/O
SP
S
D
•
Description
Loads A with the data whose address in memory is:
•
the data in BC, or
•
the data in DE, or
•
the 16-bit constant mn.
Instruction Reference Manual
67
LD A,EIR
LD A,IIR
Opcode
Instruction
Clocks
Operation
ED 57
LD A,EIR
4 (2,2)
A = EIR
ED 5F
LD A,IIR
4 (2,2)
A = IIR
Flags
ALTD
S
Z
L/V
C
F
R
•
•
-
-
•
•
I/O
SP
S
D
Description
68
•
LD A,EIR: Loads A with the data in the External Interrupt Register, EIR. The EIR is used to
specify the Most Significant Byte (MSB) of the External Interrupt address. The value loaded in
the EIR is concatenated with the appropriate External Interrupt address to form the 16-bit ISR
starting address.
•
LD A,IIR: Loads A with the data in the Internal Interrupt Register, IIR. The IIR is used to
specify the Most Significant Byte (MSB) of the Internal Peripheral Interrupt address. The value
loaded in the IIR is concatenated with the appropriate Internal Peripheral address to form the 16bit ISR starting address for that peripheral.
Rabbit 2000/3000 Microprocessor
LD A,XPC
Opcode
ED 77
Instruction
LD A,XPC
Clocks
Operation
4 (2,2)
Flags
A = XPC
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
Loads A with the data in XPC. This instruction is privileged.
Instruction Reference Manual
69
LD dd,(mn)
Opcode
Instruction
——
ED
ED
ED
ED
4B
5B
6B
7B
n
n
n
n
m
m
m
m
Clocks
Operation
LD dd,(mn)
13 (2,2,2,2,1,2,2)
LD
LD
LD
LD
13
13
13
13
dd(low) = (mn);
dd(high) = (mn + 1)
C = (mn); B = (mn + 1)
E = (mn); D = (mn + 1)
L = (mn); H = (mn + 1)
SP(low)=(mn); SP(high)=(mn+1)
BC,(mn)
DE,(mn)
HL,(mn)
SP,(mn)
(2,2,2,2,1,2,2)
(2,2,2,2,1,2,2)
(2,2,2,2,1,2,2)
(2,2,2,2,1,2,2)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
•
I/O
SP
S
D
•
Description
Loads the low-order byte of the dd (any of BC, DE, HL or SP) with the data at memory address mn. Then
loads the high-order byte of register dd with data at memory address mn plus 1.
70
Rabbit 2000/3000 Microprocessor
LD dd',BC
LD dd',DE
Opcode
Instruction
Clocks
Operation
——
ED 49
ED 59
ED 69
LD
LD
LD
LD
dd',BC
BC',BC
DE',BC
HL',BC
4
4
4
4
(2,2)
(2,2)
(2,2)
(2,2)
dd'
BC'
DE'
HL'
=
=
=
=
BC
BC
BC
BC
——
ED 41
ED 51
ED 61
LD
LD
LD
LD
dd',DE
BC',DE
DE',DE
HL',DE
4
4
4
4
(2,2)
(2,2)
(2,2)
(2,2)
dd'
BC'
DE'
HL'
=
=
=
=
DE
DE
DE
DE
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Loads the alternate register dd' (any of the registers BC', DE', or HL') with the data in BC or DE.
Instruction Reference Manual
71
LD dd,mn
Opcode
——
01
11
21
31
n
n
n
n
m
m
m
m
Instruction
LD
LD
LD
LD
LD
dd,mn
BC,mn
DE,mn
HL,mn
SP,mn
Clocks
6
6
6
6
6
Operation
(2,2,2)
(2,2,2)
(2,2,2)
(2,2,2)
(2,2,2)
Flags
dd
BC
DE
HL
SP
ALTD
S
Z
L/V
C
-
-
-
-
F
R
=
=
=
=
=
mn
mn
mn
mn
mn
I/O
SP
S
D
•
Description
Loads dd (any of BC, DE, HL, or SP) with the 16-bit value mn.
72
Rabbit 2000/3000 Microprocessor
LD EIR,A
LD IIR,A
Opcode
Instruction
Clocks
Operation
ED 47
LD EIR,A
4 (2,2)
EIR = A
ED 4F
LD IIR,A
4 (2,2)
IIR = A
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
•
LD EIR,A: Loads the External Interrupt Register, EIR, with the data in A. The EIR is used to
specify the Most Significant Byte (MSB) of the External Interrupt address. The value loaded in
the EIR is concatenated with the appropriate External Interrupt address to form the 16-bit ISR
starting address.
•
LD IIR,A: Loads the Internal Interrupt Register, IIR, with the data in A. The IIR is used to
specify the Most Significant Byte (MSB) of the Internal Peripheral Interrupt address. The value
loaded in the IIR is concatenated with the appropriate Internal Peripheral address to form the 16bit ISR starting address for that peripheral.
Instruction Reference Manual
73
LD
LD
LD
LD
HL,(mn)
HL,(HL+d)
HL,(IX+d)
HL,(IY+d)
Opcode
Instruction
Clocks
Operation
2A mn
LD HL,(mn)
11 (2,2,2,1,2,2)
L = (mn); H = (mn + 1)
DD E4 d
LD HL,(HL+d)
11 (2,2,2,1,2,2)
L = (HL + d); H = (HL + d + 1)
E4 d
LD HL,(IX+d)
9 (2,2,1,2,2)
L = (IX + d); H = (IX + d + 1)
FD E4 d
LD HL,(IY+d)
11 (2,2,2,1,2,2)
L = (IY + d); H = (IY + d + 1)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
•
I/O
SP
S
D
•
Description
74
•
LD HL,(mn): Loads L with the data whose address is mn and loads the H with the data
whose address is mn plus 1.
•
LD HL,(HL+d): Loads L with the data whose address is the data in HL plus a displacement
d. Then loads H with the data whose address is the data in HL plus a displacement d plus 1.
•
LD HL,(IX+d): Loads L with the data whose address is the data in IX plus a displacement
d. Then loads H with the data whose address is the data in IX plus a displacement d plus 1.
•
LD HL,(IY+d): Loads L with the data whose address is the data in IY plus a displacement
d. Then loads H with the data whose address is the data in IY plus a displacement d plus 1.
Rabbit 2000/3000 Microprocessor
LD HL,(SP+n)
Opcode
C4 n
Instruction
Clocks
LD HL,(SP+n)
Operation
9 (2,2,1,2,2)
Flags
L = (SP + n); H = (SP + n + 1)
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
Loads L with the data whose address is the data in SP plus a displacement d. Then loads H with the data
whose address is the data in SP plus a displacement d plus 1.
Instruction Reference Manual
75
LD HL,IX
LD HL,IY
Opcode
Instruction
Clocks
Operation
DD 7C
LD HL,IX
4 (2,2)
HL = IX
FD 7C
LD HL,IY
4 (2,2)
HL = IY
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
76
•
LD HL,IX: Loads HL with the data in IX.
•
LD HL,IY: Loads HL with the data in IY.
Rabbit 2000/3000 Microprocessor
LD IX,(mn)
Opcode
Instruction
DD 2A n m
LD IX,(mn)
Clocks
13*
Operation
IX(low) = (mn); IX(high) = (mn + 1)
*Clocking: 13 (2,2,2,2,1,2,2)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
Loads the low order byte of IX with the data whose address is mn. Then loads the high order byte of IX with
the data whose address is mn plus 1.
Instruction Reference Manual
77
LD IX,(SP+n)
Opcode
DD C4 n
Instruction
LD IX,(SP+n)
Clocks
Operation
11*
IX(low) = (SP + n); IX(high) = (SP + n + 1)
*Clocking: 11 (2,2,2,1,2,2)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Loads the low order byte of IX with the data whose address is the data in the Stack Pointer, SP, plus a displacement n. Then loads the high order byte of IX with the data whose address is the data in the Stack Pointer
register plus a displacement n plus 1.
78
Rabbit 2000/3000 Microprocessor
LD
LD
LD
LD
IX,HL
IX,mn
IY,HL
IY,mn
Opcode
Instruction
Clocks
Operation
DD 7D
LD IX,HL
4 (2,2)
IX = HL
DD 21 n m
LD IX,mn
8 (2,2,2,2)
IX = mn
FD 7D
LD IY,HL
4 (2,2)
IY = HL
FD 21 n m
LD IY,mn
8 (2,2,2,2)
IY = mn
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
•
LD IX,HL: Loads IX with the data in HL.
•
LD IX,mn: Loads IX with the 16-bit constant mn.
•
LD IY,HL: Loads IY with the data in HL.
•
LD IX,mn: Loads IY with the 16-bit constant mn.
Instruction Reference Manual
79
LD IY,(mn)
Opcode
FD 2A n m
Instruction
LD IY,(mn)
Clocks
Operation
13*
IY(low) = (mn); IY(high) = (mn + 1)
*Clocking: 13 (2,2,2,2,1,2,2)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
Description
Loads the low order byte of IY with the data at the address mn and loads the high order byte of IY with the
data at the address mn+1.
80
Rabbit 2000/3000 Microprocessor
LD IY,(SP+n)
Opcode
FD C4 n
Instruction
Clocks
Operation
LD IY,(SP+n)
11*
IY(low) = (SP + n); IY(high) = (SP + n + 1)
*Clocking: 11 (2,2,2,1,2,2)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Loads the low order byte of IY with the data whose address is the data in the Stack Pointer register SP plus a
displacement n. Then loads the high order byte of IY with the data whose address is the data in the Stack
Pointer register plus a displacement n plus 1.
Instruction Reference Manual
81
LD r,(HL)
LD r,(IX+d)
LD r,(IY+d)
Opcode
——
7E
46
4E
56
5E
66
6E
Instruction
Clocks
Operation
LD
LD
LD
LD
LD
LD
LD
LD
r,(HL)
A,(HL)
B,(HL)
C,(HL)
D,(HL)
E,(HL)
H,(HL)
L,(HL)
5
5
5
5
5
5
5
5
(2,1,2)
(2,1,2)
(2,1,2)
(2,1,2)
(2,1,2)
(2,1,2)
(2,1,2)
(2,1,2)
r
A
B
C
D
E
H
L
=
=
=
=
=
=
=
=
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
——
DD
DD
DD
DD
DD
DD
DD
7E
46
4E
56
5E
66
6E
d
d
d
d
d
d
d
LD
LD
LD
LD
LD
LD
LD
LD
r,(IX+d)
A,(IX+d)
B,(IX+d)
C,(IX+d)
D,(IX+d)
E,(IX+d)
H,(IX+d)
L,(IX+d)
9
9
9
9
9
9
9
9
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
r
A
B
C
D
E
H
L
=
=
=
=
=
=
=
=
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
——
FD
FD
FD
FD
FD
FD
FD
7E
46
4E
56
5E
66
6E
d
d
d
d
d
d
d
LD
LD
LD
LD
LD
LD
LD
LD
r,(IY+d)
A,(IY+d)
B,(IY+d)
C,(IY+d)
D,(IY+d)
E,(IY+d)
H,(IY+d)
L,(IY+d)
9
9
9
9
9
9
9
9
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
(2,2,2,1,2)
r
A
B
C
D
E
H
L
=
=
=
=
=
=
=
=
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
•
S
D
•
Description
Loads r (any of the registers A, B, C, D, E, H, or L) with the data whose address is:
82
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d.
Rabbit 2000/3000 Microprocessor
LD r,n
Opcode
——
3E
06
0E
16
1E
26
2E
n
n
n
n
n
n
n
Instruction
LD
LD
LD
LD
LD
LD
LD
LD
r,n
A,n
B,n
C,n
D,n
E,n
H,n
L,n
Clocks
4
4
4
4
4
4
4
4
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
Flags
r
A
B
C
D
E
H
L
ALTD
S
Z
L/V
C
-
-
-
-
Operation
F
R
=
=
=
=
=
=
=
=
n
n
n
n
n
n
n
n
I/O
SP
S
D
•
Description
Loads r (any of the registers A, B, C, D, E, H, or L) with the 8-bit constant n.
Instruction Reference Manual
83
LD r,g
Opcode
r,g
A
Instruction
B
C
D
E
H
L
A
7F
78
79
7A
7B
7C
7D
B
47
40
41
42
43
44
45
C
4F
48
49
4A
4B
4C
4D
D
57
50
51
52
53
54
55
E
5F
58
59
5A
5B
5C
5D
H
67
60
61
62
63
64
65
L
6F
68
69
6A
6B
6C
6D
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
LD r,g
Clocks
2
Operation
r = g
I/O
SP
S
D
•
Description
Loads r (any of the registers A, B, C, D, E, H, or L) with the data in g (any of the registers A, B, C, D, E, H,
or L).
84
Rabbit 2000/3000 Microprocessor
LD SP,HL
LD SP,IX
LD SP,IY
Opcode
Instruction
Clocks
Operation
F9
LD SP,HL
2
SP = HL
DD F9
LD SP,IX
4 (2,2)
SP = IX
FD F9
LD SP,IY
4 (2,2)
SP = IY
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Loads SP with the data in (a) HL, (b) the data in IX, or (c) the data in IY. These are privileged instructions.
Instruction Reference Manual
85
LD XPC,A
Opcode
ED 67
Instruction
LD XPC,A
Clocks
Operation
4 (2,2)
Flags
XPC = A
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Loads XPC with the data in A. This instruction is privileged.
86
Rabbit 2000/3000 Microprocessor
LDD
LDDR
LDI
LDIR
Opcode
Instruction
Clocks
ED A8
LDD
10 (2,2,1,2,3)
(DE) = (HL); BC = BC - 1;
DE = DE - 1; HL = HL - 1
ED B8
LDDR
6 + 7i (2,2,1,(2,3,2)i,1)
repeat:
(DE) = (HL); BC = BC - 1;
DE = DE - 1; HL = HL - 1
until { BC == 0 }
ED A0
LDI
10 (2,2,1,2,3)
(DE) = (HL); BC = BC - 1;
DE = DE + 1; HL = HL + 1
ED B0
LDIR
6 + 7i (2,2,1,(2,3,2)i,1)
repeat:
(DE) = (HL); BC = BC - 1;
DE = DE + 1; HL = HL + 1
until { BC == 0 }
Flags
Operation
ALTD
S
Z
L/V
C
-
-
•
-
F
R
I/O
SP
S
D
•
Description
•
LDD: Loads the memory location whose address is in DE with the data at the address in HL.
Then it decrements the data in BC, DE, and HL.
•
LDDR: While the data in BC does not equal 0 then the memory location whose address is in DE
is loaded with the data at the address in HL. Then it decrements the data in BC, DE, and HL. The
instruction then repeats until BC equals zero.
•
LDI: Loads the memory location whose address is in DE with the data at the address in HL.
Then the data in BC is decremented and the data in DE and HL is incremented.
•
LDIR: While the data in BC does not equal 0 then the memory location whose address is in DE
is loaded with the data at the address in HL. Then the data in BC is decremented and the data in
DE and HL are incremented. The instruction then repeats until BC equals zero.
If any of these block move instructions are prefixed by IOI or IOE, the destination will be in the specified I/O
space. Add 1 clock for each iteration for the prefix if the prefix is IOI (internal I/O). If the prefix is IOE, add 2
clocks plus the number of I/O wait states enabled. The V flag is cleared when BC transitions from 1 to 0. If
the V flag is not cleared another step is performed for the repeating versions of the instructions. Interrupts can
occur between different repeats, but not within an iteration equivalent to LDD or LDI. Return from the interrupt is to the first byte of the instruction which is the I/O prefix byte if there is one.
Instruction Reference Manual
87
Rabbit 3000A Instruction
LDDSR
LDISR
Opcode
Instruction
Clocks
Operation
ED 98
LDDSR
6+7i (2,2,1,
(2,3,2)i,1)
(DE) = (HL);
BC = BC - 1; HL = HL - 1;
repeat while BC != 0
ED 90
LDISR
6+7i (2,2,1,
(2,3,2)i,1)
(DE) = (HL);
BC = BC; HL = HL + 1;
repeat while BC != 0
Flags
ALTD
S
Z
L/V
C
-
-
•
-
F
R
I/O
SP
S
D
•
Description
•
LDDSR: While the data in BC does not equal 0, the memory location whose address is in DE is
loaded with the data at the address in HL. The data in BC and HL (but not DE) is then decremented. This instruction then repeats until BC equals zero. If this instruction is prefixed by IOI
or IOE, the destination will be in the specified I/O space.
•
LDISR: While the data in BC does not equal 0, the memory location whose address is in DE is
loaded with the data at the address in HL. The data in BC is then decremented and HL incremented (the data in DE remains unchanged). This instruction then repeats until BC equals zero.
If this instruction is prefixed by IOI or IOE, the destination will be in the specified I/O space.
Add 1 clock for each iteration for the prefix if the prefix is IOI (internal I/O). If the prefix is IOE, add 2 clocks
plus the number of I/O wait states enabled. The V flag is cleared when BC transitions from 1 to 0. If the V
flag is not cleared another step is performed for the repeating versions of the instructions. Interrupts can occur
between different repeats, but not within an iteration. Return from the interrupt is to the first byte of the
instruction which is the I/O prefix byte if there is one.
These instructions are implemented in the Rabbit 3000A.
88
Rabbit 2000/3000 Microprocessor
LDP (HL),HL
LDP (IX),HL
LDP (IY),HL
Opcode
Instruction
Clocks
Operation
ED 64
LDP (HL),HL
12 (2,2,2,3,3)
(HL) = L; (HL + 1) = H.
(Addr[19:16] = A[3:0])
DD 64
LDP (IX),HL
12 (2,2,2,3,3)
(IX) = L; (IX + 1) = H.
(Addr[19:16] = A[3:0])
FD 64
LDP (IY),HL
12 (2,2,2,3,3)
(IY) = L; (IY + 1) = H.
(Addr[19:16] = A[3:0])
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
These instructions are used to access 20-bit addresses. In all cases, the four most significant bits of the 20-bit
address (bits 19 through 16) are defined as the four least significant bits of A (bits 3 though 0). The LDP
instructions bypass the MMU’s address translation unit for direct access to the 20-bit memory address space.
•
LDP (HL),HL: Loads the memory location whose 16 least significant bits of its 20-bit
address are the data in HL with the data in L, and then loads the following 20-bit address with the
data in H.
•
LDP (IX),HL: Loads the memory location whose 16 least significant bits of its 20-bit
address are the data in IX with the data in L, and then loads the following 20-bit address with the
data in H.
•
LDP (IY),HL: Loads the memory location whose 16 least significant bits of its 20-bit
address are the data in IY with the data in L, and then loads the following 20-bit address with the
data in H.
Note that the LDP instructions wrap around on a 64K page boundary. Since the LDP instruction operates on
two-byte values, the second byte will wrap around and be written at the start of the page if you try to read or
write across a page boundary. Thus, if you fetch or store at address 0xn,0xFFFF, you will get the bytes
located at 0xn, 0xFFFF and 0xn,0x0000 instead of 0xn,0xFFFF and 0x(n+1),0x0000 as you might expect.
Therefore, do not use LDP at any physical address ending in 0xFFFF.
Instruction Reference Manual
89
LDP (mn),HL
LDP (mn),IX
LDP (mn),IY
Opcode
Instruction
Clocks
Operation
ED 65 n m
LDP (mn),HL
15*
(mn) = L; (mn + 1) = H.
(Addr[19:16] = A[3:0])
DD 65 n m
LDP (mn),IX
15*
(mn) = IX(low); (mn + 1) = IX(high).
(Addr[19:16] = A[3:0])
FD 65 n m
LDP (mn),IY
15*
(mn) = IY(low); (mn + 1) = IY(high).
(Addr[19:16] = A[3:0])
*Clocking: 15 (2,2,2,2,1,3,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
These instructions are used to access 20-bit addresses. In all cases, the four most significant bits of the 20-bit
address (bits 19 through 16) are defined as the four least significant bits of A (bits 3 though 0). The LDP
instructions bypass the MMU’s address translation unit for direct access to the 20-bit memory address space.
•
LDP (mn),HL: Loads the memory location whose 16 least significant bits of its 20-bit
address are the 16-bit constant mn with the data in L, and then loads the following memory location with the data in H.
•
LDP (mn),IX: Loads the memory location whose 16 least significant bits of its 20-bit
address are the 16-bit constant mn with the low order byte of IX, and then loads the following
memory location with the high order byte of IX.
•
LDP (mn),IY: Loads the memory location whose 16 least significant bits of its 20-bit
address are the 16-bit constant mn with the low order byte of IY, and then loads the following
memory location with the high order byte of IY.
Note that the LDP instructions wrap around on a 64K page boundary. Since the LDP instruction operates on
two-byte values, the second byte will wrap around and be written at the start of the page if you try to read or
write across a page boundary. Thus, if you fetch or store at address 0xn,0xFFFF, you will get the bytes
located at 0xn, 0xFFFF and 0xn,0x0000 instead of 0xn,0xFFFF and 0x(n+1),0x0000 as you might expect.
Therefore, do not use LDP at any physical address ending in 0xFFFF.
90
Rabbit 2000/3000 Microprocessor
LDP HL,(HL)
LDP HL,(IX)
LDP HL,(IY)
Opcode
Instruction
Clocks
ED 6C
LDP HL,(HL)
10 (2,2,2,2,2)
L = (HL); H = (HL + 1).
(Addr[19:16] = A[3:0])
DD 6C
LDP HL,(IX)
10 (2,2,2,2,2)
L = (IX); H = (IX + 1).
(Addr[19:16] = A[3:0])
FD 6C
LDP HL,(IY)
10 (2,2,2,2,2)
L = (IY); H = (IY + 1).
(Addr[19:16] = A[3:0])
Flags
Operation
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
These instructions are used to access 20-bit addresses. In all cases, the four most significant bits of the 20-bit
address (bits 19 through 16) are defined as the four least significant bits of A (bits 3 though 0). The LDP
instructions bypass the MMU’s address translation unit for direct access to the 20-bit memory address space.
•
LDP HL,(HL): Loads L with the data whose 16 least significant bits of its 20-bit address are
the data in HL, and then loads H with the data in the following 20-bit address.
•
LDP HL,(IX): Loads L with the data whose 16 least significant bits of its 20-bit address are
the data in IX, and then loads H with the data in the following 20-bit address.
•
LDP HL,(IY): Loads L with the data whose 16 least significant bits of its 20-bit address are
the data in IY, and then loads H with the data in the following 20-bit address.
Note that the LDP instructions wrap around on a 64K page boundary. Since the LDP instruction operates on
two-byte values, the second byte will wrap around and be written at the start of the page if you try to read or
write across a page boundary. Thus, if you fetch or store at address 0xn,0xFFFF, you will get the bytes
located at 0xn, 0xFFFF and 0xn,0x0000 instead of 0xn,0xFFFF and 0x(n+1),0x0000 as you might expect.
Therefore, do not use LDP at any physical address ending in 0xFFFF.
Instruction Reference Manual
91
LDP HL,(mn)
LDP IX,(mn)
LDP IY,(mn)
Opcode
Instruction
Clocks
Operation
ED 6D n m
LDP HL,(mn)
13*
L = (mn); H = (mn + 1).
(Addr[19:16] = A[3:0])
DD 6D n m
LDP IX,(mn)
13*
IX(low) = (mn); IX(high) = (mn + 1).
(Addr[19:16] = A[3:0])
FD 6D n m
LDP IY,(mn)
13*
IY(low) = (mn); IY(high) = (mn + 1).
(Addr[19:16] = A[3:0])
*Clocking: 13 (2,2,2,2,1,2,2)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
These instructions are used to access 20-bit addresses. In all cases, the four most significant bits of the 20-bit
address (bits 19 through 16) are defined as the four least significant bits of A (bits 3 though 0). The LDP
instructions bypass the MMU’s address translation unit for direct access to the 20-bit memory address space.
•
LDP HL,(mn): Loads L with the data whose 16 least significant bits of its 20-bit address are
the 16-bit constant mn, and then loads H with the data in the following 20-bit address.
•
LDP IX,(mn): Loads the low order byte of IX with the data whose 16 least significant bits
of its 20-bit address are the 16-bit constant mn, and then loads the high order byte of IX with the
data in the following 20-bit address.
•
LDP IY,(mn): Loads the low order byte of IY with the data whose 16 least significant bits
of its 20-bit address are the 16-bit constant mn, and then loads the high order byte of IY with the
data in the following 20-bit address.
Note that the LDP instructions wrap around on a 64K page boundary. Since the LDP instruction operates on
two-byte values, the second byte will wrap around and be written at the start of the page if you try to read or
write across a page boundary. Thus, if you fetch or store at address 0xn,0xFFFF, you will get the bytes
located at 0xn, 0xFFFF and 0xn,0x0000 instead of 0xn,0xFFFF and 0x(n+1)0x0000 as you might expect.
Therefore, do not use LDP at any physical address ending in 0xFFFF.
92
Rabbit 2000/3000 Microprocessor
LJP x,mn
Opcode
C7 n m x
Instruction
LJP x,mn
Clocks
Operation
10 (2,2,2,2,2)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
XPC = x; PC = mn
I/O
SP
S
D
Description
This instruction is similar to the JP mn instruction in that it transfers program execution to the memory location specified by the 16-bit address, mn. LJP is special in that it allows a jump to be made to a computed
address in XMEM. Note that the value of XPC and consequently the address space defined by the XPC is
dynamically changed with the LJP instructions.
The instruction loads the XPC with the 8-bit constant x. Then loads PC with the 16-bit constant mn, which
must be in the range E000–FFFF.
This instruction recognizes labels when used in the Dynamic C assembler.
Instruction Reference Manual
93
LRET
Opcode
Instruction
ED 45
LRET
Clocks
Operation
13 (2,2,1,2,2,2,2)
Flags
PC(low) = (SP);
PC(high) = (SP+1);
XPC = (SP + 2);
SP = SP + 3
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
The LRET transfers execution from a subroutine to the calling program by popping PC and the XPC off of
the stack, in order to return from an LCALL operation.
First, the low order byte of PC is loaded with the data whose address is in SP. Next, the high order byte of PC
is loaded with the data whose address is one plus the data in SP and XPC is loaded with the data whose
address is two plus the data in SP. Finally the value in SP is incremented by 3.
94
Rabbit 2000/3000 Microprocessor
Rabbit 3000A Instruction
LSDR
LSIR
LSDDR
LSIDR
Opcode
Instruction
Clocks
Operation
ED F8
LSDR
6+7i
(2,2,1,(2,3,2)i,1)
(DE) = (HL); BC = BC-1;
DE = DE-1; HL = HL-1;
repeat while BC != 0
ED F0
LSIR
6+7i
(2,2,1,(2,3,2)i,1)
(DE) = (HL); BC = BC-1;
DE = DE+1; HL = HL+1;
repeat while BC != 0
ED D8
LSDDR
6+7i
(2,2,1,(2,3,2)i,1)
(DE) = (HL);
BC = BC-1; DE = DE-1;
repeat while BC != 0
ED D0
LSIDR
6+7i
(2,2,1,(2,3,2)i,1)
(DE) = (HL);
BC = BC-1; DE = DE+1;
repeat while BC != 0
Flags
ALTD
S
Z
L/V
C
-
-
•
-
F
R
I/O
SP
S
D
•
Description
•
•
•
LSDR: While the data in BC does not equal 0, the memory location whose address is in DE is
loaded with the data at the address in HL. The data in BC, DE, and HL is then decremented.
This instruction then repeats until BC equals zero. If this instruction is prefixed by IOI or IOE,
the source will be in the specified I/O space.
LSIR: While the data in BC does not equal 0, the memory location whose address is in DE is
loaded with the data at the address in HL. The data in BC is then decremented, and the data in
DE and HL is incremented. This instruction then repeats until BC equals zero. If this instruction
is prefixed by IOI or IOE, the source will be in the specified I/O space.
LSDDR: While the data in BC does not equal 0, the memory location whose address is in DE is
loaded with the data at the address in HL. The data in BC and DE (but not HL) is then decremented. This instruction then repeats until BC equals zero. If this instruction is prefixed by IOI
or IOE, the source will be in the specified I/O space.
•
LSIDR: While the data in BC does not equal 0, the memory location whose address is in DE is
loaded with the data ta the address in HL. The data in BC is then decremented and DE incremented (the data in HL remains unchanged). This instruction then repeats until BC equals zero.
If this instruction is prefixed by IOI or IOE, the source will be in the specified I/O space.
Add 1 clock for each iteration for the prefix if the prefix is IOI (internal I/O). If the prefix is IOE, add 2 clocks
plus the number of I/O wait states enabled. The V flag is cleared when BC transitions from 1 to 0. If the V
flag is not cleared another step is performed for the repeating versions of the instructions. Interrupts can occur
between different repeats, but not within an iteration. Return from the interrupt is to the first byte of the
instruction which is the I/O prefix byte if there is one. These instructions are implemented for the Rabbit
3000A.
Instruction Reference Manual
95
MUL
Opcode
F7
Instruction
Clocks
MUL
Operation
12 (2,10)
Flags
HL:BC = BC • DE
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
A signed multiplication operation is performed on the contents of the 16-bit binary integers contained in the
BC and DE registers. The signed 32-bit result is placed in HL (bits 31 through 16) and BC (bits 15 through 0)
registers.
Examples:
LD BC, 0FFFFh
LD DE, 0FFFFh
MUL
;BC gets -1
;DE gets -1
;HL|BC = 1, HL gets 0000h, BC gets 0001h
In the above example, the 2’s complement of FFFFh is 0001h.
LD BC, 0FFFFh
LD DE, 00001h
MUL
96
;BC gets -1
;DE gets 1
;HL|BC = -1, HL gets FFFFh, BC gets FFFFh
Rabbit 2000/3000 Microprocessor
NEG
Opcode
ED 44
Instruction
NEG
Clocks
Operation
4 (2,2)
Flags
A = 0 - A
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
Description
Subtracts the value of the data in A from zero and stores the result in A.
Instruction Reference Manual
97
NOP
Opcode
00
Instruction
NOP
Clocks
Operation
2
No operation
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
No operation is performed during this cycle.
98
Rabbit 2000/3000 Microprocessor
OR (HL)
OR (IX+d)
OR (IY+d)
Opcode
Instruction
Clocks
Operation
B6
OR (HL)
5 (2,1,2)
A = A | (HL)
DD B6 d
OR (IX+d)
9 (2,2,2,1,2)
A = A | (IX+d)
FD B6 d
OR (IY+d)
9 (2,2,2,1,2)
A = A | (IY+d)
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
I/O
SP
S
D
•
Description
Performs a logical OR operation between the byte in A and the byte whose address is (a) in HL, (b) the sum
of the data in IX and a displacement d, or (c) the sum of the data in IY and a displacement d.
The relative bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes
are compared, etc.) and the associated bit in the result byte is set if either of the compared bits is set. The
result is stored in A.
Example
If the byte in A is 0100 1100 and the byte in the memory location pointed to by HL is 1110 0101, the operation:
OR (HL)
would result in A containing 1110 1101.
Instruction Reference Manual
99
OR HL,DE
Opcode
EC
Instruction
OR HL,DE
Clocks
Operation
2
HL = HL | DE
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
I/O
SP
S
D
Description
Performs a logical OR between the data in HL and the data in DE. The relative bits of each byte are compared
(i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes are compared, etc.) and the associated bit in
the result byte is set if either of the compared bits is set. The result is stored in HL.
100
Rabbit 2000/3000 Microprocessor
OR IX,DE
OR IY,DE
Opcode
Instruction
Clocks
Operation
DD EC
OR IX,DE
4 (2,2)
IX = IX | DE
FD EC
OR IY,DE
4 (2,2)
IY = IY | DE
Flags
ALTD
S
Z
L/V
C
F
•
•
L
0
•
R
I/O
SP
S
D
Description
•
OR IX,DE: Performs a logical OR operation between the data in IX and the data in DE. The
result is stored in IX
•
OR IY,DE: Performs a logical OR operation between the data in IY and the data in DE. The
result is stored in IY
The relative bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes
are compared, etc.) and the associated bit in the result byte is set if either of the compared bits is set.
Instruction Reference Manual
101
OR n
OR r
Opcode
Instruction
Clocks
Operation
F6 n
OR n
4 (2,2)
A = A | n
——
B7
B0
B1
B2
B3
B4
B5
OR
OR
OR
OR
OR
OR
OR
OR
2
2
2
2
2
2
2
2
A
A
A
A
A
A
A
A
r
A
B
C
D
E
H
L
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
=
=
=
=
=
=
=
=
A
A
A
A
A
A
A
A
|
|
|
|
|
|
|
|
r
A
B
C
D
E
H
L
I/O
SP
S
D
Description
•
OR n: Performs a logical OR operation between the byte in A and the 8-bit constant n.
•
OR r: Performs a logical OR operation between the byte in A and the byte in r (any of the registers A, B, C, D, E, H, or L).
The relative bits of each byte are compared (i.e., bit 1 of both bytes are compared, bit 2 of both bytes are compared, etc.) and the associated bit in the result byte is set if either of the compared bits is set. The result is
stored in A.
102
Rabbit 2000/3000 Microprocessor
POP IP
POP IX
POP IY
Opcode
Instruction
Clocks
Operation
ED 7E
POP IP
7 (2,2,1,2)
IP = (SP); SP = SP + 1
DD E1
POP IX
9 (2,2,1,2,2)
IX(low) = (SP); IX(high) = (SP + 1);
SP = SP + 2
FD E1
POP IY
9 (2,2,1,2,2)
IY(low) = (SP); IY(high) = (SP + 1);
SP = SP + 2
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
•
POP IP: Loads the Interrupt Priority Register, IP, with the data at the memory location in the
Stack Pointer, SP, and then increments the data in SP. This is a privileged instruction.
•
POP IX: Loads the low order byte of IX with the data at the memory address in the Stack
Pointer, SP, then loads the high order byte of IX with the data at the address immediately following the one held in SP. SP is then incremented twice.
•
POP IY: Loads the low order byte of IY with the data at the memory address in the Stack
Pointer, SP, then loads the high order byte of IY with the data at the memory address immediately following the one held in SP. SP is then incremented twice.
Instruction Reference Manual
103
Rabbit 3000A Instruction
POP SU
Opcode
Instruction
ED 6E
POP SU
Clocks
Operation
9 (2,2,2,3)
SU = (SP); SP = SP + 1
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Loads the System/User Mode Register SU with the data at the memory location in SP, then increments the
data in SP.
This instruction is privileged and is implemented in the Rabbit 3000A.
Instruction Reference Manual
104
POP zz
Opcode
Instruction
——
POP zz
7 (2,1,2,2)
F1
C1
D1
E1
POP
POP
POP
POP
7
7
7
7
AF
BC
DE
HL
Clocks
Operation
zz(low) = (SP); zz(high) =
SP = SP + 2
F = (SP); A = (SP + 1);
C = (SP); B = (SP + 1);
E = (SP); D = (SP + 1);
L = (SP); H = (SP + 1);
(2,1,2,2)
(2,1,2,2)
(2,1,2,2)
(2,1,2,2)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
(SP + 1);
SP
SP
SP
SP
=
=
=
=
SP
SP
SP
SP
+
+
+
+
2
2
2
2
I/O
SP
S
D
•
Description
Loads the low order byte of the zz (any of AF, BC, DE, or HL) with the data at the memory address in SP
then loads the high order byte of zz with the data at the memory address immediately following the one held
in SP. SP is then incremented twice.
Instruction Reference Manual
105
PUSH IP
PUSH IX
PUSH IY
Opcode
Instruction
Clocks
Operation
ED 76
PUSH IP
9 (2,2,2,3)
(SP - 1) = IP; SP = SP - 1
DD E5
PUSH IX
12 (2,2,2,3,3)
(SP - 1) = IX(high); (SP - 2) = IX(low);
SP = SP - 2
FD E5
PUSH IY
12 (2,2,2,3,3)
(SP - 1) = IY(high); (SP - 2) = IY(low);
SP = SP - 2
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
106
•
PUSH IP: Loads the location in memory whose address is 1 less that the data held in the
Stack Pointer, SP, with the data in the Interrupt Priority Register IP. Then decrements SP.
•
PUSH IX: Loads the memory location with the address 1 less than the data in the Stack
Pointer, SP, with the high order byte of the data in IX, and loads the memory location with the
address two less than the data in SP with the low order byte of the data in IX. Then SP is decremented twice.
•
PUSH IY: Loads the memory location with the address 1 less than the data in the Stack
Pointer, SP, with the high order byte of the data in IY, and loads the memory location with the
address two less than the data in SP with the low order byte of the data in IY. Then SP is decremented twice.
Rabbit 2000/3000 Microprocessor
Rabbit 3000A Instruction
PUSH SU
Opcode
Instruction
ED 66
PUSH SU
Clocks
Operation
9 (2,2,2,3)
(SP - 1) = SU; SP = SP - 1
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Loads the location in memory whose address is 1 less than the data held in SP with the data in the System/
User Mode Register (SU) then decrements SP.
This instruction is privileged and is implemented in the Rabbit 3000A.
Instruction Reference Manual
107
PUSH zz
Opcode
Instruction
——
PUSH zz
10 (2,2,3,3)
F5
C5
D5
E5
PUSH
PUSH
PUSH
PUSH
10
10
10
10
AF
BC
DE
HL
Clocks
Operation
(SP - 1) = zz(high); (SP
SP = SP - 2
(SP - 1) = A; (SP - 2)
(SP - 1) = B; (SP - 2)
(SP - 1) = D; (SP - 2)
(SP - 1) = H; (SP - 2)
(2,2,3,3)
(2,2,3,3)
(2,2,3,3)
(2,2,3,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
- 2) = zz(low);
=
=
=
=
F;
C;
E;
L;
SP
SP
SP
SP
=
=
=
=
SP
SP
SP
SP
-
2
2
2
2
I/O
SP
S
D
Description
Loads the memory location with the address 1 less than the data in the SP with the high order byte of the data
in zz (any of AF, BC, DE, or HL), and loads the memory location with the address two less than the data in
SP with the low order byte of the data in zz. Then SP is decremented twice.
108
Rabbit 2000/3000 Microprocessor
Rabbit 3000A Instruction
RDMODE
Opcode
Instruction
ED 7F
RDMODE
Clocks
Operation
4 (2,2)
CF = SU[0]
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
The RDMODE instruction sets the C flag to the value of bit 0 of the System/User Mode Register (SU).
This instruction is implemented in the Rabbit 3000A.
Instruction Reference Manual
109
RES b,(HL)
RES b,(IX+d)
RES b,(IY+d)
Opcode
Instruction
Clocks
RES
RES
RES
RES
RES
RES
RES
RES
RES
b,(HL)
bit 0,(HL)
bit 1,(HL)
bit 2,(HL)
bit 3,(HL)
bit 4,(HL)
bit 5,(HL)
bit 6,(HL)
bit 7,(HL)
10*
10*
10*
10*
10*
10*
10*
10*
10*
Operation
——
CB
CB
CB
CB
CB
CB
CB
CB
86
8E
96
9E
A6
AE
B6
BE
——
DD
DD
DD
DD
DD
DD
DD
DD
CB
CB
CB
CB
CB
CB
CB
CB
d
d
d
d
d
d
d
d
86
8E
96
9E
A6
AE
B6
BE
RES
RES
RES
RES
RES
RES
RES
RES
RES
b,(IX+d)
bit 0,(IX+d)
bit 1,(IX+d)
bit 2,(IX+d)
bit 3,(IX+d)
bit 4,(IX+d)
bit 5,(IX+d)
bit 6,(IX+d)
bit 7,(IX+d)
13**
13**
13**
13**
13**
13**
13**
13**
13**
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
+
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
d)
=
=
=
=
=
=
=
=
=
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
+
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
d)
&
&
&
&
&
&
&
&
&
~bit
~bit
~bit
~bit
~bit
~bit
~bit
~bit
~bit
0
1
2
3
4
5
6
7
——
FD
FD
FD
FD
FD
FD
FD
FD
CB
CB
CB
CB
CB
CB
CB
CB
d
d
d
d
d
d
d
d
86
8E
96
9E
A6
AE
B6
BE
RES
RES
RES
RES
RES
RES
RES
RES
RES
b,(IY+d)
bit 0,(IY+d)
bit 1,(IY+d)
bit 2,(IY+d)
bit 3,(IY+d)
bit 4,(IY+d)
bit 5,(IY+d)
bit 6,(IY+d)
bit 7,(IY+d)
13**
13**
13**
13**
13**
13**
13**
13**
13**
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
+
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
d)
=
=
=
=
=
=
=
=
=
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
+
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
d)
&
&
&
&
&
&
&
&
&
~bit
~bit
~bit
~bit
~bit
~bit
~bit
~bit
~bit
0
1
2
3
4
5
6
7
Clocking:
*10 (2,2,1,2,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
=
=
=
=
=
=
=
=
=
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
&
&
&
&
&
&
&
&
&
~bit
~bit
~bit
~bit
~bit
~bit
~bit
~bit
~bit
b
0
1
2
3
4
5
6
7
**13 (2,2,2,2,2,3)
I/O
SP
S
D
•
Description
Resets bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the data whose address is:
•
•
•
held in HL, or
the sum of the data in IX and a displacement d, or
the sum of the data in IY and a displacement d.
The bit is reset by performing a logical AND between the selected bit and its complement.
110
Rabbit 2000/3000 Microprocessor
RES b,r
Opcode
b,r
Instruction
A
B
C
D
E
H
L
CB(0)
87
80
81
82
83
84
85
CB(1)
8F
88
89
8A
8B
8C
8D
CB(2)
97
90
91
92
93
94
95
CB(3)
9F
98
99
9A
9B
9C
9D
CB(4)
A7
A0
A1
A2
A3
A4
A5
CB(5)
AF
A8
A9
AA
AB
AC
AD
CB(6)
B7
B0
B1
B2
B3
B4
B5
CB(7)
BF
B8
B9
BA
BB
BC
BD
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
RES b,r
Clocks
Operation
4 (2,2)
r =
r & ~bit
I/O
SP
S
D
•
Description
Resets bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the data held in r (any of the register A, B, C, D, E, H, or
L).
The bit is reset by performing a logical AND between the selected bit and its complement.
Instruction Reference Manual
111
RET
Opcode
Instruction
C9
RET
Clocks
Operation
8 (2,1,2,2,1)
Flags
PC(low) = (SP); PC(high) = (SP + 1);
SP = SP + 2
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
RET transfers execution from a subroutine to the program that called it. First it loads the low order byte of PC
with the data at the memory address in SP then loads the high order byte of PC with the data at the memory
address immediately following the one held in SP. The data in SP is then incremented twice.
112
Rabbit 2000/3000 Microprocessor
RET f
Opcode
Instruction
——
C0
C8
D0
D8
E0
E8
F0
F8
RET
RET
RET
RET
RET
RET
RET
RET
RET
f
NZ
Z
NC
C
LZ
LO
P
M
Operation
If
If
If
If
If
If
If
If
If
{f} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
{NZ} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
{Z} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
{NC} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
{C} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
{LZ} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
{LO} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
{P} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
{M} PC(low) = (SP); PC(high) = (SP + 1); SP = SP + 2
Clocking: 2; 8 (2,1,2,2,1)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
If the condition f is false, then the instruction is ignored. If the condition f is true, then the instruction loads the
low order byte of PC with the data at the memory address in SP then loads the high order byte of PC with the
data at the memory address immediately following the one held in SP and the data in SP is then incremented
twice.
The condition f is one of the following:
•
NZ
Z flag not set
•
Z
Z flag set
•
NC
C flag not set
•
C
C flag set
•
LZ/NV
L/V flag is not set
•
LO/V
L/V flag is set
•
P
S flag not set
•
M
S flag set.
Instruction Reference Manual
113
RETI
Opcode
ED 4D
Instruction
RETI
Clocks
Operation
12 (2,2,1,2,2,2,1)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
IP = (SP); PC(low) = (SP+1);
PC(high) = (SP + 2); SP = SP + 3
I/O
SP
S
D
Description
Loads the Interrupt Priority register (IP) with the data whose address is in SP. Then loads the low order byte
of PC with the data whose address is 1 higher than the data in SP and loads the high order byte of PC with the
data whose address is two higher than the data in SP. The data in SP is then incremented three times. This is a
privileged instruction.
114
Rabbit 2000/3000 Microprocessor
RL (HL)
RL (IX+d)
RL (IY+d)
Opcode
Instruction
Clocks
Operation
CB 16
RL (HL)
10 (2,2,1,2,3)
{CF,(HL)} = {(HL),CF}
DD CB d 16
RL (IX+d)
13 (2,2,2,2,2,3)
{CF,(IX + d)} = {(IX + d),CF}
FD CB d 16
RL (IY+d)
13 (2,2,2,2,2,3)
{CF,(IY + d)} = {(IY + d),CF}
Flags
ALTD
S
Z
L/V
C
F
•
•
L
•
•
R
I/O
SP
S
D
•
•
Description
Rotates to the left with the C flag the data whose address is:
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d.
Bits 0 through 6 move to the next highest-order bit position (bit 0 moves to bit 1, etc.) while the C flag moves
to bit 0 and bit 7 moves to the C flag. See Figure 1 below.
CF
7
0
Figure 1: The bit logic of the RL instruction.
Example
If HL contains 0x4545, the byte in the memory location 0x4545 is 0110 1010, and the C flag is set, then after
the execution of the operation
RL (HL)
the byte in memory location 0x4545 will contain 1101 0101 and the C flag will be reset.
Instruction Reference Manual
115
RL DE
Opcode
F3
Instruction
RL DE
Clocks
Operation
2
{CF,DE} = {DE,CF}
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
I/O
SP
S
D
Description
Rotates to the left with the C flag the contents of register DE. Each bit in the register moves to the next highest-order bit position (bit 0 moves to bit 1, etc.) while the C flag moves to bit 0 and bit 15 moves to the C flag.
See figure below.
CF
15
0
Figure 2: Bit logic of the RL instruction.
116
Rabbit 2000/3000 Microprocessor
RL r
Opcode
——
CB
CB
CB
CB
CB
CB
CB
17
10
11
12
13
14
15
Instruction
RL
RL
RL
RL
RL
RL
RL
RL
r
A
B
C
D
E
H
L
Clocks
4
4
4
4
4
4
4
4
Operation
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
Flags
{CF,r}
{CF,A}
{CF,B}
{CF,C}
{CF,D}
{CF,E}
{CF,H}
{CF,L}
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
=
=
=
=
=
=
=
=
{r,CF}
{A,CF}
{B,CF}
{C,CF}
{D,CF}
{E,CF}
{H,CF}
{L,CF}
I/O
SP
S
D
Description
Rotates to the left with the C flag the contents of r (any of the register A, B, C, D, E, H, or L). Each bit in the
register moves to the next highest-order bit position (bit 0 moves to bit 1, etc.) while the C flag moves to bit 0
and bit 7 moves to the C flag. See Figure 1 on page 115.
Instruction Reference Manual
117
RLA
Opcode
17
Instruction
RLA
Clocks
Operation
2
{CF,A} = {A,CF}
Flags
ALTD
S
Z
L/V
C
F
R
-
-
-
•
•
•
I/O
SP
S
D
Description
Rotates to the left with the C flag the contents of A. Each bit in the register moves to the next highest-order bit
position (bit 0 moves to bit 1, etc.) while the C flag moves to bit 0 and bit 7 moves to the C flag. See Figure 1
on page 115.
118
Rabbit 2000/3000 Microprocessor
RLC (HL)
RLC (IX+d)
RLC (IY+d)
Opcode
Instruction
Clk
CB 06
RLC (HL)
DD CB d 06
RLC (IX+d)
FD CB d 06
RLC (IY+d)
Operation
10*
(HL) = {(HL)[6,0],(HL)[7]};
CF = (HL)[7]
13**
(IX + d) = {(IX + d)[6,0],(IX + d)[7]};
CF = (IX+d)[7]
13**
(IY + d) = {(IY + d)[6,0],(IY + d)[7]};
CF = (IY + d)[7]
Clk: Clocking: *10 (2,2,1,2,3)
Flags
ALTD
S
Z
L/V
C
F
•
•
L
•
•
R
**13 (2,2,2,2,2,3)
I/O
SP
S
D
•
•
Description
Rotates to the left the data whose address is:
• the data in HL, or
• the sum of the data in IX and a displacement d, or
• the sum of the data in IY and a displacement d.
Each bit in the register moves to the next highest-order bit position (bit 0 moves to bit 1, etc.) while bit 7
moves to both bit 0 and the C flag. See figure below.
CF
7
0
Figure 3: The bit logic of the RLC instruction.
Example
If HL contains 0x4545, the byte in the memory location 0x4545 is 0110 1010, and the C flag is set, then after
the execution of the operation:
RLC (HL)
the byte in memory location 0x4545 will contain 1101 0100 and the C flag will be reset.
Instruction Reference Manual
119
RLC r
Opcode
——
CB
CB
CB
CB
CB
CB
CB
07
00
01
02
03
04
05
Instruction
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
Clocks
r
A
B
C
D
E
H
L
4
4
4
4
4
4
4
4
Operation
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
r
A
B
C
D
E
H
L
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
=
=
=
=
=
=
=
=
{r[6,0],r[7]};
{A[6,0],A[7]};
{B[6,0],B[7]};
{C[6,0],C[7]};
{D[6,0],D[7]};
{E[6,0],E[7]};
{H[6,0],H[7]};
{L[6,0],L[7]};
CF
CF
CF
CF
CF
CF
CF
CF
=
=
=
=
=
=
=
=
r[7]
A[7]
B[7]
C[7]
D[7]
E[7]
H[7]
L[7]
I/O
SP
S
D
Description
Rotates to the left the data in r (any of the register A, B, C, D, E, H, or L). Each bit in the register moves to
the next highest-order bit position (bit 0 moves to bit 1, etc.) while bit 7 moves to both bit 0 and the C flag.
See Figure 3 on page 119.
120
Rabbit 2000/3000 Microprocessor
RLCA
Opcode
07
Instruction
RLCA
Clocks
Operation
2
A = {A[6,0],A[7]}; CF = A[7]
Flags
ALTD
S
Z
L/V
C
F
R
-
-
-
•
•
•
I/O
SP
S
D
Description
Rotates to the left the data in A. Each bit in the register moves to the next highest-order bit position (bit 0
moves to bit 1, etc.) while bit 7 moves to both bit 0 and the C flag. See Figure 3 on page 119.
Instruction Reference Manual
121
RR (HL)
RR (IX+d)
RR (IY+d)
Opcode
Instruction
Clocks
Operation
CB 1E
RR (HL)
10 (2,2,1,2,3)
{(HL),CF} = {CF,(HL)}
DD CB d 1E
RR (IX+d)
13 (2,2,2,2,2,3)
{(IX+d),CF} = {CF,(IX+d)}
FD CB d 1E
RR (IY+d)
13 (2,2,2,2,2,3)
{(IY+d),CF} = {CF,(IY+d)}
Flags
ALTD
S
Z
L/V
C
F
•
•
L
•
•
R
I/O
SP
S
D
•
•
Description
Rotates to the right with the C flag the data whose address is:
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d.
Bit 0 moves to the C flag, bits 1 through 7 move to the next lowest-order bit position, and the C flag moves to
bit 7. See figure below.
7
0
CF
Figure 4: The bit logic for the RR instruction.
122
Rabbit 2000/3000 Microprocessor
RR DE
RR HL
Opcode
Instruction
Clocks
Operation
FB
RR DE
2
{DE,CF} = {CF,DE}
FC
RR HL
2
{HL,CF} = {CF,HL}
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
I/O
SP
S
D
Description
Rotates to the right with the C flag the data in DE or HL. Bit 0 moves to the C flag, bits 1 through 15 move to
the next lowest-order bit position, and the C flag moves to bit 15 (see figure below).
15
0
CF
Figure 5: The bit logic for the RR instruction.
Instruction Reference Manual
123
RR IX
RR IY
Opcode
Instruction
Clocks
Operation
DD FC
RR IX
4 (2,2)
{IX,CF} = {CF,IX}
FD FC
RR IY
4 (2,2)
{IY,CF} = {CF,IY}
Flags
ALTD
S
Z
L/V
C
F
•
•
L
•
•
R
I/O
SP
S
D
Description
Rotates to the right with the C flag the data in IX or IY. Bit 0 moves to the C flag, bits 1 through 15 move to
the next lowest-order bit position, and the C flag moves to bit 15. See Figure 5 on page 123.
124
Rabbit 2000/3000 Microprocessor
RR r
Opcode
——
CB
CB
CB
CB
CB
CB
CB
1F
18
19
1A
1B
1C
1D
Instruction
RR
RR
RR
RR
RR
RR
RR
RR
r
A
B
C
D
E
H
L
Clocks
4
4
4
4
4
4
4
4
Operation
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
Flags
{r,CF}
{A,CF}
{B,CF}
{C,CF}
{D,CF}
{E,CF}
{H,CF}
{L,CF}
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
=
=
=
=
=
=
=
=
{CF,r}
{CF,A}
{CF,B}
{CF,C}
{CF,D}
{CF,E}
{CF,H}
{CF,L}
I/O
SP
S
D
Description
Rotates to the right with the C flag the data in register r (any of the registers A, B, C, D, E, H, or L). Bit 0
moves to the C flag, bits 1 through 7 move to the next lowest-order bit position, and the C flag moves to bit 7.
See Figure 4 on page 122.
Instruction Reference Manual
125
RRA
Opcode
1F
Instruction
RRA
Clocks
Operation
2
{A,CF} = {CF,A}
Flags
ALTD
S
Z
L/V
C
F
R
-
-
-
•
•
•
I/O
SP
S
D
Description
Rotates to the right with the C flag the data in A. Bit 0 moves to the C flag, bits 1 through 7 move to the next
lowest-order bit position, and the C flag moves to bit 7. See Figure 4 on page 122.
126
Rabbit 2000/3000 Microprocessor
RRC (HL)
RRC (IX+d)
RRC (IY+d)
Opcode
Instruction
Clocks
Operation
CB 0E
RRC (HL)
10 (2,2,1,2,3)
(HL) = {(HL)[0],(HL)[7,1]};
CF = (HL)[0]
DD CB d 0E
RRC (IX+d)
13 (2,2,2,2,2,3)
(IX + d) = {(IX + d)[0],
(IX + d)[7,1]};
CF = (IX + d)[0]
FD CB d 0E
RRC (IY+d)
13 (2,2,2,2,2,3)
(IY + d) = {(IY + d)[0],
(IY + d)[7,1]};
CF = (IY + d)[0]
Flags
ALTD
S
Z
L/V
C
F
•
•
L
•
•
R
I/O
SP
S
D
•
•
Description
Rotates to the right the data whose address is:
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d.
Each bit in the register moves to the next lowest-order bit position (bit 7 moves to bit 6, etc.) while bit 0
moves to both bit 7 and the C flag. See figure below.
7
0
CF
Figure 6: The bit logic of the RRC instruction.
Instruction Reference Manual
127
RRC r
Opcode
——
CB
CB
CB
CB
CB
CB
CB
0F
08
09
0A
0B
0C
0D
Instruction
RRC
RRC
RRC
RRC
RRC
RRC
RRC
RRC
Clocks
r
A
B
C
D
E
H
L
4
4
4
4
4
4
4
4
Operation
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
r
A
B
C
D
E
H
L
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
=
=
=
=
=
=
=
=
{r[0],r[7,1]};
{A[0],A[7,1]};
{B[0],B[7,1]};
{C[0],C[7,1]};
{D[0],D[7,1]};
{E[0],E[7,1]};
{H[0],H[7,1]};
{L[0],L[7,1]};
CF
CF
CF
CF
CF
CF
CF
CF
=
=
=
=
=
=
=
=
r[0]
A[0]
B[0]
C[0]
D[0]
E[0]
H[0]
L[0]
I/O
SP
S
D
Description
Rotates to the right the data in r (any of the registers A, B, C, D, E, H, or L). Each bit in the register moves to
the next lowest-order bit position (bit 7 moves to bit 6, etc.) while bit 0 moves to both bit 7 and the C flag. See
Figure 6 on page 127.
128
Rabbit 2000/3000 Microprocessor
RRCA
Opcode
0F
Instruction
RRCA
Clocks
Operation
2
A = {A[0],A[7,1]}; CF = A[0]
Flags
ALTD
S
Z
L/V
C
F
R
-
-
-
•
•
•
I/O
SP
S
D
Description
Rotates to the right the data in A. Each bit in the register moves to the next lowest-order bit position (bit 7
moves to bit 6, etc.) while bit 0 moves to both bit 7 and the C flag. See Figure 6 on page 127.
Instruction Reference Manual
129
RST v
Opcode
Instruction
——
RST v
8 (2,2,2,2)
D7
DF
E7
EF
FF
RST
RST
RST
RST
RST
8
8
8
8
8
10
18
20
28
38
Clocks
(2,2,2,2)
(2,2,2,2)
(2,2,2,2)
(2,2,2,2)
(2,2,2,2)
Operation
(SP - 1) = PC(high); (SP - 2) = PC(low);
SP = SP - 2; PC = Restart Address
{IIR, 0x20}
{IIR, 0x30}
{IIR, 0x40}
{IIR, 0x50}
{IIR, 0x70}
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
Pushes the current Program Counter, PC, onto the stack and then resets the PC to the interrupt vector address
represented by IIR:v, where IIR is the address of the interrupt table and v is the offset into the table. The
address of the vector table can be read and set by the instructions LD A,IIR and LD IIR,A respectively, where
A is the upper nibble of the 16 bit vector table address. The vector table is always on a 100h boundary.
The push is accomplished by first loading the high-order byte of the PC into the memory location with the
address 1 less than the number in the Stack Pointer, SP. Then the low-order byte of the PC is loaded into the
memory location with the address two less than the number in SP. The value in SP is then decremented twice.
The PC is reset by loading it with the address to reset to v (any of the addresses 0020, 0030, 0040, 0050, or
0070).
130
Rabbit 2000/3000 Microprocessor
SBC A,(HL)
SBC (IX+d)
SBC (IY+d)
Opcode
Instruction
Clocks
Operation
9E
SBC A,(HL)
5 (2,1,2)
A = A - (HL) - CF
DD 9E d
SBC (IX+d)
9 (2,2,2,1,2)
A = A - (IX + d) - CF
FD 9E d
SBC (IY+d)
9 (2,2,2,1,2)
A = A - (IY + d) - CF
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
•
Description
Subtracts the C flag and the data whose address is:
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d
from the data in A. The result is stored in A.
These operations output an inverted carry:
•
The C flag is set if A is less than the data being subtracted from it.
•
The C flag is cleared if A is greater than the data being subtracted from it.
•
The C flag is unchaged if A is equal to the data being subracted from it.
Instruction Reference Manual
131
SBC A,n
SBC A,r
Opcode
Instruction
Clocks
Operation
DE n
SBC A,n
4 (2,2)
A = A - n - CF
——
9F
98
99
9A
9B
9C
9D
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
2
2
2
2
2
2
2
2
A
A
A
A
A
A
A
A
A,r
A,A
A,B
A,C
A,D
A,E
A,H
A,L
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
=
=
=
=
=
=
=
=
A
A
A
A
A
A
A
A
-
r
A
B
C
D
E
H
L
-
CF
CF
CF
CF
CF
CF
CF
CF
I/O
SP
S
D
Description
•
SBC A,n: Subtracts the C flag and the 8-bit constant n from the data in A.
•
SBC A,r: Subtracts the C flag and the data in r (any of the registers A, B, C, D, E, H, or L)
from the data in A.
The difference is stored in A.
These operations output an inverted carry:
132
•
The C flag is set if A is less than the data being subtracted from it.
•
The C flag is cleared if A is greater than the data being subtracted from it.
•
The C flag is unchaged if A is equal to the data being subracted from it.
Rabbit 2000/3000 Microprocessor
SBC HL,ss
Opcode
——
ED
ED
ED
ED
42
52
62
72
Instruction
SBC
SBC
SBC
SBC
SBC
HL,ss
HL,BC
HL,DE
HL,HL
HL,SP
Clocks
4
4
4
4
4
Operation
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
Flags
HL
HL
HL
HL
HL
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
=
=
=
=
=
HL
HL
HL
HL
HL
-
ss
BC
DE
HL
SP
-
CF
CF
CF
CF
CF
I/O
SP
S
D
Description
Subtracts the C flag and the data in ss (any of BC, DE, HL, or SP) from the data in HL. The difference is
stored in HL.
These operations output an inverted carry:
•
The C flag is set if A is less than the data being subtracted from it.
•
The C flag is cleared if A is greater than the data being subtracted from it.
•
The C flag is unchaged if A is equal to the data being subracted from it.
Instruction Reference Manual
133
SCF
Opcode
37
Instruction
SCF
Clocks
Operation
2
CF = 1
Flags
ALTD
S
Z
L/V
C
F
-
-
-
1
•
R
I/O
SP
S
D
Description
Sets the C flag.
134
Rabbit 2000/3000 Microprocessor
SET b,(HL)
SET b,(IX+d)
SET b,(IY+d)
Opcode
CB
CB
CB
CB
CB
CB
CB
CB
C6
CE
D6
DE
E6
EE
F6
FE
DD
DD
DD
DD
DD
DD
DD
DD
CB
CB
CB
CB
CB
CB
CB
CB
d
d
d
d
d
d
d
d
FD
FD
FD
FD
FD
FD
FD
FD
CB
CB
CB
CB
CB
CB
CB
CB
d
d
d
d
d
d
d
d
Instruction
Clocks
Operation
SET
SET
SET
SET
SET
SET
SET
SET
SET
b,(HL)
bit 0,(HL)
bit 1,(HL)
bit 2,(HL)
bit 3,(HL)
bit 4,(HL)
bit 5,(HL)
bit 6,(HL)
bit 7,(HL)
10*
10*
10*
10*
10*
10*
10*
10*
10*
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
=
=
=
=
=
=
=
=
=
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
(HL)
C6
CE
D6
DE
E6
EE
F6
FE
SET
SET
SET
SET
SET
SET
SET
SET
SET
b,(IX+d)
bit 0,(IX+d)
bit 1,(IX+d)
bit 2,(IX+d)
bit 3,(IX+d)
bit 4,(IX+d)
bit 5,(IX+d)
bit 6,(IX+d)
bit 7,(IX+d)
13**
13**
13**
13**
13**
13**
13**
13**
13**
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
+
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
d)
C6
CE
D6
DE
E6
EE
F6
FE
SET
SET
SET
SET
SET
SET
SET
SET
SET
b,(IY+d)
bit 0,(IY+d)
bit 1,(IY+d)
bit 2,(IY+d)
bit 3,(IY+d)
bit 4,(IY+d)
bit 5,(IY+d)
bit 6,(IY+d)
bit 7,(IY+d)
13**
13**
13**
13**
13**
13**
13**
13**
13**
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
+
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
d)
|
|
|
|
|
|
|
|
|
bit
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
=
=
=
=
=
=
=
=
=
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
(IX
+
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
d)
|
|
|
|
|
|
|
|
|
bit
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
=
=
=
=
=
=
=
=
=
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
(IY
+
+
+
+
+
+
+
+
+
d)
d)
d)
d)
d)
d)
d)
d)
d)
|
|
|
|
|
|
|
|
|
bit
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
Clocking: *10 (2,2,1,2,3) **13 (2,2,2,2,2,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
•
•
Description
Sets bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the byte whose address is
•
•
•
the data in HL, or
the sum of the data in IX and a displacement d, or
the sum of the data in IY and a displacement d.
Instruction Reference Manual
135
SET b,r
Opcode
Instruction
SET b,r
b,r
A
B
C
D
E
H
L
CB (0)
C7
C0
C1
C2
C3
C4
C5
CB (1)
CF
C8
C9
CA
CB
CC
CD
CB (2)
D7
D0
D1
D2
D3
D4
D5
CB (3)
DF
D8
D9
DA
DB
DC
DD
CB (4)
E7
E0
E1
E2
E3
E4
E5
CB (5)
EF
E8
E9
EA
EB
EC
ED
CB (6)
F7
F0
F1
F2
F3
F4
F5
CB (7)
FF
F8
F9
FA
FB
FC
FD
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
Clocks
4 (2,2)
Operation
r = r | bit
I/O
SP
S
D
•
Description
Sets bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the data in r (any of the registers A, B, C, D, E, H, or L).
136
Rabbit 2000/3000 Microprocessor
Rabbit 3000A Instruction
SETUSR
Opcode
ED 6F
Instruction
SETUSR
Clocks
Operation
4 (2,2)
Flags
SU={SU[5:0],0x01}
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
The System/User Mode Register, SU, is an 8 bit register that forms a stack of the current processor mode and
the previous 3 modes. SETUSR shifts the contents of SU 2 bits to the left, then sets bit 1 to 0 and bit 0 to 1,
signifying user mode.
This instruction is privileged and only implemented for the Rabbit 3000A.
Instruction Reference Manual
137
SLA (HL)
SLA (IX+d)
SLA (IY+d)
Opcode
Instruction
Clocks
Operation
CB 26
SLA (HL)
10*
(HL) = {(HL)[6,0],0}; CF = (HL)[7]
DD CB d 26
SLA (IX+d)
13**
(IX + d) = {(IX + d)[6,0],0};
CF = (IX + d)[7]
FD CB d 26
SLA (IY+d)
13**
(IY + d) = {(IY + d)[6,0],0};
CF = (IY + d)[7]
Clocking: *10 (2,2,1,2,3) **13 (2,2,2,2,2,3)
Flags
ALTD
S
Z
L/V
C
F
•
•
L
•
•
R
I/O
SP
S
D
•
•
Description
Arithmetically shifts to the left the bits of the data whose address is
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d.
Bits 0 through 6 are each shifted to the next highest-order bit position (bit 0 moves to bit 1, etc.). Bit 7 is
shifted to the C flag. Bit 0 is reset. See figure below.
CF
7
0
‘0’
Figure 7: The bit logic of the SLA instruction.
138
Rabbit 2000/3000 Microprocessor
SLA r
Opcode
——
CB
CB
CB
CB
CB
CB
CB
27
20
21
22
23
24
25
Instruction
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
r
A
B
C
D
E
H
L
Clocks
4
4
4
4
4
4
4
4
Operation
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
Flags
r
A
B
C
D
E
H
L
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
=
=
=
=
=
=
=
=
{r[6,0],0};
{A[6,0],0};
{B[6,0],0};
{C[6,0],0};
{D[6,0],0};
{E[6,0],0};
{H[6,0],0};
{L[6,0],0};
CF
CF
CF
CF
CF
CF
CF
CF
=
=
=
=
=
=
=
=
r[7]
A[7]
B[7]
C[7]
D[7]
E[7]
H[7]
L[7]
I/O
SP
S
D
Description
Arithmetically shifts to the left the bits of the data in register r (any of A, B, C, D, E, H, or L). Bits 0 through
6 are each shifted to the next highest-order bit position (bit 0 moves to bit 1, etc.). Bit 7 is shifted to the C flag.
Bit 0 is reset. See Figure 7 on page 138.
Instruction Reference Manual
139
SRA (HL)
SRA (IX+d)
SRA (IY+d)
Opcode
Instruction
Clocks
Operation
CB 2E
SRA (HL)
10*
(HL) = {(HL)[7],(HL)[7,1]};
CF = (HL)[0]
DD CB d 2E
SRA (IX+d)
13**
(IX + d) = {(IX + d)[7],(IX + d)[7,1]};
CF = (IX + d)[0]
FD CB d 2E
SRA (IY+d)
13**
(IY +d) = {(IY + d)[7],(IY + d)[7,1]};
CF = (IY + d)[0]
Clocking: *10 (2,2,1,2,3) **13 (2,2,2,2,2,3)
Flags
ALTD
S
Z
L/V
C
F
•
•
L
•
•
R
I/O
SP
S
D
•
•
Description
Arithmetically shifts to the right the bits in the data whose address is
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d.
Bits 7 through 1 are shifted to the next lowest-order bit position (bit 7 is shifted to bit 6, etc.). Bit 7 is also copied to itself. Bit 0 is shifted to the C flag. See figure below.
7
0
CF
Figure 8: The bit logic of the SRA instruction.
140
Rabbit 2000/3000 Microprocessor
SRA r
Opcode
——
CB
CB
CB
CB
CB
CB
CB
2F
28
29
2A
2B
2C
2D
Instruction
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
Clocks
r
A
B
C
D
E
H
L
4
4
4
4
4
4
4
4
Operation
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
Flags
r
A
B
C
D
E
H
L
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
=
=
=
=
=
=
=
=
{r[7],r[7,1]};
{A[7],A[7,1]};
{B[7],B[7,1]};
{C[7],C[7,1]};
{D[7],D[7,1]};
{E[7],E[7,1]};
{H[7],H[7,1]};
{L[7],L[7,1]};
CF
CF
CF
CF
CF
CF
CF
CF
=
=
=
=
=
=
=
=
r[0]
A[0]
B[0]
C[0]
D[0]
E[0]
H[0]
L[0]
I/O
SP
S
D
Description
Arithmetically shifts to the right the bits in r (any of the registers A, B, C, D, E, H, or L). Bits 7 through 1 are
shifted to the next lowest-order bit position (bit 7 is shifted to bit 6, etc.). Bit 7 is also copied to itself. Bit 0 is
shifted to the C flag. See Figure 8 on page 140.
Instruction Reference Manual
141
SRL (HL)
SRL (IX+d)
SRL (IY+d)
Opcode
Instruction
Clocks
Operation
CB 3E
SRL (HL)
10*
(HL) = {0,(HL)[7,1]}; CF = (HL)[0]
DD CB d 3E
SRL (IX+d)
13**
(IX + d) = {0,(IX + d)[7,1]};
CF = (IX + d)[0]
FD CB d 3E
SRL (IY+d)
13**
(IY + d) = {0,(IY + d)[7,1]};
CF = (IY + d)[0]
Clocking: *10 (2,2,1,2,3) **13 (2,2,2,2,2,3)
Flags
ALTD
S
Z
L/V
C
F
•
•
L
•
•
R
I/O
SP
S
D
•
•
Description
Logically shifts to the right the bits of the data whose address is
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d.
Each bit is shifted to the next lowest-order bit position (Bit 7 shifts to bit 6, etc.) Bit 0 shift to the C flag. Bit 7
is reset. See figure below.
‘0’
7
0
CF
Figure 9: The bit logic of the SRL instruction.
142
Rabbit 2000/3000 Microprocessor
SRL r
Opcode
——
CB
CB
CB
CB
CB
CB
CB
3F
38
39
3A
3B
3C
3D
Instruction
SRL
SRL
SRL
SRL
SRL
SRL
SRL
SRL
r
A
B
C
D
E
H
L
Clocks
4
4
4
4
4
4
4
4
Operation
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
(2,2)
Flags
r
A
B
C
D
E
H
L
ALTD
S
Z
L/V
C
F
R
•
•
L
•
•
•
=
=
=
=
=
=
=
=
{0,r[7,1]};
{0,A[7,1]};
{0,B[7,1]};
{0,C[7,1]};
{0,D[7,1]};
{0,E[7,1]};
{0,H[7,1]};
{0,L[7,1]};
CF
CF
CF
CF
CF
CF
CF
CF
=
=
=
=
=
=
=
=
r[0]
A[0]
B[0]
C[0]
D[0]
E[0]
H[0]
L[0]
I/O
SP
S
D
Description
Logically shifts to the right the bits in r (any of the registers A, B, C, D, E, H, or L). Each bit is shifted to the
next lowest-order bit position (Bit 7 shifts to bit 6, etc.) Bit 0 shift to the C flag. Bit 7 is reset. See Figure 9 on
page 142.
Instruction Reference Manual
143
SUB (HL)
SUB (IX+d)
SUB (IY+d)
Opcode
Instruction
Clocks
Operation
96
SUB (HL)
5 (2,1,2)
A = A - (HL)
DD 96 d
SUB (IX+d)
9 (2,2,2,1,2)
A = A - (IX + d)
FD 96 d
SUB (IY+d)
9 (2,2,2,1,2)
A = A - (IY + d)
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
•
Description
Subtracts from the data in A the data whose address is
•
•
•
the data in HL, or
the sum of the data in IX and a displacement d, or
the sum of the data in IY and a displacement d.
The result is stored in A.
144
Rabbit 2000/3000 Microprocessor
SUB n
Opcode
D6 n
Instruction
SUB n
Clocks
Operation
4 (2,2)
Flags
A = A - n
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
I/O
SP
S
D
Description
Subtracts from the data in A the 8-bit constant n. The result is stored in A.
Instruction Reference Manual
145
SUB r
Opcode
——
97
90
91
92
93
94
95
Instruction
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
r
A
B
C
D
E
H
L
Clocks
Operation
2
2
2
2
2
2
2
2
A
A
A
A
A
A
A
A
Flags
ALTD
S
Z
L/V
C
F
R
•
•
V
•
•
•
=
=
=
=
=
=
=
=
A
A
A
A
A
A
A
A
-
r
A
B
C
D
E
H
L
I/O
SP
S
D
Description
Subtracts from the data in A the data in r (any of the registers A, B, C, D, E, H, or L). The result is stored in A.
146
Rabbit 2000/3000 Microprocessor
Rabbit 3000A Instruction
SURES
Opcode
ED 7D
Instruction
SURES
Clocks
Operation
4 (2,2)
Flags
SU = {SU[1:0],SU[7:2]}
ALTD
S
Z
L/V
C
-
-
-
-
F
R
I/O
SP
S
D
Description
The SURES instruction rotates the contents of the System/User Mode Register SU 2 bits to the right, replacing the current processor mode with the previous mode.
This instruction is privileged and only implemented for the Rabbit 3000A.
Instruction Reference Manual
147
Rabbit 3000A Instruction
SYSCALL
Opcode
ED 75
Instruction
SYSCALL
Clocks
Operation
10 (2,2,3,3)
Flags
ALTD
S
Z
L/V
C
-
-
-
-
F
R
SP = SP-2; PC = {R,v}
where v = SYSCALL offset
I/O
SP
S
D
Description
Pushes the current PC onto the stack and then resets the PC to the interrupt vector address represented by
IIR:0x60, where IIR is the address of the interrupt table and 0x60 is the offset into the table. The address of
the vector table can be read and set by the instructions LD A,IIR and LD IIR,A respectively, where A is
the upper nibble of the 16 bit vector table address. The vector table is always on a 100h boundary.
The push is accomplished by first loading the high-order byte of the PC into the memory location with the
address 1 less than the number in SP. Then the low-order byte of the PC is loaded into the memory location
with the address two less than the number in SP. The value in SP is then decremented twice.
This instruction is implemented in the Rabbit 3000A.
148
Rabbit 2000/3000 Microprocessor
Rabbit 3000A Instruction
UMA
UMS
Opcode
Instruction
Clocks
Operation
ED C0
UMA
8+8i (2,2,2,
(2,2,3,1)i,2)
[CY:DE’:(HL)} =
(IX) + [(IY)*DE+DE’+CY];
BC = BC - 1; IX = IX + 1;
IY = IY + 1; HL = HL + 1;
repeat while BC != 0
ED C8
UMS
8+8i (2,2,2,
(2,2,3,1)i,2)
[CY:DE’:(HL)} =
(IX) - [(IY)*DE+DE’+CY];
BC = BC - 1; IX = IX + 1;
IY = IY + 1; HL = HL + 1;
repeat while BC != 0
Flags
ALTD
S
Z
L/V
C
-
-
-
•
F
R
I/O
SP
S
D
Description
While the data in the BC does not equal 0, then:
•
the data at the address in IY is multiplied by the data in DE;
•
the data in alternate register DE’ is added to that value;
•
the C flag is added to that value; and
•
this value is added to the data at the address in IX (for UMA) or
this value is subtracted from the data at the address in IX (for UMS).
This results in a 24-bit value. The lowest eight bits of this value are stored memory at the address in HL, and
the upper 16 bits are stored in the alternate register DE’. If The data in IX, IY, and HL are then incremented,
and the data in BC is decremented. The instruction then repeats until BC equals zero. Interrupts can occur
between different repeats, but not within an iteration.
These instructions are implemented in the Rabbit 3000A.
Instruction Reference Manual
149
XOR (HL)
XOR (IX+d)
XOR (IY+d)
Opcode
Instruction
Clocks
Operation
AE
XOR (HL)
5 (2,1,2)
A = [A & ~(HL)] | [~A & (HL)]
DD AE d
XOR (IX+d)
9 (2,2,2,1,2)
A = [A & ~(IX + d)] |
[~A & (IX + d)]
FD AE d
XOR (IY+d)
9 (2,2,2,1,2)
A = [A & ~(IY + d)] |
[~A & (IY + d)]
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
I/O
SP
S
D
•
Description
Performs an exclusive OR operation between the data in A and the data whose address is:
•
the data in HL, or
•
the sum of the data in IX and a displacement d, or
•
the sum of the data in IY and a displacement d.
The corresponding bits of each byte are compared (i.e., bit 0 of both bytes are compared, bit 1 of both bytes
are compared, etc.). The associated bit in the result byte is set if and only if one of the two compared bits is
set. The result is stored in A.
Example
If HL contains 0x4000 and the memory location 0x4000 contains the byte 1001 0101 and A contains the byte
0101 0011 then the execution of the instruction
XOR (HL)
would result in the byte in A becoming 1100 0110.
150
Rabbit 2000/3000 Microprocessor
XOR n
Opcode
EE n
Instruction
XOR n
Clocks
Operation
4 (2,2)
Flags
A = [A & ~n] | [~A & n]
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
I/O
SP
S
D
Description
Performs an exclusive OR operation between the byte in A and the 8-bit constant n. The corresponding bits of
each byte are compared (i.e., bit 0 of both bytes are compared, the bit 1 of both bytes are compared, etc.). The
associated bit in the result byte is set if and only if one of the two compared bits is set. The result is stored in
A.
Instruction Reference Manual
151
XOR r
Opcode
——
AF
A8
A9
AA
AB
AC
AD
Instruction
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
r
A
B
C
D
E
H
L
Clocks
Operation
2
2
2
2
2
2
2
2
A
A
A
A
A
A
A
A
Flags
ALTD
S
Z
L/V
C
F
R
•
•
L
0
•
•
=
=
=
=
=
=
=
=
[A
[A
[A
[A
[A
[A
[A
[A
&
&
&
&
&
&
&
&
~r]
~A]
~B]
~C]
~D]
~E]
~H]
~L]
|
|
|
|
|
|
|
|
[~A
[~A
[~A
[~A
[~A
[~A
[~A
[~A
&
&
&
&
&
&
&
&
r]
A]
B]
C]
D]
E]
H]
L]
I/O
SP
S
D
Description
Performs an exclusive OR operation between the byte in A and r (any of the registers A, B, C, D, E, H, or L).
The corresponding bits of each byte are compared (i.e., bit 0 of both bytes are compared, bit 1 of both bytes
are compared, etc.). The associated bit in the result byte is set if and only if one of the two compared bits is
set. The result is stored in A.
152
Rabbit 2000/3000 Microprocessor
6. Opcode Map
Table 1: Main Page
LSB
SB\
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
NOP
LD
BC,mn
LD
(BC),A
INC
BC
INC
B
DEC
B
LD
B,n
RLCA
EX
AF,AF'
ADD
HL,BC
LD
A,(BC)
DEC
BC
INC
C
DEC
C
LD
C,n
RRCA
1
DJNZ
e
LD
DE,mn
LD
(DE),A
INC
DE
INC
D
DEC
D
LD
D,n
RLA
JR
e
ADD
HL,DE
LD
A,(DE)
DEC
DE
INC
E
DEC
E
LD
E,n
RRA
2
JR
NZ,e
LD
HL,mn
LD
(mn),HL
INC
HL
INC
H
DEC
H
LD
H,n
ADD
SP,d
JR
Z,e
ADD
HL,HL
LD
HL,(mn)
DEC
HL
INC
L
DEC
L
LD
L,n
CPL
3
JR
NC,e
LD
SP,mn
LD
(mn),A
INC
SP
INC
(HL)
DEC
(HL)
LD
(HL),n
SCF
JR
C,e
ADD
HL,SP
LD
A,(mn)
DEC
SP
INC
A
DEC
A
LD
A,n
CCF
4
LD
B,B
LD
B,C
LD
B,D
LD
B,E
LD
B,H
LD
B,L
LD
B,(HL)
LD
B,A
LD
C,B
LD
C,C
LD
C,D
LD
C,E
LD
C,H
LD
C,L
LD
C,(HL)
LD
C,A
5
LD
D,B
LD
D,C
LD
D,D
LD
D,E
LD
D,H
LD
D,L
LD
D,(HL)
LD
D,A
LD
E,B
LD
E,C
LD
E,D
LD E,E
(IDET)
LD
E,H
LD
E,L
LD
E,(HL)
LD
E,A
6
LD
H,B
LD
H,C
LD
H,D
LD
H,E
LD
H,H
LD
H,L
LD
H,(HL)
LD
H,A
LD
L,B
LD
L,C
LD
L,D
LD
L,E
LD
L,H
LD
L,L
LD
L,(HL)
LD
L,A
LD
(HL),D
LD
(HL),E
LD
(HL),H
LD
(HL),L
ALTD
LD
(HL),A
LD
A,B
LD
A,C
LD
A,D
LD
A,E
LD
A,H
LD
A,L
LD
A,(HL)
LD
A,A
7
LD
LD
(HL),B (HL),C
8
ADD
A,B
ADD
A,C
ADD
A,D
ADD
A,E
ADD
A,H
ADD
A,L
ADD
A,(HL)
ADD
A,A
ADC
A,B
ADC
A,C
ADC
A,D
ADC
A,E
ADC
A,H
ADC
A,L
ADC
A,(HL)
ADC
A,A
9
SUB
B
SUB
C
SUB
D
SUB
E
SUB
H
SUB
L
SUB
(HL)
SUB
A
SBC
A,B
SBC
A,C
SBC
A,D
SBC
A,E
SBC
A,H
SBC
A,L
SBC
A,(HL)
SBC
A,A
A
AND
B
AND
C
AND
D
AND
E
AND
H
AND
L
AND
(HL)
AND
A
XOR
B
XOR
C
XOR
D
XOR
E
XOR
H
XOR
L
XOR
(HL)
XOR
A
B
OR
B
OR
C
OR
D
OR
E
OR
H
OR
L
OR
(HL)
OR
A
CP
B
CP
C
CP
D
CP
E
CP
H
CP
L
CP
(HL)
CP
A
C
RET
NZ
POP
BC
JP
NZ,mn
JP
mn
LD HL,
(SP+n)
PUSH
BC
ADD
A,n
LJP
x,mn
RET
Z
RET
JP
Z,mn
esc
BOOL
HL
CALL
nn
ADC
A,n
LCALL
x,mn
RET
NC
POP
DE
JP
NC,mn
IOI
LD
(SP+n),
HL
PUSH
DE
SUB
n
RST
10
RET
C
EXX
JP
C,mn
IOE
AND
HL,DE
esc
D
SBC
A,n
RST
18
E
RET
PO
POP
HL
JP
PO,mn
EX
DE',HL
LD HL,
(IX+d)
PUSH
HL
AND
n
RST
20
RET
PE
JP
(HL)
JP
PE,mn
EX
DE,HL
OR
HL,DE
esc
XOR
n
RST
28
RET
P
POP
AF
JP
P,mn
RL
DE
LD
(IX+d),
HL
PUSH
AF
OR
n
MUL
RET
M
LD
SP,HL
JP
M,mn
RR
DE
RR
HL
esc
F
CP
n
RST
38
Instruction Reference Manual
153
Table 2: ED Page
\LSB
MSB\
0
1
2
3
4
5
6
7
4
LD
BC',DE
SBC
HL,BC
LD
(mn),BC
NEG
LRET
IPSET
0
5
LD
DE',DE
SBC
HL,DE
LD
EX
(mn),DE (SP),HL
IPSET
1
6
LD
HL',DE
SBC
HL,HL
SBC
HL,SP
8
9
A
B
LD
I,A
LD
BC',BC
ADC
HL,BC
LD
A,I
LD
DE',BC
LD
LDP
LDP
PUSH SU
(mn),HL (HL),HL (mn),HL
LD
XPC,A
LD
HL',BC
LD
(mn),SP
LD
A,XPC
C
D
E
F
LD
BC,(mn)
RETI
IPSET
2
LD
R,A
ADC
HL,DE
LD
DE,(mn)
IPRES
IPSET
3
LD
A,R
ADC
HL,HL
LD
LDP
LDP
POP SU SETUSR
HL,(mn) HL,(HL) HL,(mn)
ADC
HL,SP
LD
SP,(mn)
0
1
2
3
7
SYSCALL PUSH IP
SURES
POP
IP
RDMODE
8
9
LDISR
A
LDI
LDD
B
LDIR
LDDR
LDDSR
C
UMA
UMS
D
LSIDR
LSDDR
LSIR
LSDR
E
F
154
Instruction Reference Manual
Table 3: DD Page
\LSB
MSB\
0
1
2
3
4
5
6
7
8
9
0
ADD
IX,BC
1
ADD
IX,DE
2
LD
IX,mn
LD
(mn),IX
INC
IX
ADD
IX,IX
INC
(IX+d)
3
DEC
LD
(IX+d) (IX+d),n
A
B
LD
IX,(mn)
DEC
IX
C
D
E
F
ADD
IX,SP
4
LD
B,(IX+d)
LD
C,(IX+d)
5
LD
D,(IX+d)
LD
E,(IX+d)
6
LDP
LDP
LD
(IX),HL (mn),IX H,(IX+d)
LDP
LDP
LD
HL,(IX) IX,(mn) L,(IX+d)
7
LD
LD
LD
LD
LD
LD
(IX+d), (IX+d), (IX+d), (IX+d), (IX+d), (IX+d),
B
C
D
E
H
L
LD
(IX+d),
A
LD
HL,IX
LD
IX,HL
LD
A,(IX+d)
8
ADD
A,(IX+d)
ADC
A,(IX+d)
9
SUB
(IX+d)
SBC
A,(IX+d)
A
AND
(IX+d)
XOR
(IX+d)
B
OR
(IX+d)
CP
(IX+d)
C
LD IX,
(SP+n)
D
LD
(SP+n),
IX
E
POP
IX
EX
LD HL,
(SP),IX (HL+d)
F
Instruction Reference Manual
LD
(HL+d),
HL
esc
BOOL
IX
AND
IX,DE
PUSH
IX
JP
(IX)
OR
IX,DE
LD
SP,IX
RR
IX
155
Table 4: FD Page
\LSB
MSB\
0
1
2
3
4
5
6
7
8
9
0
ADD
IY,BC
1
ADD
IY,DE
2
LD
IY,mn
LD
(mn),IY
INC
IY
ADD
IY,IY
INC
(IY+d)
3
DEC
(IY+d)
LD
(IY+d),n
A
B
LD
IY,(mn)
DEC
IY
C
D
E
ADD
IX,SP
4
LD
B,(IY+d)
LD
C,(IY+d)
5
LD
D,(IY+d)
LD
E,(IY+d)
6
LDP
LDP
LD
(IY),HL (mn),IY H,(IY+d)
7
LD
LD
LD
LD
LD
LD
(IY+d), (IY+d), (IY+d), (IY+d), (IY+d), (IY+d),
B
C
D
E
H
L
LDP
LDP
HL,(IY) IY,(mn)
LD
(IY+d),
A
LD
HL,IY
LD
IY,HL
LD
L,(IY+d)
LD
A,(IY+d)
8
ADD
A,(IY+d)
ADC
A,(IY+d)
9
SUB
(IY+d)
SBC
A,(IY+d)
A
AND
(IY+d)
XOR (IY+d)
B
OR (IY+d)
C
LD IY,
(SP+n)
D
LD
(SP+n),
IY
E
F
156
POP
IY
EX
LD HL,
(SP),IY (IY+d)
LD
(IY+d),
HL
F
CP
esc
(IY+d)
BOOL
IY
AND
IY,DE
PUSH
IY
JP
(IY)
OR
IY,DE
LD
SP,IY
RR
IY
Instruction Reference Manual
Table 5: CB Page
SB
SB\
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
RLC
B
RLC
C
RLC
D
RLC
E
RLC
H
RLC
L
RLC
(HL)
RLC
A
RRC
B
RRC
C
RRC
D
RRC
E
RRC
H
RRC
L
RRC
(HL)
RRC
A
1
RL
B
RL
C
RL
D
RL
E
RL
H
RL
L
RL
(HL)
RL
A
RR
B
RR
C
RR
D
RR
E
RR
H
RR
L
RR
(HL)
RR
A
2
SLA
B
SLA
C
SLA
D
SLA
E
SLA
H
SLA
L
SLA
(HL)
SLA
A
SRA
B
SRA
C
SRA
D
SRA
E
SRA
H
SRA
L
SRA
(HL)
SRA
A
SRL
B
SRL
C
SRL
D
SRL
E
SRL
H
SRL
L
SRL
(HL)
SRL
A
3
4
BIT
0,B
BIT
0,C
BIT
0,D
BIT
0,E
BIT
0,H
BIT
0,L
BIT
0,(HL)
BIT
0,A
BIT
1,B
BIT
1,C
BIT
1,D
BIT
1,E
BIT
1,H
BIT
1,L
BIT
1,(HL)
BIT
1,A
5
BIT
2,B
BIT
2,C
BIT
2,D
BIT
2,E
BIT
2,H
BIT
2,L
BIT
2,(HL)
BIT
2,A
BIT
3,B
BIT
3,C
BIT
3,D
BIT
3,E
BIT
3,H
BIT
3,L
BIT
3,(HL)
BIT
3,A
6
BIT
4,B
BIT
4,C
BIT
4,D
BIT
4,E
BIT
4,H
BIT
4,L
BIT
4,(HL)
BIT
4,A
BIT
5,B
BIT
5,C
BIT
5,D
BIT
5,E
BIT
5,H
BIT
5,L
BIT
5,(HL)
BIT
5,A
7
BIT
6,B
BIT
6,C
BIT
6,D
BIT
6,E
BIT
6,H
BIT
6,L
BIT
6,(HL)
BIT
6,A
BIT
7,B
BIT
7,C
BIT
7,D
BIT
7,E
BIT
7,H
BIT
7,L
BIT
7,(HL)
BIT
7,A
8
RES
0,B
RES
0,C
RES
0,D
RES
0,E
RES
0,H
RES
0,L
RES
0,(HL)
RES
0,A
RES
1,B
RES
1,C
RES
1,D
RES
1,E
RES
1,H
RES
1,L
RES
1,(HL)
RES
1,A
9
RES
2,B
RES
2,C
RES
2,D
RES
2,E
RES
2,H
RES
2,L
RES
2,(HL)
RES
2,A
RES
3,B
RES
3,C
RES
3,D
RES
3,E
RES
3,H
RES
3,L
RES
3,(HL)
RES
3,A
A
RES
4,B
RES
4,C
RES
4,D
RES
4,E
RES
4,H
RES
4,L
RES
4,(HL)
RES
4,A
RES
5,B
RES
5,C
RES
5,D
RES
5,E
RES
5,H
RES
5,L
RES
5,(HL)
RES
5,A
B
RES
6,B
RES
6,C
RES
6,D
RES
6,E
RES
6,H
RES
6,L
RES
6,(HL)
RES
6,A
RES
7,B
RES
7,C
RES
7,D
RES
7,E
RES
7,H
RES
7,L
RES
7,(HL)
RES
7,A
C
SET
0,B
SET
0,C
SET
0,D
SET
0,E
SET
0,H
SET
0,L
SET
0,(HL)
SET
0,A
SET
1,B
SET
1,C
SET
1,D
SET
1,E
SET
1,H
SET
1,L
SET
1,(HL)
SET
1,A
D
SET
2,B
SET
2,C
SET
2,D
SET
2,E
SET
2,H
SET
2,L
SET
2,(HL)
SET
2,A
SET
3,B
SET
3,C
SET
3,D
SET
3,E
SET
3,H
SET
3,L
SET
3,(HL)
SET
3,A
E
SET
4,B
SET
4,C
SET
4,D
SET
4,E
SET
4,H
SET
4,L
SET
4,(HL)
SET
4,A
SET
5,B
SET
5,C
SET
5,D
SET
5,E
SET
5,H
SET
5,L
SET
5,(HL)
SET
5,A
F
SET
6,B
SET
6,C
SET
6,D
SET
6,E
SET
6,H
SET
6,L
SET
6,(HL)
SET
6,A
SET
7,B
SET
7,C
SET
7,D
SET
7,E
SET
7,H
SET
7,L
SET
7,(HL)
SET
7,A
Instruction Reference Manual
157
Table 6: DD-CB Page
B
B\
158
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
RLC
(IX+d)
RRC
(IX+d)
RL
(IX+d)
RR
(IX+d)
SLA
(IX+d)
SRA
(IX+d)
F
SRL
(IX+d)
BIT
0,(IX+d)
BIT
1,(IX+d)
BIT
2,(IX+d)
BIT
3,(IX+d)
BIT
4,(IX+d)
BIT
5,(IX+d)
BIT
6,(IX+d)
BIT
7,(IX+d)
RES
0,(IX+d)
RES
1,(IX+d)
RES
2,(IX+d)
RES
3,(IX+d)
RES
4,(IX+d)
RES
5,(IX+d)
RES
6,(IX+d)
RES
7,(IX+d)
SET
0,(IX+d)
SET
1,(IX+d)
SET
2,(IX+d)
SET
3,(IX+d)
SET
4,(IX+d)
SET
5,(IX+d)
SET
6,(IX+d)
SET
7,(IX+d)
Instruction Reference Manual
Table 7: FD-CB Page
B
B\
0
1
2
3
Instruction Reference Manual
4
5
6
7
8
9
A
B
C
D
E
RLC
(IY+d)
RRC
(IY+d)
RL
(IY+d)
RR
(IY+d)
SLA
(IY+d)
SRA
(IY+d)
F
SRL
(IY+d)
BIT
0,(IY+d)
BIT
1,(IY+d)
BIT
2,(IY+d)
BIT
3,(IY+d)
BIT
4,(IY+d)
BIT
5,(IY+d)
BIT
6,(IY+d)
BIT
7,(IY+d)
RES
0,(IY+d)
RES
1,(IY+d)
RES
2,(IY+d)
RES
3,(IY+d)
RES
4,(IY+d)
RES
5,(IY+d)
RES
6,(IY+d)
RES
7,(IY+d)
SET
0,(IY+d)
SET
1,(IY+d)
SET
2,(IY+d)
SET
3,(IY+d)
SET
4,(IY+d)
SET
5,(IY+d)
SET
6,(IY+d)
SET
7,(IY+d)
159
160
Instruction Reference Manual
7. Quick Reference Table
Key
•
Instruction: The mnemonic syntax of the instruction.
•
Opcode: The binary bytes that represent the instruction.
•
Clock cycles: The number of clock cycles that the instruction takes to complete. The numbers in
parenthesis are a breakdown of the total clocks. For more information, please see Table 1: "Typical
Clocks Breakdown" on page 7.
•
A: How the ALTD prefix affects the instruction. For more information, please see Table 2: "ALTD
(“A” Column) Symbol Key" on page 8.
•
I: How the IOI or IOE prefixes affect the instruction. For more information, please see Table 3: "IOI
and IOE (“I” Column) Symbol Key" on page 8. A “b” in this column indicates that the prefix applies to
both source and destination.
•
S; Z; LV; C: These columns denote how the instruction affects the flags. For more information, please
see Table 4: "Flag Register Key" on page 8.
•
Operation: A symbolic representation of the operation performed.
•
N/M/P: An “N” in this column indicates that the instruction has been added to the Z180 instruction
set by the Rabbit 2000/3000. An “M” indicates that this instruction is from the Z180, but has been
modified. A “P” indicates a privileged instruction.
Instruction
Opcode
byte 1
Opcode
byte 2
Opcode
byte 3
Opcode
byte 4
Clock cycles
A
I
S Z LV C
Operation
N/M/P
ADC A,(HL)
10001110
5 (2,1,2)
fr
s
*
*
V
*
A = A + (HL) + CF
ADC A,(IX+d)
11011101
10001110
----d---
9 (2,2,2,1,2)
fr
s
*
*
V
*
A = A + (IX+d) + CF
ADC A,(IY+d)
11111101
10001110
----d---
9 (2,2,2,1,2)
fr
s
*
*
V
*
A = A + (IY+d) + CF
ADC A,n
11001110
----n---
4 (2,2)
fr
*
*
V
*
A = A + n + CF
ADC A,r
10001-r-
2
fr
*
*
V
*
A = A + r + CF
ADC HL,ss
11101101
4 (2,2)
fr
*
*
V
*
HL = HL + ss + CF
ADD A,(HL)
10000110
5 (2,1,2)
fr
s
*
*
V
*
A = A + (HL)
ADD A,(IX+d)
11011101
10000110
----d---
9 (2,2,2,1,2)
fr
s
*
*
V
*
A = A + (IX+d)
ADD A,(IY+d)
11111101
10000110
----d---
9 (2,2,2,1,2)
fr
s
*
*
V
*
A = A + (IY+d)
ADD A,n
11000110
----n---
4 (2,2)
fr
*
*
V
*
A=A+n
ADD A,r
10000-r-
2
fr
*
*
V
*
A=A+r
ADD HL,ss
00ss1001
2
fr
-
-
-
*
HL = HL + ss
ADD IX,xx
11011101
00xx1001
4 (2,2)
f
-
-
-
*
IX = IX + xx
ADD IY,yy
11111101
00yy1001
4 (2,2)
f
-
-
-
*
IY = IY + yy
ADD SP,d
00100111
----d---
4 (2,2)
f
-
-
-
*
SP = SP + d
N
alternate register destination
for next instruction
N
ALTD
01110110
01ss1010
2
-
-
-
-
AND (HL)
10100110
5 (2,1,2)
fr
s
*
*
L
0
A = A & (HL)
AND (IX+d)
11011101
10100110
----d---
9 (2,2,2,1,2)
fr
s
*
*
L
0
A = A & (IX+d)
AND (IY+d)
11111101
10100110
----d---
9 (2,2,2,1,2)
fr
s
*
*
L
0
A = A & (IY+d)
AND HL,DE
11011100
2
fr
*
*
L
0
HL = HL & DE
Instruction Reference Manual
N
161
Instruction
Opcode
byte 1
Opcode
byte 2
AND IX,DE
11011101
AND IY,DE
AND n
Opcode
byte 3
Opcode
byte 4
Clock cycles
A
11011100
4 (2,2)
11111101
11011100
11100110
----n---
I
S Z LV C
Operation
N/M/P
f
*
*
L
0
IX = IX & DE
N
4 (2,2)
f
*
*
L
0
IY = IY & DE
N
4 (2,2)
fr
*
*
L
0
A=A&n
2
fr
*
*
L
0
A=A&r
7 (2,2,1,2)
f
s
-
*
-
-
(HL) & bit
AND r
10100-r-
BIT b,(HL)
11001011
01-b-110
BIT b,(IX+d)
11011101
11001011
----d---
01-b-110
10 (2,2,2,2,2)
f
s
-
*
-
-
(IX+d) & bit
BIT b,(IY+d)
11111101
11001011
----d---
01-b-110
10 (2,2,2,2,2)
f
s
-
*
-
-
(IY+d) & bit
BIT b,r
11001011
01-b--r-
4 (2,2)
f
-
*
-
-
r & bit
BOOL HL
11001100
2
fr
*
*
0
0
if (HL != 0) HL = 1
N
BOOL IX
11011101
11001100
4 (2,2)
f
*
*
0
0
if (IX != 0) IX = 1
N
BOOL IY
11111101
11001100
4 (2,2)
f
*
*
0
0
if (IY != 0) IY = 1
N
CALL mn
11001101
CCF
00111111
----n---
----m---
12 (2,2,2,3,3)
2
f
-
-
-
-
(SP-1) = PCH; (SP-2) = PCL;
PC = mn; SP = SP-2
-
-
-
*
CF = ~CF
CP (HL)
10111110
5 (2,1,2)
f
s
*
*
V
*
A - (HL)
CP (IX+d)
11011101
10111110
----d---
9 (2,2,2,1,2)
f
s
*
*
V
*
A - (IX+d)
CP (IY+d)
11111101
10111110
----d---
9 (2,2,2,1,2)
f
s
*
*
V
*
A - (IY+d)
CP n
11111110
----n---
4 (2,2)
f
*
*
V
*
A-n
CP r
10111-r-
2
f
*
*
V
*
A-r
CPL
00101111
2
r
-
-
-
-
A = ~A
DEC (HL)
00110101
8 (2,1,2,3)
f
b
*
*
V
-
(HL) = (HL) - 1
DEC (IX+d)
11011101
00110101
----d---
12 (2,2,2,1,2,3)
f
b
*
*
V
-
(IX+d) = (IX+d) -1
DEC (IY+d)
11111101
00110101
----d---
12 (2,2,2,1,2,3)
f
b
*
*
V
-
(IY+d) = (IY+d) -1
DEC IX
11011101
00101011
4 (2,2)
-
-
-
-
IX = IX - 1
DEC IY
11111101
00101011
4 (2,2)
-
-
-
-
IY = IY - 1
DEC r
00-r-101
2
fr
*
*
V
-
r=r-1
DEC ss
00ss1011
2
r
-
-
-
-
ss = ss - 1
DJNZ e
00010000
--(e-2)-
5 (2,2,1)
r
-
-
-
-
B = B-1; if {B != 0} PC = PC + e
EX (SP),HL
11101101
01010100
15 (2,2,1,2,2,3,3)
r
-
-
-
-
H <-> (SP+1); L <-> (SP)
EX (SP),IX
11011101
11100011
15 (2,2,1,2,2,3,3)
-
-
-
-
IXH <-> (SP+1); IXL <-> (SP)
EX (SP),IY
11111101
11100011
15 (2,2,1,2,2,3,3)
-
-
-
-
IYH <-> (SP+1); IYL <-> (SP)
EX AF,AF’
00001000
2
-
-
-
-
AF <-> AF'
EX DE,HL
11101011
2
s
-
-
-
-
if (!ALTD) then DE <-> HL else DE <-> HL'
EX DE’,HL
11100011
2
s
-
-
-
-
if (!ALTD) then DE' <-> HL else DE' <-> HL'
EXX
11011001
2
-
-
-
-
BC <-> BC'; DE <-> DE'; HL <-> HL'
IDET
01011011
2
-
-
-
-
E = E, but if (EDMR && SU[0])
then System Violation interrupt flag is set
INC (HL)
00110100
8 (2,1,2,3)
f
b
*
*
V
-
(HL) = (HL) + 1
INC (IX+d)
11011101
00110100
----d---
12 (2,2,2,1,2,3)
f
b
*
*
V
-
(IX+d) = (IX+d) + 1
INC (IY+d)
11111101
00110100
----d---
12 (2,2,2,1,2,3)
f
b
*
*
V
-
(IY+d) = (IY+d) + 1
INC IX
11011101
00100011
4 (2,2)
-
-
-
-
IX = IX + 1
INC IY
11111101
00100011
4 (2,2)
-
-
-
-
IY = IY + 1
INC r
00-r-100
2
fr
*
*
V
-
r=r+1
INC ss
00ss0011
2
r
-
-
-
-
ss = ss + 1
IOE
11011011
2
-
-
-
-
I /O external prefix
P
M
N
N
IOI
11010011
2
-
-
-
-
I /O internal prefix
N
IPSET 0
11101101
01000110
4 (2,2)
-
-
-
-
IP = {IP[5:0], 00}
NP
IPSET 1
11101101
01010110
4 (2,2)
-
-
-
-
IP = {IP[5:0], 01}
NP
162
Rabbit 2000/3000 Microprocessor
Instruction
Opcode
byte 1
Opcode
byte 2
Opcode
byte 3
Opcode
byte 4
IPSET 2
11101101
01001110
4 (2,2)
-
-
-
IPSET 3
11101101
01011110
4 (2,2)
-
-
-
01011101
4 (2,2)
-
-
4 (2,2)
-
-
Clock cycles
A
I
S Z LV C
Operation
N/M/P
-
IP = {IP[5:0], 10}
NP
-
IP = {IP[5:0], 11}
NP
-
-
IP = {IP[1:0], IP[7:2]}
NP
-
-
PC = HL
IPRES
11101101
JP (HL)
11101001
JP (IX)
11011101
11101001
6 (2,2,2)
-
-
-
-
PC = IX
JP (IY)
11111101
11101001
6 (2,2,2)
-
-
-
-
PC = IY
JP f,mn
11-f-010
----n---
----m---
7 (2,2,2,1)
-
-
-
-
if {f} PC = mn
JP mn
11000011
----n---
----m---
7 (2,2,2,1)
-
-
-
-
PC = mn
JR cc,e
001cc000
--(e-2)-
5 (2,2,1)
-
-
-
-
if {cc} PC = PC + e
JR e
00011000
--(e-2)-
5 (2,2,1)
-
-
-
-
PC = PC + e
LCALL x,mn
11001111
----n---
19 (2,2,2,2,1,3,3,3,1)
-
-
-
-
(SP-1) = PCL; (SP-2) = PCH; (SP-3) =
XPC; XPC = x; PC = mn; SP = SP-3
LD (BC),A
00000010
7 (2,2,3)
d
-
-
-
-
(BC) = A
LD (DE),A
00010010
7 (2,2,3)
d
-
-
-
-
(DE) = A
LD (HL),n
00110110
7 (2,2,3)
d
-
-
-
-
(HL) = n
----m---
---x----
----n---
LD (HL),r
01110-r-
LD (HL+d),HL
11011101
11110100
LD (IX+d),HL
11110100
----d---
LD (IX+d),n
11011101
00110110
----d---
----d---
----n---
6 (2,1,3)
d
-
-
-
-
(HL) = r
13 (2,2,2,1,3,3)
d
-
-
-
-
(HL+d) = L; (HL+d+1) = H
N
11 (2,2,1,3,3)
d
-
-
-
-
(IX+d) = L; (IX+d+1) = H
N
11 (2,2,2,2,3)
d
-
-
-
-
(IX+d) = n
LD (IX+d),r
11011101
01110-r-
----d---
10 (2,2,2,1,3)
d
-
-
-
-
(IX+d) = r
LD (IY+d),HL
11111101
11110100
----d---
13 (2,2,2,1,3,3)
d
-
-
-
-
(IY+d) = L; (IY+d+1) = H
LD (IY+d),n
11111101
00110110
----d---
11 (2,2,2,2,3)
d
-
-
-
-
(IY+d) = n
LD (IY+d),r
11111101
01110-r-
----d---
10 (2,2,2,1,3)
d
-
-
-
-
(Iy+d) = r
----n---
N
LD (mn),A
00110010
----n---
----m---
10 (2,2,2,1,3)
d
-
-
-
-
(mn) = A
LD (mn),HL
00100010
----n---
----m---
13 (2,2,2,1,3,3)
d
-
-
-
-
(mn) = L; (mn+1) = H
LD (mn),IX
11011101
00100010
----n---
----m---
15 (2,2,2,2,1,3,3)
d
-
-
-
-
(mn) = IXL; (mn+1) = IXH
(mn) = IYL; (mn+1) = IYH
N
LD (mn),IY
11111101
00100010
----n---
----m---
15 (2,2,2,2,1,3,3)
d
-
-
-
-
LD (mn),ss
11101101
01ss0011
----n---
----m---
15 (2,2,2,2,1,3,3)
d
-
-
-
-
(mn) = ssl; (mn+1) = ssh
LD (SP+n),HL
11010100
----n---
11 (2,2,1,3,3)
-
-
-
-
(SP+n) = L; (SP+n+1) = H
N
LD (SP+n),IX
11011101
11010100
----n---
13 (2,2,2,1,3,3)
-
-
-
-
(SP+n) = IXL; (SP+n+1) = IXH
N
LD (SP+n),IY
11111101
11010100
----n---
13 (2,2,2,1,3,3)
N
LD A,(BC)
00001010
LD A,(DE)
00011010
LD A,(mn)
00111010
----n---
LD A,EIR
11101101
LD A,IIR
11101101
LD A,XPC
11101101
LD dd,(mn)
11101101
01dd1011
LD dd',BC
11101101
01dd1001
4 (2,2)
LD dd',DE
11101101
01dd0001
4 (2,2)
LD dd,mn
00dd0001
----n---
LD EIR,A
11101101
01000111
LD IIR,A
11101101
01001111
LD HL,(mn)
00101010
----n---
----m---
11 (2,2,2,1,2,2)
r
LD HL,(HL+d)
11011101
11100100
----d---
11 (2,2,2,1,2,2)
LD HL,(IX+d)
11100100
----d---
9 (2,2,1,2,2)
LD HL,(IY+d)
11111101
11100100
11 (2,2,2,1,2,2)
-
-
-
-
(SP+n) = IYL; (SP+n+1) = IYH
6 (2,2,2)
r
s
-
-
-
-
A = (BC)
6 (2,2,2)
r
s
-
-
-
-
A = (DE)
9 (2,2,2,1,2)
r
s
-
-
-
-
A = (mn)
01010111
4 (2,2)
fr
*
*
-
-
A = EIR
01011111
4 (2,2)
fr
*
*
-
-
A = IIR
01110111
4 (2,2)
r
-
-
-
-
A = XPC
13 (2,2,2,2,1,2,2)
r
-
-
-
-
ddl = (mn); ddh = (mn+1)
-
-
-
-
dd' = BC (dd': 00-BC', 01-DE', 10-HL')
N
-
-
-
-
dd' = DE (dd': 00-BC', 01-DE', 10-HL')
N
-
-
-
-
dd = mn
4 (2,2)
-
-
-
-
EIR = A
4 (2,2)
-
-
-
-
IIR = A
s
-
-
-
-
L = (mn); H = (mn+1)
r
s
-
-
-
-
L = (HL+d); H = (HL+d+1)
N
r
s
-
-
-
-
L = (IX+d); H = (IX+d+1)
N
r
s
-
-
-
-
L = (IY+d); H = (IY+d+1)
N
----m---
----n---
----m---
----d---
Instruction Reference Manual
----m---
6 (2,2,2)
s
r
N
163
Instruction
Opcode
byte 1
Opcode
byte 2
LD HL,(SP+n)
11000100
LD HL,IX
LD HL,IY
Opcode
byte 3
Opcode
byte 4
Clock cycles
A
----n---
9 (2,2,1,2,2)
r
-
-
-
11011101
01111100
4 (2,2)
r
-
-
11111101
01111100
4 (2,2)
r
-
-
LD IX,(mn)
11011101
00101010
----n---
-
LD IX,(SP+n)
11011101
11000100
----n---
11 (2,2,2,1,2,2)
----m---
13 (2,2,2,2,1,2,2)
I
s
S Z LV C
Operation
N/M/P
-
L = (SP+n); H = (SP+n+1)
N
-
-
HL = IX
N
-
-
HL = IY
N
-
-
-
IXL = (mn); IXH = (mn+1)
-
-
-
-
IXL = (SP+n); IXH = (SP+n+1)
N
N
LD IX,HL
11011101
01111101
4 (2,2)
-
-
-
-
IX = HL
LD IX,mn
11011101
00100001
----n---
----m---
8 (2,2,2,2)
-
-
-
-
IX = mn
----m---
13 (2,2,2,2,1,2,2)
LD IY,(mn)
11111101
00101010
----n---
LD IY,(SP+n)
11111101
11000100
----n---
-
-
-
-
IYL = (mn); IYH = (mn+1)
11 (2,2,2,1,2,2)
-
-
-
-
IYL = (SP+n); IYH = (SP+n+1)
N
4 (2,2)
-
-
-
-
IY = HL
N
8 (2,2,2,2)
-
-
-
-
IY = mn
LD IY,HL
11111101
01111101
LD IY,mn
11111101
00100001
LD r,(HL)
01-r-110
LD r,(IX+d)
11011101
01-r-110
LD r,(IY+d)
11111101
01-r-110
LD XPC,A
11101101
01100111
4 (2,2)
LD r,n
00-r-110
----n---
4 (2,2)
----n---
----m---
s
5 (2,1,2)
r
s
-
-
-
-
r = (HL)
----d---
9 (2,2,2,1,2)
r
s
-
-
-
-
r = (IX+d)
----d---
9 (2,2,2,1,2)
r
s
-
-
-
-
r = (IY+d)
-
-
-
-
XPC = A
r
-
-
-
-
r=n
r
NP
LD r,g
01-r--g
2
-
-
-
-
r=g
LD SP,HL
11111001
2
-
-
-
-
SP = HL
P
LD SP,IX
11011101
11111001
4 (2,2)
-
-
-
-
SP = IX
P
LD SP,IY
11111101
11111001
4 (2,2)
-
-
-
-
SP = IY
P
LDD
11101101
10101000
10 (2,2,1,2,3)
d
-
-
*
-
(DE) = (HL); BC = BC-1; DE = DE-1; HL =
HL-1
LDDR
11101101
10111000
6+7i (2,2,1,(2,3,2)i,1)
d
-
-
*
-
repeat: (DE) = (HL); BC = BC-1; DE = DE1; HL = HL-1 until {BC==0}
LDDSR
11101101
10011000
6+7i (2,2,1,(2,3,2)i,1)
d
-
-
*
-
(DE) = (HL); BC = BC-1; HL = HL-1;
repeat while BC != 0
LDI
11101101
10100000
10 (2,2,1,2,3)
d
-
-
*
-
(DE) = (HL); BC = BC-1; DE = DE+1; HL
= HL+1
LDIR
11101101
10110000
6+7i (2,2,1,(2,3,2)i,1)
d
-
-
*
-
repeat: (DE) = (HL); BC = BC-1; DE =
DE+1; HL = HL+1 until {BC == 0}
LDISR
11101101
10010000
6+7i (2,2,1,(2,3,2)i,1)
d
-
-
*
-
(DE) = (HL); BC = BC-1; HL = HL+1;
repeat while BC != 0
LDP (HL),HL
11101101
01100100
12 (2,2,2,3,3)
-
-
-
-
(HL) = L; (HL+1) = H. (Addr[19:16] =
A[3:0])
N
LDP (IX),HL
11011101
01100100
12 (2,2,2,3,3)
-
-
-
-
(IX) = L; (IX+1) = H. (Addr[19:16] =
A[3:0])
N
LDP (IY),HL
11111101
01100100
12 (2,2,2,3,3)
-
-
-
-
(IY) = L; (IY+1) = H. (Addr[19:16] =
A[3:0])
N
LDP (mn),HL
11101101
01100101
----n---
----m---
15 (2,2,2,2,1,3,3)
-
-
-
-
(mn) = L; (mn+1) = H. (Addr[19:16] =
A[3:0])
N
LDP (mn),IX
11011101
01100101
----n---
----m---
15 (2,2,2,2,1,3,3)
-
-
-
-
(mn) = IXL; (mn+1) = IXH. (Addr[19:16] =
A[3:0])
N
LDP (mn),IY
11111101
01100101
----n---
----m---
15 (2,2,2,2,1,3,3)
-
-
-
-
(mn) = IYL; (mn+1) = IYH. (Addr[19:16] =
A[3:0])
N
LDP HL,(HL)
11101101
01101100
10 (2,2,2,2,2)
-
-
-
-
L = (HL); H = (HL+1). (Addr[19:16] =
A[3:0])
N
LDP HL,(IX)
11011101
01101100
10 (2,2,2,2,2)
-
-
-
-
L = (IX); H = (IX+1). (Addr[19:16] =
A[3:0])
N
LDP HL,(IY)
11111101
01101100
10 (2,2,2,2,2)
-
-
-
-
L = (IY); H = (IY+1). (Addr[19:16] =
A[3:0])
N
LDP HL,(mn)
11101101
01101101
----n---
----m---
13 (2,2,2,2,1,2,2)
-
-
-
-
L = (mn); H = (mn+1). (Addr[19:16] =
A[3:0])
N
LDP IX,(mn)
11011101
01101101
----n---
----m---
13 (2,2,2,2,1,2,2)
-
-
-
-
IXL = (mn); IXH = (mn+1). (Addr[19:16] =
A[3:0])
N
164
Rabbit 2000/3000 Microprocessor
Instruction
Opcode
byte 1
Opcode
byte 2
Opcode
byte 3
Opcode
byte 4
Clock cycles
LDP IY,(mn)
11111101
01101101
----n---
----m---
13 (2,2,2,2,1,2,2)
-
-
-
-
LJP x,mn
11000111
----n---
----m---
---x----
10 (2,2,2,2,2)
-
-
-
A
I
S Z LV C
Operation
N/M/P
IYL = (mn); IYH = (mn+1). (Addr[19:16] =
A[3:0])
N
-
XPC = x; PC = mn
N
N
-
-
-
-
PCL = (SP); PCH = (SP+1); XPC =
(SP+2); SP = SP+3
s
-
-
*
-
(DE) = (HL); BC = BC-1; DE = DE-1;
HL = HL-1; repeat while BC != 0
6+7i (2,2,1,(2,3,2)i,1)
s
-
-
*
-
(DE) = (HL); BC = BC-1; DE = DE-1;
repeat while BC != 0
11010000
6+7i (2,2,1,(2,3,2)i,1)
s
-
-
*
-
(DE) = (HL); BC = BC-1; DE = DE+1;
repeat while BC != 0
11110000
6+7i (2,2,1,(2,3,2)i,1)
s
-
-
*
-
(DE) = (HL); BC = BC-1; DE = DE+1;
HL = HL+1; repeat while BC != 0
-
-
-
-
HL:BC = BC * DE
*
*
V
*
A=0-A
-
-
-
-
No operation
LRET
11101101
01000101
13 (2,2,1,2,2,2,2)
LSDR
11101101
11111000
6+7i (2,2,1,(2,3,2)i,1)
LSDDR
11101101
11011000
LSIDR
11101101
LSIR
11101101
MUL
11110111
12 (2,10)
01000100
4 (2,2)
fr
N
NEG
11101101
NOP
00000000
OR (HL)
10110110
5 (2,1,2)
fr
s
*
*
L
0
A = A | (HL)
OR (IX+d)
11011101
10110110
----d---
9 (2,2,2,1,2)
fr
s
*
*
L
0
A = A | (IX+d)
10110110
----d---
9 (2,2,2,1,2)
fr
s
*
*
L
0
A = A | (IY+d)
2
fr
*
*
L
0
HL = HL | DE
N
f
*
*
L
0
IX = IX | DE
N
N
2
OR (IY+d)
11111101
OR HL,DE
11101100
OR IX,DE
11011101
11101100
4 (2,2)
OR IY,DE
11111101
11101100
4 (2,2)
f
*
*
L
0
IY = IY | DE
OR n
11110110
----n---
4 (2,2)
fr
*
*
L
0
A=A|n
2
fr
OR r
10110-r-
*
*
L
0
A=A|r
POP IP
11101101
01111110
7 (2,2,1,2)
-
-
-
-
IP = (SP); SP = SP+1
POP IX
11011101
11100001
9 (2,2,1,2,2)
-
-
-
-
IXL = (SP); IXH = (SP+1); SP = SP+2
POP IY
11111101
11100001
9 (2,2,1,2,2)
-
-
-
-
IYL = (SP); IYH = (SP+1); SP = SP+2
POP SU
11101101
01101110
9 (2,2,2,3)
-
-
-
-
SU = (SP); SP = SP+1
POP zz
11zz0001
-
-
-
-
zzl = (SP); zzh = (SP+1); SP = SP+2
PUSH IP
11101101
01110110
9 (2,2,2,3)
-
-
-
-
(SP-1) = IP; SP = SP-1
PUSH IX
11011101
11100101
12 (2,2,2,3,3)
-
-
-
-
(SP-1) = IXH; (SP-2) = IXL; SP = SP-2
PUSH IY
11111101
11100101
12 (2,2,2,3,3)
-
-
-
-
(SP-1) = IYH; (SP-2) = IYL; SP = SP-2
PUSH SU
11101101
01100110
9 (2,2,2,3)
-
-
-
-
(SP-1) = SU; SP = SP-1
PUSH zz
11zz0101
10 (2,2,3,3)
-
-
-
-
(SP-1) = zzh; (SP-2) = zzl; SP = SP-2
7 (2,1,2,2)
r
RDMODE
11101101
01111111
4 (2,2)
-
-
-
•
CF = SU[0]
RES b,(HL)
11001011
10-b-110
10 (2,2,1,2,3)
d
-
-
-
-
(HL) = (HL) & ~bit
RES b,(IX+d)
11011101
11001011
----d---
10-b-110
13 (2,2,2,2,2,3)
d
-
-
-
-
(IX+d) = (IX+d) & ~bit
RES b,(IY+d)
11111101
11001011
----d---
10-b-110
13 (2,2,2,2,2,3)
d
-
-
-
-
(IY+d) = (IY+d) & ~bit
RES b,r
11001011
10-b--r-
-
-
-
-
r = r & ~bit
RET
11001001
8 (2,1,2,2,1)
-
-
-
-
PCL = (SP); PCH = (SP+1); SP = SP+2
RET f
11-f-000
2
8 (2,1,2,2,1)
-
-
-
-
if {f} PCL = (SP); PCH = (SP+1);
SP = SP+2
RETI
11101101
01001101
12 (2,2,1,2,2,2,1)
-
-
-
-
IP = (SP); PCL = (SP+1);
PCH = (SP+2); SP = SP+3
4 (2,2)
r
RL (HL)
11001011
00010110
10 (2,2,1,2,3)
f
b
*
*
L
*
{CY,(HL)} = {(HL),CY}
RL (IX+d)
11011101
11001011
----d---
00010110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
{CY,(IX+d)} = {(IX+d),CY}
RL (IY+d)
11111101
11001011
----d---
00010110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
{CY,(IY+d)} = {(IY+d),CY}
RL DE
11110011
RL r
11001011
RLA
00010111
RLC (HL)
11001011
2
fr
*
*
L
*
{CY,DE} = {DE,CY}
00010-r-
4 (2,2)
fr
*
*
L
*
{CY,r} = {r,CY}
2
fr
00000110
10 (2,2,1,2,3)
f
Instruction Reference Manual
b
-
-
-
*
{CY,A} = {A,CY}
*
*
L
*
(HL) = {(HL)[6,0],(HL)[7]}; CY = (HL)[7]
NP
P
N
P
P
NP
N
165
Instruction
Opcode
byte 1
Opcode
byte 2
Opcode
byte 3
Opcode
byte 4
Clock cycles
A
I
S Z LV C
RLC (IX+d)
11011101
11001011
----d---
00000110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
(IX+d) = {(IX+d)[6,0],(IX+d)[7]};
CY = (IX+d)[7]
RLC (IY+d)
11111101
11001011
----d---
00000110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
(IY+d) = {(IY+d)[6,0],(IY+d)[7]};
CY = (IY+d)[7]
RLC r
11001011
00000-r-
4 (2,2)
fr
*
*
L
*
r = {r[6,0],r[7]}; CY = r[7]
2
fr
-
-
-
*
A = {A[6,0],A[7]}; CY = A[7]
10 (2,2,1,2,3)
f
b
*
*
L
*
{(HL),CY} = {CY,(HL)}
Operation
N/M/P
RLCA
00000111
RR (HL)
11001011
00011110
RR (IX+d)
11011101
11001011
----d---
00011110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
{(IX+d),CY} = {CY,(IX+d)}
RR (IY+d)
11111101
11001011
----d---
00011110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
{(IY+d),CY} = {CY,(IY+d)}
RR DE
11111011
2
fr
*
*
L
*
{DE,CY} = {CY,DE}
N
RR HL
11111100
2
fr
*
*
L
*
{HL,CY} = {CY,HL}
N
RR IX
11011101
11111100
4 (2,2)
f
*
*
L
*
{IX,CY} = {CY,IX}
N
RR IY
11111101
11111100
4 (2,2)
f
*
*
L
*
{IY,CY} = {CY,IY}
N
RR r
11001011
00011-r-
4 (2,2)
fr
*
*
L
*
{r,CY} = {CY,r}
2
fr
-
-
-
*
{A,CY} = {CY,A}
10 (2,2,1,2,3)
f
b
*
*
L
*
(HL) = {(HL)[0],(HL)[7,1]}; CY = (HL)[0]
RRA
00011111
RRC (HL)
11001011
00001110
RRC (IX+d)
11011101
11001011
----d---
00001110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
(IX+d) = {(IX+d)[0],(IX+d)[7,1]};
CY = (IX+d)[0]
RRC (IY+d)
11111101
11001011
----d---
00001110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
(IY+d) = {(IY+d)[0],(IY+d)[7,1]};
CY = (IY+d)[0]
00001-r-
RRC r
11001011
4 (2,2)
fr
*
*
L
*
r = {r[0],r[7,1]}; CY = r[0]
RRCA
00001111
2
fr
-
-
-
*
A = {A[0],A[7,1]}; CY = A[0]
RST v
11-v-111
8 (2,2,2,2)
-
-
-
-
(SP-1) = PCH; (SP-2) = PCL;
SP = SP - 2; PC = {R, 0, v, 0000}
SBC A,(HL)
11011101
10011110
----d---
9 (2,2,2,1,2)
fr
s
*
*
V
*
A = A - (IX+d) - CY
SBC (IX+d)
11111101
10011110
----d---
9 (2,2,2,1,2)
fr
s
*
*
V
*
A = A - (IY+d) - CY
SBC (IY+d)
10011110
5 (2,1,2)
fr
s
*
*
V
*
A = A - (HL) - CY
SBC A,n
11011110
4 (2,2)
fr
*
*
V
*
A = A - n - CY
SBC A,r
10011-r-
2
fr
*
*
V
*
A = A - r - CY
SBC HL,ss
11101101
4 (2,2)
fr
*
*
V
*
HL = HL - ss - CF
SCF
00110111
2
f
-
-
-
1
CF = 1
SET b,(HL)
11001011
11-b-110
SET b,(IX+d)
11011101
11001011
----d---
SET b,(IY+d)
11111101
11001011
----d---
SET b,r
11001011
11-b--r-
4 (2,2)
SETUSR
11101101
01101111
4 (2,2)
SLA (HL)
11001011
00100110
10 (2,2,1,2,3)
f
SLA (IX+d)
11011101
11001011
----d---
00100110
13 (2,2,2,2,2,3)
f
SLA (IY+d)
11111101
11001011
----d---
00100110
13 (2,2,2,2,2,3)
f
SLA r
11001011
00100-r-
4 (2,2)
fr
SRA (HL)
11001011
00101110
10 (2,2,1,2,3)
f
SRA (IX+d)
11011101
11001011
----d---
00101110
13 (2,2,2,2,2,3)
SRA (IY+d)
11111101
11001011
----d---
00101110
----n---
01ss0010
10 (2,2,1,2,3)
b
-
-
-
-
(HL) = (HL) | bit
11-b-110
13 (2,2,2,2,2,3)
b
-
-
-
-
(IX+d) = (IX+d) | bit
11-b-110
13 (2,2,2,2,2,3)
b
-
-
-
-
(IY+d) = (IY+d) | bit
-
-
-
-
r = r | bit
-
-
-
-
SU = {SU[5:0], 0x01}
b
*
*
L
*
(HL) = {(HL)[6,0],0}; CY = (HL)[7]
b
*
*
L
*
(IX+d) = {(IX+d)[6,0],0}; CY = (IX+d)[7]
b
*
*
L
*
(IY+d) = {(IY+d)[6,0],0}; CY = (IY+d)[7]
*
*
L
*
r = {r[6,0],0}; CY = r[7]
b
*
*
L
*
(HL) = {(HL)[7],(HL)[7,1]}; CY = (HL)[0]
f
b
*
*
L
*
(IX+d) = {(IX+d)[7],(IX+d)[7,1]}; CY =
(IX+d)[0]
13 (2,2,2,2,2,3)
f
b
*
*
L
*
(IY+d) = {(IY+d)[7],(IY+d)[7,1]}; CY =
(IY+d)[0]
r
SRA r
11001011
00101-r-
4 (2,2)
fr
*
*
L
*
r = {r[7],r[7,1]}; CY = r[0]
SRL (HL)
11001011
00111110
10 (2,2,1,2,3)
f
b
*
*
L
*
(HL) = {0,(HL)[7,1]}; CY = (HL)[0]
SRL (IX+d)
11011101
11001011
----d---
00111110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
(IX+d) = {0,(IX+d)[7,1]}; CY = (IX+d)[0]
SRL (IY+d)
11111101
11001011
----d---
00111110
13 (2,2,2,2,2,3)
f
b
*
*
L
*
(IY+d) = {0,(IY+d)[7,1]}; CY = (IY+d)[0]
SRL r
11001011
00111-r-
4 (2,2)
fr
*
*
L
*
r = {0,r[7,1]}; CY = r[0]
166
P
Rabbit 2000/3000 Microprocessor
Instruction
Opcode
byte 1
Opcode
byte 2
Opcode
byte 3
SUB (HL)
10010110
SUB (IX+d)
11011101
10010110
----d---
SUB (IY+d)
11111101
10010110
----d---
SUB n
11010110
----n---
SUB r
10010-r-
SURES
11101101
01111101
SYSCALL
11101101
UMA
Opcode
byte 4
Clock cycles
A
I
S Z LV C
5 (2,1,2)
fr
s
*
*
V
*
A = A - (HL)
9 ( 2,2,2,1,2)
fr
s
*
*
V
*
A = A - (IX+d)
9 ( 2,2,2,1,2)
fr
s
*
*
V
*
A = A - (IY+d)
4 (2,2)
fr
*
*
V
*
A=A-n
2
fr
*
*
V
*
A=A-r
4 (2,2)
-
-
-
-
SU = {SU[1:0],SU[7:2]}
01110101
10 (2,2,3,3)
-
-
-
-
SP = SP-2; PC = {R,v}
where v = SYSCALL offset
11101101
11000000
8+8i (2,2,2,(2,2,3,1)i,2)
-
-
-
*
{CY:DE’:(HL)} = (IX) + [(IY)*DE+DE’+CY];
BC = BC-1; IX = IX+1; IY = IY+1; HL =
HL+1; repeat while BC != 0
UMS
11101101
11001000
8+8i (2,2,2,(2,2,3,1)i,2)
-
-
-
*
{CY:DE’:(HL)} = (IX) - [(IY)*DE+DE’+CY];
BC = BC-1; IX = IX+1; IY = IY+1; HL =
HL+1; repeat while BC != 0
XOR (HL)
10101110
5 (2,1,2)
fr
s
*
*
L
0
A = [A & ~(HL)] | [~A & (HL)]
XOR (IX+d)
11011101
10101110
----d---
9 (2,2,2,1,2)
fr
s
*
*
L
0
A = [A & ~(IX+d)] | [~A & (IX+d)]
XOR (IY+d)
11111101
10101110
----d---
9 (2,2,2,1,2)
fr
s
*
*
L
0
A = [A & ~(IY+d)] | [~A & (IY+d)]
XOR n
11101110
----n---
4 (2,2)
fr
*
*
L
0
A = [A & ~n] | [~A & n]
XOR r
10101-r-
2
fr
*
*
L
0
A = [A & ~r] | [~A & r]
Instruction Reference Manual
Operation
N/M/P
P
167
168
Rabbit 2000/3000 Microprocessor
Rabbit 2000/3000 Microprocessor Instruction Reference Manual
Part Number 019–0098 F • 040114 • Printed in U.S.A.
©2001 Rabbit Semiconductor • All rights reserved.
Rabbit Semiconductor reserves the right to make changes
and improvements to its products without providing notice.
Dynamic C is a registered trademark of Z-World.
Z80 and Z180 are trademarks of Zilog, Inc.
Notice to Users
Rabbit Semiconductor products are not authorized for use as critical components in life-support devices or systems unless a specific written agreement regarding such intended use is entered
into between the customer and Rabbit Semiconductor prior to
use. Life-support devices or systems are devices or systems
intended for surgical implantation into the body or to sustain life,
and whose failure to perform, when properly used in accordance
with instructions for use provided in the labeling and user’s manual, can be reasonably expected to result in significant injury.
No complex software or hardware system is perfect. Bugs are
always present in a system of any size. In order to prevent danger
to life or property, it is there responsibility of the system designer
to incorporate redundant protective mechanisms appropriate to
the risk involved.
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Instruction Reference
169
170
Rabbit 2000/3000 Microprocessor
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