Cypress Semiconductor | Perform nvSRAM | Specifications | Cypress Semiconductor Perform nvSRAM Specifications

CY14B256KA
256-Kbit (32 K × 8) nvSRAM with
Real Time Clock
256-Kbit (32 K × 8) nvSRAM with Real Time Clock
Features
■
256-Kbit nonvolatile static random access memory (nvSRAM)
❐ 25 ns and 45 ns access times
❐ Internally organized as 32 K × 8 (CY14B256KA)
❐ Hands off automatic STORE on power-down with only a small
capacitor
❐ STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power-down
❐ RECALL to SRAM initiated on power-up or by software
■ High reliability
❐ Infinite Read, Write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ 20 year data retention
■ Real time clock (RTC)
❐ Full-featured real time clock
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Capacitor or battery backup for RTC
❐ Backup current of 0.35 µA (Typ)
■
Industry standard configurations
❐ Single 3 V +20%, –10% operation
❐ Industrial temperature
❐ 48-pin shrink small-outline package (SSOP)
❐ Pb-free and Restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B256KA combines a 256-Kbit nonvolatile
static RAM with a full featured real time clock in a monolithic
integrated circuit. The embedded nonvolatile elements
incorporate QuantumTrap technology producing the world’s
most reliable nonvolatile memory. The SRAM is read and written
an infinite number of times, while independent nonvolatile data
resides in the nonvolatile elements.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
Logic Block
Diagram
Logic
Block
Diagram
VCC
QuantumTrap
512 X 512
A5
A9
A 11
A 12
A 13
POWER
CONTROL
STORE
ROW DECODER
A6
A7
A8
STATIC RAM
ARRAY
512 X 512
RECALL
DQ 0
DQ 4
DQ 5
DQ 6
VRTCcap
STORE/
RECALL
CONTROL
HSB
A14
- A0
COLUMN IO
INPUT BUFFERS
DQ 2
DQ 3
VRTCbat
SOFTWARE
DETECT
A 14
DQ 1
VCAP
COLUMN DEC
RTC
xout
xin
INT
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
MUX
A14
- A0
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-55720 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 3, 2013
CY14B256KA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ................................................................ 4
SRAM Write ................................................................. 4
AutoStore Operation .................................................... 4
Hardware STORE (HSB) Operation ............................ 4
Hardware RECALL (Power-Up) .................................. 5
Software STORE ......................................................... 5
Software RECALL ....................................................... 5
Preventing AutoStore .................................................. 6
Data Protection ............................................................ 6
Real Time Clock Operation .............................................. 7
nvTIME Operation ....................................................... 7
Clock Operations ......................................................... 7
Reading the Clock ....................................................... 7
Setting the Clock ......................................................... 7
Backup Power ............................................................. 7
Stopping and Starting the Oscillator ............................ 7
Calibrating the Clock ................................................... 8
Alarm ........................................................................... 8
Watchdog Timer .......................................................... 8
Power Monitor ............................................................. 9
Interrupts ..................................................................... 9
Interrupt Register ......................................................... 9
Flags Register ............................................................. 9
RTC External Components ....................................... 10
PCB Design Considerations for RTC ............................ 11
Layout requirements .................................................. 11
Maximum Ratings ........................................................... 16
Operating Range ............................................................. 16
Document Number: 001-55720 Rev. *H
DC Electrical Characteristics ........................................ 16
Data Retention and Endurance ..................................... 17
Capacitance .................................................................... 17
Thermal Resistance ........................................................ 17
AC Test Loads ................................................................ 18
AC Test Conditions ........................................................ 18
RTC Characteristics ....................................................... 18
AC Switching Characteristics ....................................... 19
SRAM Read Cycle .................................................... 19
SRAM Write Cycle ..................................................... 19
AutoStore/Power-Up RECALL ....................................... 21
Switching Waveforms .................................................... 21
Software Controlled STORE/RECALL Cycle ................ 22
Switching Waveforms .................................................... 22
Hardware STORE Cycle ................................................. 23
Switching Waveforms .................................................... 23
Truth Table For SRAM Operations ................................ 24
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC® Solutions ...................................................... 28
Cypress Developer Community ................................. 28
Technical Support ..................................................... 28
Page 2 of 28
CY14B256KA
Pinouts
Figure 1. 48-pin SSOP pinout
VCAP
[1]
NC
A14
A12
A7
A6
A5
INT
A4
NC
NC
NC
VSS
NC
VRTCbat
DQ0
A3
A2
A1
A0
DQ1
DQ2
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 - SSOP
(x8)
Top View
(not to scale)
48
47
VCC
NC[1]
46
45
44
43
42
41
40
HSB
WE
A13
A8
A9
39
38
37
36
NC
NC
NC
VSS
NC
35
34
33
32
31
30
29
28
27
26
25
NC
A11
VRTCcap
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
Pin Definitions
Pin Name
A0–A14
DQ0–DQ7
NC
WE
CE
OE
Xout[2]
Xin[2]
I/O Type
Input
Input/Output
No connect
Input
Description
Address inputs. Used to select One of the 32,768 bytes of the nvSRAM.
Bidirectional data I/O Lines. Used as input or output lines depending on operation.
No connect. This pin is not connected to the die.
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input
Input
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
Deasserting OE HIGH causes the I/O pins to tristate.
Crystal connection. Drives crystal on start up.
Crystal connection. For 32.768 kHz crystal.
Output
Input
VRTCcap[2] Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used.
VRTCbat[2] Power supply Battery supplied backup RTC supply voltage. Left unconnected if VRTCcap is used.
[2]
Output
Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power
INT
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
VSS
Ground
Ground for the device. Must be connected to the ground of the system.
VCC
HSB
Power supply Power supply inputs to the Device. 3.0 V +20%, –10%
Input/Output Hardware STORE Busy (HSB)
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Notes
1. Address expansion for 1-Mbit. NC pin not connected to die.
2. Left unconnected if RTC feature is not used.
Document Number: 001-55720 Rev. *H
Page 3 of 28
CY14B256KA
The CY14B256KA nvSRAM is made up of two functional
components paired in the same physical cell. These are a SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations
SRAM read and write operations are inhibited. The
CY14B256KA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer the Truth Table For SRAM Operations on page 24 for a
complete description of read and write modes.
Figure 2. AutoStore Mode
VCC
0.1 uF
10 kOhm
Device Operation
VCC
WE
VCAP
VCAP
VSS
SRAM Read
The CY14B256KA performs a read cycle whenever CE and OE
are LOW, and WE and HSB are HIGH. The address specified on
pins A0–14 determines which of the 32,768 data bytes are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle #1). If the
read is initiated by CE or OE, the outputs are valid at tACE or at
tDOE, whichever is later (read cycle #2). The data output
repeatedly responds to address changes within the tAA access
time without the need for transitions on any control input pins.
This remains valid until another address change or until CE or
OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins IO0–7 are
written into the memory if it is valid tSD before the end of a
WE-controlled write, or before the end of an CE-controlled write.
It is recommended that OE be kept HIGH during the entire write
cycle to avoid data bus contention on common I/O lines. If OE is
left LOW, internal circuitry turns off the output buffers tHZWE after
WE goes LOW.
AutoStore Operation
The CY14B256KA stores data to the nvSRAM using one of three
storage operations. These three operations are: Hardware
STORE, activated by the HSB; Software STORE, activated by
an address sequence; AutoStore, on device power-down. The
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256KA.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 6. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Document Number: 001-55720 Rev. *H
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 16 for the size of the VCAP. The voltage
on the VCAP pin is driven to VCC by a regulator on the chip. Place
a pull-up on WE to hold it inactive during power-up. This pull-up
is only effective if the WE signal is tristate during power-up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-RECALL, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place.
Hardware STORE (HSB) Operation
The CY14B256KA provides the HSB pin to control and
acknowledge the STORE operations. The HSB pin is used to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B256KA conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle begins only if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B256KA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
During any STORE operation, regardless of how it is initiated,
the CY14B256KA continues to drive the HSB pin LOW, releasing
Page 4 of 28
CY14B256KA
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on powerup, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B256KA Software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
Document Number: 001-55720 Rev. *H
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Page 5 of 28
CY14B256KA
Table 1. Mode Selection
OE
X
A14–A0[3]
X
Mode
I/O
Power
Not Selected
Output High Z
Standby
H
L
X
Read SRAM
Output Data
Active
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[4]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[4]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[4]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[4]
CE
H
WE
X
L
L
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B45 AutoStore Disable
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation.
To initiate the AutoStore enable sequence, the following
sequence of CE or OE controlled read operations must be
performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) issued to save the
AutoStore state through subsequent power-down cycles. The
part comes from the factory with AutoStore enabled and 0x00
written in all cells.
Data Protection
The CY14B256KA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low voltage condition is detected when
VCC is less than VSWITCH. If the CY14B256KA is in a write mode
(both CE and WE are LOW) at power-up, after a RECALL or
STORE, the write is inhibited until the SRAM is enabled after
tLZHSB (HSB to output active). This protects against inadvertent
writes during power-up or brown out conditions.
Notes
3. While there are 15 address lines on the CY14B256KA, only the lower 14 are used to control software modes.
4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-55720 Rev. *H
Page 6 of 28
CY14B256KA
Real Time Clock Operation
nvTIME Operation
The CY14B256KA offers internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. RTC registers
use the last 16 address locations of the SRAM. Internal double
buffering of the clock and timer information registers prevents
accessing transitional internal clock data during a read or write
operation. Double buffering also circumvents disrupting normal
timing counts or the clock accuracy of the internal clock when
accessing clock data. Clock and alarm registers store data in
BCD format.
RTC functionality is described in the following sections. The RTC
register addresses for CY14B256KA range from 0x7FF0 to
0x7FFF. Refer to Table 3 on page 12 and Table 4 on page 13 for
a detailed Register Map description.
Clock Operations
The clock registers maintain time up to 9,999 years in
one-second increments. The time can be set to any calendar
time and the clock automatically keeps track of days of the week
and month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time with a read cycle. These
registers contain the time of day in BCD format. Bits defined as
‘0’ are currently not used and are reserved for future use by
Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. Internal updates to the
CY14B256KA time keeping registers are stopped when the read
bit ‘R’ (in the flags register at 0x7FF0) is set to ‘1’ before reading
clock data to prevent reading of data in transition. Stopping the
register updates does not affect clock accuracy.
When a read sequence of RTC device is initiated, the update of
the user timekeeping registers stops and does not restart until a
‘0’ is written to the read bit ‘R’ (in the flags register at 0x7FF0).
After the end of read sequence, all the RTC registers are simultaneously updated within 20 ms.
Setting the Clock
A write access to the RTC device stops updates to the time
keeping registers and enables the time to be set when the write
bit ‘W’ (in the flags register at 0x7FF0) is set to ‘1’. The correct
day, date, and time is then written into the registers and must be
in 24 hour BCD format. The time written is referred to as the
“Base Time”. This value is stored in nonvolatile registers and
used in the calculation of the current time. When the write bit ‘W’
is cleared by writing ‘0’ to it, the values of timekeeping registers
are transferred to the actual clock counters after which the clock
resumes normal operation.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
Note After ‘W’ bit is set to ‘0’, values written into the timekeeping,
alarm, calibration, and interrupt registers are transferred to the
RTC time keeping counters in tRTCp time. These counter values
must be saved to nonvolatile memory either by initiating a
Document Number: 001-55720 Rev. *H
Software/Hardware STORE or AutoStore operation. While
working in AutoStore disabled mode, perform a STORE
operation after tRTCp time while writing into the RTC registers for
the modifications to be correctly recorded.
Backup Power
The RTC in the CY14B256KA is intended for permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14B256KA consumes a
0.35 µA (Typ) at room temperature. The user must choose
capacitor or battery values according to the application.
Note: If a battery is applied to VRTCbat pin prior to VCC, the chip
will draw high IBAK current. This occurs even if the oscillator is
disabled. In order to maximize battery life, VCC must be applied
before a battery is applied to VRTCbat pin.
Backup time values based on maximum current specifications
are shown in the following Table 2. Nominal backup times are
approximately two times longer.
Table 2. RTC Backup Time
Capacitor Value
0.1 F
0.47 F
1.0 F
Backup Time
72 hours
14 days
30 days
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3 V lithium is recommended and the CY14B256KA
sources current only from the battery when the primary power is
removed. However, the battery is not recharged at any time by
the CY14B256KA. The battery capacity must be chosen for total
anticipated cumulative down time required over the life of the
system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FF8 controls the
enable and disable of the oscillator. This bit is nonvolatile and is
shipped to customers in the “enabled” (set to ‘0’) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum level,
the oscillator may fail.The CY14B256KA has the ability to detect
oscillator failure when system power is restored. This is recorded
in the Oscillator Fail Flag (OSCF) of the flags register at the
address 0x7FF0. When the device is powered on (VCC goes
above VSWITCH) the OSCEN bit is checked for the ‘enabled’
status. If the OSCEN bit is enabled and the oscillator is not active
Page 7 of 28
CY14B256KA
within the first 5 ms, the OSCF bit is set to ‘1’. The system must
check for this condition and then write ‘0’ to clear the flag.
Note that in addition to setting the OSCF flag bit, the time
registers are reset to the ‘Base Time’, which is the value last
written to the timekeeping registers. The control or calibration
registers and the OSCEN bit are not affected by the ‘oscillator
failed’ condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
To reset OSCF, set the write bit ‘W’ (in the flags register at
0x7FF0) to a ‘1’ to enable writes to the flags register . Write a ‘0’
to the OSCF bit and then reset the write bit to ‘0’ to disable writes.
Calibrating the Clock
The RTC is driven by a quartz controlled crystal with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystals available in market
typically have an error of +20 ppm to +35 ppm. However,
CY14B256KA employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25 °C. This implies an error of +2.5
seconds to –5 seconds per month.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in Calibration register at 0x7FF8. The
calibration bits occupy the five lower order bits in the Calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it
corresponds to an adjustment of 4.068 or –2.034 ppm offset in
oscillator error, depending on the sign.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once every minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the flags
register (0x7FF0) must be set to ‘1’. This causes the INT pin to
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
Note Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit ‘W’ (in the flags register at
0x7FF0) to ‘1’ to enable writes to the flags register . Write a value
to CAL, and then reset the write bit to ‘0’ to disable writes.
Document Number: 001-55720 Rev. *H
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x7FF1-5) with the corresponding time of day and date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
There are four alarm match fields – date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register
at 0x7FF0 indicates that a date or time match has occurred. The
AF bit is set to ‘1’ when a match occurs. Reading the flags
register clears the alarm flag bit (and all others). A hardware
interrupt pin may also be used to detect an alarm event.
To set, clear or enable an alarm, set the ‘W’ bit (in flags register
– 0x7FF0) to ‘1’ to enable writes to Alarm Registers. After writing
the alarm value, clear the ‘W’ bit back to ‘0’ for the changes to
take effect.
Note CY14B256KA requires the alarm match bit for seconds (bit
‘D7’ in Alarm-Seconds register 0x7FF2) to be set to ‘0’ for proper
operation of Alarm Flag and Interrupt..
Watchdog Timer
The watchdog timer is a free running down counter that uses the
32 Hz clock (31.25 ms) derived from the crystal oscillator. The
oscillator must be running for the watchdog to function. It begins
counting down from the value loaded in the watchdog timer
register.
The timer consists of a loadable register and a free running
counter. On power-up, the watchdog time out value in register
0x7FF7 is loaded into the counter load register. Counting begins
on power-up and restarts from the loadable value any time the
watchdog strobe (WDS) bit is set to ‘1’. The counter is compared
to the terminal value of ‘0’. If the counter reaches this value, it
causes an internal flag and an optional interrupt output. You can
prevent the time out interrupt by setting WDS bit to ‘1’ prior to the
counter reaching ‘0’. This causes the counter to reload with the
watchdog time out value and to be restarted. As long as the user
sets the WDS bit prior to the counter reaching the terminal value,
the interrupt and WDT flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5–D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5–D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 3. Note that setting the
watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the watchdog interrupt
enable (WIE) bit in the interrupt register is set, a hardware
Page 8 of 28
CY14B256KA
interrupt on INT pin is also generated on watchdog timeout. The
flag and the hardware interrupt are both cleared when user reads
the flags register.
.
Figure 3. Watchdog Timer Block Diagram
Clock
Divider
Oscillator
32,768 KHz
Interrupts are only generated while working on normal power and
are not triggered when system is running in backup power mode.
1 Hz
32 Hz
Counter
Zero
Compare
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
WDF
Note CY14B256KA generates valid interrupts only after the
Powerup RECALL sequence is completed. All events on INT pin
must be ignored for tHRECALL duration after powerup.
Interrupt Register
Load
Register
WDS
D
Q
WDW
Q
write to
Watchdog
Register
Watchdog
Register
Power Monitor
The CY14B256KA provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to VSWITCH
threshold.
As described in the AutoStore Operation on page 4, when
VSWITCH is reached as VCC decays from power loss, a data
STORE operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
When operating from the backup source, read and write
operations to nvSRAM are inhibited and the RTC functions are
not available to the user. The RTC clock continues to operate in
the background. The updated RTC time keeping registers data
are available to the user after VCC is restored to the device (see
AutoStore/Power-Up RECALL on page 21).
Interrupts
The CY14B256KA has flags register, interrupt register and
interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the interrupt
register (0x7FF6). In addition, each has an associated flag bit in
the flags register (0x7FF0) that the host processor uses to
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
An interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in interrupts
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
Document Number: 001-55720 Rev. *H
Watchdog Interrupt Enable (WIE). When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in flags register.
Alarm Interrupt Enable (AIE). When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF flag in flags register.
Power Fail Interrupt Enable (PFE). When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in flags
register.
High/Low (H/L). When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives high only
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. The INT pin
must be pulled up to Vcc by a 10 k resistor while using the
interrupt in active LOW mode.
Pulse/Level (P/L). When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
flags register is read.
When an enabled interrupt source activates the INT pin, an
external host reads the flags register to determine the cause. All
flags are cleared when the register is read. If the INT pin is
programmed for level mode, then the condition clears and the
INT pin returns to its inactive state. If the pin is programmed for
pulse mode, then reading the flag also clears the flag and the pin.
The pulse does not complete its specified duration if the flags
register is read. If the INT pin is used as a host reset, then the
flags register is not read during a reset.
Flags Register
The flags register has three flag bits: WDF, AF, and PF, which
can be used to generate an interrupt. These flags are set by the
watchdog timeout, alarm match, or power fail monitor
respectively. The processor can either poll this register or enable
interrupts to be informed when a flag is set. These flags are
automatically reset when the register is read. The flags register
is automatically loaded with the value 0x00 on power-up (except
for the OSCF bit; see Stopping and Starting the Oscillator on
page 7).
Page 9 of 28
CY14B256KA
Figure 4. Interrupt Block Diagram
WDF
Watchdog
Timer
WIE
P/L
VCC
PF
Power
Monitor
Pin
Driver
PFE
INT
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
Enable
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
VINT
H/L
VSS
AF
Clock
Alarm
AIE
RTC External Components
The RTC requires connecting an external 32.768 kHz crystal and
C1, C2 load capacitance as shown in the Figure 5. The figure
shows the recommnded RTC external component values. The
load capacitances C1 and C2 are inclusive of parasitic of the
printed circuit board (PCB). The PCB parasitic includes the
capacitance due to land pattern of crystal pads/pins, Xin/Xout
pads and copper traces connecting crystal and device pins.
Figure 5. RTC Recommended Component Configuration [5]
Recommended Values
Y1 = 32.768 kHz (12.5 pF)
C1 = 10 pF
C2 = 67 pF
Note: The recommended values for C1 and C2 include
board trace capacitance.
C1
Y1
C2
Xout
Xin
Note
5. For nonvolatile static random access memory (nvSRAM) real time clock (RTC) design guidelines and best practices, see application note AN61546.
Document Number: 001-55720 Rev. *H
Page 10 of 28
CY14B256KA
PCB Design Considerations for RTC
RTC crystal oscillator is a low current circuit with high impedance
nodes on their crystal pins. Due to lower timekeeping current of
RTC, the crystal connections are very sensitive to noise on the
board. Hence it is necessary to isolate the RTC circuit from other
signals on the board.
It is also critical to minimize the stray capacitance on the PCB.
Stray capacitances add to the overall crystal load capacitance
and therefore cause oscillation frequency errors. Proper
bypassing and careful layout are required to achieve the
optimum RTC performance.
■
Keep Xin and Xout trace width lesser than 8 mils. Wider trace
width leads to larger trace capacitance. The larger these bond
pads and traces are, the more likely it is that noise can couple
from adjacent signals.
■
Shield the Xin and Xout signals by providing a guard ring around
the crystal circuitry. This guard ring prevents noise coupling
from neighboring signals.
■
Take care while routing any other high speed signal in the
vicinity of RTC traces. The more the crystal is isolated from
other signals on the board, the less likely it is that noise is
coupled into the crystal. Maintain a minimum of 200 mil
separation between the Xin, Xout traces and any other high
speed signal on the board.
■
No signals should run underneath crystal components on the
same PCB layer.
Layout requirements
The board layout must adhere to (but not limited to) the following
guidelines during routing RTC circuitry. Following these guidelines help you achieve optimum performance from the RTC
design.
■
It is important to place the crystal as close as possible to the
Xin and Xout pins. Keep the trace lengths between the crystal
and RTC equal in length and as short as possible to reduce the
probability of noise coupling by reducing the length of the
antenna.
Create an isolated solid copper plane on adjacent PCB layer and
underneath the crystal circuitry to prevent unwanted noise
coupled from traces routed on the other signal layers of the PCB.
The local plane should be separated by at least 40 mils from the
neighboring plane on the same PCB layer. The solid plane
should be in the vicinity of RTC components only and its
perimeter should be kept equal to the guard ring perimeter.
Figure 6 shows the recommended layout for RTC circuit.
Figure 6. Recommended Layout for RTC
Top component layer: L1
Ground plane layer: L2
System ground
C1
Isolated ground plane on
layer 2 : L2
Guard ring - Top (Component)
layer: L1
Y1
C2
Via: Via connects to isolated
ground plane on L2
Document Number: 001-55720 Rev. *H
Via: Via connects to system ground
plane on L2
Page 11 of 28
CY14B256KA
Table 3. RTC Register Map [6, 7]
BCD Format Data [6]
Register
CY14B256KA
D7
0x7FFF
0x7FFE
D6
D5
D4
D3
D2
D1
10s years
0
0
0x7FFD
0
0
0x7FFC
0
0
0x7FFB
0
0
0x7FFA
0
0
10s
months
10s day of month
0
0
Years: 00–99
Months
Months: 01–12
Day of month
Day of month: 01–31
Day of week
10s hours
10s seconds
Function/Range
Years
0
10s minutes
D0
Day of week: 01–07
Hours
Hours: 00–23
Minutes
Minutes: 00–59
0x7FF9
0
0x7FF8
OSCEN
(0)
0
Seconds
0x7FF7
WDS (0)
WDW
(0)
0x7FF6
WIE (0)
AIE (0) PFE (0)
0x7FF5
M (1)
0
10s alarm date
Alarm day
Alarm, Day of month: 01–31
0x7FF4
M (1)
0
10s alarm hours
Alarm hours
Alarm, hours: 00–23
Cal
sign (0)
Seconds: 00–59
Calibration values [8]
Calibration (00000)
Watchdog [8]
WDT (000000)
0
H/L (1)
P/L (0)
0
0
Interrupts [8]
0x7FF3
M (1)
10s alarm minutes
Alarm minutes
Alarm, minutes: 00–59
0x7FF2
M (1)
10s alarm seconds
Alarm, seconds
Alarm, seconds: 00–59
0x7FF1
0x7FF0
10s centuries
WDF
AF
PF
Centuries
OSCF [9]
0
CAL
(0)
W (0)
Centuries: 00–99
R (0)
Flags [8]
Notes
6. The unused bits of RTC registers are reserved for future use and should be set to ‘0’.
7. ( ) designates values shipped from the factory.
8. This is a binary value, not a BCD value.
9. When the user resets OSCF flag bit, the flags register will be updated after tRTCp time.
Document Number: 001-55720 Rev. *H
Page 12 of 28
CY14B256KA
Table 4. Register Map Detail
Register
Description
CY14B256KA
0x7FFF
Time Keeping - Years
D7
D6
D5
D4
D3
D2
10s years
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble
(four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
0x7FFE
Time Keeping - Months
D7
D6
D5
D4
0
0
0
10s month
D3
D2
D1
D0
Months
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;
upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.
0x7FFD
Time Keeping - Date
D7
D6
0
0
D5
D4
D3
10s day of month
D2
D1
D0
Day of month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is
1–31. Leap years are automatically adjusted for.
0x7FFC
Time Keeping - Day
D7
D6
D5
D4
D3
0
0
0
0
0
D2
D1
D0
Day of week
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter
that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not
integrated with the date.
0x7FFB
Time Keeping - Hours
D7
D6
0
0
D5
D4
D3
D2
10s hours
D1
D0
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register
is 0–23.
0x7FFA
Time Keeping - Minutes
D7
D6
0
D5
D4
D3
D2
10s minutes
D1
D0
Minutes
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;
upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is
0–59.
0x7FF9
Time Keeping - Seconds
D7
D6
0
D5
10s seconds
D4
D3
D2
D1
D0
Seconds
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;
upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59.
Document Number: 001-55720 Rev. *H
Page 13 of 28
CY14B256KA
Table 4. Register Map Detail (continued)
Register
Description
CY14B256KA
0x7FF8
OSCEN
Calibration/Control
D7
D6
D5
OSCEN
0
Calibration
sign
D4
D3
D2
D1
D0
Calibration
Oscillator Enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs. Disabling the
oscillator saves battery or capacitor power during storage.
Calibration Sign Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.
Calibration
0x7FF7
These five bits control the calibration of the clock.
WatchDog Timer
D7
D6
WDS
WDW
D5
D4
D3
D2
D1
D0
WDT
WDS
Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect.
The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always
returns a 0.
WDW
Watchdog write enable. Setting this bit to ‘1’ disables any WRITE to the watchdog timeout value (D5–D0). This
allows the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to ‘0’ allows
bits D5–D0 to be written to the watchdog register when the next write cycle is complete. This function is explained
in more detail in Watchdog Timer on page 8.
WDT
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It
represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to
2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written
only if the WDW bit was set to 0 on a previous cycle.
0x7FF6
Interrupt Status/Control
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
0
H/L
P/L
0
0
WIE
Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer drives the INT
pin and the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF flag.
AIE
Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the
alarm match only affects the AF flag.
PFE
Power fail enable. When set to ‘1’, the power fail monitor drives the INT pin and the PF flag. When set to ‘0’, the
power fail monitor affects only the PF flag.
0
Reserved for future use
H/L
High/Low. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0’, the INT pin is open drain, active LOW.
P/L
Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for
approximately 200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L) until the flags
register is read.
0x7FF5
Alarm - Day
D7
D6
M
0
D5
D4
10s alarm date
D3
D2
D1
D0
Alarm date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
M
Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the date value.
Document Number: 001-55720 Rev. *H
Page 14 of 28
CY14B256KA
Table 4. Register Map Detail (continued)
Register
Description
CY14B256KA
0x7FF4
Alarm - Hours
D7
D6
M
0
D5
D4
D3
10s alarm hours
D2
D1
D0
Alarm hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
0x7FF3
Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the
match circuit to ignore the hours value.
Alarm - Minutes
D7
D6
M
D5
D4
D3
10s alarm minutes
D2
D1
D0
Alarm minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
0x7FF2
Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to ‘1’ causes the
match circuit to ignore the minutes value.
Alarm - Seconds
D7
D6
M
D5
D4
D3
10s alarm seconds
D2
D1
D0
Alarm seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M
0x7FF1
Match. When this bit is set to ‘0’, the seconds value is used in the alarm match. Setting this bit to ‘1’ causes the
match circuit to ignore the seconds value.
Time Keeping - Centuries
D7
D6
D5
D4
D3
D2
10s centuries
D1
D0
Centuries
Contains the BCD value of centuries. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;
upper nibble (four bits) contains the upper digit and operates from 0 to 9. The range for the register is 0–99
centuries.
0x7FF0
Flags
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
WDF
Watchdog timer flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach 0 without being
reset by the user. It is cleared to ‘0’ when the flags register is read or on power-up.
AF
Alarm flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers
with the match bits = 0. It is cleared when the flags register is read or on power-up.
PF
Power fail flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared
to 0 when the flags register is read or on power-up.
OSCF
Oscillator fail flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first 5 ms of operation.
This indicates that RTC backup power failed and clock value is no longer valid. This bit survives the power cycle
and is never cleared internally by the chip. The user must check for this condition and write '0' to clear this flag.
When user resets OSCF flag bit, the bit will be updated after tRTCp time.
CAL
Calibration mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin
resumes normal operation. This bit defaults to 0 (disabled) on power-up.
W
Write enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then write to RTC
registers, alarm registers, calibration register, interrupt register and flags register. Setting the ‘W’ bit to ‘0’ causes
the contents of the RTC registers to be transferred to the time keeping counters if the time has changed. This
transfer process takes tRTCp time to complete. This bit defaults to 0 on power-up.
R
Read enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates are not seen
during the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding register. Setting this bit does
not require ‘W’ bit to be set to ‘1’. This bit defaults to 0 on power-up.
Document Number: 001-55720 Rev. *H
Page 15 of 28
CY14B256KA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
At 150 C ambient temperature ...................... 1000 h
DC output current (1 output at a time, 1s duration) .... 15 mA
At 85 C ambient temperature ..................... 20 Years
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Maximum junction temperature ..................................150C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VCC + 0.5 V
Input voltage ....................................... –0.5 V to VCC + 0.5 V
Latch up current ............................................... ..... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
–40 C to +85 C
2.7 V to 3.6 V
Industrial
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ [10]
Max
Unit
2.7
3.0
3.6
V
VCC
Power supply voltage
ICC1
Average Vcc current
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
–
–
70
52
mA
mA
ICC2
Average VCC current during
STORE
All inputs don’t care, VCC = Max.
Average current for duration tSTORE
–
–
10
mA
ICC3[10]
Average VCC current at
tRC= 200 ns, VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
–
35
–
mA
ICC4
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current
for duration tSTORE
–
–
5
mA
ISB
VCC standby current
CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
W bit set to ‘0’.
Standby current level after
nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
–
–
5
mA
IIX[11]
Input leakage current (except
HSB)
VCC = Max, VSS < VIN < VCC
–1
–
+1
µA
Input leakage current (for HSB)
VCC = Max, VSS < VIN < VCC
–100
–
+1
µA
–1
–
+1
µA
2.0
–
VCC + 0.5
V
IOZ
Off state output leakage current
VIH
Input HIGH voltage
VIL
Input LOW voltage
VSS – 0.5
–
0.8
V
VOH
Output HIGH voltage
IOUT = –2 mA
2.4
–
–
V
VOL
Output LOW voltage
IOUT = 4 mA
–
–
0.4
V
VCC = Max, VSS < VOUT < VCC,
CE or OE > VIH or WE < VIL
Notes
10. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
11. The HSB pin has IOUT = –2 µA for VOH of 2.4 V when both active HIGH and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document Number: 001-55720 Rev. *H
Page 16 of 28
CY14B256KA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
VCAP[12]
VVCAP[13, 14]
Description
Storage capacitor
Test Conditions
Between VCAP pin and VSS
Maximum voltage driven on VCAP VCC = Max
pin by the device
Min
Typ [10]
Max
Unit
61
68
180
µF
–
–
VCC
V
Data Retention and Endurance
Over the Operating Range
Parameter
Description
Min
Unit
20
Years
1,000
K
Max
Unit
Input capacitance (except HSB) TA = 25 C, f = 1 MHz, VCC = VCC(Typ)
7
pF
Input capacitance (for HSB)
8
pF
Output capacitance (except HSB)
7
pF
Output capacitance (for HSB)
8
pF
Test Conditions
48-pin SSOP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
37.47
C/W
24.71
C/W
DATAR
Data retention
NVC
Nonvolatile STORE operations
Capacitance
Parameter[14]
CIN
COUT
Description
Test Conditions
Thermal Resistance
Parameter[14]
Description
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Notes
12. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on
VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
13. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating
temperature range should be higher than the VVCAP voltage.
14. These parameters are guaranteed by design and are not tested.
Document Number: 001-55720 Rev. *H
Page 17 of 28
CY14B256KA
AC Test Loads
Figure 7. AC Test Loads
577 
577 
3.0 V
3.0 V
R1
R1
OUTPUT
OUTPUT
30 pF
R2
789 
R2
789 
5 pF
AC Test Conditions
Input pulse levels ...................................................0 V to 3 V
Input rise and fall times (10%–90%) ............................ <3 ns
Input and output timing reference levels ....................... 1.5 V
RTC Characteristics
Over the Operating Range
Parameter
Description
VRTCbat
RTC battery pin voltage
IBAK[16]
RTC backup current
TA (Min)
(Refer Figure 5 for the recommended external componets 25 °C
for RTC)
TA (Max)
VRTCcap
[17]
RTC capacitor pin voltage
tOCS
RTC oscillator time to start
tRTCp
RTC processing time from end of ‘W’ bit set to ‘0’
RBKCHG
RTC backup capacitor charge current-limiting resistor
Min
Typ [15]
1.8
3.0
3.6
V
–
–
0.35
µA
–
0.35
–
µA
–
–
0.5
µA
Max
Units
TA (Min)
1.6
–
3.6
V
25 °C
1.5
3.0
3.6
V
TA (Max)
1.4
–
3.6
V
–
1
2
sec
–
–
350
s
350
–
850

Notes
15. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
16. From either VRTCcap or VRTCbat.
17. If VRTCcap > 0.5 V or if no capacitor is connected to VRTCcap pin, the oscillator starts in tOCS time. If a backup capacitor is connected and VRTCcap < 0.5 V, the capacitor
must be allowed to charge to 0.5 V for oscillator to start.
Document Number: 001-55720 Rev. *H
Page 18 of 28
CY14B256KA
AC Switching Characteristics
Over the Operating Range
Parameters [18]
Cypress
Alt Parameter
Parameter
25 ns
Description
45 ns
Min
Max
Min
Max
Unit
SRAM Read Cycle
tACE
tACS
tRC
Chip enable access time
Read cycle time
–
25
25
–
–
45
45
–
ns
ns
tAA [20]
tAA
Address access time
–
25
–
45
ns
tDOE
tOE
Output enable to data valid
–
12
–
20
ns
tOHA[20]
tLZCE [21, 22]
tHZCE [21, 22]
tLZOE [21, 22]
tHZOE [21, 22]
tPU [21]
tPD [21]
tOH
Output hold after address change
3
–
3
–
ns
tLZ
Chip enable to output active
3
–
3
–
ns
tHZ
Chip disable to output Inactive
–
10
–
15
ns
tOLZ
Output enable to output active
0
–
0
–
ns
tOHZ
Output disable to output inactive
–
10
–
15
ns
tPA
Chip enable to power active
0
–
0
–
ns
tPS
Chip disable to power standby
–
25
–
45
ns
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
25
20
20
10
0
20
0
0
–
–
–
–
–
–
–
–
–
10
45
30
30
15
0
30
0
0
–
–
–
–
–
–
–
–
–
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output active after end of write
3
–
3
–
ns
tRC
[19]
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
[21, 22, 23] t
tHZWE
WZ
[21, 22]
t
tLZWE
OW
Switching Waveforms
Figure 8. SRAM Read Cycle #1 (Address Controlled) [19, 20, 24]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
18. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 7 on page 18.
19. WE must be HIGH during SRAM read cycles.
20. Device is continuously selected with CE and OE LOW.
21. These parameters are guaranteed by design and are not tested.
22. Measured ±200 mV from steady state output voltage.
23. If WE is low when CE goes low, the outputs remain in the high impedance state.
24. HSB must remain HIGH during Read and Write cycles.
Document Number: 001-55720 Rev. *H
Page 19 of 28
CY14B256KA
Switching Waveforms (continued)
Figure 9. SRAM Read Cycle #2 (CE and OE Controlled) [25, 26]
Address
Address Valid
tRC
tHZCE
tACE
CE
tAA
tLZCE
tHZOE
tDOE
OE
tLZOE
Data Output
High Impedance
Output Data Valid
tPU
ICC
tPD
Active
Standby
Figure 10. SRAM Write Cycle #1 (WE Controlled) [26, 27, 28]
tWC
Address
Address Valid
tSCE
tHA
CE
tAW
tPWE
WE
tSA
tHD
tSD
Data Input
Input Data Valid
tLZWE
tHZWE
Data Output
High Impedance
Previous Data
Figure 11. SRAM Write Cycle #2 (CE Controlled) [26, 27, 28]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tPWE
WE
tSD
Input Data Valid
Data Input
Data Output
tHD
High Impedance
Notes
25. WE must be HIGH during SRAM read cycles.
26. HSB must remain HIGH during Read and Write cycles.
27. If WE is low when CE goes low, the outputs remain in the high impedance state.
28. CE or WE must be >VIH during address transitions.
Document Number: 001-55720 Rev. *H
Page 20 of 28
CY14B256KA
AutoStore/Power-Up RECALL
Over the Operating Range
Parameter
Min
–
Max
20
Unit
ms
STORE cycle duration
–
8
ms
tDELAY [31]
Time allowed to complete SRAM write cycle
–
25
ns
VSWITCH
Low voltage trigger level
–
2.65
V
tHRECALL
tSTORE
[29]
[30]
tVCCRISE
[32]
VHDIS[32]
tLZHSB[32]
tHHHD[32]
Description
Power-Up RECALL duration
VCC rise time
150
–
µs
HSB output disable voltage
–
1.9
V
HSB to output active time
HSB high active time
–
–
5
500
µs
ns
Switching Waveforms
Figure 12. AutoStore or Power-Up RECALL [33]
VCC
VSWITCH
VHDIS
t VCCRISE
tHHHD
Note30
tSTORE
Note
tHHHD
34
Note
30
tSTORE
34
Note
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
29. tHRECALL starts from the time VCC rises above VSWITCH.
30. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place
31. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
32. These parameters are guaranteed by design and are not tested.
33. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
34. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-55720 Rev. *H
Page 21 of 28
CY14B256KA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
Parameter [35, 36]
tRC
tSA
tCW
tHA
tRECALL
tSS [37, 38]
25 ns
Description
Min
25
0
20
0
–
–
STORE/RECALL initiation cycle time
Address setup time
Clock pulse width
Address hold time
RECALL duration
Soft sequence processing time
45 ns
Max
–
–
–
–
200
100
Min
45
0
30
0
–
–
Max
–
–
–
–
200
100
Unit
ns
ns
ns
ns
µs
µs
Switching Waveforms
Figure 13. CE & OE Controlled Software STORE/RECALL Cycle [36]
tRC
Address
tRC
Address #1
tSA
Address #6
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tHZCE
tLZCE
t DELAY
39
Note
tLZHSB
High Impedance
tSTORE/tRECALL
DQ (DATA)
RWI
Figure 14. AutoStore Enable/Disable Cycle[36]
Address
tRC
tRC
Address #1
Address #6
tSA
CE
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tLZCE
tSS
tHZCE
39
Note
t DELAY
DQ (DATA)
RWI
Notes
35. The software sequence is clocked with CE controlled or OE controlled reads.
36. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.
37. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
38. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
39. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document Number: 001-55720 Rev. *H
Page 22 of 28
CY14B256KA
Hardware STORE Cycle
Over the Operating Range
Parameter
Description
Min
Max
Unit
tDHSB
HSB to output active time when write latch not set
–
25
ns
tPHSB
Hardware STORE pulse width
15
–
ns
Switching Waveforms
Figure 15. Hardware STORE Cycle [40]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
tLZHSB
DQ (Data Out)
RWI
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100 kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
HSB (IN)
HSB (OUT)
tDELAY
tDHSB
tDHSB
RWI
Figure 16. Soft Sequence Processing [41, 42]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Notes
40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
41. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
42. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document Number: 001-55720 Rev. *H
Page 23 of 28
CY14B256KA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 5. Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High Z
Deselect/Power-down
Standby
L
H
L
Data out (DQ0–DQ7)
Read
Active
L
H
H
High Z
Output disabled
Active
L
L
X
Data in (DQ0–DQ7)
Write
Active
Ordering Information
Speed
(ns)
25
Ordering Code
CY14B256KA-SP25XIT
Package Diagram
51-85061
Package Type
48-pin SSOP
Operating Range
Industrial
CY14B256KA-SP25XI
45
CY14B256KA-SP45XIT
CY14B256KA-SP45XI
All the above parts are Pb-free.
Ordering Code Definitions
CY 14 B 256 K A - SP 25 X I T
Option:
T - Tape and Reel
Blank - Std.
Pb-free
Temperature:
I - Industrial (–40 °C to 85 °C)
Speed:
25 - 25 ns
45 - 45 ns
Package:
SP - 48-pin SSOP
Die revision:
Blank - No Rev
A - 1st Rev
Data Bus:
K - × 8 + RTC
Voltage:
B - 3.0 V
Density:
256 - 256 Kb
14 - nvSRAM
Cypress
Document Number: 001-55720 Rev. *H
Page 24 of 28
CY14B256KA
Package Diagram
Figure 17. 48-pin SSOP (300 Mils) Package Outline, 51-85061
51-85061 *F
Document Number: 001-55720 Rev. *H
Page 25 of 28
CY14B256KA
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BCD
Binary Coded Decimal
CE
CMOS
Chip Enable
%
percent
Complementary Metal Oxide Semiconductor
°C
degree celsius
EIA
Electronic Industries Alliance
F
farad
HSB
I/O
Hardware Store Busy
Hz
hertz
Input/Output
kHz
kilohertz
nvSRAM
non-volatile Static Random Access Memory
k
kilohm
OE
Output Enable
A
microampere
PCB
RoHS
Printed Circuit Board
mA
milliampere
Restriction of Hazardous Substances
F
microfarad
RTC
Real Time Clock
MHz
megahertz
RWI
Read and Write Inhibited
s
microsecond
SRAM
Static Random Access Memory
ms
millisecond
SSOP
Shrink Small Outline Package
ns
nanosecond
WE
Write Enable
pF
picofarad
ppm
parts per million
V
volt

ohm
W
watt
Document Number: 001-55720 Rev. *H
Symbol
Unit of Measure
Page 26 of 28
CY14B256KA
Document History Page
Document Title: CY14B256KA, 256-Kbit (32 K × 8) nvSRAM with Real Time Clock
Document Number: 001-55720
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2763469
GVCH
09/14/09
New data sheet.
*A
2829117
GVCH
12/16/09
Added data retention and endurance table
Updated STORE cycles to QuantumTrap from 200K to 1 Million
Updated IBAK RTC backup current spec unit from nA to A
Added Contents. Moved to external web
*B
2922858
GVCH
04/26/10
Pin Definitions: Added more clarity on HSB pin operation
Hardware STORE (HSB) Operation: Added more clarity on HSB pin operation
Updated HSB pin operation in Figure 12 and updated footnote 34.
Updated package diagram.
*C
3143855
GVCH
01/17/2011
Updated Setting the Clock description
Added footnote 7
Updated ‘W’ bit description in Register Map Detail table
Updated Maximum Ratings
Added tRTCp parameter to RTC Characteristics table
Figure 11: Typo error fixed
Added Acronyms table and Units of Measure table
*D
3315247
GVCH
07/15/2011
Updated DC Electrical Characteristics (Added Note 12 and referred the same
note in VCAP parameter).
Updated Capacitance (Included Input capacitance (for HSB) and Output
capacitance (for HSB)).
Updated AC Switching Characteristics (Added Note 18 and referred the same
note in Parameters).
*E
3587664
GVCH
04/16/2012
Updated Pin Definitions (Added Note 2 and referred the same note in VRTCcap,
VRTCbat, Xout, Xin, INT pins).
Added Note 5 and referred the same note in Figure .
Updated Package Diagram.
*F
3660966
GVCH
06/29/2012
Updated DC Electrical Characteristics (Added VVCAP parameter and its details,
added Note 13 and referred the same note in VVCAP parameter, also referred
Note 14 in VVCAP parameter).
*G
3759143
GVCH
09/28/2012
Updated Real Time Clock Operation (description).
Updated Maximum Ratings (Removed “Ambient temperature with power
applied” and included “Maximum junction temperature”).
Updated Package Diagram (spec 51-85061 (Changed revision from *E to *F)).
*H
4048849
GVCH
07/03/2013
Updated Pin Definitions:
Updated HSB pin description (Added more clarity).
Description of Change
Updated Device Operation:
Updated AutoStore Operation (Removed sentence “The HSB signal is
monitored by the system to detect if an AutoStore cycle is in progress.”).
Updated Real Time Clock Operation:
Updated Backup Power (Added Note).
Added RTC External Components.
Moved Figure 5 from Flags Register section to RTC External Components
section.
Added PCB Design Considerations for RTC.
Updated in new template.
Document Number: 001-55720 Rev. *H
Page 27 of 28
CY14B256KA
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-55720 Rev. *H
Revised July 3, 2013
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