Cypress Semiconductor | NoBL CY7C1462AV25 | CY7C1460AV25/CY7C1462AV25, 36-Mbit (1 M × 36/2 M

CY7C1460AV25
CY7C1462AV25
36-Mbit (1 M × 36/2 M × 18)
Pipelined SRAM with NoBL™ Architecture
36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin-compatible and functionally equivalent to ZBT™
■
Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200 and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte Write capability
■
2.5 V core power supply
■
2.5 V/1.8 V I/O power supply
■
Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
CY7C1460AV25,
CY7C1462AV25
available
in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 165-ball FBGA package.
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
Burst capability – linear or interleaved burst order
■
“ZZ” sleep mode option and stop clock option
The
CY7C1460AV25/CY7C1462AV25
are
2.5 V,
1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No
Bus Latency™ (NoBL logic, respectively. They are designed
to support unlimited true back-to-back read/write operations with
no wait states. The CY7C1460AV25/CY7C1462AV25 are
equipped with the advanced NoBL logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent write/read
transitions.
The
CY7C1460AV25/CY7C1462AV25
are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1460AV25 and BWa–BWb for
CY7C1462AV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram – CY7C1460AV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
MEMORY
ARRAY
WRITE
DRIVERS
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document Number: 38-05354 Rev. *J
O
U
T
P
U
T
D
A
T
A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 24, 2012
CY7C1460AV25
CY7C1462AV25
Logic Block Diagram – CY7C1462AV25
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
BURST A0'
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
BWb
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05354 Rev. *J
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Page 2 of 31
CY7C1460AV25
CY7C1462AV25
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Burst Read Accesses .................................................. 7
Single Write Accesses ................................................. 7
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Partial Write Cycle Description ..................................... 10
Partial Write Cycle Description ..................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 16
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
Document Number: 38-05354 Rev. *J
1.8 V TAP AC Test Conditions ....................................... 17
1.8 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC Solutions ......................................................... 31
Page 3 of 31
CY7C1460AV25
CY7C1462AV25
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
2.6
435
120
3.2
385
120
3.4
335
120
ns
mA
mA
Maximum access time
Maximum operating current
Maximum CMOS standby current
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1462AV25
(2 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
NC/72M
VSS
VDD
A
A
A
A
A
A
A
A
NC/72M
VSS
VDD
NC/144M
NC/288M
MODE
A
A
A
A
A1
A0
Document Number: 38-05354 Rev. *J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC/288M
(1 M × 36)
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
NC/144M
CY7C1460AV25
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 4 of 31
CY7C1460AV25
CY7C1462AV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1460AV25 (1 M × 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
CE2
BWc
BWb
CE3
CEN
ADV/LD
A
A
NC
BWa
VSS
CLK
WE
VSS
VSS
OE
VSS
VDD
A
A
NC
VSS
VSS
VDDQ
VDDQ
NC
DQb
DQPb
DQb
R
MODE
NC/1G
A
DQPc
DQc
NC
DQc
VDDQ
VDDQ
BWd
VSS
VDD
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
NC
DQd
DQc
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQb
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQc
NC
DQd
VDDQ
VDDQ
NC
VDDQ
DQb
NC
DQa
DQb
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
A
A
TMS
A0
TCK
A
A
A
8
9
10
CEN
ADV/LD
A
A
A
WE
VSS
OE
VSS
A
A
NC
VDDQ
VSS
VDD
VDDQ
NC
NC
DQPa
DQa
NC/144M NC/72M
A
VSS
NC/288M
A
CY7C1462AV25 (2 M × 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
NC/576M
A
NC/1G
A
NC
NC
3
4
5
CE1
CE2
BWb
NC
NC
NC
DQb
VDDQ
VSS
VDD
VSS
VDDQ
VSS
VSS
VSS
BWa
6
CE3
CLK
7
11
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
NC
NC
DQb
DQb
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQb
NC
NC
VDDQ
VDDQ
NC
VDDQ
NC
NC
DQa
DQa
DQa
ZZ
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
A
A
TDI
A1
TDO
A
A
A
A
A
TMS
A0
TCK
A
A
A
NC/144M NC/72M
MODE
A
Document Number: 38-05354 Rev. *J
NC/288M
A
Page 5 of 31
CY7C1460AV25
CY7C1462AV25
Pin Definitions
Pin Name
A0, A1, A
I/O Type
Pin Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous
BWa, BWb,
InputByte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input used to advance the on-chip address counter or load a new address. When
synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, active LOW. Combined with the synchronous logic block inside the device to control
asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
DQa, DQb,
DQc, DQd
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by AX
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd
are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPa,
DQPb,
DQPc,
DQPd
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
TDI
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
input
synchronous
TMS
Test mode This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
select
synchronous
TCK
JTAG-clock
Clock input to the JTAG circuitry.
Document Number: 38-05354 Rev. *J
Page 6 of 31
CY7C1460AV25
CY7C1462AV25
Pin Definitions (continued)
Pin Name
VDD
VDDQ
I/O Type
Pin Description
Power supply Power supply inputs to the core of the device.
I/O power
supply
Power supply for the I/O circuitry.
VSS
NC
NC/72M
Ground
N/A
N/A
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/576M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/1G
N/A
Not connected to the die. Can be tied to any voltage level.
ZZ
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
Not connected to the die. Can be tied to any voltage level.
InputZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Functional Overview
The
CY7C1460AV25/CY7C1462AV25
are
synchronous-pipelined burst NoBL SRAMs designed specifically
to eliminate wait states during write/read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[x] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (200-MHz device)
Document Number: 38-05354 Rev. *J
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will three-state following the next clock rise.
Burst Read Accesses
The CY7C1460AV25/CY7C1462AV25 have an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Accesses section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and will wrap-around when incremented sufficiently.
A HIGH input on ADV/LD will increment the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (Read or Write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the address register. The write signals are latched
into the control logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1460AV25 and DQa,b/DQPa,b for
CY7C1462AV25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
Page 7 of 31
CY7C1460AV25
CY7C1462AV25
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1460AV25 and DQa,b/DQPa,b for
CY7C1462AV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into the
device and the write is complete.
( BWa,b,c,d for CY7C1460AV25 and BWa,b for CY7C1462AV25)
inputs must be driven in each cycle of the burst write in order to
write the correct bytes of data.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1460AV25 and BWa,b for CY7C1462AV25)
signals. The CY7C1460AV25/CY7C1462AV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Sleep Mode
Interleaved Burst Address Table
(MODE = Floating or VDD)
Because the CY7C1460AV25/CY7C1462AV25 are common I/O
devices, data should not be driven into the device while the
outputs are active. The output enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
First
Address
A1:A0
00
01
10
11
( DQa,b,c,d/DQPa,b,c,d for CY7C1460AV25 and DQa,b/DQPa,b for
CY7C1462AV25) inputs. Doing so will tri-state the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1460AV25 and DQa,b/DQPa,b for CY7C1462AV25) are
automatically three-stated during the data portion of a write
cycle, regardless of the state of OE.
Second
Address
A1:A0
01
00
11
10
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
10
01
00
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
00
01
10
Linear Burst Address Table
Burst Write Accesses
(MODE = GND)
The CY7C1460AV25/CY7C1462AV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in the Single Write Accesses section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct BW
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
10
11
00
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Sleep mode standby current
Test Conditions
ZZ  VDD 0.2 V
tZZS
Device operation to ZZ
ZZ VDD  0.2 V
tZZREC
ZZ recovery time
ZZ  0.2 V
tZZI
ZZ active to sleep current
tRZZI
ZZ Inactive to exit sleep current
Document Number: 38-05354 Rev. *J
Min
Max
Unit
–
100
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 8 of 31
CY7C1460AV25
CY7C1462AV25
Truth Table
The truth table for CY7C1460AV25/CY7C1462AV25 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Deselect cycle
Address Used CE
None
H
ZZ
L
ADV/LD WE BWx
L
X
X
OE
X
CEN CLK
L
L–H
DQ
Tri-state
Continue deselect cycle
None
X
L
H
X
X
X
L
L–H
Read cycle (begin burst)
External
L
L
L
H
X
L
L
L–H Data out (Q)
Tri-state
Read cycle (continue burst)
Next
X
L
H
X
X
L
L
L–H Data out (Q)
NOP/dummy read (begin burst)
External
L
L
L
H
X
H
L
L–H
Dummy read (continue burst)
Next
X
L
H
X
X
H
L
L–H
Tri-state
Write cycle (begin burst)
External
L
L
L
L
L
X
L
L–H
Data in (D)
Write cycle (continue burst)
Next
X
L
H
X
L
X
L
L–H
Data in (D)
NOP/WRITE ABORT (begin burst)
None
L
L
L
L
H
X
L
L–H
Tri-state
WRITE ABORT (continue burst)
Next
X
L
H
X
H
X
L
L–H
Tri-state
IGNORE CLOCK EDGE (stall)
Current
X
L
X
X
X
X
H
L–H
–
Sleep MODE
None
X
H
X
X
X
X
X
X
Tri-state
Tri-state
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Three-state when OE is
inactive or when the device is deselected, and DQs=data when OE is active.
Document Number: 38-05354 Rev. *J
Page 9 of 31
CY7C1460AV25
CY7C1462AV25
Partial Write Cycle Description
The partial write cycle description table for CY7C1460AV25 follows. [8, 9, 10, 11]
WE
BWd
BWc
BWb
BWa
Read
Function (CY7C1460AV25)
H
X
X
X
X
Write – no bytes written
L
H
H
H
H
Write byte a – (DQa and DQPa)
L
H
H
H
L
Write byte b – (DQb and DQPb)
L
H
H
L
H
Write bytes b, a
L
H
H
L
L
Write byte c – (DQc and DQPc)
L
H
L
H
H
Write bytes c, a
L
H
L
H
L
Write bytes c, b
L
H
LL
L
H
Write bytes c, b, a
L
H
L
L
L
Write byte d – (DQd and DQPd)
L
L
H
H
H
Write bytes d, a
L
L
H
H
L
Write bytes d, b
L
L
H
L
H
Write bytes d, b, a
L
L
H
L
L
Write bytes d, c
L
L
L
H
H
Write bytes d, c, a
L
L
L
H
L
Write bytes d, c, b
L
L
L
L
H
Write all bytes
L
L
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
9. Write is defined by WE and BWX. See Write Cycle Description table for details.
10. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
11. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05354 Rev. *J
Page 10 of 31
CY7C1460AV25
CY7C1462AV25
Partial Write Cycle Description
The partial write cycle description table for CY7C1462AV25 follows. [12, 13, 14, 15]
WE
BWb
BWa
Read
Function (CY7C1462AV25)
H
X
X
Write – no bytes written
L
H
H
Write byte a – (DQa and DQPa)
L
H
L
Write byte b – (DQb and DQPb)
L
L
H
Write both bytes
L
L
L
Notes
12. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
13. Write is defined by WE and BWX. See Write Cycle Description table for details.
14. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
15. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05354 Rev. *J
Page 11 of 31
CY7C1460AV25
CY7C1462AV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1460AV25/CY7C1462AV25 incorporates a serial
boundary scan test access port (TAP). This part is fully compliant
with 1149.1. The TAP operates using JEDEC-standard 2.5 V/1.8
V I/O logic level.
The CY7C1460AV25/CY7C1462AV25 contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller Block
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see TAP Controller State Diagram on
page 14). The output changes on the falling edge of TCK. TDO
is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 15. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in the
Scan Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 19 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
TAP Instruction Set
Overview
TAP Registers
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
Document Number: 38-05354 Rev. *J
Page 12 of 31
CY7C1460AV25
CY7C1462AV25
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK# captured in the boundary
scan register.
Document Number: 38-05354 Rev. *J
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tri-state,” is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 31
CY7C1460AV25
CY7C1462AV25
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05354 Rev. *J
Page 14 of 31
CY7C1460AV25
CY7C1462AV25
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
Selection
Circuitry
. 2 1 0
TDO
Identification Register
x .
.
.
.
. 2 1 0
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Timing
1
2
Test Clock
(TCK)
3
tTH
tTMSS
tTMSH
tTDIS
tTDIH
t
TL
4
5
6
tCYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTDOV
tTDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 38-05354 Rev. *J
UNDEFINED
Page 15 of 31
CY7C1460AV25
CY7C1462AV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS set-up to TCK clock rise
5
–
ns
tTDIS
TDI set-up to TCK clock rise
5
–
ns
tCS
Capture set-up to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
Set-up Times
Hold Times
Notes
16. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 38-05354 Rev. *J
Page 16 of 31
CY7C1460AV25
CY7C1462AV25
2.5 V TAP AC Test Conditions
1.8 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 2.5 V
Input pulse levels ................................ 0.2 V to VDDQ – 0.2 V
Input rise and fall time ....................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................... ..............1.25 V
Input timing reference levels ......................................... 0.9 V
Output reference levels .............................................. 1.25 V
Output reference levels ................................................ 0.9 V
Test load termination supply voltage .......................... 1.25 V
Test load termination supply voltage ............................ 0.9 V
2.5 V TAP AC Output Load Equivalent
1.8 V TAP AC Output Load Equivalent
1.25V
0.9V
50
50
TDO
TDO
Z O= 50
Z O= 50
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [18]
Min
Max
Unit
VOH1
Output HIGH voltage
Description
IOH = –1.0 mA
Test Conditions
VDDQ = 2.5 V
1.7
–
V
VOH2
Output HIGH voltage
IOH = –100 A
VDDQ = 2.5 V
2.1
–
V
VDDQ = 1.8 V
1.6
–
V
VOL1
Output LOW voltage
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW voltage
IOL = 100 A
VDDQ = 2.5 V
–
0.2
V
VDDQ = 1.8 V
–
0.2
V
VIH
Input HIGH voltage
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 1.8 V
1.26
VDD + 0.3
V
VIL
Input LOW voltage
VDDQ = 2.5 V
–0.3
0.7
V
VDDQ = 1.8 V
–0.3
0.36
V
IX
Input load current
–5
5
A
GND  VI  VDDQ
Note
18. All voltages referenced to VSS (GND).
Document Number: 38-05354 Rev. *J
Page 17 of 31
CY7C1460AV25
CY7C1462AV25
Identification Register Definitions
Instruction Field
CY7C1460AV25
(1 M × 36)
CY7C1462AV25
(2 M × 18)
000
000
Revision number (31:29)
Device depth (28:24)
Architecture/memory type(23:18)
Bus width/density(17:12)
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Description
Describes the version number
01011
01011
001000
001000
Defines memory type and architecture
Reserved for internal use
Defines width and density
100111
010111
00000110100
00000110100
1
1
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Instruction
Bit Size (× 36)
Bit Size (× 18)
3
3
Bypass
1
1
ID
32
32
Boundary scan order (165-ball FBGA package)
89
89
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 38-05354 Rev. *J
Page 18 of 31
CY7C1460AV25
CY7C1462AV25
Boundary Scan Order
165-ball FBGA [19]
CY7C1460AV25 (1 M × 36), CY7C1462AV25 (2 M × 18)
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
27
D11
52
A2
77
N2
3
N10
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
14
M11
39
C10
64
F2
89
Internal
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
A5
72
J2
23
H10
48
A4
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Note
19. Bit# 89 is preset HIGH.
Document Number: 38-05354 Rev. *J
Page 19 of 31
CY7C1460AV25
CY7C1462AV25
Maximum Ratings
Current into outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001V
Latch-up current ................................................... > 200 mA
Operating Range
Supply voltage on VDD relative to GND .......–0.5 V to +3.6 V
Range
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Commercial
DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V
Industrial
Ambient
Temperature
VDD
VDDQ
0 °C to +70 °C
2.5 V – 5% /
+ 5%
1.7 V to VDD
–40 °C to +85 °C
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range
Parameter [20, 21]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
IOZ
IDD
Test Conditions
for 2.5 V I/O
for 1.8 V I/O
Output HIGH voltage
for 2.5 V I/O, IOH =1.0 mA
for 1.8 V I/O, IOH = –100 A
Output LOW voltage
for 2.5 V I/O, IOL =1.0 mA
for 1.8 V I/O, IOL = 100 A
Input HIGH voltage [20]
for 2.5 V I/O
for 1.8 V I/O
Input LOW voltage [20]
for 2.5 V I/O
for 1.8 V I/O
Input leakage current except ZZ GND  VI  VDDQ
and MODE
Input current of MODE
Input = VSS
Input = VDD
Input current of ZZ
Input = VSS
Input = VDD
Output leakage current
GND  VI  VDDQ, output disabled
VDD operating supply
VDD = Max, IOUT = 0 mA,
4-ns cycle,
f = fMAX = 1/tCYC
250 MHz
5-ns cycle,
200 MHz
6-ns cycle,
167 MHz
Min
2.375
2.375
1.7
2.0
1.6
–
–
1.7
1.26
–0.3
–0.3
–5
Max
Unit
2.625
V
VDD
V
1.9
V
–
V
–
V
0.4
V
0.2
V
VDD + 0.3 V V
VDD + 0.3 V
V
0.7
V
0.36
V
5
A
–30
–
–5
–
–5
–
5
–
30
5
435
A
A
A
A
A
mA
–
385
mA
–
335
mA
ISB1
Automatic CE power-down
current – TTL inputs
Max VDD, device deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC
All speed
grades
–
185
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max VDD, device deselected,
All speed
VIN  0.3 V or VIN > VDDQ 0.3 V, grades
f=0
–
120
mA
Notes
20. Overshoot: VIH(AC) < VDD +1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
21. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05354 Rev. *J
Page 20 of 31
CY7C1460AV25
CY7C1462AV25
Electrical Characteristics (continued)
Over the Operating Range
Parameter [20, 21]
Description
Test Conditions
ISB3
Automatic CE power-down
current – CMOS inputs
ISB4
Automatic CE power-down
current – TTL inputs
Max VDD, device deselected,
VIN  0.3 V or VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
Max VDD, device deselected,
VIN  VIH or VIN  VIL, f = 0
Min
Max
Unit
All speed
grades
–
160
mA
All speed
grades
–
135
mA
Capacitance
Parameter [22]
Description
100-pin TQFP 165-ball FBGA Unit
Max
Max
Test Conditions
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
TA = 25 °C, f = 1 MHz,
VDD = 2.5 V VDDQ = 2.5 V
6.5
7
pF
3
7
pF
5.5
6
pF
Thermal Resistance
Parameter [22]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
25.21
20.8
°C/W
2.58
3.2
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3 V
OUTPUT
R = 317 
Z0 = 50 
VT = 1.5 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V I/O Test Load
2.5 V
OUTPUT
GND
R = 351 
VT = 1.25 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
 1 ns
 1 ns
(b)
(c)
R = 1667 
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 
Z0 = 50 
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 
GND
R = 1538 
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
22. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05354 Rev. *J
Page 21 of 31
CY7C1460AV25
CY7C1462AV25
Switching Characteristics
Over the Operating Range
Parameter [23, 24]
tPower[25]
Description
VCC(typical) to the first access read or write
-250
-200
-167
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
ms
4.0
–
5.0
–
6.0
–
ns
–
250
–
200
–
167
MHz
Clock
tCYC
Clock cycle time
FMAX
Maximum operating frequency
tCH
Clock HIGH
1.5
–
2.0
–
2.4
–
ns
tCL
Clock LOW
1.5
–
2.0
–
2.4
–
ns
–
2.6
–
3.2
–
3.4
ns
Output Times
tCO
Data output valid after CLK rise
tEOV
OE LOW to output valid
tDOH
Data output hold after CLK rise
tCHZ
tCLZ
tEOHZ
tEOLZ
Clock to high Z
Clock to low Z
[26, 27, 28]
[26, 27, 28]
OE HIGH to output high Z
OE LOW to output low Z
[26, 27, 28]
[26, 27, 28]
–
2.6
–
3.0
–
3.4
ns
1.0
–
1.5
–
1.5
–
ns
–
2.6
–
3.0
–
3.4
ns
1.0
–
1.3
–
1.5
–
ns
–
2.6
–
3.0
–
3.4
ns
0
–
0
–
0
–
ns
Set-up Times
tAS
Address set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tDS
Data input set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tCENS
CEN set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tWES
WE, BWx set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tALS
ADV/LD set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tCES
Chip select set-up
1.2
–
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
Hold Times
tCENH
CEN hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tWEH
WE, BWx hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tCEH
Chip select hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
Notes
23. Timing reference is 1.25 V when VDDQ = 2.5 V and 0.9 V when VDDQ = 1.8 V.
24. Test conditions shown in (a) of Figure 3 on page 21 unless otherwise noted.
25. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated.
26. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 3 on page 21. Transition is measured ±200 mV from steady-state voltage.
27. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
28. This parameter is sampled and not 100% tested.
Document Number: 38-05354 Rev. *J
Page 22 of 31
CY7C1460AV25
CY7C1462AV25
Switching Waveforms
Figure 4. Read/Write/Timing [29, 30, 31]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
In-Out (DQ)
tDH
D(A1)
tDOH
tCLZ
D(A2)
Q(A3)
D(A2+1)
tOEV
tCHZ
Q(A4+1)
Q(A4)
D(A5)
Q(A6)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Figure 5. NOP, STALL and DESELECT Cycles [29, 30, 32]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
29. For this waveform ZZ is tied low.
30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
31. Order of the burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved). Burst operations are optional.
32. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 38-05354 Rev. *J
Page 23 of 31
CY7C1460AV25
CY7C1462AV25
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [33, 34]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
33. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
34. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 38-05354 Rev. *J
Page 24 of 31
CY7C1460AV25
CY7C1462AV25
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
200
250
Ordering Code
CY7C1460AV25-167AXC
Package
Diagram
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1460AV25-167BZC
51-85165 165-ball FBGA (15 × 17 × 1.4 mm)
CY7C1462AV25-167BZI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm)
CY7C1460AV25-167BZXI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
CY7C1460AV25-200BZXI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
CY7C1460AV25-200BZI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm)
CY7C1460AV25-200BZXC
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
CY7C1462AV25-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1460AV25-250AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
Industrial
Industrial
Commercial
Commercial
Ordering Code Definitions
CY 7
C 146X A V25 - XXX XX
X X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 167 MHz or 200 MHz or 250 MHz
V25 = 2.5 V VDD
Process Technology: A  90 nm
Part Identifier: 146X = 1460 or 1462
1460 = PL, 1 Mb × 36 (36 Mb)
1462 = PL, 2 Mb × 18 (36 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAMs
Company ID: CY = Cypress
Document Number: 38-05354 Rev. *J
Page 25 of 31
CY7C1460AV25
CY7C1462AV25
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05354 Rev. *J
Page 26 of 31
CY7C1460AV25
CY7C1462AV25
Package Diagrams (continued)
Figure 8. 165-ball FBGA (15 × 17 × 1.4 mm) (0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *D
Document Number: 38-05354 Rev. *J
Page 27 of 31
CY7C1460AV25
CY7C1462AV25
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CEN
clock enable
°C
degree Celsius
CMOS
complementary metal-oxide-semiconductor
MHz
megahertz
EIA
electronic industries alliance
µA
microampere
FBGA
fine-pitch ball grid array
mA
milliampere
I/O
input/output
mm
millimeter
JEDEC
joint electron devices engineering council
ms
millisecond
JTAG
joint test action group
mV
millivolt
LSB
least significant bit
ns
nanosecond
MSB
most significant bit
%
percent
NoBL
No Bus Latency
pF
picofarad
OE
output enable
V
volt
SRAM
static random access memory
W
watt
TAP
test access port
TCK
test clock
TMS
test mode select
TDI
test data-in
TDO
test data-out
TQFP
thin quad flat pack
TTL
transistor-transistor logic
WE
write enable
Document Number: 38-05354 Rev. *J
Symbol
Unit of Measure
Page 28 of 31
CY7C1460AV25
CY7C1462AV25
Document History Page
Document Title: CY7C1460AV25/CY7C1462AV25, 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05354
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
254911
See ECN
SYT
New data sheet
Part number changed from previous revision (New and old part number differ
by the letter “A”)
*A
303533
See ECN
SYT
Updated Pin Configurations (Changed H9 pin from VSSQ to VSS for 209-ball
FBGA).
Updated Electrical Characteristics (Changed the test condition for VOL
parameter from VDD = Min. to VDD = Max., changed maximum value of IDD
parameter from 450 mA, 400 mA and 350 mA to 435 mA, 385 mA and 335 mA
for 250 MHz, 200 MHz and 167 MHz respectively, changed maximum value of
ISB1 parameter from 190 mA, 180 mA and 170 mA to 185 mA for 250 MHz,
200 MHz and 167 MHz respectively, changed maximum value of ISB2
parameter from 80 mA to 100 mA for all frequencies, changed maximum value
of ISB3 parameter from 180 mA, 170 mA and 160 mA to 160 mA for 250 MHz,
200 MHz and 167 MHz respectively, changed maximum value of ISB4
parameter from 100 mA to 110 mA for all frequencies).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to respective Thermal Values for all Packages).
Updated Capacitance (Changed values of CIN, CCLK and CI/O parameters to
6.5 pF, 3 pF and 5.5 pF from 5 pF, 5 pF and 7 pF for 100-pin TQFP Package).
Updated Switching Characteristics (Changed maximum value of tCO
parameter from 3.0 ns to 3.2 ns for 200 MHz Speed Bin, changed maximum
value of tDOH parameter from 1.3 ns to 1.5 ns for 200 MHz Speed Bin).
Updated Ordering Information (Added Pb-free information for 100-pin TQFP,
165-ball FBGA and 209-ball FBGA packages).
*B
331778
See ECN
SYT
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 165-ball FBGA and 209-ball FBGA Package as per JEDEC standards).
Updated Pin Definitions.
Updated Operating Range (Added Industrial Temperature Range).
Updated Electrical Characteristics (Updated test conditions for VOL and VOH
parameters, changed maximum value of ISB2 parameter from 100 mA to
120 mA, changed maximum value of ISB4 parameter from 110 mA to 135 mA
respectively).
Updated Capacitance (Changed values of CIN, CCLK and CI/O parameters to
7 pF, 7 pF and 6 pF from 5 pF, 5 pF and 7 pF for 165-ball FBGA Package).
Updated Ordering Information (By shading and unshading MPNs as per
availability).
*C
417547
See ECN
RXU
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 21 (Changed test condition
from VDDQ < VDD to VDDQ  VDD), changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”, changed minimum
value of IX parameter (corresponding to Input current of MODE (Input = VSS))
from –5 A to –30 A, changed maximum value of IX parameter (corresponding
to Input current of MODE (Input = VDD)) from 30 A to 5 A respectively,
changed minimum value of IX parameter (corresponding to Input current of ZZ
(Input = VSS)) from –30 A to –5 A, changed maximum value of IX parameter
(corresponding to Input current of ZZ (Input = VDD)) from 5 A to 30 A
respectively).
Updated Ordering Information (Replaced Package Name column with
Package Diagram in the Ordering Information table).
Updated Package Diagrams.
Document Number: 38-05354 Rev. *J
Page 29 of 31
CY7C1460AV25
CY7C1462AV25
Document History Page (continued)
Document Title: CY7C1460AV25/CY7C1462AV25, 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05354
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
*D
473650
See ECN
VKN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated TAP AC Switching Characteristics (Changed minimm value of tTH and
tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Ordering Information (Updated part numbers).
*E
2898564
03/24/10
NJY
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
*F
3023843
09/28/2010
NJY
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*G
3067448
10/21/2010
NJY
Updated Ordering Information (Updated part numbers).
*H
3342808
08/11/2011
OSN
Updated Package Diagrams.
Updated in new template.
*I
3591743
05/10/2012
*J
3753130
09/24/2012
Document Number: 38-05354 Rev. *J
NJY / PRIT Updated Features (Removed CY7C1464AV25 related information, removed
209-ball FBGA package related information).
Updated Functional Description (Removed CY7C1464AV25 related
information).
Removed Logic Block Diagram – CY7C1464AV25.
Updated Pin Configurations (Removed CY7C1464AV25 related information,
removed 209-ball FBGA package related information).
Updated Pin Definitions.
Updated Functional Overview (Removed CY7C1464AV25 related
information).
Updated Truth Table (Removed CY7C1464AV25 related information).
Removed Partial Write Cycle Description (Corresponding to CY7C1464AV25).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1464AV25 related information, removed 209-ball FBGA package related
information).
Updated Identification Register Definitions (Removed CY7C1464AV25 related
information).
Updated Scan Register Sizes (Removed Bit Size (× 72) column, removed
209-ball FBGA package related information).
Removed Boundary Scan Order (Corresponding to 209-ball FBGA package).
Updated Capacitance (Removed 209-ball FBGA package related information).
Updated Thermal Resistance (Removed 209-ball FBGA package related
information).
Updated Package Diagrams (spec 51-85165 (changed revision from *C to *D),
removed 209-ball FBGA package related information (spec 51-85167)).
PRIT
No technical updates. Completing sunset review.
Page 30 of 31
CY7C1460AV25
CY7C1462AV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical & Image Sensing
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05354 Rev. *J
Revised September 24, 2012
Page 31 of 31
ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned
in this document may be the trademarks of their respective holders.
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