Cypress | CY14B101L | Cypress Semiconductor CY14B101L-SP35XI datasheet: pdf

CY14B101L
1 Mbit (128K x 8) nvSRAM
Features
Functional Description
■
25 ns, 35 ns, and 45 ns access times
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, device pin, or Autostore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Infinite READ, WRITE, and RECALL cycles
■
10 mA typical ICC at 200 ns cycle time
The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology, producing the
world’s most reliable nonvolatile memory. The SRAM provides
infinite read and write cycles, while independent, nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power down. On power
up, data is restored to the SRAM (the RECALL operation) from
the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
■
200, 000 STORE cycles to QuantumTrap
■
20 year data retention at 55°C
■
Single 3V operation +20%, –10%
■
Commercial and industrial temperature
■
SOIC and SSOP packages
■
RoHS compliance
Logic Block Diagram
VCC
QuantumTrap
1024 x 1024
A5
DQ 4
DQ 5
DQ 6
RECALL
STORE/
RECALL
CONTROL
HSB
A15 - A 0
COLUMN IO
INPUT BUFFERS
DQ 2
DQ 3
STATIC RAM
ARRAY
1024 X 1024
SOFTWARE
DETECT
DQ 0
DQ 1
POWER
CONTROL
STORE
ROW DECODER
A6
A7
A8
A9
A 12
A 13
A 14
A 15
A 16
VCAP
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10 A 11
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06400 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 01, 2008
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CY14B101L
Pinouts
Figure 1. Pin Diagram - 32-Pin SOIC
VCAP
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
HSB
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Figure 2. Pin Diagram - 48-Pin SSOP
VCAP
A16
A14
A12
A7
A6
A5
NC
A4
NC
NC
NC
VSS
NC
NC
DQ0
A3
A2
A1
A0
DQ1
DQ2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Top View
(not to scale)
19
20
21
22
23
24
VCC
A15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
HSB
WE
A13
A8
A9
NC
A11
NC
NC
NC
VSS
NC
34
33
32
31
30
29
28
27
26
25
NC
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
Table 1. Pin Definitions
Pin Name
A0 – A16
IO Type
Input
DQ0 – DQ7 Input/Output
Description
Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM.
Bidirectional Data IO Lines. Used as input or output lines, depending on operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE high.
VSS
Ground
Ground for the Device. Must be connected to ground of the system.
VCC
Power Supply Power Supply Inputs to the Device
HSB
Input/Output
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC
No Connect
Hardware Store Busy (HSB). When low, this output indicates a hardware store is in progress. When
pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected. (connection optional)
No Connect. This pin is not connected to the die.
Document Number: 001-06400 Rev. *H
Page 2 of 19
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CY14B101L
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation takes place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a WRITE operation has taken place.
Monitor the HSB signal by the system to detect if an AutoStore
cycle is in progress.
Figure 3. AutoStore Mode
V CC
V CAP
The CY14B101L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0-16 determines which of the 131,072 data bytes are
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of tAA (READ cycle 1). If the
READ is initiated by CE or OE, the outputs are valid at tACE or at
tDOE, whichever is later (READ cycle 2). The data outputs
repeatedly respond to address changes within the tAA access
time, without the need for transitions on any control input pins. It
remains valid until another address change or until CE or OE is
brought HIGH, or WE or HSB is brought LOW.
V CAP
SRAM Read
V CC
0.1UF
The CY14B101L nvSRAM is made up of two functional
components paired in the same physical cell, the SRAM memory
cell, and the nonvolatile QuantumTrap cell. The SRAM memory
cell operates as a standard fast static RAM. Data transfers from
the SRAM to the nonvolatile cell (the STORE operation) or from
the nonvolatile cell to SRAM (the RECALL operation). All cells
stored and recalled in parallel are enabled by this unique
architecture. During the STORE and RECALL operations SRAM
READ and WRITE operations are inhibited. The CY14B101L
supports infinite reads and writes similar to a typical SRAM. It
provides infinite RECALL operations from the nonvolatile cells
and up to 200,000 STORE operations.
section DC Electrical Characteristics on page 6 for the size of
VCAP. The voltage on the VCAP pin is driven to 5V by a charge
pump internal to the chip. A pull up is placed on WE to hold it
inactive during power up.
10k Ohm
Device Operation
WE
SRAM Write
A WRITE cycle is performed whenever CE and WE are low and
HSB is high. The address inputs are stable before entering the
WRITE cycle and must remain stable until either CE or WE goes
high at the end of the cycle.
The data on the common IO pins IO0–7are written into the
memory if the data is valid tSD before the end of a WE controlled
WRITE or before the end of an CE controlled WRITE. Keep the
OE HIGH during the entire WRITE cycle to avoid data bus
contention on common IO lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B101L stores data to nvSRAM using one of the three
storage operations:
1. Hardware Store activated by HSB
2. Software Store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101L.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 3 on page 3 shows the proper connection of the storage
capacitor (VCAP) for automatic store operation. Refer to the
Document Number: 001-06400 Rev. *H
Hardware STORE Operation
The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY14B101L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven low to indicate a busy condition while the STORE (initiated
by any means) is in progress.
SRAM READ and WRITE operations that are in progress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B101L continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it is allowed a time,
tDELAY to complete. However, any SRAM WRITE cycles
requested after HSB goes low are inhibited until HSB returns
HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14B101L continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY14B101L remains disabled until the
HSB pin returns high. Leave the HSB unconnected if is not used.
Page 3 of 19
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CY14B101L
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B101L software STORE
cycle is initiated by executing sequential CE controlled READ
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, further input and
output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If there are intervening
READ or WRITE accesses, the sequence gets aborted and no
STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence is clocked with CE controlled READs or
OE controlled READs. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence, although it is not necessary that OE
is low for the sequence to be valid. After the tSTORE cycle time is
fulfilled, the SRAM is again activated for READ and WRITE
operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations must
be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for READ and WRITE operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 2. Mode Selection
CE
H
WE
X
OE
X
A15 – A0
Mode
IO
Power
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06400 Rev. *H
Page 4 of 19
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CY14B101L
Table 2. Mode Selection (continued)
CE
L
WE
H
OE
L
A15 – A0
Mode
IO
Power
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[1, 2, 3]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[1, 2, 3]
Preventing AutoStore
Noise Considerations
Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, perform the following sequence of
CE controlled READ operations:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
The CY14B101L is a high speed memory, and as a result, has a
high frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals reduces circuit
noise.
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, perform the following sequence of
CE controlled READ operations:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
Low Average Active Power
CMOS technology provides the CY14B101L the benefit of
drawing less current when it is cycled at times longer than 50ns.
Figure 4 shows the relationship between ICC and READ/WRITE
Cycle Time. Worst case current consumption shown for
commercial temperature range VCC is equal to 3.6V, and chip
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn by
the CY14B101L depends on the following items:
1. Duty cycle of chip enable
2. Overall cycle rate for accesses
3. Ratio of READs to WRITEs
4. Operating temperature
5. VCC level
6. IO loading
Figure 4. Current vs. Cycle Time
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Data Protection
The CY14B101L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH. If the CY14B101L is in a WRITE
mode (CE and WE LOW) at power up after a RECALL or after a
STORE, the WRITE is inhibited until a negative transition on CE
or WE is detected.
This protects against inadvertent writes during power up or
brownout conditions.
Document Number: 001-06400 Rev. *H
Page 5 of 19
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CY14B101L
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Surface Mount Lead Soldering
Temperature (three seconds) .................................... +260°C
Storage Temperature .................................. –65°C to +150°C
Output Short Circuit Current [4] .................................... 15 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Latch-up Current.................................................... > 200 mA
Voltage Applied to Outputs
in High Z State ....................................... –0.5V to VCC + 0.5V
Operating Range
Input Voltage.......................................... –0.5V to VCC + 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Range
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.6V
–40°C to +85°C
2.7V to 3.6V
Commercial
Industrial
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V) [5, 6, 7]
Parameter
ICC1
Description
Average VCC Current
Test Conditions
tRC = 25 ns
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
IOUT = 0 mA.
Min
Commercial
Industrial
Max
Unit
65
55
50
mA
mA
mA
55
(tRC = 45 ns)
mA
6
mA
ICC2
Average VCC Current
during STORE
ICC3
Average VCC Current at WE > (VCC – 0.2). All other inputs cycling.
tAA = 200 ns, 3V, 25°C Dependent on output loading and cycle rate.
Values obtained without output loads. IOUT = 0 mA.
Typical
10
mA
ICC4
Average VCAP Current All inputs do not care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
3
mA
ISB
VCC Standby Current
3
mA
IIX
–1
+1
μA
IOZ
Input Leakage Current VCC = Max, VSS < VIN < VCC
Off State Output
VCC = Max, VSS < VIN < VCC, CE or OE > VIH
Leakage Current
–1
+1
μA
VIH
Input HIGH Voltage [7]
2.0
Vcc + 0.3
V
VIL
Input LOW Voltage
Vss – 0.5
0.8
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and VSS, 5V rated
All inputs do not care, VCC = Max
Average current for duration tSTORE
WE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
IOUT = –2 mA
2.4
17
V
0.4
V
120
μF
Notes
4. Outputs shorted for no more than one second. No more than one output shorted at a time.
5. Typical conditions for the active current shown on the front page of the data sheet are average values at 25°C (room temperature) and VCC = 3V. Not 100% tested.
6. The HSB pin has IOUT = –10 μA for VOH of 2.4 V. This parameter is characterized but not tested.
7. VIH changes by 100 mV when VCC > 3.5V.
Document Number: 001-06400 Rev. *H
Page 6 of 19
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CY14B101L
Capacitance
These parameters are guaranteed but not tested.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
7
pF
7
pF
32-SOIC 48-SSOP
Unit
TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V
Thermal Resistance
These parameters are guaranteed but not tested.
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(junction to ambient)
Thermal Resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
TBD
TBD
°C/W
TBD
TBD
°C/W
AC Test Loads
R1 577Ω
R1 577Ω
For Tri-state Specs
3.0V
3.0V
OUTPUT
OUTPUT
30 pF
R2
789Ω
5 pF
R2
789Ω
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% – 90%) ...................... < 5 ns
Input and Output Timing Reference Levels .................... 1.5V
Document Number: 001-06400 Rev. *H
Page 7 of 19
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CY14B101L
AC Switching Characteristics
Parameter
Cypress
Parameter
25 ns Part
35 ns Part
45 ns Part
Description
Alt.
Parameter
Unit
Min
Max
Min
Max
Min
Max
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
tRC
[9]
tRC
Read Cycle Time
tAA
[10]
tAA
Address Access Time
25
35
45
ns
tOE
Output Enable to Data Valid
12
15
20
ns
tDOE
25
25
35
35
45
45
ns
ns
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE
[11]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE
[11]
tHZ
Chip Disable to Output Inactive
tLZOE
[11]
tOLZ
Output Enable to Output Active
tHZOE [11]
tOHA
tOHZ
Output Disable to Output Inactive
tPU
[8]
tPA
Chip Enable to Power Active
tPD
[8]
tPS
Chip Disable to Power Standby
10
0
13
0
10
0
15
0
13
0
25
ns
15
0
35
ns
ns
ns
45
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
25
35
45
ns
tPWE
tWP
Write Pulse Width
20
25
30
ns
tSCE
tCW
Chip Enable to End of Write
20
25
30
ns
tSD
tDW
Data Setup to End of Write
10
12
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
ns
tAW
tAW
Address Setup to End of Write
20
25
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
0
0
ns
tHZWE [11, 12] tWZ
tLZWE
[11]
tOW
Write Enable to Output Disable
Output Active after End of Write
10
3
13
3
15
3
ns
ns
Notes
8. These parameters are guaranteed but not tested.
9. WE is HIGH during SRAM read cycles.
10. Device is continuously selected with CE and OE low.
11. Measured ± 200 mV from steady state output voltage.
12. If WE is low when CE goes low, the outputs remain in the high impedance state.
Document Number: 001-06400 Rev. *H
Page 8 of 19
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CY14B101L
AutoStore or Power Up RECALL
Parameter
tHRECALL [13]
tSTORE
[14, 15]
CY14B101L
Description
Min
Unit
Max
Power Up RECALL Duration
20
ms
STORE Cycle Duration
12.5
ms
VSWITCH
Low Voltage Trigger Level
2.65
V
tVCCRISE
VCC Rise Time
μs
150
Software Controlled STORE/RECALL Cycles [16, 17, 18]
25 ns Part
Parameter
35 ns Part
45 ns Part
Description
Unit
Min
Max
Min
Max
Min
Max
tRC
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tAS
Address Setup Time
0
0
0
ns
tCW
Clock Pulse Width
20
25
30
ns
tGHAX
Address Hold Time
1
1
1
ns
tRECALL
RECALL Duration
50
50
50
μs
Soft Sequence Processing Time
70
70
70
μs
tSS
[19, 20]
Hardware STORE Cycle
CY14B101L
Parameter
Description
Unit
Min
Max
70
tDELAY [21]
Time Allowed to Complete SRAM Cycle
1
tHLHX
Hardware STORE Pulse Width
15
μs
ns
Notes
13. tHRECALL starts from the time VCC rises above VSWITCH.
14. If an SRAM write has not taken place since the last nonvolatile cycle, no STORE takes place.
15. Industrial grade devices require 15 ms max.
16. The software sequence is clocked with CE controlled or OE controlled READs.
17. The six consecutive addresses are read in the order listed in the Table 2 on page 4. WE is HIGH during all six consecutive cycles.
18. A 600Ω resistor must be connected to HSB to use the software command.
19. This is the amount of time it takes to take action on a soft sequence command. Vcc power remains HIGH to effectively register the command.
20. Commands such as STORE and RECALL lock out IO until operation is complete, which further increases this time. See the specific command.
21. READ and WRITE cycles in progress before HSB are given this amount of time to complete.
Document Number: 001-06400 Rev. *H
Page 9 of 19
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CY14B101L
Switching Waveforms
Figure 5. SRAM Read Cycle 1 (address controlled) [9, 10, 22]
tRC
ADDRESS
t AA
t OHA
DQ (DATA OUT)
DATA VALID
Figure 6. SRAM Read Cycle 2 (CE and OE controlled) [9, 22]
tRC
ADDRESS
tLZCE
CE
tACE
tPD
tHZCE
OE
tLZOE
DQ (DATA OUT)
t PU
ICC
tHZOE
tDOE
DATA VALID
ACTIVE
STANDBY
Note
22. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-06400 Rev. *H
Page 10 of 19
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CY14B101L
Switching Waveforms (continued)
Figure 7. SRAM Write Cycle 1 (WE controlled) [22, 23]
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tSD
tHD
DATA VALID
DATA IN
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
Figure 8. SRAM Write Cycle 2 (CE controlled)
tWC
ADDRESS
CE
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Note
23. CE or WE must be > VIH during address transitions.
Document Number: 001-06400 Rev. *H
Page 11 of 19
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CY14B101L
Switching Waveforms (continued)
Figure 9. AutoStore or Power Up RECALL
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
Figure 10. CE Controlled Software STORE/RECALL Cycle [17]
tRC
tSCE
ADDRESS # 6
ttGHAX
GLAX
OE
a
a
a
a
a
a
a
a
tSA
CE
a
a
a a
ADDRESS # 1
ADDRESS
tRC
DQ (DATA)
DATA VALID
Document Number: 001-06400 Rev. *H
a
a
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Page 12 of 19
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CY14B101L
Switching Waveforms (continued)
Figure 11. OE Controlled Software STORE/RECALL Cycle [17]
tRC
ADDRESS # 1
ADDRESS
CE
tSA
ADDRESS # 6
tSCE
OE
t STORE / t RECALL
DQ (DATA)
a
a
ttGLAX
GHAX
DATA VALID
DATA VALID
a
a
a
a
a
a
a
a
a
a
a a
tRC
HIGH IMPEDANCE
Figure 12. Hardware STORE Cycle
a
a
tHLHX
HSB (IN)
tSTORE
HSB (OUT)
a
a
tHLBL
HIGH IMPEDANCE
HIGH IMPEDANCE
a
a
t DELAY
DATA VALID
DQ (DATA OUT)
DATA VALID
Figure 13. Soft Sequence Processing [19, 20]
ADDRESS # 1
ADDRESS # 6
34
t SS
Soft Sequence Command
ADDRESS # 1
a
a
ADDRESS
a
a
Soft Sequence Command
34
t SS
ADDRESS # 6
VCC
Document Number: 001-06400 Rev. *H
Page 13 of 19
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CY14B101L
Part Numbering Nomenclature
CY 14 B 101 L - SZ 25 X C T
Option
T - Tape and Reel
Blank - Std.
Temperature
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
Package
SZ - 32 SOIC
SP - 48 SSOP
Speed
25 - 25 ns
35 - 35 ns
45 - 45 ns
Data Bus
L - x8
Density
101 - 1 Mb
Voltage
B - 3.0V
NVSRAM
14 - AutoStore + Software Store + Hardware Store
Cypress
Document Number: 001-06400 Rev. *H
Page 14 of 19
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CY14B101L
Ordering Information
The following parts are all Pb-free. Shaded areas contain advance information. Contact your local Cypress sales representative for
availability of these parts.
Speed (ns)
25
25
35
35
45
45
Ordering Code
Package Diagram
Package Type
CY14B101L-SZ25XCT
51-85127
32-pin SOIC
CY14B101L-SP25XCT
51-85061
48-pin SSOP
CY14B101L-SZ25XC
51-85127
32-pin SOIC
CY14B101L-SP25XC
51-85061
48-pin SSOP
CY14B101L-SZ25XIT
51-85127
32-pin SOIC
CY14B101L-SP25XIT
51-85061
48-pin SSOP
CY14B101L-SZ25XI
51-85127
32-pin SOIC
CY14B101L-SP25XI
51-85061
48-pin SSOP
CY14B101L-SZ35XCT
51-85127
32-pin SOIC
CY14B101L-SP35XCT
51-85061
48-pin SSOP
CY14B101L-SZ35XC
51-85127
32-pin SOIC
CY14B101L-SP35XC
51-85061
48-pin SSOP
CY14B101L-SZ35XIT
51-85127
32-pin SOIC
CY14B101L-SP35XIT
51-85061
48-pin SSOP
CY14B101L-SZ35XI
51-85127
32-pin SOIC
CY14B101L-SP35XI
51-85061
48-pin SSOP
CY14B101L-SZ45XCT
51-85127
32-pin SOIC
CY14B101L-SP45XCT
51-85061
48-pin SSOP
CY14B101L-SZ45XC
51-85127
32-pin SOIC
CY14B101L-SP45XC
51-85061
48-pin SSOP
CY14B101L-SZ45XIT
51-85127
32-pin SOIC
CY14B101L-SP45XIT
51-85061
48-pin SSOP
CY14B101L-SZ45XI
51-85127
32-pin SOIC
CY14B101L-SP45XI
51-85061
48-pin SSOP
Document Number: 001-06400 Rev. *H
Operating Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 15 of 19
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CY14B101L
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC
PIN 1 ID
16
1
REFERENCE JEDEC MO-119
0.405[10.287]
0.419[10.642]
17
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.292[7.416]
0.299[7.594]
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
32
SEATING PLANE
0.810[20.574]
0.822[20.878]
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.050[1.270]
TYP.
0.026[0.660]
0.032[0.812]
0.014[0.355]
0.020[0.508]
0.004[0.101]
0.0100[0.254]
0.021[0.533]
0.041[1.041]
0.006[0.152]
0.012[0.304]
51-85127 *A
Document Number: 001-06400 Rev. *H
Page 16 of 19
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CY14B101L
Package Diagrams (continued)
Figure 15. 48-Pin Shrunk Small Outline Package
51-85061 *C
Document Number: 001-06400 Rev. *H
Page 17 of 19
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CY14B101L
Document History Page
Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM
Document Number: 001-06400
REV.
ECN
Orig. of
Change
Submission
Date
Description of Change
**
425138
TUP
New data sheet
*A
437321
TUP
Show data sheet on External Web
*B
471966
TUP
Changed ICC3 from 5 mA to 10 mA
Changed ISB from 2 mA to 3 mA
Changed VIH(min) from 2.2V to 2.0V
Changed tRECALL from 40 μs to 50 μs
Changed Endurance from 1 million Cycles to 500K Cycles
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
*C
503272
PCI
Changed from Advance to Preliminary
Changed the term “Unlimited” to “Infinite”
Changed Endurance from 500K Cycles to 200K Cycles
Added temperature specification to Data Retention - 20 years at 55°C
Removed Icc1 values from the DC table for 25 ns and 35 ns industrial
grade
Changed Icc2 value from 3 mA to 6 mA in the DC table
Added a footnote on VIH
Changed VSWITCH(min) from 2.55V to 2.45V
Added footnote 17 related to using the software command
Updated Part Nomenclature Table and Ordering Information Table
*D
597002
TUP
Removed VSWITCH(min) specification from the AutoStore/Power Up RECALL table
Changed tGLAX specification from 20 ns to 1 ns
Added tDELAY(max) specification of 70 μs in the hardware STORE cycle
table
Removed tHLBL specification
Changed tSS specification from 70 μs (min) to 70 μs (max)
Changed VCAP(max) from 57 μF to 120 μF
*E
688776
VKN
Added footnote related to HSB
Changed tGLAX to tGHAX
*F
1349963
UHA/SFV
*G
2427986
GVCH
*H
2546756
GVCH/AESA
Document Number: 001-06400 Rev. *H
Changed from Preliminary to Final
Updated Ordering Information Table
Move to external web
08/01/2008
Aligned part number nomenclature
Corrected typo in ordering information
Changed pin definition of NC pin
Updated data sheet template
Page 18 of 19
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CY14B101L
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC Solutions
PSoC
psoc.cypress.com
Clocks & Buffers
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
image.cypress.com
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06400 Rev. *H
Revised August 01, 2008
Page 19 of 19
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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