Aptio 5.x Status Codes

Checkpoints & Beep Codes for Debugging

Document Revision 2.03

Revision Date: July 10th, 2015

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Aptio 5.x Status Codes

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Table of Contents

DOCUMENT INFORMATION ....................................................................................................................................... 4

P

URPOSE

........................................................................................................................................................................... 4

A

UDIENCE

......................................................................................................................................................................... 4

R

EFERENCES

....................................................................................................................................................................... 4

C

HANGE

H

ISTORY

............................................................................................................................................................... 4

CONCEPT & DESIGN ................................................................................................................................................... 5

I

NTRODUCTION

................................................................................................................................................................... 5

A

PTIO

B

OOT

F

LOW

............................................................................................................................................................. 5

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Aptio 5.x Status Codes

V

IEWING

C

HECKPOINTS

........................................................................................................................................................ 5

APTIO CHECKPOINTS .................................................................................................................................................. 7

C

HECKPOINT

R

ANGES

.......................................................................................................................................................... 7

S

TANDARD

C

HECKPOINTS

..................................................................................................................................................... 7

SEC Phase ................................................................................................................................................................... 7

SEC Beep Codes .......................................................................................................................................................... 8

PEI Phase .................................................................................................................................................................... 8

PEI Beep Codes ......................................................................................................................................................... 10

DXE Phase ................................................................................................................................................................ 10

DXE Beep Codes ....................................................................................................................................................... 13

ACPI/ASL Checkpoints .............................................................................................................................................. 13

OEM-R

ESERVED

C

HECKPOINT

R

ANGES

................................................................................................................................. 13

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Aptio 5.x Status Codes

Document Information

Purpose

This document lists standard checkpoint codes and beep codes generated by Aptio 5.x core firmware.

The checkpoint and beep codes defined in this document are inherent to the Aptio 5.x generic core, and do not include any chipset specific, board specific, or OEM specific code definitions.

Audience

The intended audiences are Generic Chipset Porting Engineers, OEM Porting Engineers, Technicians, and AMI Customers.

References

AMI Debug Rx product page

AMI Debug Rx User Manual

AMI Debug Rx Quick Start Guide

Change History

Date

2014-4-10

2014-8-01

2015-5-13

2015-7-10

Revision

2.00

2.01

2.02

2.03

Description

Converted from Aptio 4.

Updated some definitions of Beep Codes



Updated some definitions of Beep Codes



Concept & Design Section is updated

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Aptio 5.x Status Codes

Concept & Design

Introduction

A status code is a data value used to provide diagnostic information about the boot process. Progress codes are status codes that signify successful progression to a following initialization step. Error codes signify error conditions encountered in the process of system initialization.

Aptio 5.x core can be configured to send status codes to a variety of sources. The two most commonly used types of status codes are checkpoint codes and beep codes.

Checkpoint codes are byte length data values. Checkpoints are typically output to I/O port 80h, but Aptio

5.x core can be configured to send checkpoints to a variety of sources. Aptio 5.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing.

Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process on production hardware.

Beep code is a series of short sound signals. Beep codes are typically error codes that do not occur during normal boot process.

Note: Beep codes are not the only sounds generated during the boot process. Some firmware components may use sounds to notify user about other events such as detection of a hot-pluggable device. These sounds are typically generated using a frequency that is different from the frequency of the beep codes.

Aptio Boot Flow

Aptio 5.x core follows the firmware model described by the UEFI Platform Initialization Specification (PI).

The PI Specification refers the following “boot phases”, which may apply to various checkpoint and beep code descriptions:

Security (SEC)

– initial low-level initialization

Pre-EFI Initialization (PEI)

– memory initialization

1

Driver Execution Environment (DXE)

– main hardware initialization

2

Boot Device Selection (BDS)

– system setup, pre-OS user interface & selecting a bootable device

(CD/DVD, HDD, USB, Network, Shell, …)

Viewing Checkpoints

Checkpoints generated by Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a “POST Card” or “POST Diagnostic

Card”. These PCI add-in cards show the value of I/O port 80h on a LED display. Checkpoint cards are available through a variety of computer mailorder outlets.

1

Analogous to “bootblock” functionality of legacy BIOS

2

Analogou s to “POST” functionality in legacy BIOS

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Aptio 5.x Status Codes designed for BIOS developers.

Newer systems feature support for AMI Debug Rx , a USB connected alternative to the PCI POST

Card. AMI Debug Rx is a low-cost debug tool built around the debug port feature common to today’s

USB 2.0 EHCI controllers.

AMI Debug Rx is designed as replacement for the

PCI POST Checkpoint Card as newer systems omit

PCI expansion slots. Along with checkpoints, AMI

Debug Rx has a number of features specifically

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Aptio 5.x Status Codes

Aptio Checkpoints

Checkpoint Ranges

Status Code Range

0x01

– 0x0B

0x0C

– 0x0F

0x10

– 0x2F

0x30

– 0x4F

0x50

– 0x5F

0x60

– 0x8F

0x90

– 0xCF

0xD0

– 0xDF

0xE0

– 0xE8

0xE9

– 0xEF

0xF0

– 0xF8

0xF9

– 0xFF

Description

SEC execution

SEC errors

PEI execution up to and including memory detection

PEI execution after memory detection

PEI errors

DXE execution up to BDS

BDS execution

DXE errors

S3 Resume (PEI)

S3 Resume errors (PEI)

Recovery (PEI)

Recovery errors (PEI)

Standard Checkpoints

SEC Phase

Status Code Description

0x00

Progress Codes

Not used

0x01

0x02

0x03

0x04

Power on. Reset type detection (soft/hard).

AP initialization before microcode loading

North Bridge initialization before microcode loading

South Bridge initialization before microcode loading

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

OEM initialization before microcode loading

Microcode loading

AP initialization after microcode loading

North Bridge initialization after microcode loading

South Bridge initialization after microcode loading

OEM initialization after microcode loading

Cache initialization

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Aptio 5.x Status Codes

SEC Error Codes

0x0C

– 0x0D Reserved for future AMI SEC error codes

0x0E

0x0F

Microcode not found

Microcode not loaded

SEC Beep Codes

None

PEI Phase

Status Code Description

Progress Codes

0x10 PEI Core is started

0x11

0x12

0x13

0x14

Pre-memory CPU initialization is started

Pre-memory CPU initialization (CPU module specific)

Pre-memory CPU initialization (CPU module specific)

Pre-memory CPU initialization (CPU module specific)

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x15

0x16

0x17

0x18

Pre-memory North Bridge initialization is started

Pre-Memory North Bridge initialization (North Bridge module specific)

Pre-Memory North Bridge initialization (North Bridge module specific)

Pre-Memory North Bridge initialization (North Bridge module specific)

0x19

0x1A

Pre-memory South Bridge initialization is started

Pre-memory South Bridge initialization (South Bridge module specific)

0x1B Pre-memory South Bridge initialization (South Bridge module specific)

0x1C Pre-memory South Bridge initialization (South Bridge module specific)

0x1D

– 0x2A OEM pre-memory initialization codes

0x2B

0x2C

0x2D

Memory initialization. Serial Presence Detect (SPD) data reading

Memory initialization. Memory presence detection

Memory initialization. Programming memory timing information

Memory initialization. Configuring memory

Memory initialization (other).

Reserved for ASL (see ASL Status Codes section below)

Memory Installed

CPU post-memory initialization is started

CPU post-memory initialization. Cache initialization

CPU post-memory initialization. Application Processor(s) (AP) initialization

CPU post-memory initialization. Boot Strap Processor (BSP) selection

CPU post-memory initialization. System Management Mode (SMM) initialization

Post-Memory North Bridge initialization is started

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Aptio 5.x Status Codes

0x38

0x39

0x3A

0x3B

0x3C

Post-Memory North Bridge initialization (North Bridge module specific)

Post-Memory North Bridge initialization (North Bridge module specific)

Post-Memory North Bridge initialization (North Bridge module specific)

Post-Memory South Bridge initialization is started

Post-Memory South Bridge initialization (South Bridge module specific)

0x3D

0x3E

Post-Memory South Bridge initialization (South Bridge module specific)

Post-Memory South Bridge initialization (South Bridge module specific)

0x3F-0x4E OEM post memory initialization codes

0x4F DXE IPL is started

PEI Error Codes

0x50 Memory initialization error. Invalid memory type or incompatible memory speed

0x51

0x52

Memory initialization error. SPD reading has failed

Memory initialization error. Invalid memory size or memory modules do not match.

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

Memory initialization error. No usable memory detected

Unspecified memory initialization error.

Memory not installed

Invalid CPU type or Speed

CPU mismatch

CPU self test failed or possible CPU cache error

CPU micro-code is not found or micro-code update is failed

Internal CPU error

0x5B

0x5C reset PPI is not available

PEI phase BMC self-test failure

0x5C-0x5F Reserved for future AMI error codes

S3 Resume Progress Codes

0xE0

0xE1

0xE2

S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)

S3 Boot Script execution

Video repost

0xE3 OS S3 wake vector call

0xE4-0xE7 Reserved for future AMI progress codes

S3 Resume Error Codes

0xE8 S3 Resume Failed

0xE9 S3 Resume PPI not Found

0xEA

0xEB

S3 Resume Boot Script Error

S3 OS Wake Error

0xEC-0xEF Reserved for future AMI error codes

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Aptio 5.x Status Codes

Recovery Progress Codes

0xF0

0xF1

0xF2

0xF3

Recovery condition triggered by firmware (Auto recovery)

Recovery condition triggered by user (Forced recovery)

Recovery process started

Recovery firmware image is found

0xF4 Recovery firmware image is loaded

0xF5-0xF7 Reserved for future AMI progress codes

Recovery Error Codes

0xF8 Recovery PPI is not available

0xF9 Recovery capsule is not found

0xFA Invalid recovery capsule

0xFB

– 0xFF Reserved for future AMI error codes

PEI Beep Codes

# of Beeps Description

4

4

7

1

2

3

Memory not installed

Recovery started

Typically for development use.

The beep code is generated when DXEIPL PPI or DXE Core is not found.

Recovery failed

S3 Resume failed

Typically for development use.

The beep code is generated when platform cannot be reset because reset PPI is not available.

DXE Phase

Status Code Description

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

DXE Core is started

NVRAM initialization

Installation of the South Bridge Runtime Services

CPU DXE initialization is started

CPU DXE initialization (CPU module specific)

CPU DXE initialization (CPU module specific)

CPU DXE initialization (CPU module specific)

CPU DXE initialization (CPU module specific)

PCI host bridge initialization

North Bridge DXE initialization is started

North Bridge DXE SMM initialization is started

North Bridge DXE initialization (North Bridge module specific)

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Aptio 5.x Status Codes

0x6C

0x6D

0x6E

0x6F

0x70

North Bridge DXE initialization (North Bridge module specific)

North Bridge DXE initialization (North Bridge module specific)

North Bridge DXE initialization (North Bridge module specific)

North Bridge DXE initialization (North Bridge module specific)

South Bridge DXE initialization is started

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

South Bridge DXE SMM initialization is started

South Bridge devices initialization

South Bridge DXE Initialization (South Bridge module specific)

South Bridge DXE Initialization (South Bridge module specific)

South Bridge DXE Initialization (South Bridge module specific)

South Bridge DXE Initialization (South Bridge module specific)

South Bridge DXE Initialization (South Bridge module specific)

ACPI module initialization

0x79 CSM initialization

0x7A

– 0x7F Reserved for future AMI DXE codes

0x80

– 0x8F OEM DXE initialization codes

0x90 Boot Device Selection (BDS) phase is started

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

Driver connecting is started

PCI Bus initialization is started

PCI Bus Hot Plug Controller Initialization

PCI Bus Enumeration

PCI Bus Request Resources

PCI Bus Assign Resources

Console Output devices connect

Console input devices connect

0x99

0x9A

0x9B

Super IO Initialization

USB initialization is started

USB Reset

0x9C USB Detect

0x9D USB Enable

0x9E

– 0x9F Reserved for future AMI codes

0xA0

0xA1

IDE initialization is started

IDE Reset

0xA2

0xA3

0xA4

0xA5

0xA6

IDE Detect

IDE Enable

SCSI initialization is started

SCSI Reset

SCSI Detect

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Aptio 5.x Status Codes

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

SCSI Enable

Setup Verifying Password

Start of Setup

Reserved for ASL (see ASL Status Codes section below)

Setup Input Wait

Reserved for ASL (see ASL Status Codes section below)

Ready To Boot event

Legacy Boot event

Exit Boot Services event

Runtime Set Virtual Address MAP Begin

Runtime Set Virtual Address MAP End

Legacy Option ROM Initialization

System Reset

0xB4

0xB5

USB hot plug

PCI bus hot plug

0xB6 Clean-up of NVRAM

0xB7 Configuration Reset (reset of NVRAM settings)

0xB8

– 0xBF Reserved for future AMI codes

0xC0

– 0xCF OEM BDS initialization codes

DXE Error Codes

0xD0 CPU initialization error

North Bridge initialization error

South Bridge initialization error

Some of the Architectural Protocols are not available

PCI resource allocation error. Out of Resources

No Space for Legacy Option ROM

No Console Output Devices are found

No Console Input Devices are found

Invalid password

Error loading Boot Option (LoadImage returned error)

Boot Option is failed (StartImage returned error)

Flash update is failed

Reset protocol is not available

DXE phase BMC self-test failure

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Aptio 5.x Status Codes

DXE Beep Codes

# of Beeps Description

1 Invalid password

4

5

Typically for development use.

The beep code is generated when some of the Architectural Protocols are not available.

No Console Input or Output Devices are found

1,2

6 Flash update is failed

7

8

Typically for development use.

The beep code is generated when platform cannot be reset because reset protocol is not available.

Platform PCI resource requirements cannot be met

1

Note serial console redirection is considered a console out device if enabled

2

Note serial console redirection is considered a console in device if enabled. Also, depending on configuration PS/2 driver may always report a console in device even if one is not connected.

ACPI/ASL Checkpoints

Status Code Description

0x01

0x02

0x03

0x04

0x05

0x10

0x20

0x30

0x40

0xAC

0xAA

System is entering S1 sleep state

System is entering S2 sleep state

System is entering S3 sleep state

System is entering S4 sleep state

System is entering S5 sleep state

System is waking up from the S1 sleep state

System is waking up from the S2 sleep state

System is waking up from the S3 sleep state

System is waking up from the S4 sleep state

System has transitioned into ACPI mode. Interrupt controller is in PIC mode.

System has transitioned into ACPI mode. Interrupt controller is in APIC mode.

OEM-Reserved Checkpoint Ranges

Status Code Description

0x05 OEM SEC initialization before microcode loading

0x0A OEM SEC initialization after microcode loading

0x1D

– 0x2A OEM pre-memory initialization codes

0x3F

– 0x4E OEM PEI post memory initialization codes

0x80

– 0x8F OEM DXE initialization codes

0xC0

– 0xCF OEM BDS initialization codes

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