通訊多媒體核心設計 (Multimedia Communication IP Design) 課程目標

通訊多媒體核心設計
(Multimedia Communication IP
Design)
蔡宗漢
(Tsung-Han Tsai)
Dept. of E.E., N.C.U.
課程目標
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Realize the various SOC and IP Design concepts,
their related SOC design flow. Using these
concepts to design the actual IP core targeting for
some communication and multimedia application.
Realize the multimedia communication system.
Realize the know-how of the system architecture
design.
Driving the students to attend the IP contest.
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內容綱要
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Introduction to IP and SoC
IP Core Design Flow
Algorithm and Architecture Explorations
VCI Standard and On-chip Bus
Communication System IP core design
Multimedia System realization
Audio IP core design
Video IP core design
Term Project case design
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Grading & Textbook
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Homework & Class Participation : 30%
Architecture Discussion and Mid-term Report: 20%
Term Project and Presentation: 50%
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(Materials):
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Handouts
Papers
(References):
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Image and Video Compression Standards (authors: K. Konstantinides)
Digital Signal Processing for Multimedia Systems (authors: K. K. Parhi)
Reuse Methodology Manual for System-On-A-Chip Designs by
Michael Keating, Pierre Bricaud (Hardcover - June 1999)
DSP Integrated Circuit (author: Lars Wanhammar)
VLSI Digital Signal Processing Systems(author: Keshab K. Parhi)
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Term Project
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Discuss and implement one of the related design discussed
in our lecture.
The term project result should be nearly a Soft IP.
Each team can have 2 members. “Everyone” should present
in oral.
A Homepage for your result is required.
FPGA prototype implementation is recommended.
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先修課程
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VLSI Design
Cell-based Design Flow
HDL (Verilog, VHDL) Training
FPGA Design Flow
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3
Agenda
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Overview of SOC
Reuse Methodology Manual (RMM) for SOC
Digital IP Authoring
RTL Coding Guideline
SOC and IP Core Design
Embedded CPU Design
Hardware/Software Co-Design
Low Power Design Issue
IP Design for Algorithm and Architecture Exploration
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Overview of SOC
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Technology Trend in Microelectronics
SOC Design Strategy
SOC Design Challenge
Reusable IP Methodology
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Semiconductor Industry De-integration
Example: Telecommunications IC
Vertically Integrated Companies Replaced by
“ Horizontal” Experts
Possible Supply Chain Flow
c System Specification
e
d IC Design
c
d
e IP Sourcing
UMC, Japan
UMC, Taiwan
f Manufacturing
fg
f
g Assembly / Test
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Dis-integration of the IC Industry
IDM/ASIC
IDM/ASIC
System Co.
Fabless Co.
Fabless Co.
System
System
Design
Design
IC
ICDesign
Design
System
System
Design
Design
ICICDesign
Design
System
System
Design
Design
IC
ICDesign
Design
IP
IP
IC
IC
Design
Design
Fab
Fab
Fab
Fab
Assembly
Assembly
&&Test
Test
System
System
Design
Design
System
System
Design
Design
IC
IC
Design
Design
Design
Design
Foundry
Foundry
(Design Service)
(Design Service)
Foundry
Foundry
Contract
Contract
Assembly
Assembly
&&Test
Test
Assembly
Assembly
&&Test
Test
Assembly
Assembly
&&Test
Test
After 2000
1990 s
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Wafer
Foundry
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Source: TSMC 2000 Technology Symposium
5
Accelerating Technology and
Complexity
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Moore’s Law: Driving Advances
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Logic capacity doubles per IC every 18 months
(1975)
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Silicon Process Roadmaps
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Technology Migration Influence
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Low Cost
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A transistor cost $30 in 1960
8080 (5,000 tx) cost $150 in 1974
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Pentium-II (7,500,000 tx) cost $225 in 1997
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3 cents/tx
0.003 cents/tx
1,000 fold decrease from 1960 to 1974
1,000,000 fold decrease from 1960 to 1997
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System Revolution
1999-2000
Discrete Component Era
LSI/VLSI Era
SOC/SLI Era
Mainframe Era
PC Era
Post PC Era
Mainframe Computer
PC
IA
Internet Appliance
Information Appliance
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Technology Convergence It’s a convergence world !
Centralized
Computing
Personal
Computing
Host-based
Network
Client-Server
Network
Network-Centric
Computing
Mainframe/Minicomputer
Computer
WAN/
Data Comm.
LAN
SPC
IN
Consumer
Electronics
Telephone
with S/W
(Switch)
Analog-based/
Broadcast
TV, VCR, ...
Comm.
Very little
Multimedia
MPEG-II
Computer
Computer
Consumer
Electronics
CATV
Information
Network
Digital TV
Computer
Comm.
Internet/Intranet
Comm.
Consumer
Electronics
Video phone/
conferencing
Comm.
Consumer
Electronics
We
We are
are here
here
Digital Convergence heading
to
Digital Revolution
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Overview of SOC
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Technology Trend in Microelectronics
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SOC Design Strategy
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SOC Design Challenge
Reusable IP Methodology
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What does SOC contains
DES-PRO, DES-CORE, Concatenated CODEC,
Reed-Solomon CODEC, Viterbi CODEC
PLL
ADC
DAC
BadgapV
C25, C50, FFT/IFFT,
FIR, RRS, DDS, NCO,
ADSP
DSP
10/100 MAC
Gigabit MAC
10/100 PHY
ATM SAR, T1/E1, HDLC,
ISDN, X50
Network
Encryption, FEC
Peripheral:Controller, DMA, Timer,
CRT, RTC, PIC, PPI, UART,
Floppy/Tape Control
Bus
Interface
PCMCIA
SCSI
1284
I2C
USB
Consumer
Mi
xe
d
CPU/MCU
ARM
MIPS
6502
Z80
8042/48
8051/52
XA16
80/86186
DCT,QAM,QPSK, MPEG2, NTSC/PAL Encoder, DVD, DVB,
Speech Codecs
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SOC Technology Improvement
Physical Component
IP or Function Block
System Board
System Chip
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SOC Market Potential
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Grow to 4.4 B in 2000
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Primary market in cost reduction segment
Predominant 90% in wireless market
SOC has out paced ASIC market by 10%
Reach 11.4 B in 2003
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Over 50% growth in 2002 and 2003
Significant growth in high performance SOC
More ASIC will port into SOC
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Where SOC Goes To ?
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The Design Productivity Gap
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Customization and Short Product
Life
Complex Design Work
Short Design Cycle
Brain Power
Design Power
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VLSI Design Trends
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Handset silicon
1999
20 + discretes
1996
INTEGRATED PROCESSOR FILTER
LNA &MIXER
FILTER
ASIC
(includes
DSP)
2000+?
<10 discretes
50 + discretes
BB
MCU
PA
MIXER
Baseband
RF
RF/IF
LNA
MEMORY
DSP
PA
RF/IF
Baseband
1993
Baseband
1/0
RF/IF
2000+?
150 + discretes
Multichip BB packages now available from
vendors
2 chip/1 chip mixed signal solutions now
foreseeable
CODEC
MCU
VPC
BB &
RF
PA
MEMORY
Baseband
RF/IF
Baseband
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RF/IF
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SOC Example:
Bluetooth Block Schematic
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Bluetooth SOC Microphotograph
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SOC Example:
Motion Engine in PS2
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SOC Example:
Transceiver IC Block Diagram
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Chip Photograph
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SOC Application Product
Reconfigurable Baseband Processor for Wireless
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RMM2
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Reuse Methodology Manual For System-on-a-Chip
Designs, 2nd Edition
by Michael Keating, Synopsys Inc., USA
and Pierre Bricaud, Mentor Graphics Corporation, USA
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Provides designers with detailed guidelines on
planning, specifications, design practices, coding,
testing and documentation for creating reusable IP
Broadly accepted by SoC Industry
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RMM2 - Table of Contents
1. Introduction.
2. The System-on-a-Chip Design Process.
3. System-Level Design Issues: Rules and Tools.
4. The Macro Design Process.
5. RTL Coding Guidelines.
6. Macro Synthesis Guidelines.
7. Macro Verification Guidelines.
8. Developing Hard Macros.
9. Macro Deployment: Packaging for Reuse.
10. System Integration with Reusable Macros.
11. System-Level Verification Issues.
12. Data and Project Management.
13. Implementing a Reuse Process.
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SOC Definition
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“RMM” defines a SOC design should consists of:
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A microprocessor and its memory system
A datapath that includs interfaces to the external system
(DSP?)
Blocks that perform transformations on data received
from the external system (ADC/DAC)
Another I/O interface to the external system
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Surviving the SOC Revolution
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A guide to Platform-based Design
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by Henry Chang, Larry Cooke, Merrill Hunt, Grant Martin,
and McNelly, Andrew McNelly, Lee Todd
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Surviving the SOC Revolution Table of Contents
1. Moving to System-on-Chip Design.
2. Overview of the SOC Design Process.
3. Integration Platforms and SOC Design.
4. Function-Architecture Co-Design.
5. Designing Communications Networks.
6. Developing an Integration Platform.
7. Creating Derivative Designs.
8. Analog/Mixed-Signal in SOC Design.
9. Software Design in SOCs.
10. In Conclusion.
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SOC Definition
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“Surviving the SOC Revolution” defines a SOC as a
complex IC that integrates the major functional
elements of a complete end-product into a single
chip or chipset
The SOC design typically incorporates
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Programmable processor
On-chip memory
H/W accelerating function units (DSP)
Peripheral interfaces
Embedded software
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SOC Definition - generally heard
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SOC = CPU + embedded memory + I/O
SOC = DSP + memory + AMS blocks
SOC = integration of pre-verified chips
The IC products designed by our company is definitely
SOCs
Most likely SOC stands for system-on-chip
Typically SOC has the same meaning of system level
integration (SLI)
System chips integration
Must integrate optical devices or micro mechanical devices
Bio-chips
...
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SOC Definition - in my view point
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Include the Heterogeneity chip design cores --> C
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Need integration --> O
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Need a system requirement and/or demand --> S
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Overview of SOC
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Technology Trend in Microelectronics
SOC Design Strategy
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SOC Design Challenge
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Reusable IP Methodology
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Services to Enable Successful SOC
Design
IP Block Design Flow
System
Synth
Verify
Test
Layout
Design Reuse
Methodology
Customized
Flows
SoC
Design & Verification
Assistance
IP & Libraries
RISC
DSP
Core
Core
CACHE
Glue
PLL
Secur it y
En cr yption
Third Party
IP
EEPROM
Logic
Digital
Mod/De-mod
DRAM
DSP
Blocks
I/O
Interfaces
PIO
RTC
DMA
USB
1394
PCI
Protocol
Decoder
D AC
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RAM
FLASH
ROM
A/D
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A Quadruple Challenges in SOC
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Design Challenges - Silicon
Complexity
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Large numbers of interacting devices and
interconnects
Power and current management: voltage scaling
Need for new logic families to meet performance
challenges
New interconnect and substrate technologies
(such as copper, low k dielectric, SOI and SiGe)
Deep Sub-Micron design issue
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Design Challenge - System
Heterogeneity
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Embedded software as a key design problem
SOC design with a diversity of design styles
(including analog, mixed-signal, RF, MEMS, electrooptical)
Increase system and function size
Integrated passive components
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Design Challenge - DSM Effect
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Signal Integrity
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Reliability
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Crosstalk
IR (voltage) drop
Electromigration
Hot electron device degradation
Manufacturability
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SOC - Revolution or Evolution ?
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EDA and ASIC vendors said that SOC is a
revolution of IC design ! (so you need to learn new
design methodology and to buy “NEW” EDA tools.)
But what do you think about the design progress of
SSI -> MSI -> LSI -> VLSI -> ULSI -> SOC ?
No matter what it is, the $OC is the SOC. (Joho
Hsuan, Chairman UMC)
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Problems in SOC Era
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Time-to-market pressure
Difficult verification due o increasing complexity
Difficult timing closure due to deep submicron
process
Difficult integration due to various levels and areas
of expertise
Solution: Block-based design with reusable IPs
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Overview of SOC
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Technology Trend in Microelectronics
SOC Design Strategy
SOC Design Challenge
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Reusable IP Methodology
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What is IP ?
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Internet Phone ?
Internet Protocol ?
Intellectual Property
Virtual Components (VC)
Macros
Mega cells
Pre-design and Pre-verified functional blocks
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Type of IP
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Soft IP (“Code”)
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Synthesizable HDL description at RTL level
Flexible: can be changed to suit an application
Technology independent: may be re-synthesized across
processes
Customers are responsible for synthesis, timing closure,
and all front-end processing
Significant IP protection risk
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Type of IP (cont.)
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Firm IP (“synthesizable netlist + structure”)
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Delivered as a netlist to be included in customer’s netlist
(with don’t touch attribute)
Gate-level netlist optimized structurally and topologically
for performance and size
Floor planning or placement without routing
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Type of IP (cont.)
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Hard IP (“physical”)
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Provide as a blackbox (GDSII)
Usually very tight timing constrains
Internal views not be alterable or visible to the customer
Ready for “drop in”
Include layout and timing information
Optimized for performance, size, and power
IP is easily protected
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Categorizing Reusable Blocks
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IP value
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Foundation IP
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Star IP
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ARM processors
Niche IP
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Cell
MegaCell
ARM (low power) and Low power DSP
Standard IP
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USB, IEEE 1394, ADC/DAC
MPEG1/MPEG2/MPEG4
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IP sources
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Legacy IP
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New IP
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From previous IP
Specifically designed for reuse
License IP
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From IP vendors
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Sampling of Cores Classified by
Functionality
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Issues in IP Integration
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System-level IC Development
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Key to Success
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For VC creators
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Design reusable soft/hard VCs
For VC Integrators
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Integrate VCs into a SOC design
Verify functional and timing of SOC implementations
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Design for Use
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To be reusable, be usable first !
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Documentation
Code quality
Through commenting
Well-designed verification environments and test suits
(testbench + verification patterns)
Robust scripts
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Design for Reuse
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Design to maximize the flexibility
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Design for use in multiple technologies
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Robust and verified (silicon proven)
Design verified to a high level of confidence
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Portable designs
Design with complete verification process
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Configurable and parameterize
Provide physical samples or demo system
Design with full document set
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Role Change in SOC Era
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Conventional framework
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System/design houses take responsibility for RTL design
and synthesis
ASIC vendor take care physical implementation
New framework
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System/design houses provide SOC spec. and focus on
embedded S/W and applications
ASIC vendors offer IPs and integration services
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Retooling for New Roles
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For system/design houses
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Improve S/W and system architecture skill to
differentiate the end products
For ASIC vendors
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Learn to develop, integrate and manage reusable IPs
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To Be Reusable or Not to Be
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Normally designer teams treat design reuse as a burden
because it seems to lengthen the design cycle
Reuse vs. use-once design fashion
2x~3x development cost for reuse design
10x~100x productivity in successive designs
The only way to design million-gate chips is to employ
reuse methodology
Barriers to the adoption of reuse are managerial and
cultural in nature
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Mission
Your SOC Design Foundry
Mixed-Mode
DAC /ADC /PLL...
Glue Logic
Interface
USB /
1394 /
UART /
IrDA...
Processor
Storage
μC /
DSP /
MPU
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SRAM /
DRAM /
Flash /
ROM...
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References
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Shin-Wu Tung, “Reuse Methodology Manual for SoC Designs”.
Juinn-Dar Huang, “Reusable IP Authoring”.
Yao-Wen Chang, “Physical Design for SoC”
An-Yeu Wu, “SoC and IP Reuse”
Shen-Iuan Liu, “SOC Design from Mixed-signal’s View”
Andy Chao, “SOC Design from Mixed-signal’s View”
C. W. Jen, IP course design at NCTU
Textbook
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ARM System-on-Chip Architecture by Steve Furber (Paperback)
System-On-A-Chip : Design and Test (Artech House Signal Processing
Library) by Rochit Rajsuman (Hardcover - July 2000)
Reuse Methodology Manual for System-On-A-Chip Designs by Michael
Keating, Pierre Bricaud (Hardcover - June 1999)
ARM System-on-Chip Architecture, by Steve Furber. Paperback (August 25,
2000)
Reuse Methodology Manual for System-On-A-Chip Designs, by Michael
Keating, Pierre Bricaud. Hardcover (June 1999)
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Reference
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High-Level Synthesis : Introduction to Chip and System Design, by Daniel D. Gajski.
Hardcover (January 1992)
IEEE Computer Society Workshop on Vlsi '99 : System Design : Towards System-On-A-Chip
Paradigm : April 8-9, 1999 Orlando, Florida : Proceedings, by IEEE Computer Society, et al.
Paperback (March 1999)
IEEE Vlsi Text Symposium Chip-To-System Test, 1991, Paperback (December 1991)
Reuse Methodology Manual for System-On-A-Chip Designs, by Michael Keating, Pierre
Bricaud. Hardcover (May 1998)
System-On-Chip Semiconductors in Japan: A Strategic Entry Report, 1997 (Strategic Planning
Series), by The Electronics Research Group. Ring-bound (April 7, 1999)
Wescon/98 : Systems-On-A-Chip - Next Generation Ip Networks, Chip-Level Design, System
Design, Embedded Systems, Aerospace Applications, Quality/relia, by IEEE Region 6.
Paperback (October 1998)
Surviving the SOC Revolution – A Guild to Platform –Based Design, by H. Chang
VSI Standard
Website
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http://www.nii.org.tw/3C/
http://www.design-reuse.com/WORKSHOP/IP_design00.html
http://www.vsia.com
http://www.siliconip.org
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Agenda
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Overview of SOC
Reuse Methodology Manual (RMM) for SOC
Digital IP Authoring
RTL Coding Guideline
SOC and IP Core Design
Embedded CPU Design
Hardware/Software Co-Design
Low Power Design Issue
IP Design for Algorithm and Architecture Exploration
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Outline
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SoC Design Methodology
RTL Coding Guidelines
SoC Integration
Design Verification
Deliverables and Documentation
Management Issues
VSIA and Other References
Conclusions
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System Design Flow - Conventional
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High stage performance goal must be met for the low stage
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The lager chip size is, the more develop iteration it needs.
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All stage must be development serialized
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Work well up to 100K gates and down to 0.5u
H/W and S/W development are serial
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Waterfall Model
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System Design Flow - SOC
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Parallel, concurrent development of hardware and software.
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Parallel verification and synthesis of modules.
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Floorplan and place-and route included in the synthesis
process.
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Modules developed only if a pre-designed hard or soft
macro is not available.
Develop modules only if not available
„
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Spiral Model
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Top-Down and Bottom-Up
„
Traditional top-down design flow
„
„
„
„
„
Recursively partition the design into manageable blocks
Design blocks or select proper IPs
Recursively integrate blocks into the top-level
Iterate if any lower level block becomes unfeasible
Combination of top-down and bottom-up flow
„
Build critical blocks at the early design stage
„
„
Bottom-up fashion
Build up the system concurrently with some basic IPs and preverified reusable macros
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Fundamental Elements of IP
„
Specifications
„
„
„
Netlist
„
„
„
„
Design specification
Target specification
Behavior model
RTL code (soft IP)
Physical layout and SPICE netlist (hard IP)
Test patterns
„
Test plan and test bench
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38
Specification Requirements
„
„
„
„
„
„
Functionality
Performance/area/power
Test Coverage (fault coverage)
External interface to other HW blocks
(packaging information)
Interface timing
Interface to software
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Types of Specification (1/2)
„
Natural language
„
„
Ambiguities, incompleteness, error-prone
Formal specification
„
„
„
Written by a formal specification language
Formal verification can be used to check whether a specific
implementation meets the specification
To date, not been used widely because the specification writer
may introduce errors
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39
Types of Specification (2/2)
Executable specification
„
„
„
„
„
„
Usually written in C/C++, SDL, VERA, Specman
Verify basic functionality and interface between HW
and SW
Enables the SW development earlier (simulator)
Addresses functional behavior only
Require another written document to describe physical
specification
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Contents of Design Specification
„
„
„
Overview
Functional requirements
Physical requirements
„
Design requirements
„
Block diagrams
„
„
„
„
„
Area, performance, power ….
„
„
„
„
„
RTL design rules
„
External interface
I/O pin list
Timing constraints on I/O ports
Special signals such as clock and
reset
NCUEE -- Multimedia Communication IP Design
Manufacturing test
methodology
S/W programming model
„
Register map, ….
S/W requirements
Deliverables
Verification plan
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40
System Design Process
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4 Major Phases for Macro Design
„
Design top-level macro
„
„
Design each sub-block
„
„
„
Define the target spec.
Sub-module design
Integrate sub-blocks
Macro production
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Top Level Macro Design Flow
„
Specification
„
„
„
Partition
„
STEP 1
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Need to create a
behavior model and
testbench
Test the behavior mode
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Partition the design into
subblocks
83
Sub-Block Design Flow
STEP 2
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Sub-Block Design Flow
STEP 3
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Sub-Block Design Flow
STEP 4
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43
Sub-Block Integration Flow
STEP 5
Tasks
„
„
„
„
Generate top-level
HDL and netlist
Perform functional test
Synthesis
„
„
„
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Scan insertion
ATPG
Verify test coverage
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Sub-Block Integration Flow
STEP 6
„
Preparing macro for
SoC integration
„
„
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Soft macro
Hard macro
88
44
Macro Productization
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Design for Reuse IP
„
Design to maximize the flexibility
„
configurable
„
parameterizable
„
„
„
MPY-generator
USB for various kinds of devices
Design for use in multiple technologies
„
portable
„
Synthesis scripts for a variety of technologies
„
fit in multiple technology
„
Design with complete verification process
„
Design verified to a high level of confidence
„
„
„
robust and verified
physical prototype, demo system
Design with complete document set
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Parameterized IP design
Why to parameterize IP ?
„
„
„
Provide flexibility in interface and functionality
Facilitate verification
Parameterizable types
„
„
Logic/Algorithm functionality
„
Structural functionality
„
„
„
DCT, IDCT, DST, IDST
Bit-width, depth of FIFO, etc
Design process functionality
„
„
„
Test events
Event reports (what, when, where)
Automatic check event
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IP generator/Compiler
„
Inputs
„
„
„
„
Power dissipation, code size, application performance, die size, etc.
Types, numbers, and sizes of functional units, including processor
User defined instructions
Outputs
„
„
„
RTL code and testbenches
Synthesis and P&R scripts
Simulation and verification modelers
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46
Outline
„
„
„
„
„
„
„
„
SoC Design Methodology
RTL Coding Guidelines
SoC Integration
Design Verification
Deliverables and Documentation
Management Issues
VSIA and Other References
Conclusions
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Why Coding Guideline ?
„
„
„
To handle such high-complexity designs, many CAD tools
have to be involved in the design flow
However, each tool has its own capabilities and limitations
To obtain the best performance, we have to adjust our
coding styles for specific tools
„
„
Coding guideline are required !!
Details will be discussed later in separate materials
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Principles
„
„
„
„
„
„
Readability
Simplicity
Locality
Portability
Reusability
Reconfigurability
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Naming Conventions
„
„
„
„
„
Lowercase letters for signal names
Uppercase letters for constants
Case-insensitive naming
Use clk for clocks, rst for resets
Suffixes
„
„
„
„
_n for active-low, _a for async, _z for tri-state, …
Identical names for connected signals and ports
Do not use HDL reserved words
Consistency within group, division and corporation
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File Header
„
„
Should be included for all source files
Contents
„
„
„
„
„
„
„
„
author information
revision history
purpose description
available parameters
reset scheme and clock domain
critical timing and asynchronous interface
test structures
A corporation-wide standard template
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File Header (cont.)
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Comments and Formats
„
Appropriate comments
„
„
„
„
Comment end statements
One statement per line
Line length restriction
„
„
process (always block), function,…
a fixed number between 72-78
Indentation
„
„
2 or 4
do not use tab
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Ports
„
Ordering
„
„
„
„
one port per line with appropriate comments
inputs first then outputs
clocks, resets, enables, other controls, address bus, then
data bus
Mapping
„
use named mapping instead of positional mapping
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50
Coding Practices
„
Little-endian for multi-bit bus
„
„
„
„
„
Operand sizes should match
Expression in condition must be a 1-bit value
Use parentheses in complex statements
Do not assign signals don’t-care values
„
„
„
avoid don’t-care propagation
Reset all storage elements
„
„
[31:0] instead [0:31]
avoid don’t-care propagation
Use function to model combinational logic
Use local variables
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Portability
„
Do not use hard-coded numbers
„
„
„
Avoid embedded synthesis scripts
Use technology-independent libraries
„
„
secret=6’h 591003; //???
GTECH or DesignWare
Avoid instantiating vendor-specific gates
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Clocks and Resets
„
„
Simple clocking is easier to understand, analyze, and
maintain
Avoid using both edges of the clock
„
„
„
Do not buffer clock and reset networks
„
„
„
duty-cycle sensitive
difficult DfT process
should be handled during physical synthesis later
Avoid inadvertent clock gating
Avoid internally generated clocks and resets
„
limited testability
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Synchronicity
„
Infer technology-independent registers
„
„
Avoid latches intentionally
„
„
„
except for small memory and FIFO
for low-power
Avoid latches unintentionally
„
„
„
„
(positive) edge-triggered registers
avoid incomplete assignment in case statement
use default assignments
avoid incomplete if-then-else chain
Avoid combinational feedback loops
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Combinational Blocks
„
Combinational block
„
„
„
„
use blocking assignments
minimize signals required in sensitivity list
assignment should be applied in topological order
Use Verilog-Mode, www.veripool.com
„
„
„
„
„
„
AUTOSENSE
AUTOARG
AUTOINST
AUTOWIRE
AUTOREG
...
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Sequential Blocks
„
Sequential block
„
„
„
use non-blocking assignments
avoid race problems in simulation
Comb./Seq. Logic should be separated
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Verilog-Mode
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Module Tedium?
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54
Why is this information redundant?
„
„
„
„
„
The argument list is a duplication of the input/output
statements
Reg statements are needed for signals already ‘declared’ as
outputs
Wires need to be declared for interconnecting submodule
signals
Sensitivity lists are needed for obvious combinatorial logic
Name based submodule instantiations are a duplicate of
the submodule’s input/output statements
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Why eliminate redundancy?
„
„
„
„
Reduce spins on fixing lint or compiler warnings
Reduce sensitivity problems
„ If you forget (or don’t have) a linter, these are
horrible to debug!
Make it easier to name signals consistently through the
hierarchy
„ Reduce cut & paste errors on multiple instantiations.
„ Make it more obvious what a signal does.
Reducing the number of lines is goodness alone.
„ Less code to "look" at.
„ Less time typing.
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55
What would we like in a fix?
„
„
„
„
„
Don’t want a new language
„ All tools would need a upgrade!
„ (Verilog 2000 unfortunately faces this hurdle.)
Don’t want a preprocessor
„ Yet another tool to add to the flow!
„ Would need all users to have the preprocessor!
Would like input & output code to be completely "valid" Verilog.
„ Want non-tool users to remain happy.
„ Can always edit code without the program.
Want it trivial to learn basic functions
„ Let the user’s pick up new features as they need them.
Net result: **NO** disadvantage to using it
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Idea… Use comments!
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Sensitivity Lists
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Argument Lists
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Automatic Wires
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Automatic Registers
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58
Simple Instantiations
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State Machines
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Making upper level modules
„
Building null or shell modules
„
„
„
You want a module with same input/output list as another module.
/*AUTOINOUTMODULE(“from.v”)*/
Output all signals
„
„
„
You have a shell which outputs everything.
/*AUTOOUTPUT*/
Dc_shell preserves output net names, so this is great for
determining how fast each internal signal is generated.
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Verifiable RTL
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Verifiable RTL (cont.)
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Coding for Synthesis
„
Specify complete but no redundant sensitivity lists
„
„
„
If-then-else often infers a casecaded encoder
„
„
simulation coherence
simulation speed
inputs signals with different arrival time
case infers a single-level mux
„
„
case is better if priority encoding is not required
case is generally simulated faster than if-then-else
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Coding for Synthesis (cont.)
„
conditional assignment
„
„
„
„
No # delay statements
Avoid full_case and parallel_case
„
„
„
„
evil twin
pre-synthesis and post-synthesis simulation mismatch
Explicitly declare wires
Avoid glue logic at the top-level
„
„
infers a mux with slower simulation performance
better avoided
f1 (a&b, c, d), thus the AND gate has no name!
Avoid expressions in port connections
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Coding for FSM
„
„
„
„
Partition FSM and non-FSM logic
Prefer Moore (PO is PI-independent) to Mealy (PO is PIdependent)
Prefer Moore with state-outputs as POs
3-always paradigm
„
„
„
„
„
one for sequential logic
one for next-state logic
one for PO logic (if required)
Use parameters to define the state names
Assign a default (reset) state
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62
Coding for DfT
„
Avoid tri-state buses
„
„
„
„
„
bus contention, bus floating
using MUX will be better
Avoid internally generated clocks and resets
Scan support logic for gated clocks
Clock and set/reset should be fully externally controllable
under the test mode
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Partitioning
„
Register all outputs
„
„
„
Keep related logic together
„
„
„
improve synthesis quality
Partition logic with different design goals
Avoid asynchronous logic
„
„
„
„
make output drive strengths and input delay predictable
ease time budgeting and constrains
technology dependent
more difficult to ensure correct functionality and timing
as small as possible and isolation
Keep sharable resources in the same block
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63
Partitioning (cont.)
„
Avoid timing exception
„
„
point-to-point, false path, multi-cycle path
Chip-level partitioning
„
„
„
level 1: I/O pad ring only
level 2: clock generation, analog, memory,
JTAG
level 3: digital core
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Linter
„
Fast static RTL code checker
„
„
preprocessor of the synthesizer
RTL purification
„
„
„
„
„
syntax, semantics, simulation
timing checks
testability checks
reusability checks
Shorten design cycle by avoiding lengthy iterations
Lint is your first line of defense !
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64
Outline
„
„
„
„
„
„
„
„
SoC Design Methodology
RTL Coding Guidelines
SoC Integration
Design Verification
Deliverables and Documentation
Management Issues
VSIA and Other References
Conclusions
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SoC Integration Process
„
„
„
Select IPs and prepare them for integration
Integrate all IPs into the top-level RTL
Make a rough physical design
„
„
„
„
ex: floor plan
Synthesis and initial timing analysis
Final physical design, timing verification and power
analysis
Physical verification
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IP Selection
„
Good documentation
„
Documents, scripts, …..
„
Comprehensive verification environments
„
Design robustness
„
„
„
Quality of the deliverables, silicon-proof
User friendliness
„
„
„
Testbenches, test suites, models
Installation scripts
GUI interface
Physical design limitation (for hard IP only)
„
Aspect ratio, blockage, porosity, clocking, power
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Integration Problems
„
In-house newly developed IP blocks
„
„
„
„
„
Low-level interface may not work
Misunderstandings of the functionality in specification
May have functional bugs in block level designs
Relatively easy to fix because all sources are there
IPs obtained from external sources
„
„
„
Some guy of the team need to be familiar with these IPs
Documentation may be incomplete
IP interface may not match the system requirement
„
„
„
Result in large adoption logic for the external IP
Models are incomplete or with poor quality
Limited supports from the IP provider
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Integrated IP Example
(IP Provider)
•The IP provider uses VERA
to accelerate the verification
of the IP by developing a selfchecking testbench complete
with stimulus generator, selfchecking monitors, and coverage
objects.
• The IP provider then uses VERA CORE to turn the VERA
testbench into a secure, portable verification environment that
can be
shipped toCommunication
its customers
along with Tsung-Han
the simulator
model.
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-- Multimedia
IP Design
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Integrated IP Example
(IP purchasers)
•VERA CORE checks for the correct operation of the IP and looks
for completeness of coverage during system simulation.
•The IP is stimulated by other logic interacting with the IP. The
functional checkers and coverage monitors in VERA CORE are
selectively activated to provide self-checking and coverage
analysis on the IP. Any violation on the IP interface or unexpected
behavior inside the IP is immediately caught.
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VC Interface
„
An universal bus standard is the ultimate goal
„
„
„
Different power, performance, protocol requirements
Long way to go for the industry
Strategies
„
Plan the interface at the early stage
Keep all interfaces as simple as possible
Standardize on a few popular buses
„
Accumulate IP and experience with the IP
„
Document the experience and expertise
„
„
„
„
AMBA, VCI, OCP, PCI
Multiple related products on a platform to leverage investment
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Concept of Virtual Socket
Source: http:://www.vsi.org
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Interface designs
„
„
„
Provide communication link with other IPs
Too simplified interface is usually not practical
Interface capability
„
„
„
„
Handshaking mechanism
Cross clock domains
Data buffering
Commonly used interfaces
„
„
„
„
FIFO-based
Micro-controller-based
Industry standards
On-Chip Bus (OCB) – AMBA, VCI
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ARM OCB-AMBA
„
„
Advanced Microcontroller Bus Architecture (AMBA)
AMBA 2.0 specifies
„
„
„
„
the Advanced High-performance Bus (AHB)
the Advanced System Bus (ASB)
the Advanced Peripheral Bus (APB)
test methodology
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ARM OCB-AMBA
„
A typical AMBA system
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Virtual Component Interface (VCI)
„
What is VCI ?
„
„
A request-response protocol, contents and coding, for the transfer
of requests and response
VCI specifies
„
Three levels of protocol, compatible with each other
„
„
„
„
Advanced VCI (AVCI)
Basic VCI (BVCI)
Peripheral VCI (PVCI)
Transaction language
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VCI usage with a bus
„
Used as an interface to a
wrapper
1.
„
OCB suppliers provide VCI
wrappers
EDA vendors provide tools
to create wrappers
automatically
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VCI bus hierarchy
„
Local processor bus
„
„
„
System bus (backbone)
„
„
„
Processor-specific
Processor, cache, MMU, co-processor
DSP, DMA (master)
Memory, high-resolution LCD peripheral
Peripheral bus
„
„
Components with other design considerations (power, gate
count,etc.)
The bridge is the only bus master
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VCI (OCB) bus hierarchy
Multiple buses within a system
„
„
Organized by bandwidth
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Interfacing with Hard Macros
„
Clock distribution
„
„
„
Clock output for synchronization
Power and ground
Test structure
„
„
„
Integrated into the chip-level test structure
IEEE P1450 (STIL)
IEEE P1500
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72
Integrating Memory
„
„
Memory block is usually obtained from the
memory compilers
Synchronous RAM interface is preferred
„
„
„
Write-enable signal is very critical for asynchronous RAM
Consider the blockage effect for large memories
Consider BIST
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Models
„
Functional (simulation) models
„
„
„
„
„
Floor plan model
„
„
Behavioral or ISA model
Full (cycle-accurate) function model
Bus functional model (BFM) if appropriate
Emulation model (optional to accelerate simulation)
LEF format
Synthesis (timing) model
„
Synopsys .lib or .db format
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Functional Models
„
Functional models of different abstractions
„
„
„
Tradeoffs between accuracy and simulation speed
Meet various needs of the H/W and S/W terms in various design
phases
Model security
„
„
„
Functional models usually developed by C/C++ or HDL
Protection should be applied if security is a concern
Compiled (encrypted) model are usually required
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Behavioral Models
„
Behavioral model is required for all IPs
„
„
„
BFM model is required for interface IPs
„
„
Faster simulation and integration in system level designs
A very secure model for customer’s evaluation (evaluate
functionality only?)
PCI, USB, IEEE 1394 ……
ISA model implemented in C/C++ with PLI wrapper is
required for processor IPs
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Behavioral and ISA Models
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Bus Functional Model
„
„
„
„
Abstract out all internal behavior
Only provide the capability of creating
transactions on the outputs
Let integrators to test the rest of the system
A very fast and accurate model at the macro’s
interface
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Full Functional Model
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Synthesis Timing Model
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System Integration Guidelines
„
System-level guidelines
„
„
„
„
For producing well-designed IPs
For integrating well-designed IPs into an SoC design
Mostly driven by IP integrators and chip designers
Cornerstones of system level guidelines
„
„
„
DISCIPLINE
SIMPLICITY
LOCALITY
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Timing Closure Problem
„
Timing problems due to deep-submicron
„
„
„
„
„
Increasingly significant wire delay
Statistical wire-load model becomes imprecise
Algorithmic variations among EDA tools
Hard to achieve the timing closure
Tactics
„
„
„
Register all inputs/outputs of the macro
Register all outputs of the subblock within the macro
Timing-driven placement and routing
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Synchronous vs. Asynchronous
„
„
Avoid asynchronous and multi-cycle paths
Register-based synchronous design is preferred
„
„
„
„
Avoid to use latch as possible
„
„
„
Accelerate synthesis and simulation
Ease static timing analysis
Use single (positive) edge triggered flip-flop
Latches are no longer viewed as offering greater density and performance
than register based design
Over a large design, timing analysis of latch based design becomes
impossible
True register based design is recommended
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Clocking
„
Minimize the number of clock domains
„
„
„
Document the interface timing requirements
„
„
Isolate the interface between two domains
Careful synchronizer design to avoid metastability
Timing budget
PLL (Phase Lock Loop)
„
„
With disable/bypassing mechanism
Ease testing
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Clocking (cont.)
„
RuleNumber of clock domains and clock frequencies must be documented. It
is especially important to document
„
„
„
Required clock frequencies and associated phase locked loop.
„
External timing requirements (setup/hold and output timing) needed to
interface to the reset of the system
Guideline„
Use the smallest possible number of clock domain
„
If PLL is used for on chip clock generation, disable or bypass the PLL
should be provide
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Reset
„
Synchronous reset
„
„
„
„
Asynchronous reset
„
„
„
„
easy to synthesize
requires a free-running clock, especially at power-on
hard to deal with tri-state bus initialization at power-on
does not require a free-running clock
synchronous de-assertion problem
hard to implement, like clocks
Synchronous reset is preferred
„
„
timing model for it is much simpler than asynchronous
avoid possible race conditions and difficult static timing analysis
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Reset (cont.)
Rule
„
„
The basic reset strategy for the chip must be documented. It is particularly
important to addressing the following issues.
„
Is the reset synchronous or asynchronous ?
„
Is each macro individual resettable for debug purpose ?
Guideline
„
„
Tristate buses require very careful physical design to ensure only one
driver is enable at a time. We recommend that users not employ any
tristate buses in their SoC design.
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System Interconnection (1/2)
„
Tri-state bus
„
Bus connection problems
„
„
„
„
„
„
May reduce reliability
One and only one active bus driver at a time
Limited driving strength
Bus floating problems
„
„
?
Floating nets with ambiguous logic values
Solution: bus keeper or pull up/down resistances
ATPG problem
FPGA prototyping problem
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System Interconnection (2/2)
„
Multiplexer is better than Tri-state
buffer for SoC designs
E1
S
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Low Power Issue
„
Reduce supply voltage
„
„
Design with deep-submicron process
Reduce capacitance (and resistance)
„
„
P = CV2fsw
Low-power cell and I/O library
Reduce switching activity
„
„
„
Architectural and RTL exploration
Power-driven synthesis
Gate-level re-synthesis for low power
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81
Low Power Issue for Memories
„
Memory
„
Low-power memory design
„
„
Partition a large memory into smaller blocks
„
„
Memory = address decoder + data input buffer + memory array + sense
amplifier + data output buffer
Instant of using a single, deep memory, it may be possible to partition
the memory into several blocks
Only the block being accessed is power up to save power consumption
„ Gray-coded interface
„
Reduce switching activity
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Low Power Issue for Memories
(cont.)
„
Clock gating
„
„
„
50% ~ 70% power consumed in clock network
reported
gating the clock to an entire block
gating the clock to a register
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Low Power Issue for Memories
(cont.)
„
Trade fault converge for power consumption
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Macro Interface
macro A
CHIP
macro B
•Both inputs and outputs should be registered.
•Make timing closure within each block completely local.
•Macro A and Macro B can be design independently.
•Relative position on the chip need not concern at all.
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Subblock Interface
Macro A
Subblock 1
Subblock 2
•Registering the output of subblock is sufficient to provide locality
in timing closure.
•Since designer has all the timing context information .
•We provide to the physical design tools should all be accurate
enough to achieve rapid timing closure in physical design.
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On-Chip Bus (OCB)
„
„
„
Communications among IPs within a SoC
Standardize the OCB is impractical in real world
Two alternatives
„
„
Bus wrapper (VSIA’s approach)
Dedicated I/F (interface) blocks for several selected buses
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On-Chip Bus (OCB) (cont.)
„
A lower-speed bus is used to connect all of the
modules
„
„
„
Each macro can synchronize its own local clock to
the bus clock
„
„
„
To achieve lower power consumption
All the bus is fully synchronous
buffering the bus clock
PLL
The local clock can be multiple of the bus clock,
allowing higher frequency clocking locally
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On Chip Debug Structure
•Rule-Without effective debug structures, even the simplest of bugs can be very
difficult to troubleshoot on a large SoC design.
•Guideline-Controllability:The system should be designed so that each macro can be
effectively turn on, off, or put into a debug mode where only
its most basic function are operational.
-Observation:Adding bus monitor to the system provide a interface to the
outside word for debugging.
•Motorola, Hitachi, HP, Siemens and Bosh have form a association to devise a
debug interface standard
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Clock Distribution
•Rule-The design team must decide on the basic clock distribution architecture for
the chip early in the design process.
•To date, balance clock tree is a popular selected architecture in chip design.
•For lager, high speed chip, this requires extremely large, high power clock buffer.
•Guideline-A lower-speed bus is used to connect modules and all transactions between
modules use this bus. Each macro synchronous its own local clock to the
bus clock.
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Tri-State Bus vs. Multiplexer
„
Tri-state bus is not good
„
bus contention problem
„
„
„
bus floating problem
„
„
„
„
„
reduce reliability
one and only one driver at a time
reduce reliability
bus keeper
ATPG problem
FPGA prototyping problem
MUX bus
„
Higher cost
„
Technology independents
„
Shorter develop times
„
Synchronous system is available
Multiplexer is better than Tri-State
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Design for Test
System-level test plan must be developed in the initial
„
design stage
Test plan must be developed as soon as possible
On-chip test structures are recommended for all blocks
Different kinds of blocks will have different test strategies
„
„
„
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Design for Test (cont.)
„
Memory test
„
„
Processor test
„
„
„
chip-level test controller (including scan chain controller and JTAG
controller)
combined with embedded ICE for On-Chip-Debug (OCD)
Other macros
„
„
memory BIST is recommended
full-scan is recommended
Logic BIST
„
embedded stimulus generator and response checker
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Design For Timing Closure : Physical
Design Issue
The key to achieving rapid timing closure in physical design is to plan physical design early !
•Floorplanning
-Rule- Some initial floorplan should be developed as part of the initial
functional specification for the SoC design.
-To prevent the macro communicate with each other placed far apart.
•Synthesis strategy
-Rule- Overall design goals for timing, area, and power should be document
before macros are design and selected.
-Recommend bottom-up synthesis approach to ensure the origin wire load model
still holds and is not subsumed into a larger floorplan block.
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Outline
„
„
„
„
„
„
„
„
SoC Design Methodology
RTL Coding Guidelines
SoC Integration
Design Verification
Deliverables and Documentation
Management Issues
VSIA and Other References
Conclusions
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SoC Verification
„
„
Verification takes 60% - 80% of the design time
Key to success
„
„
„
„
„
„
„
„
„
Quality of the verification plan
Quality and abstraction level of the modules and testbenches
Quality and performance of the verification tools
Robustness of the pre-designed IPs
100% fault coverage of a SoC design is impossible.
Best strategy for minimizing defects is to do bottom-up
verification.(Locality)
Major difficulty in bottom-up verification is developing testbench at every
level of hierarchy.
For well designed block with clean,well-defined interface testbench
creation language, such as VERA and Specman create testbench
automatically.
Rule-Verification strategy should be based on bottom up verification. Clear
goals,testbench creation methodology, and completion metrics should all
be defined.
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Outline
„
„
„
„
„
„
„
„
SoC Design Methodology
RTL Coding Guidelines
SoC Integration
Design Verification
Deliverables and Documentation
Management Issues
VSIA and Other References
Conclusions
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Deliverables for Soft Macros
„
Product files
„
„
„
„
„
„
Documentation files
„
Synthesizable RTL
Application notes
All synthesis-related scripts
Scan/ATPG scripts
Installation scripts
„
„
„
System integration files
„
„
Verification files
„
„
„
„
BFM and bus monitors used in
testbench
Testbench and test suites
Verification guide
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User guide
Functional specification
Datasheet
Appropriate behavioral models
Recommendation of available
EDA tools for
„ HW/SW co-simulation
„ System integration
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Deliverables for Hard Macros
„
Product files
„
„
Verification files
„
„
Installation scripts
None !
Documentation files
„
„
„
„
„
User guide
Functional specification
Datasheet
Integration guide
Test guide
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System integration files
„
„
„
„
„
„
„
ISA or behavioral model
BSM for large macro
Full functional model
Timing and synthesis model
Floor plan model
Test pattern for manufacturing
test
Recommendation of available EDA
tools for
„ HW/SW co-simulation
„ System integration
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90
Outline
„
„
„
„
„
„
„
„
SoC Design Methodology
RTL Coding Guidelines
SoC Integration
Design Verification
Deliverables and Documentation
Management Issues
VSIA and Other References
Conclusions
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Reuse-based SoC Design
„
Key elements
„
Design-for-reuse IPs
„
„
„
IP repository (IP mall)
„
„
„
In-house development
Qualification and acquisition of 3rd party IPs
Central database and service infrastructure
Integration Methodology
Reuse support structure
„
Same attitude for senior managers, managers and engineers
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Key Steps
„
Develop the reuse methodology
„
„
„
„
„
Employee training
Tool flow
Demonstrate the effectiveness with pilot project(s)
Enrich the IP repository and apply the reuse
methodology to each project
Refine the methodology
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Reuse Economy
„
„
Financial incentives are very important
IP development team should be rewarded:
„
„
In terms of ease of integration
Not in terms of area, speed and power
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VCX (Virtual Component Exchange)
„
The VCX, an industry-backed initiative, is
dedicated to providing solutions for the business
and legal issues associated with transactions of
VCs
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VCX (cont.)
„
„
„
Focused on organising an Internet-based businesstobusiness marketplace for the buying and selling of
semiconductor IP (VCs)
Help organize the global trading of VCs into an efficient,
international and open structure
Buying and incorporating VCs through the VCX will
ensure reduced time-to-market for new products while
offering protection, support and a sustainable business
model for both VC providers and users
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VCX Homepage
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Virtual Socket Interface Alliance
„
The goal of VSIA
„
„
Establishing a unifying vision for the system-on-chip industry, and
the technical standards required to enable the most critical
component
Development Working Group (DWG)
„
„
„
„
„
„
„
„
Analog Mixed-Signal (AMS)
Implementation/Verification (I/V)
IP Protection (IPP)
Manufacturing Related Test (TST)
On-Chip Buses (OCB)
System-Level Design (SLD)
Virtual Component Transfer (VCT)
Verification
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OpenMORE
„
Open Measure of Reuse Excellence (OpenMORE)
„
„
„
„
„
Based on Reuse Methodology Manual (RMM)
IP providers use OpenMORE for self-evaluation
Designers can ensure that each portion of a design is
workable and reusable
Supported by industry groups --- VSIA, VCX, RAPID, and
Design and Reuse
http://www.openmore.com/
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IP Catalyst Programs
•The IP Catalyst program manages the Measure of Reuse
Excellence (MORE) rating system and the IP Catalyst Catalog.
• The MORE rating system evaluates how well IP design processes
follow the Reuse Methodology Manual's (RMM) approximately
150 rules and guidelines for the creation, verification and delivery
of soft IP.
• IP Catalyst partners agree to publish a MORE rating of their IP in
the web-based IP Catalyst Catalog and can be downloaded from
the IP Catalyst web site .
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Some References
„
Books and Reports
−
−
−
−
−
„
“Reuse Methodology Manual for System-On-AChip Designs”, Second Edition by M. Keating
and P. Bricaud, Kluwer Academic Publishers,
1999.
“Principles of Verifiable RTL Design”, by L.
Bening and H. Foster, Kluwer Academic
Publishers, 2000.
“Surviving the SOC Revolution – A Guide to
Platform-Based Design”, by H. Chang et al,
Kluwer Academic Publishers, 1999.
Open Core Protocol,
http://www.sonicsinc.com/mnet/
ocp_descr.html
Motorola’s SRS,
http://mot-sps.com/technology/srs/
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Web Sites
−
−
−
−
−
−
−
−
Tsung-Han Tsai
RAPID, http://www.rapid.org
VCX, http://www.vcx.org
VSIA, http://www.vsi.org
Design and Reuse,
http://www.design-reuse.com
OpenMORE,
http://www.openmore.com
The Free IP Project,
http://www.free-ip.com
Open Cores,
http://www.opencores.org
Open Collector,
http://www.opencollector.org
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Conclusions
„
„
„
„
„
Design reuse is a new paradigm
Common standards help to speed up the progress
The process is disciplined and rigorous
Paradigm shift requires attitude changes from both
the design teams and managers
Reuse is not a technical problem but a managerial
and cultural one !
Most importantly,
REUSE is simply the belief !
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Platform-Based SOC Design
„
Embedded Processor for SOC
Embedded DSP for SOC
SOPC - FPGA Approach
„
Platform-Based Design
„
„
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Platform-Based SOC
„
„
„
Definition
„ “Reference Hw/Sw architecture that satisfies a set of
architectural constraints, and allows the re-use of Hw and
Sw components”
In Practice:
„ Superset of an architecture, adapted by removing
components
„ Stripped down architecture, adapted by adding
components
Initial development costly, but derivative designs cheap
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From IP to Platform
„
SOC design increasingly based on pre-designed
components (IP reuse) and even pre-defined
platform (architecture reuse)
„
„
„
2000 -> 50 %
2005 -> 80%
2010 -> 95%
source: Dataquest, 2000
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Benefits for Platform Based
„
„
„
„
„
Reduce overall system cost
Increase performance
Low power consumption
Reduce overall silicon size
Concerns: the separation of function and
architecture, of communication and computation
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What is Platform-Based Design
„
A Pre-designed and Pre-verified application
architecture framework
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Prototype vs. Platform
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How to Works?
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Platform-Based Integration
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Ingredients of Platform
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How to Build a Platform
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Platform-Based Design
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Design Stage - System Specification
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Design Stage - Design Partition
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Design Stage - Architecture
Evaluation
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Design Stage - Integration &
Verification
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Three Level Platform Design System
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Type of Platform
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Platform design
„
AMBA is an open standard, on-chip bus specification that
details a strategy for the interconnection and management of
functional blocks that makes up a System-on-chip (SoC).
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