Cypress Semiconductor | STK11C68-5 | Cypress Semiconductor STK11C68-C35I datasheet: pdf

STK11C68
64 Kbit (8K x 8) SoftStore nvSRAM
Functional Description
■
25 ns, 35 ns, and 45 ns access times
■
Pin compatible with industry standard SRAMs
■
Software initiated nonvolatile STORE
■
Unlimited Read and Write endurance
■
Automatic RECALL to SRAM on power up
■
Unlimited RECALL cycles
■
1,000,000 STORE cycles
The Cypress STK11C68 is a 64Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers under software control from SRAM to the nonvolatile
elements (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation) from the
nonvolatile memory. RECALL operations are also available
under software control.
■
100 year data retention
■
Single 5V+10% operation
■
Commercial and industrial temperature
■
28-pin (330 mil) SOIC package
■
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages
■
RoHS compliance
ROW DECODER
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Features
Logic Block Diagram
A7
A8
A9
A 11
A 12
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
STATIC RAM
ARRAY
128 X 512
VCAP
POWER
CONTROL
STORE
N
A6
INPUT BUFFERS
A5
VCC
Quantum Trap
128 X 512
RECALL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
A0
- A 12
COLUMN I/O
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-50638 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 8, 2010
[+] Feedback
STK11C68
Contents
Features ............................................................................. 1
Operating Range ............................................................... 6
Functional Description ..................................................... 1
DC Electrical Characteristics .......................................... 6
Logic Block Diagram ........................................................ 1
Data Retention and Endurance ....................................... 6
Contents ............................................................................ 2
Capacitance ...................................................................... 7
Pin Configurations ........................................................... 3
Thermal Resistance .......................................................... 7
Pin Definitions .................................................................. 3
AC Test Conditions .......................................................... 7
Device Operation .............................................................. 4
AC Switching Characteristics ......................................... 8
SRAM Read Cycle ...................................................... 8
SRAM Write Cycle ....................................................... 9
Hardware Protect .............................................................. 4
Noise Considerations ....................................................... 4
Low Average Active Power .............................................. 4
s.
Ordering Information ........................................................ 12
Package Diagrams ............................................................ 13
Document History Page ................................................... 15
Sales, Solutions, and Legal Information ........................ 15
Worldwide Sales and Design Support ......................... 15
Products ...................................................................... 15
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Best Practices ................................................................... 5
Part Numbering Nomenclature ........................................ 12
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Hardware RECALL (Power Up) ........................................ 4
Software Controlled STORE/RECALL Cycle .................. 11
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Software RECALL ............................................................. 4
AutoStore INHIBIT or Power Up RECALL ...................... 10
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Software STORE ............................................................... 4
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SRAM Write ....................................................................... 4
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SRAM Read ....................................................................... 4
N
Maximum Ratings ............................................................. 6
Document Number: 001-50638 Rev. *C
Page 2 of 15
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STK11C68
Pin Configurations
:(
1&
$
$
$
$
$
$ $
$
$
2(
$ $
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'4 '4
'4 '4
'4 '4
'4
966
Alt
A0–A12
Input or
Output
WE
W
CE
E
OE
G
VCC
'4
I/O Type
Input
DQ0-DQ7
VSS
Description
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
I/O pins is written to the specific address location.
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
N
Pin Name
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Pin Definitions
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Figure 1. Pin Diagram - 28-Pin SOIC/DIP and 28-Pin LLC
Ground
Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 001-50638 Rev. *C
Page 3 of 15
[+] Feedback
STK11C68
The STK11C68 performs a Read cycle whenever CE and OE are
LOW while WE is HIGH. The address specified on pins A0–12
determines the 8,192 data bytes accessed. When the Read is
initiated by an address transition, the outputs are valid after a
delay of tAA (Read cycle 1). If the Read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (Read
cycle 2). The data outputs repeatedly respond to address
changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another
address change or until CE or OE is brought HIGH, or WE
brought LOW.
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A Write cycle is performed whenever CE and WE are LOW. The
address inputs must be stable prior to entering the Write cycle
and must remain stable until either CE or WE goes HIGH at the
end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if it has valid tSD, before the end of a WE
controlled Write or before the end of an CE controlled Write.
Keep OE HIGH during the entire Write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
Software STORE
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.
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SRAM Write
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled Read operations is
performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
s.
SRAM Read
Software RECALL
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The STK11C68 is a versatile memory chip that provides several
modes of operation. The STK16C88 can operate as a standard
8K x 8 SRAM. A 8K x 8 array of nonvolatile storage elements
shadow the SRAM. SRAM data can be copied nonvolatile
memory or nonvolatile data can be recalled to the SRAM.
tSTORE cycle time is fulfilled, the SRAM is again activated for
Read and Write operation.
og
Device Operation
During power up or after any low power condition (VCC <
VRESET), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
If the STK11C68 is in a Write state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system VCC or between CE and system VCC.
Hardware Protect
The STK11C68 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage conditions. When VCAP<VSWITCH, all externally initiated STORE
operations and SRAM Writes are inhibited.
N
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK11C68 software STORE
cycle is initiated by executing sequential CE controlled Read
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of Reads from specific addresses is used
for STORE initiation, it is important that no other Read or Write
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following Read
sequence is performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
The software sequence is clocked with CE controlled Reads.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
Read cycles and not Write cycles are used in the sequence. It is
not necessary that OE is LOW for a valid sequence. After the
Hardware RECALL (Power Up)
Document Number: 001-50638 Rev. *C
Noise Considerations
The STK11C68 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Low Average Active Power
CMOS technology provides the STK11C68 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 2 shows the relationship between ICC and
Read or Write cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled.
Page 4 of 15
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STK11C68
The overall average current drawn by the STK11C68 depends
on the following items:
■
The duty cycle of chip enable
■
The overall cycle rate for accesses
■
The ratio of Reads to Writes
■
CMOS versus TTL input levels
■
The operating temperature
■
The VCC level
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that an NV array
is in a set programmed state. Routines that check memory
content values to determine first time system configuration,
■
cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■
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I/O loading
Figure 2. Current Versus Cycle Time (Read)
Figure 3. Current Versus Cycle Time (Write)
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Table 1. Hardware Mode Selection
CE
WE
A12–A0
Mode
I/O
Notes
L
H
0x0000
0x1555
0x0AAA
0x1FFF
0x10F0
0x0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
[1]
L
H
0x0000
0x1555
0x0AAA
0x1FFF
0x10F0
0x0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
[1]
Note
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
Document Number: 001-50638 Rev. *C
Page 5 of 15
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STK11C68
Maximum Ratings
Power Dissipation ......................................................... 1.0W
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
DC Output Current (1 output at a time, 1s duration).... 15 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Temperature under bias.............................. –55°C to +125°C
Range
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V
Commercial
Voltage on Input Relative to Vss............ –0.6V to VCC + 0.5V
Industrial
Ambient
Temperature
VCC
0°C to +70°C
4.5V to 5.5V
-40°C to +85°C
4.5V to 5.5V
Voltage on DQ0-7 ...................................–0.5V to Vcc + 0.5V
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V)
Commercial
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tRC = 25 ns
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
IOUT = 0 mA.
s.
Min
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Average VCC Current
Test Conditions
Industrial
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Description
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Parameter
Max
Unit
90
75
65
mA
mA
mA
90
75
65
mA
mA
mA
3
mA
ICC2
Average VCC Current
during STORE
ICC3
Average VCC Current at WE > (VCC – 0.2V). All other inputs cycling.
tRC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained
Typical
without output loads.
10
mA
ISB1[2]
VCC Standby Current
(Standby, Cycling TTL
Input Levels)
Commercial
27
23
20
mA
mA
mA
Industrial
28
24
21
mA
mA
mA
750
μA
1500
μA
-1
+1
μA
-5
+5
μA
2.2
VCC +
0.5
V
VSS – 0.5
0.8
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ISB2 [2]
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
VCC Standby Current
tRC = 25 ns, CE > VIH
tRC = 35 ns, CE > VIH
tRC = 45 ns, CE > VIH
CE > (VCC – 0.2V). All others VIN < 0.2V or > Commercial
(VCC – 0.2V). Standby current level after
nonvolatile cycle is complete.
Industrial
Inputs are static. f = 0 MHz.
Input Leakage Current VCC = Max, VSS < VIN < VCC
Off State Output
Leakage Current
VIH
Input HIGH Voltage
N
IIX
IOZ
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
IOUT = –4 mA
VOL
Output LOW Voltage
IOUT = 8 mA
V
2.4
V
0.4
V
Data Retention and Endurance
Parameter
Description
DATAR
Data Retention
NVC
Nonvolatile STORE Operations
Min
Unit
100
Years
1,000
K
Note
2. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
Document Number: 001-50638 Rev. *C
Page 6 of 15
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STK11C68
Capacitance
In the following table, the capacitance parameters are listed.[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
Max
Unit
8
pF
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[3]
Parameter
ΘJA
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
Thermal Resistance
(Junction to Case)
28-SOIC
28-CDIP
28-LCC
Unit
TBD
TBD
TBD
°C/W
TBD
TBD
TBD
°C/W
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ΘJC
Description
Thermal Resistance
(Junction to Ambient)
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Figure 4. AC Test Loads
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R1 480Ω
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5.0V
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Output
30 pF
R2
255Ω
AC Test Conditions
N
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times (10% to 90%) ...................... <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
3. These parameters are guaranteed by design and are not tested.
Document Number: 001-50638 Rev. *C
Page 7 of 15
[+] Feedback
STK11C68
AC Switching Characteristics
SRAM Read Cycle
25 ns
Min
Max
Min
45 ns
Max
25
35
25
45
25
10
35
15
5
5
45
20
5
5
5
5
13
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0
10
15
s.
10
0
0
13
15
0
25
Max
45
35
0
Min
0
35
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
35 ns
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Description
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Parameter
Cypress
Alt
Parameter
tELQV
tACE
tAVAV, tELEH
tRC [4]
tAVQV
tAA [5]
tGLQV
tDOE
tAXQX
tOHA [5]
tELQX
tLZCE [6]
tEHQZ
tHZCE [6]
[6]
tGLQX
tLZOE
tGHQZ
tHZOE [6]
tELICCH
tPU [3]
[3]
tEHICCL
tPD
tio
Switching Waveforms
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Figure 5. SRAM Read Cycle 1: Address Controlled [4, 5]
W5&
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W2+$
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Figure 6. SRAM Read Cycle 2: CE and OE Controlled [4]
$''5(66
N
W5&
W$&(
W3'
W/=&(
&(
W+=&(
2(
W+=2(
W'2(
W/=2(
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W 38
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$&7,9(
67$1'%<
Notes
4. WE must be High during SRAM Read cycles.
5. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
6. Measured ±200 mV from steady state output voltage.
Document Number: 001-50638 Rev. *C
Page 8 of 15
[+] Feedback
STK11C68
SRAM Write Cycle
Parameter
tAVAV
tWLWH, tWLEH
tELWH, tELEH
tDVWH, tDVEH
tWHDX, tEHDX
tAVWH, tAVEH
tAVWL, tAVEL
tWHAX, tEHAX
tWLQZ
tWHQX
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE [6,7]
tLZWE [6]
Min
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Max
Min
25
20
20
10
0
20
0
0
45 ns
Max
35
25
25
12
0
25
0
0
Min
10
13
5
5
15
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Switching Waveforms
Max
45
30
30
15
0
30
0
0
s.
Alt
35 ns
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Cypress
Parameter
25 ns
Description
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Figure 7. SRAM Write Cycle 1: WE Controlled [7, 8]
tio
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tWC
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ADDRESS
tHA
tSCE
CE
tAW
tSA
WE
tPWE
tSD
DATA IN
tHD
DATA VALID
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
N
Figure 8. SRAM Write Cycle 2: CE and OE Controlled [7, 8]
ADDRESS
CE
tWC
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Notes
7. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
8. CE or WE must be greater than VIH during address transitions.
Document Number: 001-50638 Rev. *C
Page 9 of 15
[+] Feedback
STK11C68
AutoStore INHIBIT or Power Up RECALL
Parameter
tHRECALL [9]
tSTORE
VSWITCH
VRESET
Alt
tRESTORE
tHLHZ
STK11C68
Max
550
10
4.0
4.5
3.6
Description
Min
Power up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
Low Voltage Reset Level
Unit
μs
ms
V
V
Switching Waveform
Figure 9. AutoStore INHIBIT/Power Up RECALL
s.
VCC
ra
m
5V
VSWITCH
STORE INHIBIT
POWER-UP RECALL
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VRESET
tHRECALL
DQ (DATA OUT)
N
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
Note
9. tHRECALL starts from the time VCC rises above VSWITCH.
Document Number: 001-50638 Rev. *C
Page 10 of 15
[+] Feedback
STK11C68
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [10, 11]
Parameter
Alt
Description
25 ns
Min
35 ns
Max
Min
45 ns
Max
Min
Max
Unit
tRC
tAVAV
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tSA[10]
tCW[10]
tHACE[10]
tRECALL[10]
tAVEL
Address Setup Time
0
0
0
ns
tELEH
Clock Pulse Width
20
25
30
ns
tELAX
Address Hold Time
20
20
20
ns
RECALL Duration
20
20
20
μs
Switching Waveform
tSA
CE
pr
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ADDRESS # 6
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ADDRESS # 1
ADDRESS
tRC
tio
tRC
og
ra
m
s.
Figure 10. CE Controlled Software STORE/RECALL Cycle [11]
tSCE
tHACE
OE
DATA VALID
DATA VALID
HIGH IMPEDANCE
N
DQ (DATA)
t STORE / t RECALL
Notes
10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
11. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
Document Number: 001-50638 Rev. *C
Page 11 of 15
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STK11C68
Part Numbering Nomenclature
STK11C68 - S F 45 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
Temperature Range:
Blank - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
ra
m
s.
Lead Finish
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
pr
og
F = 100% Sn (Matte Tin)
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Package:
S = Plastic 28-pin 330 mil SOIC
C = Ceramic 28-pin 300 mil DIP
L = Ceramic 28-pin 350 mil LLC
Ordering Information
These parts are not recommended for new designs. They are in production to support ongoing production programs only.
Speed (ns)
Ordering Code
Package Diagram
Package Type
STK11C68-C35I
001-51695
28-Pin CDIP (300 mil)
45
STK11C68-SF45TR
51-85058
28-Pin SOIC (330 mil)
STK11C68-SF45
51-85058
28-Pin SOIC (330 mil)
STK11C68-SF45ITR
51-85058
28-Pin SOIC (330 mil)
STK11C68-SF45I
51-85058
28-Pin SOIC (330 mil)
N
35
Operating Range
Industrial
Industrial
All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts
Document Number: 001-50638 Rev. *C
Page 12 of 15
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STK11C68
Package Diagrams
51-85058 *B
N
In ot r
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Figure 11. 28-Pin (330 Mil) SOIC (51-85058)
Document Number: 001-50638 Rev. *C
Page 13 of 15
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STK11C68
Package Diagrams (continued)
001-51695 *A
N
In ot r
pr ec
od om
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tio en
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Figure 12. 28-Pin (300 Mil) Side Braze DIL (001-51695)
Document Number: 001-50638 Rev. *C
Page 14 of 15
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STK11C68
Document History Page
Document Title: STK11C68 64 Kbit (8K x 8) SoftStore nvSRAM
Document Number: 001-50638
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2625084
GVCH/PYRS
01/30/09
*A
2826441
GVCH
12/11/2009
Added following text in the Ordering Information section: “These parts are
not recommended for new designs. In production to support ongoing production programs only.”
Added watermark in PDF stating “Not recommended for new designs. In
production to support ongoing production programs only.”
Added Contents on page 2.
*B
2902591
GVCH
04/05/2010
Removed inactive parts from Ordering Information.
Updated Package Diagrams.
*C
3052511
GVCH
10/08/10
Description of Change
s.
New data sheet
tio
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pr
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Removed the following inactive parts from the Ordering Information table:
STK11C68-L35, STK11C68-L35I, STK11C68-L45, STK11C68-L45I,
STK11C68-SF25, STK11C68-SF25I, STK11C68-SF25ITR,
STK11C68-SF25TR
Removed the 28-pin LCC package diagram
In ot r
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
Clocks & Buffers
Wireless
Memories
Image Sensors
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/usb
N
USB
psoc.cypress.com
© Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-50638 Rev. *C
Revised October 8, 2010
Page 15 of 15
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