DS821

DS821
LogiCORE IP 7 Series FPGAs
Integrated Block v1.1
for PCI Express
DS821 March 1, 2011
Product Specification
Introduction
The LogiCORE™ IP 7 Series FPGAs Integrated Block
for PCI Express® core is a high-bandwidth, scalable,
and reliable serial interconnect building block for use
with 7 Series FPGA families. The Integrated Block for
PCI Express (PCIe®) solution supports 1-lane, 2-lane,
4-lane, and 8-lane Endpoint configurations at up to
Gen2 (5 Gb/s) speeds, all of which are compliant with
the PCI Express Base Specification, rev. 2.1. This solution
supports the AXI4-Stream interface for the customer
user interface.
PCI Express offers a serial architecture that alleviates
many of the limitations of parallel bus architectures by
using clock data recovery (CDR) and differential
signaling. Using CDR (as opposed to source
synchronous clocking) lowers pin count, enables
superior frequency scalability, and makes data
synchronization easier. The layered architecture of PCI
Express provides for future attachment to copper,
optical, or emerging physical signaling media. PCI
Express technology, adopted by the PCI-SIG® as the
next generation PCI, is backward-compatible to the
existing PCI software model.
With higher bandwidth per pin, low overhead, low
latency, reduced signal integrity issues, and CDR
architecture, the Integrated Block for PCIe sets the
industry
standard
for
a
high-performance,
cost-efficient, third-generation I/O solution.
The Integrated Block for PCI Express solution is
compatible with industry-standard application form
factors such as the PCI Express Card Electromechanical
(CEM) v2.0 and the PCI Industrial Computer
Manufacturers Group (PICMG) 3.4 specifications.
LogiCORE IP Facts
Core Specifics
Supported
FPGA
Families (1)
Virtex-7, Kintex-7
XC7K30T-1 (2)
Minimum
Device
Supported
User Interfaces
Resources
Special
Features
AXI4-Stream
See Table 1
GTXE2 Transceivers,
7 Series FPGA Integrated Block for
PCI Express,
Virtex-7/Kintex-7 FPGA MMCM,
Block RAM
Provided with Core
Documentation
Design Files
Constraints File
Product Specification,
User Guide, Instantiation Template
Verilog/VHDL RTL Source
and Simulation Models
Verilog/VHDL Test Bench,
Verilog/VHDL Example Design
User Constraints File (UCF)
Design Tool Support
HDL Synthesis
Tool
XST 13.1
Synopsys Synplify Pro D-2011.03
Xilinx
Implementation
Tools
ISE® 13.1
Simulation
Tools
Cadence Incisive Enterprise Simulator (IES) 10.2
Synopsys VCS and VCS MX 2010.06
Mentor Graphics ModelSim 6.6d
ISim 13.1
Support
Provided by Xilinx, Inc. @ www.xilinx.com/support
1. For the complete list of supported devices, see the release notes
for this core.
2. Designs needing 8-lane operation with Gen2 (5 Gb/s) speeds must
use the 128-bit version of the product.
© Copyright 2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States
and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
DS821 March 1, 2011
Product Specification
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1
LogiCORE IP 7 Series FPGAs Integrated Block v1.1 for PCI Express
Table 1: Resources Used
Product
Interface GTXE1 LUT (1)
RX Buffers
FF (2)
Width
Size (KB)
1-lane
Gen1/Gen2
64-bit
1
350
575
2-lane
Gen1/Gen2
64-bit
2
500
675
4-lane Gen1
64-bit
4
750
950
4-lane Gen2
64-bit,
128-bit
4
850
1300
8-lane, Gen1
64-bit,
128-bit
8
1600
2350
8-lane, Gen2
128-bit
8
1600
2500
TX Buffers
Size (KB)
CMPS (2)
(Bytes)
Block
RAM
4-32
128-1024
4 or 8
8 or 16
1. Numbers are for the default core configuration. Actual LUT and FF utilization values vary based on specific configurations.
2. Capability Maximum Payload Size (CMPS).
Features
•
2
High-performance, highly flexible, scalable, and reliable, general-purpose I/O core
•
Compliant with the PCI Express Base Specification, rev. 2.1
•
Compatible with conventional PCI software model
•
Incorporates Xilinx® Smart-IP™ technology to guarantee critical timing
•
Uses GTXE2 transceivers for 7 Series FPGA families
•
2.5 GT/s and 5.0 GT/s line speed
•
Supports 1-lane, 2-lane, 4-lane, and 8-lane operation
•
Elastic buffers and clock compensation
•
Automatic clock data recovery
•
Supports Endpoint configurations
•
8B/10B encode and decode
•
Supports Lane Reversal and Lane Polarity Inversion per PCI Express specification requirements
•
Standardized user interface
•
Supports AXI4-Stream interface
•
Easy-to-use packet-based protocol
•
Full-duplex communication
•
Back-to-back transactions enable greater link bandwidth utilization
•
Supports flow control of data and discontinuation of an in-process transaction in transmit
direction
•
Supports flow control of data in receive direction
•
Compliant with PCI/PCI Express power management functions
•
Supports a maximum transaction payload of up to 1024 bytes
•
Supports Multi-Vector MSI for up to 32 vectors and MSI-X
•
Up-configure capability enables application driven bandwidth scalability
•
Compliant with PCI Express transaction ordering rules
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DS821 March 1, 2011
Product Specification
LogiCORE IP 7 Series FPGAs Integrated Block v1.1 for PCI Express
Applications
The 7 series Integrated Block for PCI Express architecture enables a broad range of computing and
communications target applications, emphasizing performance, cost, scalability, feature extensibility
and mission-critical reliability. Typical applications include
•
Data communications networks
•
Telecommunications networks
•
Broadband wired and wireless applications
•
Cross-connects
•
Network interface cards
•
Chip-to-chip and backplane interconnect
•
Crossbar switches
•
Wireless base stations
Functional Description
For information about the internal architecture and detailed descriptions of the interfaces of the
Virtex®-7 and Kintex™-7 FPGA integrated block, see UG477, LogiCORE IP 7 Series FPGAs Integrated
Block for PCI Express User Guide. Figure 1 illustrates the interfaces to the core.
•
System (SYS) Interface
•
PCI Express (PCI EXP) Interface
•
Physical Layer Control and Status (PL) Interface
•
Configuration (CFG) Interface
•
AXI4-Stream Interface
X-Ref Target - Figure 1
LogiCORE IP 7 Series FPGAs
Integrated Block for PCI Express
TX
Block RAM
User
Logic
Physical Layer
Control and Status
Host
Interface
User
Logic
RX
Block RAM
AXI4-Stream
Interface
Physical
(PL)
7 Series FPGAs
Integrated Block for
PCI Express
(PCIE_2_1)
PCI Express
(PCI_EXP)
Transceivers
Configuration
(CFG)
Optional Debug
Optional Debug
(DRP)
System
(SYS)
PCI
Express
Fabric
User Logic
Clock
and
Reset
Figure 1: Integrated Block for PCI Express Top-Level Functional Blocks and Interfaces
DS821 March 1, 2011
Product Specification
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3
LogiCORE IP 7 Series FPGAs Integrated Block v1.1 for PCI Express
Protocol Layers
The integrated block follows the PCI Express Base Specification, rev. 2.1 layering model, which consists of
the Physical, Data Link, and Transaction Layers. The protocol uses packets to exchange information
between layers. Packets are formed in the Transaction and Data Link Layers to carry information from
the transmitting component to the receiving component. Necessary information is added to the packet
being transmitted, which is required to handle the packet at specific layers.
At the receiving end, each layer of the receiving element processes the incoming packet, strips the
relevant information and forwards the packet to the next layer. As a result, the received packets are
transformed from their Physical Layer representation to their Data Link Layer representation and
Transaction Layer representation.
The functions of the protocol layers include:
•
Generating and processing of TLPs
•
Flow-control management
•
Initialization and power management functions
•
Data protection
•
Error checking and retry functions
•
Physical link interface initialization
•
Maintenance and status tracking
•
Serialization, deserialization and other circuitry for interface operation
Each of the protocol layers are defined in the sections that follow.
Physical Layer
The Physical Layer exchanges information with the Data Link Layer in an implementation-specific
format. This layer is responsible for converting information received from the Data Link Layer into an
appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width
compatible with the remote device.
Data Link Layer
The Data Link Layer acts as an intermediate stage between the Transaction Layer and the Physical
Layer. Its primary responsibility is to provide a reliable mechanism for the exchange of Transaction
Layer Packets (TLPs) between the two Components on a Link.
Services provided by the Data Link Layer include data exchange (TLPs), error detection and recovery,
initialization services and the generation and consumption of Data Link Layer Packets (DLLPs). DLLPs
are the mechanism used to transfer information between Data Link Layers of two directly connected
components on the Link. DLLPs are used for conveying information such as Flow Control and TLP
acknowledgments.
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The primary function of the
Transaction Layer is the assembly and disassembly of Transaction Layer Packets (TLPs). Packets are
formed in the Transaction and Data Link Layers to carry the information from the transmitting
component to the receiving component. TLPs are used to communicate transactions, such as read and
write, as well as certain types of events. To maximize the efficiency of communication between devices,
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DS821 March 1, 2011
Product Specification
LogiCORE IP 7 Series FPGAs Integrated Block v1.1 for PCI Express
the Transaction Layer implements a pipelined, full split-transaction protocol and manages credit-based
flow control of TLPs.
Configuration Management
The Configuration Management Layer supports generation and reception of System Management
Messages by communicating with the other layers and the user application. This layer contains the
device configuration space and other system functions. The Configuration layer implements
PCI/PCI-Express power management capabilities, and facilitates exchange of power management
messages, including support for PME event generation. Also implemented are user-triggered error
message generation, and user-read access to the device configuration space.
PCI Configuration Space
The configuration space consists of three primary parts. These include the following:
•
•
•
Legacy PCI v3.0 Type 0/1 Configuration Space Header
•
Type 0 Configuration Space Header, used by Endpoint applications
•
Type 1 Configuration Space Header, used by Root Port applications
Legacy Extended Capability Items
•
PCIe Capability Item
•
Power Management Capability Item
•
Message Signaled Interrupt (MSI) Capability Item
•
MSI-X Capability Item (optional)
PCIe Extended Capabilities
•
Device Serial Number Extended Capability (optional)
•
Virtual Channel Extended Capability (optional)
•
Vendor Specific Extended Capability (optional)
•
Advanced Error Reporting Extended Capability (optional)
•
Resizeable BAR Extended Capability (optional)
These capabilities, together with the standard Type 0/1 header, support software driven Plug and Play
initialization and configuration.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
The 7 Series FPGAs Integrated Block for PCI Express is included with the CORE Generator™ software.
No license key is required.
DS821 March 1, 2011
Product Specification
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5
LogiCORE IP 7 Series FPGAs Integrated Block v1.1 for PCI Express
References
The following documents provide supplemental information useful with this data sheet:
•
UG761: Xilinx AXI Reference Guide
•
AMBA AXI4-Stream Protocol Specification
Revision History
The following table shows the revision history for this document:
Date
Version
Description of Revisions
03/01/11
1.0
Initial Xilinx release. This release is for ISE 13.1 software and core release
v1.1.
Notice of Disclaimer
Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any
kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation
thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for
any implementation based on the Information. All specifications are subject to change without notice. XILINX
EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY
WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE. Except as stated herein, none of the Information may be copied, reproduced,
distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including,
but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent
of Xilinx.
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DS821 March 1, 2011
Product Specification
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