201601151306011767
PICO-IMX6
REV. A1 – VER. 1.00
September 30, 2015
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
REVISION HISTORY
Revision
1.00
Date
September 30, 2015
Originator
TechNexion
Notes
Initial Public release
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
TABLE OF CONTENTS
1. Introduction ............................................................................................................................................... 7
1.1. General Introduction ........................................................................................................................... 7
1.2. General Care and Maintenance ......................................................................................................... 8
1.3. Block Diagram .................................................................................................................................. 10
1.4. PICO Compute Module Compatibility............................................................................................... 11
1.5. Dimensional Drawing........................................................................................................................ 12
1.6. Component Location ........................................................................................................................ 13
2. Core Components ................................................................................................................................... 15
2.1. Freescale i.MX6 Cortex-A9 Multi-core Processor ............................................................................ 15
2.1.1. i.MX6 Memory Interfaces ........................................................................................................... 17
2.1.2. i.MX6 DMA Engine .................................................................................................................... 17
2.1.3. i.MX6 Video and Graphics Subsystems .................................................................................... 18
2.2. Memory ............................................................................................................................................. 19
2.2.1 SKHynix ...................................................................................................................................... 19
2.2.2. Micron ........................................................................................................................................ 20
2.3. eMMC Storage (PICO-IMX6-EMMC Only) ....................................................................................... 21
2.3.1. Sandisk iNAND SDIN7DP2 ....................................................................................................... 21
2.3.2. Kingston KE4CN2H5A ............................................................................................................... 22
2.3.3. Micro-SD Cardslot (PICO-IMX6-SD only) .................................................................................. 23
2.5. Broadcom BCM4339 WiFi/Bluetooth SiP Module ............................................................................ 24
3. PICO Compute Module Connector Interfaces ........................................................................................ 27
3.1 Ethernet ............................................................................................................................................. 27
3.2. HDMI (High Definition Multi-Media Interface) ................................................................................... 28
3.3. LVDS Interface ................................................................................................................................. 29
3.4. Digital Display Sub-System (DSS) or TTL Interface ........................................................................ 30
3.5. MIPI Display ..................................................................................................................................... 32
3.6. MIPI Camera .................................................................................................................................... 33
3.7. Audio Interface ................................................................................................................................. 34
3.8. PCI Express ...................................................................................................................................... 35
3.9. Serial ATA Interface ......................................................................................................................... 36
3.10. Universal Serial Bus (USB) Interface ............................................................................................. 37
3.11. SDIO/MMC Interface ...................................................................................................................... 38
3.12. CAN BUS Interface signals ............................................................................................................ 39
3.13. Universal Asynchronous Receiver/Transmitter (UART) Interface .................................................. 40
3.14. Serial Peripheral Interface (SPI) ..................................................................................................... 41
2
3.15. I C Bus............................................................................................................................................ 42
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.16. General Purpose Input/Output (GPIO) ........................................................................................... 43
3.17. Pulse Width Modulation (PWM) ..................................................................................................... 44
3.18. Manufacturing and Boot Control ..................................................................................................... 45
3.19. Input Power Requirements ............................................................................................................. 46
3.19.1. Power Management Signals .................................................................................................... 46
3.19.2. Power Sequence ..................................................................................................................... 47
4. PICO Compute Module Pin Assignment ................................................................................................. 48
5. Development Kits, Proto-type Components and Accessories ................................................................ 56
5.1. PICO-IMX6 Evaluation Kits .............................................................................................................. 56
5.1.1. PICO Evaluation Start Kit Pack Content .................................................................................... 56
5.2. PICO Compatible Displays ............................................................................................................... 57
5.2.1. LVDSEXPANDER Translation Board to Connect to LVDS Panels ........................................... 57
5.2.2. TDHJ070NA4RESKIT Resistive Touch Display Kit Pack Content ............................................ 58
5.2.3. TDHJ070NAPCAPKIT PCAP Touch Display Kit Pack Content ................................................ 59
5.3. Accessories ...................................................................................................................................... 60
5.3.1. EDMANTP150A138045D2450BK Pack Content....................................................................... 60
5.4. PICO Compute Module Product Ordering Part Numbers ................................................................ 61
5.4.1 Standard Part Numbers .............................................................................................................. 61
5.4.2. Custom Part Number Creation Rules ........................................................................................ 62
6. Important Notice ...................................................................................................................................... 63
7. DISCLAIMER .......................................................................................................................................... 64
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
LIST OF TABLES
Table 1 - EDM Compatibility Overview ....................................................................................................... 11
Table 2 - eMMC Signal Description ............................................................................................................ 23
Table 3 - SD Cardslot Signal Description ................................................................................................... 23
Table 4 - BCM4339 WiFi Signal Description............................................................................................... 25
Table 5 - BCM4339 Bluetooth Signal Description ...................................................................................... 26
Table 6 - Ethernet Signal Description ......................................................................................................... 27
Table 7 - HDMI Signal Description .............................................................................................................. 28
Table 8 - LVDS Signal Description ............................................................................................................. 29
Table 9 - TTL Display Signal Description.................................................................................................... 30
Table 10 - MIPI Display Signal Description ................................................................................................. 32
Table 11 - MIPI Camera Signal Description................................................................................................ 33
2
Table 12 - I S Audio Signal Description ...................................................................................................... 34
Table 13 - PCI Express Signal Description ................................................................................................. 35
Table 14 - Serial ATA Signal Description .................................................................................................... 36
Table 15 - USB Host Signal Description ..................................................................................................... 37
Table 16 - USB OTG Signal Description ..................................................................................................... 37
Table 17 - SDIO/MMC Interface Signal Description ................................................................................... 38
Table 18 - CAN Bus Signal Description ...................................................................................................... 39
Table 19 - UART Signal Description ........................................................................................................... 40
Table 20 - SPI Channel Signal Description ................................................................................................. 41
2
Table 21 - I C Bus Signal Description ......................................................................................................... 42
Table 22 - GPIO Signal Description ............................................................................................................ 43
Table 23 - PWM Signal Description ........................................................................................................... 44
Table 24 - Boot Selection Pins .................................................................................................................... 45
Table 25 - Boot Signal Configuration .......................................................................................................... 45
Table 26 - Input Power Signals ................................................................................................................... 46
Table 27 - Power Management Signals ...................................................................................................... 46
Table 28 - Input Power Sequencing for AT based configurations .............................................................. 47
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
LIST OF FIGURES
Figure 1 - PICO-IMX6-SD Block Diagram ................................................................................................... 10
Figure 2 - PICO-IMX6-EMMC Block Diagram............................................................................................. 10
Figure 3 – PICO-IMX6 Compatibility Chart ................................................................................................. 11
Figure 4 - PICO-IMX6 Dimensional Drawing .............................................................................................. 12
Figure 5 - PICO-IMX6 Top view .................................................................................................................. 13
Figure 6 - PICO-IMX6-SD Bottom view ...................................................................................................... 13
Figure 7 - PICO-IMX6-EMMC Bottom view ................................................................................................ 14
Figure 8 – Freescale i.MX6 Processor Blocks ............................................................................................ 15
Figure 9 – Freescale i.MX6 Processor Scalability Overview (Solo/Duallite/Dual/Quad) ............................ 16
Figure 10 - PICO-IMX6 Antenna u.FL Connector Location ........................................................................ 24
Figure 11 - Input Power sequence for AT based configurations ................................................................. 47
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
1. Introduction
1.1. General Introduction
The PICO-IMX6 is a high performance highly integrated PICO Compute Module designed around the
Freescale i.MX6 Multicore ARM Cortex-A9. The PICO-IMX6 provides an ideal building block that easily
integrates with a wide range of target markets requiring rich multimedia functionality, powerful graphics
and video capabilities, as well as high-processing power, compact, cost effective and with low power
consumption.
The modular approach offered by the PICO Compute Module gives your project scalability, fast time to
market and upgradability while reducing engineering risk and maintain a competitive total cost of
ownership.
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
1.2. General Care and Maintenance
Your device is a product of superior design and craftsmanship and should be treated with care.
The following suggestions will help you.
 Keep the device dry. Precipitation, humidity, and all types of liquids or moisture can contain
minerals that will corrode electronic circuits. If your device does get wet, allow it to dry completely.
 Do not use or store the device in dusty, dirty areas. Its moving parts and electronic components
can be damaged.
 Do not store the device in hot areas. High temperatures can shorten the life of electronic devices,
damage batteries, and warp or melt certain plastics.
 Do not store the device in cold areas. When the device returns to its normal temperature,
moisture can form inside the device and damage electronic circuit boards.
 Do not attempt to open the device.
 Do not drop, knock, or shake the device. Rough handling can break internal circuit boards and
fine mechanics.
 Do not use harsh chemicals, cleaning solvents, or strong detergents to clean the device.
 Do not paint the device. Paint can clog the moving parts and prevent proper operation.
 Unauthorized modifications or attachments could damage the device and may violate regulations
governing radio devices.
These suggestions apply equally to your device, battery, charger, or any enhancement. If any device is
not working properly, take it to the nearest authorized service facility for service.
Regulatory information
Disposal of Waste Equipment by Users in Private Household in the European Union
This symbol on the product or on its packaging indicates that this product must not be
disposed of with your other household waste. Instead, it is your responsibility to dispose
of your waste equipment by handing it over to a designated collection point for the
recycling of waste electrical and electronic equipment. The separate collection and
recycling of your waste equipment at the time of disposal will help to conserve natural
resources and ensure that it is recycled in a manner that protects human health and the
environment. For more information about where you can drop off your waste equipment
for recycling, please contact your local city office, your household waste disposal service or the shop
where you purchased the product.
We hereby declare that the product is in compliance with the essential requirements and
other relevant provisions of European Directive 1999/5/EC (radio equipment and
telecommunications terminal equipment Directive).
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
Federal Communications Commission (FCC) Unintentional emitter per FCC Part 15
This device has been tested and found to comply with the limits for a Class B digital
device, pursuant to Part 15 of the FCC rules. These limits are designed to provide
reasonable protection against harmful interference in a residential installation. This
equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instructions, may cause harmful interference
to radio or television reception. However, there is no guarantee that interference will
not occur in a particular installation. If this equipment does cause interference to radio and television
reception, which can be determined by turning the equipment off and on, the user is encouraged to try to
correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna
■ Increase the separation between the equipment and receiver
■ Connect the equipment to an outlet on a different circuit from that to which the receiver is connected
■ Consult the dealer or an experienced radio/TV technician for help.
WARNING! To reduce the possibility of heat-related injuries or of overheating the
computer, do not place the computer directly on your lap or obstruct the computer air
vents. Use the computer only on a hard, flat surface. Do not allow another hard surface,
such as an adjoining optional printer, or a soft surface, such as pillows or rugs or
clothing, to block airflow. Also, do not allow the AC adapter to contact the skin or a soft
surface, such as pillows or rugs or clothing, during operation. The computer and the AC
adapter comply with the user-accessible surface temperature limits defined by the International Standard
for Safety of Information Technology Equipment (IEC 60950).
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
1.3. Block Diagram
Figure 1 - PICO-IMX6-SD Block Diagram
Figure 2 - PICO-IMX6-EMMC Block Diagram
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
1.4. PICO Compute Module Compatibility
®
The PICO-IMX6 is function compatible with Intel Edison and adds additional multimedia I/O Interfaces on
two additional expansion interfaces.
Figure 3 – PICO-IMX6 Compatibility Chart
Table 1 - EDM Compatibility Overview
Interface
LAN
LVDS
HDMI
TTL Display
PCIe
SATA
USB Host
USB OTG
2
IS
CAN Bus
UART
SDIO
SPI
2
IC
GPIO
PWM
Description
1 Gigabit Ethernet Signaling
1 single channel 18/24 bit
1 HDMI ver.1.4 compatible
1 TTL 18/24 bit Display
1 Lane PCIe 2.0
Not available (Check PICO-IMX6POP for availability)
1 USB 2.0 Host port
1 USB 2.0 OTG port (possible to use in Host mode)
2
2 Independent I S interfaces
2 FlexCAN CAN 2.0B protocol compliant interfaces
1 UART (2 wire)
1 UART (4 wire)
1 SDIO interface 4 bit
1 SPI interfaces with 2 chip selects
2
3 independent I C channels
13 dedicated GPIO’s available
4 PWM available
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
1.5. Dimensional Drawing
®
The PICO-IMX6 Compute Module is partly size compatible with Intel Edison and adds several additional
I/O expansion interfaces on an enlarged footprint.
2D and 3D files can be obtained from the www.technexion.com homepage.
Figure 4 - PICO-IMX6 Dimensional Drawing
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
1.6. Component Location
Figure 5 - PICO-IMX6 Top view
1
2
3
Item
1
3
Description
Freescale i.MX6 Processor
BCM4339 WiFi/Bluetooth IC
4
Item
2
4
Description
Memory IC
Antenna connector
Figure 6 - PICO-IMX6-SD Bottom view
5
1
3
2
4
Item
1
3
5
Description
Memory IC
Intel® Edison Compatible Connector
Expansion Connector 2
Item
2
4
Description
Micro-SD Slot
Expansion Connector 1
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
Figure 7 - PICO-IMX6-EMMC Bottom view
5
1
3
2
4
Item
1
3
5
Description
Memory IC
Intel® Edison Compatible Connector
Expansion Connector 2
Item
2
4
Description
eMMC Storage IC
Expansion Connector 1
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
2. Core Components
2.1. Freescale i.MX6 Cortex-A9 Multi-core Processor
The Freescale i.MX6 processor is an implementation of the Single/Dual/Quad ARM Cortex™-A9 core,
which operates at frequencies up to 1.2 GHz. The i.MX6 provides a variety of interfaces and supports the
following main features:
 Single / Dual / Quad Core ARM Cortex™-A9. Core configuration is symmetric, where each core
includes:
o 32 KByte L1 Instruction Cache
o 32 KByte L1 Data Cache
o Private Timer and Watchdog
o Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
 Level 2 Cache—Unified instruction and data (up to 1 MByte)
 General Interrupt Controller (GIC) with 128 interrupt support
 Global Timer
 Snoop Control Unit (SCU)
 NEON MPE coprocessor:
o SIMD Media Processing Architecture
o NEON register file with 32x64-bit general-purpose registers
o NEON Integer execute pipeline (ALU, Shift, MAC)
o NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
o NEON load/store and permute pipeline
 Integrated Power Management unit:
o Temperature Sensor for monitoring the die temperature
o DVFS techniques for low power modes
o Flexible clock gating control scheme
 Multimedia Hardware Accelerators
Figure 8 – Freescale i.MX6 Processor Blocks
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
Figure 9 – Freescale i.MX6 Processor Scalability Overview (Solo/Duallite/Dual/Quad)
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
2.1.1. i.MX6 Memory Interfaces



The memory system consists of the following components:
o Level 1 Cache—32 KB Instruction, 32 KB Data cache per core
o Level 2 Cache—Unified instruction and data (1 MByte)
On-Chip Memory:
o Boot ROM, including HAB (96 KB)
o Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)
o Secure/non-secure RAM (16 KB)
External memory interfaces:
o 16-bit, 32-bit, and 64-bit DDR3-1066 and LV-DDR3-1066
o 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
o BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 32 bit.
2.1.2. i.MX6 DMA Engine
The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by offloading the various cores in dynamic data routing. It has the following features:
 Powered by a 16-bit Instruction-Set micro-RISC engine
 Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels
 48 events with total flexibility to trigger any combination of channels
 Memory accesses including linear, FIFO, and 2D addressing
 Shared peripherals between ARM and SDMA
 Very fast Context-Switching with 2-level priority based preemptive multi-tasking
 DMA units with auto-flush and prefetch capability
 Flexible address management for DMA transfers (increment, decrement, and no address
changes on source and destination address)
 DMA ports can handle unit-directional and bi-directional flows (copy mode)
 Up to 8-word buffer for configurable burst transfers
 Support of byte-swapping and CRC calculations
 Library of Scripts and API is available
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
2.1.3. i.MX6 Video and Graphics Subsystems
The PICO-IMX6 video graphics subsystem consists of the following i.MX6 sub-blocks.



VPU: A multi-standard high performance video codec engine supporting encode/decode
operations of the following:
o Decoding: H.264 BP/CBP/MP/HP, VC-1 SP/MP/AP, MPEG-4 SP/ASP, H.263 P0/P3,
MPEG-1/2 MP, Divx (Xvid) HP/PP/HTP/HDP, VP8 (1280x720), AVS, H.264-MVC
(1280x720), MJPEG BP (max. 8192x8192) up to full-HD 1920x1088 @30fps plus D1
@30fps.
o Encoding: H.264 BP/CBP, MPEG-4 SP, H.263 P0/P3, MJPEG BP (max. 192x8192) up to
full-HD [email protected]
GPU2Dv2: Hardware acceleration of 2D graphics (Bit BLT and Stretch BLT). Based on the
Vivante GC320 IP core.
GPUVG: An OpenVG 1.1 Graphics Processing Unit providing hardware acceleration of vector
graphics. Based on the Vivante GC355 IP core
Additionally the PICO-IMX6 incorporates the following 3D GPU engine
The PICO-IMX6 featuring an i.MX6 Dual or Quad processor (Availability restrictions apply):

GPU3Dv4: A 3D GPU (Vivante GC2000), compliant with OpenGL ES2.0, OpenGL ES1.1 and
OpenVG 1.1.
The PICO-IMX6 featuring an i.MX6 Duallite or Solo processor:

GPU3Dv5: A 3D GPU (Vivante GC880), compliant with OpenGL ES2.0, OpenGL ES1.1 and
OpenVG 1.1.
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
2.2. Memory
The PICO-IMX6 integrates Double Data Rate III (DDR3) Synchronous DRAM in a single (32 bit) channel
configuration.
The following memory chips have been validated and tested on the PICO-IMX6 Compute Module:
2.2.1 SKHynix
SKHynix CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory
applications which requires large memory density and high bandwidth. SKHynix DDR3 SDRAMs offer
fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses
and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes
and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are
internally pipelined and 8-bit prefetched to achieve very high bandwidth.
SK Hynix memory features:
 VDD=VDDQ=1.5V +/- 0.075V
 Fully differential clock inputs (CK, CK) operation
 Differential Data Strobe (DQS, DQS)
 On chip DLL align DQ, DQS and DQS transition with CK transition
 DM masks write data-in at the both rising and falling edges of the data strobe
 All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
 Programmable CAS latency 5, 6, 7, 8, 9, 10 and 11, 13 supported
 Programmable additive latency 0, CL-1, and CL-2 supported
 Programmable CAS Write latency (CWL) = 5, 6, 7, 8
 Programmable burst length 4/8 with both nibble sequential and interleave mode
 BL switch on the fly
 8banks
 Average Refresh Cycle (Tcase of 0o C~ 95 o C)
- 7.8 μs at 0 o C ~ 85 o C
- 3.9 μs at 85 o C ~ 95 o C
 • Auto Self Refresh supported
 JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16)
 Driver strength selected by EMRS
 Dynamic On Die Termination supported
 Asynchronous RESET pin supported
 ZQ calibration supported
 TDQS (Termination Data Strobe) supported (x8 only)
 Write Levelization supported
 8 bit pre-fetch
More information can be retrieved from SKHynix:
Part number:
H5TQ2G63FFR-PBC preferred part 2Gbit
H5TQ2G63DFR-H9C backup part 2Gbit
H5TQ4G63FFR-PBC preferred part 4Gbit
H5TQ4G63DFR-H9C backup part 4Gbit
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
2.2.2. Micron
Micron 1.35V DDR3L SDRAM device is a low-voltage version of the 1.5V DDR3 SDRAM device. Unless
stated otherwise, the DDR3L SDRAM device meets the functional and timing specifications listed in the
equivalent density standard or automotive DDR3 SDRAM data sheet located on www.micron.com.
Micron memory features:
 VDD = VDDQ = 1.35V (1.283–1.45V)
 Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
 Differential bidirectional data strobe
 8n-bit prefetch architecture
 Differential clock inputs (CK, CK#)
 8 internal banks
 Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
 Programmable CAS (READ) latency (CL)
 Programmable posted CAS additive latency (AL)
 Programmable CAS (WRITE) latency (CWL)
 Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
 Selectable BC4 or BL8 on-the-fly (OTF)
 Self-refresh mode
 TC of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
 Self-refresh temperature (SRT)
More information can be retrieved from Micron:
Part number:
MT41K128M16JT-125 IT:K for general configurations 2Gbit
MT41K256M16HA-125 IT:E for general configurations 4Gbit
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
2.3. eMMC Storage (PICO-IMX6-EMMC Only)
The PICO-IMX6 can be ordered with onboard eMMC storage in different configurations and capacity.
The onboard eMMC device is connected on the SD3 pins of the i.MX6 processor in an 8 bit width
configuration.
The following eMMC chips have been validated and tested on the EDM1-CF-IMX6 System-on-Module:
2.3.1. Sandisk iNAND SDIN7DP2
iNAND Ultra is an Embedded Flash Drive (EFD) designed for mobile handsets and consumer electronic
devices. iNAND Ultra is a hybrid device combining an embedded thin flash controller and standard MLC
NAND flash memory, with an industry standard e.MMC 4.511 interface. Empowered with a new
e.MMC4.51 feature set such as Power Off Notifications and Packed commands, as well as legacy
e.MMC4.41 features such as Boot and RPMB partitions, HPI, and HW Reset the iNAND Ultra e.MMC is
the optimal device for reliable code and data storage.
iNAND provides mass storage of up to 128GB in JEDEC compatible form factors, with low power
consumption and high performance.
In addition to the high reliability and high system performance, it offers plug-and-play integration and
support for multiple NAND technology transitions, as well as features such as advanced power
management scheme.
iNAND Ultra uses advanced Multi-Level Cell (MLC) NAND flash technology, enhanced by embedded
flash management software running as firmware on the flash controller.
The architecture and embedded firmware fully emulates a hard disk to the host processor, enabling
read/write operations identical to a standard, sector-based hard drive. In addition, SanDisk firmware
employs patented methods, such as virtual mapping, dynamic and static wear-levelling, and automatic
block management to ensure high data reliability and maximize flash life expectancy.
SanDisk iNAND Extreme, with MMC interface, features include the following:
 Memory controller and NAND flash
 Complies with e.MMC Specification Ver. 4.512
 Mechanical design complies with JEDED MO-276C Specification
 Offered in two TFBGA packages of e.MMC 4.513
 Operating temperature range: -25C° to +85C°
 Dual power system
 Core voltage (VCC) 2.7-3.6v
 I/O (VCCQ) voltage 2.7-3.6v
 Supports three data bus widths: 1bit (default), 4bit, 8bit.
 Variable clock frequencies of 0-20 MHz, 0-26 MHz (default), 0-52 MHz (high-speed)
 Up to 104 MB/sec bus transfer rate, using 8 parallel data lines at 52 MHz, DDR Mode
 Correction of memory field errors
 Designed for portable and stationary applications that require high performance and reliable data
storage
More information can be retrieved from SanDisk:
Part number:
SDIN7DP2 for general configurations
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PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
2.3.2. Kingston KE4CN2H5A
Kingston e•MMC™ products follow the JEDEC e•MMC™ 4.5 standard. It is an ideal universal storage
solutions for many electronic devices, including smartphones, tablet PCs, PDAs, eBook readers, digital
cameras, recorders, MP3, MP4 players, electronic learning products, digital TVs and set-top boxes.
E•MMC™ encloses the MLC NAND and e•MMC™ controller inside as one JEDEC standard package,
providing a standard interface to the host. The e•MMC™ controller directly manages NAND flash,
including ECC, wear-leveling, IOPS optimization and read sensing.
The Kingston NAND Device is fully compatible with the JEDEC Standard Specification No.JESD84-B45.
This datasheet describes the key and specific features of the Kingston e•MMC™ Device. Any additional
information required interfacing the Device to a host system and all the practical methods for device
detection and access can be found in the proper sections of the JEDEC Standard Specification.
Kingston e•MMC™, with MMC interface, features include the following:
 Packaged NAND flash memory with e•MMC™ 4.5 interface
 Compliant with e•MMC™ Specification Ver.4.4, 4.41 & 4.5
 Bus mode
o High-speed e•MMC™ protocol
o Provide variable clock frequencies of 0-200MHz.
o Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
 Supports three different data bus widths : 1 bit(default), 4 bits, 8 bits
o Data transfer rate: up to 52Mbyte/s (using 8 parallel data lines at 52 MHz)
o Single data rate : up to 200Mbyte/s @ HS200(Host clock @ 200MHz)
o Dual data rate : up to 104Mbyte/s @ 52MHz
 Supports (Alternate) Boot Operation Mode to provide a simple boot sequence method
 Supports SLEEP/AWAKE (CMD5).
 Host initiated explicit sleep mode for power saving
 Enhanced Write Protection with Permanent and Partial protection options
 Supports Multiple User Data Partition with Enhanced User Data Area options
 Supports Background Operations & High Priority Interrupt (HPI)
 Supports enhanced storage media feature for better reliability
 Operating voltage range :
o VCCQ = 1.8 V/3.3 V
o VCC = 3.3 V
 Error free memory access
o Internal error correction code (ECC) to protect data communication
o Internal enhanced data management algorithm
o Solid protection of sudden power failure safe-update operations for data content
 Security
o Support secure bad block erase commands
o Enhanced write Protection with permanent and partial protection options
More information can be retrieved from Kingston:
Part number:
KE4CN2H5A for general configurations
Page 22 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
Table 2 - eMMC Signal Description
CPU
BALL
E14
F14
A15
B15
D13
C13
E13
F13
B13
D14
D15
CPU PAD NAME
Signal
SD3_DAT0
SD3_DAT1
SD3_DAT2
SD3_DAT3
SD3_DAT4
SD3_DAT5
SD3_DAT6
SD3_DAT7
SD3_CMD
SD3_CLK
SD3_RST
eMMC_DATA0
eMMC_DATA1
eMMC_DATA2
eMMC_DATA3
eMMC_DATA4
eMMC_DATA5
eMMC_DATA6
eMMC_DATA7
eMMC_CMD
eMMC_CLK
eMMC_RST
V
I/O
Description
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
MMC/SDIO Data bit 0
MMC/SDIO Data bit 1
MMC/SDIO Data bit 2
MMC/SDIO Data bit 3
MMC/SDIO Data bit 4
MMC/SDIO Data bit 5
MMC/SDIO Data bit 6
MMC/SDIO Data bit 7
MMC/SDIO Command
MMC/SDIO Clock
MMC/SDIO Reset Signal
2.3.3. Micro-SD Cardslot (PICO-IMX6-SD only)
Kingston e•MMC™ products follow the JEDEC e•MMC™ 4.5 standard. It is an ideal universal storage
solutions for many electronic devices, including smartphones, tablet PCs, PDAs, eBook readers, digital
cameras, recorders, MP3, MP4 players, electronic learning products, digital TVs and set-top boxes.
E•MMC™ encloses the MLC NAND and e•MMC™ controller inside as one JEDEC standard package,
providing a standard interface to the host. The e•MMC™ controller directly manages NAND flash,
including ECC, wear-leveling, IOPS optimization and read sensing.
Table 3 - SD Cardslot Signal Description
CPU
BALL
E14
F14
A15
B15
B13
D14
T1
CPU PAD NAME
Signal
SD3_DAT0
SD3_DAT1
SD3_DAT2
SD3_DAT3
SD3_CMD
SD3_CLK
GPIO_2
SD3_DATA0
SD3_DATA1
SD3_DATA2
SD3_DATA3
SD3_CMD
SD3_CLK
SD3_CD
V
I/O
Description
3V3
3V3
3V3
3V3
3V3
3V3
3V3
I/O
I/O
I/O
I/O
I/O
O
I/O
MMC/SDIO Data bit 0
MMC/SDIO Data bit 1
MMC/SDIO Data bit 2
MMC/SDIO Data bit 3
MMC/SDIO Command
MMC/SDIO Clock
MMC/SDIO Card Detect
Page 23 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
2.5. Broadcom BCM4339 WiFi/Bluetooth SiP Module
The PICO-IMX6 can be ordered with an optional onboard WiFI/Bluetooth SIP module. The 802.11ac + BT
SiP module is a small sized BGA mounted module that provides full function of 802.11ac and Bluetooth
class 4.0 +HS
The small size & low profile physical design make it easier for system design to enable high performance
wireless connectivity without space constrain. The low power consumption and excellent radio
performance make it the best solution for OEM customers who require embedded 802.11ac Wi-Fi +
Bluetooth features.
The SIP module is based on Broadcom 4339 chipset which is a WiFi + BT SOC. The Radio architecture &
high integration MAC/BB chip provide excellent sensitivity with rich system performance.
In addition to WEP 64/128, WPA and TKIP, AES, CCX is supported to provide the latest security
requirement on your network.
The SiP module is designed to operate with a single antenna for WiFi and Bluetooth to be connected to
the u.FL connector available on the PICO-IMX6.
For the software and driver development, TechNexion provides extensive technical document and
reference software code for the system integration under the agreement of Broadcom International Ltd.
Figure 10 - PICO-IMX6 Antenna u.FL Connector Location
ANTENNA
Page 24 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
Table 4 - BCM4339 WiFi Signal Description
i.MX6
BALL
A22
E20
A23
B22
F19
C21
R2
R3
PAD NAME
Signal
SD2_DAT0
SD2_DAT1
SD2_DAT2
SD2_DAT3
SD2_CMD
SD2_CLK
GPIO_16
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_CMD
SDIO_CLK
WL_HOST_WAKE
GPIO_7
WL_REG_ON
I/O
Description
I/O
I/O
I/O
I/O
I/O
I/O
O
MMC/SDIO Data bit 0
MMC/SDIO Data bit 1
MMC/SDIO Data bit 2
MMC/SDIO Data bit 3
MMC/SDIO Command
MMC/SDIO Clock
General purpose interface pin. This pin is
high-impedance on power up and reset.
Subsequently, it becomes an input or
output through software control. This pin
has a programmable weak pull-up/down.
Used by PMU (OR-gated with
BT_REG_ON) to power up or power
down internal BCM4339 regulators used
by the WLAN section. This pin is also a
low-asserting reset for WLAN only
(Bluetooth is not affected by this pin).
I
Page 25 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
Table 5 - BCM4339 Bluetooth Signal Description
i.MX6
BALL
D19
PAD NAME
Signal
I/O
Description
SD4_DAT7
“UART2_TXD”
SD4_DAT4
“UART2_RXD”
SD4_DAT6
“UART2_CTS”
BT_UART_RXD
I
BT_UART_TXD
O
BT_UART_CTS
I/O
C19
SD4_DAT5
“UART2_RTS”
BT_UART_RTS
I/O
V6
BT_PCM_IN
I
BT_PCM_OUT
O
PCM data output
BT_PCM_CLK
I/O
BT_PCB_SYNC
I/O
R6
KEY_ROW0
“AUD5_TXD”
KEY_ROW1
“AUD5_RXD”
KEY_COL0
“AUD5_TXC”
KEY_COL1
“AUD5_TXFS”
GPIO_4
Bluetooth UART Serial Input. Serial data
input for the HCI UART Interface
Bluetooth UART Serial Output. Serial data
output for the HCI UART Interface.
Bluetooth UART Clear to Send. Activelow clear-to-send signal for the HCI UART
interface.
Bluetooth UART Request to Send. Activelow request-to-send signal for the HCI
UART interface.
PCM data input
BT_WAKE
I
R1
R4
GPIO_17
GPIO_5
BT_RST_N
BT_HOST_WAKE
I
O
E18
B20
U6
W5
U7
PCM clock
PCM sync signal
Bluetooth device wake-up: Signal from
the host to the module indicating that the
host requires attention.
• Asserted: Bluetooth device must wakeup or remain awake.
• Deserted: Bluetooth device may sleep
when sleep criteria are met.
The polarity of this signal is software
configurable and can be asserted high or
low.
Low asserting reset for BT core
Host UART wake up. Signal from the
module to the host indicating that the
module requires Attention.
• Asserted: Host device must wake-up or
remain awake.
• Deserted: Host device may sleep when
sleep criteria are met.
The polarity of this signal is software
configurable and can be asserted high or
low.
Page 26 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3. PICO Compute Module Connector Interfaces
3.1 Ethernet
The PICO-IMX6 implements a triple speed 10/100/1000 Mbit/s Ethernet MAC compliant with the
IEEE802.3-2002 standard. The MAC layer provides compatibility with half- or full-duplex 10/100 Mbit/s
Ethernet LANs and full-duplex gigabit Ethernet LANs.
The Ethernet MAC supports the following features:







Implements the full 802.3 specification with preamble/SFD generation, frame padding generation,
CRC generation and checking
Supports zero-length preamble
Dynamically configurable to support 10/100 Mbit/s and gigabit operation
Supports 10/100 Mbit/s full-duplex and configurable half-duplex operation
Supports gigabit full-duplex operation
Compliant with the AMD magic packet detection with interrupt for node remote power
management
Seamless interface to commercial ethernet PHY devices via one of the following:
o 4-bit Media Independent Interface (MII) operating at 2.5/25 MHz.
o 4-bit non-standard MII-Lite (MII without the CRS and COL signals) operating at 2.5/25
MHz.
o 2-bit Reduced MII (RMII) operating at 50 MHz.
o (Double data rate) 4-bit Reduced GMII (RGMII) operating at 125 MHz.
For additional details, please refer to chapter 23 of the “i.MX6 Reference Manual”.
Table 6 - Ethernet Signal Description
PIN
CPU
BALL
X1_33
CPU PAD NAME
Signal
V
V20
ENET_MDC
RGMII_MDC
3V3
X1_35
X1_37
X1_39
V23
W22
V21
ENET_MDIO
ENET_RXD1
ENET_TX_EN
RGMII_MDIO
RGMII_nRST
RGMII_INT
3V3
3V3
3V3
X1_41
V22
ENET_REF_CLK
RGMII_REF_CLK
3V3
X1_43
X1_45
X1_49
X1_51
X1_53
X1_55
X1_57
X1_61
X1_63
X1_65
X1_67
X1_69
C23
D22
D21
C22
F20
E21
A24
B25
C24
B23
B24
D23
RGMII_TX_CTL
RGMII_RX_CTL
RGMII_TXC
RGMII_TD0
RGMII_TD1
RGMII_TD2
RGMII_TD3
RGMII_RXC
RGMII_RD0
RGMII_RD1
RGMII_RD2
RGMII_RD3
RGMII_TXEN
RGMII_RXDV
RGMII_TXCLK
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
RGMII_RXCLK
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
1V5
1V5
1V5
1V5
1V5
1V5
1V5
1V5
1V5
1V5
1V5
1V5
I/O
Description
O
O
O
O
O
I
I
I
I
I
Management data clock
reference
Management data
Ethernet reset
Ethernet interrupt output
Synchronous Ethernet
recovered clock
RGMII transmit enable
RGMII receive data valid
RGMII transmit clock
RGMII transmit data 0
RGMII transmit data 1
RGMII transmit data 2
RGMII transmit data 3
RGMII receive clock
RGMII receive data 0
RGMII receive data 1
RGMII receive data 2
RGMII receive data 3
Page 27 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.2. HDMI (High Definition Multi-Media Interface)
The HDMI interface available with PICO-IMX6 is based on the “HDMI transmitter” & “HDMI 3D Tx PHY”
integrated into the i.MX6 processor. The “HDMI transmitter” combines video/display data from the IPU,
Audio data from i.MX6 memory & control/status data from the ARM complex, into TMDS data & clock
channels. The “HDMI 3D TX PHY” transmits the combined data by means of 3 TMDS data pairs and a
2
TMDS clock pair together with the DDC/I C configuration signals to the EDM connector.
The HDMI 3D TX PHY integrated into the i.MX6 processor supports the following standards & features:
 High-Definition Multimedia Interface Specification, Version 1.4a
 Digital Visual Interface, Revision 1.0
 HDMI Compliance Test Specification, Version 1.4a
 Support for up to 720p at 100Hz and 720i at 200Hz or 1080p at 60Hz and 1080i/720i at 120Hz
HDTV display resolutions and up to QXGA graphic display resolutions.
 Support for 4k x 2k and 3D video formats
 Support for up to 16-bit Deep Color modes
For additional details, please refer to chapters 32 and 33 of the “i.MX6 Reference Manual”.
Table 7 - HDMI Signal Description
PIN
CPU
BALL
X2_16
CPU PAD NAME
Signal
V
I/O
K6
HDMI_D0P
HDMI1_D0P
3V3
O
X2_18
K5
HDMI_D0M
HDMI1_D0M
3V3
O
X2_22
J4
HDMI_D1P
HDMI1_D1P
3V3
O
X2_24
J3
HDMI_D1M
HDMI1_D1M
3V3
O
X2_28
K4
HDMI_D2P
HDMI1_D2P
3V3
O
X2_30
K3
HDMI_D2M
HDMI1_D2M
3V3
O
X2_34
J6
HDMI_CLKP
HDMI1_CLKP
3V3
O
X2_36
J5
HDMI_CLKM
HDMI1_CLKM
3V3
O
X2_40
H19
EIM_A25
HDMI1_CEC
1V8
I/O
X2_42
K1
HDMI_HPD
HDMI1_HPD
3V3
I
X2_13
X2_15
U5
T7
KEY_COL3
KEY_ROW3
I2C2_SCL
I2C2_SDA
3V3
3V3
I/O
I/O
Description
HDMI differential pair 0
positive signal
HDMI differential pair 0
negative signal
HDMI differential pair 1
positive signal
HDMI differential pair 1
negative signal
HDMI differential pair 2
positive signal
HDMI differential pair 2
negative signal
HDMI differential pair clock
positive signal
HDMI differential pair clock
negative signal
HDMI Consumer Electronics
Control
HDMI/DP Hot plug detection
signal that serves as an
interrupt request
2
I C bus clock line
2
I C bus data line
Page 28 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.3. LVDS Interface
The PICO-IMX6 is equipped with single LVDS Display interfaces. The LVDS Display Bridge (LDB)
connects the IPU (Image Processing Unit) to an External LVDS Display Interface. The purpose of the
LDB is to support flow of synchronous RGB data from the IPU to external display devices through LVDS
interface.
The LDB output complies with the EIA-644-A standard and supports the following features:






Connectivity to relevant devices - Displays with LVDS receivers.
Arranging the data as required by the external display receiver and by LVDS display standards.
Synchronization and control capabilities.
Data input interface (inside the i.MX6 processor)
o RGB Data of 18 or 24 bits
o Pixel clock
o Control signals: HSYNC, VSYNC, DE, and 1 additional optional general purpose control
2
(I C)
Single channel output data output interface
o Total of up to 28 bits per data interface are transferred per pixel clock cycle.
Data Rates
o Overall: LDB supports rates needed by WUXGA 16:10 aspect ratio (1920 x 1200 @ 60
frames per second, data rate supported up to 170 MHz)
o For single input data interface case: Up to 170 MHz pixel clock (WUXGA 1920x1200)
o For dual input data interface case: Up to 85 MHz per interface. (WXGA 1366x768 @ 60
frames per second, 35% blanking).
For additional details, please refer to chapter 39 of the “i.MX6 Reference Manual”.
Table 8 - LVDS Signal Description
PIN
CPU
BALL
X1_3
CPU PAD NAME
Signal
V
I/O
W2
LVDS0_TX3_N
LVDS0_TX3_N
2V5
O
X1_4
D18
SD4_DAT0
LVDS0_BLT_EN
3V3
O
X1_5
W1
LVDS0_TX3_P
LVDS0_TX3_P
2V5
O
X1_6
X1_9
X1_11
B19
V4
V3
SD4_DAT1
LVDS0_CLK_N
LVDS0_CLK_P
LVDS0_BLT_CTRL
LVDS0_CLK_N
LVDS0_CLK_P
3V3
2V5
2V5
O
O
O
X1_15
V2
LVDS0_TX2_N
LVDS0_TX2_N
2V5
O
X1_17
V1
LVDS0_TX2_P
LVDS0_TX2_P
2V5
O
X1_21
U4
LVDS0_TX1_N
LVDS0_TX1_N
2V5
O
X1_23
U3
LVDS0_TX1_P
LVDS0_TX1_P
2V5
O
X1_27
U2
LVDS0_TX0_N
LVDS0_TX0_N
2V5
O
X1_29
U1
LVDS0_TX0_P
LVDS0_TX0_P
2V5
O
Description
LVDS differential pair 3
negative signal
LVDS panel backlight enable
LVDS differential pair 3
positive signal
LVDS panel backlight control
LVDS clock negative signal
LVDS clock positive signal
LVDS differential pair 2
negative signal
LVDS differential pair 2
positive signal
LVDS differential pair 1
negative signal
LVDS differential pair 1
positive signal
LVDS differential pair 0
negative signal
LVDS differential pair 0
positive signal
NOTE: LVDS_BLT_CTRL is also used as PWM3_1V8 signal.
Page 29 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.4. Digital Display Sub-System (DSS) or TTL Interface
The Parallel Display interface of PICO-IMX6 is derived directly from the DI0 port of the IPU, effectively
bypassing all the i.MX6 integrated display bridges.
Each DI port supports the following:
 Compatible with MIPI-DPI standard.
 Supports BT.656 (8-bit) and BT.1120 (16-bit) protocols.
 Supports HDTV standards SMPTE274 (1080i/p) and SMPTE296 (720p)
 Scan Order: progressive or interlaced
 Synchronization:
 Programmable horizontal and vertical synchronization output signals
 Data enabling output signal
 The combined data rate for the two DI ports is up to 240 MP/sec
 Supported pixel data formats:
 RGB - color depth fully configurable; up to 8 bits/value (color component)
 YUV 4:2:2, 8 bits/value
 All mandatory formats in MIPI DBI, DPI and DSI
For examples of valid mappings, please refer to the “IPU Display Interface Signal Mapping” chapter of the
i.MX6 datasheet.
Table 9 - TTL Display Signal Description
X1_8
X1_10
X1_12
X1_14
X1_16
X1_18
X1_20
X1_22
X1_24
X1_26
X1_28
X1_30
X1_32
X1_34
X1_36
X1_38
X1_40
X1_42
X1_44
X1_46
X1_48
X1_50
X1_52
X1_54
X1_56
CPU
BALL
W24
V24
T20
U22
U23
V25
U24
T21
T22
U25
R20
T24
T23
R21
T25
R22
R24
R23
R25
P20
P21
P23
P22
P24
P25
X1_58
N25
PIN
CPU PAD NAME
Signal
V
I/O
Description
DISP0_DAT23
DISP0_DAT22
DISP0_DAT21
DISP0_DAT20
DISP0_DAT19
DISP0_DAT18
DISP0_DAT17
DISP0_DAT16
DISP0_DAT15
DISP0_DAT14
DISP0_DAT13
DISP0_DAT12
DISP0_DAT11
DISP0_DAT10
DISP0_DAT9
DISP0_DAT8
DISP0_DAT7
DISP0_DAT6
DISP0_DAT5
DISP0_DAT4
DISP0_DAT3
DISP0_DAT2
DISP0_DAT1
DISP0_DAT0
DI0_PIN4
DISP0_DAT23
DISP0_DAT22
DISP0_DAT21
DISP0_DAT20
DISP0_DAT19
DISP0_DAT18
DISP0_DAT17
DISP0_DAT16
DISP0_DAT15
DISP0_DAT14
DISP0_DAT13
DISP0_DAT12
DISP0_DAT11
DISP0_DAT10
DISP0_DAT9
DISP0_DAT8
DISP0_DAT7
DISP0_DAT6
DISP0_DAT5
DISP0_DAT4
DISP0_DAT3
DISP0_DAT2
DISP0_DAT1
DISP0_DAT0
DISP0_BLT_EN
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DISP0_HSYNC
3V3
O
LCD Pixel Data bit 23
LCD Pixel Data bit 22
LCD Pixel Data bit 21
LCD Pixel Data bit 20
LCD Pixel Data bit 19
LCD Pixel Data bit 18
LCD Pixel Data bit 17
LCD Pixel Data bit 16
LCD Pixel Data bit 15
LCD Pixel Data bit 14
LCD Pixel Data bit 13
LCD Pixel Data bit 12
LCD Pixel Data bit 11
LCD Pixel Data bit 10
LCD Pixel Data bit 9
LCD Pixel Data bit 8
LCD Pixel Data bit 7
LCD Pixel Data bit 6
LCD Pixel Data bit 5
LCD Pixel Data bit 4
LCD Pixel Data bit 3
LCD Pixel Data bit 2
LCD Pixel Data bit 1
LCD Pixel Data bit 0
LCD backlight enable/disable
LCD Horizontal
Synchronization
DI0_PIN2
Page 30 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
X1_60
X1_62
X1_64
N21
N20
N19
DI0_PIN15
DI0_PIN3
DI0_DISP_CLK
DISP0_DE
DISP0_VSYNC
DISP0_CLK
3V3
3V3
3V3
O
O
O
X1_66
F17
SD4_DAT2
DISP0_BLT_CTRL
3V3
O
X1_68
A20
SD4_DAT3
DISP0_VDD_EN
3V3
O
LCD dot enable pin signal
LCD Vertical Synchronization
LCD Pixel Clock
LCD Backlight brightness
Control
LCD Voltage On
NOTE: DISP0_BLT_CTRL is also used as PWM4_1V8 signal.
Page 31 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.5. MIPI Display
The PICO-IMX6 provides MIPI Serial Interface camera signals.
The MIPI DSI Host Controller supports the following features:
IPU SIDE (input):
 Compliant with MIPI Alliance Specification for Display Serial Interface (DSI), Version 1.01.00 - 21
February 2008
 Fully Compliant with MIPI Alliance Standard for Display Pixel Interface (DPI-2), Version 2.00 15
September 2005 with Pixel Data bus width up to 24bits
 Compliant with MIPI Alliance Standard for Display Bus Interface (DBI-2) Version 2.00 - 29
November 2005.
Supported DBI types are:
 Type B
 16bit, 9bit and 8bit Data bus width
 DBI and DPI interface can coexist (only one is operational at a time)
 Support all commands defined in MIPI Alliance Specification for Display Command Set (DCS),
Version 1.02.00 - 23 July 2009
D-PHY side (output):
 Interface with MIPI D-PHY following PHY Protocol Interface (PPI), as defined in MIPI Alliance
Specification for D-PHY, Version 1.00.00 - 14 May 2009
 Supports up to 2 D-PHY Data Lanes:
 Bidirectional Communication and Escape Mode Support through Data Lane 0.
 Programmable display resolutions, from 160x120(QQVGA) to 1024x768(XVGA).
 Multiple Peripheral Support capability, configurable Virtual Channels.
 Video Mode Pixel Formats, 16bpp(RGB565), 18bpp(RGB666) packed, 18bpp(RGB666) loosely,
24bpp(RGB888).
For additional details, please refer to the “MIPI DSI Host Controller” chapter of the “i.MX6 Reference
Manual”.
Table 10 - MIPI Display Signal Description
PIN
CPU
BALL
X2_53
CPU PAD NAME
Signal
V
I/O
G1
DSI_D0P
DSI_D0P
2V5
O
X2_55
G2
DSI_D0M
DSI_D0M
2V5
O
X2_57
H1
DSI_D1P
DSI_D1P
2V5
O
X2_59
H2
DSI_D1M
DSI_D1M
2V5
O
X2_61
H3
DSI_CLK0M
DSI_CLK0M
2V5
O
X2_63
H4
DSI_CLK0P
DSI_CLK0P
2V5
O
Description
MIPI Display Serial Interface
data pair 0 positive signal
MIPI Display Serial Interface
data pair 0 negative signal
MIPI Display Serial Interface
data pair 1 positive signal
MIPI Display Serial Interface
data pair 1 negative signal
MIPI Display Serial Interface
clock pair negative signal
MIPI Display Serial Interface
clock pair positive signal
Page 32 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.6. MIPI Camera
The PICO-IMX6 provides MIPI Serial Interface camera signals.
The MIPI CSI-2 Host Controller supports the following features:
 Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2), Version 1.00 – 29
November 2005
 Supports up to 4 Data Lanes
 Dynamically configurable multi-lane merging
 Long and Short packet decoding
 Timing accurate signaling of Frame and Line synchronization packets
 Supports all primary and secondary data formats:
 RGB, YUV and RAW color space definitions
 From 24-bit down to 6-bit per pixel
 Generic or user-defined byte-based data types
For additional details on MIPI-CSI and other relevant system blocks, please refer to chapters 18, 39 and
36.4.3.1 of the “i.MX6 Reference Manual”.
Table 11 - MIPI Camera Signal Description
PIN
CPU
BALL
X2_31
CPU PAD NAME
Signal
V
I/O
F4
CSI_CLK0M
CSI_CLK0M
2V5
I
X2_33
F3
CSI_CLK0P
CSI_CLK0P
2V5
I
X2_35
E4
CSI_D0M
CSI_D0M
2V5
I
X2_37
E3
CSI_D0P
CSI_D0P
2V5
I
X2_39
D2
CSI_D1P
CSI_D1P
2V5
I
X2_41
D1
CSI_D1M
CSI_D1M
2V5
I
X2_43
E2
CSI_D2P
CSI_D2P
2V5
I
X2_45
E1
CSI_D2M
CSI_D2M
2V5
I
X2_47
F2
CSI_D3M
CSI_D3M
2V5
I
X2_49
F1
CSI_D3P
CSI_D3P
2V5
I
Description
MIPI Camera Serial Interface
clock pair negative signal
MIPI Camera Serial Interface
clock pair positive signal
MIPI Camera Serial Interface
data pair 0 negative signal
MIPI Camera Serial Interface
data pair 0 positive signal
MIPI Camera Serial Interface
data pair 1 positive signal
MIPI Camera Serial Interface
data pair 1 negative signal
MIPI Camera Serial Interface
data pair 2 positive signal
MIPI Camera Serial Interface
data pair 2 negative signal
MIPI Camera Serial Interface
data pair 3 negative signal
MIPI Camera Serial Interface
data pair 3 positive signal
NOTE: MIPI Camera Serial Interface data pair 2 and data pair 3 are only available on the i.MX6 Dual and
i.MX6 Quad processor.
Page 33 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.7. Audio Interface
2
The PICO-IMX6 incorporates one I S / AUDMUX instance and can as well provide surround audio over
the HDMI data signals.
The AUDMUX provides flexible, programmable routing of the serial interfaces (SSI1 or SSI2) to and from
off-chip devices. The AUDMUX routes audio data (and even splices together multiple time-multiplexed
audio streams) but does not decode or process audio data itself. The AUDMUX is controlled by the ARM
but can route data even when the ARM is in a low-power mode.
The ESAI (Enhanced Serial Audio Interface) provides a full-duplex serial port for serial communication
with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other
processors. The ESAI consists of independent transmitter and receiver sections, each section with its
own clock generator. The ESAI is connected to the IOMUX and to the ESAI_BIFIFO module.
The ESAI_BIFIFO (ESAI Bus Interface and FIFO) is the interface between the ESAI module and the
shared peripheral bus. It contains the FIFOs used to buffer data to and from the ESAI, as well as
providing the data word alignment and padding necessary to match the 24-bit data bus of the ESAI to the
32-bit data bus of the shared peripheral bus.
The ASRC (Asynchronous Sample Rate Converter) converts the sampling rate of a signal associated to
an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample
rate conversions of up to 10 channels of over 120dB THD+N. The sample rate conversion of each
channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three
sampling rate pairs. The ASRC is connected to the shared peripheral bus.
Key features of the audio signal block include:
 Full 6-wire SSI interfaces for asynchronous receive and transmit
 Configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interfaces
 Independent Tx/Rx frame sync and clock direction selection for host or peripheral
 Each host interface's capability to connect to any other host or peripheral interface in a point-topoint or point-to-multipoint (network mode)
 Transmit and receive data switching to support external network mode
2
Table 12 - I S Audio Signal Description
PIN
CPU
BALL
E1_50
CPU PAD NAME
Signal
V
I/O
N3
CSI0_DAT7
AUD3_RXD
1V8
I
E1_52
N1
CSI0_DAT4
AUD3_TXC
1V8
O
E1_54
N4
CSI0_DAT6
AUD3_TXFS
1V8
O
E1_56
P2
CSI0_DAT5
AUD3_TXD
1V8
O
Description
Integrated Interchip Sound
2
(I S) channel receive data
line
Integrated Interchip Sound
2
(I S) channel word clock
signal
Integrated Interchip Sound
2
(I S) channel frame
synchronization signal
Integrated Interchip Sound
2
(I S) channel transmit data
line
Page 34 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.8. PCI Express
The PICO-IMX6 is equipped with a single lane PCI Express interface, implemented in the i.MX6
processor.
The PCI Express interface complies with PCIe specification Gen 2.0 and supports the PCI Express
1.1/2.0 standards. The PCI Express module is a dual mode complex, supporting root complex operations
and endpoint operations.
PCI Express PHY Features
 5 Gbps data transmission rate
 Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD.
 Programmable RX equalization
 Designed for excellent performance margin and receiver sensitivity
 Robust PHY architecture tolerates wide process, voltage and temperature variations
 Low-jitter PLL technology with excellent supply isolation
 IEEE 1149.6 (JTAG) boundary scan
 Built-in Self-Test (BIST) features for production, at-speed, testing on any digital tester
 5Gb/s PCIe Gen 2 and 2.5Gb/s PCIe Gen 1.1 test modes supported
 Advanced built-in diagnostics including on-chip sampling scope for easy debug
 Visibility & controllability of hard macro functionality thru programmable registers in the design
 Over-rides on all ASIC side inputs for easy debug
 Access register space thru simple 16 bit parallel interface
 Access register space thru JTAG
For additional details, please refer to chapter 49 of the “i.MX6 Reference Manual”.
Table 13 - PCI Express Signal Description
PIN
CPU
BALL
X2_56
CPU PAD NAME
Signal
V
I/O
D7
CLK1_P
PCIEA_CLKP
2V5
O
X2_58
C7
CLK1_N
PCIEA_CLKN
2V5
O
X2_62
B3
PCIE_TXP
PCIEA_TXP
2V5
O
X2_64
A3
PCIE_TXM
PCIEA_TXN
2V5
O
X2_68
B2
PCIE_RXP
PCIEA_RXP
2V5
I
X2_70
B1
PCIE_RXM
PCIEA_RXN
2V5
I
Description
PCI Express clock differential
pair positive signal
PCI Express clock differential
pair negative signal
PCI Express Transmit output
differential pair positive
signal
PCI Express Transmit output
differential pair negative
signal
PCI Express Receive input
differential pair positive
signal
PCI Express Receive input
differential pair negative
signal
NOTE: The PCIE_TX pair has decoupling capacitors on the EDM module valued 10nF
Page 35 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.9. Serial ATA Interface
The PICO-IMX6 incorporates a single SATA-II port implemented with the Freescale i.MX6 integrated
SATA controller and PHY when the PICO-IMX6 is featured with a i.MX6 Dual or Quad Processor.
(Availability restrictions apply)
The interface supports the following main features:
 The SATA block fully complies with AHCI specification version 1.10 and partially complies with
AHCI specification version 1.3 (FIS-based switching is currently not supported).
 SATA 1.5 Gb/s and SATA 3.0 Gb/s speed.
 Power management features including automatic partial-to-slumber transition.
 eSATA (external analog logic also needs to support eSATA).
 Hardware-assisted Native Command Queuing (NCQ) for up to 32 entries.
For additional details, please refer to chapter 53 of the “i.MX6 Reference Manual”.
Table 14 - Serial ATA Signal Description
PIN
CPU
BALL
X2_4
CPU PAD NAME
Signal
V
I/O
B14
SATA_RXP
SATA1_RXP
2V5
I
X2_6
A14
SATA_RXM
SATA1_RXN
2V5
I
X2_10
B12
SATA_TXM
SATA1_TXN
2V5
O
X2_12
A12
SATA_TXP
SATA1_TXP
2V5
O
Description
Serial ATA Receive
differential pair positive
signal
Serial ATA Receive
differential pair negative
signal
Serial ATA Transmit
differential pair negative
signal
Serial ATA Transmit
differential pair positive
signal
NOTE: SATA is only available on PICO-IMX6 modules that feature the i.MX6 Dual or i.MX6 Quad
processor and is not available on the i.MX6 Solo and i.MX6 Duallite processor.
Page 36 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.10. Universal Serial Bus (USB) Interface
The PICO-IMX6 incorporates a single USB Host controller and an additional USB Host/OTG controller.
Each of the USB controllers provides the following main features:
USB 2.0 Host/OTG Controller
 High-Speed/Full-Speed/Low-Speed OTG core
 HS/FS/LS UTMI compliant interface
 High Speed, Full Speed and Low Speed operation in Host mode (with UTMI transceiver)
 High Speed, and Full Speed operation in Peripheral mode (with UTMI transceiver)
 Hardware support for OTG signaling, session request protocol, and host negotiation protocol
 Up to 8 bidirectional endpoints
 Support charger detection
USB 2.0 Host Controller
 High-Speed/Full-Speed/Low-Speed Host-Only core
 HS/FS/LS UTMI compliant interface
For additional details, please refer to chapter 65 of the “i.MX6 Reference Manual”.
Table 15 - USB Host Signal Description
PIN
CPU
BALL
X2_46
CPU PAD NAME
Signal
V
I/O
F10
USB_H1_DN
X2_48
E10
X2_50
D10
X2_52
P5
Description
USB_HOST_DN
3V3
I/O
USB_H1_DP
USB_HOST_DP
3V3
I/O
USB_H1_VBUS
USB_H1_VBUS
5V
I/O
GPIO_19
USB_H1_OC
3V3
I
V
I/O
Description
USB OTG ID Pin
Universal Serial Bus
differential pair positive
signal
Universal Serial Bus
differential pair negative
signal
Over current detect input pin
to monitor USB power over
current
Universal Serial Bus power
Universal Serial Bus power
enable
Universal Serial Bus
differential pair negative
signal
Universal Serial Bus
differential pair positive
signal
Universal Serial Bus power
Active low input, to inform
USB overcurrent condition
(low = overcurrent detected)
Table 16 - USB OTG Signal Description
E1_3
CPU
BALL
W23
E1_16
A6
USB_OTG_DP
USB_OTG_DP
USB
I/O
E1_18
B6
USB_OTG_DN
USB_OTG_DN
USB
I/O
E1_19
J20
EIM_D30
FAULT
1V8
I
E1_20
E9
USB_OTG_VBUS
USB_OTG_VBUS
5V
I/O
E1_21
E23
EIM_D22
USB_OTG_PWR_EN
USB
O
PIN
CPU PAD NAME
Signal
ENET_RX_ER
USB_ID
3V3
I/O
NOTE: While using USB OTG in USB HOST mode. The USB_ID pin should have a pull-down resistor to
GND.
Page 37 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.11. SDIO/MMC Interface
The PICO-IMX6 features a MMC / SD / SDIO host interfaces connected to the Freescale i.MX6 integrated
“Ultra Secured Digital Host Controller” (uSDHC).
The following main features are supported by uSDHC:
 Compatible with the MMC System Specification version 4.2/4.3/4.4/4.5.
 Conforms to the SD Host Controller Standard Specification version 3.0.
 Compatible with the SD Memory Card Specification version 3.0 and supports the “Extended
Capacity SD Memory Card”.
 Compatible with the SDIO Card Specification version 3.0.
 Supports 1-bit / 4-bit SD and SDIO modes, 1-bit / 4-bit
The MMC/SD/SDIO host controller can support a single MMC / SD / SDIO card or device.
For additional details, please refer to chapter 65 of the “i.MX6 Reference Manual”.
Table 17 - SDIO/MMC Interface Signal Description
E1_58
CPU
BALL
D20
E1_60
M21
EIM_DA9
EIM_DA9
1V8
I
E1_62
E1_64
E1_66
E1_68
E1_70
B21
E19
A21
F18
C20
SD1_CMD
SD1_DAT2
SD1_DAT0
SD1_DAT3
SD1_DAT1
SD1_CMD
SD1_DAT2
SD1_DAT0
SD1_DAT3
SD1_DAT1
1V8
1V8
1V8
1V8
1V8
I/O
I/O
I/O
I/O
I/O
PIN
CPU PAD NAME
Signal
V
I/O
Description
SD1_CLK
SD1_CLK
1V8
I/O
MMC/SDIO Clock
SD Card detect input (Active
low)
MMC/SDIO Command
MMC/SDIO Data bit 2
MMC/SDIO Data bit 0
MMC/SDIO Data bit 3
MMC/SDIO Data bit 1
Page 38 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.12. CAN BUS Interface signals
The PICO-IMX6 features two CAN bus interfaces. The CAN bus interfaces are implemented with the
i.MX6 on chip “Flexible Controller Area Network” (FlexCAN) communication modules.
FlexCAN supports the following main features:
 Compliant with the CAN 2.0B protocol specification
 Programmable bit rate up to 1 Mb/sec
Integration of a CAN Bus transceiver and optional galvanic isolation should be incorporated on the EDM
carrier board.
For additional details, please refer to chapter 25 of the “i.MX6 Reference Manual”.
Table 18 - CAN Bus Signal Description
PIN
CPU
BALL
X2_19
CPU PAD NAME
Signal
V
I/O
W6
KEY_COL2
CAN1_TX
3V3
I/O
X2_21
W4
KEY_ROW2
CAN1_RX
3V3
I/O
X2_25
T6
KEY_COL4
CAN2_TX
3V3
I/O
X2_27
V5
KEY_ROW4
CAN2_RX
3V3
I/O
Description
CAN (controller Area
Network) transmit signal
CAN (controller Area
Network) receive signal
CAN (controller Area
Network) transmit signal
CAN (controller Area
Network) receive signal
Page 39 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.13. Universal Asynchronous Receiver/Transmitter (UART) Interface
The PICO-IMX6 makes 2 UART ports available on the EDM connector and utilizes an additional UART on
the module to connect to the WiFi/Bluetooth module.
The i.MX6 processor integrated UARTs support the following features:
 High-speed TIA/EIA-232-F compatible, up to 5.0 Mbit/s.
 Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s).
 9-bit or Multidrop mode (RS-485) support (automatic slave address detection).
 7 or 8 data bits for RS-232 characters or 9 bit RS-485 format, 1 or 2 stop bits.
 Programmable parity (even, odd, and no parity).
 Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
 RXD input and TXD output can be inverted respectively in RS-232/RS-485 mode
 RS-485 driver direction control via CTS signal
 Auto baud rate detection (up to 115.2 Kbit/s)
 Two independent, 32-entry FIFOs for transmit and receive
For additional details, please refer to chapter 62 of the “i.MX6 Reference Manual”.
Table 19 - UART Signal Description
PIN
CPU
BALL
E1_22
CPU PAD NAME
Signal
V
I/O
M3
CSI0_DAT11
UART1_RX
1V8
I
E1_27
M1
CSI0_DAT10
UART1_TX
1V8
O
E1_46
F22
EIM_D24
UART3_TXD
1V8
O
E1_61
G22
EIM_D25
UART3_RXD
1V8
I
E1_63
H21
EIM_D31
UART3_RTS
1V8
O
E1_65
D25
EIM_D23
UART3_CTS
1V8
O
Description
Universal Asynchronous
Receive Transmit receive
data signal
Universal Asynchronous
Receive Transmit transmit
data signal
Universal Asynchronous
Receive Transmit transmit
data signal
Universal Asynchronous
Receive Transmit receive
data signal
Universal Asynchronous
Receive Transmit request to
send signal
Universal Asynchronous
Receive Transmit clear to
send signal
NOTE: it is recommended to use the UART1 interface as system debug where possible and use the
UART3 signals in applications where one serial port is required.
NOTE: UART2 is not listed in this section. This interface is connected from the i.MX6 processor towards
the WiFi/Bluetooth interface present on PICO-IMX6 and can be found in the WiFi/Bluetooth section of this
manual.
Page 40 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.14. Serial Peripheral Interface (SPI)
The PICO -IMX6 features two Enhanced Configurable SPI ports, which are derived from the i.MX6
processor, integrated ECSPI IPs.
The following main features are supported:
 Full-duplex synchronous serial interface
 Master/Slave configurable
 Transfer continuation function allows unlimited length data transfers
 32-bit wide by 64-entry FIFO for both transmit and receive data
 32-bit wide by 16-entry FIFO for HT message data
 Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable Direct Memory
Access (DMA) support
For additional details, please refer to chapter 20 of the “i.MX6 Reference Manual”.
Table 20 - SPI Channel Signal Description
PIN
CPU
BALL
E1_51
CPU PAD NAME
Signal
V
I/O
K22
EIM_LBA
SPI CS0
1V8
E1_53
K20
EIM_RW
SPI CS1
1V8
E1_55
H24
EIM_CS0
CSPI2_SCLK
1V8
O
E1_57
J23
EIM_CS1
CSPI2_MOSI
1V8
O
E1_59
J24
EIM_OE
CSPI2_MISO
1V8
I
Description
Serial Peripheral Interface
Chip Select 0 signal
Serial Peripheral Interface
Chip Select 1 signal
Serial Peripheral Interface
clock signal
Serial Peripheral Interface
master output slave input
signal
Serial Peripheral Interface
master input slave output
signal
Page 41 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.15. I2C Bus
2
2
The PICO-IMX6 I C interfaces are implemented with the i.MX6 integrated I C controller. There are two
2
2
general purpose I C interfaces and one I C interface dedicated towards display and system management
functions.
The following features are supported:
2
 Compliance with Philips I C specification version 2.1
 Multiple-master operation
 Support for standard mode (up to 100K bits/s) and fast mode (up to 400K bits/s)
 Arbitration-lost interrupt with automatic mode switching from master to slave
For additional details, please refer to chapter 34 of the “i.MX6 Reference Manual”.
2
Table 21 - I C Bus Signal Description
PIN
X2_13
X2_15
E1_41
E1_43
E1_45
E1_47
CPU
BALL
U5
T7
H20
G23
F21
D24
2
CPU PAD NAME
Signal
KEY_COL3
KEY_ROW3
EIM_D21
EIM_D28
EIM_D17
EIM_D18
I2C2_SCL
I2C2_SDA
I2C1_SCL
I2C1_SDA
I2C3_SCL
I2C3_SDA
V
I/O
Description
3V3
3V3
1V8
1V8
1V8
1V8
I/O
I/O
I/O
I/O
I/O
I/O
I C bus clock line
2
I C bus data line
2
I C bus clock line
2
I C bus data line
2
I C bus clock line
2
I C bus data line
2
2
NOTE: All I C bus data and clock lines for all I C interfaces have 2.2K Ω pull-up resistors present on the
PICO-IMX6 module.
NOTE: It is recommended to use I2C2 signals for HDMI EDID functionality and set these pins in software
DDC mode.
Page 42 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.16. General Purpose Input/Output (GPIO)
The PICO-IMX6 has 10 dedicated GPIO pins at 1.8V and 3 dedicated GPIO pins at 3.3V. Many of the
other pins used on the PICO Compute Module can be put in GPIO module however doing so might break
scalability with other PICO Compute Modules.
The GPIO signals can be configured for the following applications:
 Data input / output
 Interrupt generation
For additional details, please refer to chapter 27 of the “I.MX6 Reference Manual”.
Table 22 - GPIO Signal Description
PIN
CPU
BALL
E1_24
CPU PAD NAME
Signal
V
I/O
P4
CSI0_MCLK
GPIO_P24
1V8
I/O
E1_25
P1
CSI0_PIXCLK
GPIO_P25
1V8
I/O
E1_26
N2
CSI0_VSYNC
GPIO_P26
1V8
I/O
E1_28
P3
CSI0_DATA_EN
GPIO_P28
1V8
I/O
E1_30
N6
CSI0_DAT8
GPIO_P30
1V8
I/O
E1_32
N5
CSI0_DAT9
GPIO_P32
1V8
I/O
E1_34
M4
CSI0_DAT14
GPIO_P34
1V8
I/O
E1_42
M2
CSI0_DAT12
GPIO_P42
1V8
I/O
E1_44
L1
CSI0_DAT13
GPIO_P44
1V8
I/O
E1_48
M5
CSI0_DAT15
GPIO_P48
1V8
I/O
X2_65
R5
GPIO_8
GPIO_8
3V3
I/O
X2_67
T3
GPIO_6
GPIO_6
3V3
I/O
X2_69
R7
GPIO_3
GPIO3_CLKO
3V3
I/O
Description
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
Page 43 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.17. Pulse Width Modulation (PWM)
The PICO-IMX6 has 4 dedicated PWM pins at 1.8V.
The following features characterize the PWM:
 16-bit up-counter with clock source selection
 4 x 16 FIFO to minimize interrupt overhead
 12-bit prescaler for division of clock
 Sound and melody generation
 Active high or active low configured output
 Can be programmed to be active in low-power mode
 Can be programmed to be active in debug mode
 Interrupts at compare and rollover
For additional details, please refer to chapter 52 of the “I.MX6 Reference Manual”.
Table 23 - PWM Signal Description
PIN
CPU
BALL
E1_33
CPU PAD NAME
Signal
V
I/O
T4
GPIO_1
PWM2_1V8
1V8
I/O
E1_35
T2
GPIO_9
PWM1_1V8
1V8
I/O
E1_37
B19
SD4_DAT1
PWM3_1V8
1V8
I/O
E1_39
F17
SD4_DAT2
PWM4_1V8
1V8
I/O
Description
General Purpose Input
Output with PWM control
General Purpose Input
Output with PWM control
General Purpose Input
Output with PWM control
General Purpose Input
Output with PWM control
NOTE: PWM3_1V8 signal is also used for LVDS_BLT_CTRL: LVDS Display Brightness Control.
NOTE: PWM4_1V8 signal is also used for DISP0_BLT_CTRL: TTL Display Brightness Control.
Page 44 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.18. Manufacturing and Boot Control
The PICO-IMX6 has a number of pins to override the default boot media present on the PICO-IMX6
Compute Module (eMMC or SD Cardslot).
Table 24 - Boot Selection Pins
PIN
X2_3
X2_5
X2_7
X2_9
CPU
BALL
M24
N23
M23
L23
CPU PAD NAME
Signal
EIM_DA12
EIM_DA14
EIM_DA13
EIM_DA5
EIM_DA12
EIM_DA14
EIM_DA13
EIM_DA5
V
I/O
1V8
1V8
1V8
1V8
I
I
I
I
Description
Boot Select pin
Boot Select pin
Boot Select pin
Boot Select pin
To boot from an external carrierboard SD cardslot instead of the PICO-IMX6 Compute module boot
media the following signals should be modified.
Table 25 - Boot Signal Configuration
PIN
X2_3
X2_5
X2_7
X2_9
CPU BALL
M24
N23
M23
L23
Carrier Board SD Cardslot Boot Configuration
HIGH
LOW
HIGH
LOW
Page 45 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.19. Input Power Requirements
The PICO-IMX6 is designed to be driven with a single input power rail.
The power domain pins have to be connected as follow:


All GND pins have to be connected to the carrier board ground pane.
All VSYS pins should be connected to the main power source.
Table 26 - Input Power Signals
Power Rail
VSYS (4 pin)
Nominal Input
5V
Input Range
+4.2V - +5.25V
Maximum Input Ripple
±50 mV
3.19.1. Power Management Signals
The PICO-IMX6 has the following set of signals to control the system power states such as the power-on
and reset conditions. This enables the system designer to implement a fully ACPI compliant system
supporting system states.
Table 27 - Power Management Signals
E1_17
CPU
BALL
D12
E1_36
C11
PIN
CPU PAD NAME
Signal
V
I/O
ONOFF
ON_OFF
3V3
I
POR_B
nRESETOUT
1V8
I/O
Description
Power ON button input signal
General Purpose Input
Output
Page 46 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
3.19.2. Power Sequence
PICO-IMX6 input power sequencing requirements are as follow:
If a backup Real Time Clock (RTC) is required in the host system. We recommend to design an RTC
circuit on the PICO carrier board. For example the Maxim Integrated DS1337+ connected over the
2
general purpose I C can be used.
Start Sequence:
VCC_RTC must come up at the same time or before VCC comes up.
Stop Sequence:
VCC must go down at the same time or before VCC_RTC goes down
Table 28 - Input Power Sequencing for AT based configurations
Item
T1
T2
Description
VCC_RTC rise to VCC rise
VCC fall to VCC_RTC fall
Value
≥ 0 ms
≥ 0 ms
Figure 11 - Input Power sequence for AT based configurations
Page 47 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
4. PICO Compute Module Pin Assignment
The PICO-IMX6 has three 70-pin Hirose board to board connectors.
X2
E1
X1
PIN
CPU
BALL
CPU PAD NAME
Signal
V
I/O
E1_1
GND
P
E1_2
VSYS
P
E1_3
W23
ENET_RX_ER
USB_ID
3V3
I/O
E1_4
VSYS
P
E1_5
GND
P
E1_6
VSYS
P
E1_7
E1_8
E1_9
E1_10
E1_11
NC
3V3
GND
3V3
GND
P
P
P
P
E1_12
1V8
P
E1_13
GND
P
E1_14
VSYS
P
E1_15
GND
P
E1_16
A6
E1_17
D12
USB_OTG_DP
USB_OTG_DP
USB
I/O
ONOFF
ON_OFF
3V3
I
Description
Ground
System input power (4.0 to
5.25V)
USB OTG ID Pin
System input power (4.0 to
5.25V)
Ground
System input power (4.0 to
5.25V)
Not Connected
System 3.3V Output
Ground
System 3.3V Output
Ground
System 1.8V Output (same
as E1 connector I/O voltage
levels)
Ground
System input power (4.0 to
5.25V)
Ground
Universal Serial Bus
differential pair positive
signal
Power ON button input signal
Page 48 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
PIN
CPU
BALL
E1_18
CPU PAD NAME
Signal
V
I/O
B6
USB_OTG_DN
USB_OTG_DN
USB
I/O
E1_19
J20
EIM_D30
FAULT
1V8
I
E1_20
E9
USB_OTG_VBUS
USB_OTG_VBUS
5V
I/O
E1_21
E23
EIM_D22
USB_OTG_PWR_EN
USB
O
E1_22
M3
CSI0_DAT11
UART1_RX
1V8
I
E1_23
NC
E1_24
P4
CSI0_MCLK
GPIO_P24
1V8
I/O
E1_25
P1
CSI0_PIXCLK
GPIO_P25
1V8
I/O
E1_26
N2
CSI0_VSYNC
GPIO_P26
1V8
I/O
E1_27
M1
CSI0_DAT10
UART1_TX
1V8
O
E1_28
P3
CSI0_DATA_EN
GPIO_P28
1V8
I/O
1V8
I/O
E1_29
E1_30
NC
N6
CSI0_DAT8
E1_31
GPIO_P30
NC
E1_32
N5
CSI0_DAT9
GPIO_P32
1V8
I/O
E1_33
T4
GPIO_1
PWM2_1V8
1V8
I/O
E1_34
M4
CSI0_DAT14
GPIO_P34
1V8
I/O
E1_35
T2
GPIO_9
PWM1_1V8
1V8
I/O
E1_36
C11
POR_B
nRESETOUT
1V8
I/O
E1_37
B19
SD4_DAT1
PWM3_1V8
1V8
I/O
E1_38
NC
E1_39
F17
SD4_DAT2
PWM4_1V8
1V8
I/O
E1_40
E1_41
H20
EIM_D21
NC
I2C1_SCL
1V8
I/O
E1_42
M2
CSI0_DAT12
GPIO_P42
1V8
I/O
E1_43
G23
EIM_D28
I2C1_SDA
1V8
I/O
E1_44
L1
CSI0_DAT13
GPIO_P44
1V8
I/O
E1_45
F21
EIM_D17
I2C3_SCL
1V8
I/O
Description
Universal Serial Bus
differential pair negative
signal
Over current detect input pin
to monitor USB power over
current
Universal Serial Bus power
Universal Serial Bus power
enable
Universal Asynchronous
Receive Transmit receive
data signal
Not Connected
General Purpose Input
Output
General Purpose Input
Output
General Purpose Input
Output
Universal Asynchronous
Receive Transmit transmit
data signal
General Purpose Input
Output
Not Connected
General Purpose Input
Output
Not Connected
General Purpose Input
Output
General Purpose Input
Output with PWM control
General Purpose Input
Output
General Purpose Input
Output with PWM control
General Purpose Input
Output
General Purpose Input
Output with PWM control
Not Connected
General Purpose Input
Output with PWM control
Not Connected
2
I C bus clock line
General Purpose Input
Output
2
I C bus data line
General Purpose Input
Output
2
I C bus clock line
Page 49 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
PIN
CPU
BALL
E1_46
CPU PAD NAME
Signal
V
I/O
F22
EIM_D24
UART3_TXD
1V8
O
E1_47
D24
EIM_D18
I2C3_SDA
1V8
I/O
E1_48
M5
CSI0_DAT15
GPIO_P48
1V8
I/O
I
E1_49
NC
E1_50
N3
CSI0_DAT7
AUD3_RXD
1V8
E1_51
K22
EIM_LBA
SPI CS0
1V8
E1_52
N1
CSI0_DAT4
AUD3_TXC
1V8
E1_53
K20
EIM_RW
SPI CS1
1V8
E1_54
N4
CSI0_DAT6
AUD3_TXFS
1V8
O
E1_55
H24
EIM_CS0
CSPI2_SCLK
1V8
O
E1_56
P2
CSI0_DAT5
AUD3_TXD
1V8
O
E1_57
J23
EIM_CS1
CSPI2_MOSI
1V8
O
E1_58
D20
SD1_CLK
SD1_CLK
1V8
I/O
E1_59
J24
EIM_OE
CSPI2_MISO
1V8
I
E1_60
M21
EIM_DA9
EIM_DA9
1V8
I
E1_61
G22
EIM_D25
UART3_RXD
1V8
I
E1_62
B21
SD1_CMD
SD1_CMD
1V8
I/O
E1_63
H21
EIM_D31
UART3_RTS
1V8
O
E1_64
E19
SD1_DAT2
SD1_DAT2
1V8
I/O
E1_65
D25
EIM_D23
UART3_CTS
1V8
O
E1_66
E1_67
E1_68
E1_69
E1_70
A21
SD1_DAT0
1V8
I/O
F18
SD1_DAT3
1V8
I/O
C20
SD1_DAT1
SD1_DAT0
NC
SD1_DAT3
NC
SD1_DAT1
1V8
I/O
O
Description
Universal Asynchronous
Receive Transmit transmit
data signal
2
I C bus data line
General Purpose Input
Output
Not Connected
Integrated Interchip Sound
2
(I S) channel receive data
line
Serial Peripheral Interface
Chip Select 0 signal
Integrated Interchip Sound
2
(I S) channel word clock
signal
Serial Peripheral Interface
Chip Select 1 signal
Integrated Interchip Sound
2
(I S) channel frame
synchronization signal
Serial Peripheral Interface
clock signal
Integrated Interchip Sound
2
(I S) channel transmit data
line
Serial Peripheral Interface
master output slave input
signal
MMC/SDIO Clock
Serial Peripheral Interface
master input slave output
signal
SD Card detect input (Active
low)
Universal Asynchronous
Receive Transmit receive
data signal
MMC/SDIO Command
Universal Asynchronous
Receive Transmit request to
send signal
MMC/SDIO Data bit 2
Universal Asynchronous
Receive Transmit clear to
send signal
MMC/SDIO Data bit 0
Not Connected
MMC/SDIO Data bit 3
Not Connected
MMC/SDIO Data bit 1
Page 50 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
PIN
CPU
BALL
CPU PAD NAME
X1_1
X1_2
Signal
V
GND
GND
I/O
P
P
X1_3
W2
LVDS0_TX3_N
LVDS0_TX3_N
2V5
O
X1_4
D18
SD4_DAT0
LVDS0_BLT_EN
3V3
O
X1_5
W1
LVDS0_TX3_P
LVDS0_TX3_P
2V5
O
X1_6
X1_7
X1_8
X1_9
X1_10
X1_11
X1_12
X1_13
X1_14
B19
SD4_DAT1
3V3
W24
V4
V24
V3
T20
DISP0_DAT23
LVDS0_CLK_N
DISP0_DAT22
LVDS0_CLK_P
DISP0_DAT21
U22
DISP0_DAT20
LVDS0_BLT_CTRL
GND
DISP0_DAT23
LVDS0_CLK_N
DISP0_DAT22
LVDS0_CLK_P
DISP0_DAT21
GND
DISP0_DAT20
3V3
O
P
O
O
O
O
O
P
O
X1_15
V2
LVDS0_TX2_N
LVDS0_TX2_N
2V5
O
X1_16
U23
DISP0_DAT19
DISP0_DAT19
3V3
O
X1_17
V1
LVDS0_TX2_P
LVDS0_TX2_P
2V5
O
X1_18
X1_19
X1_20
V25
DISP0_DAT18
3V3
U24
DISP0_DAT17
DISP0_DAT18
GND
DISP0_DAT17
3V3
O
P
O
X1_21
U4
LVDS0_TX1_N
LVDS0_TX1_N
2V5
O
X1_22
T21
DISP0_DAT16
DISP0_DAT16
3V3
O
X1_23
U3
LVDS0_TX1_P
LVDS0_TX1_P
2V5
O
X1_24
X1_25
X1_26
T22
DISP0_DAT15
3V3
U25
DISP0_DAT14
DISP0_DAT15
GND
DISP0_DAT14
3V3
O
P
O
X1_27
U2
LVDS0_TX0_N
LVDS0_TX0_N
2V5
O
X1_28
R20
DISP0_DAT13
DISP0_DAT13
3V3
O
X1_29
U1
LVDS0_TX0_P
LVDS0_TX0_P
2V5
O
X1_30
X1_31
X1_32
T24
DISP0_DAT12
3V3
T23
DISP0_DAT11
DISP0_DAT12
GND
DISP0_DAT11
O
P
O
X1_33
V20
ENET_MDC
RGMII_MDC
3V3
X1_34
X1_35
X1_36
X1_37
X1_38
X1_39
X1_40
R21
V23
T25
W22
R22
V21
R24
DISP0_DAT10
ENET_MDIO
DISP0_DAT9
ENET_RXD1
DISP0_DAT8
ENET_TX_EN
DISP0_DAT7
DISP0_DAT10
RGMII_MDIO
DISP0_DAT9
RGMII_nRST
DISP0_DAT8
RGMII_INT
DISP0_DAT7
3V3
3V3
3V3
3V3
3V3
3V3
3V3
X1_41
V22
ENET_REF_CLK
RGMII_REF_CLK
3V3
3V3
2V5
3V3
2V5
3V3
3V3
O
O
O
O
Description
Ground
Ground
LVDS differential pair 3
negative signal
LVDS panel backlight enable
LVDS differential pair 3
positive signal
LVDS panel backlight control
Ground
LCD Pixel Data bit 23
LVDS clock negative signal
LCD Pixel Data bit 22
LVDS clock positive signal
LCD Pixel Data bit 21
Ground
LCD Pixel Data bit 20
LVDS differential pair 2
negative signal
LCD Pixel Data bit 19
LVDS differential pair 2
positive signal
LCD Pixel Data bit 18
Ground
LCD Pixel Data bit 17
LVDS differential pair 1
negative signal
LCD Pixel Data bit 16
LVDS differential pair 1
positive signal
LCD Pixel Data bit 15
Ground
LCD Pixel Data bit 14
LVDS differential pair 0
negative signal
LCD Pixel Data bit 13
LVDS differential pair 0
positive signal
LCD Pixel Data bit 12
Ground
LCD Pixel Data bit 11
Management data clock
reference
LCD Pixel Data bit 10
Management data
LCD Pixel Data bit 9
Ethernet reset
LCD Pixel Data bit 8
Ethernet interrupt output
LCD Pixel Data bit 7
Synchronous Ethernet
recovered clock
Page 51 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
PIN
X1_42
X1_43
X1_44
X1_45
X1_46
X1_47
X1_48
X1_49
X1_50
X1_51
X1_52
X1_53
X1_54
X1_55
X1_56
X1_57
CPU
BALL
R23
C23
R25
D22
P20
CPU PAD NAME
Signal
DISP0_DAT6
RGMII_TX_CTL
DISP0_DAT5
RGMII_RX_CTL
DISP0_DAT4
V
I/O
Description
3V3
1V5
3V3
1V5
3V3
O
3V3
1V5
3V3
1V5
3V3
1V5
3V3
1V5
3V3
1V5
O
P
O
O
O
O
O
O
O
O
O
O
LCD Pixel Data bit 6
RGMII transmit enable
LCD Pixel Data bit 5
RGMII receive data valid
LCD Pixel Data bit 4
Ground
LCD Pixel Data bit 3
RGMII transmit clock
LCD Pixel Data bit 2
RGMII transmit data 0
LCD Pixel Data bit 1
RGMII transmit data 1
LCD Pixel Data bit 0
RGMII transmit data 2
LCD backlight enable/disable
RGMII transmit data 3
LCD Horizontal
Synchronization
Ground
LCD dot enable pin signal
RGMII receive clock
LCD Vertical Synchronization
RGMII receive data 0
LCD Pixel Clock
RGMII receive data 1
LCD Backlight brightness
Control
RGMII receive data 2
LCD Voltage On
RGMII receive data 3
Ground
P21
D21
P23
C22
P22
F20
P24
E21
P25
A24
DISP0_DAT3
RGMII_TXC
DISP0_DAT2
RGMII_TD0
DISP0_DAT1
RGMII_TD1
DISP0_DAT0
RGMII_TD2
DI0_PIN4
RGMII_TD3
DISP0_DAT6
RGMII_TXEN
DISP0_DAT5
RGMII_RXDV
DISP0_DAT4
GND
DISP0_DAT3
RGMII_TXCLK
DISP0_DAT2
RGMII_TXD0
DISP0_DAT1
RGMII_TXD1
DISP0_DAT0
RGMII_TXD2
DISP0_BLT_EN
RGMII_TXD3
X1_58
N25
DI0_PIN2
DISP0_HSYNC
3V3
O
X1_59
X1_60
X1_61
X1_62
X1_63
X1_64
X1_65
N21
B25
N20
C24
N19
B23
DI0_PIN15
RGMII_RXC
DI0_PIN3
RGMII_RD0
DI0_DISP_CLK
RGMII_RD1
GND
DISP0_DE
RGMII_RXCLK
DISP0_VSYNC
RGMII_RXD0
DISP0_CLK
RGMII_RXD1
3V3
1V5
3V3
1V5
3V3
1V5
P
O
I
O
I
O
I
X1_66
F17
SD4_DAT2
DISP0_BLT_CTRL
3V3
O
X1_67
X1_68
X1_69
X1_70
B24
A20
D23
RGMII_RD2
SD4_DAT3
RGMII_RD3
RGMII_RXD2
DISP0_VDD_EN
RGMII_RXD3
GND
1V5
3V3
1V5
I
O
I
P
O
Page 52 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
PIN
CPU
BALL
CPU PAD NAME
Signal
V
I/O
1V8
P
P
I
X2_1
X2_2
X2_3
M24
EIM_DA12
GND
GND
EIM_DA12
X2_4
B14
SATA_RXP
SATA1_RXP
2V5
I
X2_5
N23
EIM_DA14
EIM_DA14
1V8
I
X2_6
A14
SATA_RXM
SATA1_RXN
2V5
I
X2_7
X2_8
X2_9
M23
EIM_DA13
1V8
L23
EIM_DA5
EIM_DA13
GND
EIM_DA5
1V8
I
P
I
X2_10
B12
SATA_TXM
SATA1_TXN
2V5
O
X2_11
GND
P
X2_12
A12
SATA_TXP
SATA1_TXP
2V5
O
X2_13
X2_14
X2_15
U5
KEY_COL3
3V3
T7
KEY_ROW3
I2C2_SCL
GND
I2C2_SDA
3V3
I/O
P
I/O
X2_16
K6
HDMI_D0P
HDMI1_D0P
3V3
O
X2_17
GND
P
X2_18
K5
HDMI_D0M
HDMI1_D0M
3V3
O
X2_19
W6
KEY_COL2
CAN1_TX
3V3
I/O
X2_20
GND
P
X2_21
W4
KEY_ROW2
CAN1_RX
3V3
I/O
X2_22
J4
HDMI_D1P
HDMI1_D1P
3V3
O
X2_23
GND
P
X2_24
J3
HDMI_D1M
HDMI1_D1M
3V3
O
X2_25
T6
KEY_COL4
CAN2_TX
3V3
I/O
X2_26
GND
P
X2_27
V5
KEY_ROW4
CAN2_RX
3V3
I/O
X2_28
K4
HDMI_D2P
HDMI1_D2P
3V3
O
X2_29
GND
P
X2_30
K3
HDMI_D2M
HDMI1_D2M
3V3
O
X2_31
F4
CSI_CLK0M
CSI_CLK0M
2V5
I
X2_32
GND
P
Description
Ground
Ground
Boot Select pin
Serial ATA Receive
differential pair positive
signal
Boot Select pin
Serial ATA Receive
differential pair negative
signal
Boot Select pin
Ground
Boot Select pin
Serial ATA Transmit
differential pair negative
signal
Ground
Serial ATA Transmit
differential pair positive
signal
2
I C bus clock line
Ground
2
I C bus data line
HDMI differential pair 0
positive signal
Ground
HDMI differential pair 0
negative signal
CAN (controller Area
Network) transmit signal
Ground
CAN (controller Area
Network) receive signal
HDMI differential pair 1
positive signal
Ground
HDMI differential pair 1
negative signal
CAN (controller Area
Network) transmit signal
Ground
CAN (controller Area
Network) receive signal
HDMI differential pair 2
positive signal
Ground
HDMI differential pair 2
negative signal
MIPI Camera Serial Interface
clock pair negative signal
Ground
Page 53 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
PIN
CPU
BALL
X2_33
CPU PAD NAME
Signal
V
I/O
F3
CSI_CLK0P
CSI_CLK0P
2V5
I
X2_34
J6
HDMI_CLKP
HDMI1_CLKP
3V3
O
X2_35
E4
CSI_D0M
CSI_D0M
2V5
I
X2_36
J5
HDMI_CLKM
HDMI1_CLKM
3V3
O
X2_37
E3
CSI_D0P
CSI_D0P
2V5
I
X2_38
GND
P
X2_39
D2
CSI_D1P
CSI_D1P
2V5
I
X2_40
H19
EIM_A25
HDMI1_CEC
1V8
I/O
X2_41
D1
CSI_D1M
CSI_D1M
2V5
I
X2_42
K1
HDMI_HPD
HDMI1_HPD
3V3
I
X2_43
E2
CSI_D2P
CSI_D2P
2V5
I
X2_44
GND
P
X2_45
E1
CSI_D2M
CSI_D2M
2V5
I
X2_46
F10
USB_H1_DN
USB_HOST_DN
3V3
I/O
X2_47
F2
CSI_D3M
CSI_D3M
2V5
I
X2_48
E10
USB_H1_DP
USB_HOST_DP
3V3
I/O
X2_49
F1
CSI_D3P
CSI_D3P
2V5
I
X2_50
X2_51
D10
USB_H1_VBUS
USB_H1_VBUS
GND
5V
I/O
P
X2_52
P5
GPIO_19
USB_H1_OC
3V3
I
X2_53
G1
DSI_D0P
DSI_D0P
2V5
O
X2_54
GND
P
X2_55
G2
DSI_D0M
DSI_D0M
2V5
O
X2_56
D7
CLK1_P
PCIEA_CLKP
2V5
O
X2_57
H1
DSI_D1P
DSI_D1P
2V5
O
X2_58
C7
CLK1_N
PCIEA_CLKN
2V5
O
X2_59
H2
DSI_D1M
DSI_D1M
2V5
O
Description
MIPI Camera Serial Interface
clock pair positive signal
HDMI differential pair clock
positive signal
MIPI Camera Serial Interface
data pair 0 negative signal
HDMI differential pair clock
negative signal
MIPI Camera Serial Interface
data pair 0 positive signal
Ground
MIPI Camera Serial Interface
data pair 1 positive signal
HDMI Consumer Electronics
Control
MIPI Camera Serial Interface
data pair 1 negative signal
HDMI/DP Hot plug detection
signal that serves as an
interrupt request
MIPI Camera Serial Interface
data pair 2 positive signal
Ground
MIPI Camera Serial Interface
data pair 2 negative signal
Universal Serial Bus
differential pair negative
signal
MIPI Camera Serial Interface
data pair 3 negative signal
Universal Serial Bus
differential pair positive
signal
MIPI Camera Serial Interface
data pair 3 positive signal
Universal Serial Bus power
Ground
Active low input, to inform
USB overcurrent condition
(low = overcurrent detected)
MIPI Display Serial Interface
data pair 0 positive signal
Ground
MIPI Display Serial Interface
data pair 0 negative signal
PCI Express clock differential
pair positive signal
MIPI Display Serial Interface
data pair 1 positive signal
PCI Express clock differential
pair negative signal
MIPI Display Serial Interface
data pair 1 negative signal
Page 54 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
PIN
CPU
BALL
CPU PAD NAME
X2_60
Signal
V
GND
I/O
P
X2_61
H3
DSI_CLK0M
DSI_CLK0M
2V5
O
X2_62
B3
PCIE_TXP
PCIEA_TXP
2V5
O
X2_63
H4
DSI_CLK0P
DSI_CLK0P
2V5
O
X2_64
A3
PCIE_TXM
PCIEA_TXN
2V5
O
X2_65
R5
GPIO_8
GPIO_8
3V3
I/O
X2_66
GND
P
X2_67
T3
GPIO_6
GPIO_6
3V3
I/O
X2_68
B2
PCIE_RXP
PCIEA_RXP
2V5
I
X2_69
R7
GPIO_3
GPIO3_CLKO
3V3
I/O
X2_70
B1
PCIE_RXM
PCIEA_RXN
2V5
I
Description
Ground
MIPI Display Serial Interface
clock pair negative signal
PCI Express Transmit output
differential pair positive
signal
MIPI Display Serial Interface
clock pair positive signal
PCI Express Transmit output
differential pair negative
signal
General Purpose Input
Output
Ground
General Purpose Input
Output
PCI Express Receive input
differential pair positive
signal
General Purpose Input
Output
PCI Express Receive input
differential pair negative
signal
Page 55 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
5. Development Kits, Proto-type Components and Accessories
To evaluate the EDM1-CF-IMX6 TechNexion has made available a large number of evaluation kits and
accessories available.
5.1. PICO-IMX6 Evaluation Kits
5.1.1. PICO Evaluation Start Kit Pack Content
Partnumber
PICODWARFIMX6S10R512SDBW
Description
PICO Compute Module Freescale i.MX6 Solo + 512MB RAM +
802.11ac + Bluetooth 4.0 + SD cardslot
PICO Dwarf Carrierboard
4 mounting screws + 8 mounting nuts
Partnumber
PICODWARFIMX6U10R1GBSDBW
Description
PICO Compute Module Freescale i.MX6 Duallite + 1GB RAM +
802.11ac + Bluetooth 4.0 + SD cardslot
PICO Dwarf Carrierboard
4 mounting screws + 8 mounting nuts
Partnumber
PICODWARFIMX6S10R512NI4GBW
Description
PICO Compute Module Freescale i.MX6 Solo + 512MB RAM +
4GB eMMC + 802.11ac + Bluetooth 4.0
PICO Dwarf Carrierboard
4 mounting screws + 8 mounting nuts
Partnumber
PICODWARFIMX6U10R1GBNI4GBW
Description
PICO Compute Module Freescale i.MX6 Duallite + 1GB RAM +
4GB eMMC + 802.11ac + Bluetooth 4.0
PICO Dwarf Carrierboard
4 mounting screws + 8 mounting nuts
Page 56 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
5.2. PICO Compatible Displays
5.2.1. LVDSEXPANDER Translation Board to Connect to LVDS Panels
Partnumber
LVDSEXPANDER
Description
Expansion Translation Board to connect to LVDS Panels
Page 57 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
5.2.2. TDHJ070NA4RESKIT Resistive Touch Display Kit Pack Content
Partnumber
TDHJ070NA4RESKIT
Description
7 inch LVDS interface LCD display 1024*600 resolution 250 nits
with 4 wire resistive touchsensor.
Adaptor interface board to easily connect to EDM Carrier boards
LVDS signal cable
Touch panel link cable
NOTE: To connect to PICO-DWARF or PICO-HOBBIT you will also need to purchase LVDS-EXPANDER.
NOTE: Many other display and touch solutions are available. Please connect with your TechNexion
distributor or account manager for conditions and availability.
Page 58 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
5.2.3. TDHJ070NAPCAPKIT PCAP Touch Display Kit Pack Content
Partnumber
TDHJ070NAPCAPKIT
Description
7 inch LVDS interface LCD display 1024*600 resolution 500 nits
with PCAP multitouch touchsensor.
Adaptor interface board to easily connect to EDM Carrier boards
LVDS signal cable
USB Touch panel link cable
NOTE: To connect to PICO-DWARF or PICO-HOBBIT you will also need to purchase LVDS-EXPANDER.
NOTE: Many other display and touch solutions are available. Please connect with your TechNexion
distributor or account manager for conditions and availability.
Page 59 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
5.3. Accessories
5.3.1. EDMANTP150A138045D2450BK Pack Content.
Partnumber
EDMANTP150A138045D2450BK
Description
4.5 dB, 2.4/5 GHz, black color antenna
u.FL to SMA patch cable
Page 60 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
5.4. PICO Compute Module Product Ordering Part Numbers
The PICO-IMX6 is available in a number of standard configurations. Custom tailored versions with other
memory configuration, de-population of interfaces or extended and industrial temperature options are
available upon request.
5.4.1 Standard Part Numbers
Standard PICO-IMX6 System-on-Modules part numbers can be ordered in multiples of 10 units in the
following configurations.
Standard Part numbers featuring Freescale i.MX6 Solo booting from SD card slot
Part Number
PICOIMX6S10R512SD
PICOIMX6S10R512SDBW
Description
PICO Compute Module Freescale i.MX6 Solo + 512MB RAM +
SD cardslot
PICO Compute Module Freescale i.MX6 Solo + 512MB RAM +
SD cardslot + 802.11ac + Bluetooth 4.0
Standard Part numbers featuring Freescale i.MX6 Solo booting from eMMC
Part Number
PICOIMX6S10R512NI4G
PICOIMX6S10R512NI4GBW
Description
PICO Compute Module Freescale i.MX6 Solo + 512MB RAM +
4GB eMMC
PICO Compute Module Freescale i.MX6 Solo + 512MB RAM +
4GBeMMC + 802.11ac + Bluetooth 4.0
Standard Part numbers featuring Freescale i.MX6 Duallite booting from SD cardslot
Part Number
PICOIMX6U10R1GBSD
PICOIMX6U10R1GBSDBW
Description
PICO Compute Module Freescale i.MX6 Duallite + 1GB RAM +
SD cardslot
PICO Compute Module Freescale i.MX6 Duallite + 1GB RAM +
SD cardslot + 802.11ac + Bluetooth 4.0
Standard Part numbers featuring Freescale i.MX6 Duallite booting from eMMC
Part Number
PICOIMX6S10R1GBNI4G
PICOIMX6S10R1GBNI4GBW
Description
PICO Compute Module Freescale i.MX6 Duallite + 1GB RAM +
4GB eMMC
PICO Compute Module Freescale i.MX6 Duallite + 1GB RAM +
4GBeMMC + 802.11ac + Bluetooth 4.0
Page 61 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
5.4.2. Custom Part Number Creation Rules
The PICO-IMX6 can be ordered in custom tailored to meet special application requirements and
conditions according to the following custom part number creation rules.
Custom part numbers carry minimum order quantities. Please connect with your TechNexion distributor or
account manager for conditions and availability.
Part number format:
PICO-IMX6S10-R512-SD-BW- xx-xxxx
PICO-IMX6S10-R512-NI4G-BW- xx-xxxx
Interface
Processor
Proccesor speed
Memory
Storage
Wireless Networking
Temperature Range
Custom ID
Code
S
U
D
Q
08
10
12
R512
R1GB
R2GB
SD
NIxG
BW
TE
TI
TEC
TIC
XXXX
Description
i.MX6 Solo
i.MX6 Duallite
i.MX6 Dual
i.MX6 Quad
800 Mhz
1 Ghz (Default)
1.2 Ghz
512 MB DDR3
1GB DDR3
2GB DDR3
MicroSD Cardslot
Other capacities of eMMC are possible (8GB, 16GB, 32GB, 64GB)
No
802.11ac + Bluetooth 4.0
Commercial Temperature range (0~60°C) (Default)
Extended Temperature range (-20~70°C)
Industrial Temperature range (-40~85°C)
Certified Extended Temperature range (-20~70°C)
Certified Industrial Temperature range (-40~85°C)
Custom Partnumber ID for customized software loader and special
component (BOM)
NOTE: Wireless Networking option is not available in “TI” Industrial Temperature Range.
Page 62 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
6. Important Notice
TechNexion reserve the right to make corrections, modifications, enhancements, improvements, and
other changes to its products and services at any time and to discontinue any product or service without
notice. Customers should obtain the latest relevant information before placing orders and should verify
that such information is current and complete. All products are sold subject to TechNexion terms and
conditions of sale supplied at the time of order acknowledgment.
TechNexion warrants performance of its hardware products to the specifications applicable at the time of
sale in accordance with TechNexion’s standard warranty. Testing and other quality control techniques are
used to the extent TechNexion deems necessary to support this warranty. Except where mandated by
government requirements, testing of all parameters of each product is not necessarily performed.
TechNexion assumes no liability for applications assistance or customer product design. Customers are
responsible for their products and applications using TechNexion components. To minimize the risks
associated with customer products and applications, customers should provide adequate design and
operating safeguards.
TechNexion does not warrant or represent that any license, either express or implied, is granted under
any TechNexion patent right, copyright, mask work right, or other TechNexion intellectual property right
relating to any combination, machine, or process in which TechNexion products or services are used.
Information published by TechNexion regarding third-party products or services does not constitute a
license from TechNexion to use such products or services or a warranty or endorsement thereof. Use of
such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TechNexion under the patents or other intellectual property of
TechNexion.
TechNexion products are not authorized for use in safety-critical applications (such as life support) where
a failure of the TechNexion product would reasonably be expected to cause severe personal injury or
death, unless officers of the parties have executed an agreement specifically governing such use. Buyers
represent that they have all necessary expertise in the safety and regulatory ramifications of their
applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and
safety-related requirements concerning their products and any use of TechNexion products in such
safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TechNexion. Further, Buyers must fully indemnify TechNexion and its representatives against
any damages arising out of the use of TechNexion products in such safety-critical applications.
TechNexion products are neither designed nor intended for use in military/aerospace applications or
environments unless the TechNexion products are specifically designated by TechNexion as military
grade or "enhanced plastic." Only products designated by TechNexion as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TechNexion products which
TechNexion has not designated as military-grade is solely at the Buyer's risk, and that they are solely
responsible for compliance with all legal and regulatory requirements in connection with such use.
TechNexion products are neither designed nor intended for use in automotive applications or
environments unless the specific TechNexion products are designated by TechNexion as compliant with
ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TechNexion will not be responsible for any failure to meet such
requirements.
Page 63 of 64
PICO-IMX6 REV. A1. HARDWARE MANUAL – VER 1.00 – SEP 30 2015
7. DISCLAIMER
© 2013-2015 TechNexion Ltd.
All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means whether, electronic, mechanical, or otherwise without
the prior written permission of TechNexion Ltd.
No warranty of accuracy is given concerning the contents of the information contained in this publication.
To the extent permitted by law no liability (including liability to any person by reason of negligence) will be
accepted by TechNexion Ltd., its subsidiaries or employees for any direct or indirect loss or damage
caused by omissions from or inaccuracies in this document.
TechNexion Ltd. reserves the right to change details in this publication without notice.
Product and company names herein may be the trademarks of their respective owners.
TechNexion Ltd.
16F-5, No. 736, Zhongzheng Road,
ZhongHe District, 23511, New Taipei City, Taiwan
Phone : +886-2-82273585
Fax
: +886-2-82273590
E-mail : [email protected]
Web
: http://www.technexion.com/
Page 64 of 64
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