datasheet for SDR12872D1B62MT
Data Sheet
Rev.1.0
22.05.2008
1GB DDR – SDRAM registered DIMM
Features:
184Pin ECC Registered DIMM
SDR12872D1B62MT-50R
1GB PC 3200 in FBGA Technique
RoHS compliant
Options:
1
Frequency / Latency
DDR400 MHz CL3
DDR 333 MHz CL2,5
1
Module densities
1024MB with 18 dies and 2 ranks
1
Standard Grade
Marking
-50
-60
Tambient
0°C to 70°C
Environmental Requirements:
1
1
1
1
1
1
Operating temperature (ambient)
Standard Grade
0°C to 70°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
1 184-pin 72-bit Dual-In-Line module.
Double Date Rate synchronous DRAM
Module for server applications
1 DDR-SDRAM component base: MICRON
MT46V64M8P-5B-F
1 VDD 2.5V ±0.2V, VDDQ 2.5V ±0.2V
1 Registered Inputs with one-clock delay
1 Phase-lock loop (PLL) clock driver to reduce
loading
1 Supports ECC error detection and correction
1 Programmable CAS Latency, Burst Length
and Wrap Sequence
1 Auto Refresh (CBR) and Self Refresh
1 Posted CAS by programmable additive
latency for better command and data bus
efficiency
1 2.5V I/O ( SSTL_2 compatible)
1 Serial Presence Detect with EEPROM
1 Gold-contact pad
1 This module family is fully pin and functional
compatible to the JEDEC DDR1 spec.
1 The pcb and all components are
manufactured according to the RoHS
compliance specification
[EU Directive 2002/95/EC Restriction of
Hazardous Substances (RoHS)]
Figure: mechanical dimensions
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 1
of 13
Data Sheet
Rev.1.0
22.05.2008
This Swissbit module family is industry standard 184-pin 8-byte Double Date rate synchronous SDRAM Dual-In-line
Memory Modules (DIMMs), which are organized as x72 high speed memory arrays designed for use in server
applications. These DIMMs are assembled in FBGA Technology. The passive devices and the EEPROM are SMD
components.
The DIMMs use serial presence detects (SPD) implemented via serial EEPROM using the two-pin-I2C protocol.
The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.
All Swissbit DIMMs provide a high performance, flexible 8-byte interface in a 133,35mm long footprint.
All modules of the extended temperature grade have seen special tests during the manufacturing process to
ensure proper operation according to the field of operation as stated in the environmental conditions.
Module Configuration
Organization
DDR SDRAMs
used
Row
Addr.
Bank
Select
Col.
Addr.
Refresh
128M x 72
18 x 128M x 8
14
BA0, BA1
12
8k
Module Dimensions
in mm
133,35 max
Product Spectrum
Part Number
Module Density
Transfer Rate
Memory clock/Data
bit rate
Latency
SDR12872D1B62MT-50R
1GB
3.2 GB/s
5.0ns/400MT/s
3200-333
SDR12872D1B62MT-60R
1GB
2.7 GB/s
6.0ns/333MT/s
2700-2533
Pin Name
A0-A12
Address Inputs
BA0, BA1
Bank Selects
DQ0 – DQ63
Data Input/Output
CB0 - CB7
Check Bits
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Read / Write Enable
CKE0 – CKE1
Clock Enable
CK0 – CK2
Clock Inputs, positive line
/CK0 – /CK2
Clock Inputs, negative line
DQS0- DQS17
Data strobes
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 2
of 13
Data Sheet
/S0, /S1
Chip Select
VDD
Power (2.5V± 0.2V)
VDDQ
DQ Power (2.5V±0.2V)
VDDSPD
SPD Power
VREF
Input/Output Reference
Vss
Ground
SCL
Clock for Presence Detect
Rev.1.0
SDA
Serial Data Out for Presence Detect
SA0 – SA2
Slave Address Select Bus for Presence Detect
NC
No Connection
22.05.2008
Pin Configuration
Front Side
PIN #
PIN Name
PIN #
Back Side
PIN Name
PIN #
PIN Name
PIN #
PIN Name
1
VREF
47
DQS8
93
VSS
139
VSS
2
DQ0
48
A0
94
DQ4
140
DQS17
3
VSS
49
CB2
95
DQ5
141
A10
4
DQ1
50
VSS
96
VDDQ
142
CB6
5
DQS0
51
CB3
97
DQS9
143
VDDQ
6
DQ2
52
BA1
98
DQ6
144
CB7
7
VDD
53
DQ32
99
DQ7
145
VSS
8
DQ3
54
VDDQ
100
VSS
146
DQ36
9
NC
55
DQ33
101
NC
147
DQ37
10
/Reset
56
DQS4
102
NC
148
VDD
11
VSS
57
DQ34
103
NC
149
DQS13
12
DQ8
58
VSS
104
VDDQ
150
DQ38
13
DQ9
59
BA0
105
DQ12
151
DQ39
14
DQS1
60
DQ35
106
DQ13
152
VSS
15
VDDQ
61
DQ40
107
DQS10
153
DQ44
16
NC
62
VDDQ
108
VDD
154
/RAS
17
NC
63
/WE
109
DQ14
155
DQ45
18
VSS
64
DQ41
110
DQ15
156
VDDQ
19
DQ10
65
/CAS
111
CKE1
157
/S0
20
DQ11
66
VSS
112
VDDQ
158
/S1
21
CKE0
67
DQS5
113
NC
159
DQS14
22
VDDQ
68
DQ42
114
DQ20
160
VSS
23
DQ16
69
DQ43
115
A12
161
DQ46
24
DQ17
70
VDD
116
VSS
162
DQ47
25
DQS2
71
NC
117
DQ21
163
NC
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 3
of 13
Data Sheet
Rev.1.0
Front Side
PIN #
PIN Name
PIN #
Back Side
PIN Name
PIN #
PIN Name
PIN #
PIN Name
26
VSS
72
DQ48
118
A11
164
VDDQ
27
A9
73
DQ49
119
DQS11
165
DQ52
28
DQ18
74
VSS
120
VDD
166
DQ53
29
A7
75
NC
121
DQ22
167
NC
30
VDDQ
76
NC
122
A8
168
VDD
31
DQ19
77
VDDQ
123
DQ23
169
DQS15
32
A5
78
DQS6
124
VSS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
34
VSS
80
DQ51
126
DQ28
172
VDDQ
35
DQ25
81
VSS
127
DQ29
173
NC
36
DQS3
82
VDDID
128
VDDQ
174
DQ60
37
A4
83
DQ56
129
DQS12
175
DQ61
38
VDD
84
DQ57
130
A3
176
VSS
39
DQ26
85
VDD
131
DQ30
177
DQS16
40
DQ27
86
DQS7
132
VSS
178
DQ62
41
A2
87
DQ58
133
DQ31
179
DQ63
42
VSS
88
DQ59
134
CB4
180
VDDQ
43
A1
89
VSS
135
CB5
181
SA0
44
CB0
90
NC
136
VDDQ
182
SA1
45
CB1
91
SDA
137
CK0
183
SA2
46
VDD
92
SCL
138
/CK0
184
VDDSPD
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
22.05.2008
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 4
of 13
Data Sheet
Rev.1.0
22.05.2008
FUNCTIONAL BLOCK DIAGRAMM 1GB 2 Ranks DDR-SDRAM DIMM
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 5
of 13
Data Sheet
Rev.1.0
22.05.2008
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C 1 TA 1 + 70°C ; V DD = +2.5V ± 0.2V, VDDQ = +2.5V ± 0.2V) see Note 1 on Page 9
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT
Any input 0V 1 VIN 1 VDD, VREF pin 0V 1 VIN 11.35V
SYMBOL
VDD
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
MIN
2.3
2.3
0.49 x VDDQ
VREF – 0.04
VREF + 0.15
-0.3
MAX
2.7
2.7
0.51x VDDQ
VREF + 0.04
VDD + 0.3
VREF – 0.15
UNITS
V
V
V
V
V
V
II
-10
10
µA
IOZ
-10
10
µA
IOH
-16.8
-
mA
IOL
16.8
-
mA
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
(DQS are disabled; 0V 1 VOUT 1 VDDQ)
OUTPUT LEVELS:
High Current (VOUT = VDDQ-0.373V,minimum VREF,
minimum VTT )
Low Current (VOUT =0.373V, maximum VREF,
maximum VTT )
AC INPUT OPERATING CONDITIONS
(0°C 1 TA 1 + 70°C ; V DD = +2.5V ± 0.2V, VDDQ = +2.5V ± 0.2V) see Note 1 on Page 9
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
I/O Reference Voltage
SYMBOL
VIH (AC)
VIL (AC)
VREF(AC)
MIN
VREF + 0.310
0.49 x VDDQ
MAX
VREF - 0.310
0.51x VDDQ
UNITS
V
V
V
MAX
5.0
27.0
27.0
14.0
27.0
UNITS
pF
pF
pF
pF
pF
CAPACITANCE
PARAMETER
Input/Output Capacitance: DQ, DQS
Input Capacitance: Command and Address
Input Capacitance: /S 0,1
Input Capacitance: CK, /CK
Input Capacitance: CKE
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
SYMBOL
C10
C11
C11
C12
C13
MIN
4.0
18.0
18.0
10.0
18.0
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eMail: [email protected]
Page 6
of 13
Data Sheet
Rev.1.0
22.05.2008
IDD Specifications AND CONDITIONS
(0°C 1 TA 1 + 70°C ; V DDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
Parameter
& Test Condition
OPERATING CURRENT *) : One device bank; ActivePrecharge;
tRC= tRC (Min); tCK = tCK (Min); DQ, DM and DQS inputs
changing
once per clock cycle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT :*)
One device bank; Active-Read-Precharge;
Burst = 2; tRC= tRC (Min);
tCK = tCK (Min);IOUT = 0mA;
Address and control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN STANDBY CURRENT:
All device banks idle;
Power-down mode;
tCK = tCK (Min); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device
banks idle;
tCK = tCK (Min); CKE= HIGH; Address and other control
inputs changing once per clock cycle.
VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One
device bank active; Power-down mode; tCK = tCK
(Min);CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE =
HIGH; One device bank; Active-Precharge; tRC= tRAS
(Max); tCK = tCK (Min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT:
Burst = 2; Reads; Continous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK = tCK (Min);
IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (Min);
DQ, DM, and DQS inputs changing twice per clock
cycle
AUTO
tRC = tRC (Min)
REFRESH
tRC = 7.8125µs
CURRENT
SELF REFRESH CURRENT: CKE 1 0.2V
Symb.
max.
Unit
3200-3033
2700-2533
IDDO
1440
1215
mA
IDD1
2160
1485
mA
IDD2P
90
90
mA
IDD2F
990
810
mA
IDD3P
810
630
mA
IDD3N
1080
900
mA
IDD4R
4815
1530
mA
IDD4W
1854
1620
mA
IDD5
6210
5220
mA
IDD6
198
180
mA
IDD7
90
90
mA
OPERATING CURRENT*): Four device bank interleaving
IDD8
mA
4050
3690
READs (BL =4) with auto precharge, tRC = tRC (Min);
tCK = tCK (Min); Address and control inputs change only during
Active READ, or WRITE commands
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 7
of 13
Data Sheet
Rev.1.0
22.05.2008
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C 1 TA 1 + 70°C ; V DDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
AC CHARACTERISTICS
PARAMETER
Access window of DQS CK/CK#
CK high-level width
CK low-level width
Clock cycle time CL=2.0
CL=2.5
CL=3.0
DQ and DM input hold time relative
to DQS
DQ and DM input setup time relative
to DQS
DQ and DM input pulse width
( for each input )
Access window of DQS from
CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS –DQ skew, DQS to last DQ
valid, per group, per access
Write command to first DQS latching
transition
DQS falling edge to CK rising- setup
time
DQS falling edge from CK risinghold time
Half clock period
Data-out high-impedance window
from CK/CK#
Data-out low-impedance window
from CK/CK#
Address and control input hold time
( fast slew rate )
Address and control input setup time
( fast slew rate )
Address and control input hold time
( slow slew rate )
Address and control input setup time
( slow slew rate )
LOAD MODE REGISTER command
cycle time
Adress and control input pulse width
(for each input)
DQ-DQS hold, DQS to first DQ to go
non-valid, per access
Data hold skew factor
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
3200-3033
SYMBOL
tck (2.5)
tck (3.0)
MIN
-0.70
0.45
0.45
7.5
6.0
5.0
tDH
0.40
0.45
ns
tDS
0.40
0.45
ns
tDIPW
1.75
1.75
ns
tDQSCK
-0.6
tDQSH
tDQSL
0.35
0.35
tAC
tCH
tCL
tck (2.0)
tDQSQ
MAX
+0.70
0.55
0.55
13.0
13.0
13.0
2700-2533
+0.6
MIN
-0.70
0.45
0.45
7.5
6.0
-0.6
MAX
+0.70
0.55
0.55
13.0
13.0
+0.6
0.35
0.35
0.40
Unit
ns
tCK
tCK
ns
ns
ns
tCK
tCK
0.45
ns
1.25
tCK
tDQSS
0.72
tDSS
0.2
0.2
tCK
tDSH
0.2
0.2
tCK
tHP
tch,
tcl
tch,
tcl
ns
tHZ
1.28
0.75
+0.7
+0.7
ns
tLZ
-0.7
-0.7
ns
tIHF
0.6
0.75
ns
tISF
0.6
0.75
ns
tIHS
0.6
0.8
ns
tISS
0.6
0.8
ns
tMRD
10
12
ns
tIPW
2.2
2.2
ns
tQH
tQHS
tHP - tQHS
0.5
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
tHP - tQHS
0.6
ns
ns
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Page 8
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Data Sheet
AC CHARACTERISTICS
PARAMETER
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto
precharge
command
ACTIVE to ACTIVE/AUTO
REFRESH
command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b
command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command
delay
Data valid output window
REFRESH to REFRESH command
interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ
command
Exit SELF REFRESH to READ
command
3200-3033
SYMBOL
tRAS
tRAP
MIN
40
MAX
70.000
Rev.1.0
2700-2533
MIN
42
15
15
55
60
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
70
15
15
0.9
0.4
72
15
15
0.9
0.4
10
12
tWPRE
tWPRES
tWPST
tWR
tWTR
0.25
0
0.4
15
0.25
0
0.4
15
MAX
70.000
Unit
ns
ns
ns
tRC
na
tREFC
22.05.2008
1.1
0.6
0.6
2
1.1
0.6
0.6
1
tQH - tDQSQ
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
tQH - tDQSQ
70.3
70.3
tREFI
tVTD
tXSNR
0
0
70
75
tXSRD
200
200
7.8
µs
ns
ns
7.8
tCK
Note 1: Values for AC timing, IDD, and electrical AC and DC characteristics might have been collected within the
standard temperature range and at nominal reference/supply voltage levels, but the related specifications and
device operation are guaranteed for the full voltage range specified and for the corresponding field of operation
according to the actual temperature grade of the module (extended E, I or W; refer to the environmental conditions
for more details).
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 9
of 13
Data Sheet
Rev.1.0
22.05.2008
Register Timing Requirements and Switching Characteristics
Register
SSTL (bit
pattern
by JESD82-3
or JESD82-4)
Symbol Parameter
fclock
tpd
tPHL
tw
tact
tinact
tsu
th
0°C 1 TA 1 +70°C
VDD = +2.5V ±0.2V
Condition
Clock Frequency
Clock to Output Time
Reset To Output Time
Pulse Duration
Differential Inputs Active Time
Differential Inputs Inactive
Time
Setup Time, Fast Slew Rate
Setup Time, Slow Slew Rate
Hold Time, Fast Slew Rate
Hold Time, Slow Slew Rate
30pF to GND and
50 Ohms to VTT
CK, CK# HIGH or LOW
Data Before CK
HIGH, CK# LOW
Data After CK
HIGH, CK# LOW
Min
1,1
2,5
-
Max
200
2,8
5
22
-
22
0,75
0,9
0,75
0,9
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2
3
4,6
5,6
4,6
5,6
NOTE:
1. The timing and switching specifications for the register listed above are critical for proper operation of the DDR SDRAM
Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed
information for this register is available in JEDEC Standard JESD82-4.
2. Data inputs must be low a minimum time of tact max, after RESET# is taken HIGH.
3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET# is taken LOW.
4. For data signal input slew rate ≥ 1 V/ns.
5. For data signal input slew rate ≥ 0.5 V/ns and < 1V/ns.
6. CK, CK# signals input slew rate ≥ 1V/ns.30
PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter
0°C 1 TA 1 +70°C
VDD = +2.5V ±0.2V
Symbol
Min
60
40
-75
-50
-75
-100
1,0
1,0
Nominal
0
-
Units Notes
Max
170
60
100
75
50
100
75
100
4
2
Operating Clock Frequency
fck
MHz
2,3
Input Duty Cycle
tDC
%
Stabilization Time
tSTAB
ms
4
Cycle to Cycle Jitter
tJITTCC
ps
Static Phase Offset
ps
5
t∅
Output Clock Skew
tSKo
ps
Period Jitter
tJITTPER
ps
6
Half-Period Jitter
tJITTHPER
ps
6
Input Clock Slew Rate
tLSI
V/ns
Output Clock Slew Rate
tLSO
V/ns
NOTE:
1. The timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM
Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed
information for this PLL is available in JEDEC Standard JESD82.
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet
the other timing parameters. (Used for low speed system debug.)
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference
signal after power up.
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 10
of 13
Data Sheet
Rev.1.0
22.05.2008
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
0
1
2
3
4
5
6
7
8
9
NUMBER OF SPD BYTES USED
TOTAL NUMBER OF BYTES IN SPD DEVICE
FUNDAMENTAL MEMORY TYPE
NUMBER OF ROW ADDRESSES ON ASSEMBLY
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
NUMBER OF PHYSICAL BANKS ON DIMM
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS (VDDQ)
SDRAM CYCLE TIME, (tCK )
(CAS LATENCY =2.5 (2700, 2100) ; CL=3* (3200)
SDRAM ACCESS FROM CLOCK, (tAC)
(CAS LATENCY =2.5 (2700, 2100); CL=3* (3200))
MODULE CONFIGURATION TYPE
REFRESH RATE/ TYPE
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
ERROR- CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY, BACK- TO- BACK
RANDOM COLUMN ACCESS
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
CS LATENCY
WE LATENCY
SDRAM MODULE ATTRIBUTES
SDRAM DEVICE ATTRIBUTES: GENERAL
SDRAM CYCLE TIME, (tCK)
(CAS LATENCY=2(2700, 2100) CL=2,5*(3200))
SDRAM ACCESS FROM CK, (tAC)
(CAS LATENCY=2(2700, 2100) CL=2.5*(3200)
SDRAM CYCLE TIME, (tCK)
(CAS LATENCY=1.5(2700, 2100) CL=2*(3200))
SDRAM ACCESS FROM CK, (tAC)
(CAS LATENCY=1.5(2700, 2100) CL=2*(3200)
MINIMUM ROW PRECHARGE TIME, (tRP)
MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD)
MINIMUM RAS# TO CAS# DELAY, (tRCD)
MINIMUM RAS# PULSE WIDTH, (tRAS)
MODULE BANK DENSITY
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
3200-3033
2700-2533
0x80
0x08
0x07
0x0d
0x0b
0x02
0x48
0x00
0x04
0x50
0x60
0x70
0x70
0x02
0x82
0x08
0x08
0x01
0x0e
0x04
0x1c
0x0c
0x01
0x02
0x26
0xc0
0x60
0x75
0x70
0x70
0x75
0x00
0x75
0x00
0x3c
0x28
0x3c
0x28
0x48
0x30
0x48
0x2a
0x80
www.swissbit.com
eMail: [email protected]
Page 11
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Data Sheet
Rev.1.0
22.05.2008
SERIAL PRESENCE-DETECT MATRIX (continued)
BYTE
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
64
65
66
67
72
73-90
91
92
93
94
95-98
99-127
DESCRIPTION
3200-3033
0x60
0x60
0x40
0x40
ADDRESS AND COMMAND SETUP TIME, (tIS)
ADDRESS AND COOMAND HOLD TIME, (tIH)
DATA/DATA MASK INPUT SETUP TIME, (tDS)
DATA/DATA MASK INPUT HOLD TIME, (tDH)
RESERVED
MIN ACTIVE AUTO REFRESH TIME (tRC)
MINIMUM AUTO REFRESH TO ACTIVE/
AUTO REFRESH COMMAND PERIOD, (tRFC)
SDRAM DEVICE MAX CYCLE TIME (tCKMAX)
SDRAM DEVICE MAX DQS-DQ SKEW TIME
(tDQSQ)
SDRAM DEVICE MAX READ DATA HOLD SKEW
FACTOR (tQHS)
RESERVED
SPD REVISION
CHECKSUM FOR BYTES 0-62
MANUFACTURER`S JEDEC ID CODE
MANUFACTURER`S JEDEC ID CODE
MANUFACTURER`S JEDEC ID CODE
MANUFACTURER`S JEDEC ID CODE
(continued)
MANUFACTURING LOCATION
MODULE PART NUMBER (ASCII)
PCB IDENTIFICATION CODE
IDENTIFICATION CODE (continued)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
MODULE SERIAL NUMBER
MANUFACTURER-SPECIFIC DATA (RSVD)
2700-2533
0x80
0x80
0x45
0x45
0x00
0x37
0x3c
0x46
0x48
0x30
0x28
0x2d
0x50
0x60
0x00
0x11
0xd9
0x8c
7F
7F
7F
DA
x
“SDR12872D1B62MT-xx”
x
x
x
x
xx
Part Number Code
S
D
R
128
72
D1
B
6
2
MT
1
2
3
4
5
6
7
8
9
10
-
50
*
R
11
12
13
*RoHs compl.
DDR-400MHz
Swissbit AG
SDRAM DDR1
184 Pin Registered 2.5V
Depth (1024MB)
Width
PCB-Type (BRDA80A)
Chip Vendor (Micron)
2 Module Ranks
Chip Rev. F
Chip organisation x8
* optional / additional information
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 12
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Data Sheet
Rev.1.0
22.05.2008
Locations
Swissbit AG
Industriestrasse 4 – 8
CH – 9552 Bronschhofen
Switzerland
Phone: +41 (0)71 913 72 66
Fax: +41 (0)71 913 74 50
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone: +49 (0)30 93 69 54 – 0
Fax: +49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
18 Willett Avenue, Suite 203
Port Chester, NY 10573
USA
Phone: +1 914 935 1400
Fax: +1 914 935 9865
_____________________________
Swissbit NA, Inc.
7801 North Lamar Boulevard, Suite E – 186
Austin, TX 78752
USA
Phone: +1 512 302 9001
Fax: +1 512 302 4808
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 13
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