ATmega8_L

ATmega8_L

Features

High-performance, Low-power Atmel

®

AVR

®

8-bit Microcontroller

Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution

– 32 × 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16MHz

– On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

– 8Kbytes of In-System Self-programmable Flash program memory

– 512Bytes EEPROM

– 1Kbyte Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Three PWM Channels

– 8-channel ADC in TQFP and QFN/MLF package

Eight Channels 10-bit Accuracy

– 6-channel ADC in PDIP package

Six Channels 10-bit Accuracy

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

I/O and Packages

– 23 Programmable I/O Lines

– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF

Operating Voltages

– 2.7V - 5.5V (ATmega8L)

– 4.5V - 5.5V (ATmega8)

Speed Grades

– 0 - 8MHz (ATmega8L)

– 0 - 16MHz (ATmega8)

Power Consumption at 4Mhz, 3V, 25°C

– Active: 3.6mA

– Idle Mode: 1.0mA

– Power-down Mode: 0.5µA

8-bit with 8KBytes In-

System

Programmable

Flash

ATmega8

ATmega8L

Summary

Rev. 2486ZS–AVR–02/11

Pin

Configurations

(RESET) PC6

(RXD) PD0

(TXD) PD1

(INT0) PD2

(INT1) PD3

(XCK/T0) PD4

VCC

GND

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0

8

9

10

11

12

13

14

5

6

3

4

7

1

2

PDIP

21

20

19

18

17

16

15

28

27

26

25

24

23

22

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

PC1 (ADC1)

PC0 (ADC0)

GND

AREF

AVCC

PB5 (SCK)

PB4 (MISO)

PB3 (MOSI/OC2)

PB2 (SS/OC1B)

PB1 (OC1A)

TQFP Top View

(INT1) PD3

(XCK/T0) PD4

GND

VCC

GND

VCC

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

5

6

3

4

1

2

7

8

20

19

18

17

24

23

22

21

PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK)

ATmega8(L)

MLF Top View

(INT1) PD3

(XCK/T0) PD4

GND

VCC

GND

VCC

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

5

6

3

4

1

2

7

8

20

19

18

17

24

23

22

21

PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK)

NOTE:

The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.

2

2486ZS–AVR–02/11

Overview

Block Diagram

ATmega8(L)

The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture.

By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

Figure 1. Block Diagram

XTAL1

RESET

VCC

PC0 - PC6 PB0 - PB7

XTAL2

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

GND

PORTB DRIVERS/BUFFERS

PORTB DIGITAL INTERFACE

AGND

AREF

MUX &

ADC

ADC

INTERFACE

PROGRAM

COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

AVR CPU

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

X

Y

Z

ALU

STATUS

REGISTER

PROGRAMMING

LOGIC

+

-

SPI

COMP.

INTERFACE

TWI

TIMERS/

COUNTERS

OSCILLATOR

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

INTERRUPT

UNIT

OSCILLATOR

EEPROM

USART

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

PD0 - PD7

3

2486ZS–AVR–02/11

Disclaimer

ATmega8(L)

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8 provides the following features: 8 Kbytes of In-System Programmable Flash with

Read-While-Write capabilities, 512 bytes of EEPROM, 1 Kbyte of SRAM, 23 general purpose

I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Twowire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with

10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the

AVR core. The boot program can use any interface to download the application program in the

Application Flash memory. Software in the Boot Flash Section will continue to run while the

Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel

ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.

The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Minimum and Maximum values will be available after the device is characterized.

4

2486ZS–AVR–02/11

ATmega8(L)

Pin Descriptions

VCC

GND

Port B (PB7..PB0)

XTAL1/XTAL2/TOSC1/

TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting

Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1

input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in “Alternate Functions of Port B” on page

58 and “System Clock and Clock Options” on page 25 .

Port C (PC5..PC0)

Digital supply voltage.

Ground.

PC6/RESET

Port D (PD7..PD0)

RESET

Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in Table 15 on page 38 . Shorter pulses are not guaranteed to generate a Reset.

The various special features of Port C are elaborated on page 61 .

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8 as listed on page

63 .

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page

38 . Shorter pulses are not guaranteed to generate a reset.

5

2486ZS–AVR–02/11

ATmega8(L)

AV

CC

AREF

ADC7..6 (TQFP and

QFN/MLF Package

Only)

AV

CC

is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to V

CC

, even if the ADC is not used. If the ADC is used, it should be connected to V

CC

through a low-pass filter. Note that Port C (5..4) use digital supply voltage, V

CC

.

AREF is the analog reference pin for the A/D Converter.

In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the A/D converter.

These pins are powered from the analog supply and serve as 10-bit ADC channels.

2486ZS–AVR–02/11

6

ATmega8(L)

Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr .

Note: 1.

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

2486ZS–AVR–02/11

7

ATmega8(L)

Register Summary

Name

PIND

SPDR

SPSR

SPCR

UDR

UCSRA

UCSRB

UBRRL

ACSR

ADMUX

ADCSRA

ADCH

ADCL

TWDR

TWAR

UCSRC

EEARH

EEARL

EEDR

EECR

Reserved

Reserved

Reserved

PORTB

DDRB

PINB

PORTC

DDRC

PINC

PORTD

DDRD

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

TCCR2

TCNT2

OCR2

ASSR

WDTCR

UBRRH

SREG

SPH

SPL

Reserved

GICR

GIFR

TIMSK

TIFR

SPMCR

TWCR

MCUCR

MCUCSR

TCCR0

TCNT0

OSCCAL

SFIOR

Bit 7

I

SP7

COM1A1

ICNC1

FOC2

SPIF

SPIE

RXC

RXCIE

ACD

REFS1

ADEN

TWA6

0x20 (1) (0x40) (1)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

Address

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

INT1

INTF1

OCIE2

OCF2

SPMIE

TWINT

SE

URSEL

URSEL

EEAR7

PORTB7

DDB7

PINB7

PORTD7

DDD7

PIND7

COM1A0

ICES1

WGM20

UMSEL

EEAR6

TWA5

PORTB6

DDB6

PINB6

PORTC6

DDC6

PINC6

PORTD6

DDD6

PIND6

WCOL

SPE

TXC

TXCIE

ACBG

REFS0

ADSC

Bit 6

T

SP6

INT0

INTF0

TOIE2

TOV2

RWWSB

TWEA

SM2

Bit 5

H

SP5

Bit 4

S

SP4

Bit 3

V

SP3

Bit 2

N

SP10

SP2

Bit 1

Z

SP9

SP1

TICIE1

ICF1

TWSTA

SM1

OCIE1A

OCF1A

RWWSRE

TWSTO

SM0

OCIE1B

OCF1B

BLBSET

TWWC

ISC11

WDRF

– –

Timer/Counter0 (8 Bits)

Oscillator Calibration Register

– ACME PUD

COM1B1

COM1B0

WGM13

FOC1A

WGM12

Timer/Counter1 – Counter Register High byte

Timer/Counter1 – Counter Register Low byte

FOC1B

CS12

Timer/Counter1 – Output Compare Register A High byte

Timer/Counter1 – Output Compare Register A Low byte

Timer/Counter1 – Output Compare Register B High byte

Timer/Counter1 – Output Compare Register B Low byte

TOIE1

TOV1

PGWRT

TWEN

ISC10

BORF

CS02

PSR2

WGM11

CS11

Timer/Counter1 – Input Capture Register High byte

Timer/Counter1 – Input Capture Register Low byte

COM21 COM20 WGM21

Timer/Counter2 (8 Bits)

CS22

Timer/Counter2 Output Compare Register

UPM1

EEAR5

WDCE

UPM0

USBS

EEAR4 EEAR3

EEPROM Data Register

AS2

WDE

EERIE

TCN2UB

WDP2

UCSZ1

EEAR2

EEMWE

CS21

OCR2UB

WDP1

UBRR[11:8]

UCSZ0

EEAR1

EEWE

IVSEL

PGERS

ISC01

EXTRF

CS01

PORTB5

DDB5

PINB5

PORTC5

DDC5

PINC5

PORTD5

DDD5

PIND5

DORD

UDRE

UDRIE

ACO

ADLAR

ADFR

TWA4

PORTB4

DDB4

PINB4

PORTC4

DDC4

PINC4

PORTD4

DDD4

PORTB3

DDB3

PINB3

PORTC3

DDC3

PINC3

PORTD3

DDD3

PIND4 PIND3

SPI Data Register

MSTR

CPOL

USART I/O Data Register

FE DOR

RXEN TXEN

USART Baud Rate Register Low byte

PORTB2

DDB2

PINB2

PORTC2

DDC2

PINC2

PORTD2

DDD2

PIND2

CPHA

PE

UCSZ2

ACI

ADIF

ACIE

MUX3

ADIE

ADC Data Register High byte

ADC Data Register Low byte

Two-wire Serial Interface Data Register

TWA3 TWA2

ACIC

MUX2

ADPS2

TWA1 TWA0

PORTB1

DDB1

PINB1

PORTC1

DDC1

PINC1

PORTD1

DDD1

PIND1

SPR1

U2X

RXB8

ACIS1

MUX1

ADPS1

PORTB0

DDB0

PINB0

PORTC0

DDC0

PINC0

PORTD0

DDD0

PIND0

SPI2X

SPR0

MPCM

TXB8

ACIS0

MUX0

ADPS0

TWGCE

Bit 0

C

SP8

SP0

IVCE

TOIE0

TOV0

SPMEN

TWIE

ISC00

PORF

CS00

PSR10

WGM10

CS10

CS20

TCR2UB

WDP0

UCPOL

EEAR8

EEAR0

EERE

Page

11

13

13

117

43

152

150

100

114

116

116

20

20

20

20

49

,

67

67

72

,

100

,

119

72

,

101

,

119

206

165

33

,

66

41

71

72

31

58

,

74

,

120

,

186

96

99

99

99

100

98

99

99

99

127

126

125

148

65

65

65

65

65

65

65

65

65

148

149

152

186

199

200

201

201

167

167

8

2486ZS–AVR–02/11

ATmega8(L)

Register Summary (Continued)

Address

0x01 (0x21)

0x00 (0x20)

Name

TWSR

TWBR

Bit 7

TWS7

Bit 6

TWS6

Bit 5

TWS5

Bit 4 Bit 3

TWS4 TWS3

Two-wire Serial Interface Bit Rate Register

Bit 2

Bit 1

TWPS1

Bit 0

TWPS0

Page

166

165

Notes: 1. Refer to the USART description ( “USART” on page 129 ) for details on how to access UBRRH and UCSRC ( “Accessing

UBRRH/UCSRC Registers” on page 146 )

2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written

3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only

2486ZS–AVR–02/11

9

Instruction Set Summary

Mnemonics Operands Description

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

SBIC

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

RET

RETI

CPSE

CP

CPC

CPI

SBRC

SBRS

SBC

SBCI

SBIW

AND

ANDI

OR

ORI

EOR

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr

ADC

ADIW

SUB

SUBI

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

COM

NEG

SBR

CBR

INC

DEC

TST

CLR

SER

MUL

MULS

MULSU

Rd

Rd, Rr

Rd, Rr

Rd, Rr

FMUL

FMULS

Rd, Rr

Rd, Rr

FMULSU Rd, Rr

BRANCH INSTRUCTIONS

k RJMP

IJMP

RCALL

ICALL k

Rd

Rd

Rd

Rd

Rd

Rd

Rd,K

Rd,K

k

k

k

k

k

k

k

k

k

k

k

k

k

k

k

k

P, b

P, b s, k s, k

Rd,Rr

Rd,Rr

Rd,Rr

Rd,K

Rr, b

Rr, b

Add two Registers

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Multiply Unsigned

Multiply Signed

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Relative Jump

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

Interrupt Return

Compare, Skip if Equal

Compare

Compare with Carry

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

2486ZS–AVR–02/11

ATmega8(L)

Operation

Rd

← Rd + Rr

Rd

← Rd + Rr + C

Rdh:Rdl

← Rdh:Rdl + K

Rd

← Rd - Rr

Rd

← Rd - K

Rd

← Rd - Rr - C

Rd

← Rd - K - C

Rdh:Rdl

← Rdh:Rdl - K

Rd

← Rd • Rr

Rd

← Rd • K

Rd

← Rd v Rr

Rd

← Rd v K

Rd

← Rd ⊕ Rr

Rd

← 0xFF − Rd

Rd

← 0x00 − Rd

Rd

← Rd v K

Rd

← Rd • (0xFF - K)

Rd

← Rd + 1

Rd

← Rd − 1

Rd

← Rd • Rd

Rd

← Rd ⊕ Rd

Rd

← 0xFF

R1:R0

← Rd x Rr

R1:R0

← Rd x Rr

R1:R0

← Rd x Rr

R1:R0

← (Rd x Rr)

<< 1

R1:R0

← (Rd x Rr)

<< 1

R1:R0

← (Rd x Rr)

<< 1

PC

← PC + k + 1

PC

← Z

PC

← PC + k + 1

PC

← Z

PC

← STACK

PC

← STACK if (Rd = Rr) PC

← PC + 2 or 3

Rd

− Rr

Rd

− Rr − C

Rd

− K if (Rr(b)=0) PC

← PC + 2 or 3 if (Rr(b)=1) PC

← PC + 2 or 3 if (P(b)=0) PC

← PC + 2 or 3 if (P(b)=1) PC

← PC + 2 or 3 if (SREG(s) = 1) then PC

←PC+k + 1 if (SREG(s) = 0) then PC

←PC+k + 1 if (Z = 1) then PC

← PC + k + 1 if (Z = 0) then PC

← PC + k + 1 if (C = 1) then PC

← PC + k + 1 if (C = 0) then PC

← PC + k + 1 if (C = 0) then PC

← PC + k + 1 if (C = 1) then PC

← PC + k + 1 if (N = 1) then PC

← PC + k + 1 if (N = 0) then PC

← PC + k + 1 if (N

⊕ V= 0) then PC ← PC + k + 1 if (N

⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC

← PC + k + 1 if (H = 0) then PC

← PC + k + 1 if (T = 1) then PC

← PC + k + 1 if (T = 0) then PC

← PC + k + 1 if (V = 1) then PC

← PC + k + 1 if (V = 0) then PC

← PC + k + 1

#Clocks

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1

1

1 / 2 / 3

1 / 2 / 3

1 / 2 / 3

1 / 2 / 3

1 / 2

1 / 2

3

3

2

2

4

4

1 / 2 / 3

1

2

2

2

2

2

1

2

1

1

1

1

1

1

1

1

1

1

1

1

2

1

1

1

1

1

1

1

2

Flags

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

I

None

None

Z, N, V, C, H

Z, N, V, C, H

Z, N, V, C, H

None

None

None

None

None

None

None

Z, C

Z, C

Z, C

Z, C

Z, C

Z, C

Z, C, N, V

Z, C, N, V, H

Z, N, V

Z, N, V

Z, N, V

Z, N, V

Z, N, V

Z, N, V

Z, C, N, V, H

Z, C, N, V, H

Z, C, N, V, S

Z, C, N, V, H

Z, C, N, V, H

Z, C, N, V, H

Z, C, N ,V, H

Z, C, N, V, S

Z, N, V

Z, N, V

Z, N, V

Z, N, V

Z, N, V

10

Instruction Set Summary (Continued)

Mnemonics Operands

ST

ST

STD

ST

ST

ST

STD

STS

ST

ST

ST

ST

LD

LD

LDD

LDS

LD

LD

LD

LD

LD

LD

LDD

LD

BRIE

BRID

k

k

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr

MOVW

LDI

Rd, Rr

Rd, K

Rd, X

Rd, X+

Rd, - X

Rd, Y

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Z+, Rr

-Z, Rr

Z+q,Rr k, Rr

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

X, Rr

X+, Rr

- X, Rr

Y, Rr

CLI

SES

CLS

SEV

CLV

SET

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

LPM

LPM

LPM

SPM

IN

OUT

PUSH

POP

Rd, Z

Rd, Z+

Rd, P

P, Rr

Rr

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b

CBI

LSL

P,b

Rd

Rd

Rd

Rd

Rd

Rd s s

Rr, b

Rd, b

Description

Branch if Interrupt Enabled

Branch if Interrupt Disabled

Move Between Registers

Copy Register Word

Load Immediate

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

Out Port

Push Register on Stack

Pop Register from Stack

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

Bit Store from Register to T

Bit load from T to Register

Set Carry

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

2486ZS–AVR–02/11

ATmega8(L)

Operation

if ( I = 1) then PC

← PC + k + 1 if ( I = 0) then PC

← PC + k + 1

Rd

← Rr

Rd+1:Rd

← Rr+1:Rr

Rd

← K

Rd

← (X)

Rd

← (X), X ← X + 1

X

← X - 1, Rd ← (X)

Rd

← (Y)

Rd

← (Y), Y ← Y + 1

Y

← Y - 1, Rd ← (Y)

Rd

← (Y + q)

Rd

← (Z)

Rd

← (Z), Z ← Z+1

Z

← Z - 1, Rd ← (Z)

Rd

← (Z + q)

Rd

← (k)

(X)

← Rr

(X)

← Rr, X ← X + 1

X

← X - 1, (X) ← Rr

(Y)

← Rr

(Y)

← Rr, Y ← Y + 1

Y

← Y - 1, (Y) ← Rr

(Y + q)

← Rr

(Z)

← Rr

(Z)

← Rr, Z ← Z + 1

Z

← Z - 1, (Z) ← Rr

(Z + q)

← Rr

(k)

← Rr

R0

← (Z)

Rd

← (Z)

Rd

← (Z), Z ← Z+1

(Z)

← R1:R0

Rd

← P

P

← Rr

STACK

← Rr

Rd

← STACK

N

← 0

Z

← 1

Z

← 0

I

← 1

I

← 0

S

← 1

S

← 0

V

← 1

V

← 0

T

← 1

I/O(P,b)

← 1

I/O(P,b)

← 0

Rd(n+1)

← Rd(n), Rd(0) ← 0

Rd(n)

← Rd(n+1), Rd(7) ← 0

Rd(0)

←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)

←C,Rd(n)← Rd(n+1),C←Rd(0)

Rd(n)

← Rd(n+1), n=0..6

Rd(3..0)

←Rd(7..4),Rd(7..4)←Rd(3..0)

SREG(s)

← 1

SREG(s)

← 0

T

← Rr(b)

Rd(b)

← T

C

← 1

C

← 0

N

← 1

#Clocks

1 / 2

1 / 2

1

1

1

1

1

1

1

1

1

1

1

1

2

2

1

1

1

1

1

1

1

1

1

1

1

3

-

3

3

2

2

2

2

2

2

1

1

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

1

1

1

Flags

None

None

None

None

Z, C, N, V

Z, C, N, V

Z, C, N, V

Z, C, N, V

Z, C, N, V

None

SREG(s)

SREG(s)

T

C

N

None

C

S

V

I

S

V

T

I

Z

N

Z

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

11

Instruction Set Summary (Continued)

Mnemonics Operands

CLT

SEH

CLH

MCU CONTROL INSTRUCTIONS

NOP

SLEEP

Description

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

Sleep

ATmega8(L)

T

← 0

H

← 1

H

← 0

Operation

(see specific descr. for Sleep function)

Flags

T

H

H

None

None

#Clocks

1

1

1

1

1

2486ZS–AVR–02/11

12

ATmega8(L)

Ordering Information

Speed (MHz)

8

16

Power Supply (V)

2.7 - 5.5

4.5 - 5.5

Ordering Code

(2)

ATmega8L-8AU

ATmega8L-8AUR

(3)

ATmega8L-8PU

ATmega8L-8MU

ATmega8L-8MUR

(3)

ATmega8-16AU

ATmega8-16AUR

(3)

ATmega8-16PU

ATmega8-16MU

ATmega8-16MUR

(3)

Package

32A

32A

28P3

32M1-A

32M1-A

32A

32A

28P3

32M1-A

32M1-A

(1)

Operation Range

Industrial

(-40

°

C to 85

°

C)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green

3. Tape & Reel

32A

28P3

32M1-A

2486ZS–AVR–02/11

Package Type

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32-pad, 5 × 5 × 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

13

ATmega8(L)

Packaging Information

32A

PIN 1 IDENTIFIER e

PIN 1

D1

D

B

E1 E

C

0°~7°

A1

A2 A

L

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

A –

A1

A2

D

D1

0.05

0.95

8.75

6.90

E

E1

8.75

6.90

B 0.30

C

L

e

0.09

0.45

NOM

1.00

9.00

7.00

9.00

7.00

0.80 TYP

MAX NOTE

1.20

0.15

1.05

9.25

7.10 Note 2

9.25

7.10 Note 2

0.45

0.20

0.75

R

2325 Orchard Parkway

San Jose, CA 95131

TITLE

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

2010-10-20

DRAWING NO.

REV.

32A C

14

2486ZS–AVR–02/11

ATmega8(L)

28P3

D

PIN

1

E1

A

SEATING PLANE

L

A1

B2

(4 PLACES)

B1

B e

E

Note:

C

0º ~ 15º REF

1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

R

2325 Orchard Parkway

San Jose, CA 95131

TITLE

eB

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

A –

A1

D

E

0.508

34.544

7.620

E1

B

B1

B2

7.112

0.381

1.143

0.762

NOM

MAX

4.5724

– –

– 34.798 Note 1

8.255

7.493

0.533

1.397

1.143

L

C

3.175

0.203

3.429

0.356

eB – – 10.160

e 2.540 TYP

NOTE

Note 1

09/28/01

DRAWING NO.

REV.

28P3

B

15

2486ZS–AVR–02/11

ATmega8(L)

32M1-A

D

D1

1

2

3

Pin 1 ID

0

E1

E

SIDE VIEW

P

P

TOP VIEW

K

D2

Pin #1 Notch

(0.20 R) b

BOTTOM VIEW

e

1

2

3

E2

L

K

A2

A

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

A3

A1

0.08 C

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

A 0.80

A1 –

A2

A3

b

0.18

D

D1

D2

E

E1

E2

e

4.90

4.70

2.95

4.90

4.70

2.95

L

P

0

K

0.30

0.20

NOM

0.90

0.02

0.65

0.20 REF

0.23

5.00

4.75

3.10

5.00

4.75

3.10

0.50 BSC

0.40

MAX

1.00

0.05

1.00

0.50

0.60

12 o

0.30

5.10

4.80

3.25

5.10

4.80

3.25

NOTE

R

2325 Orchard Parkway

San Jose, CA 95131

TITLE

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

5/25/06

DRAWING NO.

REV.

32M1-A E

16

2486ZS–AVR–02/11

Errata

ATmega8

Rev. D to I, M

ATmega8(L)

The revision letter in this section refers to the revision of the ATmega8 device.

First Analog Comparator conversion may be delayed

Interrupts may be lost when writing the timer registers in the asynchronous timer

Signature may be Erased in Serial Programming Mode

CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32KHz Oscillator is

Used to Clock the Asynchronous Timer/Counter2

Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1.

First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V take longer than expected on some devices.

CC

, the first Analog Comparator conversion will

Problem Fix / Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion.

2.

Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronized to the asynchronous timer clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.

Problem Fix / Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor

0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous

Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).

3.

Signature may be Erased in Serial Programming Mode

If the signature bytes are read before a chiperase command is completed, the signature may be erased causing the device ID and calibration bytes to disappear. This is critical, especially, if the part is running on internal RC oscillator.

Problem Fix / Workaround:

Ensure that the chiperase command has exceeded before applying the next command.

4.

CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32KHz

Oscillator is Used to Clock the Asynchronous Timer/Counter2

When the internal RC Oscillator is used as the main clock source, it is possible to run the

Timer/Counter2 asynchronously by connecting a 32KHz Oscillator between XTAL1/TOSC1 and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and

XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and

XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed.

Problem Fix / Workaround

Use external capacitors in the range of 20pF - 36pF on XTAL1/TOSC1 and XTAL2/TOSC2.

This will be fixed in ATmega8 Rev. G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is selected as main clock source. For ATmega8 Rev. G,

CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Customers who want compatibility between Rev. G and older revisions, must ensure that

CKOPT is unprogrammed (CKOPT = 1).

17

2486ZS–AVR–02/11

ATmega8(L)

5.

Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

2486ZS–AVR–02/11

18

ATmega8(L)

Datasheet

Revision

History

Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.

Changes from Rev.

2486Y- 10/10 to

Rev. 2486Z- 02/11

1.

Updated the datasheet according to the Atmel new Brand Style Guide.

2.

Updated “Ordering Information” on page 13 . Added Ording Information for

“Tape&Reel” devices

Changes from Rev.

2486X- 06/10 to

Rev. 2486Y- 10/10

1.

Max Rise/Fall time in Table 102 on page 239 has been corrected from 1.6ns to 1600ns.

2.

Note is added to “Performing Page Erase by SPM” on page 209 .

3.

Updated/corrected several short-cuts and added some new ones.

4.

Updated last page according to new standard.

Changes from Rev.

2486W- 02/10 to

Rev. 2486X- 06/10

1.

Updated “DC Characteristics” on page 235 with new V

OL

0.6V).

maximum value (0.9V and

Changes from Rev.

2486V- 05/09 to

Rev. 2486W- 02/10

1.

Updated “ADC Characteristics” on page 241 with V

INT

maximum value (2.9V).

Changes from Rev.

2486U- 08/08 to

Rev. 2486V- 05/09

1.

Updated “Errata” on page 289 .

2.

Updated the last page with Atmel’s new adresses.

Changes from Rev.

2486T- 05/08 to

Rev. 2486U- 08/08

1.

Updated “DC Characteristics” on page 235 with

I

CC

typical values.

Changes from Rev.

2486S- 08/07 to

Rev. 2486T- 05/08

1.

Updated Table 98 on page 233 .

2.

Updated “Ordering Information” on page 285 .

- Commercial Ordering Code removed.

- No Pb-free packaging option removed.

19

2486ZS–AVR–02/11

ATmega8(L)

Changes from Rev.

2486R- 07/07 to

Rev. 2486S- 08/07

1.

Updated “Features” on page 1 .

2.

Added “Data Retention” on page 7 .

3.

Updated “Errata” on page 289 .

4.

Updated “Slave Mode” on page 125 .

Changes from Rev.

2486Q- 10/06 to

Rev. 2486R- 07/07

1.

Added text to Table 81 on page 211 .

2.

Fixed typo in “Peripheral Features” on page 1 .

3.

Updated Table 16 on page 42 .

4.

Updated Table 75 on page 199 .

5.

Removed redundancy and updated typo in Notes section of “DC Characteristics” on page 235 .

Changes from Rev.

2486P- 02/06 to

Rev. 2486Q- 10/06

1.

Updated “Timer/Counter Oscillator” on page 32 .

2.

Updated “Fast PWM Mode” on page 88 .

3.

Updated code example in “USART Initialization” on page 134 .

4.

Updated Table 37 on page 96 , Table 39 on page 97 , Table 42 on page 115 , Table 44 on page 115 , and Table 98 on page 233 .

5.

Updated “Errata” on page 289 .

Changes from Rev.

2486O-10/04 to

Rev. 2486P- 02/06

1.

Added “Resources” on page 7 .

2.

Updated “External Clock” on page 32 .

3.

Updated “Serial Peripheral Interface – SPI” on page 121 .

4.

Updated Code Example in “USART Initialization” on page 134 .

5.

Updated Note in “Bit Rate Generator Unit” on page 164 .

6.

Updated Table 98 on page 233 .

7.

Updated Note in Table 103 on page 241 .

8.

Updated “Errata” on page 289 .

Changes from Rev.

2486N-09/04 to

Rev. 2486O-10/04

1.

Removed to instances of “analog ground”. Replaced by “ground”.

2.

Updated Table 7 on page 29 , Table 15 on page 38 , and Table 100 on page 237 .

3.

Updated “Calibrated Internal RC Oscillator” on page 30 with the 1 MHz default value.

20

2486ZS–AVR–02/11

ATmega8(L)

4.

Table 89 on page 218 and Table 90 on page 218 moved to new section “Page Size” on page 218 .

5.

Updated descripton for bit 4 in “Store Program Memory Control Register – SPMCR” on page 206 .

6.

Updated “Ordering Information” on page 285 .

Changes from Rev.

2486M-12/03 to

Rev. 2486N-09/04

1.

Added note to MLF package in “Pin Configurations” on page 2 .

2.

Updated “Internal Voltage Reference Characteristics” on page 42 .

3.

Updated “DC Characteristics” on page 235 .

4.

ADC4 and ADC5 support 10-bit accuracy. Document updated to reflect this.

Updated features in “Analog-to-Digital Converter” on page 189 .

Updated “ADC Characteristics” on page 241 .

5.

Removed reference to “External RC Oscillator application note” from “External RC

Oscillator” on page 28 .

Changes from Rev.

2486L-10/03 to

Rev. 2486M-12/03

1.

Updated “Calibrated Internal RC Oscillator” on page 30 .

Changes from Rev.

2486K-08/03 to

Rev. 2486L-10/03

1.

Removed “Preliminary” and TBDs from the datasheet.

2.

Renamed ICP to ICP1 in the datasheet.

3.

Removed instructions CALL and JMP from the datasheet.

4.

Updated t

RST

in Table 15 on page 38 , V

BG

in Table 16 on page 42 , Table 100 on page

237 and Table 102 on page 239 .

5.

Replaced text “XTAL1 and XTAL2 should be left unconnected (NC)” after Table 9 in

“Calibrated Internal RC Oscillator” on page 30 . Added text regarding XTAL1/XTAL2 and CKOPT Fuse in “Timer/Counter Oscillator” on page 32 .

6.

Updated Watchdog Timer code examples in “Timed Sequences for Changing the

Configuration of the Watchdog Timer” on page 45 .

7.

Removed bit 4, ADHSM, from “Special Function IO Register – SFIOR” on page 58 .

8.

Added note 2 to Figure 103 on page 208 .

9.

Updated item 4 in the “Serial Programming Algorithm” on page 231 .

10. Added t

WD_FUSE

to Table 97 on page 232 and updated Read Calibration Byte, Byte 3, in

Table 98 on page 233 .

11. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics” on page 235 .

21

2486ZS–AVR–02/11

ATmega8(L)

Changes from Rev.

2486J-02/03 to

Rev. 2486K-08/03

1.

Updated V

BOT

values in Table 15 on page 38 .

2.

Updated “ADC Characteristics” on page 241 .

3.

Updated “ATmega8 Typical Characteristics” on page 242 .

4.

Updated “Errata” on page 289 .

Changes from Rev.

2486I-12/02 to Rev.

2486J-02/03

1.

Improved the description of “Asynchronous Timer Clock – clk

ASY

” on page 26 .

2.

Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz

Crystal Oscillator” application note, which do not exist.

3.

Corrected OCn waveforms in Figure 38 on page 89 .

4.

Various minor Timer 1 corrections.

5.

Various minor TWI corrections.

6.

Added note under “Filling the Temporary Buffer (Page Loading)” on page 209 about writing to the EEPROM during an SPM Page load.

7.

Removed ADHSM completely.

8.

Added section “EEPROM Write during Power-down Sleep Mode” on page 23 .

9.

Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of “Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/TOSC2” on page 5 .

10. Improved the table under “SPI Timing Characteristics” on page 239 and removed the table under “SPI Serial Programming Characteristics” on page 234 .

11. Corrected PC6 in “Alternate Functions of Port C” on page 61 .

12. Corrected PB6 and PB7 in “Alternate Functions of Port B” on page 58 .

13. Corrected 230.4 Mbps to 230.4 kbps under “Examples of Baud Rate Setting” on page

153 .

14. Added information about PWM symmetry for Timer 2 in “Phase Correct PWM Mode” on page 111 .

15. Added thick lines around accessible registers in Figure 76 on page 163 .

16. Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits under “Performing a Page Write” on page 209 .

17. Added note for RSTDISBL Fuse in Table 87 on page 216 .

18. Updated drawings in “Packaging Information” on page 286 .

22

2486ZS–AVR–02/11

ATmega8(L)

Changes from Rev.

2486H-09/02 to

Rev. 2486I-12/02

1.

Added errata for Rev D, E, and F on page 289 .

Changes from Rev.

2486G-09/02 to

Rev. 2486H-09/02

1.

Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

Changes from Rev.

2486F-07/02 to

Rev. 2486G-09/02

1.

Updated Table 103, “ADC Characteristics,” on page 241 .

Changes from Rev.

2486E-06/02 to

Rev. 2486F-07/02

1.

Changes in “Digital Input Enable and Sleep Modes” on page 55 .

2.

Addition of OCS2 in “MOSI/OC2 – Port B, Bit 3” on page 59 .

3.

The following tables have been updated:

Table 51, “CPOL and CPHA Functionality,” on page 127 , Table 59, “UCPOL Bit Settings,” on page 152 , Table 72, “Analog Comparator Multiplexed Input

(1)

,” on page 188 , Table 73,

“ADC Conversion Time,” on page 193 , Table 75, “Input Channel Selections,” on page 199 , and Table 84, “Explanation of Different Variables used in Figure 103 on page 208 and the

Mapping to the Z-pointer,” on page 214 .

4.

Changes in “Reading the Calibration Byte” on page 227 .

5.

Corrected Errors in Cross References.

Changes from Rev.

2486D-03/02 to

Rev. 2486E-06/02

1.

Updated Some Preliminary Test Limits and Characterization Data

The following tables have been updated:

Table 15, “Reset Characteristics,” on page 38 , Table 16, “Internal Voltage Reference Characteristics,” on page 42 , DC Characteristics on page 235 , Table , “ADC Characteristics,” on page 241 .

2.

Changes in External Clock Frequency

Added the description at the end of “External Clock” on page 32 .

Added period changing data in Table 99, “External Clock Drive,” on page 237 .

3.

Updated TWI Chapter

More details regarding use of the TWI bit rate prescaler and a Table 65, “TWI Bit Rate Prescaler,” on page 167 .

Changes from Rev.

2486C-03/02 to

Rev. 2486D-03/02

1.

Updated Typical Start-up Times.

The following tables has been updated:

Table 5, “Start-up Times for the Crystal Oscillator Clock Selection,” on page 28 , Table 6,

“Start-up Times for the Low-frequency Crystal Oscillator Clock Selection,” on page 28 ,

Table 8, “Start-up Times for the External RC Oscillator Clock Selection,” on page 29 , and

Table 12, “Start-up Times for the External Clock Selection,” on page 32 .

2.

Added “ATmega8 Typical Characteristics” on page 242 .

23

2486ZS–AVR–02/11

Changes from Rev.

2486B-12/01 to

Rev. 2486C-03/02

1.

Updated TWI Chapter.

More details regarding use of the TWI Power-down operation and using the TWI as Master with low TWBRR values are added into the datasheet.

Added the note at the end of the “Bit Rate Generator Unit” on page 164 .

Added the description at the end of “Address Match Unit” on page 164 .

2.

Updated Description of OSCCAL Calibration Byte.

In the datasheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections:

Improved description of “Oscillator Calibration Register – OSCCAL” on page 31 and “Calibration Byte” on page 218 .

3.

Added Some Preliminary Test Limits and Characterization Data.

Removed some of the TBD’s in the following tables and pages:

Table 3 on page 26 , Table 15 on page 38 , Table 16 on page 42 , Table 17 on page 44 , “T

A

=

-40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted)” on page 235 , Table 99 on page 237 , and Table 102 on page 239 .

4.

Updated Programming Figures.

Figure 104 on page 219 and Figure 112 on page 230 are updated to also reflect that AV

CC must be connected during Programming mode.

5.

Added a Description on how to Enter Parallel Programming Mode if RESET Pin is Disabled or if External Oscillators are Selected.

Added a note in section “Enter Programming Mode” on page 221 .

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2486ZS–AVR–02/11

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