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Phlips Semiconductors
80C51 Family
80C51 family hardware description
HARDWARE DESCRIPTION
This chapter provides a detailed description
of the 80C51 microcontroller (see Figure 1).
Included in this description are:
• The port drivers and how they function both
as ports and, for Ports 0 and 2, in bus
operations
• The Timers/Counters
• The Serial Interface
• The Interrupt System
• Reset
VCC
• The Reduced Power Modes in CMOS
devices
• The EPROM version of the 80C51
P0.0-P0.7
P2.0-P2.7
Port 0
Drivers
Port 2
Drivers
Port 0
Latch
Port 2
Latch
VSS
RAM Address
Register
RAM
EPROM/
ROM
Stack
Pointer
ACC
B
Register
TMP2
Program
Address
Register
TMP1
PCON
SCON
TMOD
TCON
T2CON
TH0
TL0
TH1
SBUF
IE
IP
Buffer
TL1
ALU
PC
Incrementer
Interrupt, Serial
Port, and Timer
Blocks
Program
Counter
PSW
PSEN
ALE
EA
Timing
and
Control
Instruction
Register
DPTR
RST
PD
Port 1 Latch
Port 3 Latch
Port 1
Drivers
Port 3
Drivers
Oscillator
XTAL1
XTAL2
P1.0-P1.7
P3.0-P3.7
SU00529
Figure 1. 80C51 Architecture
March 1995
1
Phlips Semiconductors
80C51 Family
80C51 family hardware description
Special Function Registers
A Map of the on-chip memory area called the
Special Function Register (SFR) space is
shown in Figure 2.
Note that in the SFRs not all of the addresses
are occupied. Unoccupied addresses are not
implemented on the chip. Read accesses to
these addresses will in general return random
data, and write accesses will have no effect.
User software should not write 1s to these
unimplemented locations, since they may be
used in other 80C51 Family derivative
products to invoke new features. The
functions of the SFRs are described in the
text that follows.
Accumulator
ACC is the Accumulator register. The
mnemonics for Accumulator-Specific
instructions, however, refer to the
Accumulator simply as A.
B Register
The B register is used during multiply and
divide operations. For other instructions it can
be treated as another scratch pad register.
Program Status Word
The PSW register contains program status
information as detailed in Figure 3.
PUSH and CALL executions. While the stack
may reside anywhere in on-chip RAM, the
Stack Pointer is initialized to 07H after a
reset. This causes the stack to begin at
locations 08H.
Data Pointer
The Data Pointer (DPTR) consists of a high
byte (DPH) and a low byte (DPL). Its
intended function is to hold a 16-bit address.
It may be manipulated as a 16-bit register or
as two independent 8-bit registers.
Ports 0 to 3
P0, P1, P2, and P3 are the SFR latches of
Ports 0, 1, 2, and 3, respectively. Writing a
one to a bit of a port SFR (P0, P1, P2, or P3)
causes the corresponding port output pin to
switch high. Writing a zero causes the port
output pin to switch low. When used as an
input, the external state of a port pin will be
held in the port SFR (i.e., if the external state
of a pin is low, the corresponding port SFR bit
will contain a 0; if it is high, the bit will contain
a 1).
Serial Data Buffer
The Serial Buffer is actually two separate
registers, a transmit buffer and a receive
buffer. When data is moved to SBUF, it goes
to the transmit buffer and is held for serial
transmission. (Moving a byte to SBUF is what
Stack Pointer
The Stack Pointer register is 8 bits wide. It is
incremented before data is stored during
initiates the transmission.) When data is
moved from SBUF, it comes from the receive
buffer.
Timer Registers Basic to 80C51
Register pairs (TH0, TL0), and (TH1, TL1)
are the 16-bit Counting registers for
Timer/Counters 0 and 1, respectively.
Control Register for the 80C51
Special Function Registers IP, IE, TMOD,
TCON, SCON, and PCON contain control
and status bits for the interrupt system, the
Timer/Counters, and the serial port. They are
described in later sections.
Port Structures and Operation
All four ports in the 80C51 are bidirectional.
Each consists of a latch (Special Function
Registers P0 through P3), an output driver,
and an input buffer.
The output drivers of Ports 0 and 2, and the
input buffers of Port 0, are used in accesses
to external memory. In this application, Port 0
outputs the low byte of the external memory
address, time-multiplexed with the byte being
written or read.
Port 2 outputs the high byte of the external
memory address when the address is 16 bits
wide. Otherwise, the Port 2 pins continue to
emit the P2 SFR content.
8 BYTES
F8
F0
FF
B
F7
E8
E0
EF
ACC
E7
D8
D0
DF
D7
PSW
C8
CF
C0
C7
B8
IP
BF
B0
P3
B7
A8
IE
AF
A0
P2
98
SCON
90
P1
88
TCON
TMOD
TL0
TL1
80
P0
SP
DPL
DPH
A7
9F
SBUF
97
TH0
8F
TH1
PCON
87
BIT ADDRESSABLE
SU00530
Figure 2. 80C51 SFR Memory Map
March 1995
2
Phlips Semiconductors
80C51 Family
80C51 family hardware description
MSB
LSB
CY
AC
BIT
PSW.7
PSW.6
PSW.5
PSW.4
SYMBOL
CY
AC
F0
RS1
PSW.3
RS0
PSW.2
PSW.1
PSW.0
OV
—
P
F0
RS1
RS
OV
—
P
FUNCTION
Carry flag.
Auxilliary Carry flag. (For BCD operations.)
Flag 0. (Available to the user for general purposes.)
Register bank select control bit 1.
Set/cleared by software to determine working register bank. (See Note.)
Register bank select control bit 0.
Set/cleared by software todetermine working register bank. (See Note.)
Overflow flag.
User-definable flag.
Parity flag.
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of “one” bits in the Accumulator, i.e., even parity.
NOTE: The contents of (RS1, RS0) enable the working register banks as follows:
(0,0)— Bank 0 (00H–07H)
(0,1)— Bank 1 (08H–0fH)
(1,0)— Bank 2 (10H–17H)
(1,1)— Bank 3 (18H–17H)
SU00531
Figure 3. Program Status Word (PSW) Register
All the Port 3 pins are multifunctional. They
are not only port pins, but also serve the
functions of various special features as listed
below:
CONTROL signal for use in external memory
accesses. During external memory accesses,
the P2 SFR remains unchanged, but the P0
SFR gets 1s written to it.
Port
Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
Also shown in Figure 4 is that if a P3 bit latch
contains a 1, then the output level is
controlled by the signal labeled “alternate
output function.” The actual P3.X pin level is
always available to the pin’s alternate input
function, if any.
Alternate Function
RxD (serial input port)
TxD (serial output port)
INT0 (external interrupt)
INT1 (external interrupt)
T0 (Timer/Counter 0 external input)
T1 (Timer/Counter 1 external input)
WR (external Data Memory write
strobe)
P3.7 RD (external Data Memory read strobe)
The alternate functions can only be activated
if the corresponding bit latch in the port SFR
contains a 1. Otherwise the port pin remains
at 0.
I/O Configurations
Figure 4 shows a functional diagram of a
typical bit latch and I/O buffer in each of the
four ports. The bit latch (one bit in the port’s
SFR) is represented as a Type D flip-flop,
which will clock in a value from the internal
bus in response to a “write to latch” signal
from the CPU. The level of the port pin itself
is placed on the internal bus in response to a
“read pin” signal from the CPU. Some
instructions that read a port activate the “read
latch” signal, and others activate the “read
pin” signal.
As shown in Figure 4, the output drivers of
Port 0 and 2 are switchable to an internal
ADDR and ADDR/DATA bus by an internal
March 1995
Ports 1, 2, and 3 have internal pullups, and
Port 0 has open drain outputs. Each I/O line
can be independently used as an input or an
output. (Port 0 and 2 may not be used as
general purpose I/O when being used as the
ADDR/DATA BUS for external memory during
normal operation.) To be used as an input,
the port bit latch must contain a 1, which
turns off the output driver FET. Then, for
Ports 1, 2, and 3, the pin is pulled high by a
weak internal pullup, and can be pulled low
by an external source.
Port 0 differs in that its internal pullups are
not active during normal port operation. The
pullup FET in the P0 output driver (see
Figure 4) is used only when the port is emitting
1s during external memory accesses.
Otherwise the pullup FET is off. Consequently
P0 lines that are being used as output port
lines are open drain. Writing a 1 to the bit
latch leaves both output FETs off, so the pin
floats. In that condition it can be used as a
high-impedance input.
Because Ports 1, 2, and 3 have fixed internal
pullups, they are sometimes called “quasi3
bidirectional” ports. When configured as
inputs they pull high and will source current
(IIL, in the data sheets) when externally
pulled low. Port 0, on the other hand, is
considered “true” bidirectional, because when
configured as an input it floats.
All the port latches in the 80C51 have 1s
written to them by the reset function. If a 0 is
subsequently written to a port latch, it can be
reconfigured as an input by writing a 1 to it.
Writing to a Port
In the execution of an instruction that
changes the value in a port latch, the new
value arrives at the latch during S6P2 of the
final cycle of the instruction. However, port
latches are in fact sampled by their output
buffers only during Phase 1 of an clock
period. (During Phase 2 the output buffer
holds the value it saw during the previous
Phase 1). Consequently, the new value in the
port latch won’t actually appear at the output
pin until the next Phase 1, which will be at
S1P1 of the next machine cycle.
If the change requires a 0-to-1 transition in
Port 1, 2, or 3, an additional pullup is turned
on during S1P1 and S1P2 of the cycle in
which the transition occurs. This is done to
increase the transition speed. The extra
pullup can source about 100 times the
current that the normal pullup can. It should
be noted that the internal pullups are
field-effect transistors, not linear resistors.
The pullup arrangements are shown in
Figure 5.
Phlips Semiconductors
80C51 Family
80C51 family hardware description
ADDR/Data
VCC
Control
Read
Latch
Read
Latch
VCC
Internal
Pullup*
P0.X
Pin
Int. Bus
D
Write to
Latch
CL
Q
P0.X
Latch
MUX
Q
Int. Bus
D
Write to
Latch
CL
Read
Pin
P1.X
Pin
Q
P1.X
Latch
Q
Read
Pin
a. Port 0 Bit
b. Port 1 Bit
Alternate
Output
Function
ADDR/Data
Control
Read
Latch
VCC
Read
Latch
Internal
Pullup*
Internal
Pullup*
MUX
Int. Bus
D
Write to
Latch
CL
Q
P2.X
Latch
VCC
P2.X
Pin
Q
Int. Bus
D
Write to
Latch
CL
Q
P3.X
Latch
Q
Read
Pin
Read
Pin
P3.X
Pin
Alternate
Input
Function
c. Port 2 Bit
d. Port 3 Bit
SU00532
*See Figure 5 for details of the internal pullup.
Figure 4. 80C51 Port Bit Latches and I/O Buffers
In the NMOS 8051 part, the fixed part of the
pullup is a depletion mode transistor with the
gate wired to the source. This transistor will
allow the pin to source about 0.25mA when
shorted to ground. In parallel with the fixed
pullup is an enhancement mode transistor,
which is activated during S1 whenever the
port bit does a 0-to-1 transition. During this
interval, if the port pin is shorted to ground,
this extra transistor will allow the pin to
source an additional 30mA.
In the CMOS 80C51, the pullup consists of
three pFETs. It should be noted that an
n-channel FET (nFET) is turned on when a
logical 1 is applied to its gate, and is turned
off when a logical 0 is applied to its gate. A
p-channel FET (pFET) is the opposite: it is on
when its gate sees a 0, and off when its gate
sees a 1.
March 1995
pFET1 in Figure 5 is the transistor that is
turned on for 2 oscillator periods after a
0-to-1 transition in the port latch. While it’s
on, it turns on pFET3 (a weak pullup),
through the inverter. This inverter and pFET3
form a latch which holds the 1.
Note that if the pin is emitting a 1, a negative
glitch on the pin from some external source
can turn off pFET3, causing the pin to go into
a float state. pFET2 is a very weak pullup
which is on whenever the nFET is off, in
traditional CMOS style. It’s only about 1/10
the strength of pFET1. Its function is to
restore a 1 to the pin in the event the pin had
a 1 and lost it to a glitch.
Port Loading and Interfacing
The output buffers of Ports 1, 2, and 3 can
each drive 4 LS TTL inputs. These ports on
4
NMOS versions can be driven in a normal
manner by a TTL or NMOS circuit. Both
NMOS and CMOS pins can be driven by
open-collector and open-drain outputs, but
note that 0-to-1 transitions will not be fast.
In the NMOS device, if the pin is driven by an
open-collector output, a 0-to-1 transition will
have to be driven by the relatively weak
depletion mode FET in Figure 5a. In the
CMOS device, an input 0 turns off pullup
pFET3, leaving only the very weak pullup
pFET2 to drive the transition.
Port 0 output buffers can each drive 8 LS TTL
inputs. They do, however, require external
pullups to drive NMOS inputs, except when
being used as the ADDRESS/DATA bus for
external memory.
Phlips Semiconductors
80C51 Family
80C51 family hardware description
VCC
2 Osc. Periods
Enhancement Mode FET
Depletion Mode FET
Port
Pin
Q
From Port
Latch
VSS
a. NMOS Configuration.
The enhancement mode transistor is turned on for 2 oscillator periods after Q makes a 0-to-1 transition.
VCC
VCC
P1
P2
VCC
2 Osc. Periods
P3
Port
Pin
n
Q
From Port
Latch
Input Data
Read Port Pin
b. CMOS Configuration.
pFET1 is turned on for 2 oscillator periods after Q makes a 0-to-1 transition.
During this time, pFET1 also turns on pFET3 through the inverter to form a latch which holds the 1. pFET2 is also on.
SU00533
Figure 5. Ports 1 and 3 NMOS and CMOS Internal Pullup Configurations
(Port 2 is similar except that it holds the strong pullup on while emitting 1s that are address bits. See Accessing External Memory.)
Read-Modify-Write Feature
Some instructions that read a port read the
latch and others read the pin. Which ones do
which? The instructions that read the latch
rather than the pin are the ones that read a
value, possibly change it, and then rewrite it
to the latch. These are called
“read-modify-write” instructions. The
instructions listed below are
read-modify-write instructions. When the
destination operand is a port, or a port bit,
these instructions read the latch rather than
the pin:
ANL
ORL
March 1995
(logical AND, e.g., ANL P1,A)
(logical OR, e.g., ORL P2,A)
XRL
JBC
byte, all 8 bits, modify the addressed bit, then
write the new byte back to the latch.
It is not obvious that the last three
instructions in this list are read-modify-write
instructions, but they are. They read the port
The reason that read-modify-write
instructions are directed to the latch rather
than the pin is to avoid a possible
misinterpretation of the voltage level at the
pin. For example, a port bit might be used to
drive the base of a transistor. When a 1 is
written to the bit, the transistor is turned on. If
the CPU then reads the same port bit at the
pin rather than the latch, it will read the base
voltage of the transistor and interpret it as a
0. Reading the latch rather than the pin will
return the correct value of 1.
(logical EX-OR, e.g., XRL P3,A)
(jump if bit = 1 and clear bit,
e.g., JBC P1.1,LABEL)
CPL
(complement bit, e.g., CPL P3.0)
INC
(increment, e.g., INC P2)
DEC
(decrement, e.g., DEC P2)
DJNZ
(decrement and jump if not
zero, e.g., DJNZ P3,LABEL)
MOV PX.Y,C (move carry bit to bit Y of Port X)
CLR PX.Y (clear bit Y of Port X)
SET PX.Y (set bit Y of Port X)
5
Phlips Semiconductors
80C51 Family
Accessing External Memory
Accesses to external memory are of two
types: accesses to external Program Memory
and accesses to external Data Memory.
Accesses to external Program Memory use
signal PSEN (program store enable) as the
read strobe. Accesses to external Data
Memory use RD or WR (alternate functions
of P3.7 and P3.6) to strobe the memory.
Fetches from external Program Memory
always use a 16-bit address. Accesses to
external Data Memory can use either a 16-bit
address (MOVX @ DPTR) or an 8-bit
address (MOVX @Ri).
Whenever a 16-bit address is used, the high
byte of the address comes out on Port 2,
where it is held for the duration of the read or
write cycle. Note that the Port 2 drivers use
the strong pullups during the entire time that
they are emitting address bits that are 1s.
This is during the execution of a MOVX
@DPTR instruction. During this time the Port
2 latch (the Special Function Register) does
not have to contain 1s, and the contents of
the Port 2 SFR are not modified. If the
external memory cycle is not immediately
followed by another external memory cycle,
the undisturbed contents of the Port 2 SFR
will reappear in the next cycle.
If an 8-bit address is being used (MOVX
@Ri), the contents of the Port 2 SFR remain
at the Port 2 pins throughout the external
memory cycle. This will facilitate paging.
In any case, the low byte of the address is
time-multiplexed with the data byte on Port 0.
The ADDR/DATA signals drive both FETs in
the Port 0 output buffers. Thus, in this
application the Port 0 pins are not open-drain
outputs, and do not require external pullups.
ALE (Address Latch Enable) should be used
to capture the address byte into an external
latch. The address byte is valid at the
negative transition of ALE. Then, in a write
cycle, the data byte to be written appears on
Port 0 just before WR is activated, and
remains there until after WR is deactivated. In
a read cycle, the incoming byte is accepted
at Port 0 just before the read strobe is
deactivated.
During any access to external memory, the
CPU writes 0FFH to the Port 0 latch (the
Special Function Register), thus obliterating
whatever information the Port 0 SFR may
have been holding.
External Program Memory is accessed under
two conditions: Whenever signal EA is active;
or whenever the program counter (PC)
contains a number that is larger than 0FFFH
(in the 80C51).
March 1995
80C51 family hardware description
This require that the ROMless versions have
EA wired low to enable the lower 4k program
bytes to be fetched from external memory.
When the CPU is executing out of external
Program Memory, all 8 bits of Port 2 are
dedicated to an output function and may not
be used for general purpose I/O. During
external program fetches they output the high
byte of the PC. During this time the Port 2
drivers use the strong pullups to emit PC bits
that are 1s.
Timer/Counters
The 80C51 has two 16-bit Timer/Counter
registers: Timer 0 and Timer 1. Both can be
configured to operate either as timers or
event counters (see Figure 6).
In the “Timer” function, the register is
incremented every machine cycle. Thus, one
can think of it as counting machine cycles.
Since a machine cycle consists of 12
oscillator periods, the count rate is 1/12 of the
oscillator frequency.
In the “Counter” function, the register is
incremented in response to a 1-to-0 transition
at its corresponding external input pin, T0 or
T1. In this function, the external input is
sampled during S5P2 of every machine
cycle.
When the samples show a high in one cycle
and a low in the next cycle, the count is
incremented. The new count value appears in
the register during S3P1 of the cycle
following the one in which the transition was
detected. Since it takes 2 machine cycles (24
oscillator periods) to recognize a 1-to-0
transition, the maximum count rate is 1/24 of
the oscillator frequency. There are no
restrictions on the duty cycle of the external
input signal, but to ensure that a given level is
sampled at least once before it changes, it
should be held for at least one full cycle. In
addition to the “Timer” or “Counter” selection,
Timer 0 and Timer 1 have four operating
modes from which to select.
Timer 0 and Timer 1
The “Timer” or “Counter” function is selected
by control bits C/T in the Special Function
Register TMOD. These two Timer/Counters
have four operating modes, which are
selected by bit-pairs (M1, M0) in TMOD.
Modes 0, 1, and 2 are the same for both
Timers/Counters. Mode 3 is different. The
four operating modes are described in the
following text.
Mode 0
Putting either Timer into Mode 0 makes it
look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler.
6
Figure 7 shows the Mode 0 operation as it
applies to Timer 1.
In this mode, the Timer register is configured
as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt
flag TF1. The counted input is enabled to the
Timer when TR1 = 1 and either GATE = 0 or
INT1 = 1. (Setting GATE = 1 allows the Timer
to be controlled by external input INT1, to
facilitate pulse width measurements). TR1 is
a control bit in the Special Function Register
TCON (Figure 8). GATE is in TMOD.
The 13-bit register consists of all 8 bits of
TH1 and the lower 5 bits of TL1. The upper 3
bits of TL1 are indeterminate and should be
ignored. Setting the run flag (TR1) does not
clear the registers.
Mode 0 operation is the same for the Timer 0
as for Timer 1. Substitute TR0, TF0, and
INT0 for the corresponding Timer 1 signals in
Figure 7. There are two different GATE bits,
one for Timer 1 (TMOD.7) and one for Timer
0 (TMOD.3).
Mode 1
Mode 1 is the same as Mode 0, except that
the Timer register is being run with all 16 bits.
Mode 2
Mode 2 configures the Timer register as an
8-bit Counter (TL1) with automatic reload, as
shown in Figure 9. Overflow from TL1 not
only sets TF1, but also reloads TL1 with the
contents of TH1, which is preset by software.
The reload leaves TH1 unchanged.
Mode 2 operation is the same for
Timer/Counter 0.
Mode 3
Timer 1 in Mode 3 simply holds its count. The
effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0
as two separate counters. The logic for Mode
3 on Timer 0 is shown in Figure 10. TL0 uses
the Timer 0 control bits: C/T, GATE, TR0,
INT0, and TF0. TH0 is locked into a timer
function (counting machine cycles) and takes
over the use of TR1 and TF1 from Timer 1.
Thus, TH0 now controls the “Timer 1”
interrupt.
Mode 3 is provided for applications requiring
an extra 8-bit timer on the counter. With
Timer 0 in Mode 3, an 80C51 can look like it
has three Timer/Counters. When Timer 0 is in
Mode 3, Timer 1 can be turned on and off by
switching it out of and into its own Mode 3, or
can still be used by the serial port as a baud
rate generator, or in fact, in any application
not requiring an interrupt.
Phlips Semiconductors
80C51 Family
80C51 family hardware description
MSB
GATE
LSB
C/T
M1
M0
GATE
TIMER 1
GATE
M0
0
1
0
1
1
1
1
M1
M0
TIMER 0
Gating control when set. Timer/Counter “x” is enabled only while “INTx” pin is high and
“TRx” control pin is set. when cleared Timer “x” is enabled whenever “TRx” control bit is set.
Timer or Counter Selector cleared for Timer operation (input from in=ternal system clock.)
Set for Counter operation (input from “Tx” input pin).
C/T
M1
0
0
1
C/T
OPERATING
8048 Timer “TLx” serves as 5-bit prescaler.
16-bit Timer/Counter “THx” and “TLx” are cascaded; there is no prescaler.
8-bit auto-reload Timer/Counter “THx” holds a value which is to be reloaded
into “TLx” each time it overflows.
(Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
(Timer 1) Timer/Counter 1 stopped.
SU00534
Figure 6. Timer/Counter Mode Control (TMOD) Register
÷12
Osc.
C/T = 0
TL1
(5 Bits)
TH1
(8 Bits)
TF1
Interrupt
C/T = 1
Control
T1 Pin
TR1
Gate
INT1 Pin
SU00535
Figure 7. Timer/Counter Mode 0: 13-Bit Counter
MSB
TF1
BIT
TCON.7
SYMBOL
TF1
TCON.6
TCON.5
TR1
TF0
TCON.4
TCON.3
TR0
IE1
TCON.2
IT1
TCON.1
IE0
TCON.0
IT0
LSB
TR1
TF0
TR0
IE1
IT1
IE0
IT0
FUNCTION
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software.
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software.
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level
triggered external interrupts.
SU00536
Figure 8. Timer/Counter Control (TCON) Register
March 1995
7
Phlips Semiconductors
80C51 Family
80C51 family hardware description
÷12
Osc.
C/T = 0
TL1
(8 Bits)
TF1
Interrupt
C/T = 1
Control
T1 Pin
Reload
TR1
Gate
TH1
(8 Bits)
INT1 Pin
SU00537
Figure 9. Timer/Counter Mode 2: 8-Bit Auto-Load
÷12
Osc.
1/12 fOSC
1/12 fOSC
C/T = 0
TL0
(8 Bits)
TF0
Interrupt
TH0
(8 Bits)
TF1
Interrupt
C/T = 1
T0 Pin
Control
TR0
Gate
INT0 Pin
1/12 fOSC
Control
TR1
SU00538
Figure 10. Timer/Counter 0 Mode 3: Two 8-Bit Counters
March 1995
8
Phlips Semiconductors
80C51 Family
Standard Serial Interface
The serial port is full duplex, meaning it can
transmit and receive simultaneously. It is also
receive-buffered, meaning it can commence
reception of a second byte before a
previously received byte has been read from
the register. (However, if the first byte still
hasn’t been read by the time reception of the
second byte is complete, one of the bytes will
be lost.) The serial port receive and transmit
registers are both accessed at Special
Function Register SBUF. Writing to SBUF
loads the transmit register, and reading SBUF
accesses a physically separate receive
register.
The serial port can operate in 4 modes:
Mode 0: Serial data enters and exits
through RxD. TxD outputs the shift clock. 8
bits are transmitted/received (LSB first). The
baud rate is fixed at 1/12 the oscillator
frequency.
Mode 1: 10 bits are transmitted (through
TxD) or received (through RxD): a start bit
(0), 8 data bits (LSB first), and a stop bit (1).
On receive, the stop bit goes into RB8 in
Special Function Register SCON. The baud
rate is variable.
Mode 2: 11 bits are transmitted (through
TxD) or received (through RxD): start bit (0),
8 data bits (LSB first), a programmable 9th
data bit, and a stop bit (1). On Transmit, the
9th data bit (TB8 in SCON) can be assigned
the value of 0 or 1. Or, for example, the parity
bit (P, in the PSW) could be moved into TB8.
On receive, the 9th data bit goes into RB8 in
Special Function Register SCON, while the
stop bit is ignored. The baud rate is
programmable to either 1/32 or 1/64 the
oscillator frequency.
Mode 3: 11 bits are transmitted (through
TxD) or received (through RxD): a start bit
(0), 8 data bits (LSB first), a programmable
9th data bit, and a stop bit (1). In fact, Mode 3
is the same as Mode 2 in all respects except
baud rate. The baud rate in Mode 3 is
variable.
March 1995
80C51 family hardware description
In all four modes, transmission is initiated by
any instruction that uses SBUF as a
destination register. Reception is initiated in
Mode 0 by the condition RI = 0 and REN = 1.
Reception is initiated in the other modes by
the incoming start bit if REN = 1.
Multiprocessor Communications
Modes 2 and 3 have a special provision for
multiprocessor communications. In these
modes, 9 data bits are received. The 9th one
goes into RB8. Then comes a stop bit. The
port can be programmed such that when the
stop bit is received, the serial port interrupt
will be activated only if RB8 = 1. This feature
is enabled by setting bit SM2 in SCON. A
way to use this feature in multiprocessor
systems is as follows:
When the master processor wants to transmit
a block of data to one of several slaves, it
first sends out an address byte which
identifies the target slave. An address byte
differs from a data byte in that the 9th bit is 1
in an address byte and 0 in a data byte. With
SM2 = 1, no slave will be interrupted by a
data byte. An address byte, however, will
interrupt all slaves, so that each slave can
examine the received byte and see if it is
being addressed. The addressed slave will
clear its SM2 bit and prepare to receive the
data bytes that will be coming. The slaves
that weren’t being addressed leave their
SM2s set and go on about their business,
ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1
can be used to check the validity of the stop
bit. In a Mode 1 reception, if SM2 = 1, the
receive interrupt will not be activated unless a
valid stop bit is received.
Serial Port Control Register
The serial port control and status register is
the Special Function Register SCON, shown
in Figure 11. This register contains not only
the mode selection bits, but also the 9th data
bit for transmit and receive (TB8 and RB8),
and the serial port interrupt bits (TI and RI).
9
Baud Rates
The baud rate in Mode 0 is fixed: Mode 0
Baud Rate = Oscillator Frequency / 12. The
baud rate in Mode 2 depends on the value of
bit SMOD in Special Function Register
PCON. If SMOD = 0 (which is the value on
reset), the baud rate is 1/64 the oscillator
frequency. If SMOD = 1, the baud rate is 1/32
the oscillator frequency.
Mode 2 Baud Rate =
2 SMOD (Oscillator Frequency)
64
In the 80C51, the baud rates in Modes 1 and
3 are determined by the Timer 1 overflow
rate.
Using Timer 1 to Generate Baud Rates
When Timer 1 is used as the baud rate
generator, the baud rates in Modes 1 and 3
are determined by the Timer 1 overflow rate
and the value of SMOD as follows:
Mode 1, 3 Baud Rate =
2 SMOD (Timer 1 Overflow Rate)
32
The Timer 1 interrupt should be disabled in
this application. The Timer itself can be
configured for either “timer” or “counter”
operation, and in any of its 3 running modes.
In the most typical applications, it is
configured for “timer” operation, in the
auto-reload mode (high nibble of TMOD =
0010B). In that case the baud rate is given by
the formula:
Mode 1, 3 Baud Rate =
2 SMOD Oscillator Frequency
32
12 [256 (TH1)]
One can achieve very low baud rates with
Timer 1 by leaving the Timer 1 interrupt
enabled, and configuring the Timer to run as
a 16-bit timer (high nibble of TMOD =
0001B), and using the Timer 1 interrupt to do
a 16-bit software reload. Figure 12 lists
various commonly used baud rates and how
they can be obtained from Timer 1.
Phlips Semiconductors
80C51 Family
80C51 family hardware description
MSB
SM0
LSB
SM1
SM2
REN
TB8
RB8
TI
RI
Where SM0, SM1 specify the serial port mode, as follows:
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
fosc/ 12
variable
fosc/64 or fosc/32
variable
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be
activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not
received. In Mode 0, SM2 should be 0.
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0,
RB8 is not used.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other
modes, in any serial transmission. Must be cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other
modes, in any serial reception (except see SM2). Must be cleared by software.
SU00120
Figure 11. Serial Port Control (SCON) Register
Timer 1
Baud Rate
Mode 0 Max: 1.67MHz
Mode 2 Max: 625k
Mode 1, 3 Max: 104.2k
19.2k
9.6k
4.8k
2.4k
1.2k
137.5
110
110
fOSC
SMOD
20MHz
20MHz
20MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.986MHz
6MHz
12MHz
X
1
1
1
0
0
0
0
0
0
0
C/T
Mode
Reload Value
X
X
0
0
0
0
0
0
0
0
0
X
X
2
2
2
2
2
2
2
2
1
X
X
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72H
FEEBH
Figure 12. Timer 1 Generated Commonly Used Baud Rates
More About Mode 0
Serial data enters and exits through RxD.
TxD outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first).
The baud rate is fixed a 1/12 the oscillator
frequency.
Figure 13 shows a simplified functional
diagram of the serial port in Mode 0, and
associated timing.
Transmission is initiated by any instruction
that uses SBUF as a destination register. The
“write to SBUF” signal at S6P2 also loads a 1
into the 9th position of the transmit shift
register and tells the TX Control block to
commence a transmission. The internal
timing is such that one full machine cycle will
March 1995
elapse between “write to SBUF” and
activation of SEND.
SEND enables the output of the shift register
to the alternate output function line of P3.0
and also enable SHIFT CLOCK to the
alternate output function line of P3.1. SHIFT
CLOCK is low during S3, S4, and S5 of every
machine cycle, and high during S6, S1, and
S2. At S6P2 of every machine cycle in which
SEND is active, the contents of the transmit
shift are shifted to the right one position.
As data bits shift out to the right, zeros come
in from the left. When the MSB of the data
byte is at the output position of the shift
register, then the 1 that was initially loaded
into the 9th position, is just to the left of the
10
MSB, and all positions to the left of that
contain zeros. This condition flags the TX
Control block to do one last shift and then
deactivate SEND and set T1. Both of these
actions occur at S1P1 of the 10th machine
cycle after “write to SBUF.”
Reception is initiated by the condition
REN = 1 and R1 = 0. At S6P2 of the next
machine cycle, the RX Control unit writes the
bits 11111110 to the receive shift register, and
in the next clock phase activates RECEIVE.
RECEIVE enable SHIFT CLOCK to the
alternate output function line of P3.1. SHIFT
CLOCK makes transitions at S3P1 and S6P1
of every machine cycle. At S6P2 of every
machine cycle in which RECEIVE is active,
Phlips Semiconductors
80C51 Family
the contents of the receive shift register are
shifted to the left one position. The value that
comes in from the right is the value that was
sampled at the P3.0 pin at S5P2 of the same
machine cycle.
As data bits come in from the right, 1s shift
out to the left. When the 0 that was initially
loaded into the rightmost position arrives at
the leftmost position in the shift register, it
flags the RX Control block to do one last shift
and load SBUF. At S1P1 of the 10th machine
cycle after the write to SCON that cleared RI,
RECEIVE is cleared as RI is set.
More About Mode 1
Ten bits are transmitted (through TxD), or
received (through RxD): a start bit (0), 8 data
bits (LSB first), and a stop bit (1). On receive,
the stop bit goes into RB8 in SCON. In the
80C51 the baud rate is determined by the
Timer 1 overflow rate.
Figure 14 shows a simplified functional
diagram of the serial port in Mode 1, and
associated timings for transmit receive.
Transmission is initiated by any instruction
that uses SBUF as a destination register. The
“write to SBUF” signal also loads a 1 into the
9th bit position of the transmit shift register
and flags the TX Control unit that a
transmission is requested. Transmission
actually commences at S1P1 of the machine
cycle following the next rollover in the
divide-by-16 counter. (Thus, the bit times are
synchronized to the divide-by-16 counter, not
to the “write to SBUF” signal.)
The transmission begins with activation of
SEND which puts the start bit at TxD. One bit
time later, DATA is activated, which enables
the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time
after that.
As data bits shift out to the right, zeros are
clocked in from the left. When the MSB of the
data byte is at the output position of the shift
register, then the 1 that was initially loaded
into the 9th position is just to the left of the
MSB, and all positions to the left of that
contain zeros. This condition flags the TX
Control unit to do one last shift and then
deactivfate SEND and set TI. This occurs at
the 10th divide-by-16 rollover after “write to
SBUF.”
Reception is initiated by a detected 1-to-0
transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud
rate has been established. When a transition
is detected, the divide-by-16 counter is
immediately reset, and 1FFH is written into
the input shift register. Resetting the
divide-by-16 counter aligns its rollovers with
the boundaries of the incoming bit times.
March 1995
80C51 family hardware description
The 16 states of the counter divide each bit
time into 16ths. At the 7th, 8th, and 9th
counter states of each bit time, the bit
detector samples the value of RxD. The
value accepted is the value that was seen in
at least 2 of the 3 samples. This is done for
noise rejection. If the value accepted during
the first bit time is not 0, the receive circuits
are reset and the unit goes back to looking
for another 1-to-0 transition. This is to provide
rejection of false start bits. If the start bit
proves valid, it is shifted into the input shift
register, and reception of the rest of the frame
will proceed.
As data bits come in from the right, 1s shift
out to the left. When the start bit arrives at the
leftmost position in the shift register (which in
mode 1 is a 9-bit register), it flags the RX
Control block to do one last shift, load SBUF
and RB8, and set RI. The signal to load
SBUF and RB8, and to set RI, will be
generated if, and only if, the following
conditions are met at the time the final shift
pulse is generated.:
1. R1 = 0, and
2. Either SM2 = 0,
or the received stop bit = 1.
If either of these two conditions is not met,
the received frame is irretrievably lost. If both
conditions are met, the stop bit goes into
RB8, the 8 data bits go into SBUF, and RI is
activated. At this time, whether the above
conditions are met or not, the unit goes back
to looking for a 1-to-0 transition in RxD.
More About Modes 2 and 3
Eleven bits are transmitted (through TxD), or
received (through RxD): a start bit (0), 8 data
bits (LSB first), a programmable 9th data bit,
and a stop bit (1). On transmit, the 9th data
bit (TB8) can be assigned the value of 0 or 1.
On receive, the 9the data bit goes into RB8 in
SCON. The baud rate is programmable to
either 1/32 or 1/64 the oscillator frequency in
Mode 2. Mode 3 may have a variable baud
rate generated from Timer 1.
synchronized to the divide-by-16 counter, not
to the “write to SBUF” signal.)
The transmission begins with activation of
SEND, which puts the start bit at TxD. One
bit time later, DATA is activated, which
enables the output bit of the transmit shift
register to TxD. The first shift pulse occurs
one bit time after that. The first shift clocks a
1 (the stop bit) into the 9th bit position of the
shift register. Thereafter, only zeros are
clocked in. Thus, as data bits shift out to the
right, zeros are clocked in from the left. When
TB8 is at the output position of the shift
register, then the stop bit is just to the left of
TB8, and all positions to the left of that
contain zeros. This condition flags the TX
Control unit to do one last shift and then
deactivate SEND and set TI. This occurs at
the 11th divide-by-16 rollover after “write to
SUBF.”
Reception is initiated by a detected 1-to-0
transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud
rate has been established. When a transition
is detected, the divide-by-16 counter is
immediately reset, and 1FFH is written to the
input shift register.
At the 7th, 8th, and 9th counter states of each
bit time, the bit detector samples the value of
R-D. The value accepted is the value that
was seen in at least 2 of the 3 samples. If the
value accepted during the first bit time is not
0, the receive circuits are reset and the unit
goes back to looking for another 1-to-0
transition. If the start bit proves valid, it is
shifted into the input shift register, and
reception of the rest of the frame will
proceed.
As data bits come in from the right, 1s shift
out to the left. When the start bit arrives at the
leftmost position in the shift register (which in
Modes 2 and 3 is a 9-bit register), it flags the
RX Control block to do one last shift, load
SBUF and RB8, and set RI.
Figures 15 and 16 show a functional diagram
of the serial port in Modes 2 and 3. The
receive portion is exactly the same as in
Mode 1. The transmit portion differs from
Mode 1 only in the 9th bit of the transmit shift
register.
The signal to load SBUF and RB8, and to set
RI, will be generated if, and only if, the
following conditions are met at the time the
final shift pulse is generated.
1. RI = 0, and
2. Either SM2 = 0,
or the received 9th data bit = 1.
Transmission is initiated by any instruction
that uses SBUF as a destination register. The
“write to SBUF” signal also loads TB8 into the
9th bit position of the transmit shift register
and flags the TX Control unit that a
transmission is requested. Transmission
commences at S1P1 of the machine cycle
following the next rollover in the divide-by-16
counter. (Thus, the bit times are
If either of these conditions is not met, the
received frame is irretrievably lost, and RI is
not set. If both conditions are met, the
received 9th data bit goes into RB8, and the
first 8 data bits go into SBUF. One bit time
later, whether the above conditions were met
or not, the unit goes back to looking for a
1-to-0 transition at the RxD input.
11
Phlips Semiconductors
80C51 Family
80C51 family hardware description
80C51 Internal Bus
Write
to
SBUF
S
D
Q
RxD
P3.0 Alt
Output
Function
SBUF
CL
Zero Detector
Start
Shift
TX Control
S6
TX Clock
Send
T1
Serial
Port
Interrupt
R1
RX Clock
Receive
RX Control
REN
RI
Start
1
1
1
TxD
P3.1 Alt
Output
Function
Shift
Clock
Shift
1
1
1
1
0
RxD
P3.0 Alt
Input
Function
Input Shift Register
Shift
Load
SBUF
SBUF
Read
SBUF
80C51 Internal Bus
S4 . .
S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1
ALE
Write to SBUF
S6P2
Send
Shift
Transmit
RxD (Data Out)
D0
D1
D2
D3
D4
D5
D6
D7
TxD (Shift Clock)
S3P1
TI
S6P1
Write to SCON (Clear RI)
RI
Receive
Shift
RxD (Data In)
Receive
D0
D1
D2
D3
D4
D5
D6
D7
S5P2
TxD (Shift Clock)
SU00539
Figure 13. Serial Port Mode 0
March 1995
12
Phlips Semiconductors
80C51 Family
80C51 family hardware description
Timer 1
Overflow
80C51 Internal Bus
TB8
÷2
SMOD = 0
SMOD = 1
Write
to
SBUF
S
D
Q
SBUF
TxD
CL
Zero Detector
Start
Data
Shift
TX Control
÷ 16
TX Clock
T1
Send
RX Clock RI
Load
SBUF
Serial
Port
Interrupt
÷ 16
Sample
RX Control
1-to-0
Transition
Detector
Shift
Start
1FFH
Bit Detector
Input Shift Register
(9 Bits)
Shift
RxD
Load
SBUF
SBUF
Read
SBUF
80C51 Internal Bus
TX
Clock
Write to SBUF
Send
Data
S1P1
Transmit
Shift
TxD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop Bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop Bit
TI
÷ 16 Reset
RX
Clock
RxD
Bit Detector
Sample Times
Start
Bit
Receive
Shift
RI
SU00540
Figure 14. Serial Port Mode 1
March 1995
13
Phlips Semiconductors
80C51 Family
80C51 family hardware description
80C51 Internal Bus
TB8
Write
to
SBUF
S
D
Q
SBUF
TxD
CL
Phase 2 Clock
(1/2 fOSC)
Zero Detector
Mode 2
Start
÷ 16
SMOD = 1
Stop Bit
Gen.
TX Control
TX Clock
Shift
Data
T1
Send
R1
Load
SBUF
Serial
Port
Interrupt
÷2
SMOD = 0
(SMOD is
PCON.7)
÷ 16
RX Clock
Sample
RX Control
1-to-0
Transition
Detector
Shift
Start
1FFH
Bit Detector
Input Shift Register
(9 Bits)
Shift
RxD
Load
SBUF
SBUF
Read
SBUF
80C51 Internal Bus
TX
Clock
Write to SBUF
Send
Data
S1P1
Transmit
Shift
TxD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
TB8
D0
D1
D2
D3
D4
D5
D6
D7
RB8
Stop Bit
TI
Stop Bit Gen.
÷ 16 Reset
RX
Clock
RxD
Bit Detector
Sample Times
Start
Bit
Stop Bit
Receive
Shift
RI
SU00541
Figure 15. Serial Port Mode 2
March 1995
14
Phlips Semiconductors
80C51 Family
80C51 family hardware description
Timer 1
Overflow
80C51 Internal Bus
TB8
Write
to
SBUF
÷2
SMOD = 0
SMOD = 1
S
D
Q
SBUF
TxD
CL
Zero Detector
Start
Data
Shift
TX Control
÷ 16
TX Clock
T1
Send
R1
Load
SBUF
Serial
Port
Interrupt
÷ 16
RX Clock
Sample
RX Control
1-to-0
Transition
Detector
Shift
Start
1FFH
Bit Detector
Input Shift Register
(9 Bits)
Shift
RxD
Load
SBUF
SBUF
Read
SBUF
80C51 Internal Bus
TX
Clock
Write to SBUF
Send
Data
S1P1
Transmit
Shift
TxD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
TB8
D0
D1
D2
D3
D4
D5
D6
D7
RB8
Stop Bit
TI
Stop Bit Gen.
RX
Clock
RxD
Bit Detector
Sample Times
÷ 16 Reset
Start
Bit
Stop Bit
Receive
Shift
RI
SU00542
Figure 16. Serial Port Mode 3
March 1995
15
Phlips Semiconductors
80C51 Family
80C51 family hardware description
0
INT0
IT0
IE0
1
TF0
0
IE1
IT1
INT1
Interrupt
Sources
1
TF1
TI
RI
SU00543
Figure 17. 80C51 Interrupt Sources
Interrupts
The 80C51 provides 5 interrupt sources.
These are shown in Figure 17. The External
Interrupts INT0 and INT1 can each be either
level-activated or transition-activated,
depending on bits IT0 and IT1 in Register
TCON. The flags that actually generate these
interrupts are bits IE0 and IE1 in TCON.
When an external interrupt is generated, the
flag that generated it is cleared by the
hardware when the service routine is
vectored to only if the interrupt was
transition-activated. If the interrupt was
level-activated, then the external requesting
source is what controls the request flag,
rather than the on-chip hardware.
The Timer 0 and Timer 1 Interrupts are
generated by TF0 and TF1, which are set by
a rollover in their respective Timer/Counter
registers (except see Timer 0 in Mode 3).
When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip
hardware when the service routine is
vectored to.
The Serial Port Interrupt is generated by the
logical OR of RI and TI. Neither of these flags
is cleared by hardware when the service
routine is vectored to. In fact, the service
routine will normally have to determine
whether it was RI or TI that generated the
interrupt, and the bit will have to be cleared in
software.
All of the bits that generate interrupts can be
set or cleared by software, with the same
result as though it had been set or cleared by
hardware. That is, interrupts can be
generated or pending interrupts can be
canceled in software.
March 1995
Each of these interrupt sources can be
individually enabled or disabled by setting or
clearing a bit in Special Function Register IE
(Figure 18). IE also contains a global disable
bit, EA, which disables all interrupts at once.
Priority Level Structure
Each interrupt source can also be individually
programmed to one of two priority levels by
setting or clearing a bit in Special Function
Register IP (Figure 19). A low-priority
interrupt can itself be interrupted by a
high-priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt
can’t be interrupted by any other interrupt
source.
If two request of different priority levels are
received simultaneously, the request of
higher priority level is serviced. If requests of
the same priority level are received
simultaneously, an internal polling sequence
determines which request is serviced. Thus
within each priority level there is a second
priority structure determined by the polling
sequence as follows:
Source
1. IE0
2. TF0
3. IE1
4. TF1
5. RI+TI
Priority Within Level
(highest)
(lowest)
Note that the “priority within level” structure is
only used to resolve simultaneous requests
of the same priority level.
The IP register contains a number of
unimplemented bits. IP.7, IP.6, and IP.5 are
reserved in the 80C51. User software should
not write 1s to these positions, since they
may be used in other 8051 Family products.
16
How Interrupts Are Handled
The interrupt flags are sampled at S5P2 of
every machine cycle. The samples are polled
during the following machine cycle. If one of
the flags was in a set condition at S5P2 of the
preceding cycle, the polling cycle will find it
and the interrupt system will generate an
LCALL to the appropriate service routine,
provided this hardware-generated LCALL is
not blocked by any of the following
conditions:
1. An interrupt of equal or higher priority
level is already in progress.
2. The current (polling) cycle is not the final
cycle in the execution of the instruction in
progress.
3. The instruction in progress is RETI or any
write to the IE or IP registers.
Any of these three conditions will block the
generation of the LCALL to the interrupt
service routine. Condition 2 ensures that the
instruction in progress will be completed
before vectoring to any service routine.
Condition 3 ensures that if the instruction in
progress is RETI or any access to IE or IP,
then at least one more instruction will be
executed before any interrupt is vectored to.
The polling cycle is repeated with each
machine cycle, and the values polled are the
values that were present at S5P2 of the
previous machine cycle. Note that if an
interrupt flag is active but not being
responded to for one of the above conditions,
if the flag is not still active when the blocking
condition is removed, the denied interrupt will
not be serviced. In other words, the fact that
the interrupt flag was once active but not
serviced is not remembered. Every polling
cycle is new.
Phlips Semiconductors
80C51 Family
80C51 family hardware description
MSB
LSB
EA
BIT
IE.7
SYMBOL
EA
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
—
ES
ET1
EX1
ET0
EX0
X
X
ES
ET1
EX1
ET0
EX0
FUNCTION
Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
Reserved.
Reserved.
Enables or disables the Serial Port interrupt. If ES=0, the Serial Port interrupt is disabled.
Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled.
Enables or disables External Interrupt 1. If EX1=0, External interrupt 1 is disabled.
Enables or disables the Timer 0 Overflow interrupt. If ET0=0, the Timer 0 interrupt is disabled.
Enables or disables External interrupt 0. If EX0=0, External interrupt 0 is disabled.
SU00544
Figure 18. Interrupt Enable Register (IE)
MSB
LSB
X
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL
—
—
—
PS
PT1
PX1
PT0
PX0
X
X
PS
PT1
PX1
PT0
PX0
FUNCTION
Reserved.
Reserved.
Reserved.
Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level.
Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level.
Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level.
Enables or disables the Timer 0 interrupt priority level. PT0=1 programs it to the higher priority level.
Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level.
SU00545
Figure 19. Interrupt Priority Register (IP)
.........
C1
S5P2
C2
C3
C4
C5
....
S6
.........
....
....
ε
Interrupt
Goes
Active
Interrupts
Are Polled
Long Call to
Interrupt
Vector Address
Interrupt Routine
Interrupt
Latched
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.
SU00546
Figure 20. Interrupt Response Timing Diagram
The polling cycle/LCALL sequence is
illustrated in Figure 20.
instruction of the lower priority routine having
been executed.
Note that if an interrupt of higher priority level
goes active prior to S5P2 of the machine
cycle labeled C3 in Figure 20, then in
accordance with the above rules it will be
vectored to during C5 and C6, without any
Thus the processor acknowledges an
interrupt request by executing a
hardware-generated LCALL to the
appropriate servicing routine. In some cases
it also clears the flag that generated the
March 1995
17
interrupt, and in other cases it doesn’t. It
never clears the Serial Port flag. This has to
be done in the user’s software. It clears an
external interrupt flag (IE0 or IE1) only if it
was transition-activated. The
hardware-generated LCALL pushes the
contents of the Program Counter on to the
Phlips Semiconductors
80C51 Family
stack (but it does not save the PSW) and
reloads the PC with an address that depends
on the source of the interrupt being vectored
to, as shown below:
Source
IE0
TF0
IE1
TF1
RI+TI
Vector Address
0003H
000BH
0013H
001BH
0023H
Execution proceeds from that location until
the RETI instruction is encountered. The
RETI instruction informs the processor that
this interrupt routine is no longer in progress,
then pops the top two bytes from the stack
and reloads the Program Counter. Execution
of the interrupted program continues from
where it left off.
Note that a simple RET instruction would also
have returned execution to the interrupted
program, but it would have left the interrupt
control system thinking an interrupt was still
in progress, making future interrupts
impossible.
External Interrupts
The external sources can be programmed to
be level-activated or transition-activated by
setting or clearing bit IT1 or IT0 in Register
TCON. If ITx = 0, external interrupt x is
triggered by a detected low at the INTx pin. If
ITx = 1, external interrupt x is edge triggered.
In this mode if successive samples of the
INTx pin show a high in one cycle and a low
in the next cycle, interrupt request flag IEx in
TCON is set. Flag bit IEx then requests the
interrupt.
Since the external interrupt pins are sampled
once each machine cycle, an input high or
low should hold for at least 12 oscillator
periods to ensure sampling. If the external
interrupt is transition-activated, the external
source has to hold the request pin high for at
least one cycle, and then hold it low for at
least one cycle. This is done to ensure that
the transition is seen so that interrupt request
flag IEx will be set. IEx will be automatically
cleared by the CPU when the service routine
is called.
If the external interrupt is level-activated, the
external source has to hold the request active
until the requested interrupt is actually
generated. Then it has to deactivate the
request before the interrupt service routine is
completed, or else another interrupt will be
generated.
Response Time
The INT0 and INT1 levels are inverted and
latched into IE0 and IE1 at S5P2 of every
March 1995
80C51 family hardware description
machine cycle. The values are not actually
polled by the circuitry until the next machine
cycle. If a request is active and conditions are
right for it to be acknowledged, a hardware
subroutine call to the requested service
routine will be the next instruction to be
executed. The call itself takes two cycles.
Thus, a minimum of three complete machine
cycles elapse between activation of an
external interrupt request and the beginning
of execution of the first instruction of the
service routine. Figure 20 shows interrupt
response timings.
A longer response time would result if the
request is blocked by one of the 3 previously
listed conditions. If an interrupt of equal or
higher priority level is already in progress, the
additional wait time obviously depends on the
nature of the other interrupt’s service routine.
If the instruction in progress is not in its final
cycle, the additional wait time cannot be more
the 3 cycles, since the longest instructions
(MUL and DIV) are only 4 cycles long, and if
the instruction in progress is RETI or an
access to IE or IP, the additional wait time
cannot be more than 5 cycles (a maximum of
one more cycle to complete the instruction in
progress, plus 4 cycles to complete the next
instruction if the instruction is MUL or DIV).
Thus, in a single-interrupt system, the
response time is always more than 3 cycles
and less than 9 cycles.
there until INT0 is pulsed (from low to high to
low). Then it will execute RETI, go back to
the task program, execute one instruction,
and immediately re-enter the External
Interrupt 0 routine to await the next pulsing of
P3.2. One step of the task program is
executed each time P3.2 is pulsed.
Reset
The reset input is the RST pin, which is the
input to a Schmitt Trigger. A reset is
accomplished by holding the RST pin high for
at least two machine cycles (24 oscillator
periods), while the oscillator is running. The
CPU responds by generating an internal
reset, with the timing shown in Figure 21.
The external reset signal is asynchronous to
the internal clock. The RST pin is sampled
during State 5 Phase 2 of every machine
cycle. The port pins will maintain their current
activities for 19 oscillator periods after a logic
1 has been sampled at the RST pin; that is,
for 19 to 31 oscillator periods after the
external reset signal has been applied to the
RST pin.
The internal reset algorithm writes 0s to all
the SFRs except the port latches, the Stack
Pointer, and SBUF. The port latches are
initialized to FFH, the Stack Pointer to 07H,
and SBUF is indeterminate. Table 1 lists the
SFR reset values. The internal RAM is not
affected by reset. On power up the RAM
content is indeterminate.
Single-Step Operation
The 80C51 interrupt structure allows
single-step execution with very little software
overhead. As previously noted, an interrupt
request will not be responded to while an
interrupt of equal priority level is still in
progress, nor will it be responded to after
RETI until at least one other instruction has
been executed. Thus, once an interrupt
routine has been entered, it cannot be
re-entered until at least one instruction of the
interrupted program is executed. One way to
use this feature for single-step operation is to
program one of the external interrupts (e.g.,
INT0) to be level-activated. The service
routine for the interrupt will terminate with the
following code:
JNB P3.2,$ ;Wait Till INT0 Goes High
JB
P3.2,$ ;Wait Till INT0 Goes Low
RETI
;Go Back and Execute One
Instruction
Now if the INT0 pin, which is also the P3.2
pin, is held normally low, the CPU will go right
into the External Interrupt 0 routine and stay
18
Table 1.
80C51 SFR Reset Values
REGISTER
RESET VALUE
PC
ACC
B
PSW
SP
DPTR
P0–P3
IP
IE
TMOD
TCON
TH0
TL0
TH1
TL1
SCON
SBUF
PCON (NMOS)
PCON (CMOS)
000H
00H
00H
00H
07H
0000H
FFH
XXX00000B
0XX00000B
00H
00H
00H
00H
00H
00H
00H
Indeterminate
0XXXXXXXB
0XXX0000B
Phlips Semiconductors
80C51 Family
80C51 family hardware description
12 Osc. Periods
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
RST:
Internal Reset Signal
Sample RST
Sample RST
ALE:
PSEN:
P0:
Inst.
Addr.
Inst.
Addr.
Inst.
Addr.
11 Osc. Periods
Inst.
Addr.
Inst.
Addr.
19 Osc. Periods
SU00547
Figure 21. Reset Timing
Power-on Reset
An automatic reset can be obtained when
VCC is turned on by connecting the RST pin
to VCC through a 10µf capacitor and to VSS
through an 8.2k resistor, providing the VCC
rise time does not exceed 1 millisecond and
the oscillator start-up time does not exceed
10 milliseconds. This power-on reset circuit is
shown in Figure 22. The CMOS devices do
not require the 8.2k pulldown resistor,
although its presence does no harm.
When power is turned on, the circuit holds
the RST pin high for an amount of time that
depends on the value of the capacitor and
the rate at which it charges. To ensure a good
reset, the RST pin must be high long enough
to allow the oscillator time to start-up
(normally a few ms) plus two machine cycles.
Note that the port pins will be in a random
state until the oscillator has started and the
internal reset algorithm has written 1s to
them.
With this circuit, reducing VCC quickly to 0
causes the RST pin voltage to momentarily
fall below 0V. However, this voltage is
internally limited, and will not harm the
device.
Power-Saving Modes of
Operation
For applications where power consumption is
critical the CMOS version provides power
reduced modes of operation as a standard
feature. The power down mode in NMOS
devices is no longer a standard feature.
CMOS Power Reduction Mode
CMOS versions have two power reducing
modes, Idle and Power Down. The input
through which backup power is supplied
during these operations is VCC. Figure 23
shows the internal circuitry which implements
these features. In the Idle modes (IDL = 1),
the oscillator continues to run and the
Interrupt, Serial Port, and Timer blocks
continue to be clocked, but the clock signal is
gated off to the CPU. In Power Down (PD =
1), the oscillator is frozen. The Idle and
Power Down Modes are activated by setting
bits in Special Function Register PCON. The
address of this register is 87H. Figure 24
details its contents.
In the NMOS devices the PCON register only
contains SMOD. The other four bits are
implemented only in the CMOS devices. User
software should never write 1s to
unimplemented bits, since they may be used
in other 80C51 Family products.
Idle Mode
An instruction that sets PCON.0 causes that
to be the last instruction executed before
going into the Idle mode, the internal clock
signal is gated off to the CPU but not to the
Interrupt, Timer, and Serial Port functions.
The CPU status is preserved in its entirety;
the Stack Pointer, Program Counter, Program
Status Word, Accumulator, and all other
registers maintain their data during Idle. The
port pins hold the logical states they had at
the time Idle was activated. ALE and PSEN
hold at logic high levels.
There are two ways to terminate the Idle.
Activation of any enabled interrupt will cause
March 1995
19
PCON.0 to be cleared by hardware,
terminating the Idle mode. The interrupt will
be serviced, and following RETI, the next
instruction to be executed will be the one
following the instruction that put the device
into Idle.
The flag bits GF0 and GF1 can be used to
give an indication if an interrupt occurred
during normal operation or during an Idle. For
example, an instruction that activates Idle
can also set one or both flag bits. When Idle
is terminated by an interrupt, the interrupt
service routine can examine the flag bits. The
other way of terminating the Idle mode is with
a hardware reset. Since the clock oscillator is
still running, the hardware reset needs to be
held active for only two machine cycles (24
oscillator periods) to complete the reset.
The signal at the RST pin clears the IDL bit
directly and asynchronously. At this time the
CPU resumes program execution from where
it left off; that is, at the instruction following
the one that invoked the Idle Mode. As shown
in Figure 21, two or three machine cycles of
program execution may take place before the
internal reset algorithm takes control. On-chip
hardware inhibits access to the internal RAM
during this time, but access to the port pins is
not inhibited, so, the insertion of 3 NOP
instructions is recommended following the
instruction that invokes idle mode. To
eliminate the possibility of unexpected
outputs at the port pins, the instruction
following the one that invokes Idle should not
be one that writes to a port pin or to external
Data RAM.
Phlips Semiconductors
80C51 Family
80C51 family hardware description
VCC
VCC
10µf
80C51
RST
8.2kΩ
VSS
SU00548
Figure 22. Power-On Reset Circuit
XTAL2
XTAL1
Osc.
Interrupt,
Serial Port,
Timer Blocks
Clock
Gen.
CPU
PD
IDL
SU00549
Figure 23. Idle and Power Down Hardware
MSB
LSB
SMOD
BIT
PCON.7
SYMBOL
SMOD
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
—
—
—
GF1
GF0
PD
IDL
—
—
—
GF1
GF0
PD
IDL
FUNCTION
Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the
Serial Port is used in modes 1, 2, or 3.
Reserved.
Reserved.
Reserved.
General-purpose flag bit.
General-purpose flag bit.
Power-Down bit. Setting this bit activates power-down operation.
Idle mode bit. Setting this bit activate idle mode operation.
If 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XXX0000).
In the NMOS devices, the PCON register only contains SMOD. The other four bits are implemented only in the CMOS
devices. User software should never write 1s to unimplemented bits, since they may be used in future products.
SU00550
Figure 24. Power Control (PCON) Register
March 1995
20
Phlips Semiconductors
80C51 Family
80C51 family hardware description
Power-Down Mode
An instruction that sets PCON.1 causes that
to be the last instruction executed before
going into the Power Down mode. In the
Power Down mode, the on-chip oscillator is
stopped. With the clock frozen, all functions
are stopped, the contents of the on-chip RAM
and Special Function Registers are
maintained. The port pins output the values
held by their respective SFRs. The ALE and
PSEN output are held low.
The only exit from Power Down is a hardware
reset. Reset redefines all the SFRs, but does
not change the on-chip RAM.
In the Power Down mode of operation, VCC
can be reduced to as low as 2V. Care must
be taken, however, to ensure that VCC is not
reduced before the Power Down mode is
invoked, and that VCC is restored to its
normal operating level, before the Power
Down mode is terminated. The reset that
terminates Power Down also frees the
oscillator. The reset should not be activated
before VCC is restored to its normal operating
level, and must be held active long enough to
allow the oscillator to restart and stabilize
(normally less than 10ms).
ONCE Mode
The ONCE (“on-circuit emulation”) mode
facilitates testing and debugging of systems
using the device without the device having to
be removed from the circuit. The ONCE
mode is invoked by:
1. Pull ALE low while the device in in reset
and PSEN is high;
port pins and ALE and PSEN are weakly
pulled high. The oscillator circuit remains
active. While the device is in this mode, an
emulator or test CPU can be used to drive
the circuit. Normal operation is restored after
a normal reset is applied.
linear inverter intended for use as a
crystal-controlled, positive reactance
oscillator in the same manner as the NMOS
parts. However, there are some important
differences.
One difference is that the 80C51 is able to
turn off its oscillator under software control
(by writing a 1 to the PD bit in PCON).
Another difference is that, in the 80C51, the
internal clocking circuitry is driven by the
signal at XTAL1, whereas in the NMOS
versions it is by the signal at XTAL2.
The On-Chip Oscillators
NMOS Version
The on-chip oscillator circuitry for the NMOS
members of the 80C51 family is a single
stage linear inverter (Figure 25), intended for
use as a crystal-controlled, positive
reactance oscillator (Figure 26). In this
application the crystal is operated in its
fundamental response mode as an inductive
reactance in parallel resonance with
capacitance external to the crystal.
The feedback resistor Rf in Figure 28
consists of paralleled n- and p-channel FETs
controlled by the PD bit, such that Rf is
opened when PD = 1. The diodes D1 and D2,
which act as clamps to VCC and VSS, are
parasitic to the Rf FETs. The oscillator can be
used with the same external components as
the NMOS versions, as shown in Figure 29.
Typically, C1 = C2 = 30pF when the feedback
element is a quartz crystal, and C1 = C2 =
47pF when a ceramic resonator is used.
The crystal specifications and capacitance
values (C1 and C2 in Figure 26) are not
critical. 30pF can be used in these positions
at any frequency with good quality crystals. A
ceramic resonator can be used in place of
the crystal in cost-sensitive applications.
When a ceramic resonator is used, C1 and
C2 are normally selected to be of somewhat
higher values, typically, 47pF. The
manufacturer of the ceramic resonator should
be consulted for recommendation on the
values of these capacitors.
2. Hold ALE low as RST is deactivated.
To drive the NMOS parts with an external
clock source, apply the external clock signal
to XTAL2, and ground XTAL1, as shown in
Figure 27. A pullup resistor may be used (to
increase noise margin), but is optional if VOH
of the driving gate exceeds the VIH minimum
specification of XTAL.
While the device is in the ONCE mode, the
Port 0 pins go into a float state, and the other
CMOS Versions
The on-chip oscillator circuitry for the 80C51,
shown in Figure 28, consists of a single stage
When a crystal is used at frequencies above
25MHz, C1 and C2 should be in the range of
20pF to 25pF.
To drive the CMOS parts with an external
clock source, apply the external clock signal
to XTAL1, and leave XTAL2 float, as shown
in Figure 30.
The reason for this change from the way the
NMOS part is driven can be seen by
comparing Figures 26 and 28. In the NMOS
devices the internal timing circuits are driven
by the signal at XTAL2. In the CMOS devices
the internal timing circuits are driven by the
signal at XTAL1.
VCC
TO INTERNAL
TIMING CIRCUITS
Q3
XTAL2
Q2
Q4
XTAL1
Q1
SUBST.
VSS
SU00551
Figure 25. On-Chip Oscillator in the NMOS Version of the 8051 Family
March 1995
21
Phlips Semiconductors
80C51 Family
80C51 family hardware description
Q2
TO INTERNAL
TIMING CIRCUITS
Q1
Q3, Q4
VSS
8051
XTAL1
XTAL2
QUARTZ CRYSTAL OR
CERAMIC RESONATOR
C1
C2
SU00552
Figure 26. Using the NMOS On-Chip Oscillator
VCC
8051
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTAL1
TTL GATE WITH
TOTEM-POLE OUTPUT
VSS
SU00553
Figure 27. Driving the NMOS 8051 Family Parts with an External Clock
VCC
TO INTERNAL
TIMING CIRCUITS
•
Q2
D1
400Ω
XTAL1
•
•
•
Q1
Rf
•
XTAL2
Q3
D2
•
PD
Q4
VSS
Figure 28. On-Chip Oscillator Circuitry in the CMOS Version of the 80C51 Family
March 1995
22
SU00554
Phlips Semiconductors
80C51 Family
80C51 family hardware description
VCC
PD
TO INTERNAL
TIMING CIRCUITS
Rf
VSS
80C51
XTAL2
XTAL1
QUARTZ CRYSTAL OR
CERAMIC RESONATOR
C1
C2
SU00555
Figure 29. Using the CMOS On-Chip Oscillator
80C51
NC
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTAL1
VSS
CMOS GATE
SU00556
Figure 30. Driving the CMOS Family Parts with an External Clock Source
Internal Timing
80C51 Pin Descriptions
Figures 31 through 34 show when the
various strobe and port signals are clocked
internally. The figures do not show rise and
fall times of the signals, nor do they show
propagation delays between the XTAL2
signal and events at other pins.
ALE/PROG: Address Latch Enable output
pulse for latching the low byte of the address
during accesses to external memory. ALE is
emitted at a constant rate of 1/6 of the
oscillator frequency, for external timing or
clocking purposes, even when there are no
accesses to external memory. (However, one
ALE pulse is skipped during each access to
external Data Memory.) This pin is also the
program pulse input (PROG) during EPROM
programming.
Rise and fall times are dependent on the
external loading that each pin must drive.
They are often taken to be something in the
neighborhood of 10ns, measured between
0.8V and 2.0V.
Propagation delays are different for different
pins. For a given pin they vary with pin
loading, temperature, VCC, and
manufacturing lot. If the XTAL2 waveform is
taken as the timing reference, prop delays
may vary up to ±200%.
The AC Timings section of the data sheets do
not reference any timing to the XTAL2
waveform. Rather, they relate the critical
edges of control and input signals to each
other. The timings published in the data
sheets include the effects of propagation
delays under the specified test conditions.
March 1995
PSEN: Program Store Enable is the read
strobe to external Program Memory. When
the device is executing out of external
Program Memory, PSEN is activated twice
each machine cycle (except that two PSEN
activations are skipped during accesses to
external Data Memory). PSEN is not
activated when the device is executing out of
internal Program Memory.
EA/VPP: When EA is held high the CPU
executes out of internal Program Memory
(unless the Program Counter exceeds
0FFFH in the 80C51). Holding EA low forces
the CPU to execute out of external memory
regardless of the Program Counter value. In
the 80C31, EA must be externally wired low.
23
In the EPROM devices, this pin also receives
the programming supply voltage (VPP) during
EPROM programming.
XTAL1: Input to the inverting oscillator
amplifier.
XTAL2: Output from the inverting oscillator
amplifier.
Port 0: Port 0 is an 8-bit open drain
bidirectional port. As an open drain output
port, it can sink eight LS TTL loads. Port 0
pins that have 1s written to them float, and in
that state will function as high impedance
inputs. Port 0 is also the multiplexed
low-order address and data bus during
accesses to external memory. In this
application it uses strong internal pullups
when emitting 1s. Port 0 emits code bytes
during program verification. In this
application, external pullups are required.
Port 1: Port 1 is an 8-bit bidirectional I/O port
with internal pullups. Port 1 pins that have 1s
written to them are pulled high by the internal
pullups, and in that state can be used as
inputs. As inputs, port 1 pins that are
externally being pulled low will source current
because of the internal pullups.
Phlips Semiconductors
80C51 Family
80C51 family hardware description
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
Port 2: Port 2 is an 8-bit bidirectional I/O port
with internal pullups. Port 2 emits the
high-order address byte during accesses to
external memory that use 16-bit addresses.
In this application, it uses the strong internal
pullups when emitting 1s.
Port 3: Port 3 is an 8-bit bidirectional I/O port
with internal pullups. It also serves the
functions of various special features of the
80C51 Family as follows:
State 1
P1
P2
P3.7
State 2
P1
P2
State 3
P2
P1
Alternate Function
RxD (serial input port)
TxD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory
write strobe)
RD (external data memory
read strobe)
State 4
P1
P2
State 5
P1
P2
VCC: Supply voltage
VSS: Circuit ground potential
State 6
P1
P2
State 1
P1
P2
State 2
P1
P2
XTAL2:
ALE:
PSEN:
Data Sampled
Data Sampled
PCL
Out
P0:
Data Sampled
PCL
Out
P2:
PCH Out
PCL
Out
PCH Out
PCH Out
SU00557
Figure 31. External Program Memory Fetches
State 4
P1
P2
State 5
P1
P2
State 6
P1
P2
State 1
P1
P2
State 2
P1
P2
State 3
P1
P2
State 4
P1
P2
State 5
P1
P2
XTAL2:
ALE:
RD:
PCL Out if Program
Memory Is External
Data Sampled
P0:
P2:
Float
DPL or RI
Out
PCH or P2
SFR
Float
DPH or P2 SFR Out
PCH or P2
SFR
SU00558
Figure 32. External Data Memory Read Cycle
March 1995
24
Phlips Semiconductors
80C51 Family
80C51 family hardware description
State 4
P1
P2
State 5
P1
P2
State 6
P1
P2
State 1
P1
P2
State 2
P1
P2
State 3
P1
P2
State 4
P1
P2
State 5
P1
P2
XTAL2:
ALE:
WR:
PCL Out if Program
Memory Is External
DPL or RI
Out
P0:
P2:
PCL
Out
Data Out
PCH or P2
SFR
PCH or P2
SFR
DPH or P2 SFR Out
SU00559
Figure 33. External Data Memory Write Cycle
State 4
P1
P2
State 5
P1
P2
State 6
P2
P1
State 1
P1
P2
State 2
P1
P2
State 3
P1
P2
State 4
P1
P2
State 5
P1
P2
XTAL2:
P0, P1
P0, P1
Inputs Sampled:
P2, P3, RST
MOV Port, SRC:
P2, P3, RST
Old Data
New Data
Serial Port
Shift Clock
(Mode 0):
RXD Pin Sampled
RXD Sampled
SU00560
Figure 34. Port Operation
March 1995
25
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