datasheet for A29L640 by AMIC Technology

datasheet for A29L640 by AMIC Technology
A29L640 Series
8M X 8 Bit / 4M X 16 Bit CMOS 3.0 Volt-only,
Boot Sector Flash Memory
Document Title
8M X 8 Bit / 4M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No.
History
Issue Date
0.0
Initial issue
October 16, 2008
1.0
Final version release
May 12, 2009
1.1
Page 1: Change from typical 100,000 cycles to minimum 100,000
December 1, 2010
Remark
Preliminary
Final
cycles
(December, 2010, Version 1.1)
AMIC Technology, Corp.
A29L640 Series
8M X 8 Bit / 4M X 16 Bit CMOS 3.0 Volt-only,
Boot Sector Flash Memory
Features
̈ Single power supply operation
- Regulated voltage range: 2.7 to 3.6 volt read and write
operations for compatibility with high performance 3 volt
microprocessors
̈ Access times:
- 70ns (max.)
̈ Current:
- 2mA active read current at 1MHz
- 10mA active read current at 5MHz
- 20mA typical program/erase current
- 1μA typical CMOS standby or Automatic Sleep Mode
current
̈ Flexible sector architecture
- 8KB x 8 sectors
- 64KB x 127 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
̈ Extra 128-word sector for security
̈ Unlock Bypass Program Command
- Reduces overall programming time when issuing
multiple program command sequence
̈ Top or bottom boot block available
̈ Embedded Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies data at specified addresses
̈ Minimum 100,000 program/erase cycles per sector
̈ 20-year data retention at 125°C
- Reliable operation for the life of the system
̈ CFI (Common Flash Interface) compliant
- Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
̈ Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
- Superior inadvertent write protection
̈ Data Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
̈ Ready / BUSY pin (RY / BY )
- Provides a hardware method of detecting completion of
program or erase operations (not available on 44-pin
SOP)
̈ Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
̈ Hardware reset pin ( RESET )
- Hardware method to reset the device to reading array
data
̈ WP /ACC input pin
- Write protect ( WP ) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- Acceleration (ACC) function provides accelerated
program times
̈ Hardware/Software temporary sector block unprotect
command allows code changes in previously locked
sectors
̈ Hardware/Software sector protect/unprotect command
̈ Package options
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
- All Pb-free (Lead-free) products are RoHS compliant
General Description
A29L640 also offers the ability to program in the Erase
Suspend mode. The standard A29L640 offers access times
of 70ns, allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention the device
has separate chip enable ( CE ), write enable ( WE ) and
The A29L640 is a 64Mbit, 3.3 volt-only Flash memory
organized as 4,194,304 words of 16 bits or 8,388,608 bytes
of 8 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16
bits of data appear on I/O0~I/O15. The A29L640 is offered in
44-Pin SOP, 48-Pin TSOP and 48-ball TFBGA packages.
This device is designed to be programmed in-system with the
standard system 3.3 volt VCC supply. Additional 12.0 volt
VPP is not required for in-system write or erase operations.
However, the A29L640 can also be programmed in standard
EPROM programmers.
The A29L640 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29L640 has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
(December, 2010, Version 1.1)
output enable ( OE ) controls.
The device requires only a single 3.3 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29L640 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
1
AMIC Technology, Corp.
A29L640 Series
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L640 is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY / BY pin, or by
reading the I/O7 ( Data Polling) and I/O6 (toggle) status bits.
After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
Pin Configurations
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A29L640M
̈ SOP
̈ TSOP (I)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
WE
VSS
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
(December, 2010, Version 1.1)
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
A21
WP
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A29L640V
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O15(A-1)
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
VSS
CE
A0
AMIC Technology, Corp.
A29L640 Series
Pin Configurations (continued)
̈ TFBGA
TFBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
A13
A12
A14
A15
A16
BYTE
A5
B5
C5
D5
E5
F5
G5
A9
A8
A10
A11
I/O7
I/O14
I/O13
A4
B4
C4
D4
E4
F4
G4
H4
RESET
A21
A19
I/O5
I/O12
VCC
I/O4
B3
C3
D3
E3
F3
G3
H3
WP/ACC
A18
A20
I/O 2
I/O10
I/O11
I/O3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
I/O0
I/O 8
I/O9
I/O1
A1
B1
C1
E1
F1
G1
H1
A3
A4
A2
A0
CE
OE
VSS
WE
A3
RY/BY
(December, 2010, Version 1.1)
D1
A1
3
H6
G6
I/O15(A-1)
VSS
H5
I/O6
AMIC Technology, Corp.
A29L640 Series
Block Diagram
RY/BY
I/O0 - I/O15 (A-1)
VCC
VSS
Sector Switches
RESET
WE
Input/Output
Buffers
Erase Voltage
Generator
State
Control
BYTE
WP/ACC
PGM Voltage
Generator
Command
Register
Chip Enable
Output Enable
Logic
CE
OE
VCC Detector
Timer
A0-A21
Data Latch
Y-Decoder
Y-Gating
X-decoder
Cell Matrix
Address Latch
STB
STB
Pin Descriptions
Pin No.
A0 – A21
Address Inputs
I/O0 - I/O14
Data Inputs/Outputs
I/O15 (A-1)
I/O15
Data Input/Output, Word Mode
A-1
LSB Address Input, Byte Mode
CE
Chip Enable
WE
Write Enable
OE
Output Enable
RESET
Hardware Reset
BYTE
Selects Byte Mode or Word Mode
RY/ BY
Ready/ BUSY - Output
VSS
Ground
VCC
Power Supply
NC
WP /ACC
(December, 2010, Version 1.1)
Description
Pin not connected internally
Hardware Write Protect / Acceleration Pin
4
AMIC Technology, Corp.
A29L640 Series
Absolute Maximum Ratings*
*Comments
Storage Temperature Plastic Packages. . . -65°C to + 150°C
Ambient Temperature with Power Applied. -55°C to + 125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V
A9, OE & RESET (Note 2) . . . . . . . . . . . . . -0.5V to +10.5V
WP /ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V
All other pins (Note 1) . . . . . . . . . . . . . . -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . 200mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Operating Ranges
Notes:
Commercial (C) Devices
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0V
for periods up to 20ns.
2. Minimum DC input voltage on A9, OE and RESET is -
Ambient Temperature (TA) . . . . . . . . . . . . . . . . 0°C to +70°C
Extended Range Devices
Ambient Temperature (TA)
For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
For –I series . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
0.5V. During voltage transitions, A9, OE and RESET
may overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +10.5V which may
overshoot to 14.0V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . . . . . +2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
Table 1. A29L640 Device Bus Operations
Operation
WP /
ACC
A0 - A21
(Note 1)
I/O0 - I/O7
BYTE =VIH
BYTE =VIL
H
L/H
AIN
DOUT
DOUT
L
H
(Note 3)
AIN
(Note 4)
(Note 4)
I/O8~I/O14=High-Z
I/O15=A-1
H
L
H
VHH
AIN
(Note 4)
(Note 4)
High-Z
X
X
H
X
High-Z
High-Z
High-Z
H
H
VCC ±
0.3 V
H
L/H
X
High-Z
High-Z
High-Z
X
X
L
L/H
X
High-Z
High-Z
High-Z
WE RESET
CE
OE
Read
L
L
H
Write
L
H
Accelerated
Program
Standby
L
VCC ±
0.3 V
L
X
Output Disable
Reset
I/O8 - I/O15
Sector Address,
Sector Protect
L
H
L
VID
(Note 4)
X
X
L/H
A6=L, A1=H, A0=L
(Note 2)
Sector Address,
Sector Unprotect
L
H
L
VID
L/H
(Note 4)
X
X
A6=H, A1=H, A0=L
(Note 2)
Temporary Sector
X
X
X
VID
L/H
AIN
(Note 4)
(Note 4)
High-Z
Unprotect
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 9V-10.5V, VHH = 9V-10.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Notes:
1. Addresses are A21:A0 in word mode ( BYTE =VIH), A21: A-1 in byte mode ( BYTE =VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector
Block Protection and Unprotection”.
3. If WP /ACC=VIL, the two outermost boot sectors remain protected. If WP /ACC=VIH, the two outermost boot sector protection depends
on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection. If
WP /ACC = VHH, all sectors are unprotected. If WP /ACC is left floating, it is internally held to VDD via a pull-up resistor.
4. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
(December, 2010, Version 1.1)
5
AMIC Technology, Corp.
A29L640 Series
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Word/Byte Configuration
The BYTE pin determines whether the I/O pins I/O15-I/O0
operate in the byte or word configuration. If the BYTE pin is
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by CE and OE .
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
If the BYTE pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled by
CE and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used
as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
Standby Mode
To read array data from the outputs, the system must drive
the CE and OE pins to VIL. CE is the power control and
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE
input.
selects the device. OE is the output control and gates array
data to the output pins. WE should remain at VIH all the time
during read operation. The BYTE pin determines whether
the device outputs array data in words and bytes. The
internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
The device enters the CMOS standby mode when the CE &
RESET pins are both held at VCC ± 0.3V. (Note that this is a
more restricted voltage range than VIH.) If CE and RESET
are held at VIH, but not within VCC ± 0.3V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (tCE) before it
is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 and ICC4 in the DC Characteristics tables represent the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
sleep mode is independent of the CE , WE and OE control
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep
mode current specification.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE to VIL, and
OE to VIH. For program operations, the BYTE pin
determines whether the device accepts program data in
bytes or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Word / Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An erase
operation can erase one sector, multiple sectors, or the
entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector address"
consists of the address inputs required to uniquely select a
sector. See the "Command Definitions" section for details on
erasing a sector or the entire chip, or suspending/resuming
the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
(December, 2010, Version 1.1)
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS ± 0.3V, the device draws
6
AMIC Technology, Corp.
A29L640 Series
Embedded Algorithms). The system can thus monitor
RY/ BY to determine whether the reset operation is
complete. If RESET is asserted when a program or erase
operation is not executing (RY/ BY pin is “1”), the reset
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
the RESET pin return to VIH.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
CMOS standby current (ICC4 ). If RESET is held at VIL but not
within VSS ± 0.3V, the standby current will be greater.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
the RY/ BY pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Table 2. A29L640 Top Boot Block Sector Address Table
Sector
A21-A12
Sector Size
(Kbytes/ Kwords)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
0000000XXX
0000001XXX
0000010XXX
0000011XXX
0000100XXX
0000101XXX
0000110XXX
0000111XXX
0001000XXX
0001001XXX
0001010XXX
0001011XXX
0001100XXX
0001101XXX
0001110XXX
0001111XXX
0010000XXX
0010001XXX
0010010XXX
0010011XXX
0010100XXX
0010101XXX
0010110XXX
0010111XXX
0011000XXX
0011001XXX
0011010XXX
0011011XXX
0011100XXX
0011101XXX
0011110XXX
0011111XXX
0100000XXX
0100001XXX
0100010XXX
0100011XXX
0100100XXX
0100101XXX
0100110XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(December, 2010, Version 1.1)
7
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
000000–00FFFF
000000–007FFF
010000–01FFFF
008000–00FFFF
020000–02FFFF
010000–017FFF
030000–03FFFF
018000–01FFFF
040000–04FFFF
020000–027FFF
050000–05FFFF
028000–02FFFF
060000–06FFFF
030000–037FFF
070000–07FFFF
038000–03FFFF
080000–08FFFF
040000–047FFF
090000–09FFFF
048000–04FFFF
0A0000–0AFFFF
050000–057FFF
0B0000–0BFFFF
058000–05FFFF
0C0000–0CFFFF
060000–067FFF
0D0000–0DFFFF
068000–06FFFF
0E0000–0EFFFF
070000–077FFF
0F0000–0FFFFF
078000–07FFFF
100000–10FFFF
080000–087FFF
110000–11FFFF
088000–08FFFF
120000–12FFFF
090000–097FFF
130000–13FFFF
098000–09FFFF
140000–14FFFF
0A0000–0A7FFF
150000–15FFFF
0A8000–0AFFFF
160000–16FFFF
0B0000–0B7FFF
170000–17FFFF
0B8000–0BFFFF
180000–18FFFF
0C0000–0C7FFF
190000–19FFFF
0C8000–0CFFFF
1A0000–1AFFFF
0D0000–0D7FFF
1B0000–1BFFFF
0D8000–0DFFFF
1C0000–1CFFFF
0E0000–0E7FFF
1D0000–1DFFFF
0E8000–0EFFFF
1E0000–1EFFFF
0F0000–0F7FFF
1F0000–1FFFFF
0F8000–0FFFFF
200000–20FFFF
100000–107FFF
210000–21FFFF
108000–10FFFF
220000–22FFFF
110000–117FFF
230000–23FFFF
118000–11FFFF
240000–24FFFF
120000–127FFF
250000–25FFFF
128000–12FFFF
260000–26FFFF
130000–137FFF
AMIC Technology, Corp.
A29L640 Series
Table 2. A29L640 Top Boot Block Sector Address Table (continued)
Sector
A21-A12
Sector Size
(Kbytes/ Kwords)
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
0100111XXX
0101000XXX
0101001XXX
0101010XXX
0101011XXX
0101100XXX
0101101XXX
0101110XXX
0101111XXX
0110000XXX
0110001XXX
0110010XXX
0110011XXX
0110100XXX
0110101XXX
0110110XXX
0110111XXX
0111000XXX
0111001XXX
0111010XXX
0111011XXX
0111100XXX
0111101XXX
0111110XXX
0111111XXX
1000000XXX
1000001XXX
1000010XXX
1000011XXX
1000100XXX
1000101XXX
1000110XXX
1000111XXX
1001000XXX
1001001XXX
1001010XXX
1001011XXX
1001100XXX
1001101XXX
1001110XXX
1001111XXX
1010000XXX
1010001XXX
1010010XXX
1010011XXX
1010100XXX
1010101XXX
1010110XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(December, 2010, Version 1.1)
8
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
270000–27FFFF
138000–13FFFF
280000–28FFFF
140000–147FFF
290000–29FFFF
148000–14FFFF
2A0000–2AFFFF
150000–157FFF
2B0000–2BFFFF
158000–15FFFF
2C0000–2CFFFF
160000–167FFF
2D0000–2DFFFF
168000–16FFFF
2E0000–2EFFFF
170000–177FFF
2F0000–2FFFFF
178000–17FFFF
300000–30FFFF
180000–187FFF
310000–31FFFF
188000–18FFFF
320000–32FFFF
190000–197FFF
330000–33FFFF
198000–19FFFF
340000–34FFFF
1A0000–1A7FFF
350000–35FFFF
1A8000–1AFFFF
360000–36FFFF
1B0000–1B7FFF
370000–37FFFF
1B8000–1BFFFF
380000–38FFFF
1C0000–1C7FFF
390000–39FFFF
1C8000–1CFFFF
3A0000–3AFFFF
1D0000–1D7FFF
3B0000–3BFFFF
1D8000–1DFFFF
3C0000–3CFFFF
1E0000–1E7FFF
3D0000–3DFFFF
1E8000–1EFFFF
3E0000–3EFFFF
1F0000–1F7FFF
3F0000–3FFFFF
1F8000–1FFFFF
400000–40FFFF
200000–207FFF
410000–41FFFF
208000–20FFFF
420000–42FFFF
210000–217FFF
430000–43FFFF
218000–21FFFF
440000–44FFFF
220000–227FFF
450000–45FFFF
228000–22FFFF
460000–46FFFF
230000–237FFF
470000–47FFFF
238000–23FFFF
480000–48FFFF
240000–247FFF
490000–49FFFF
248000–24FFFF
4A0000–4AFFFF
250000–257FFF
4B0000–4BFFFF
258000–25FFFF
4C0000–4CFFFF
260000–267FFF
4D0000–4DFFFF
268000–26FFFF
4E0000–4EFFFF
270000–277FFF
4F0000–4FFFFF
278000–27FFFF
500000–50FFFF
280000–287FFF
510000–51FFFF
288000–28FFFF
520000–52FFFF
290000–297FFF
530000–53FFFF
298000–29FFFF
540000–54FFFF
2A0000–2A7FFF
550000–55FFFF
2A8000–2AFFFF
560000–56FFFF
2B0000–2B7FFF
AMIC Technology, Corp.
A29L640 Series
Table 2. A29L640 Top Boot Block Sector Address Table (continued)
Sector
A21-A12
Sector Size
(Kbytes/ Kwords)
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
1010111XXX
1011000XXX
1011001XXX
1011010XXX
1011011XXX
1011100XXX
1011101XXX
1011110XXX
1011111XXX
1100000XXX
1100001XXX
1100010XXX
1100011XXX
1100100XXX
1100101XXX
1100110XXX
1100111XXX
1101000XXX
1101001XXX
1101010XXX
1101011XXX
1101100XXX
1101101XXX
1101110XXX
1101111XXX
1110000XXX
1110001XXX
1110010XXX
1110011XXX
1110100XXX
1110101XXX
1110110XXX
1110111XXX
1111000XXX
1111001XXX
1111010XXX
1101011XXX
1101100XXX
1101101XXX
1101110XXX
1101111XXX
1110000XXX
1110001XXX
1110010XXX
1110011XXX
1110100XXX
1110101XXX
1110110XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(December, 2010, Version 1.1)
9
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
570000–57FFFF
2B8000–2BFFFF
580000–58FFFF
2C0000–2C7FFF
590000–59FFFF
2C8000–2CFFFF
5A0000–5AFFFF
2D0000–2D7FFF
5B0000–5BFFFF
2D8000–2DFFFF
5C0000–5CFFFF
2E0000–2E7FFF
5D0000–5DFFFF
2E8000–2EFFFF
5E0000–5EFFFF
2F0000–2F7FFF
5F0000–5FFFFF
2F8000–2FFFFF
600000–60FFFF
300000–307FFF
610000–61FFFF
308000–30FFFF
620000–62FFFF
310000–317FFF
630000–63FFFF
318000–31FFFF
640000–64FFFF
320000–327FFF
650000–65FFFF
328000–32FFFF
660000–66FFFF
330000–337FFF
670000–67FFFF
338000–33FFFF
680000–68FFFF
340000–347FFF
690000–69FFFF
348000–34FFFF
6A0000–6AFFFF
350000–357FFF
6B0000–6BFFFF
358000–35FFFF
6C0000–6CFFFF
360000–367FFF
6D0000–6DFFFF
368000–36FFFF
6E0000–6EFFFF
370000–377FFF
6F0000–6FFFFF
378000–37FFFF
700000–70FFFF
380000–387FFF
710000–71FFFF
388000–38FFFF
720000–72FFFF
390000–397FFF
730000–73FFFF
398000–39FFFF
740000–74FFFF
3A0000–3A7FFF
750000–75FFFF
3A8000–3AFFFF
760000–76FFFF
3B0000–3B7FFF
770000–77FFFF
3B8000–3BFFFF
780000–78FFFF
3C0000–3C7FFF
790000–79FFFF
3C8000–3CFFFF
7A0000–7AFFFF
3D0000–3D7FFF
6B0000–6BFFFF
358000–35FFFF
6C0000–6CFFFF
360000–367FFF
6D0000–6DFFFF
368000–36FFFF
6E0000–6EFFFF
370000–377FFF
6F0000–6FFFFF
378000–37FFFF
700000–70FFFF
380000–387FFF
710000–71FFFF
388000–38FFFF
720000–72FFFF
390000–397FFF
730000–73FFFF
398000–39FFFF
740000–74FFFF
3A0000–3A7FFF
750000–75FFFF
3A8000–3AFFFF
760000–76FFFF
3B0000–3B7FFF
AMIC Technology, Corp.
A29L640 Series
Table 2. A29L640 Top Boot Block Sector Address Table (continued)
Sector
A21-A12
Sector Size
(Kbytes/ Kwords)
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1110111XXX
1111000XXX
1111001XXX
1111010XXX
1111011XXX
1111100XXX
1111101XXX
1111110XXX
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
770000–77FFFF
3B8000–3BFFFF
780000–78FFFF
3C0000–3C7FFF
790000–79FFFF
3C8000–3CFFFF
7A0000–7AFFFF
3D0000–3D7FFF
7B0000–7BFFFF
3D8000–3DFFFF
7C0000–7CFFFF
3E0000–3E7FFF
7D0000–7DFFFF
3E8000–3EFFFF
7E0000–7EFFFF
3F0000–3F7FFF
7F0000–7F1FFF
3F8000–3F8FFF
7F2000–7F3FFF
3F9000–3F9FFF
7F4000–7F5FFF
3FA000–3FAFFF
7F6000–7F7FFF
3FB000–3FBFFF
7F8000–7F9FFF
3FC000–3FCFFF
7FA000–7FBFFF
3FD000–3FDFFF
7FC000–7FDFFF
3FE000–3FEFFF
7FE000–7FFFFF
3FF000–3FFFFF
Top Boot Security Sector Addresses
Sector Size
Byte Mode
(bytes)
Word Mode
(words)
256
128
Sector Address
A21-A12
1111111111
Address Range (in hexadecimal)
Byte Mode
(x8)
Word Mode
(x16)
7FFF00–7FFFFF
3FFF80–3FFFFF
Note:
Address range is A21: A-1 in byte mode and A21 : A0 in word mode. See “Word/Byte Configuration” section.
(December, 2010, Version 1.1)
10
AMIC Technology, Corp.
A29L640 Series
Table 3. A29L640 Bottom Boot Block Sector Address Table
Sector
A21 -A12
Sector Size
(Kbytes/ Kwords)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX
0000010XXX
0000011XXX
0000100XXX
0000101XXX
0000110XXX
0000111XXX
0001000XXX
0001001XXX
0001010XXX
0001011XXX
0001100XXX
0001101XXX
0001110XXX
0001111XXX
0010000XXX
0010001XXX
0010010XXX
0010011XXX
0010100XXX
0010101XXX
0010110XXX
0010111XXX
0011000XXX
0011001XXX
0011010XXX
0011011XXX
0011100XXX
0011101XXX
0011110XXX
0011111XXX
0100000XXX
0100001XXX
0100010XXX
0100011XXX
0100100XXX
0100101XXX
0100110XXX
0100111XXX
0101000XXX
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(December, 2010, Version 1.1)
11
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
000000–001FFF
000000–000FFF
002000–003FFF
001000–001FFF
004000–005FFF
002000–002FFF
006000–007FFF
003000–003FFF
008000–009FFF
004000–004FFF
00A000–00BFFF
005000–005FFF
00C000–00DFFF
006000–006FFF
00E000–00FFFF
007000–007FFF
010000–01FFFF
008000–00FFFF
020000–02FFFF
010000–017FFF
030000–03FFFF
018000–01FFFF
040000–04FFFF
020000–027FFF
050000–05FFFF
028000–02FFFF
060000–06FFFF
030000–037FFF
070000–07FFFF
038000–03FFFF
080000–08FFFF
040000–047FFF
090000–09FFFF
048000–04FFFF
0A0000–0AFFFF
050000–057FFF
0B0000–0BFFFF
058000–05FFFF
0C0000–0CFFFF
060000–067FFF
0D0000–0DFFFF
068000–06FFFF
0E0000–0EFFFF
070000–077FFF
0F0000–0FFFFF
078000–07FFFF
100000–10FFFF
080000–087FFF
110000–11FFFF
088000–08FFFF
120000–12FFFF
090000–097FFF
130000–13FFFF
098000–09FFFF
140000–14FFFF
0A0000–0A7FFF
150000–15FFFF
0A8000–0AFFFF
160000–16FFFF
0B0000–0B7FFF
170000–17FFFF
0B8000–0BFFFF
180000–18FFFF
0C0000–0C7FFF
190000–19FFFF
0C8000–0CFFFF
1A0000–1AFFFF
0D0000–0D7FFF
1B0000–1BFFFF
0D8000–0DFFFF
1C0000–1CFFFF
0E0000–0E7FFF
1D0000–1DFFFF
0E8000–0EFFFF
1E0000–1EFFFF
0F0000–0F7FFF
1F0000–1FFFFF
0F8000–0FFFFF
200000–20FFFF
100000–107FFF
210000–21FFFF
108000–10FFFF
220000–22FFFF
110000–117FFF
230000–23FFFF
118000–11FFFF
240000–24FFFF
120000–127FFF
250000–25FFFF
128000–12FFFF
260000–26FFFF
130000–137FFF
270000–27FFFF
138000–13FFFF
280000–28FFFF
140000–147FFF
AMIC Technology, Corp.
A29L640 Series
Table 3. A29L640 Bottom Boot Block Sector Address Table (continued)
Sector
A21 -A12
Sector Size
(Kbytes/ Kwords)
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
0101001XXX
0101010XXX
0101011XXX
0101100XXX
0101101XXX
0101110XXX
0101111XXX
0110000XXX
0110001XXX
0110010XXX
0110011XXX
0110100XXX
0110101XXX
0110110XXX
0110111XXX
0111000XXX
0111001XXX
0111010XXX
0111011XXX
0111100XXX
0111101XXX
0111110XXX
0111111XXX
1000000XXX
1000001XXX
1000010XXX
1000011XXX
1000100XXX
1000101XXX
1000110XXX
1000111XXX
1001000XXX
1001001XXX
1001010XXX
1001011XXX
1001100XXX
1001101XXX
1001110XXX
1001111XXX
1010000XXX
1010001XXX
1010010XXX
1010011XXX
1010100XXX
1010101XXX
1010110XXX
1010111XXX
1011000XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(December, 2010, Version 1.1)
12
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
290000–29FFFF
148000–14FFFF
2A0000–2AFFFF
150000–157FFF
2B0000–2BFFFF
158000–15FFFF
2C0000–2CFFFF
160000–167FFF
2D0000–2DFFFF
168000–16FFFF
2E0000–2EFFFF
170000–177FFF
2F0000–2FFFFF
178000–17FFFF
300000–30FFFF
180000–187FFF
310000–31FFFF
188000–18FFFF
320000–32FFFF
190000–197FFF
330000–33FFFF
198000–19FFFF
340000–34FFFF
1A0000–1A7FFF
350000–35FFFF
1A8000–1AFFFF
360000–36FFFF
1B0000–1B7FFF
370000–37FFFF
1B8000–1BFFFF
380000–38FFFF
1C0000–1C7FFF
390000–39FFFF
1C8000–1CFFFF
3A0000–3AFFFF
1D0000–1D7FFF
3B0000–3BFFFF
1D8000–1DFFFF
3C0000–3CFFFF
1E0000–1E7FFF
3D0000–3DFFFF
1E8000–1EFFFF
3E0000–3EFFFF
1F0000–1F7FFF
3F0000–3FFFFF
1F8000–1FFFFF
400000–40FFFF
200000–207FFF
410000–41FFFF
208000–20FFFF
420000–42FFFF
210000–217FFF
430000–43FFFF
218000–21FFFF
440000–44FFFF
220000–227FFF
450000–45FFFF
228000–22FFFF
460000–46FFFF
230000–237FFF
470000–47FFFF
238000–23FFFF
480000–48FFFF
240000–247FFF
490000–49FFFF
248000–24FFFF
4A0000–4AFFFF
250000–257FFF
4B0000–4BFFFF
258000–25FFFF
4C0000–4CFFFF
260000–267FFF
4D0000–4DFFFF
268000–26FFFF
4E0000–4EFFFF
270000–277FFF
4F0000–4FFFFF
278000–27FFFF
500000–50FFFF
280000–287FFF
510000–51FFFF
288000–28FFFF
520000–52FFFF
290000–297FFF
530000–53FFFF
298000–29FFFF
540000–54FFFF
2A0000–2A7FFF
550000–55FFFF
2A8000–2AFFFF
560000–56FFFF
2B0000–2B7FFF
570000–57FFFF
2B8000–2BFFFF
580000–58FFFF
2C0000–2C7FFF
AMIC Technology, Corp.
A29L640 Series
Table 3. A29L640 Bottom Boot Block Sector Address Table (continued)
Sector
A21 -A12
Sector Size
(Kbytes/ Kwords)
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1011001XXX
1011010XXX
1011011XXX
1011100XXX
1011101XXX
1011110XXX
1011111XXX
1100000XXX
1100001XXX
1100010XXX
1100011XXX
1100100XXX
1100101XXX
1100110XXX
1100111XXX
1101000XXX
1101001XXX
1101010XXX
1101011XXX
1101100XXX
1101101XXX
1101110XXX
1101111XXX
1110000XXX
1110001XXX
1110010XXX
1110011XXX
1110100XXX
1110101XXX
1110110XXX
1110111XXX
1111000XXX
1111001XXX
1111010XXX
1111011XXX
1111100XXX
1111101XXX
1111110XXX
1111111XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
590000–59FFFF
2C8000–2CFFFF
5A0000–5AFFFF
2D0000–2D7FFF
5B0000–5BFFFF
2D8000–2DFFFF
5C0000–5CFFFF
2E0000–2E7FFF
5D0000–5DFFFF
2E8000–2EFFFF
5E0000–5EFFFF
2F0000–2F7FFF
5F0000–5FFFFF
2F8000–2FFFFF
600000–60FFFF
300000–307FFF
610000–61FFFF
308000–30FFFF
620000–62FFFF
310000–317FFF
630000–63FFFF
318000–31FFFF
640000–64FFFF
320000–327FFF
650000–65FFFF
328000–32FFFF
660000–66FFFF
330000–337FFF
670000–67FFFF
338000–33FFFF
680000–68FFFF
340000–347FFF
690000–69FFFF
348000–34FFFF
6A0000–6AFFFF
350000–357FFF
6B0000–6BFFFF
358000–35FFFF
6C0000–6CFFFF
360000–367FFF
6D0000–6DFFFF
368000–36FFFF
6E0000–6EFFFF
370000–377FFF
6F0000–6FFFFF
378000–37FFFF
700000–70FFFF
380000–387FFF
710000–71FFFF
388000–38FFFF
720000–72FFFF
390000–397FFF
730000–73FFFF
398000–39FFFF
740000–74FFFF
3A0000–3A7FFF
750000–75FFFF
3A8000–3AFFFF
760000–76FFFF
3B0000–3B7FFF
770000–77FFFF
3B8000–3BFFFF
780000–78FFFF
3C0000–3C7FFF
790000–79FFFF
3C8000–3CFFFF
7A0000–7AFFFF
3D0000–3D7FFF
7B0000–7BFFFF
3D8000–3DFFFF
7C0000–7CFFFF
3E0000–3E7FFF
7D0000–7DFFFF
3E8000–3EFFFF
7E0000–7EFFFF
3F0000–3F7FFF
7F0000–7FFFFF
3F8000–3FFFFF
Bottom Boot Security Sector Addresses
Sector Size
Byte Mode
(bytes)
Word Mode
(words)
256
128
Sector Address
A21-A12
0000000000
Address Range (in hexadecimal)
Byte Mode
(x8)
Word Mode
(x16)
000000–0000FF
000000–00007F
Note:
Address range is A21 : A-1 in byte mode and A21 : A0 in word mode. See “Word/Byte Configuration” section.
(December, 2010, Version 1.1)
13
AMIC Technology, Corp.
A29L640 Series
Protect Verify and/or Security Sector Protect Verify to query
the lock status of the device
In factory-locked device, security sector region is protected
when shipping from factory and the security silicon sector
indicator bit is set to “1”. In customer lockable device,
security sector region is unprotected when shipping from
factory and the security silicon indicator bit is set to “0”.
Factory Locked: Security Sector Programmed and Protected
at the factory
In a factory locked device, the security silicon region is
permanently locked after shipping from factory. The device
will have a 16-byte (8-word) ESN in the security region. In
bottom boot device: 000000h – 000007h. In Top boot device:
3FFFF8 h– 3FFFFFh.
Customer Lockable: Security Sector NOT Programmed or
Protected at the factory
When the security feature is not required, the security region
can act as an extra memory space.
Security silicon sector can also be protected the method
listed below. Note that once the security silicon sector is
protected, there is no way to unprotect the security silicon
sector and the content of it can no longer be altered.
The method is to write a three-cycle command of enter
Security Region, and then follow the sector group protect
algorithm as illustrated in Fig 2-1, except that /RESET pin
may at either VIH or VHH.
After the security silicon is locked and verified, system must
write Exit Security Sector Region, go through a power cycle,
or issue a hardware reset to return the device to read normal
array mode.
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 -I/O0. This mode is primarily
intended for programming equipment to automatically match
a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (9V to 10.5V) on address pin A9. Address pins
A6, A1, and A0 must be as shown in Autoselect Codes (High
Voltage Method) table. In addition, when verifying sector
protection, the sector address must appear on the
appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown in
the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on using
the autoselect mode.
Security Sector Flash Memory Region
The Security Sector region is an extra memory space of 128
words in length. The security sectors can be locked upon
shipping from factory, or it can be locked by customer after
shipping. Customer can issue Security Sector Factory
Table 4. A29L640 Autoselect Codes (High Voltage Method)
Description
Mode
Manufacturer ID: AMIC
Device ID:
CE
OE
WE
A21
to
A12
A11
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
I/O8
to
I/O15
I/O7
to
I/O0
L
L
H
X
X
VID
X
L
X
L
L
X
37h
22h
C9h
L
L
H
X
X
VID
X
L
X
L
H
Word
A29L640
(Top Boot Block)
Byte
X
C9h
Device ID:
Word
22h
CBh
X
CBh
X
(Note 2)
X
01h
(protected)
X
00h
(unprotected)
A29L640
(Bottom Boot Block)
L
L
H
X
X
VID
X
L
X
L
H
Byte
Indicator for Security Sector
L
L
H
X
X
VID
X
L
X
H
H
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.
Note: 1. The autoselect codes may also be accessed in-system via command sequences.
2. Factory locked code: WP protects bottom two address sector: 88h.
WP protects top two address sector: 98h.
Factory unlocked code: WP protects bottom two address sector: 08h.
WP protects top two address sector: 18h.
(December, 2010, Version 1.1)
14
AMIC Technology, Corp.
A29L640 Series
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 5 and 6).
Table 5. Top Boot Sector/Sector Block Addresses for
Protection/Unprotection
Table 6. Bottom Boot Sector/Sector Block Addresses for
Protection/Unprotection
Sector
Group
Sectors
A21-A12
Sector
Group Size
SG 0
SG 1
SG 2
SG 3
SG 4
SG 5
SG 6
SG 7
SG 8
SG 9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SA0-SA3
SA4-SA 7
SA8-SA 11
SA 12-SA 15
SA 16-SA 19
SA 20-SA 23
SA 24-SA 27
SA 28-SA 31
SA 32-SA 35
SA 36-SA 39
SA 40-SA 43
SA 44-SA 47
SA 48-SA 51
SA 52-SA 55
SA 56-SA 59
SA 60-SA 63
SA 64-SA 67
SA 68-SA 71
SA 72-SA 75
SA 76-SA 79
SA 80-SA 83
SA 84-SA 87
SA 88-SA 91
SA 92-SA 95
SA 96-SA 99
SA100-SA103
SA104-SA107
SA108-SA111
SA112-SA115
SA116-SA119
SA120-SA123
00000XXXXX
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
SG31
SA124-SA126
1111100XXX
1111101XXX
1111110XXX
64 Kbytes x 3
SG32
SG33
SG34
SG35
SG36
SG37
SG38
SG39
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
(December, 2010, Version 1.1)
Sector
Group
15
Sectors
A21-A12
Sector
Group Size
SG39
SG38
SG37
SG36
SG35
SG34
SA134-SA131
SA130-SA127
SA126-SA123
SA122-SA119
SA118-SA115
SA114-SA111
11111XXXXX
11110XXXXX
11101XXXXX
11100XXXXX
11011XXXXX
11010XXXXX
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
SG33
SA110-SA107
11001XXXXX
64 Kbytes x 4
SG32
SG31
SG30
SG29
SG28
SG27
SG26
SG25
SG24
SG23
SG22
SG21
SG20
SG19
SG18
SG17
SG16
SG15
SG14
SG13
SG12
SG11
SG10
SA106-SA103
SA102-SA 99
SA 98-SA 95
SA 94-SA 91
SA 90-SA 87
SA 86-SA 83
SA 82-SA 79
SA 78-SA 75
SA 74-SA 71
SA 70-SA 67
SA 66-SA 63
SA 62-SA 59
SA 58-SA 55
SA 54-SA 51
SA 50-SA 47
SA 46-SA 43
SA 42-SA 39
SA 38-SA 35
SA 34-SA 31
SA 30-SA 27
SA 26-SA 23
SA 22-SA 19
SA 18-SA 15
11000XXXXX
10111XXXXX
10110XXXXX
10101XXXXX
10100XXXXX
10011XXXXX
10010XXXXX
10001XXXXX
10000XXXXX
01111XXXXX
01110XXXXX
01101XXXXX
01100XXXXX
01011XXXXX
01010XXXXX
01001XXXXX
01000XXXXX
00111XXXXX
00110XXXXX
00101XXXXX
00100XXXXX
00011XXXXX
00010XXXXX
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 3
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
SG 9
SA 14-SA 11
00001XXXXX
64 Kbytes x 4
SG 8
SA 10-SA 8
0000011XXX
0000010XXX
0000001XXX
64 Kbytes x 3
SG 7
SA 7
0000000111
8 Kbytes
SG 6
SG 5
SG 4
SG 3
SG 2
SG 1
SG 0
SA 6
SA 5
SA 4
SA 3
SA 2
SA 1
SA 0
0000000110
0000000101
0000000100
0000000011
0000000010
0000000001
0000000000
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
AMIC Technology, Corp.
A29L640 Series
Sector Protection/Unprotection
Write Pulse "Glitch" Protection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
Sector protection / unprotection can be implemented via two
methods. The primary method requires VID on the
RESET pin only, and can be implemented either in-system or
via programming equipment. Figure 2 shows the algorithm
and the Sector Protect / Unprotect Timing Diagram illustrates
the timing waveforms for this feature. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle. The alternate
method for protection and unprotection is by software sector
block protect/unprotect command. See Figure 2 for
Command Flow.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
Noise pulses of less than 5ns (typical) on OE , CE or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE =VIL,
CE = VIH or WE = VIH. To initiate a write cycle, CE and
WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the
device does not accept commands on the rising edge of
WE . The internal state machine is automatically reset to
reading array data on the initial power-up.
Temporary Sector Unprotect
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to VID.
During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the RESET pin, all the previously
protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Hardware Data Protection
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device
is powered up to read array data to avoid accidentally writing
data to the array.
(December, 2010, Version 1.1)
16
AMIC Technology, Corp.
A29L640 Series
START
START
555/AA + 2AA/55 + 555/77
RESET = VID
(Note 1)
(Note 1)
Perform Erase or
Program Operations
Perform Erase or
Program Operations
XXX/F0
(Reset Command)
RESET = VIH
Soft-ware Temporary
Sector Unprotect
Completed
(Note 2)
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Notes:
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Figure 1-2. Temporary Sector Unprotect Operation by Software Mode
Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode
(December, 2010, Version 1.1)
17
AMIC Technology, Corp.
A29L640 Series
START
START
Protect all sectors:
The indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
PLSCNT=1
RESET=VID
Wait 1 us
No
Temporary Sector
Unprotect Mode
PLSCNT=1
RESET=VID
Wait 1 us
No
First Write
Cycle=60h?
Yes
Temporary Sector
Unprotect Mode
All sectors
protected?
Sector Protec:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Increment
PLSCNT
No
Yes
Set up sector
address
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
First Write
Cycle=60h?
Reset
PLSCNT=1
Wait 15 ms
Read from
sector address
with A6=0,
A1=1, A0=0
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Increment
PLSCNT
No
PLSCNT
=25?
No
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?
No
Device failed
Protect another
sector?
PLSCNT=
1000?
Yes
No
Yes
No
Remove VID
from RESET
Device failed
Write reset
command
Sector Protect
Algorithm
Set up
next sector
address
Yes
Yes
Sector Protect
complete
Data=00h?
Yes
Last sector
verified?
No
Yes
Remove VID
from RESET
Sector Unprotect
Algorithm
Write reset
Command
Sector Unprotect
complete
Figure 2-1. In-System Sector Protect/Unprotect
Algorithms
(December, 2010, Version 1.1)
18
AMIC Technology, Corp.
A29L640 Series
START
START
PLSCNT=1
555/AA + 2AA/55 +
555/77
Wait 1 us
No
Temporary Sector
Unprotect Mode
PLSCNT=1
Protect all sectors:
The indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
555/AA + 2AA/55 +
555/77
Wait 1 us
No
First Write
Cycle=60h?
Yes
Temporary Sector
Unprotect Mode
All sectors
protected?
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Increment
PLSCNT
No
Yes
Set up sector
address
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
First Write
Cycle=60h?
Reset
PLSCNT=1
Wait 15 ms
Read from
sector address
with A6=0,
A1=1, A0=0
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Increment
PLSCNT
No
PLSCNT
=25?
No
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?**
No
Device failed
Protect another
sector?
PLSCNT=
1000?
Yes
No
Yes
No
Write reset
command
Sector Protect
Algorithm
Set up
next sector
address
Yes
Yes
Device failed
Sector Protect
complete
Data=00h?**
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Write reset
Command
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Access time is 200ns-300ns
Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms
(December, 2010, Version 1.1)
19
AMIC Technology, Corp.
A29L640 Series
ready to read array data. The system can read CFI
information at the addresses given in Table 5-8. In word
mode, the upper address bits (A7-MSB) must be all zeros.
To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the
device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the
addresses given in Table 5-8. The system must write the
reset command to return the device to the autoselect mode.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to
be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and
forward- and backward-compatible for the specified flash
device families. Flash vendors can standardize their existing
interface for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in word
mode (or address AAh in byte mode), any time the device is
Table 7. CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
Data
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
Table 8. System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
1Bh
36h
0027h
1Ch
38h
0036h
Data
Description
VCC Min. (write/erase)
I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt
VCC Max. (write/erase)
I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt
1Dh
3Ah
0000h
Vpp Min. voltage (00h = no Vpp pin present)
1Eh
3Ch
0000h
Vpp Max. voltage (00h = no Vpp pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2N μs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N μs (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
(December, 2010, Version 1.1)
20
AMIC Technology, Corp.
A29L640 Series
Table 9. Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
27h
4Eh
0017h
28h
50h
0002h
29h
52h
0000h
2Ah
54h
0000h
Max. number of byte in multi-byte write = 2N
2Bh
56h
0000h
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
5Ah
0007h
2Eh
5Ch
0000h
Erase Block Region 1 Information
2Fh
5Eh
0020h
(refer to the CFI specification)
30h
60h
0000h
31h
62h
007Eh
32h
64h
0000h
33h
66h
0000h
34h
68h
0001h
35h
6Ah
0000h
36h
6Ch
0000h
37h
6Eh
0000h
38h
40h
0000h
Data
39h
72h
0000h
3Ah
74h
0000h
3BH
76h
0000h
3Ch
78h
0000h
(December, 2010, Version 1.1)
Description
Device Size = 2N byte
Flash Device Interface description
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
21
AMIC Technology, Corp.
A29L640 Series
Table 10. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
44h
88h
0031h
Minor version number, ASCII
45h
8Ah
0000h
Address Sensitive Unlock
Data
Description
Query-unique ASCII string “PRI”
0 = Required, 1 = Not Required
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0004h
48h
90h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29L160 mode
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh
96h
0000h
4Ch
98h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
0090h
ACC (Acceleration) Supply Minimum
00 = Not Supported, D7-D4: Volt, D3-D0: 100mV
4Eh
9Ch
00A5h
4Fh
9Eh
000Xh
ACC (Acceleration) Supply Maximum
00 = Not Supported, D7-D4: Volt, D3-D0: 100mV
Top/Bottom Boot Sector Flag
02 = Bottom Boot Device, 03h = Top Boot Device
(December, 2010, Version 1.1)
22
AMIC Technology, Corp.
A29L640 Series
Command Definitions
Autoselect Command Sequence
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of WE or CE ,
whichever happens later. All data is latched on the rising
edge of WE or CE , whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics"
section.
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code. A read cycle at address XX01h returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in returns 01h if that sector is protected, or 00h if
it is unprotected. Refer to the Sector Address tables for valid
sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended
sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE pin. Programming is a
four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are
written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the
programmed cell margin. Table 9 shows the address and data
requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the
program operation by using I/O7, I/O6, or RY/ BY . See “White
Operation Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data
integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5 to
“1”, or cause the Data Polling algorithm to indicate the
operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
(December, 2010, Version 1.1)
23
AMIC Technology, Corp.
A29L640 Series
00h. Addresses are don’t care for both cycle. The device
returns to reading array data.
Figure 3 illustrates the algorithm for the program operation.
See the Erase/Program Operations in “AC Characteristics” for
parameters, and to Program Operation Timings for timing
diagrams.
START
Write Program
Command
Sequence
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 4 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Data Poll
from System
Embedded
Program
algorithm in
progress
Verify Data ?
No
Yes
Increment Address
No
Last Address ?
Yes
Programming
Completed
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase timeout of 50μs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50μs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector
erase commands can be assumed to be less than 50μs, the
system need not monitor I/O3. Any command other than
Sector Erase or Erase Suspend during the time-out period
resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 3. Program Operation
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 9
shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The first
cycle must contain the data 90h; the second cycle the data
(December, 2010, Version 1.1)
24
AMIC Technology, Corp.
A29L640 Series
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
WE pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
4 illustrates the algorithm for the erase operation. Refer to
the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes
of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
START
Write Erase
Command
Sequence
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50μs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20μs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O7
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within nonsuspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
(December, 2010, Version 1.1)
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O 3 : Sector Erase Timer" for more information.
Figure 4. Erase Operation
25
AMIC Technology, Corp.
A29L640 Series
Table 11. A29L640 Command Definitions
Cycles
Command
Sequence
(Note 1)
Read (Note 6)
1
Reset (Note 7)
Autoselect (Note 8)
Manufacturer ID
Device ID,
Top Boot Block
Security Sector
Factory Protect
Verify
Sector Protect Verify
(Note 9)
First
Addr Data
Second
Addr Data
Third
Fourth
Addr Data Addr Data
2AA
555
2AA
555
555
AAA
555
AAA
RA
RD
1
Word
4
Byte
Word
4
Byte
XXX
555
AAA
555
AAA
F0
Word
555
AA
2AA
55
555
90
AAA
AA
555
55
AAA
90
AA
AA
55
55
90
X00
90
X01
X02
4
Byte
Word
555
4
Byte
Word
1
Byte
Command Temporary
Sector Unprotect (Note 10)
Word
Program
Byte
4
Byte
Word
3
Byte
Byte
2AA
AA
AAA
CFI Query (Note 11)
Unlock Bypass
Bus Cycles (Notes 2 - 5)
3
55
AA
555
AAA
555
AAA
555
AAA
555
55
555
AAA
AA
AA
AA
2AA
555
2AA
555
2AA
555
55
55
55
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 13)
Chip Erase
Word
Byte
Sector Erase
Word
Byte
Word
Enter Security Sector
Region enable
Byte
Word
Exit Security Sector
Byte
2
90
AA
AA
AA
AA
XXX
2AA
555
2AA
555
2AA
555
2AA
555
00
3
3
4
4
XXX
555
AAA
555
AAA
555
AAA
555
AAA
Erase Suspend (Note 14)
1
XXX
B0
Erase Resume (Note 15)
1
XXX
30
6
37
22F6
F6
98/18(T)
X03
88/08(B)
98/18(T)
X06
88/08(B)
(SA)
XX00
X02
XX01
(SA)
X04
00
PA
PD
01
98
Unlock Bypass Program (Note 12)
6
90
Fifth
Sixth
Addr Data Addr Data
AA
AA
55
55
55
55
55
55
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
77
A0
20
80
80
88
88
90
90
555
AAA
555
AAA
XXX
XXX
AA
AA
2AA
555
2AA
555
55
555
AAA
10
55
SA
30
00
00
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21- A12 select a unique sector.
(December, 2010, Version 1.1)
26
AMIC Technology, Corp.
A29L640 Series
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD.
5. Address bits A21 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
10. Once a reset command is applied, software temporary unprotect is exit to return to read array data. But under erase
suspend condition, this command is still effective even a reset command has been applied. The reset command which can
deactivate the software temporary unprotect command is useful only after the erase command is complete.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
15. The Erase Resume command is valid only during the Erase Suspend mode.
(December, 2010, Version 1.1)
27
AMIC Technology, Corp.
A29L640 Series
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/ BY are provided in
the A29L640 to determine the status of a write operation.
Table 10 and the following subsections describe the
functions of these status bits. I/O7, I/O6 and RY/ BY each
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
START
Read I/O7-I/O0
Address = VA
I/O7: Data Polling
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data Polling is
Yes
I/O7 = Data ?
valid after the rising edge of the final WE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 2μs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data Polling produces a "1" on I/O7.This is analogous to the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100μs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable
( OE ) is asserted low. The Data Polling Timings (During
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 10 shows the outputs for Data
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
Yes
I/O7 = Data ?
No
FAIL
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Polling on I/O7. Figure 5 shows the Data Polling algorithm.
(December, 2010, Version 1.1)
PASS
Figure 5. Data Polling Algorithm
28
AMIC Technology, Corp.
A29L640 Series
RY/ BY : Read/ Busy
I/O2: Toggle Bit II
The RY/ BY is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or
complete. The RY/ BY status is valid after the rising edge of
the final WE pulse in the command sequence. Since RY/ BY
is an open-drain output, several RY/ BY pins can be tied
together in parallel with a pull-up resistor to VCC (The RY/ BY
pin is not available on the 44-pin SOP package).
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 10 shows the outputs for RY/ BY . Refer to “ RESET
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final WE pulse in the command sequence (prior to the
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use either OE or CE to control the read
cycles.) When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100μs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the device
enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 : Data
Polling").
If a program address falls within a protected sector, I/O6
toggles for approximately 2μs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle Bit
II".
(December, 2010, Version 1.1)
29
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE pulse in the command sequence.
I/O2 toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
use either OE or CE to control the read cycles.) But I/O2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 10 to compare outputs for I/O2 and I/O6.
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The I/O2
vs. I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
Reading Toggle Bits I/O6, I/O2
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7 - I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
AMIC Technology, Corp.
A29L640 Series
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O5
produces a "1."
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
START
Read I/O7-I/O0
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50μs. See also the "Sector Erase Command
Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Data Polling) or I/O6
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 10 shows the outputs for I/O3.
Read I/O7-I/O0
Toggle Bit
= Toggle ?
(Note 1)
No
Yes
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Twice
Toggle Bit
= Toggle ?
(Notes 1,2)
No
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O5
changes to "1". See text.
Figure 6. Toggle Bit Algorithm
(December, 2010, Version 1.1)
30
AMIC Technology, Corp.
A29L640 Series
Table 12. Write Operation Status
I/O7
Operation
I/O6
(Note 1)
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspend Sector
Erase-Suspend-Program
I/O5
I/O3
(Note 2)
I/O2
RY/ BY
(Note 1)
I/O7
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
I/O7
Toggle
0
N/A
N/A
0
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
(December, 2010, Version 1.1)
20ns
31
AMIC Technology, Corp.
A29L640 Series
DC Characteristics
CMOS Compatible
Parameter
Parameter Description
Symbol
ILI
Input Load Current
ILIT
ILO
A9 Input Load Current
Output Leakage Current
Test Description
Unit
±1.0
35
μA
VCC = VCC Max, A9 =12.5V
VOUT = VSS to VCC. VCC = VCC Max
±1.0
μA
VIN = VSS to VCC. VCC = VCC Max
ICC2
ICC3
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
VCC Standby Current (Note 2)
10
16
1 MHz
2
4
CE = VIL, OE = VIH
5 MHz
10
16
Word Mode
1 MHz
2
4
CE = VIL, OE =VIH
20
30
Ma
CE = RESET = VCC ± 0.3V
1
5
μA
RESET = VSS ± 0.3V
1
5
μA
VIH = VCC ± 0.3V; VIL = VSS ± 0.3V
1
5
μA
VIL
VCC Standby Current During Reset
(Note 2)
Automatic Sleep Mode
(Note 2, 4, 5)
Input Low Level
VIH
Input High Level
VHH
Voltage for WP /ACC Sector Protect/ VCC=3.0V ± 10%
Unprotect and Program Acceleration
Voltage for Autoselect and
VCC = 3.0 V ± 10%
Temporary Unprotect Sector
Output Low Voltage
IOL = 4.0mA, VCC = VCC Min
ICC4
ICC5
VID
VOL
VOH1
VOH2
Output High Voltage
μA
5 MHz
Byte Mode
ICC1
Typ.
Max.
CE = VIL, OE = VIH
VCC Active Read Current
(Notes 1, 2)
Min.
IOH = -2.0 mA, VCC = VCC Min
IOH = -100 μA, VCC = VCC Min
mA
-0.5
0.8
V
0.7 x VCC
VCC + 0.3
V
9
10.5
V
9
10.5
V
0.45
V
0.85 x VCC
VCC - 0.4
V
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE at VIH. Typical VCC is 3.3V.
2. Maximum ICC specifications are tested with VCC = VCC max. If WP is connected to ground, the ICC3 typical spec. would be
5uA.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current
is 1μA.
5. Not 100% tested.
(December, 2010, Version 1.1)
32
AMIC Technology, Corp.
A29L640 Series
DC Characteristics (continued)
Zero Power Flash
Supply Current in mA
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1MHz
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
3.6V
8
Supply Current in mA
3.0V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note : T = 25 ° C
Typical ICC1 vs. Frequency
(December, 2010, Version 1.1)
33
AMIC Technology, Corp.
A29L640 Series
AC Characteristics
Read Only Operations
Parameter Symbols
Description
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
Speed
Test Setup
Unit
-70
Min.
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
tOEH
Output Enable Hold
Time (Note 1)
70
ns
70
ns
CE = VIL
OE = VIL
Max.
OE = VIL
Max.
70
ns
Max.
30
ns
0
0
ns
10
10
ns
Max.
16
ns
16
ns
Read
Toggle and
Data Polling
tEHQZ
tHZ
Chip Enable to Output High Z
(Notes 1)
tGHQZ
tDF
Output Enable to Output High Z
(Notes 1)
tAXQX
tOH
Output Hold Time from Addresses, CE or
OE , Whichever Occurs First (Note 1)
0
Min.
ns
Notes:
1. Not 100% tested.
2. See Test Conditions and Test Setup for test specifications.
Timing Waveforms for Read Only Operation
tRC
Addresses
Addresses Stable
tACC
CE
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
Output
Output Valid
High-Z
RESET
0V
RY/BY
(December, 2010, Version 1.1)
34
AMIC Technology, Corp.
A29L640 Series
AC Characteristics
Hardware Reset ( RESET )
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
μs
tREADY
RESET Pin Low (Not During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET Pulse Width
Min
500
ns
tRH
RESET High Time Before Read (See Note)
Min
50
ns
tRB
RY/ BY Recovery Time
Min
0
ns
tRPD
RESET Low to Standby Mode
Min
20
μs
Note: Not 100% tested.
RESET Timings
RY/BY
CE, OE
tRH
RESET
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
~
~ ~
~
tReady
RY/BY
tRB
CE, OE
~
~
RESET
tRP
(December, 2010, Version 1.1)
35
AMIC Technology, Corp.
A29L640 Series
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET Setup Time for Temporary Sector
Unprotect
Min
4
μs
tVHH
VHH Rise and Fall Time (See Note)
Min
250
ns
tRRB
RESET Hold Time from RY/ BY High for
Temporary Sector/Sector Block Unprotect
Min
4
μs
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
VID
~
~
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
RESET
tVIDR
tVIDR
Program or Erase Command Sequence
CE
~
~
WE
~ ~
~
~
tRSP
RY/BY
tRRB
Accelerated Program Timing Diagram
VCC
WP/ACC
~
~
VHH
VIL or VIH
VIL or VIH
tVHH
tVHH
AC Characteristics
Word/Byte Configuration ( BYTE )
Parameter
JEDEC
All Speed Options
Description
Std
Unit
-70
CE to BYTE Switching Low or High
Max
5
ns
tFLQZ
BYTE Switching Low to Output High-Z
Max
25
ns
tHQV
BYTE Switching High to Output Active
Min
70
ns
tELFL/tELFH
(December, 2010, Version 1.1)
36
AMIC Technology, Corp.
A29L640 Series
BYTE Timings for Read Operations
CE
OE
BYTE
tELFL
BYTE
Switching
from word to
byte mode
Data Output
(I/O0-I/O14)
I/O0-I/O14
Data Output
(I/O0-I/O7)
I/O15
Output
I/O15 (A-1)
Address Input
tFLQZ
tELFH
BYTE
BYTE
Switching
from byte to
word mode
I/O0-I/O14
Data Output
(I/O0-I/O7)
I/O15 (A-1)
Address Input
Data Output
(I/O0-I/O14)
I/O15
Output
tFHQV
BYTE Timings for Write Operations
CE
The falling edge of the last WE signal
WE
BYTE
tSET
(tAS)
tHOLD(tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
(December, 2010, Version 1.1)
37
AMIC Technology, Corp.
A29L640 Series
AC Characteristics
Erase and Program Operations
Parameter
Speed
Description
Unit
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
70
ns
tAVWL
tAS
Address Setup Time
Min.
0
ns
tWLAX
tAH
Address Hold Time
Min.
40
ns
tDVWH
tDS
Data Setup Time
Min.
40
ns
tWHDX
tDH
Data Hold Time
Min.
0
ns
tOES
Output Enable Setup Time
Min.
0
ns
Read Recover Time Before Write
Min.
0
ns
tGHWL
tGHWL
-70
( OE high to WE low)
tELWL
tCS
CE Setup Time
Min.
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
ns
tWLWH
tWP
Write Pulse Width
Min.
30
ns
tWHWL
tWPH
Write Pulse Width High
Min.
30
ns
Byte
Typ.
6
tWHWH1
tWHWH1
Word
Typ.
9
Sector Erase Operation (Note 2)
Typ.
0.7
sec
tvcs
VCC Set Up Time (Note 1)
Min.
50
μs
tRB
Recovery Time from RY/ BY (Note 1)
Min
0
ns
Program/Erase Valid to RY/ BY Delay (Note 1)
Min
90
ns
tWHWH2
tWHWH2
tBUSY
Byte Programming Operation
(Note 2)
μs
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(December, 2010, Version 1.1)
38
AMIC Technology, Corp.
A29L640 Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
PA
555h
PA
tAH
PA
~
~ ~
~
Addresses
tAS
~
~
tWC
Read Status Data (last two cycles)
CE
~
~
tCH
OE
tWP
~
~
tWHWH1
WE
tCS
tWPH
A0h
Data
tDH
PD
~
~
tDS
Status
DOUT
tRB
tBUSY
~
~ ~
~
RY/BY
tVCS
VCC
Note :
1. PA = program addrss, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
(December, 2010, Version 1.1)
39
AMIC Technology, Corp.
A29L640 Series
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
tAS
~
~
tWC
SA
2AAh
VA
555h for chip erase
tAH
VA
~
~ ~
~
Addresses
Read Status Data
~
~
CE
OE
tCH
~
~
tWP
WE
tWPH
tWHWH2
tCS
Data
tDH
55h
30h
~
~
tDS
10h for chip erase
tBUSY
In
Progress
Complete
tRB
~
~
RY/BY
~
~
tVCS
VCC
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustratin shows device in word mode.
(December, 2010, Version 1.1)
40
AMIC Technology, Corp.
A29L640 Series
Timing Waveforms for Data Polling (During Embedded Algorithms)
~
~
tRC
Addresses
VA
~
~ ~
~
tACC
CE
VA
VA
tCE
tCH
~
~
tOE
OE
tDF
~
~
tOEH
WE
tOH
Status Data
~
~
Complement
Complement
True
Valid Data
~
~
High-Z
I/O7
Status Data
True
Valid Data
High-Z
I/O0 - I/O6
High-Z
tBUSY
~
~
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
(December, 2010, Version 1.1)
41
AMIC Technology, Corp.
A29L640 Series
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
~
~
tRC
Addresses
VA
tACC
CE
VA
VA
~
~ ~
~
VA
tCE
tCH
tOE
~
~
OE
tDF
~
~
tOEH
WE
I/O6 , I/O2
High-Z
tBUSY
Valid Status
Valid Status
(first read)
(second read)
~
~
tOH
Valid Status
Valid Data
(stop togging)
~
~
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
(December, 2010, Version 1.1)
42
AMIC Technology, Corp.
A29L640 Series
Timing Waveforms for Sector Protect/Unprotect
VID
VIH
~
~
RESET
SA, A6,
A1, A0
Valid*
Valid*
~
~
Valid*
Verify
~
~
Sector Protect/Unprotect
60h
60h
40h
Status
~
~
Data
Sector Protect:150us
Sector Unprotect:15ms
1us
CE
WE
OE
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0
Timing Waveforms for I/O2 vs. I/O6
~
~
Erase
Complete
~
~
~
~
Erase
~
~
~
~
~
~
Erase Suspend
Read
~
~
~
~
~
~
I/O2
~
~
I/O6
Erase
Suspend
Program
Erase Suspend
Read
~
~
Erase
Erase
Resume
~
~
WE
Enter Erase
Suspend Program
~
~
~
~
Erase
Suspend
~
~
Enter
Embedded
Erasing
I/O2 and I/O6 toggle with OE and CE
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.
(December, 2010, Version 1.1)
43
AMIC Technology, Corp.
A29L640 Series
Timing Waveforms for Alternate CE Controlled Write Operation
PA for program
SA for sector erase
555 for chip erase
Data Polling
~
~
555 for program
2AA for erase
PA
~
~
Addresses
tAS
tWH
tAH
~
~
tWC
~
~
WE
OE
tWHWH1 or 2
~
~
tCP
tBUSY
tCPH
CE
tWS
tDS
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
I/O7
DOUT
~
~
~
~
tDH
RESET
~
~
RY/BY
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Typ. (Note 1)
Unit
Sector Erase Time
0.7
sec
Chip Erase Time
45
sec
Byte Programming Time
6
μs
Word Programming Time
9
μs
Comments
Excludes 00h programming prior to erasure
Chip Programming Time
Byte Mode
45
sec
(Note 2)
Word Mode
40
sec
Excludes system-level overhead (Note 4)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern..
2. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 9
for further information on command definitions.
5. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
(December, 2010, Version 1.1)
44
AMIC Technology, Corp.
A29L640 Series
Latch-up Characteristics
Description
Min.
Max.
-1.0V
VCC+1.0V
-100 mA
+100 mA
-1.0V
12.5V
Input Voltage with respect to VSS on all I/O pins
VCC Current
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE and RESET )
Includes all pins except VCC. Test conditions: VCC = 3.3V, one pin at time.
SOP/TSOP/TFBGA Pin Capacitance
Parameter Symbol
CIN
Parameter Description
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
VIN=0
VOUT=0
VIN=0
Typ.
Max.
SOP/TSOP
6
7.5
pF
TFBGA
4.2
5
pF
SOP/TSOP
8.5
12
pF
TFBGA
5.4
6.5
pF
SOP/TSOP
7.5
9
pF
TFBGA
3.9
4.7
pF
Unit
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
(December, 2010, Version 1.1)
45
AMIC Technology, Corp.
A29L640 Series
Test Conditions
Test Specifications
Test Condition
-70
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
0.0 – VCC
V
Input timing measurement reference levels
0.5VCC
V
Output timing measurement reference levels
0.5VCC
V
Input Pulse Levels
Test Setup
3.0V
2.7 K Ω
Device
Under
Test
CL
6.2 K Ω
Diodes = IN3064 or Equivalent
Input Waveforms and Measurement Levels
VCC
Input
0.5VCC
Measurement Level
0.5VCC
Output
0.0V
(December, 2010, Version 1.1)
46
AMIC Technology, Corp.
A29L640 Series
Ordering Information
Top Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (μA)
A29L640TM-70F
Package
44 Pin Pb-Free SOP
70
A29L640TM-70UF
10
20
0.5
44 Pin Pb-Free SOP
A29L640TM-70IF
44 Pin Pb-Free SOP
A29L640TV-70F
48 Pin Pb-Free TSOP
70
A29L640TV-70UF
10
20
0.5
48 Pin Pb-Free TSOP
A29L640TV-70IF
48 Pin Pb-Free TSOP
A29L640TG-70F
48 ball Pb-Free TFBGA
70
A29L640TG-70UF
10
20
0.5
48 ball Pb-Free TFBGA
A29L640TG-70IF
48 ball Pb-Free TFBGA
Note: -U is for industrial operating temperature range: -40°C to +85°C
-I is for industrial operating temperature range: -25°C to +85°C
Bottom Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (μA)
A29L640UM-70F
A29L640UM-70UF
Package
44 Pin Pb-Free SOP
70
10
20
0.5
44 Pin Pb-Free SOP
A29L640UM-70IF
44 Pin Pb-Free SOP
A29L640UV-70F
48 Pin Pb-Free TSOP
A29L640UV-70UF
70
10
20
0.5
48 Pin Pb-Free TSOP
A29L640UV-70IF
48 Pin Pb-Free TSOP
A29L640UG-70F
48 ball Pb-Free TFBGA
A29L640UG-70UF
70
10
20
A29L640UG-70IF
0.5
48 ball Pb-Free TFBGA
48 ball Pb-Free TFBGA
Note: -U is for industrial operating temperature range: -40°C to +85°C
-I is for industrial operating temperature range: -25°C to +85°C
(December, 2010, Version 1.1)
47
AMIC Technology, Corp.
A29L640 Series
Package Information
SOP 44L Outline Dimensions
unit: inches/mm
23
Gauge Plane
HE
E
44
θ
L
0.010"
1
b 22
Detail F
e
y
A1
D
S
A
A2
C
D
L1
Seating Plane
See Detail F
Symbol
A
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
-
-
0.118
-
-
3.00
A1
0.004
-
-
0.10
-
-
A2
0.103
0.106
0.109
2.62
2.69
2.77
b
0.013
0.016
0.020
0.33
0.40
0.50
C
0.007
0.008
0.010
0.18
0.20
0.25
D
-
1.122
1.130
-
28.50
28.70
E
0.490
0.496
0.500
12.45
12.60
12.70
e
-
0.050
-
-
1.27
-
HE
0.620
0.631
0.643
15.75
16.03
16.33
L
0.024
0.032
0.040
0.61
0.80
1.02
L1
-
0.0675
-
-
1.71
-
S
-
-
0.045
-
-
1.14
y
-
-
0.004
-
-
0.10
θ
0°
-
8°
0°
-
8°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(December, 2010, Version 1.1)
48
AMIC Technology, Corp.
A29L640 Series
Package Information
TSOP 48L (Type I) Outline Dimensions
unit: inches/mm
1
48
24
25
y
D1
A1
A2 A
D
0.25
c
S
e
E
b
D
Detail "A"
L
θ
Detail "A"
Symbol
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.042
0.94
1.00
1.06
b
0.007
0.009
0.011
0.18
0.22
0.27
c
0.004
-
0.008
0.12
-
0.20
D
0.779
0.787
0.795
19.80
20.00
20.20
D1
0.720
0.724
0.728
18.30
18.40
18.50
E
-
0.472
0.476
-
12.00
12.10
e
L
0.020 BASIC
0.016
S
0.020
0.50 BASIC
0.024
0.40
0.011 Typ.
0.50
0.60
0.28 Typ.
y
-
-
0.004
θ
0°
-
8°
0°
-
0.10
8°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(December, 2010, Version 1.1)
49
AMIC Technology, Corp.
A29L640 Series
Package Information
48LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
(48TFBGA)
BOTTOM VIEW
TOP VIEW
b
3
2
1
1
H
H
G
G
F
F
E
E
D
D
C
C
B
B
A
A
2
3
4
5
6
E
4
E1
5
e
6
e
D1
Ball*A1 CORNER
D
A
SIDE VIEW
SEATING PLANE
A1
C
0.10 C
Symbol
A
A1
b
D
D1
e
E
E1
(December, 2010, Version 1.1)
Dimensions in mm
Min.
0.20
0.30
5.90
Nom.
0.25
6.00
4.00 BSC
0.80
7.90
8.00
5.60 BSC
50
Max.
1.20
0.30
0.40
6.10
8.10
AMIC Technology, Corp.
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