datasheet for VL41B5763F

datasheet for VL41B5763F

Product Specifications

PART NO.:

VL41B5763F-K0/K9/F8/E7S REV: 1.0

General Information

2GB 256Mx72 DDR3 SDRAM ULP ECC UNBUFFERED SO-UDIMM 204-PIN

Description

The VL41B5763F is a 256Mx72 DDR3 SDRAM high density SO-UDIMM. This memory module is single rank, consists of nine CMOS 256Mx8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM in an 8-pin MLF package. This module is a 204-pin small-outline dual in-line memory module and is intended for mounting into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board for each

DDR3 SDRAM.

204-pin, unbuffered small-outline dual in-line memory module (SO-UDIMM)

Supports ECC error detection and correction

Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, PC3-6400

VDD = VDDQ = 1.5V +/-0.075V

JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 compatible )

VDDSPD = 3.0V to 3.6V

Eight internal component banks for concurrent operation

8-bit architecture

Bi-directional differential data-strobe

Nominal and dynamic on-die termination (ODT)

ZQ calibration support

Programmable CAS# latency:

11 (DDR3-1600), 9 (DDR3-1333), 7 (DDR3-1066), 6 (DDR3-800)

Programmable burst; length (8)

Average refresh period 7.8 us

• reset

Fly-by

On board terminated command, address, and control bus

Serial presence detect (SPD) with EEPROM

Lead-free, RoHS compliant

Gold edge contacts

JEDEC

PCB:

Operating temperature (T

OPER

): - Commercial (0 o

C <= Tc <= 95 o

C)

- Industrial (-40 o

C <= Tc <= 95 o

C)

Notes: Double refresh rate is required when 85 o

C < T

OPER

< 95 o

C.

T

OPER

is DRAM case temperature (Tc).

Order Information:

VL41B5763F K0 S X -

X

OPERATING TEMPERATURE

None: Commercial

S1: Industrial screening

DRAM DIE (Option)

DRAM MANUFACTURER

S - SAMSUNG

MODULE SPEED

K0: PC3-12800 @ CL11

K9: PC3-10600 @ CL9

F8: PC3-8500 @ CL7

E7: PC3-6400 @ CL6

VL: Lead-free/RoHS

Pin Name

A12/BC#

DQS0#~DQS8#

CB0~CB7

ODT0

RAS#

CAS#

RESET#

VSS Ground

SDA

SCL

VREFCA

VREFDQ

VDDSPD

Function

Address Input/ Burst Chop

Data Strobes Complement

Data Check Bits I/O

On-die Termination Control

Row Address Strobes

Column Address Strobes

Register and SDRAM Control

SPD Data Input/Output

SPD Clock Input

Reference Voltage for CA

Reference Voltage for DQ

SPD Voltage Supply

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Product Specifications

PART NO.:

VL41B5763F-K0/K9/F8/E7S REV: 1.0

Pin Configuration

204-PIN DDR3 SO-UDIMM FRONT 204-PIN DDR3 SO-UDIMM BACK

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

1 VREFDQ 53 VSS 105 A1 157 DM5 2 VSS 54 DQ28 106 A2 158 VSS

7

9

DQ1

VSS

59

61

DM3

VSS

107 A0 159 4 DQ4 56

6 DQ5 58 VSS 110 VDD 162 DQ47

111

113

CK0

CK0#

163

165

VSS

DQ48

8

10

VSS

DQS0#

60

62

DQS3#

DQS3

112

114

CK1

CK1#

164

166

VSS

DQ52

119

12 DQS0 64 VSS 116 VDD 168 DQ53

A10/AP 14 VSS 66 170 VSS

BA0 171 DQS6# 16 DQ6 68 DQ31 120 CS2# * 172 DM6 15 DQ3 67 VSS

17 VSS 69 CB0 121 WE# 173 DQS6 18 DQ7 70 VSS 122 RAS# 174 DQ54

VDD DQ55

23 VSS

25 DQS1#

75 DQS8# 127

77 DQS8 129

CS0#

CS1# *

177 22 DQ12 74 CB5 126 ODT0 178 VSS

179

181

DQ51

VSS

27 DQS1 79 VSS 131 VDD 183 DQ56

29 VSS 81 CB2 133 DQ32 185 DQ57

24

26

DQ13

VSS

76

78

DM8

VSS

128

130

ODT1 *

A13

180

182

DQ60

DQ61

28 DM1 80 CB6 132 VDD 184 VSS

30 RESET# 82 CB7 134 DQ36 186 DQS7#

35 VSS 87 CKE0 139 DQS4# 191 DQ58

37 DQ16 89 CKE1 * 141 DQS4 193 DQ59

39 DQ17 91 BA2 143 VSS 195 VSS

34 DQ14 86 VDD 138 VSS 190 VSS

36 DQ15 88 A15 * 140 DM4 192 DQ62

38 VSS 90 A14 142 DQ38 194 DQ63

40 DQ20 92 A9 144 DQ39 196 VSS

DQ34 42 DQ21 94 VDD 146 VSS 198

DQ35 199 VDDSPD 44 DM2 96 A11 148 DQ44 200 SDA 43 DQS2# 95 A12/BC# 147

45 DQS2 97 A8 149 VSS 201 SA1 46 VSS 98 A7 150 DQ45 202 SCL

49 DQ18 101 VDD 153 DQ41

51 DQ19 103 A3 155 VSS

*: These pins are not used in this module.

50

52

DQ23

VSS

102

104

VDD

A4

154 DQS5#

156 DQS5

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PART NO.:

Function Block Diagram

Product Specifications

VL41B5763F-K0/K9/F8/E7S REV: 1.0

A0-A14

BA0-BA2

RAS#

CAS#

WE#

CKE0

ODT0

RESET#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DQS3#

DM3

DQS1

DQS1#

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS2#

DM2

CS0#

DQS0

DQS0#

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS8

DQS8#

DM8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS#

D0

DQS#

ZQ

DQS DQS#

D1

CS# DQS

D2

ZQ

DQS#

ZQ

CS# DQS DQS#

D3

ZQ

Vss

Vss

Vss

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D8

ZQ

Vss

A0-A14: SDRAMs D0-D8

BA0-BA2: SDRAMs D0-D8

RAS#: SDRAMs D0-D8

CAS#: SDRAMs D0-D8

WE#: SDRAMs D0-D8

CKE0: SDRAMs D0-D8

ODT0: SDRAMs D0-D8

RESET#: SDRAMs D0-D8

Notes:

1. Unless otherw ise noted, resistor values are 15 ohms +/-5%

2. ZQ resistors are 240 ohms +/-1%

DQS4

DQS4#

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DQS5#

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DQS6#

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DQS7#

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D4

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D5

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D6

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D7

ZQ

Vss

CK0

CK0#

3.3pF

D0-D8

Command, address, control, and clock line terminations

A0-A14, BA0-BA2

RAS#, CAS#, WE#,

CS0#, CKE0, ODT0

DDR3

SDRAM

39 ohm +/-5%

VTT

CK0

CK0#

DDR3

SDRAM

36 ohm +/-5%

0.1uF

VDD

Serial PD

SCL

Vss

WP

A0 A1 A2

SA0 SA1

Vss

SDA

VDDSPD

VDD

VTT

VREFCA

VREFDQ

VSS

Serial PD

D0-D8

D0-D8

D0-D8

D0-D8

D0-D8

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Product Specifications

PART NO.:

VL41B5763F-K0/K9/F8/E7S

Absolute Maximum Ratings

Symbol Parameter

VDD Voltage on VDD pin relative to VSS

VDDQ Voltage on VDDQ pin relative to VSS

VIN, VOUT Voltage on any pin relative to VSS

-0.4

-0.4

-0.4

-55

REV: 1.0

1.975

1.975

1.975

100

V

V

V

0

C

IL

Input leakage current; Any input 0V<VIN<VDD;

VREF input 0V<VIN<0.95V;

Other pins not under test = 0V

Address, RAS#,

CAS#, WE#, BA

CS#, CKE, ODT,

CK, CK#

IOZ

IVREF

Output leakage current;

0V<VOUT<VDDQ; DQs and ODT are disabled

DQ, DQS, DQS#

VREF supply leakage current; VREF = Valid VREF level

-5

-9

5

9 uA uA

DC Operating Conditions

Symbol Parameter Min Max

1.425 1.5 1.575 V 1,2

VDDQ I/O Supply Voltage

VREFDQ (DC) I/O reference voltage DQ bus

VREFCA (DC) Input reference voltage CMD/ADD bus

1.425

0.49 x VDD

0.49 x VDD

1.5

0.5 x VDD

0.5 x VDD

1.575

0.51 x VDD

0.51 x VDD

V

V

V

1,2

3,4

3,4

VTT Termination Reference Voltage -0.483 x VDDQ 0.5 x VDDQ +0.517 x VDDQ V

Notes:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD

4. For reference: approximate VDD/2 +/-15mV.

5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce timing margins.

5

Operating Temperature Condition

Symbol Parameter

T

OPER

Operating

Commercial

Industrial

Rating Units Notes

0 to 95

-40 to +95

0

C 1,2

Notes:

1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51-2.

2. At -40 to +85

85 o o

C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when

C < TOPER <= 95 o

C.

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Product Specifications

PART NO.:

VL41B5763F-K0/K9/F8/E7S REV: 1.0

Input DC Logic Level

All voltages referenced to VSS

Symbol Parameter Min Unit

Command and Address

VIHCA(DC)

VILCA(DC)

Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)

Input Low (Logic 0) Voltage

(DDR3-800/1066/1333/1600)

DQ and DM

VREF + 0.100

VSS

VDD

VREF - 0.100

V

V

VIHDQ(DC) VREF + 0.100 VDD V

Input High (Logic 1) Voltage

(DDR3-800/1066/1333/1600)

VILDQ(DC) VSS VREF - 0.100 V Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)

Input AC Logic Level

All voltages referenced to VSS

Symbol Parameter Min Unit

Command and Address

VIHCA(AC)

VILCA(AC)

DQ and DM

Input High (Logic 1) Voltage

(DDR3-800/1066/1333/1600)

Input Low (Logic 0) Voltage

(DDR3-800/1066/1333/1600)

VREF + 0.175

-

-

VREF - 0.175

V

V

VIHDQ(AC) Input High (Logic 1) Voltage (

DDR3-800/1066)

VREF + 0.175 - V

VILDQ(AC)

VIHDQ(AC)

Input Low (Logic 0) Voltage (DDR3-800/1066)

Input High (Logic 1) Voltage (DDR3-1333/1600)

-

VREF + 0.150

VREF - 0.175

-

V

V

VILDQ(AC) - VREF - 0.150 V

Input Low (Logic 0) Voltage

(DDR3-1333/1600)

Input/Output Capacitance

TA=25

0

C, f=100MHz

Parameter Symbol

K0 K9 F8 E7

(DDR3-1600) (DDR3-1333)

(DDR3-1066)

(DDR3-800)

Min Max Min Max Min Max Min Max

Unit

Input capacitance (A0~A14, BA0~BA2, RAS#,

CAS#, WE#)

CIN1 10.75 15.7 10.75 15.7 10.75 17.5 10.75 17.5 pF

CIN2 10.75 15.7 10.75 15.7 10.75 17.5 10.75 17.5 pF

Input capacitance (CK0, CK0#) CIN3

Input/Output capacitance (DQ, DQS, DQS#, CB, DM) CIO

11.2

5.5

16.6 11.2 16.6 11.2

6.3 5.5 6.5 5.5

18.4 11.2 18.4

6.7 5.5 7 pF pF

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Product Specifications

PART NO.:

VL41B5763F-K0/K9/F8/E7S REV: 1.0

IDD Specification

Condition Symbol

(DDR3-1600) (DDR3-1333) (DDR3-1066)

E7

(DDR3-800)

Operating one bank active-precharge current;

tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

Precharge power-down current;

All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING.

Precharge standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is

HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING.

Precharge quiet standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is

HIGH; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING.

Active power-down current;

All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING.

Active standby current;

All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING.

Operating burst read current;

All device banks open; Continuous burst reads; IOUT = 0mA;

BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS

MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as IDD4W.

Operating burst write current;

All device banks open; Continuous burst writes; BL = 8; CL =

CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Burst refresh current;

tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Self refresh current;

Unit

IDD5** 1080 1035 990 990 mA

CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING.

Operating bank interleave read current;

All bank interleaving reads; IOUT = 0mA; BL = 8; CL =

CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is

HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R.

IDD7* 1260 1215 945

Note: IDD specification is based on Samsung D-die components.

*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.

**: Value calculated reflects all module ranks in this operating condition.

945 mA

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Product Specifications

PART NO.:

VL41B5763F-K0/K9/F8/E7S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 - 8 - ns

Average Clock Period tCK(avg)

Clock Period

Average high pulse width

Average low pulse width

Clock Period Jitter tCK(abs) tCH(avg) tCL(avg) tJIT(per)

1.25 <1.50 1.5 <1.875 1.875 <2.5 2.5 3.3 tCK(avg)min

+

tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+ tCK(avg)min

+

tJIT(per)max tJIT(per)min tCK(avg)max

+

tJIT(per)max

0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 ns ns tCK(avg)

0.47

-70

0.53

70

0.47

-80

0.53

80

0.47

-90

0.53

90

0.47

-100

0.53

100 tCK(avg) ps

Clock Period Jitter during DLL locking period tJIT(per, lck)

Cycle to Cycle Period Jitter

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) Cumulative error across 3 cycles

Cumulative error across 4 cycles tERR(4per) tERR(5per) Cumulative error across 5 cycles

Cumulative error across 6 cycles tERR(6per) tERR(7per) Cumulative error across 7 cycles

Cumulative error across 8 cycles tERR(8per) tERR(9per) Cumulative error across 9 cycles

Cumulative error across 10 cycles tERR(10per) tERR(11per) Cumulative error across 11 cycles

Cumulative error across 12 cycles

Cumulative error across n = 13, 14 ... 49, 50 cycles

Absolute clock HIGH pulse width tERR(12per) tERR(nper) tCH(abs) tCL(abs) Absolute clock Low pulse width

Data Timing

DQS,DQS# to DQ skew, per group, per access

DQ output hold time from DQS, DQS#

DQ low-impedance time from CK, CK#

DQ high-impedance time from CK, CK#

Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels

Data hold time to DQS, DQS# referenced to

Vih(ac)Vil(ac) levels

DQ and DM Input pulse width for each input tQH tLZ(DQ) tHZ(DQ) tDIPW

-60

-155

-163

-169

-175

-103

-122

-136

-147

-180

-184

-188

0.43

0.43

0.38

-450

-

360

140

120

60

155

163

169

175

103

122

136

147

180

184

188

-

-

-

225

225

-

-70 70 -80 80

160

140

180

160

-177

-186

-193

-200

-118

-140

-155

-168

118

140

155

168

177

186

193

200

-132

-157

-175

-188

-200

-209

-217

-224

-205

-210

205

210

-231

-237

231

237

-215 215 -242 242 tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min

tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max

0.43 - 0.43 -

0.43 - 0.43 -

200

209

217

224

132

157

175

188

0.38

-500

-

400

-

250

250

-

0.38

-600

-

490

-

300

300

-

-90

-222

-232

-241

-249

-147

-175

-194

-209

-257

-263

-269

0.43

0.43

0.38

-800

-

600

200

180

90

222

232

241

249

147

175

194

209

257

263

269

-

-

-

400

400

- tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) tCK(avg)

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PART NO.:

Product Specifications

VL41B5763F-K0/K9/F8/E7S REV: 1.0

Data Strobe Timing

DQS, DQS# differential READ Postamble

DQS, DQS# output high time

DQS, DQS# output low time

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

tRPST tQSH tQSL

0.3

0.4

0.4

-

-

-

0.3

0.4

0.4

-

-

-

0.3

0.38

0.38

-

-

-

0.3

0.38

0.38

-

-

- tCK tCK(avg) tCK(avg)

DQS, DQS# rising edge output access time from rising CK, CK#

DQS, DQS# low-impedance time

(Referenced from

DQS, DQS# high-impedance time

(Referenced from RL+BL/ 2)

DQS, DQS# differential input low pulse width

DQS, DQS# differential input high pulse width

DQS, DQS# rising edge to CK, CK# rising edge

DQS,DQS# failing edge setup time to CK,

CK# rising edge

DQS,DQS# failing edge hold time to CK,

CK# rising edge

Command and Address Timing

tDQSCK -225 225 -255 255 -300 300 -400 400 ps tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Internal READ Command to PRECHARGE

Command delay

Delay from start of internal write transaction to internal read command tRTP tWTR max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

-

Mode Register Set command cycle time

Mode Register Set command update delay

CAS# to CAS# command delay

Auto precharge write recovery + precharge time

Multi-Purpose Register Recovery Time

ACTIVE to PRECHARGE command period

ACTIVE to ACTIVE command period for

1KB page size

ACTIVE to ACTIVE command period for

2KB page size

Four activate window for 1KB page size

Four activate window for 2KB page size

Command and Address setup time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Command and Address hold time from CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Control & Address Input pulse width for each input tMRD tMOD tCCD tDAL(min) tMPRR tRAS tRRD tRRD tFAW tFAW

4 max

(12tCK,15ns)

4

1

35 max

(4tCK,6ns) max

(4tCK,7.5ns)

30

40

-

-

-

4 max

(12tCK,15ns)

4

-

-

-

4 max

(12tCK,15ns)

4

-

-

-

4 max

(12tCK,15ns)

4

- nCK

-

- nCK

WR + roundup (tRP / tCK(AVG))

- 1 nCK nCK - 1 - 1 -

9*tREFI 36 9*tREFI 37.5 9*tREFI 37.5 9*tREFI ns

-

-

- max

(4tCK,6ns) max

(4tCK,7.5ns)

30

-

-

- max

(4tCK,7.5ns) max

(4tCK,10ns)

37.5

-

-

- max

(4tCK,10ns) max

(4tCK,10ns)

40

-

-

- ns

- 45 - 50 - 50 - ns tIPW 560 - 620 - 780 - 900 - ps

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Product Specifications

PART NO.:

VL41B5763F-K0/K9/F8/E7S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

Refresh Timing

2Gb REFRESH to REFRESH or REFRESH to ACTIVE command interval

Average periodic refresh interval

(0°C<= TCASE <= 85 °C)

Average periodic refresh interval

(85°C<= TCASE <= 95 °C)

Calibration Timing

tRFC 160 - 160 - 160 - 160 - ns

Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - 512 - tCK

Normal operation Full calibration time tZQoper 256 - 256 - 256 - 256 - tCK

Reset Timing

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

Valid Clock Requirement after Self Refresh

Entry (SRE)

Valid Clock Requirement before Self

Refresh Exit (SRX)

Power Down Timing

Exit Power Down with DLL to any valid command; Exit Precharge Power Down with

DLL frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL

CKE minimum pulse width

Command pass disable delay

Power Down Entry to Exit Timing

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power

Down entry

Timing of WR command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WRA command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WR command to Power Down entry (BL4MRS)

Timing of WRA command to Power Down entry (BL4MRS)

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry tXPR tXS tCKESR tCKSRE tCKSRX max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC+10ns) tCKE(min) +

1tCK max(5tC,

10ns) max(5tC,

10ns)

-

-

-

-

-

-

-

- tXP tXPDLL tCKE tCPDED tPD max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

7.5ns)

1 tCKE(min)

-

-

-

-

9*tREFI tRDPDEN tWRPDEN tWRAPDEN tWRPDEN tWRAPDEN

RL + 4 +1

WL + 4

+(tWR/ tCK)

WL+4+WR+

1

WL + 2

+(tWR/ tCK)

WL+2+WR+

1

-

-

- max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC+10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

- max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC +10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

- max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC +10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

- nCK tCK

-

-

RL + 4 +1

WL + 4

+(tWR/ tCK)

-

-

RL + 4 +1

WL + 4

+(tWR/ tCK)

-

-

RL + 4 +1

WL + 4

+(tWR/ tCK)

-

- nCK

- WL+4+WR+1 - WL+4+WR+1 - WL+4+WR+1 - nCK

-

WL + 2

+(tWR/ tCK)

-

WL + 2

+(tWR/ tCK)

-

WL + 2

+(tWR/ tCK)

- nCK

- WL+2+WR+1 - WL+2+WR+1 - WL+2+WR+1 - nCK

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9

Product Specifications

PART NO.:

VL41B5763F-K0/K9/F8/E7S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

ODT Timing

ODT high time without write command or with write command and BC4

ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

ODT turn-on

RTT_NOM and RTT_WR turn-off time from

ODTL off reference

ODTH8 tAON

6

-225

-

225

6

-250

-

250

6

-300

-

300

6

-400

-

400 nCK ps

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is programmed

DQS/DQS delay after tDQS margining mode is programmed

Hold time for tDQSS latch

Write leveling output delay tWLH tWLO

165

0

-

7.5

195

0

-

9

245

0

-

9

325

0

-

9 ps ns

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Package Dimensions

PART NO.:

Product Specifications

VL41B5763F-K0/K9/F8/E7S

FRONT VIEW

67.60

REV: 1.0

3.40

MAX

17.78

6.00 TYP

2.15

TYP

PIN 1

1.00 +/-0.10

0.5 R

0.60

TYP

63.60

TYP

0.45

TYP

PIN 203

1.00 +/-0.10

BACK VIEW

1.80 TYP

(2X)

2.55

TYP

PIN 2

4.00 +/-0.10

PIN 204

39.00

TYP

3.00

TYP

21.00

TYP

39.00

TYP

Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.

2. The dimensional diagram is for reference only.

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Revision History:

PART NO.:

Product Specifications

VL41B5763F-K0/K9/F8/E7S REV: 1.0

04/07/2011 1.0 All Spec

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