Epson | S1C63558 | Specifications | Epson S1C63558 Specifications

MF1110-03
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C63466
Technical Manual
S1C63466 Technical Hardware
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2001, All rights reserved.
Revisions and Additions for this manual
Chapter
7
Appendix
S1C63466 Technical Manual
Section
7.5
Page
113
125
Item
OSC1 crystal oscillation circuit
Appendix
Contents
The table was revised.
The Appendix was added.
The information of the product number change
Starting April 1, 2001, the product number has been changed as listed below. Please use the new
product number when you place an order. For further information, please contact Epson sales
representative.
Configuration of product number
Devices
S1
C
63158
F
0A01
00
Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
C
63000
S5U1
A1
1
00
Packing specification
Version (1: Version 1 ∗2)
Tool type (A1: Assembler Package ∗1)
Corresponding model number
(63000: common to S1C63 Family)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
∗2: Actual versions are not written in the manuals.
Comparison table between new and previous number
S1C63 Family processors
S1C63 Family peripheral products
Previous No.
New No.
Previous No.
New No.
E0C63158
E0C63256
E0C63358
E0C63P366
E0C63404
E0C63406
E0C63408
E0C63F408
E0C63454
E0C63455
E0C63458
E0C63466
E0C63P466
S1C63158
S1C63256
S1C63358
S1C6P366
S1C63404
S1C63406
S1C63408
S1C6F408
S1C63454
S1C63455
S1C63458
S1C63466
S1C6P466
E0C63467
E0C63557
E0C63558
E0C63567
E0C63F567
E0C63658
E0C63666
E0C63F666
E0C63A08
E0C63B07
E0C63B08
E0C63B58
S1C63467
S1C63557
S1C63558
S1C63567
S1C6F567
S1C63658
S1C63666
S1C6F666
S1C63A08
S1C63B07
S1C63B08
S1C63B58
Previous No.
E0C5250
E0C5251
New No.
S1C05250
S1C05251
Comparison table between new and previous number of development tools
Development tools for the S1C63 Family
Development tools for the S1C63/88 Family
Previous No.
New No.
Previous No.
New No.
ADP63366
ADP63466
ASM63
GAM63001
ICE63
PRC63001
PRC63002
PRC63004
PRC63005
PRC63006
PRC63007
URS63366
S5U1C63366X
S5U1C63466X
S5U1C63000A
S5U1C63000G
S5U1C63000H1
S5U1C63001P
S5U1C63002P
S5U1C63004P
S5U1C63005P
S5U1C63006P
S5U1C63007P
S5U1C63366Y
ADS00002
GWH00002
URM00002
S5U1C88000X1
S5U1C88000W2
S5U1C88000W1
CONTENTS
CONTENTS
CHAPTER
1 OUTLINE ________________________________________________ 1
1.1
1.2
1.3
1.4
1.5
CHAPTER
Features ......................................................................................................... 1
Block Diagram .............................................................................................. 2
Pin Layout Diagram ..................................................................................... 3
Pin Description ............................................................................................. 5
Mask Option .................................................................................................. 6
2 POWER SUPPLY AND INITIAL RESET ____________________________ 9
2.1
Power Supply ................................................................................................ 9
2.1.1 Voltage <VD1> for oscillation circuit and internal circuits ..................... 10
2.1.2 Voltage <VC1–VC5> for LCD driving ....................................................... 10
2.2
Initial Reset .................................................................................................. 11
2.2.1 Reset terminal (RESET) ............................................................................ 11
2.2.2 Simultaneous low input to terminals K00–K03 ........................................ 12
2.2.3 Internal register at initial resetting ........................................................... 12
2.2.4 Terminal settings at initial resetting ......................................................... 13
2.3
CHAPTER
3 CPU, ROM, RAM ________________________________________ 14
3.1
3.2
3.3
3.4
CHAPTER
Test Terminal (TEST) ................................................................................... 13
CPU .............................................................................................................. 14
Code ROM .................................................................................................... 14
RAM ............................................................................................................. 14
Data ROM .................................................................................................... 15
4 PERIPHERAL CIRCUITS AND OPERATION __________________________ 16
4.1
4.2
Memory Map ................................................................................................ 16
Watchdog Timer ........................................................................................... 22
4.2.1 Configuration of watchdog timer .............................................................. 22
4.2.2 Interrupt function ...................................................................................... 22
4.2.3 I/O memory of watchdog timer ................................................................. 23
4.2.4 Programming notes ................................................................................... 23
4.3
Oscillation Circuit ....................................................................................... 24
4.3.1 Configuration of oscillation circuit .......................................................... 24
4.3.2 OSC1 oscillation circuit ............................................................................ 24
4.3.3 OSC3 oscillation circuit ............................................................................ 25
4.3.4 Switching of operating voltage ................................................................. 26
4.3.5 Clock frequency and instruction execution time ....................................... 26
4.3.6 I/O memory of oscillation circuit .............................................................. 27
4.3.7 Programming notes ................................................................................... 28
4.4
Input Ports (K00–K03 and K10–K13) ......................................................... 29
4.4.1 Configuration of input ports ..................................................................... 29
4.4.2 Interrupt function ...................................................................................... 29
4.4.3 Mask option ............................................................................................... 30
4.4.4 I/O memory of input ports ......................................................................... 31
4.4.5 Programming notes ................................................................................... 33
S1C63466 TECHNICAL MANUAL
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CONTENTS
4.5
Output Ports (R00–R03, R10–R13 and R20–R23) ...................................... 34
4.5.1 Configuration of output ports ................................................................... 34
4.5.2 Mask option ............................................................................................... 34
4.5.3 High impedance control ............................................................................ 35
4.5.4 Special output ............................................................................................ 35
4.5.5 I/O memory of output ports ....................................................................... 37
4.5.6 Programming notes ................................................................................... 39
4.6
I/O Ports (P00–P03, P10–P13 and P20–P23) ............................................ 40
4.6.1 Configuration of I/O ports ........................................................................ 40
4.6.2 Mask option ............................................................................................... 41
4.6.3 I/O control registers and input/output mode ............................................ 41
4.6.4 Pull-up during input mode ........................................................................ 41
4.6.5 Special outputs (CL, FR) ........................................................................... 42
4.6.6 I/O memory of I/O ports ............................................................................ 43
4.6.7 Programming notes ................................................................................... 46
4.7
LCD Driver (COM0–COM16, SEG0–SEG59) ........................................... 47
4.7.1 Configuration of LCD driver .................................................................... 47
4.7.2 Power supply for LCD driving .................................................................. 47
4.7.3 Mask option ............................................................................................... 48
4.7.4 LCD display control (ON/OFF) and switching of duty ............................ 48
4.7.5 Display memory ......................................................................................... 51
4.7.6 LCD contrast adjustment .......................................................................... 52
4.7.7 I/O memory of LCD driver ........................................................................ 53
4.7.8 Programming notes ................................................................................... 55
4.8
Clock Timer .................................................................................................. 56
4.8.1 Configuration of clock timer ..................................................................... 56
4.8.2 Data reading and hold function ................................................................ 56
4.8.3 Interrupt function ...................................................................................... 57
4.8.4 I/O memory of clock timer ........................................................................ 58
4.8.5 Programming notes ................................................................................... 60
4.9
Stopwatch Timer ........................................................................................... 61
4.9.1 Configuration of stopwatch timer ............................................................. 61
4.9.2 Count-up pattern ....................................................................................... 61
4.9.3 Interrupt function ...................................................................................... 62
4.9.4 I/O memory of stopwatch timer ................................................................ 63
4.9.5 Programming notes ................................................................................... 64
4.10 Programmable Timer ................................................................................... 65
4.10.1 Configuration of programmable timer .................................................... 65
4.10.2 Setting of initial value and counting down ............................................. 66
4.10.3 Counter mode .......................................................................................... 67
4.10.4 Setting of input clock in timer mode ....................................................... 68
4.10.5 Interrupt function .................................................................................... 69
4.10.6 Setting of TOUT output ........................................................................... 69
4.10.7 Transfer rate setting for serial interface ................................................ 70
4.10.8 I/O memory of programmable timer ....................................................... 71
4.10.9 Programming notes ................................................................................. 76
4.11 Serial Interface (SIN, SOUT, SCLK, SRDY) ................................................ 77
4.11.1 Configuration of serial interface ............................................................ 77
4.11.2 Mask option ............................................................................................. 78
4.11.3 Master mode and slave mode of serial interface .................................... 78
4.11.4 Data input/output and interrupt function ............................................... 79
4.11.5 I/O memory of serial interface ................................................................ 82
4.11.6 Programming notes ................................................................................. 85
4.12 Sound Generator .......................................................................................... 86
4.12.1 Configuration of sound generator .......................................................... 86
4.12.2 Mask option ............................................................................................. 86
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S1C63466 TECHNICAL MANUAL
CONTENTS
4.12.3 Control of buzzer output .......................................................................... 87
4.12.4 Setting of buzzer frequency and sound level ........................................... 87
4.12.5 Digital envelope ...................................................................................... 88
4.12.6 One-shot output ....................................................................................... 89
4.12.7 I/O memory of sound generator .............................................................. 90
4.12.8 Programming notes ................................................................................. 92
4.13 SVD (Supply Voltage Detection) Circuit ...................................................... 93
4.13.1 Configuration of SVD circuit .................................................................. 93
4.13.2 Mask option ............................................................................................. 93
4.13.3 SVD operation ......................................................................................... 93
4.13.4 I/O memory of SVD circuit ...................................................................... 94
4.13.5 Programming notes ................................................................................. 95
4.14 Interrupt and HALT ..................................................................................... 96
4.14.1 Interrupt factor ........................................................................................ 98
4.14.2 Interrupt mask ......................................................................................... 99
4.14.3 Interrupt vector ....................................................................................... 99
4.14.4 I/O memory of interrupt ......................................................................... 100
4.14.5 Programming notes ................................................................................ 102
CHAPTER
5 SUMMARY OF NOTES ______________________________________ 103
5.1
5.2
Notes for Low Current Consumption .......................................................... 103
Summary of Notes by Function ................................................................... 104
CHAPTER
6 BASIC EXTERNAL WIRING DIAGRAM ___________________________ 108
CHAPTER
7 ELECTRICAL CHARACTERISTICS _______________________________ 109
7.1
7.2
7.3
7.4
7.5
7.6
7.7
CHAPTER
8 PACKAGE _______________________________________________ 117
8.1
8.2
CHAPTER
Absolute Maximum Rating .......................................................................... 109
Recommended Operating Conditions ......................................................... 109
DC Characteristics ..................................................................................... 110
Analog Circuit Characteristics and Power Current Consumption ............ 111
Oscillation Characteristics ......................................................................... 113
Serial Interface AC Characteristics ........................................................... 115
Timing Chart ............................................................................................... 116
Plastic Package ........................................................................................... 117
Ceramic Package for Test Samples ............................................................. 120
9 PAD LAYOUT ____________________________________________ 123
9.1
9.2
Diagram of Pad Layout ............................................................................... 123
Pad Coordinates .......................................................................................... 124
APPENDIX S5U1C63000P MANUAL
(PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) __ 125
A.1 Names and Functions of Each Part ............................................................ 125
A.2 Connecting to the Target System ................................................................ 128
A.3 Usage Precautions ...................................................................................... 130
A.3.1 Operational precautions .......................................................................... 130
A.3.2 Differences with the actual IC ................................................................. 130
S1C63466 TECHNICAL MANUAL
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iii
CHAPTER 1: OUTLINE
CHAPTER
1 OUTLINE
The S1C63466 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core
CPU, ROM (16,384 words × 13 bits), RAM (1,792 words × 4 bits), serial interface, watchdog timer, programmable timer, time base counters (2 systems), SVD circuit, a dot-matrix LCD driver that can drive a
maximum 60 segments × 17 commons and sound generator built-in. The S1C63466 features high speed
operation and low current consumption in a wide operating voltage range (2.2 V to 6.4 V), this makes it
suitable for applications working with batteries. It is also suitable for LCD game because it has a large
capacity of ROM built-in.
1.1 Features
OSC1 oscillation circuit ...................... 32.768 kHz (Typ.) crystal or 60 kHz (Typ.) CR oscillation circuit (∗1)
OSC3 oscillation circuit ...................... 1.8 MHz (Typ.) CR or 4 MHz (Max.) ceramic oscillation circuit (∗1)
Instruction set ..................................... Basic instruction: 46 types (411 instructions with all)
Addressing mode: 8 types
Instruction execution time ................... During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec
During operation at 60 kHz:
33 µsec
67 µsec 100 µsec
During operation at 4 MHz:
0.5 µsec
1 µsec 1.5 µsec
ROM capacity ..................................... Code ROM:
Data ROM:
16,384 words × 13 bits
2,048 words × 4 bits (= 8K bits)
RAM capacity ...................................... Data memory:
1,792 words × 4 bits
Display memory: 1,020 bits (240 words × 4 bits + 60 × 1 bit)
Input port ............................................. 8 bits
(Pull-up resistors may be supplemented ∗1)
Output port .......................................... 12 bits
(It is possible to switch the 2 bits to special output ∗2)
I/O port ................................................ 12 bits
(It is possible to switch the 2 bits to special output and
the 4 bits to serial I/F input/output ∗2)
Serial interface .................................... 1 port
(8-bit clock synchronous system)
LCD driver ........................................... 60 segments × 8, 16 or 17 commons (∗2)
Time base counter .............................. 2 systems (Clock timer, stopwatch timer)
Programmable timer ........................... Built-in, 2 inputs × 8 bits, with event counter function
Watchdog timer ................................... Built-in
Sound generator ................................. With envelope and 1-shot output functions
Supply voltage detection (SVD) circuit .. 16 values, programmable (1.85 V to 3.30 V)
(It is possible to switch 1 value to the external voltage detection ∗1)
External interrupt ................................ Input port interrupt:
2 systems
Internal interrupt ................................. Clock timer interrupt:
4 systems
Stopwatch timer interrupt:
2 systems
Programmable timer interrupt: 2 systems
Serial interface interrupt:
1 system
Power supply voltage ......................... 2.2 V to 6.4 V (Min. 1.8 V when the OSC3 oscillation circuit is not used)
Operating temperature range ............. -20°C to 70°C
S1C63466 TECHNICAL MANUAL
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CHAPTER 1: OUTLINE
Current consumption (Typ.) ................ Single clock (OSC1: Crystal oscillation):
During HALT (32 kHz)
3.0 V (LCD power OFF)
1 µA
3.0 V (LCD power ON, VC1 standard)
6 µA
3.0 V (LCD power ON, VC2 standard)
4 µA
During operation (32 kHz)
3.0 V (LCD power ON, VC1 standard)
10 µA
Twin clock:
During operation (4 MHz)
3.0 V (LCD power ON, VC1 standard) 1,200 µA
Package .............................................. QFP8-144pin, QFP17-144pin, QFP5-128pin (plastic) or chip
∗1: Can be selected with mask option ∗2: Can be selected with software
1.2 Block Diagram
ROM
System Reset
Control
16,384 words × 13 bits
RESET
Core CPU S1C63000
OSC1
OSC2
OSC3
OSC4
OSC
Interrupt
Generator
RAM
Stopwatch
Timer
1,792 words × 4 bits
Clock
Timer
Data ROM
2,048 words × 4 bits
COM0–16
SEG0–59
VDD
VC1–5
CA–CF
VD1
VSS
VREF
SVD
BZ
Programmable
Timer/Counter
LCD Driver
60 SEG × 17 COM
Input Port
K00–K03
K10–K13
TEST
Power
Controller
Serial Interface
SVD
I/O Port
P00–P03
P10–P13
P20–P23
Sound
Generator
Output Port
R00–R03
R10–R13
R20–R23
Fig. 1.2.1 Block diagram
2
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S1C63466 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.3 Pin Layout Diagram
QFP8-144pin
QFP17-144pin
108
108
73
72
109
72
109
S1C63466
S1C63466
INDEX
INDEX
37
144
1
37
144
1
36
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
73
Name
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM7
COM6
COM5
COM4
N.C.
COM3
COM2
COM1
COM0
BZ
VSS
OSC1
OSC2
VD1
OSC3
OSC4
VDD
RESET
TEST
VREF
N.C.
N.C.
No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Name
N.C.
N.C.
R23
R22
R21
R20
R13
R12
R11
R10
R03
R02
R01
R00
P23
P22
P21
P20
P13
P12
P11
P10
P03
P02
P01
P00
K13
K12
K11
K10
K03
K02
K01
K00
N.C.
N.C.
No.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
36
Name
Name
No.
N.C.
N.C.
109
SVD
SEG47
110
VC1
SEG46
111
SEG45
VC2
112
SEG44
VC3
113
SEG43
VC4
114
SEG42
VC5
115
CF
SEG41
116
CE
SEG40
117
CD
SEG39
118
CC
SEG38
119
CB
SEG37
120
CA
SEG36
121
COM8
SEG35
122
COM9
SEG34
123
COM10 124
SEG33
COM11 125
SEG32
COM12 126
SEG31
COM13 127
SEG30
COM14 128
SEG29
COM15 129
SEG28
COM16 130
SEG27
SEG59
SEG26
131
SEG58
SEG25
132
SEG57
SEG24
133
SEG56
SEG23
134
SEG55
SEG22
135
SEG54
SEG21
136
SEG53
SEG20
137
SEG52
SEG19
138
SEG51
SEG18
139
SEG50
SEG17
140
SEG49
SEG16
141
SEG48
SEG15
142
N.C.
SEG14
143
N.C.
N.C.
144
N.C. : No Connection
Fig. 1.3.1 Pin layout diagram
Note: The pin layout diagram of the both package is same.
S1C63466 TECHNICAL MANUAL
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CHAPTER 1: OUTLINE
QFP5-128pin
102
65
64
103
S1C63466
INDEX
39
128
1
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
38
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM7
COM6
COM5
COM4
COM3
COM2
BZ
VSS
OSC1
OSC2
VD1
OSC3
OSC4
VDD
No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Name
No.
Name
RESET
97
K02
TEST
98
K01
VREF
99
K00
N.C.
100
SVD
R23
101
VC1
R22
102
VC2
R21
103
VC3
R20
104
VC4
R13
105
VC5
R12
106
CF
R11
107
CE
R10
108
CD
R03
109
CC
R02
110
CB
R01
111
CA
R00
112
COM8
P23
113
COM9
P22
114 COM10
P21
115 COM11
P20
116 COM12
P13
117 COM13
P12
118 COM14
P11
119
SEG59
P10
120
SEG58
P03
121
SEG57
P02
122
SEG56
P01
123
SEG55
P00
124
SEG54
K13
125
SEG53
K11
126
SEG52
K10
127
SEG51
K03
128
SEG50
N.C. : No Connection
Fig. 1.3.2 Pin layout diagram
Note: This package does not have the K12 terminal. For the K12 mask option, "With pull-up resistor"
should be chosen when using this package.
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S1C63466 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.4 Pin Description
Table 1.4.1 Pin description
VC1–VC5
Pin No.
QFP8-144,QFP17-144
31
25
28
75–79
QFP5-128
64
58
61
101–105
VREF
CA–CF
OSC1
34
85–80
26
67
111–106
59
O
–
I
OSC2
27
60
O
OSC3
29
62
I
OSC4
30
63
O
70–67
66,65
64
63
62–59
58–55
99–96
95,94
–
93
92–89
88–85
I
I
I
I
I/O
I/O
P20
P21
P22
54
53
52
84
83
82
I/O
I/O
I/O
P23
51
81
I/O
R00
R01
R02
50
49
48
80
79
78
O
O
O
R03
47
77
O
46–43
42–39
23,22
21,20,18–15,86–92
93,94
14–1,143–110,106–95
24
74
32
33
76–73
72–69
–
56–51,112–118
–
50–1,128–119
57
100
65
66
O
O
O
Pin name
VDD
VSS
VD1
K00–K03
K10, K11
K12
K13
P00–P03
P10–P13
R10–R13
R20–R23
COM0, COM1
COM2–COM14
COM15, COM16
SEG0–SEG59
BZ
SVD
RESET
TEST
S1C63466 TECHNICAL MANUAL
In/Out
Function
–
–
–
–
Power (+) supply pin
Power (–) supply pin
Oscillation/internal logic system regulated voltage output pin
LCD system power supply pin
1/4 bias generated internally, 1/5 bias supplied externally
(selected by mask option)
LCD system power supply testing pin
LCD system boosting/reducing capacitor connecting pin
Crystal or CR oscillation input pin
(selected by mask option)
Crystal or CR oscillation output pin
(selected by mask option)
Ceramic or CR oscillation input pin
(selected by mask option)
Ceramic or CR oscillation output pin
(selected by mask option)
Input port
Input port
Input port
Input port
I/O port
I/O port
(switching to serial I/F input/output is possible by software)
I/O port
I/O port
I/O port
(switching to CL signal output is possible by software)
I/O port
(switching to FR signal output is possible by software)
Output port
Output port
Output port
(switching to TOUT signal output is possible by software)
Output port
(switching to FOUT signal output is possible by software)
Output port
Output port
LCD common output pin
(1/8, 1/16, 1/17 duty can be selected by software)
O
O
LCD segment output pin
Sound output pin
I
I
I
SVD external voltage input pin
Initial reset input pin
Testing input pin
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5
CHAPTER 1: OUTLINE
1.5 Mask Option
Mask options shown below are provided for the S1C63466. Several hardware specifications are prepared
in each mask option, and one of them can be selected according to the application. The function option
generator winfog, that has been prepared as the development software tool of S1C63466, is used for this
selection. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the
"S5U1C63000A Manual" for the winfog.
<Functions selectable with S1C63466 mask options>
(1) External reset by simultaneous LOW input to the input port (K00–K03)
This function resets the IC when several keys are pressed simultaneously. The mask option is used to
select whether this function is used or not. Further when the function is used, a combination of the
input ports (K00–K03), which are connected to the keys to be pressed simultaneously, can be selected.
Refer to Section 2.2.2, "Simultaneous low input to terminals K00–K03", for details.
(2) Time authorize circuit for the simultaneous LOW input reset function
When using the external reset function (shown in 1 above), using the time authorize circuit or not can
be selected by the mask option. The reset function works only when the input time of simultaneous
LOW is more than the rule time if the time authorize circuit is being used.
Refer to Section 2.2.2, "Simultaneous low input to terminals K00–K03", for details.
(3) Input port pull-up resistor
The mask option is used to select whether the pull-up resistor is supplemented to the input ports or
not. It is possible to select for each bit of the input ports. When using the QFP5-128pin package, "With
pull-up resistor" option should be chosen for the K12 input port.
Refer to Section 4.4.3, "Mask option", for details.
(4) Output specification of the output port
Either complementary output or N-channel open drain output can be selected as the output specification for the output ports R10–R13 and R20–R23. The selection is done in 4-bit units (R10–R13 and R20–
R23). The output ports R00–R03 can only be used as complementary output.
Refer to Section 4.5.2, "Mask option", for details.
(5) Output specification / pull-up resistor of the I/O ports
Either complementary output or N-channel open drain output can be selected as the output specification when the P10–P13 and P20–P23 are in the output mode. The selection is done in 1-bit units or 4bit units depending on the I/O port.
1-bit unit: P20, P21, P22, P23
4-bit unit: P10–P13
Note that the P00–P03 can only be used as complementary output.
Further, whether or not the pull-up resistors working in the input mode are supplemented can be
selected. The selection is done in 1-bit units or 4-bit units depending on the I/O port.
1-bit unit: P20, P21, P22, P23
4-bit unit: P10–P13
Refer to Section 4.6.2, "Mask option", for details.
(6) LCD drive bias
Either the internal power supply (1/4 bias) or an external power supply (1/5 bias) can be selected as
the LCD system power supply.
Refer to Section 4.7.3, "Mask option", for details.
6
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S1C63466 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
(7) Synchronous clock polarity in the serial interface
The polarity of the synchronous clock SCLK and the SRDY signal in slave mode of the serial interface
is selected by the mask option. Either positive polarity or negative polarity can be selected.
Refer to Section 4.11.2, "Mask option", for details.
(8) Buzzer output specification of the sound generator
It is possible to select the polarity of the buzzer signal output from the BZ terminal. Select either
positive polarity or negative polarity according to the external drive transistor to be used.
Refer to Section 4.12.2, "Mask option", for details.
(9) External voltage detection of SVD circuit
External voltage (SVD terminal–VSS terminal) detection can be selected in addition to supply voltage
(VDD terminal–VSS terminal) detection. The SVD terminal is used to input the external voltage to be
detected.
Refer to Section 4.13.2, "Mask option", for details.
(10)OSC1 oscillation circuit
Either crystal oscillation circuit or CR oscillation circuit can be selected as the OSC1 oscillation circuit.
Refer to Section 4.3.2, "OSC1 oscillation circuit", for details.
(11)OSC3 oscillation circuit
Either CR oscillation circuit or ceramic oscillation circuit can be selected as the OSC3 oscillation circuit.
Refer to Section 4.3.3, "OSC3 oscillation circuit", for details.
<Mask option list>
The following is the option list for the S1C63466. Multiple selections are available in each option item as
indicated in the option list. Refer to Chapter 4, "Peripheral Circuits and Operation", to select the specifications that meet the application system. Be sure to select the specifications for unused functions too,
according to the instruction provided. Use winfog in the S5U1C63000A package for this selection. Refer to
the "S5U1C63000A Manual" for details.
1. OSC1 SYSTEM CLOCK
■ 1. Crystal (32.768 kHz)
■ 2. CR
2. OSC3 SYSTEM CLOCK
■ 1. Use <Ceramic (4 MHz)> or Not Use
■ 2. Use <CR (1.8 MHz)>
3. MULTIPLE KEY ENTRY RESET COMBINATION
■
■
■
■
1. Not Use
2. Use <K00, K01, K02, K03>
3. Use <K00, K01, K02>
4. Use <K00, K01>
4. MULTIPLE KEY ENTRY RESET TIME AUTHORIZE
■ 1. Not Use
■ 2. Use
5. INPUT PORT PULL UP RESISTOR
• K00 ...... ■
• K01 ...... ■
• K02 ...... ■
• K03 ...... ■
• K10 ...... ■
• K11 ....... ■
• K12 ...... ■
• K13 ...... ■
1. With Resistor
1. With Resistor
1. With Resistor
1. With Resistor
1. With Resistor
1. With Resistor
1. With Resistor
1. With Resistor
S1C63466 TECHNICAL MANUAL
■
■
■
■
■
■
■
■
2. Gate Direct
2. Gate Direct
2. Gate Direct
2. Gate Direct
2. Gate Direct
2. Gate Direct
2. Gate Direct
2. Gate Direct
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7
CHAPTER 1: OUTLINE
6. OUTPUT PORT OUTPUT SPECIFICATION
• R1x ...... ■ 1. Complementary
• R2x ...... ■ 1. Complementary
■ 2. Nch-OpenDrain
■ 2. Nch-OpenDrain
7. I/O PORT OUTPUT SPECIFICATION
• P1x .......
• P20 .......
• P21 .......
• P22 .......
• P23 .......
■
■
■
■
■
1. Complementary
1. Complementary
1. Complementary
1. Complementary
1. Complementary
■
■
■
■
■
2. Nch-OpenDrain
2. Nch-OpenDrain
2. Nch-OpenDrain
2. Nch-OpenDrain
2. Nch-OpenDrain
■
■
■
■
■
2. Gate Direct
2. Gate Direct
2. Gate Direct
2. Gate Direct
2. Gate Direct
8. I/O PORT PULL UP RESISTOR
• P1x .......
• P20 .......
• P21 .......
• P22 .......
• P23 .......
■
■
■
■
■
1. With Resistor
1. With Resistor
1. With Resistor
1. With Resistor
1. With Resistor
9. LCD DRIVING POWER
■ 1. Internal
■ 2. External
10. SERIAL PORT INTERFACE POLARITY
■ 1. Positive
■ 2. Negative
11. SVD EXTERNAL VOLTAGE DETECTION
■ 1. Not Use
■ 2. Use
12. SOUND GENERATOR POLARITY FOR OUTPUT
■ 1. Positive
■ 2. Negative
8
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S1C63466 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER
2 POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
The S1C63466 operating power voltage is as follows:
Table 2.1.1 Operating power voltage
OSC1 oscillation circuit
Crystal oscillation
OSC3 oscillation circuit
Not use
Operating power voltage
1.8 V–6.4 V
Crystal oscillation
CR oscillation
Use
–
2.2 V–6.4 V
2.2 V–6.4 V
The S1C63466 operates by applying a single power supply within the above range between VDD and VSS.
The S1C63466 itself generates the voltage necessary for all the internal circuits by the built-in power
supply circuits shown in Table 2.1.2.
Table 2.1.2 Power supply circuits
Circuit
Oscillation and internal circuits
LCD driver
Power supply circuit
Oscillation system voltage regulator
LCD system voltage circuit
Output voltage
VD1
VC1–VC5
Note: • Do not drive external loads with the output voltage from the internal power supply circuits.
• VC3 should be used only when the LCD drive voltage is supplied externally (1/5 bias); when
using the internal LCD system voltage circuit (1/4 bias), short between VC3 and VC2 terminals.
• See Chapter 7, "Electrical Characteristics", for voltage values and drive capability.
V DD
Internal
circuits
V D1
VD1
External
power
supply
+
V C1
V C2
V C3
V C4
V C5
CA
CB
CC
CD
CE
CF
Oscillation system
voltage regulator
LCD system
voltage circuit
Oscillation
circuit
V C1 – V C5
LCD driver
OSC1–4
COM0–16
SEG0–59
V SS
Fig. 2.1.1 Configuration of power supply
S1C63466 TECHNICAL MANUAL
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9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.1 Voltage <VD1> for oscillation circuit and internal circuits
VD1 is a voltage for the oscillation circuit and the internal logic circuits, and is generated by the oscillation
system voltage regulator for stabilizing the oscillation.
The S1C63466 is designed with twin clock specification; it has two types of oscillation circuits OSC1 and
OSC3 built-in. Use OSC1 clock for normal operation, and switch it to OSC3 by the software when highspeed operation is necessary. When switching the clock, the operating voltage VD1 must be switched by
the software to stabilize the operation of the oscillation circuit and internal circuits.
The oscillation system voltage regulator can output the following two types of VD1 voltage. It should be
set at the value according to the oscillation circuit and oscillation frequency by the software.
Single clock operation (OSC1 crystal oscillation):
Single clock operation (OSC1 CR oscillation):
Twin clock operation (OSC3, 4 MHz):
VD1 = 1.3 V
VD1 = 2.2 V
VD1 = 2.2 V
Refer to Section 4.3, "Oscillation Circuit", for the VD1 switching procedure.
However, since the VD1 voltage value is fixed at 2.2 V when the CR oscillation circuit has been selected as
the OSC1 oscillation circuit by mask option, it is not necessary to switch VD1 by software.
2.1.2 Voltage <VC1–VC5> for LCD driving
VC1–VC5 are the LCD drive voltages for which either the voltage generated by the LCD system voltage
circuit or voltage to be supplied from outside can be used. The built-in LCD system voltage circuit
generates four voltages (1/4 bias) VC1, VC2, VC4 and VC5 (excluding VC3). These four output voltages can
only be supplied to the externally expanded LCD driver.
When external voltages are supplied, 1/5 bias driving can be done by inputting drive voltage to the VC1–
VC5 terminals (including VC3).
Either the internal generated voltages or external voltages used for the LCD drive voltage can be selected
by a mask option.
The LCD system voltage circuit generates VC1 or VC2 with the voltage regulator built-in, and generates
three other voltages by boosting or reducing the voltage of VC1 or VC2. Table 2.1.2.1 shows the VC1, VC2,
VC4 and VC5 voltage values and boost/reduce status.
Table 2.1.2.1 LCD drive voltage when generated internally
LCD drive voltage
VC1 (0.975–1.2 V)
VC2 (1.950–2.4 V)
VC4 (2.925–3.6 V)
VC5 (3.900–4.8 V)
VDD = 1.8–6.4 V
VC1 (standard)
2 × VC1
3 × VC1
4 × VC1
VDD = 2.6–6.4 V
1/2 × VC2
VC2 (standard)
3/2 × VC2
2 × VC2
Note: The LCD drive voltage can be adjusted by the software (see Section 4.7.6). Values in the above
table are typical values.
Either the VC1 or VC2 used for the standard is selected according to the supply voltage by the software.
The VC2 standard improves the display quality and reduces current consumption, however, the power
supply voltage VDD must be 2.6 V or more.
Refer to Section 4.7, "LCD Driver", for control of the LCD drive voltage.
10
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S1C63466 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C63466 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous low input to terminals K00–K03 (mask option setting)
The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the
reset function. It is not guaranteed that the circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
OSC1
OSC2
1 Hz
OSC1
oscillation
circuit
Divider
2 Hz
Mask option
VDD
K00
K01
Mask option
Time
authorize
circuit
K02
Noise
reject
circuit
K03
VDD
R
RESET
Internal
initial
reset
Q
S
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the
initial reset is released by setting the reset terminal to a high level (VDD) and the CPU starts operation.
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when fOSC1 = 32.768 kHz) is needed until the internal initial
reset is released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or
more.
However, when turning the power on, the reset terminal should be set at a low level as in the timing
shown in Figure 2.2.1.1.
1.8 (2.2) V
VDD
2.0 msec or more
RESET
0.5•VDD
0.1•VDD or less (low level)
Power on
Fig. 2.2.1.1 Initial reset at power on
The reset terminal should be set to 0.1•VDD or less (low level) until the supply voltage becomes 1.8 V or
more (until the supply voltage becomes 2.2 V or more when the CR oscillation circuit has been selected as
the OSC1 oscillation circuit by mask option).
After that, a level of 0.5•VDD or less should be maintained more than 2.0 msec.
S1C63466 TECHNICAL MANUAL
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11
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.2 Simultaneous low input to terminals K00–K03
Another way of executing initial reset externally is to input a low signal simultaneously to the input ports
(K00–K03) selected with the mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at
low level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal operation. The noise reject circuit does not operate immediately after turning the power on until the oscillation
circuit starts oscillating. Therefore, maintain the specified input port terminals at low level for at least 1.5
msec (when the oscillation frequency fOSC1 is 32.768 kHz) after oscillation starts.
Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.
Table 2.2.2.1 Combinations of input ports
1
2
Not use
K00∗K01∗K02∗K03
3
4
K00∗K01∗K02
K00∗K01
When, for instance, mask option 2 (K00∗K01∗K02∗K03) is selected, initial reset is executed when the
signals input to the four ports K00–K03 are all low at the same time. When 3 or 4 is selected, the initial
reset is done when a key entry including a combination of selected input ports is made.
Further, the time authorize circuit can be selected with the mask option. The time authorize circuit checks
the input time of the simultaneous low input and performs initial reset if that time is the defined time (1
to 2 sec) or more.
If using this function, make sure that the specified ports do not go low at the same time during ordinary
operation.
2.2.3 Internal register at initial resetting
Initial reset initializes the CPU as shown in Table 2.2.3.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.
12
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S1C63466 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Table 2.2.3.1 Initial values
Name
Data register A
Data register B
Extension register EXT
CPU core
Symbol Number of bits
A
4
Setting value
Undefined
B
EXT
4
8
Undefined
Undefined
X
Y
16
16
Undefined
Undefined
Program counter
Stack pointer SP1
PC
SP1
16
8
0110H
Undefined
Stack pointer SP2
Zero flag
SP2
Z
8
1
Undefined
Undefined
Carry flag
Interrupt flag
C
I
1
1
Undefined
0
Extension flag
Queue register
E
Q
1
16
0
Undefined
Index register X
Index register Y
Name
RAM
Display memory
Other pheripheral circuits
Peripheral circuits
Number of bits
4
4
–
Setting value
Undefined
Undefined
∗
∗ See Section 4.1, "Memory Map".
2.2.4 Terminal settings at initial resetting
The output port (R) terminals and I/O port (P) terminals are shared with special output terminals and
input/output terminals of the serial interface. These functions are selected by the software. At initial
reset, these terminals are set to the general purpose output port terminals and I/O port terminals. Set
them according to the system in the initial routine. In addition, take care of the initial status of output
terminals when designing a system.
Table 2.2.4.1 shows the list of the shared terminal settings.
Table 2.2.4.1 List of shared terminal settings
Terminal
name
R00
R01
R02
R03
R10–R13
R20–R23
Terminal status
at initial reset
R00 (High output)
R01 (High output)
R02 (High output)
R03 (High output)
R10–R13 (High output)
R20–R23 (High output)
Special output
TOUT FOUT CL
Serial I/F
Master
Slave
TOUT
FOUT
P00–P03 P00–P03 (Input & Pull-up ∗)
P10
P10 (Input & Pull-up ∗)
P11
P11 (Input & Pull-up ∗)
P12
P13
P20
FR
SIN(I)
SIN(I)
SOUT(O) SOUT(O)
P12 (Input & Pull-up ∗)
P13 (Input & Pull-up ∗)
P20 (Input & Pull-up ∗)
SCLK(O) SCLK(I)
SRDY(O)
P21
P21 (Input & Pull-up ∗)
P22
P22 (Input & Pull-up ∗)
CL
P23
P23 (Input & Pull-up ∗)
FR
∗ When "with pull-up" is selected by mask option (high impedance when "gate direct" is selected)
For setting procedure of the functions, see explanations for each of the peripheral circuits.
2.3 Test Terminal (TEST)
This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST
terminal to VDD.
S1C63466 TECHNICAL MANUAL
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13
CHAPTER 3: CPU, ROM, RAM
CHAPTER
3 CPU, ROM, RAM
3.1 CPU
The S1C63466 has a 4-bit core CPU S1C63000 built-in as its CPU part.
Refer to the "S1C63000 Core CPU Manual" for the S1C63000.
Note: The SLP instruction cannot be used because the SLEEP operation is not assumed in the S1C63466.
3.2 Code ROM
The built-in code ROM is a mask ROM for loading programs, and has a capacity of 16,384 steps × 13 bits.
The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the
program area of the S1C63466 is step 0000H to step 3FFFH. The program start address after initial reset is
assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are
allocated to step 0100H and steps 0104H–010EH, respectively.
0000H
0000H
ROM
S1C63466
program area
3FFFH
4000H
0100H
0104H
010EH
S1C63000 core CPU
program space
FFFFH
0110H
Program area
NMI vector
Hardware
interrupt vectors
Program start address
Program area
Unused area
13 bits
Fig. 3.2.1 Configuration of code ROM
3.3 RAM
The RAM is a data memory for storing various kinds of data, and has a capacity of 1,792 words × 4 bits.
The RAM area is assigned to addresses 0000H to 06FFH on the data memory map. Addresses 0100H to
01FFH are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data.
When programming, keep the following points in mind.
(1) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay
attention not to overlap the data area and stack area.
(2) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C63466 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access.
After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and
SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts
including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must
be done as a pair.
14
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S1C63466 TECHNICAL MANUAL
CHAPTER 3: CPU, ROM, RAM
(3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use
4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacuation) in the stack area for 4-bit data.
0000H
4-bit access area
(SP2 stack area)
00FFH
0100H
4/16-bit access area
(SP1 stack area)
01FFH
0200H
4-bit access area
(Data area)
06FFH
4 bits
Fig. 3.3.1 Configuration of data RAM
3.4 Data ROM
The data ROM is a mask ROM for loading various static data such as a character generator, and has a
capacity of 2,048 words × 4 bits. The data ROM is assigned to addresses 8000H to 87FFH on the data
memory map, and the data can be read using the same data memory access instructions as the RAM.
S1C63466 TECHNICAL MANUAL
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15
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER
4 PERIPHERAL CIRCUITS AND OPERATION
The peripheral circuits of S1C63466 (timer, I/O, etc.) are interfaced with the CPU in the memory
mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on
the memory map using the memory operation instructions. The following sections explain the detailed
operation of each peripheral circuit.
4.1 Memory Map
The S1C63466 data memory consists of 1,792-word RAM, 2,048-word data ROM, 1,020-bit display
memory and 67-word peripheral I/O memory. Figure 4.1.1 shows the overall memory map of the
S1C63466, and Tables 4.1.1(a)–(e) the peripheral circuits' (I/O space) memory maps.
0000H
RAM area
0700H
F000H
Unused area
Display memory area
8000H
F277H
Data ROM area
8800H
Unused area
Unused area
F000H
FF00H
FFFFH
FF00H
FF80H
FFC0H
FFFFH
I/O memory area
Peripheral I/O area
Unused area
Peripheral I/O area
Fig. 4.1.1 Memory map
Note: Memory is not implemented in unused areas within the memory map. Further, some non-implementation areas and unused (access prohibition) areas exist in the display memory area and the
peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be
guaranteed. Refer to Section 4.7.5, "Display memory", for the display memory, and the I/O
memory maps shown in Tables 4.1.1 (a)–(e) for the peripheral I/O area.
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S1C63466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (a) I/O memory map (FF00H–FF31H)
Address
Register
D3
D2
D1
D0
CLKCHG OSCC
0
VDC
R/W
R
R/W
FF00H
SVDS3 SVDS2 SVDS1 SVDS0
FF04H
R/W
0
0
SVDDT SVDON
FF05H
R
R/W
FOUTE
0
FOFQ1 FOFQ0
R/W
R
R/W
0
0
WDEN WDRST
FF06H
FF07H
R
SIK03
SIK02
R/W
W
SIK01
SIK00
FF20H
R/W
K03
K02
K01
K00
FF21H
R
KCP03 KCP02 KCP01 KCP00
FF22H
R/W
SIK13
SIK12
SIK11
SIK10
FF24H
R/W
K13
K12
K11
K10
FF25H
R
KCP13 KCP12 KCP11 KCP10
FF26H
R/W
R03HIZ R02HIZ R01HIZ R00HIZ
FF30H
R/W
R03
R02
R01
FF31H
R/W
R00
Comment
Name Init ∗1
1
0
CLKCHG
0
OSC3 OSC1 CPU clock switch
OSCC
OSC3 oscillation On/Off
0
On
Off
0 ∗3
Unused
– ∗2
VDC
0
2.2 V
1.3 V CPU operating voltage switch (1.3 V: OSC1, 2.2 V: OSC3)
SVDS3
SVD criteria voltage setting
0
1
2
3
4
5
6
7
[SVDS3–0] 0
SVDS2
0
Voltage(V) 1.85/1.05 1.90 2.00 2.10 2.20 2.30 2.40 2.50
SVDS1
0
[SVDS3–0] 8
9
10
11
12
13
14
15
SVDS0
0
Voltage(V) 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30
0 ∗3
Unused
– ∗2
0 ∗3
– ∗2
Unused
SVDDT
0
Low Normal SVD evaluation data
SVDON
0
On
Off
SVD circuit On/Off
FOUTE
0
Enable Disable FOUT output enable
0 ∗3
Unused
– ∗2
FOUT
FOFQ1
0
1
2
[FOFQ1, 0]
0
3
frequency
Frequency fOSC1/64 fOSC1/8 fOSC1 fOSC3
FOFQ0
0
selection
0 ∗3
– ∗2
Unused
0 ∗3
– ∗2
Unused
WDEN
1
Enable Disable Watchdog timer enable
WDRST∗3 Reset Reset Invalid Watchdog timer reset (writing)
SIK03
0
Enable Disable
SIK02
0
Enable Disable
K00–K03 interrupt selection register
SIK01
0
Enable Disable
SIK00
0
Enable Disable
K03
– ∗2 High
Low
K02
– ∗2 High
Low
K00–K03 input port data
K01
– ∗2 High
Low
K00
– ∗2 High
Low
KCP03
1
KCP02
1
K00–K03 input comparison register
KCP01
1
KCP00
1
SIK13
0
Enable Disable
SIK12
0
Enable Disable
K10–K13 interrupt selection register
SIK11
0
Enable Disable
SIK10
0
Enable Disable
K13
– ∗2 High
Low
K12
– ∗2 High
Low
K10–K13 input port data
K11
– ∗2 High
Low
K10
– ∗2 High
Low
KCP13
1
KCP12
1
K10–K13 input comparison register
KCP11
1
KCP10
1
High-Z Output R03 output high impedance control (FOUTE=0)
0
R03HIZ
FOUT output high impedance control (FOUTE=1)
High-Z Output R02 output high impedance control (PTOUT=0)
0
R02HIZ
TOUT output high impedance control (PTOUT=1)
High-Z Output R01 output high impedance control
0
R01HIZ
High-Z Output R00 output high impedance control
0
R00HIZ
R03
1
High
Low R03 output port data (FOUTE=0) Fix at "1" when FOUT is used
R02
1
High
Low R02 output port data (PTOUT=0) Fix at "1" when TOUT is used
R01
1
High
Low R01 output port data
R00
1
High
Low R00 output port data
Remarks
∗1 Initial value at initial reset
∗2 Not set in the circuit
∗3 Constantly "0" when being read
S1C63466 TECHNICAL MANUAL
EPSON
17
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (b) I/O memory map (FF32H–FF46H)
Address
Register
D3
D2
D1
0
0
0
FF32H
R
R13
R12
R11
FF33H
R/W
0
0
0
FF34H
R
R23
R22
R21
FF35H
R/W
IOC03
IOC02
IOC01
FF40H
R/W
PUL03
PUL02
PUL01
FF41H
R/W
P03
P02
P01
FF42H
R/W
IOC13
IOC12
IOC11
IOC10
R/W
PUL12
PUL11
High-Z
High
High
High
High
Output
Output
Output
Output
On
On
On
On
High
High
High
High
Output
IOC12
0
Output
IOC11
0
Output
IOC10
0
Output
PUL13
1
On
PUL12
1
On
PUL11
1
On
PUL10
1
On
P13
– ∗2
High
P12
– ∗2
High
P11
– ∗2
High
P10
– ∗2
High
Name
0 ∗3
R1HIZ
0 ∗3
0 ∗3
R/W
R1HIZ
R13
R10
R12
R11
R10
0 ∗3
R2HIZ
0 ∗3
0 ∗3
R/W
R2HIZ
R23
R20
R22
R21
R20
IOC03
IOC00
IOC02
IOC01
IOC00
PUL03
PUL00
PUL02
PUL01
PUL00
P03
P00
P02
P01
P00
IOC13
FF44H
PUL13
Init ∗1
– ∗2
– ∗2
– ∗2
0
1
1
1
1
– ∗2
– ∗2
– ∗2
0
1
1
1
1
0
0
0
0
1
1
1
1
– ∗2
– ∗2
– ∗2
– ∗2
0
D0
PUL10
1
High-Z
High
High
High
High
FF45H
R/W
P13
P12
P11
FF46H
R/W
18
P10
0
Comment
Unused
Unused
Unused
Output R1 output high impedance control
Low
Low
R10–R13 output port data
Low
Low
Unused
Unused
Unused
Output R2 output high impedance control
Low
Low
R20–R23 output port data
Low
Low
Input
Input
P00–P03 I/O control register
Input
Input
Off
Off
P00–P03 pull-up control register
Off
Off
Low
Low
P00–P03 I/O port data
Low
Low
Input P13 I/O control register
functions as a general-purpose register when SIF (slave) is selected
Input P12 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Input P11 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Input P10 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Off
P13 pull-up control register
functions as a general-purpose register when SIF (slave) is selected
Off
P12 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-up control register when SIF (slave) is selected
Off
P11 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Off
P10 pull-up control register (ESIF=0)
SIN pull-up control register when SIF is selected
Low P13 I/O port data
functions as a general-purpose register when SIF (slave) is selected
Low P12 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
Low P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
Low P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (c) I/O memory map (FF48H–FF71H)
Address
Register
D3
D2
D1
D0
IOC23
IOC22
IOC21
IOC20
FF48H
R/W
PUL23
PUL22
PUL21
R/W
P22
Init ∗1
0
1
Output
0
Input
IOC22
0
Output
Input
IOC21
IOC20
PUL23
0
0
1
Output
Output
On
Input
Input
Off
PUL22
1
On
Off
PUL21
PUL20
P23
1
1
– ∗2
On
On
High
Off
Off
Low
P22
– ∗2
High
Low
PUL20
FF49H
P23
Name
IOC23
P21
P20
FF4AH
LC3
LC2
LC1
LC0
FF62H
R/W
ENRTM ENRST ENON
BZE
FF6CH
R/W
W
0
R/W
BZSTP BZSHT SHTPW
FF6DH
R
W
R/W
0
BZFQ2 BZFQ1 BZFQ0
R
R/W
0
BDTY2 BDTY1 BDTY0
R
R/W
FF6EH
FF6FH
0
0
SCTRG
ESIF
FF70H
R
SDP
R/W
SCPS
SCS1
FF71H
R/W
S1C63466 TECHNICAL MANUAL
SCS0
P23 I/O control register (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 I/O control register (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 I/O control register
P20 I/O control register
P23 pull-up control register (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 pull-up control register (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 pull-up control register
P20 pull-up control register
P23 I/O port data (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 I/O port data (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 I/O port data
P20 I/O port data
Low
– ∗2 High
Low
– ∗2 High
LCD drive duty
0
[LDUTY1, 0]
0
1
2, 3
Duty
1/17
1/16
1/8
switch
0
VC1 LCD regulated voltage switch
0
VC2
On
Off
LCD power On/Off
0
0
Enable Disable Expanded LCD driver signal control
1
All Off Normal LCD all OFF control
0
All On Normal LCD all ON control
F100-F177 F000-F077 Display memory area selection (when 1/8 duty is selected)
0
functions as a general-purpose register when 1/16, 1/17 duty is selected
LC3
LCD contrast adjustment
– ∗2
LC2
– ∗2
[LC3–0]
0
–
15
LC1
– ∗2
Contrast
Light
–
Dark
– ∗2
LC0
ENRTM
0
1 sec 0.5 sec Envelope releasing time
ENRST∗3 Reset Reset Invalid Envelope reset (writing)
ENON
Envelope On/Off
0
On
Off
BZE
0
Enable Disable Buzzer output enable
– ∗2
0 ∗3
Unused
BZSTP∗3
0
Stop
Invalid 1-shot buzzer stop (writing)
BZSHT
0
Trigger Invalid 1-shot buzzer trigger (writing)
Busy Ready 1-shot buzzer status (reading)
SHTPW
0
125 msec 31.25 msec 1-shot buzzer pulse width setting
0 ∗3
Unused
– ∗2
[BZFQ2, 1, 0]
0
1
2
3
BZFQ2
0
Buzzer
Frequency (Hz) 4096.0 3276.8 2730.7 2340.6
BZFQ1
0
frequency
[BZFQ2, 1, 0]
4
5
6
7
Frequency (Hz) 2048.0 1638.4 1365.3 1170.3
BZFQ0
0
selection
0 ∗3
Unused
– ∗2
BDTY2
0
Buzzer signal duty ratio selection
BDTY1
0
(refer to main manual)
BDTY0
0
– ∗2
0 ∗3
Unused
0 ∗3
– ∗2
Unused
SCTRG
0
Trigger Invalid Serial I/F clock trigger (writing)
Run
Stop Serial I/F clock status (reading)
ESIF
0
SIF
Serial I/F enable (P1 port function selection)
I/O
MSB first LSB first Serial I/F data input/output permutation
SDP
0
Serial I/F clock phase selection
SCPS
0
–Negative polarity (mask option)
0
1
[SCS1, 0]
–Positive polarity (mask option)
Slave
PT
Clock
SCS1
0
Serial I/F
2
3
[SCS1, 0]
SCS0
0
clock mode selection
OSC1/2 OSC1
Clock
P21
P20
LDUTY1
LDUTY1 LDUTY0 VCCHG LPWR
LDUTY0
FF60H
VCCHG
R/W
LPWR
EXLCDC
EXLCDC ALOFF ALON LPAGE ALOFF
ALON
FF61H
LPAGE
R/W
R/W
Comment
EPSON
19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (d) I/O memory map (FF72H–FFC7H)
Address
Register
D3
D2
D1
SD3
SD2
SD1
FF72H
R/W
SD7
SD6
SD5
FF73H
R/W
0
0
TMRST
FF78H
R
W
TM3
TM2
TM1
FF79H
R
TM7
TM6
TM5
FF7AH
R
0
0
SWRST
FF7CH
R
SWD3
W
SWD2
SWD1
FF7DH
R
SWD7
SWD6
SWD5
FF7EH
R
0
EVCNT FCSEL
FFC0H
R
R/W
CHSEL PTOUT CKSEL1
FFC1H
R/W
PTPS01 PTPS00 PTRST0
FFC2H
R/W
W
PTPS11 PTPS10 PTRST1
FFC3H
R/W
RLD03
W
RLD02
RLD01
FFC4H
R/W
RLD07
RLD06
RLD05
FFC5H
R/W
RLD13
RLD12
RLD11
FFC6H
R/W
RLD17
RLD16
RLD15
FFC7H
R/W
20
1
Name Init ∗1
SD3
– ∗2 High
SD0
– ∗2 High
SD2
– ∗2 High
SD1
– ∗2 High
SD0
SD7
– ∗2 High
SD4
– ∗2 High
SD6
– ∗2 High
SD5
– ∗2 High
SD4
– ∗2
0 ∗3
TMRUN
0 ∗3
– ∗2
TMRST∗3 Reset Reset
R/W
TMRUN
0
Run
TM3
0
TM0
TM2
0
TM1
0
TM0
0
TM7
0
TM4
TM6
0
TM5
0
TM4
0
– ∗2
0 ∗3
SWRUN
0 ∗3
– ∗2
SWRST∗3 Reset Reset
R/W
SWRUN
0
Run
SWD3
0
SWD0
SWD2
0
SWD1
0
SWD0
0
SWD7
0
SWD4
SWD6
0
SWD5
0
SWD4
0
0 ∗3
– ∗2
PLPOL
EVCNT
0
Event ct.
FCSEL
0
With NR
PLPOL
0
CHSEL
0
Timer1
CKSEL0
PTOUT
0
On
CKSEL1
0
OSC3
CKSEL0
0
OSC3
0
PTPS01
PTRUN0
0
PTPS00
PTRST0∗3
– ∗2 Reset
R/W
PTRUN0
0
Run
0
PTPS11
PTRUN1
0
PTPS10
PTRST1∗3
– ∗2 Reset
R/W
PTRUN1
0
Run
RLD03
0
RLD00
RLD02
0
RLD01
0
RLD00
0
RLD07
0
RLD04
RLD06
0
RLD05
0
RLD04
0
RLD13
0
RLD10
RLD12
0
RLD11
0
RLD10
0
RLD17
0
RLD14
RLD16
0
RLD15
0
RLD14
0
D0
0
Low
Low
Low
Low
Low
Low
Low
Low
Comment
MSB
Serial I/F transmit/receive data (low-order 4 bits)
LSB
MSB
Serial I/F transmit/receive data (high-order 4 bits)
LSB
Unused
Unused
Invalid Clock timer reset (writing)
Stop Clock timer Run/Stop
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Unused
Unused
Invalid Stopwatch timer reset (writing)
Stop Stopwatch timer Run/Stop
Stopwatch timer data
BCD (1/100 sec)
Stopwatch timer data
BCD (1/10 sec)
Unused
Timer Timer 0 counter mode selection
No NR Timer 0 function selection (for event counter mode)
Timer 0 pulse polarity selection (for event counter mode)
Timer0 TOUT output channel selection
TOUT output control
Off
OSC1 Prescaler 1 source clock selection
OSC1 Prescaler 0 source clock selection
Prescaler 0
[PTPS01, 00]
0
1
2
3
division ratio
Division ratio 1/1
1/4 1/32 1/256
selection
Invalid Timer 0 reset (reload)
Stop Timer 0 Run/Stop
Prescaler 1
[PTPS11, 10]
division ratio
Division ratio
selection
0
1/1
1
1/4
2
3
1/32 1/256
Invalid Timer 1 reset (reload)
Stop Timer 1 Run/Stop
MSB
EPSON
Programmable timer 0 reload data (low-order 4 bits)
LSB
MSB
Programmable timer 0 reload data (high-order 4 bits)
LSB
MSB
Programmable timer 1 reload data (low-order 4 bits)
LSB
MSB
Programmable timer 1 reload data (high-order 4 bits)
LSB
S1C63466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (e) I/O memory map (FFC8H–FFF7H)
Address
Register
D3
D2
D1
D0
PTD03
PTD02
PTD01
PTD00
FFC8H
R
PTD07
PTD06
PTD05
PTD04
FFC9H
R
PTD13
PTD12
PTD11
PTD10
FFCAH
R
PTD17
PTD16
PTD15
PTD14
FFCBH
R
0
0
EIPT1
EIPT0
FFE2H
R
0
R/W
0
0
EISIF
FFE3H
R
0
R/W
0
0
EIK0
FFE4H
R
0
R/W
0
0
EIK1
FFE5H
R
EIT3
R/W
EIT2
EIT1
EIT0
FFE6H
R/W
0
0
EISW1 EISW10
FFE7H
R
0
R/W
0
IPT1
IPT0
FFF2H
R
0
R/W
0
0
ISIF
FFF3H
R
0
R/W
0
0
IK0
FFF4H
R
0
R/W
0
0
IK1
FFF5H
R
IT3
R/W
IT2
IT1
IT0
ISW1
ISW10
FFF6H
R/W
0
0
FFF7H
R
R/W
S1C63466 TECHNICAL MANUAL
Name Init ∗1
PTD03
0
PTD02
0
PTD01
0
PTD00
0
PTD07
0
PTD06
0
PTD05
0
PTD04
0
PTD13
0
PTD12
0
PTD11
0
PTD10
0
PTD17
0
PTD16
0
PTD15
0
PTD14
0
0 ∗3
– ∗2
0 ∗3
– ∗2
EIPT1
0
EIPT0
0
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
EISIF
0
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
EIK0
0
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
EIK1
0
EIT3
0
EIT2
0
EIT1
0
EIT0
0
0 ∗3
– ∗2
0 ∗3
– ∗2
EISW1
0
EISW10
0
0 ∗3
– ∗2
0 ∗3
– ∗2
IPT1
0
IPT0
0
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
ISIF
0
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
IK0
0
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
IK1
0
IT3
0
IT2
0
IT1
0
IT0
0
0 ∗3
– ∗2
0 ∗3
– ∗2
ISW1
0
ISW10
0
1
Comment
0
MSB
Programmable timer 0 data (low-order 4 bits)
LSB
MSB
Programmable timer 0 data (high-order 4 bits)
LSB
MSB
Programmable timer 1 data (low-order 4 bits)
LSB
MSB
Programmable timer 1 data (high-order 4 bits)
Enable
Enable
Mask
Mask
Enable
Mask
Enable
Mask
Enable
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Mask
Enable
Enable
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
Mask
Mask
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
EPSON
LSB
Unused
Unused
Interrupt mask register (Programmable timer 1)
Interrupt mask register (Programmable timer 0)
Unused
Unused
Unused
Interrupt mask register (Serial I/F)
Unused
Unused
Unused
Interrupt mask register (K00–K03)
Unused
Unused
Unused
Interrupt mask register (K10–K13)
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 8 Hz)
Interrupt mask register (Clock timer 32 Hz)
Unused
Unused
Interrupt mask register (Stopwatch timer 1 Hz)
Interrupt mask register (Stopwatch timer 10 Hz)
Unused
Unused
Interrupt factor flag (Programmable timer 1)
Interrupt factor flag (Programmable timer 0)
Unused
Unused
Unused
Interrupt factor flag (Serial I/F)
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
Unused
Unused
Unused
Interrupt factor flag (K10–K13)
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 32 Hz)
Unused
Unused
Interrupt factor flag (Stopwatch timer 1 Hz)
Interrupt factor flag (Stopwatch timer 10 Hz)
21
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
4.2 Watchdog Timer
4.2.1 Configuration of watchdog timer
The S1C63466 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as
the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the
software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog
timer is not reset in at least 3–4 seconds, it generates a non-maskable interrupt (NMI) to the CPU.
Figure 4.2.1.1 is the block diagram of the watchdog timer.
Watchdog timer
OSC1 dividing signal 256 Hz
Non-maskable
interrupt (NMI)
Watchdog timer enable signal
Watchdog timer reset signal
Fig. 4.2.1.1 Watchdog timer block diagram
The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the
last stage of the counter (0.25 Hz) overflows.
Watchdog timer reset processing in the program's main routine enables detection of program overrun,
such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is
incorporated where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the nonmaskable interrupt releases the HALT status.
4.2.2 Interrupt function
If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core
CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag =
"0"). However, it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a
pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is
assigned to 0100H in the program memory.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
4.2.3 I/O memory of watchdog timer
Table 4.2.3.1 shows the I/O address and control bits for the watchdog timer.
Table 4.2.3.1 Control bits of watchdog timer
Address
Register
D3
D2
0
0
FF07H
R
Comment
1
0
Name Init ∗1
0 ∗3
– ∗2
Unused
WDEN WDRST
0 ∗3
– ∗2
Unused
WDEN
1
Enable Disable Watchdog timer enable
R/W
W
WDRST∗3 Reset Reset Invalid Watchdog timer reset (writing)
D1
D0
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
WDEN: Watchdog timer enable register (FF07H•D1)
Selects whether the watchdog timer is used (enabled) or not (disabled).
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
When "1" is written to the WDEN register, the watchdog timer starts count operation. When "0" is written,
the watchdog timer does not count and does not generate the interrupt (NMI).
At initial reset, this register is set to "1".
WDRST: Watchdog timer reset (FF07H•D0)
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading: Always "0"
When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0"
is written, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
4.2.4 Programming notes
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.
(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled
state (not used) before generating an interrupt (NMI) if it is not used.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3 Oscillation Circuit
4.3.1 Configuration of oscillation circuit
The S1C63466 has two oscillation circuits (OSC1 and OSC3). OSC1 is either a crystal or a CR oscillation
circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a
ceramic oscillation circuit. When processing with the S1C63466 requires high-speed operation, the CPU
operating clock can be switched from OSC1 to OSC3 by the software. To stabilize operation of the internal
circuits, the operating voltage VD1 must be switched according to the oscillation circuit to be used. Figure
4.3.1.1 is the block diagram of this oscillation system.
OSC1
oscillation circuit
Divider
To peripheral circuits
Clock
switch
OSC3
oscillation circuit
To CPU
CPU clock selection signal
Oscillation circuit control signal
V D1 Oscillation system
voltage regulator
Operating voltage selection signal
Fig. 4.3.1.1 Oscillation system block diagram
4.3.2 OSC1 oscillation circuit
The OSC1 oscillation circuit generates the main clock for the CPU and the peripheral circuits. Either the
crystal oscillation circuit or the CR oscillation circuit can be selected as the circuit type by mask option.
The oscillation frequency of the crystal oscillation circuit is 32.768 kHz (Typ.) and the CR oscillation
circuit is 60 kHz (Typ.).
Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit.
CGX
RDX
To CPU
(and peripheral circuits)
RFX
X'tal
OSC1
C DX
OSC2
V SS
V SS
(a) Crystal oscillation circuit
OSC1
RCR1
To CPU
(and peripheral circuits)
OSC2
C CR
(b) CR oscillation circuit
Fig. 4.3.2.1 OSC1 oscillation circuit
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
As shown in Figure 4.3.2.1, the crystal oscillation circuit can be configured simply by connecting the
crystal oscillator (X'tal) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer
capacitor (CGX) between the OSC1 and VSS terminals when crystal oscillation is selected.
The CR oscillation circuit can be configured simply by connecting the resistor RCR1 between the OSC1
and OSC2 terminals when CR oscillation is selected. See Chapter 7, "Electrical Characteristics" for resistance value of RCR1.
Note: • The current consumption of CR oscillation is larger than crystal oscillation.
• Be aware that the CR oscillation frequency changes slightly.
Pay special attention to the circuits that use fOSC1 as the source clock, such as the timer (time
lag), the LCD frame frequency (display quality, flicker in low frequency) and the sound generator
(sound quality).
4.3.3 OSC3 oscillation circuit
The S1C63466 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz)
for high speed operation and the source clock for peripheral circuits needing a high speed clock (programmable timer, FOUT output). The mask option enables selection of either the CR or ceramic oscillation circuit. When CR oscillation is selected, only a resistance is required as an external element. When
ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are
required.
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
C CR
RCR2
OSC3
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
OSC4
(a) CR oscillation circuit
C GC
VSS
To CPU
(and some peripheral circuits)
RFC
Ceramic
CDC
OSC3
OSC4
RDC
Oscillation circuit control signal
(b) Ceramic oscillation circuit
Fig. 4.3.3.1 OSC3 oscillation circuit
As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
RCR2 between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 7, "Electrical
Characteristics" for resistance value of RCR2.
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3
and OSC4 terminals, and capacitor CDC between the OSC4 and VSS terminals. For both CGC and CDC,
connect capacitors that are about 30 pF. To reduce current consumption of the OSC3 oscillation circuit,
oscillation can be stopped by the software (OSCC register).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.4 Switching of operating voltage
(1) When OSC1 crystal oscillation circuit is used
The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register). In this case,
to obtain stable operation, the operating voltage VD1 for the internal circuits must be switched by the
software (VDC register).
OSC1 (crystal oscillation) operation:
OSC3 operation:
VD1 = 1.3 V
VD1 = 2.2 V
(VDC = "0")
(VDC = "1")
When OSC3 is to be used as the CPU system clock, it should be done as the following procedure using
the software: first switch the operating voltage VD1, turn the OSC3 oscillation ON after waiting 2.5
msec or more for the above operation to stabilize, switch the clock after waiting 5 msec or more for
oscillation stabilization.
When switching from OSC3 to OSC1, turn the OSC3 oscillation circuit OFF after switching the clock
then set the operating voltage VD1 to 1.3 V.
OSC1 → OSC3
1. Set VDC to "1" (1.3 V → 2.2 V).
2. Maintain 2.5 msec or more.
3. Set OSCC to "1" (OSC3 oscillation ON).
4. Maintain 5 msec or more.
5. Set CLKCHG to "1" (OSC1 → OSC3).
OSC3 → OSC1
1. Set CLKCHG to "0" (OSC3 → OSC1).
2. Set OSCC to "0" (OSC3 oscillation OFF).
3. Set VDC to "0" (2.2 V → 1.3 V).
(2) When OSC1 CR oscillation circuit is used
When the CR oscillation circuit has been selected as the OSC1 oscillation circuit by mask option, 2.2 V
of VD1 necessary to operate with OSC1 and OSC3.
OSC1 (CR oscillation) operation:
OSC3 operation:
VD1 = 2.2 V
VD1 = 2.2 V
Since the S1C63466 fixes the VD1 voltage value at 2.2 V when the CR oscillation circuit is selected as
the OSC1 oscillation circuit by mask option, it is not necessary to switch the operating voltage VD1 by
software (VDC register). However, software control to switch the CPU system clock using the
CLKCHG register is necessary.
When OSC3 is to be used as the CPU system clock, it should be done as the following procedure using
the software: turn the OSC3 oscillation ON, switch the clock after waiting 5 msec or more for oscillation stabilization.
When switching from OSC3 to OSC1, turn the OSC3 oscillation circuit OFF after switching the clock.
OSC1 → OSC3
1. Set OSCC to "1" (OSC3 oscillation ON).
2. Maintain 5 msec or more.
3. Set CLKCHG to "1" (OSC1 → OSC3).
OSC3 → OSC1
1. Set CLKCHG to "0" (OSC3 → OSC1).
2. Set OSCC to "0" (OSC3 oscillation OFF).
4.3.5 Clock frequency and instruction execution time
Table 4.3.5.1 shows the instruction execution time according to each frequency of the system clock.
Table 4.3.5.1 Clock frequency and instruction execution time
Clock frequency
OSC1: 32.768 kHz
OSC1: 60 kHz
OSC3: 4 MHz
26
Instruction execution time (µsec)
1-cycle instruction 2-cycle instruction 3-cycle instruction
61
122
183
33
67
100
0.5
1
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.6 I/O memory of oscillation circuit
Table 4.3.6.1 shows the I/O address and the control bits for the oscillation circuit.
Table 4.3.6.1 Control bits of oscillation circuit
Address
Register
D3
D2
D1
D0
CLKCHG OSCC
0
VDC
R/W
R
R/W
FF00H
Name Init ∗1
CLKCHG
0
OSCC
0
0 ∗3
– ∗2
VDC
0
1
OSC3
On
2.2 V
Comment
0
OSC1 CPU clock switch
OSC3 oscillation On/Off
Off
Unused
1.3 V CPU operating voltage switch (1.3 V: OSC1, 2.2 V: OSC3)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
VDC: CPU operating voltage switching register (FF00H•D0)
It is used to switch the operating voltage VD1, when the crystal oscillation circuit has been selected as the
OSC1 oscillation circuit by mask option.
When "1" is written: 2.2 V (for OSC3 operation)
When "0" is written: 1.3 V (for OSC1 operation)
Reading: Valid
When switching the CPU system clock, the operating voltage VD1 should also be switched according to
the clock.
When switching from OSC1 to OSC3, first set VD1 to 2.2 V. After that maintain 2.5 msec or more, and then
turn the OSC3 oscillation ON.
When switching from OSC3 to OSC1, set VD1 to 1.3 V after switching to OSC1 and turning the OSC3
oscillation OFF.
When the CR oscillation circuit has been selected as the OSC1 oscillation circuit by mask option, setting
of this register does not affect the operating voltage VD1, and the VD1 voltage is fixed at 2.2 V.
At initial reset, this register is set to "0".
OSCC: OSC3 oscillation control register (FF00H•D2)
Controls oscillation ON/OFF for the OSC3 oscillation circuit.
When "1" is written: OSC3 oscillation ON
When "0" is written: OSC3 oscillation OFF
Reading: Valid
When it is necessary to operate the CPU at high speed, set OSCC to "1". At other times, set it to "0" to
reduce current consumption. Furthermore, when the crystal oscillation circuit has been selected as the
OSC1 oscillation circuit by mask option, it is necessary to switch the operating voltage VD1 when turning
the OSC3 oscillation circuit ON and OFF
At initial reset, this register is set to "0".
CLKCHG: CPU system clock switching register (FF00H•D3)
The CPU's operation clock is selected with this register.
When "1" is written: OSC3 clock is selected
When "0" is written: OSC1 clock is selected
Reading: Valid
When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0".
After turning the OSC3 oscillation ON (OSCC = "1"), switching of the clock should be done after waiting
5 msec or more.
When VD1 is 1.3 V (VDC = "0") and when OSC3 oscillation is OFF (OSCC = "0"), setting of CLKCHG = "1"
becomes invalid and switching to OSC3 is not performed. When the CR oscillation circuit has been
selected as the OSC1 oscillation circuit by mask option, setting VDC to "0" makes no difference.
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.7 Programming notes
(1) When switching the CPU system clock from OSC1 to OSC3, first set VD1. After that maintain 2.5 msec
or more, and then turn the OSC3 oscillation ON.
When switching from OSC3 to OSC1, set VD1 after switching to OSC1 and turning the OSC3 oscillation OFF. However, when the CR oscillation circuit has been selected as the OSC1 oscillation circuit, it
is not necessary to set VD1.
(2) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(3) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation OFF. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(4) When the CR oscillation circuit has been selected as the OSC1 oscillation circuit by mask option, it is
not necessary to switch the operating voltage VD1 using the VDC register and the VD1 voltage is fixed
at 2.2 V. The VD1 level does not change even if any data is written to the VDC register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4 Input Ports (K00–K03 and K10–K13)
4.4.1 Configuration of input ports
The S1C63466 has eight bits general-purpose input ports. Each of the input port terminals (K00–K03,
K10–K13) provides internal pull-up resistor. Pull-up resistor can be selected for each bit with the mask
option.
Figure 4.4.1.1 shows the configuration of input port.
Interrupt
request
Kxx
Data bus
VDD
Address
VSS
Mask option
Fig. 4.4.1.1 Configuration of input port
Selection of "With pull-up resistor" with the mask option suits input from the push switch, key matrix,
and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing
with other LSIs.
4.4.2 Interrupt function
All eight bits of the input ports (K00–K03, K10–K13) provide the interrupt function. The conditions for
issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be
selected by the software.
Figure 4.4.2.1 shows the configuration of K00–K03 (K10–K13) interrupt circuit.
K00, 10
Address
Address
Data bus
Input comparison
register (KCP00, 10)
Interrupt factor
flag (IK0, 1)
Interrupt
request
Address
Interrupt selection
register (SIK00, 10)
Interrupt mask
register (EIK0, 1)
Address
Address
K01, 11
K02, 12
K03, 13
Fig. 4.4.2.1 Input interrupt circuit configuration
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the
input ports K00–K03 and K10–K13, and can specify the terminals for generating interrupt and interrupt
timing.
The interrupt selection registers (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13
to use for the interrupt. Writing "1" into an interrupt selection register incorporates that input port into
the interrupt generation conditions. The changing the input port where the interrupt selection register
has been set to "0" does not affect the generation of the interrupt.
The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that
it be generated at the falling edge according to the set value of the input comparison registers (KCP00–
KCP03, KCP10–KCP13).
By setting these two conditions, the interrupt for K00–K03 or K10–K13 is generated when input ports in
which an interrupt has been enabled by the input selection registers and the contents of the input comparison registers have been changed from matching to no matching.
The interrupt mask registers (EIK0, EIK1) enable the interrupt mask to be selected for K00–K03 and K10–
K13.
When the interrupt is generated, the interrupt factor flag (IK0, IK1) is set to "1".
Figure 4.4.2.2 shows an example of an interrupt for K00–K03.
Interrupt selection register
SIK03
1
SIK02
1
SIK01
1
SIK00
0
Input comparison register
KCP03 KCP02 KCP01 KCP00
1
0
1
0
With the above setting, the interrupt of K00–K03 is generated under the following condition:
Input port
(1)
K03
1
K02
0
K01
1
K00
0
(2)
K03
1
K02
0
K01
1
K00
1
(3)
K03
0
K02
0
K01
1
K00
1
K03
K02
K01
K00
0
1
1
1
(4)
(Initial value)
Interrupt generation
Because K00 interrupt is set to disable, interrupt will be
generated when no matching occurs between the
contents of the 3 bits K01–K03 and the 3 bits input
comparison register KCP01–KCP03.
Fig. 4.4.2.2 Example of interrupt of K00–K03
K00 interrupt is disabled by the interrupt selection register (SIK00), so that an interrupt does not occur at
(2). At (3), K03 changes to "0"; the data of the terminals that are interrupt enabled no longer match the
data of the input comparison registers, so that interrupt occurs. As already explained, the condition for
the interrupt to occur is the change in the port data and contents of the input comparison registers from
matching to no matching. Hence, in (4), when the no matching status changes to another no matching
status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect
the conditions for interrupt generation.
4.4.3 Mask option
Internal pull-up resistor can be selected for each of the eight bits of the input ports (K00–K03, K10–K13)
with the input port mask option.
When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With
pull-up resistor" for input ports that are not being used. When using the QFP5-128pin package, "With
pull-up resistor" option should be chosen for the K12 input port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.4 I/O memory of input ports
Table 4.4.4.1 shows the I/O addresses and the control bits for the input ports.
Table 4.4.4.1 Control bits of input ports
Address
FF20H
FF21H
FF22H
FF24H
FF25H
FF26H
FFE4H
FFE5H
FFF4H
FFF5H
Register
Comment
1
0
Name Init ∗1
SIK03
0
Enable Disable
SIK03 SIK02 SIK01 SIK00
SIK02
0
Enable Disable
K00–K03 interrupt selection register
SIK01
0
Enable Disable
R/W
SIK00
0
Enable Disable
K03
– ∗2 High
Low
K03
K02
K01
K00
K02
– ∗2 High
Low
K00–K03 input port data
K01
– ∗2 High
Low
R
– ∗2 High
K00
Low
KCP03
1
KCP03 KCP02 KCP01 KCP00
KCP02
1
K00–K03 input comparison register
KCP01
1
R/W
KCP00
1
SIK13
0
Enable Disable
SIK13 SIK12 SIK11 SIK10
SIK12
0
Enable Disable
K10–K13 interrupt selection register
SIK11
0
Enable Disable
R/W
SIK10
0
Enable Disable
K13
– ∗2 High
Low
K13
K12
K11
K10
K12
– ∗2 High
Low
K10–K13 input port data
K11
– ∗2 High
Low
R
– ∗2 High
K10
Low
KCP13
1
KCP13 KCP12 KCP11 KCP10
KCP12
1
K10–K13 input comparison register
KCP11
1
R/W
KCP10
1
0 ∗3
– ∗2
Unused
0
0
0
EIK0
0 ∗3
– ∗2
Unused
0 ∗3
– ∗2
Unused
R
R/W
EIK0
0
Enable Mask Interrupt mask register (K00–K03)
0 ∗3
– ∗2
Unused
0
0
0
EIK1
0 ∗3
– ∗2
Unused
0 ∗3
– ∗2
Unused
R
R/W
EIK1
0
Enable Mask Interrupt mask register (K10–K13)
0 ∗3
– ∗2
(R)
Unused
(R)
0
0
0
IK0
0 ∗3
– ∗2
Yes
Unused
No
0 ∗3
– ∗2
(W)
(W) Unused
R
R/W
IK0
0
Reset Invalid Interrupt factor flag (K00–K03)
0 ∗3
Unused
– ∗2
(R)
(R)
0
0
0
IK1
0 ∗3
– ∗2
Unused
Yes
No
0 ∗3
– ∗2
(W)
(W) Unused
R
R/W
IK1
0
Reset Invalid Interrupt factor flag (K10–K13)
D3
D2
D1
D0
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
K00–K03: K0 port input port data (FF21H)
K10–K13: K1 port input port data (FF25H)
Input data of the input port terminals can be read with these registers.
When "1" is read: High level
When "0" is read: Low level
Writing: Invalid
The reading is "1" when the terminal voltage of the eight bits of the input ports (K00–K03, K10–K13) goes
high (VDD), and "0" when the voltage goes low (VSS).
These bits are dedicated for reading, so writing cannot be done.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
SIK00–SIK03: K0 port interrupt selection register (FF20H)
SIK10–SIK13: K1 port interrupt selection register (FF24H)
Selects the ports to be used for the K00–K03 and K10–K13 input interrupts.
When "1" is written: Enable
When "0" is written: Disable
Reading: Valid
Enables the interrupt for the input ports (K00–K03, K10–K13) for which "1" has been written into the
interrupt selection registers (SIK00–SIK03, SIK10–SIK13). The input port set for "0" does not affect the
interrupt generation condition.
At initial reset, these registers are set to "0".
KCP00–KCP03: K0 port input comparison register (FF22H)
KCP10–KCP13: K1 port input comparison register (FF26H)
Interrupt conditions for terminals K00–K03 and K10–K13 can be set with these registers.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading: Valid
The interrupt conditions can be set for the rising or falling edge of input for each of the eight bits (K00–
K03 and K10–K13), through the input comparison registers (KCP00–KCP03 and KCP10–KCP13).
For KCP00–KCP03, a comparison is done only with the ports that are enabled by the interrupt among
K00–K03 by means of the SIK00–SIK03 registers. For KCP10–KCP13, a comparison is done only with the
ports that are enabled by the interrupt among K10–K13 by means of the SIK10–SIK13 registers.
At initial reset, these registers are set to "0".
EIK0: K0 input interrupt mask register (FFE4H•D0)
EIK1: K1 input interrupt mask register (FFE5H•D0)
Masking the interrupt of the input port can be selected with these registers.
When "1" is written: Enable
When "0" is written: Mask
Reading: Valid
With these registers, masking of the input port interrupt can be selected for each of the two systems (K00–
K03, K10–K13).
At initial reset, these registers are set to "0".
IK0: K0 input interrupt factor flag (FFF4H•D0)
IK1: K1 input interrupt factor flag (FFF5H•D0)
These flags indicate the occurrence of input interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags IK0 and IK1 are associated with K00–K03 and K10–K13, respectively. From the
status of these flags, the software can decide whether an input interrupt has occurred.
The interrupt factor flag is set to "1" when the interrupt condition is established regardless of the interrupt
mask register setting. However, the interrupt does not occur to the CPU when the interrupt is masked.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
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4.4.5 Programming notes
(1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is
delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate waiting time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 330 kΩ
(2) The K13 terminal functions as the clock input terminal for the programmable timer, and the input
signal is shared with the input port and the programmable timer. Therefore, when the K13 terminal is
set to the clock input terminal for the programmable timer, take care of the interrupt setting.
(3) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.5 Output Ports (R00–R03, R10–R13 and R20–R23)
4.5.1 Configuration of output ports
The S1C63466 has 12 bits general output ports.
Output specifications of the output ports can be selected individually with the mask option. Two kinds of
output specifications are available: complementary output and N-channel open drain output.
Figure 4.5.1.1 shows the configuration of the output port.
VDD
Data bus
Address
High impedance
control register
Mask option
Data register
Rxx
Address
VSS
Fig. 4.5.1.1 Configuration of output port
The R02 and R03 output terminals are shared with special output terminals (TOUT, FOUT), and this
function is selected by the software.
At initial reset, these are all set to the general purpose output port.
Table 4.5.1.1 shows the setting of the output terminals by function selection.
Table 4.5.1.1 Function setting of output terminals
Terminal
name
R00
R01
Terminal status
at initial reset
R00 (High output)
R01 (High output)
Special output
TOUT
FOUT
R00
R01
R00
R01
R02
R02 (High output)
TOUT
R03
R03 (High output)
FOUT
R10–R13 R10–R13 (High output) R10–R13 R10–R13
R20–R23 R20–R23 (High output) R20–R23 R20–R23
When using the output port (R02, R03) as the special output port, the data register must be fixed at "1"
and the high impedance control register must be fixd at "0" (data output).
4.5.2 Mask option
Output specifications of the output ports can be selected with the mask option.
The output specifications of the output ports R10–R13 and R20–R23 can be selected from either complementary output or N-channel open drain output individually (each of 4bits). The output ports R00–R03
can only be used as complementary output.
However, when N-channel open drain output is selected, do not apply a voltage exceeding the power
supply voltage to the output port.
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4.5.3 High impedance control
The terminal output status of the output ports can be set to a high impedance status. This control is done
using the high impedance control registers.
The high impedance control registers are provided to correspond with the output ports as shown below.
High impedance control register
R00HIZ
R01HIZ
R02HIZ
R03HIZ
R1HIZ
R2HIZ
Corresponding output port
R00 (1-bit)
R01 (1-bit)
R02 (1-bit)
R03 (1-bit)
R10–R13 (4-bit)
R20–R23 (4-bit)
When "1" is written to the high impedance control register, the corresponding output port terminal goes
into high impedance status. When "0" is written, the port outputs a signal according to the data register.
4.5.4 Special output
In addition to the regular DC output, special output can be selected for the output ports R02 and R03 as
shown in Table 4.5.4.1 with the software.
Figure 4.5.4.1 shows the configuration of the R02 and R03 output ports.
Table 4.5.4.1 Special output
Terminal
R03
Special output
FOUT
Output control register
FOUTE
R02
TOUT
PTOUT
FOUT
Register
FOUTE
R03
(FOUT)
Data bus
Register
R03
Register
R03HIZ
TOUT
Register
PTOUT
R02
(TOUT)
Register
R02
Register
R02HIZ
Fig. 4.5.4.1 Configuration of R02 and R03 output ports
At initial reset, the output port data register is set to "1" and the high impedance control register is set to
"0". Consequently, the output terminal goes high (VDD).
When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output). The respective signal
should be turned ON and OFF using the special output control register.
Note: • Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R02 and R03 registers when the special output has been selected.
• Be aware that the output terminal shifts into high impedance status when "1" is written to the
high impedance control register (R02HIZ, R03HIZ).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
• TOUT (R02)
The R02 terminal can output a TOUT signal.
The TOUT signal is the clock that is output from the programmable timer, and can be used to provide
a clock signal to an external device.
To output the TOUT signal, fix the R02 register at "1" and the R02HIZ register at "0", and turn the
signal ON and OFF using the PTOUT register. It is, however, necessary to control the programmable
timer.
Refer to Section 4.10, "Programmable Timer" for details of the programmable timer.
Note: A hazard may occur when the TOUT signal is turned ON and OFF.
Figure 4.5.4.2 shows the output waveform of the TOUT signal.
R02HIZ register
Fix at "0"
R02 register
Fix at "1"
PTOUT register
"0"
"1"
"0"
TOUT output
Fig. 4.5.4.2 Output waveform of TOUT signal
• FOUT (R03)
The R03 terminal can output a FOUT signal.
The FOUT signal is a clock (fOSC1 or fOSC3) that is output from the oscillation circuit or a clock that the
fOSC1 clock has divided in the internal circuit, and can be used to provide a clock signal to an external
device.
To output the FOUT signal, fix the R03 register at "1" and the R03HIZ register at "0", and turn the
signal ON and OFF using the FOUTE register.
The frequency of the output clock may be selected from among 4 types shown in Table 4.5.4.2 by
setting the FOFQ0 and FOFQ1 registers.
Table 4.5.4.2 FOUT clock frequency
FOFQ1
1
1
FOFQ0
1
0
Clock frequency
fOSC3
fOSC1
0
1
fOSC1 × 1/8
0
0
fOSC1 × 1/64
fOSC1: Clock that is output from the OSC1 oscillation circuit
fOSC3: Clock that is output from the OSC3 oscillation circuit
When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes.
Note: A hazard may occur when the FOUT signal is turned ON and OFF.
Figure 4.5.4.3 shows the output waveform of the FOUT signal.
R03HIZ register
Fix at "0"
R03 register
Fix at "1"
FOUTE register
"0"
"1"
"0"
FOUT output
Fig. 4.5.4.3 Output waveform of FOUT signal
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4.5.5 I/O memory of output ports
Table 4.5.5.1 shows the I/O addresses and control bits for the output ports.
Table 4.5.5.1 Control bits of output ports
Address
Register
Comment
Name Init ∗1
1
0
FOUTE
0
Enable Disable FOUT output enable
FOUTE
0
FOFQ1 FOFQ0
0 ∗3
Unused
– ∗2
FF06H
FOUT
FOFQ1
0
1
2
[FOFQ1, 0]
0
3
frequency
R/W
R
R/W
Frequency fOSC1/64 fOSC1/8 fOSC1 fOSC3
FOFQ0
0
selection
R03HIZ
0
High-Z Output R03 output high impedance control (FOUTE=0)
FOUT output high impedance control (FOUTE=1)
R03HIZ R02HIZ R01HIZ R00HIZ
R02HIZ
0
High-Z Output R02 output high impedance control (PTOUT=0)
FF30H
TOUT output high impedance control (PTOUT=1)
R01HIZ
0
High-Z Output R01 output high impedance control
R/W
R00HIZ
0
High-Z Output R00 output high impedance control
R03
1
High
Low R03 output port data (FOUTE=0) Fix at "1" when FOUT is used
R03
R02
R01
R00
R02
1
High
Low R02 output port data (PTOUT=0) Fix at "1" when TOUT is used
FF31H
R01
1
High
Low R01 output port data
R/W
R00
1
High
Low R00 output port data
0 ∗3
Unused
– ∗2
0
0
0
R1HIZ
0 ∗3
– ∗2
Unused
FF32H
0 ∗3
– ∗2
Unused
R
R/W
R1HIZ
0
High-Z Output R1 output high impedance control
R13
1
High
Low
R13
R12
R11
R10
R12
1
High
Low
R10–R13 output port data
FF33H
R11
1
High
Low
R/W
R10
1
High
Low
0 ∗3
Unused
– ∗2
0
0
0
R2HIZ
0 ∗3
– ∗2
Unused
FF34H
0 ∗3
– ∗2
Unused
R
R/W
R2HIZ
0
High-Z Output R2 output high impedance control
R23
1
High
Low
R23
R22
R21
R20
R22
1
High
Low
R20–R23 output port data
FF35H
R21
1
High
Low
R/W
R20
1
High
Low
CHSEL
0
Timer1 Timer0 TOUT output channel selection
CHSEL PTOUT CKSEL1 CKSEL0
PTOUT
TOUT output control
0
On
Off
FFC1H
CKSEL1
0
OSC3 OSC1 Prescaler 1 source clock selection
R/W
CKSEL0
0
OSC3 OSC1 Prescaler 0 source clock selection
D3
D2
D1
D0
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
R00HIZ–R03HIZ: R0 port high impedance control register (FF30H)
R1HIZ:
R1 port high impedance control register (FF32H•D0)
R2HIZ:
R2 port high impedance control register (FF34H•D0)
Controls high impedance output of the output port.
When "1" is written: High impedance
When "0" is written: Data output
Reading: Valid
By writing "0" to the high impedance control register, the corresponding output terminal outputs according to the data register. When "1" is written, it shifts into high impedance status.
When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02HIZ register
and the R03HIZ register at "0" (data output).
At initial reset, these registers are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
R00–R03: R0 output port data register (FF31H)
R10–R13: R1 output port data register (FF33H)
R20–R23: R2 output port data register (FF35H)
Set the output data for the output ports.
When "1" is written: High level output
When "0" is written: Low level output
Reading: Valid
The output port terminals output the data written in the corresponding data registers without changing
it. When "1" is written to the register, the output port terminal goes high (VDD), and when "0" is written,
the output port terminal goes low (VSS).
When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02 register and
the R03 register at "1".
At initial reset, these registers are all set to "1".
FOUTE: FOUT output control register (FF06H•D3)
Controls the FOUT output.
When "1" is written: FOUT output ON
When "0" is written: FOUT output OFF
Reading: Valid
By writing "1" to the FOUTE register when the R03 register has been set to "1" and the R03HIZ register
has been set to "0", an FOUT signal is output from the R03 terminal. When "0" is written, the R03 terminal
goes high (VDD).
When using the R03 output port for DC output, fix this register at "0".
At initial reset, this register is set to "0".
FOFQ0, FOFQ1: FOUT frequency selection register (FF06H•D0, D1)
Selects a frequency of the FOUT signal.
Table 4.5.5.2 FOUT clock frequency
FOFQ1
1
FOFQ0
1
Clock frequency
fOSC3
1
0
0
0
1
0
fOSC1
fOSC1 × 1/8
fOSC1 × 1/64
At initial reset, this register is set to "0".
PTOUT: TOUT output control register (FFC1H•D2)
Controls the TOUT output.
When "1" is written: TOUT output ON
When "0" is written: TOUT output OFF
Reading: Valid
By writing "1" to the PTOUT register when the R02 register has been set to "1" and the R02HIZ register
has been set to "0", the TOUT signal is output from the R02 terminal. When "0" is written, the R02 terminal goes high (VDD).
When using the R02 output port for DC output, fix this register at "0".
At initial reset, this register is set to "0".
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4.5.6 Programming notes
(1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output).
Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R02 and R03 registers when the special output has been selected.
Be aware that the output terminal shifts into high impedance status when "1" is written to the high
impedance control register (R02HIZ, R03HIZ).
(2) A hazard may occur when the FOUT signal and the TOUT signal are turned ON and OFF.
(3) When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.6 I/O Ports (P00–P03, P10–P13 and P20–P23)
4.6.1 Configuration of I/O ports
The S1C63466 has 12 bits general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O
port.
Data bus
Address
VDD
Pull-up control
register (PUL)
Address
Address
Data
register
Address
I/O control
register (IOC)
PXX
Mask option
Fig. 4.6.1.1 Configuration of I/O port
The I/O port terminals P10 to P13 are shared with the serial interface input/output terminals. The P22
and P23 terminals are shared with the special output (CL, FR) terminals. The software can select the
function to be used.
At initial reset, these are all set to the I/O port.
Table 4.6.1.1 shows the setting of the input/output terminals by function selection.
Table 4.6.1.1 Function setting of input/output terminals
Terminal status
Special output
at initial reset
CL
FR
P00–P03 P00–P03 (Input & pull-up ∗)
P00–P03 P00–P03
P10
P10 (Input & pull-up ∗)
P11
P11 (Input & pull-up ∗)
P12
P12 (Input & pull-up ∗)
P13
P13 (Input & pull-up ∗)
P20
P20 (Input & pull-up ∗)
P20
P20
P21
P21 (Input & pull-up ∗)
P21
P21
P22
P22 (Input & pull-up ∗)
CL
P23
P23 (Input & pull-up ∗)
FR
∗ When "with pull-up resistor" is selected by the mask option
(high impedance when "gate direct" is set)
Terminal
Serial I/F
Master
Slave
P00–P03 P00–P03
SIN(I)
SIN(I)
SOUT(O) SOUT(O)
SCLK(O) SCLK(I)
P13
SRDY(O)
P20
P21
P20
P21
When these ports are used as I/O ports, the ports can be set to either input mode or output mode individually (in 1-bit unit). Modes can be set by writing data to the I/O control registers.
Refer to Section 4.11, "Serial Interface", for control of the serial interface.
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4.6.2 Mask option
In the I/O ports P10–P13 and P20–P23, the output specification during output mode can be selected from
either complementary output or N-channel open drain output by mask option. They are selected in 1-bit
units or 4-bit units depending on the terminal group. Note that the P00–P03 can be only used as complementary output.
Ports to be selected in 1-bit units: P20, P21, P22, P23
Ports to be selected in 4-bit units: P10–P13
The mask option also permits selection of whether the pull-up resistor is used or not during input mode.
They are selected in 1-bit units or 4-bit units depending on the terminal group.
Ports to be selected in 1-bit units: P20, P21, P22, P23
Ports to be selected in 4-bit units: P10–P13
When N-channel open drain output is selected, do not apply a voltage exceeding the power supply
voltage to the port.
When "without pull-up" during the input mode is selected, take care that the floating status does not
occur.
This option is effective even when I/O ports are used for special output or input/output of the serial
interface.
4.6.3 I/O control registers and input/output mode
Input or output mode can be set for the I/O ports by writing data into the corresponding I/O control
registers IOCxx.
To set the input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it
becomes high impedance status and works as an input port.
However, when the pull-up explained in the following section has been set by software, the input line is
pulled up only during this input mode.
To set the output mode, write "1" is to the I/O control register. When an I/O port is set to output mode , it
works as an output port, it outputs a high level (VDD) when the port output data is "1", and a low level
(VSS) when the port output data is "0".
If perform the read out in each mode; when output mode, the register value is read out, and when input
mode, the port value is read out.
At initial reset, the I/O control registers are set to "0", and the I/O ports enter the input mode.
The I/O control registers of the ports that are set as special output or input/output for the serial interface
can be used as general purpose registers that do not affect the I/O control. (See Table 4.6.1.1.)
4.6.4 Pull-up during input mode
A pull-up resistor that operates during the input mode is built into each I/O port of the S1C63466. Mask
option can set the use or non-use of this pull-up.
The pull-up resistor becomes effective by writing "1" to the pull-up control register PULxx that corresponds to each port, and the input line is pulled up during the input mode. When "0" has been written,
no pull-up is done.
At initial reset, the pull-up control registers are set to "1".
The pull-up control registers of the ports in which "without pull-up" have been selected can be used as
general purpose registers.
Even when "with pull-up" has been selected, the pull-up control registers of the ports, that are set as
special output or output for the serial interface, can be used as general purpose registers that do not affect
the pull-up control. (See Table 4.6.1.1.)
The pull-up control registers of the port, that are set as input for the serial interface, function the same as
the I/O port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.6.5 Special outputs (CL, FR)
The I/O ports P22 and P23 can be used as special output ports that output CL and FR signals by switching the function with software. Since P22 and P23 are set to I/O port (input mode) at initial reset, when
using the special outputs, select the special output function using the EXLCDC register.
The data registers, I/O control registers and pull-up control registers of the ports set in the special output
can be used as general purpose registers that do not affect the output.
When "1" is written to the EXLCDC register, P22 is set to the CL output port and P23 is set to the FR
output port.
The CL and FR signals are LCD synchronous signal (CL) and LCD flame signal (FR) for externally
expanded LCD driver, and are output from the P22 terminal and P23 terminal when the functions are
switched by the EXLCDC register.
The following tables show the frequencies of the CL and FR signals.
Table 4.6.5.1 CL signal frequency
OSC1 oscillation
frequency
32.768 kHz
60 kHz
When 1/8 duty
is selected
512 Hz
937.5 Hz
OSC1 oscillation
frequency
32.768 kHz
60 kHz
When 1/8 duty
is selected
32 Hz
58.6 Hz
When 1/16 duty
is selected
1,024 Hz
1,875 Hz
When 1/17 duty
is selected
1,024 Hz
1,875 Hz
Table 4.6.5.2 FR signal frequency
When 1/16 duty
is selected
32 Hz
58.6 Hz
When 1/17 duty
is selected
30.12 Hz
55.2 Hz
Refer to Section 4.7, "LCD Driver", for control of the LCD drive duty.
Note: A hazard may occur when the CL signal or FR signal is turned ON or OFF (when the port function
is switched).
Figure 4.6.5.1 shows the output waveforms of CL and FR signals.
CL output (P22 terminal)
FR output (P23 terminal)
When 1/17 duty is selected
CL output (P22 terminal)
FR output (P23 terminal)
When 1/16 duty is selected
CL output (P22 terminal)
FR output (P23 terminal)
When 1/8 duty is selected
Fig. 4.6.5.1 Output waveforms of CL and FR signals
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4.6.6 I/O memory of I/O ports
Tables 4.6.6.1(a) and (b) show the I/O addresses and the control bits for the I/O ports.
Table 4.6.6.1(a) Control bits of I/O ports
Address
Register
D3
D2
D1
IOC03
IOC02
IOC01
FF40H
R/W
PUL03
PUL02
PUL01
FF41H
R/W
P03
P02
P01
FF42H
R/W
IOC13
IOC12
IOC11
IOC10
R/W
PUL12
PUL11
1
Output
Output
Output
Output
On
On
On
On
High
High
High
High
Output
0
Input
Input
Input
Input
Off
Off
Off
Off
Low
Low
Low
Low
Input
IOC12
0
Output
Input
IOC11
0
Output
Input
IOC10
0
Output
Input
PUL13
1
On
Off
PUL12
1
On
Off
PUL11
1
On
Off
PUL10
1
On
Off
P13
– ∗2
High
Low
P12
– ∗2
High
Low
P11
– ∗2
High
Low
P10
– ∗2
High
Low
Name
IOC03
IOC00
IOC02
IOC01
IOC00
PUL03
PUL00
PUL02
PUL01
PUL00
P03
P00
P02
P01
P00
IOC13
FF44H
PUL13
Init ∗1
0
0
0
0
1
1
1
1
– ∗2
– ∗2
– ∗2
– ∗2
0
D0
PUL10
FF45H
R/W
P13
P12
P11
P10
FF46H
R/W
IOC23
IOC22
IOC21
FF48H
R/W
PUL23
PUL22
PUL21
R/W
P22
P21
0
Output
Input
IOC22
0
Output
Input
IOC21
IOC20
PUL23
0
0
1
Output
Output
On
Input
Input
Off
PUL22
1
On
Off
PUL21
PUL20
P23
1
1
– ∗2
On
On
High
Off
Off
Low
P22
– ∗2
High
Low
P21
P20
– ∗2
– ∗2
High
High
Low
Low
PUL20
FF49H
P23
IOC23
IOC20
P20
FF4AH
R/W
Comment
P00–P03 I/O control register
P00–P03 pull-up control register
P00–P03 I/O port data
P13 I/O control register
functions as a general-purpose register when SIF (slave) is selected
P12 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P11 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P13 pull-up control register
functions as a general-purpose register when SIF (slave) is selected
P12 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-up control register when SIF (slave) is selected
P11 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 pull-up control register (ESIF=0)
SIN pull-up control register when SIF is selected
P13 I/O port data
functions as a general-purpose register when SIF (slave) is selected
P12 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P23 I/O control register (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 I/O control register (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 I/O control register
P20 I/O control register
P23 pull-up control register (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 pull-up control register (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 pull-up control register
P20 pull-up control register
P23 I/O port data (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 I/O port data (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 I/O port data
P20 I/O port data
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
Table 4.6.6.1(b) Control bits of I/O ports
Address
Register
D3
D2
D1
EXLCDC ALOFF
ALON
FF61H
R/W
0
0
Name Init ∗1
1
0
EXLCDC
0
Enable Disable
LPAGE ALOFF
1
All Off Normal
ALON
0
All On Normal
F100-F177 F000-F077
LPAGE
0
D0
SCTRG
ESIF
FF70H
R
0 ∗3
0 ∗3
SCTRG
R/W
ESIF
– ∗2
– ∗2
0
Trigger
Run
0
SIF
Comment
Expanded LCD driver signal control
LCD all OFF control
LCD all ON control
Display memory area selection (when 1/8 duty is selected)
functions as a general-purpose register when 1/16, 1/17 duty is selected
Unused
Unused
Invalid Serial I/F clock trigger (writing)
Stop Serial I/F clock status (reading)
Serial I/F enable (P1 port function selection)
I/O
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
(1) Selection of port function
EXLCDC: Expanded LCD driver signal control register (FF61H•D3)
Sets P22 and P23 to the CL signal and the FR signal output ports.
When "1" is written: CL/FR signal output
When "0" is written: I/O port
Reading: Valid
When setting P22 to the CL (LCD synchronous signal) output and P23 to the FR (LCD frame signal)
output, write "1" to this register and when they are used as I/O ports, write "0".
The CL and FR signals are output from the P22 terminal and P23 terminal immediately after the functions
are switched by the EXLCDC register. In this case, the control registers for P22 and P23 can be used as
general purpose registers that do not affect the output.
At initial reset, this register is set to "0".
ESIF: Serial interface enable register (FF70H•D0)
Selects function for P10–P13.
When "1" is written: Serial interface input/output port
When "0" is written: I/O port
Reading: Valid
When using the serial interface, write "1" to this register and when P10–P13 are used as the I/O port,
write "0". The configuration of the terminals within P10–P13 that are used for the serial interface is
decided by the mode selected with the SCS1 and SCS0 registers (see Section 4.11).
In the slave mode, all the P10–P13 ports are set to the serial interface input/output port. In the master
mode, P10–P12 are set to the serial interface input/output port and P13 can be used as the I/O port.
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
(2) I/O port control
P00–P03: P0 I/O port data register (FF42H)
P10–P13: P1 I/O port data register (FF46H)
P20–P23: P2 I/O port data register (FF4AH)
I/O port data can be read and output data can be set through these registers.
• When writing data
When "1" is written: High level
When "0" is written: Low level
When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written,
the terminal goes low (VSS).
Port data can be written also in the input mode.
• When reading data
When "1" is read: High level
When "0" is read: Low level
The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port terminal can be read out; in the output mode the register value can be read.
When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal
voltage is low (VSS) the data is "0".
When "with pull-up resistor" has been selected with the mask option and the PUL register is set to "1", the
built-in pull-up resister goes ON during input mode, so that the I/O port terminal is pulled up.
The data registers of the port, which are set for the special output (P22, P23) or input/output of the serial
interface (P10–P12 or P10–P13), become general-purpose registers that do not affect the input/output.
Note: When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 330 kΩ
IOC00–IOC03: P0 port I/O control register (FF40H)
IOC10–IOC13: P1 port I/O control register (FF44H)
IOC20–IOC23: P2 port I/O control register (FF48H)
The input and output modes of the I/O ports are set with these registers.
When "1" is written: Output mode
When "0" is written: Input mode
Reading: Valid
The input and output modes of the I/O ports are set in 1-bit unit.
Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and
writing "0" induces the input mode.
At initial reset, these registers are all set to "0", so the I/O ports are in the input mode.
The I/O control registers of the port, which are set for the special output (P22, P23) or input/output of
the serial interface (P10–P12 or P10–P13), become general-purpose registers that do not affect the input/
output.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
PUL00–PUL03: P0 port pull-up control register (FF41H)
PUL10–PUL13: P1 port pull-up control register (FF45H)
PUL20–PUL23: P2 port pull-up control register (FF49H)
The pull-up during the input mode are set with these registers.
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
Reading: Valid
The built-in pull-up resistor which is turned ON during input mode is set to enable in 1-bit units. (The
pull-up resistor is included into the ports selected by the mask option.)
By writing "1" to the pull-up control register, the corresponding I/O ports are pulled up (during input
mode), while writing "0" turns the pull-up function OFF.
At initial reset, these registers are all set to "1", so the pull-up function is set to ON.
The pull-up control registers of the ports in which the pull-up resistor is not included become the general
purpose register. The registers of the ports that are set as special output or output for the serial interface
can also be used as general purpose registers that do not affect the pull-up control.
The pull-up control registers of the port that are set as input for the serial interface function the same as
the I/O port.
4.6.7 Programming notes
(1) When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 330 kΩ
(2) When special output (CL, FR) has been selected, a hazard may occur when the signal is turned ON or
OFF.
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S1C63466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7 LCD Driver (COM0–COM16, SEG0–SEG59)
4.7.1 Configuration of LCD driver
The S1C63466 has 17 common terminals (COM0–COM16) and 60 segment terminals (SEG0–SEG59), so
that it can drive a dot matrix type LCD with a maximum of 1,020 (60 × 17) dots.
The driving method is 1/17 duty, 1/16 duty or 1/8 duty dynamic drive with four voltages (1/4 bias),
VC1, VC2, VC4 and VC5 (1/5 bias driving can be set by impressing five voltages from outside).
LCD display ON/OFF can be controlled by the software.
4.7.2 Power supply for LCD driving
VC1–VC5 are driving voltages for the LCD, and for which either the voltages generated by the LCD
system voltage circuit or voltages to be supplied from outside can be used. The built-in LCD system
voltage circuit generates four voltages (1/4 bias) VC1, VC2, VC4 and VC5 except for VC3. These four output
voltages can be supplied to the outside only for driving the externally expanded LCD driver.
When external voltages are supplied, 1/5 bias driving can be made by inputting five voltages to the VC1–
VC5 terminals (including VC3).
Either the internal generated voltages or external voltages used for the LCD drive voltage can be selected
by the mask option.
Turning the LCD system voltage circuit ON or OFF is controlled with the LPWR register. This control is
also necessary when supplying the voltage from outside. When LPWR is set to "1", the LCD system
voltage circuit outputs the LCD drive voltages VC1–VC5 to the LCD driver.
When "internal voltage" is selected by the mask option, the LCD system voltage circuit generates VC1 or
VC2 with the voltage regulator incorporated in itself, and generates three other voltages by boosting or
reducing the voltage VC1 or VC2. Table 4.7.2.1 shows the VC1, VC2, VC4 and VC5 voltage values and boost/
reduce status.
Table 4.7.2.1 LCD drive voltage when generated internally
LCD drive voltage
VC1 (0.975–1.2 V)
VDD = 1.8–6.4 V
VC1 (standard)
VDD = 2.6–6.4 V
1/2 × VC2
VC2 (1.950–2.4 V)
VC4 (2.925–3.6 V)
2 × VC1
3 × VC1
VC2 (standard)
3/2 × VC2
VC5 (3.900–4.8 V)
4 × VC1
2 × VC2
Note: The LCD drive voltage can be adjusted by the software (see Section 4.7.6). Values in the table are
typical values.
Select either VC1 standard or VC2 standard using the VCCHG register.
When "1" is written to the VCCHG register, VC2 standard is selected and when "0" is written, VC1 standard is selected. At initial reset, VC1 standard (VCCHG = "0") is set.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7.3 Mask option
Disconnecting the internal power supply for LCD driving will enable voltages to be supplied externally.
In such case, the five voltages are entered in VC1, VC2, VC3, VC4 and VC5 terminals and 1/5 bias driving
may then be set. Since 1/5 bias driving provides better display quality, when low power current consumption is not required (i.e., when power is supplied from AC outlet), select external power mode.
However, note that in order to maintain a stable display, power source must be one which will remain
stable even when heavy load such as buzzer, etc. is driven.
Moreover, in the external power mode, the contrast adjustment function cannot be used. Accommodate
this limitation by utilizing the external circuit as necessary.
A sample circuit of external power for LCD driving when power is supplied externally is shown in Figure
4.7.3.1.
VDD
VDD (3 V)
Rxx
Power save circuit
VDD'
VC5
5V
S1C63466 VC4
4V
VC3
3V
VC2
2V
VC1
1V
VSS (0 V)
VSS
Fig. 4.7.3.1 Sample circuit of external power for LCD driving when power is supplied externally
4.7.4 LCD display control (ON/OFF) and switching of duty
(1) Display ON/OFF control
The S1C63466 incorporates the ALON and ALOFF registers to blink display. When "1" is written to
ALON, all the dots go ON, and when "1" is written to ALOFF, all the dots go OFF. At such a time, an
ON waveform or an OFF waveform is output from SEG terminals. When "0" is written to these
registers, normal display is performed. Furthermore, when "1" is written to both of the ALON and
ALOFF, ALON (all ON) has priority over the ALOFF (all OFF).
(2) Switching of drive duty
In the S1C63466, the drive duty can be set to 1/17, 1/16 or 1/8 by the software. This setting is done
using the LDUTY1 and LDUTY0 registers as shown in Table 4.7.4.1.
Table 4.7.4.1 LCD drive duty setting
LDUTY1
1
0
0
LDUTY0
∗
1
0
Drive duty
1/8
1/16
1/17
Common terminal used
COM0–COM7
COM0–COM15
COM0–COM16
Maximum segment number
480 (60 × 8)
960 (60 × 16)
1,020 (60 × 17)
Table 4.7.4.2 shows the frame frequencies corresponding to the OSC1 oscillation frequency and drive
duty.
Table 4.7.4.2 Frame frequency
OSC1 oscillation
frequency
32.768 kHz
60 kHz
48
When 1/8 duty
is selected
32 Hz
58.6 Hz
When 1/16 duty
is selected
32 Hz
58.6 Hz
EPSON
When 1/17 duty
is selected
30.12 Hz
55.2 Hz
S1C63466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Figures 4.7.4.1 and 4.7.4.2 show the dynamic drive waveform for 1/4 bias and 1/5 bias.
Drive duty
1/8
1/16
0 1 2 3
0 1 2 3
.....
.....
7 0 1 2 3
15 0 1 2 3
.....
.....
7
15
1/17
0 1 2 3
.....
16 0 1 2 3
.....
16
(LPAGE = 0)
Frame signal
32 Hz ∗
∗ When fOSC1 = 32.768 kHz
VC5
VC4
VC2 (VC3)
VC1
VSS
COM0
VC5
COM1
VC4
VC2 (VC3)
VC1
VSS
COM2
VC5
VC4
VC2 (VC3)
VC1
VSS
SEG0
VC5
VC4
VC2 (VC3)
VC1
VSS
VC5
VC4
VC2 (VC3)
VC1
VSS
SEG1
Fig. 4.7.4.1 Drive waveform for 1/4 bias
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Drive duty
1/8
0 1 2 3
1/16
1/17
0 1 2 3
0 1 2 3
.....
.....
.....
7 0 1 2 3
15 0 1 2 3
16 0 1 2 3
.....
.....
.....
7
(LPAGE = 0)
15
16
Frame signal
32 Hz ∗
∗ When fOSC1 = 32.768 kHz
VC5
VC4
VC3
VC2
VC1
COM0
VSS
VC5
VC4
VC3
VC2
COM1
VC1
VSS
VC5
VC4
VC3
VC2
COM2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
SEG0
VC5
VC4
VC3
VC2
VC1
VSS
SEG1
Fig. 4.7.4.2 Drive waveform for 1/5 bias
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7.5 Display memory
The display memory is allocated to F000H–F276H in the data memory area and the addresses and the
data bits correspond to COM and SEG outputs as shown in Figure 4.7.5.1.
1/16 duty
1/17 duty
SEG0
SEG1
■ D0
SEG2
■ D0
SEG3
■ D0
SEG59
■ D0
COM0
■ D0
COM1
COM2
■ D1
■ D2
COM3
■ D3
■ D2
■ D3
COM4
■ D0
■ D0
■ D0
■ D0
COM5
COM6
■ D1
■ D2
■ D1
■ D2
■ D1
■ D2
■ D1
■ D2
COM7
■ D3
■ D3
■ D3
■ D3
■ D3
COM8
COM9
■ D0
■ D1
■ D0
■ D0
■ D0
■ D0
■ D1
■ D2
■ D3
■ D1
■ D2
■ D3
■ D1
■ D2
■ D3
COM10 ■ D2
COM11 ■ D3
COM12 ■ D0
COM13 ■ D1
COM14 ■ D2
F000H
F001H
F100H
F101H
COM15 ■ D3
COM16 ■ D0
■ D1
■ D0
■ D1
■ D2
F002H
F003H
F102H
F103H
■ D3
F200H
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
F004H
F005H
F104H
F105H
■ D3
F202H
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
F006H . . . . .
■ D0
■ D2
■ D3
F076H
■ D0
F007H . . . . .
F106H . . . . .
F107H . . . . .
■ D3
F204H
■ D1
■ D1
■ D2
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
F077H
F176H
F177H
■ D3
F206H . . . . .
■ D0
F276H
Data bit
Memory address
(a) When 1/17 or 1/16 duty is selected
LPAGE
=0
LPAGE
=1
SEG0
■ D0
■ D1
F000H
■ D2
■ D3
■ D0
■ D1
F001H
■ D2
■ D3
SEG1
SEG2
SEG3
SEG59
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
COM0
COM1
■ D0
■ D1
COM2
COM3
COM4
■ D2
■ D3
■ D0
■ D0
■ D1
■ D2
COM5
COM6
COM7
■ D1
■ D2
■ D3
Unused ■ D0
F100H
F101H
F200H
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
F002H
F003H
F102H
F103H
F202H
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
F004H
F005H
F104H
F105H
F204H
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
F006H . . . . .
F007H . . . . .
F106H . . . . .
F107H . . . . .
F206H . . . . .
■ D0
■ D1
■ D2
■ D3
■ D0
■ D1
■ D2
■ D3
■ D0
F076H
F077H
F176H
F177H
F276H
(b) When 1/8 duty is selected
Fig. 4.7.5.1 Correspondence between display memory and LCD dot matrix
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
When a bit in the display memory is set to "1", the corresponding LCD dot goes ON, and when it is set to
"0", the dot goes OFF.
At 1/17 (1/16) duty drive, all data of COM0–COM16 (15) is output.
At 1/8 duty drive, data only corresponding to COM0–COM7 is output. However, since the display
memory has capacity for two screens, it is designed so that the memory for COM8–COM15 shown in
Figure 4.7.5.1 (b) can also be used as COM0–COM7. Select either F000H–F077H or F100H–F177H for the
area to be displayed (to be output from COM0–COM7 terminals) using the LPAGE register. It can switch
the screen in an instant.
At initial reset, the data memory content becomes undefined hence, there is need to initialize using the
software.
The display memory has read/write capability, and the addresses that have not been used for LCD
display can be used as general purpose registers.
Note: When a program that access no memory mounted area (F078H–F0FFH, F178H–F1FFH, F201H,
F203H, · · ·, F277H) is made, the operation is not guaranteed.
4.7.6 LCD contrast adjustment
In the S1C63466, the LCD contrast can be adjusted by the software.
It is realized by controlling the voltages VC1, VC2, VC4 and VC5 output from the LCD system voltage
circuit. When these voltages are supplied to the externally expanded LCD driver, the expanded LCD
contrast is adjusted at the same time. However, when the LCD drive voltage is supplied from outside by
the mask option selection, this adjustment becomes invalid.
The contrast can be adjusted to 16 levels as shown in Table 4.7.6.1. When VCCHG = "0", VC1 is changed
within the range from 0.975 V to 1.2 V, and other voltages change according to VC1. When VCCHG = "1",
VC2 is changed within the range from 1.950 V to 2.4 V, and other voltages change according to VC2.
Table 4.7.6.1 LCD contrast
No.
0
LC3
0
LC2
0
LC1
0
LC0
0
1
2
3
0
0
0
0
0
0
0
1
1
1
0
1
4
5
6
0
0
0
1
1
1
0
0
1
0
1
0
7
8
9
0
1
1
1
0
0
1
0
0
1
0
1
10
11
12
13
14
15
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Contrast
light
dark
At room temperature, use setting number 7 or 8 as standard.
Since the contents of LC0–LC3 are undefined at initial reset, initialize it by the software.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7.7 I/O memory of LCD driver
Table 4.7.7.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.7.7.1 shows the
display memory map.
Table 4.7.7.1 LCD driver control bits
Address
Register
Name Init ∗1
1
0
LDUTY1
0
LDUTY1 LDUTY0 VCCHG LPWR
LDUTY0
0
FF60H
VC1
VCCHG
0
VC2
R/W
On
Off
LPWR
0
EXLCDC
0
Enable Disable
EXLCDC ALOFF ALON LPAGE ALOFF
1
All Off Normal
ALON
0
All On Normal
FF61H
F100-F177 F000-F077
LPAGE
0
R/W
D3
LC3
D2
D1
LC2
LC1
Comment
D0
LC0
FF62H
R/W
LC3
LC2
LC1
LC0
– ∗2
– ∗2
– ∗2
– ∗2
LCD drive duty
[LDUTY1, 0]
0
1
2, 3
Duty
1/17
1/16
1/8
switch
LCD regulated voltage switch
LCD power On/Off
Expanded LCD driver signal control
LCD all OFF control
LCD all ON control
Display memory area selection (when 1/8 duty is selected)
functions as a general-purpose register when 1/16, 1/17 duty is selected
LCD contrast adjustment
[LC3–0]
Contrast
0
Light
–
–
15
Dark
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
COM0–COM7
COM8–COM15
D3
F000H COM3
F001H COM7
F002H COM3
D2
COM2
COM6
COM2
D1
COM1
COM5
COM1
D0
COM0
COM4
COM0
SEG0
SEG0
SEG1
F003H COM7
F004H COM3
:
COM6
COM2
COM5
COM1
COM4
COM0
SEG1
SEG2
F075H COM7
F076H COM3
F077H COM7
F078H
:
COM6
COM2
COM6
COM5
COM1
COM5
COM4
COM0
COM4
SEG58
SEG59
SEG59
Notimplemented
F0FFH
D3
D2
D1
F100H COM11 COM10 COM09
F101H COM15 COM14 COM13
F102H COM11 COM10 COM09
F103H COM15 COM14 COM13
F104H COM11 COM10 COM09
:
COM16
D0
COM8 SEG0
COM12 SEG0
COM8 SEG1
COM12 SEG1
COM8 SEG2
F175H COM15 COM14 COM13 COM12 SEG58
F176H COM11 COM10 COM09 COM8 SEG59
F177H COM15 COM14 COM13 COM12 SEG59
F178H
Not:
F200H
F201H
F202H
F203H
:
F274H
F275H
F276H
F277H
implemented
D3
0
D2
0
D1
0
D0
COM16 SEG0
0
0
0
COM16 SEG1
0
0
0
COM16 SEG58
0
0
0
COM16 SEG59
Non-implementation area
F1FFH
0
Unused area
Read/write disabled
Reading: Always "0"
Writing: No Operation
Fig. 4.7.7.1 Display memory map
LPWR: LCD power control (ON/OFF) register (FF60H•D0)
Turns the LCD system voltage circuit ON and OFF.
When "1" is written: ON
OFF
Reading: Valid
When "1" is written to the LPWR register, the LCD system voltage circuit goes ON and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to VSS level.
It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
At initial reset, this register is set to "0".
When "0" is written:
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VCCHG: LCD regulated voltage switching register (FF60H•D1)
Selects the reference voltage for the LCD drive voltage.
When "1" is written: VC2
When "0" is written: VC1
Reading: Valid
When "1" is written to the VCCHG register, the LCD system voltage circuit generates the LCD drive
voltage as VC2 standard. When "0" is written, it becomes VC1 standard. Select VC2 when power supply
voltage is 2.6 V or more, otherwise, select VC1.
When external power mode is selected by the mask option, this control is unnecessary.
At initial reset, this register is set to "0".
LDUTY0, LDUTY1: LCD drive duty switching register (FF60H•D2, D3)
Selects the LCD drive duty.
Table 4.7.7.2 Drive duty setting
LDUTY1
1
0
0
LDUTY0
∗
1
0
Drive duty
1/8
1/16
1/17
Common terminal used
COM0–COM7
COM0–COM15
COM0–COM16
Maximum segment number
480 (60 × 8)
960 (60 × 16)
1,020 (60 × 17)
At initial reset, this register is set to "0".
ALON: LCD all ON control register (FF61H•D1)
Displays the all LCD dots ON.
When "1" is written: All LCD dots displayed
When "0" is written: Normal display
Reading: Valid
By writing "1" to the ALON register, all the LCD dots goes ON, and when "0" is written, it returns to
normal display.
This function outputs an ON waveform to the SEG terminals, and does not affect the content of the
display memory.
ALON has priority over ALOFF.
At initial reset, this register is set to "0".
ALOFF: LCD all OFF control register (FF61H•D2)
Fade outs the all LCD dots.
When "1" is written: All LCD dots fade out
When "0" is written: Normal display
Reading: Valid
By writing "1" to the ALOFF register, all the LCD dots goes OFF, and when "0" is written, it returns to
normal display.
This function outputs an OFF waveform to the SEG terminals, and does not affect the content of the
display memory.
At initial reset, this register is set to "1".
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LPAGE: LCD display memory selection register (FF61H•D0)
Selects the display memory area at 1/8 duty drive.
When "1" is written: F100H–F177H
When "0" is written: F000H–F077H
Reading: Valid
By writing "1" to the LPAGE register, the data set in F100H–F177H (the second half of the display
memory) is displayed, and when "0" is written, the data set in F000H–F077H (the first half of the display
memory) is displayed.
This function is valid only when 1/8 duty is selected, and when 1/16 or 1/17 duty is selected, this
register can be used as a general purpose register.
At initial reset, this register is set to "0".
LC3–LC0: LCD contrast adjustment register (FF62H)
Adjusts the LCD contrast.
LC3–LC0 = 0000B
:
:
LC3–LC0 = 1111B
light
dark
At room temperature, use setting number 7 or 8 as standard.
When the LCD drive voltage is supplied from outside by the mask option selection, this adjustment
becomes invalid.
At initial reset, LC0–LC3 are undefined.
4.7.8 Programming notes
(1) When a program that access no memory mounted area (F078H–F0FFH, F178H–F1FFH, F201H, F203H,
· · ·, F277H) is made, the operation is not guaranteed.
(2) Because at initial reset, the contents of display memory and LC3–LC0 (LCD contrast) are undefined,
there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF
because these are set so that the display goes OFF.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8 Clock Timer
4.8.1 Configuration of clock timer
The S1C63466 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The
clock timer is configured of an 8-bit binary counter that serves as the input clock, fOSC1 divided clock
output from the prescaler. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software.
Figure 4.8.1.1 is the block diagram for the clock timer.
Data bus
Clock timer
OSC1
oscillation circuit
(fOSC1)
Divider
256 Hz
128 Hz–16 Hz
8 Hz–1 Hz
32 Hz, 8 Hz, 2 Hz, 1 Hz
Clock timer reset signal
Interrupt
control
Clock timer RUN/STOP signal
Interrupt
request
Fig. 4.8.1.1 Block diagram for the clock timer
Ordinarily, this clock timer is used for all types of timing functions such as clocks.
Note: When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the
frequencies and times differ from the values described in this section because the oscillation
frequency will be 60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function.
4.8.2 Data reading and hold function
The 8 bits timer data are allocated to the address FF79H and FF7AH.
<FF79H>
<FF7AH>
D0: TM0 = 128 Hz
D0: TM4 = 8 Hz
D1: TM1 = 64 Hz
D1: TM5 = 4 Hz
D2: TM2 = 32 Hz
D2: TM6 = 2 Hz
D3: TM3 = 16 Hz
D3: TM7 = 1 Hz
Since the clock timer data has been allocated to two addresses, a carry is generated from the low-order
data within the count (TM0–TM3: 128–16 Hz) to the high-order data (TM4–TM7: 8–1 Hz). When this carry
is generated between the reading of the low-order data and the high-order data, a content combining the
two does not become the correct value (the low-order data is read as FFH and the high-order data
becomes the value that is counted up 1 from that point).
The high-order data hold function in the S1C63466 is designed to operate to avoid this. This function
temporarily stops the counting up of the high-order data (by carry from the low-order data) at the point
where the low-order data has been read and consequently the time during which the high-order data is
held is the shorter of the two indicated here following.
1. Period until it reads the high-order data.
2. 0.48–1.5 msec (Varies due to the read timing.)
Note: Since the low-order data is not held when the high-order data has previously been read, the loworder data should be read first.
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4.8.3 Interrupt function
The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz, 2 Hz and 1 Hz signals. Software
can set whether to mask any of these frequencies.
Figure 4.8.3.1 is the timing chart of the clock timer.
Address
Bit
Frequency
D0
128 Hz
D1
64 Hz
D2
32 Hz
D3
16 Hz
D0
8 Hz
D1
4 Hz
D2
2 Hz
D3
1 Hz
Clock timer timing chart
FF79H
FF7AH
32 Hz interrupt request
8 Hz interrupt request
2 Hz interrupt request
1 Hz interrupt request
Fig. 4.8.3.1 Timing chart of clock timer
As shown in Figure 4.8.3.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz,
1 Hz). At this time, the corresponding interrupt factor flag (IT0, IT1, IT2, IT3) is set to "1". Selection of
whether to mask the separate interrupts can be made with the interrupt mask registers (EIT0, EIT1, EIT2,
EIT3). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at
the falling edge of the corresponding signal.
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4.8.4 I/O memory of clock timer
Table 4.8.4.1 shows the I/O addresses and the control bits for the clock timer.
Table 4.8.4.1 Control bits of clock timer
Address
FF78H
FF79H
FF7AH
FFE6H
FFF6H
Register
Name Init ∗1
1
– ∗2
0 ∗3
0
0
TMRST TMRUN
0 ∗3
– ∗2
TMRST∗3 Reset Reset
R
W
R/W
TMRUN
0
Run
TM3
0
TM3
TM2
TM1
TM0
TM2
0
TM1
0
R
TM0
0
TM7
0
TM7
TM6
TM5
TM4
TM6
0
TM5
0
R
TM4
0
EIT3
0
Enable
EIT3
EIT2
EIT1
EIT0
EIT2
0
Enable
EIT1
0
Enable
R/W
EIT0
0
Enable
IT3
0
(R)
IT3
IT2
IT1
IT0
IT2
0
Yes
IT1
0
(W)
R/W
IT0
0
Reset
D3
D2
D1
D0
0
Comment
Unused
Unused
Invalid Clock timer reset (writing)
Stop Clock timer Run/Stop
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Mask Interrupt mask register (Clock timer 1 Hz)
Mask Interrupt mask register (Clock timer 2 Hz)
Mask Interrupt mask register (Clock timer 8 Hz)
Mask Interrupt mask register (Clock timer 32 Hz)
Interrupt factor flag (Clock timer 1 Hz)
(R)
Interrupt factor flag (Clock timer 2 Hz)
No
(W) Interrupt factor flag (Clock timer 8 Hz)
Invalid Interrupt factor flag (Clock timer 32 Hz)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
TM0–TM7: Timer data (FF79H, FF7AH)
The 128–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read
only, and writing operations are invalid.
By reading the low-order data (FF79H), the high-order data (FF7AH) is held until reading or for 0.48–1.5
msec (one of shorter of them).
At initial reset, the timer data is initialized to "00H".
TMRST: Clock timer reset (FF78H•D1)
This bit resets the clock timer.
When "1" is written: Clock timer reset
When "0" is written: No operation
Reading: Always "0"
The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. No operation results
when "0" is written to TMRST.
This bit is write-only, and so is always "0" at reading.
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TMRUN: Clock timer RUN/STOP control register (FF78H•D0)
Controls RUN/STOP of the clock timer.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The clock timer enters the RUN status when "1" is written to the TMRUN register, and the STOP status
when "0" is written.
In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also,
when the STOP status changes to the RUN status, the data that is maintained can be used for resuming
the count.
At initial reset, this register is set to "0".
EIT0: 32 Hz interrupt mask register (FFE6H•D0)
EIT1: 8 Hz interrupt mask register (FFE6H•D1)
EIT2: 2 Hz interrupt mask register (FFE6H•D2)
EIT3: 1 Hz interrupt mask register (FFE6H•D3)
These registers are used to select whether to mask the clock timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (EIT0, EIT1, EIT2, EIT3) are used to select whether to mask the interrupt to
the separate frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz).
At initial reset, these registers are set to "0".
IT0: 32 Hz interrupt factor flag (FFF6H•D0)
IT1: 8 Hz interrupt factor flag (FFF6H•D1)
IT2: 2 Hz interrupt factor flag (FFF6H•D2)
IT3: 1 Hz interrupt factor flag (FFF6H•D3)
These flags indicate the status of the clock timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags (IT0, IT1, IT2, IT3) correspond to the clock timer interrupts of the respective
frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz). The software can judge from these flags whether there is a clock
timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the
signal.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
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4.8.5 Programming notes
(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–
TM7).
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequencies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
4.9 Stopwatch Timer
4.9.1 Configuration of stopwatch timer
The S1C63466 has 1/100 sec unit and 1/10 sec unit stopwatch timer built-in. The stopwatch timer is
configured with a 2 levels 4-bit BCD counter which has an input clock approximating 100 Hz signal
(signal divided from OSC1 to the closest 100 Hz) and data can be read in units of 4 bits by software.
Figure 4.9.1.1 shows the configuration of the stopwatch timer.
Data bus
Stopwatch timer
OSC1
oscillation circuit
(fOSC1)
Divider
256 Hz
10 Hz
SWD0–3
SWD4–7
10 Hz, 1 Hz
Stopwatch timer reset signal
Stopwatch timer RUN/STOP signal
Interrupt
control
Interrupt
request
Fig. 4.9.1.1 Configuration of stopwatch timer
The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch
stopwatch functions can be realized easily with software.
Note: When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the
frequencies and times differ from the values described in this section because the oscillation
frequency will be 60 kHz (Typ.). Therefore, this timer can not be used for the stopwatch function.
4.9.2 Count-up pattern
The stopwatch timer is configured of 4-bit BCD counters SWD0–SWD3 and SWD4–SWD7.
The counter SWD0–SWD3, at the stage preceding the stopwatch timer, has an approximated 100 Hz
signal for the input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The
counter SWD4–SWD7 has an approximated 10 Hz signal generated by the counter SWD0–SWD3 for the
input clock. In count-up every 1/10 sec, and generated 1 Hz signal.
Figure 4.9.2.1 shows the count-up pattern of the stopwatch timer.
SWD4–7 count-up pattern
SWD4–7 count value
Counting time (sec)
0
1
2
3
4
5
6
7
8
9
0
26 26
25 25 26
26 25 25 26 26
256 256 256 256 256 256 256 256 256 256
1 Hz
signal
generation
26 x 6 + 25 x 4 = 1 (sec)
256
256
SWD0–3 count-up pattern 1
SWD0–3 count value
Counting time (sec)
0
1
3
256
2
3
4
5
6
7
8
9
0
2
3
2
3
2
3
2
3
2
256 256 256 256 256 256 256 256 256
25
256 (sec)
Approximate
10 Hz
signal
generation
SWD0–3 count-up pattern 2
SWD0–3 count value
Counting time (sec)
0
1
2
3
4
5
6
7
8
9
0
3
3
3
2
3
2
3
2
3
2
256 256 256 256 256 256 256 256 256 256
26 (sec)
256
Approximate
10 Hz
signal
generation
Fig. 4.9.2.1 Count-up pattern of stopwatch timer
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SWD0–SWD3 generates an approximated 10 Hz signal from the basic 256 Hz signal (fOSC1 dividing
clock). The count-up intervals are 2/256 sec and 3/256 sec, so that finally two patterns are generated: 25/
256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec.
SWD4–SWD7 counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the ratio of 4 : 6, to generate a 1 Hz signal. The count-up intervals are 25/256 sec and 26/256 sec,
which do not amount to an accurate 1/10 sec.
4.9.3 Interrupt function
The stopwatch timers SWD0–SWD3 and SWD4–SWD7, through their respective overflows, can generate
10 Hz (approximate 10 Hz) and 1 Hz interrupts.
Figure 4.9.3.1 shows the timing chart for the stopwatch timer.
Address
Bit
Stopwatch timer (SWD0–3) timing chart
D0
FF7DH
1/100sec
(BCD)
D1
D2
D3
10 Hz Interrupt request
Address
Bit
Stopwatch timer (SWD4–7) timing chart
D0
FF7EH
1/10sec
(BCD)
D1
D2
D3
1 Hz Interrupt request
Fig. 4.9.3.1 Timing chart for stopwatch timer
The stopwatch interrupts are generated by the overflow of their respective counters SWD0–SWD3 and
SWD4–SWD7 (changing "9" to "0"). At this time, the corresponding interrupt factor flags (ISW10 and
ISW1) are set to "1".
The respective interrupts can be masked separately using the interrupt mask registers (EISW10 and
EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are
set to "1" by the overflow of their corresponding counters.
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4.9.4 I/O memory of stopwatch timer
Table 4.9.4.1 shows the I/O addresses and the control bits for the stopwatch timer.
Table 4.9.4.1 Control bits of stopwatch timer
Address
Register
D3
D2
0
D1
0
D0
SWRST SWRUN
FF7CH
R
SWD3
SWD2
W
R/W
SWD1
SWD0
SWD5
SWD4
FF7DH
R
SWD7
SWD6
FF7EH
R
0
0
EISW1 EISW10
FFE7H
R
0
R/W
0
ISW1
ISW10
FFF7H
R
R/W
Name Init ∗1
1
– ∗2
0 ∗3
0 ∗3
– ∗2
SWRST∗3 Reset Reset
SWRUN
0
Run
SWD3
0
SWD2
0
SWD1
0
SWD0
0
SWD7
0
SWD6
0
SWD5
0
SWD4
0
0 ∗3
– ∗2
0 ∗3
– ∗2
EISW1
0
Enable
EISW10
0
Enable
0 ∗3
– ∗2
(R)
0 ∗3
– ∗2
Yes
ISW1
0
(W)
ISW10
0
Reset
Comment
0
Unused
Unused
Invalid Stopwatch timer reset (writing)
Stop Stopwatch timer Run/Stop
Stopwatch timer data
BCD (1/100 sec)
Stopwatch timer data
BCD (1/10 sec)
Unused
Unused
Mask Interrupt mask register (Stopwatch timer 1 Hz)
Mask Interrupt mask register (Stopwatch timer 10 Hz)
Unused
(R)
Unused
No
(W) Interrupt factor flag (Stopwatch timer 1 Hz)
Invalid Interrupt factor flag (Stopwatch timer 10 Hz)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
SWD0–SWD7: Stopwatch timer data (FF7DH, FF7EH)
The 1/100 sec and the 1/10 sec data (BCD) can be read from SWD0–SWD3 and SWD4–SWD7, respectively. These eight bits are read only, and writing operations are invalid.
At initial reset, the timer data is initialized to "00H".
SWRST: Stopwatch timer reset (FF7CH•D1)
When "1" is written: Stopwatch timer reset
When "0" is written: No operation
Reading: Always "0"
The stopwatch timer is reset by writing "1" to SWRST. All timer data is set to "0". When the stopwatch
timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is
maintained. No operation results when "0" is written to SWRST.
This bit is write-only, and so is always "0" at reading.
SWRUN: Stopwatch timer RUN/STOP control register (FF7CH•D0)
Controls RUN/STOP of the stopwatch timer.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The stopwatch timer enters the RUN status when "1" is written to the SWRUN register, and the STOP
status when "0" is written.
In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also,
when the STOP status changes to the RUN status, the data that is maintained can be used for resuming
the count.
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When data of the counter is read at run mode, proper reading may not be obtained due to the carry from
low-order digits (SWD0–SWD3) into high-order digits (SWD4–SWD7) (i.e., in case SWD0–SWD3 and
SWD4–SWD7 reading span the timing of the carry). To avoid this occurrence, perform the reading after
suspending the counter once and then set the SWRUN to "1" again.
Moreover, it is required that the suspension period not exceed 976 µsec (1/4 cycle of 256 Hz).
At initial reset, this register is set to "0".
EISW10: 10Hz interrupt mask register (FFE7H•D0)
EISW1: 1Hz interrupt mask register (FFE7H•D1)
These registers are used to select whether to mask the stopwatch timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (EISW10, EISW1) are used to select whether to mask the interrupt to the
separate frequencies (10 Hz, 1 Hz).
At initial reset, these registers are set to "0".
ISW10: 10 Hz interrupt factor flag (FFF7H•D0)
ISW1: 1 Hz interrupt factor flag (FFF7H•D1)
These flags indicate the status of the stopwatch timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags ISW10 and ISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts,
respectively. The software can judge from these flags whether there is a stopwatch timer interrupt.
However, even if the interrupt is masked, the flags are set to "1" by the overflow of the corresponding
counters.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
4.9.5 Programming notes
(1) When data of the counter is read at run mode, perform the reading after suspending the counter once
and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976
µsec (1/4 cycle of 256 Hz).
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequencies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, this timer can not be used for the stopwatch function.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10 Programmable Timer
4.10.1 Configuration of programmable timer
The S1C63466 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in.
Timer 0 and timer 1 are composed of 8-bit presettable down counters and they can be used as 8-bit × 2
channel programmable timers. Timer 0 also has an event counter function using the K13 input port
terminal.
Figure 4.10.1.1 shows the configuration of the programmable timer.
The programmable timer is designed to count down from the initial value set in the counter with software. An underflow according to the initial value occurs by counting down and is used for the following
functions:
• Presetting the initial value to the counter to generate the periodical underflow signal
• Generating an interrupt
• Generating a TOUT signal output from the R02 output port terminal
• Generating the synchronous clock source for the serial interface (timer 1 underflow is used, and it is
possible to set the transfer rate)
K13
Input port
K13
Programmable timer 0
PTRST0
Timer 0 reset
Reload data register
RLD00–RLD07
Timer 0 Run/Stop
PTRUN0
OSC1
fOSC1
oscillation
circuit
Selector
CKSEL0
Clock
control
circuit
Prescaler
Divider
Timer 1 Run/Stop
2,048
Hz
8-bit
down counter
Underflow
signal
Prescaler
setting
PTPS00
PTPS01
Data buffer
PTD00–PTD07
Data bus
PTRUN1
Timer function setting
OSC3
oscillation
fOSC3
circuit
Selector
CKSEL1
Interrupt
request
FCSEL
PLPOL
Interrupt
control
circuit
EVCNT
Pulse polarity setting
Event counter mode setting
Programmable timer 1
PTRST1
Timer 1 reset
TOUT (R02)
Output port
R02
1/2
Selector
Prescaler
PTOUT
CHSEL
Serial interface
Reload data register
RLD10–RLD17
Clock
control
circuit
8-bit
down counter
Underflow
signal
Prescaler
setting
PTPS10
PTPS11
Data buffer
PTD10–PTD17
1/2
Fig. 4.10.1.1 Configuration of programmable timer
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4.10.2 Setting of initial value and counting down
Timers 0 and 1 each have a down counter and reload data register.
The reload data registers RLD00–RLD07 (timer 0) and RLD10–RLD17 (timer 1) are used to set the initial
value to the down counter.
By writing "1" to the timer reset bit PTRST0 (timer 0) or PTRST1 (timer 1), the down counter loads the
initial value set in the reload register RLD. Therefore, down-counting is executed from the stored initial
value by the input clock.
The registers PTRUN0 (timer 0) and PTRUN1 (timer 1) are provided to control the RUN/STOP for timers
0 and 1. By writing "1" to the register after presetting the reload data to the down counter, the down
counter starts counting down. Writing "0" stops the input count clock and the down counter stops
counting. This control (RUN/STOP) does not affect the counter data. The counter maintains its data
while stopped, and can restart counting continuing from that data.
The counter data can be read via the data buffers PTD00–PTD07 (timer 0) and PTD10–PTD17 (timer 1) in
optional timing. However, the counter has the data hold function the same as the clock timer, that holds
the high-order data when the low-order data is read in order to prevent the borrowing operation between
low- and high-order reading, therefore be sure to read the low-order data first.
The counter reloads the initial value set in the reload data register RLD when an underflow occurs
through the count down. It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT
signal) output and clock supplying to the serial interface.
PTRUN0 (1)
PTRST0 (1)
RLD00–07 (10–17)
A6H
F3H
Input clock
PTD07 (17)
PTD06 (16)
PTD05 (15)
PTD04 (14)
PTD03 (13)
PTD02 (12)
PTD01 (11)
PTD00 (10)
Preset
Reload &
Interrupt generation
Fig. 4.10.2.1 Basic operation timing of down counter
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4.10.3 Counter mode
The programmable timer can operate in two counter modes, timer mode and event counter mode. It can
be selected by software.
(1) Timer mode
The timer mode counts down using the prescaler output as an input clock. In this mode, the programmable timer operates as a periodical timer using the OSC1 or OSC3 oscillation clock as a clock source.
Timer 0 can operate in both the timer mode and the event counter mode. The mode can be switched
using the timer 0 counter mode selection register EVCNT. When the EVCNT register is set to "0",
timer 0 operates in the timer mode.
Timer 1 operates only in the timer mode.
At initial reset, this mode is set.
Refer to Section 4.10.2, "Setting of initial value and counting down" for basic operation and control.
The input clock in the timer mode is generated by the prescaler built into the programmable timer.
The prescaler generates the input clock by dividing the OSC1 or OSC3 oscillation clock. Refer to the
next section for setting the input clock.
(2) Event counter mode
The timer 0 has an event counter function that counts an external clock input to the input port K13.
This function is selected by writing "1" to the timer 0 counter mode selection register EVCNT. The
timer 1 operates only in the timer mode, and cannot be used as an event counter.
In the event counter mode, the clock is supplied to timer 0 from outside of the IC, therefore, the
settings of the timer 0 prescaler division ratio selection registers PTPS00 and PTPS01 and the settings
of the timer 0 source clock selection register CKSEL0 become invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the
timer 0 pulse polarity selection register PLPOL. When "0" is written to the PLPOL register, the falling
edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown
in Figure 4.10.3.1.
EVCNT
1
PTRUN0
PLPOL
0
1
K13 input
Count data
n
n-1
n-2
n-3
n-4
n-5
n-6
Fig. 4.10.3.1 Timing chart in event counter mode
The event counter mode also includes a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec* or more to count reliably. The noise rejecter allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz* signal after changing the input level of the K13 input port
terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less.
(∗: fOSC1 = 32.768 kHz).
Figure 4.10.3.2 shows the count down timing with noise rejecter.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
2,048 Hz ∗1
K13 input
Counter
input clock ∗2
Counter data
n
n-1
n-2
n-3
∗1 When fOSC1 is 32.768 kHz
∗2 When PLPOL register is set to "0"
Fig. 4.10.3.2 Count down timing with noise rejecter
The operation of the event counter mode is the same as the timer mode except it uses the K13 input as
the clock.
Refer to Section 4.10.2, "Setting of initial value and counting down" for basic operation and control.
4.10.4 Setting of input clock in timer mode
Timer 0 and timer 1 each include a prescaler. The prescalers generate the input clock for each timer by
dividing the source clock supplied from the OSC1 or OSC3 oscillation circuit.
The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software for
timer 0 and timer 1 individually.
The set input clock is used for the count clock during operation in the timer mode. When the timer 0 is
used in the event counter mode, the following settings become invalid.
The input clock is set in the following sequence.
(1) Selection of source clock
Select the source clock input to each prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection registers CKSEL0 (timer 0) and CKSEL1 (timer 1); when "0" is written to the
register, OSC1 is selected and when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(2) Selection of prescaler division ratio
Select the division ratio for each prescaler from among 4 types. This selection is done using the
prescaler division ratio selection registers PTPS00/PTPS01 (timer 0) and PTPS10/PTPS11 (timer 1).
Table 4.10.4.1 shows the correspondence between the setting value and the division ratio.
Table 4.10.4.1 Selection of prescaler division ratio
PTPS11
PTPS01
1
1
PTPS10
PTPS00
1
0
0
0
1
0
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
By writing "1" to the register PTRUN0 (timer 0) or PTRUN1 (timer 1), the prescaler inputs the source
clock and outputs the clock divided by the selected division ratio. The counter starts counting down
by inputting the clock.
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4.10.5 Interrupt function
The programmable timer can generate an interrupt due to an underflow of the timer 0 and timer 1. See
Figure 4.10.2.1 for the interrupt timing.
An underflow of timer 0 and timer 1 sets the corresponding interrupt factor flag IPT0 (timer 0) or IPT1
(timer 1) to "1", and generates an interrupt. The interrupt can also be masked by setting the corresponding interrupt mask register EIPT0 (timer 0) or EIPT1 (timer 1). However, the interrupt factor flag is set to
"1" by an underflow of the corresponding timer regardless of the interrupt mask register setting.
4.10.6 Setting of TOUT output
The programmable timer can generate a TOUT signal due to an underflow of timer 0 or timer 1. The
TOUT signal is generated by dividing the underflows in 1/2. It is possible to select which timer's underflow is to be used by the TOUT output channel selection register CHSEL. When "0" is written to the
CHSEL register, timer 0 is selected and when "1" is written, timer 1 is selected.
Figure 4.10.6.1 shows the TOUT signal waveform when the channel is changed.
CHSEL
0
1
Timer 0 underflow
Timer 1 underflow
TOUT output (R02)
Fig. 4.10.6.1 TOUT signal waveform at channel change
The TOUT signal can be output from the R02 output port terminal. Programmable clocks can be supplied
to external devices.
Figure 4.10.6.2 shows the configuration of the output port R02.
TOUT
Data bus
Register
PTOUT
R02
(TOUT)
Register
R02
Register
R02HIZ
Fig. 4.10.6.2 Configuration of R02
The output of a TOUT signal is controlled by the PTOUT register. When "1" is written to the PTOUT
register, the TOUT signal is output from the R02 output port terminal and when "0" is written, the
terminal goes to a high (VDD) level. However, the data register R02 must always be "1" and the high
impedance control register R02HIZ must always be "0" (data output state).
Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2 cycle is
generated when the signal is turned ON and OFF by setting the register.
Figure 4.10.6.3 shows the output waveform of the TOUT signal.
R02HIZ register
Fix at "0"
R02 register
Fix at "1"
PTOUT register
"0"
"1"
"0"
TOUT output
Fig. 4.10.6.3 Output waveform of the TOUT signal
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4.10.7 Transfer rate setting for serial interface
The signal that is made from underflows of timer 1 by dividing them in 1/2, can be used as the clock
source for the serial interface.
The programmable timer outputs the clock to the serial interface by setting timer 1 into RUN state
(PTRUN = "1"). It is not necessary to control with the PTOUT register.
PTRUN1
Timer 1 underflow
Source clock for serial I/F
Fig. 4.10.7.1 Synchronous clock of serial interface
A setting value for the RLD1X register according to a transfer rate is calculated by the following expression:
RLD1X = fosc / (2 ∗ bps ∗ division ratio of the prescaler) - 1
fosc: Oscillation frequency (OSC1/OSC3)
bps: Transfer rate
(00H can be set to RLD1X)
Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source.
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4.10.8 I/O memory of programmable timer
Table 4.10.8.1 shows the I/O addresses and the control bits for the programmable timer.
Table 4.10.8.1 Control bits of programmable timer
Address
FFC0H
FFC1H
FFC2H
FFC3H
FFC4H
FFC5H
FFC6H
FFC7H
FFC8H
FFC9H
FFCAH
FFCBH
FFE2H
FFF2H
Register
Name Init ∗1
1
0 ∗3
– ∗2
0
EVCNT FCSEL PLPOL
EVCNT
0
Event ct.
FCSEL
0
With NR
R
R/W
PLPOL
0
CHSEL
0
Timer1
CHSEL PTOUT CKSEL1 CKSEL0
PTOUT
0
On
CKSEL1
0
OSC3
R/W
CKSEL0
0
OSC3
PTPS01
0
PTPS01 PTPS00 PTRST0 PTRUN0
PTPS00
0
PTRST0∗3
– ∗2 Reset
R/W
W
R/W
PTRUN0
0
Run
PTPS11
0
PTPS11 PTPS10 PTRST1 PTRUN1
PTPS10
0
PTRST1∗3
– ∗2 Reset
R/W
W
R/W
PTRUN1
0
Run
RLD03
0
RLD03 RLD02 RLD01 RLD00
RLD02
0
RLD01
0
R/W
RLD00
0
RLD07
0
RLD07 RLD06 RLD05 RLD04
RLD06
0
RLD05
0
R/W
RLD04
0
RLD13
0
RLD13 RLD12 RLD11 RLD10
RLD12
0
RLD11
0
R/W
RLD10
0
RLD17
0
RLD17 RLD16 RLD15 RLD14
RLD16
0
RLD15
0
R/W
RLD14
0
PTD03
0
PTD03 PTD02 PTD01 PTD00
PTD02
0
PTD01
0
R
PTD00
0
PTD07
0
PTD07 PTD06 PTD05 PTD04
PTD06
0
PTD05
0
R
PTD04
0
PTD13
0
PTD13 PTD12 PTD11 PTD10
PTD12
0
PTD11
0
R
PTD10
0
PTD17
0
PTD17 PTD16 PTD15 PTD14
PTD16
0
PTD15
0
R
PTD14
0
0 ∗3
– ∗2
0
0
EIPT1 EIPT0
0 ∗3
– ∗2
EIPT1
0
Enable
R
R/W
EIPT0
0
Enable
0 ∗3
– ∗2
(R)
0
0
IPT1
IPT0
0 ∗3
– ∗2
Yes
IPT1
0
(W)
R
R/W
IPT0
0
Reset
D3
D2
D1
D0
Comment
0
Unused
Timer Timer 0 counter mode selection
No NR Timer 0 function selection (for event counter mode)
Timer 0 pulse polarity selection (for event counter mode)
Timer0 TOUT output channel selection
TOUT output control
Off
OSC1 Prescaler 1 source clock selection
OSC1 Prescaler 0 source clock selection
Prescaler 0
[PTPS01, 00]
0
1
2
3
division ratio
Division ratio 1/1 1/4 1/32 1/256
selection
Invalid Timer 0 reset (reload)
Stop Timer 0 Run/Stop
Prescaler 1
[PTPS11, 10]
division ratio
Division ratio
selection
0
1/1
1
1/4
2
3
1/32 1/256
Invalid Timer 1 reset (reload)
Stop Timer 1 Run/Stop
MSB
Programmable timer 0 reload data (low-order 4 bits)
LSB
MSB
Programmable timer 0 reload data (high-order 4 bits)
LSB
MSB
Programmable timer 1 reload data (low-order 4 bits)
LSB
MSB
Programmable timer 1 reload data (high-order 4 bits)
LSB
MSB
Programmable timer 0 data (low-order 4 bits)
LSB
MSB
Programmable timer 0 data (high-order 4 bits)
LSB
MSB
Programmable timer 1 data (low-order 4 bits)
LSB
MSB
Programmable timer 1 data (high-order 4 bits)
LSB
Unused
Unused
Mask Interrupt mask register (Programmable timer 1)
Mask Interrupt mask register (Programmable timer 0)
Unused
(R)
Unused
No
(W) Interrupt factor flag (Programmable timer 1)
Invalid Interrupt factor flag (Programmable timer 0)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
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CKSEL0: Prescaler 0 source clock selection register (FFC1H•D0)
CKSEL1: Prescaler 1 source clock selection register (FFC1H•D1)
Selects the source clock of the prescaler.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading: Valid
The source clock for the prescaler is selected from OSC1 or OSC3. When "0" is written to the CKSEL0
register, the OSC1 clock is selected as the input clock for the prescaler 0 (for timer 0) and when "1" is
written, the OSC3 clock is selected.
Same as above, the source clock for prescaler 1 is selected by the CKSEL1 register.
When the event counter mode is selected to timer 0, the setting of the CKSEL0 register becomes invalid.
At initial reset, these registers are set to "0".
PTPS00, PTPS01: Timer 0 prescaler division ratio selection register (FFC2H•D2, D3)
PTPS10, PTPS11: Timer 1 prescaler division ratio selection register (FFC3H•D2, D3)
Selects the division ratio of the prescaler.
Two bits of PTPS00 and PTPS01 are the prescaler division ratio selection register for timer 0, and two bits
of PTPS10 and PTPS11 are for timer 1. The prescaler division ratios that can be set by these registers are
shown in Table 4.10.8.2.
Table 4.10.8.2 Selection of prescaler division ratio
PTPS11
PTPS01
PTPS10
PTPS00
Prescaler division ratio
1
1
1
0
Source clock / 256
Source clock / 32
0
0
1
0
Source clock / 4
Source clock / 1
When the event counter mode is selected to timer 0, the setting of the PTPS00 and PTPS01 becomes
invalid.
At initial reset, these registers are set to "0".
EVCNT: Timer 0 counter mode selection register (FFC0H•D2)
Selects a counter mode for timer 0.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading: Valid
The counter mode for timer 0 is selected from either the event counter mode or timer mode. When "1" is
written to the EVCNT register, the event counter mode is selected and when "0" is written, the timer
mode is selected.
At initial reset, this register is set to "0".
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FCSEL: Timer 0 function selection register (FFC0H•D1)
Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode.
When "1" is written: With noise rejecter
When "0" is written: Without noise rejecter
Reading: Valid
When "1" is written to the FCSEL register, the noise rejecter is used and counting is done by an external
clock (K13) with 0.98 msec* or more pulse width. The noise rejecter allows the counter to input the clock
at the second falling edge of the internal 2,048 Hz* signal after changing the input level of the K13 input
port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less.
(∗: fOSC1 = 32.768 kHz).
When "0" is written to the FCSEL register, the noise rejector is not used and the counting is done directly
by an external clock input to the K13 input port terminal.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
PLPOL: Timer 0 pulse polarity selection register (FFC0H•D0)
Selects the count pulse polarity in the event counter mode.
When "1" is written: Rising edge
When "0" is written: Falling edge
Reading: Valid
The count timing in the event counter mode (timer 0) is selected from either the falling edge of the
external clock input to the K13 input port terminal or the rising edge. When "0" is written to the PLPOL
register, the falling edge is selected and when "1" is written, the rising edge is selected.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
RLD00–RLD07: Timer 0 reload data register (FFC4H, FFC5H)
RLD10–RLD17: Timer 1 reload data register (FFC6H, FFC7H)
Sets the initial value for the counter.
The reload data written in this register is loaded to the respective counters. The counter counts down
using the data as the initial value for counting.
Reload data is loaded to the counter when the counter is reset by writing "1" to the PTRST0 or PTRST1
register, or when counter underflow occurs.
At initial reset, these registers are set to "00H".
PTD00–PTD07: Timer 0 counter data (FFC8H, FFC9H)
PTD10–PTD17: Timer 1 counter data (FFCAH, FFCBH)
Count data in the programmable timer can be read from these latches.
The low-order 4 bits of the count data in timer 0 can be read from PTD00–PTD03, and the high-order data
can be read from PTD04–PTD07. Similarly, for timer 1, the low-order 4 bits can be read from PTD10–
PTD13, and the high-order data can be read from PTD14–PTD17.
Since the high-order 4 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits
first.
Since these latches are exclusively for reading, the writing operation is invalid.
At initial reset, these counter data are set to "00H".
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PTRST0: Timer 0 reset (reload) (FFC2H•D1)
PTRST1: Timer 1 reset (reload) (FFC3H•D1)
Resets the timer and presets reload data to the counter.
When "1" is written: Reset
When "0" is written: No operation
Reading: Always "0"
By writing "1" to PTRST0, the reload data in the reload register PLD00–PLD07 is preset to the counter in
timer 0. Similarly, the reload data in PLD10–PLD17 is preset to the counter in timer 1 by PTRST1.
When the counter is preset in the RUN status, the counter restarts immediately after presetting. In the
case of STOP status, the reload data is preset to the counter and is maintained.
No operation results when "0" is written.
Since these bits are exclusively for writing, always set to "0" during reading.
PTRUN0: Timer 0 RUN/STOP control register (FFC2H•D0)
PTRUN1: Timer 1 RUN/STOP control register (FFC3H•D0)
Controls the RUN/STOP of the counter.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The counter in timer 0 starts counting down by writing "1" to the PTRUN0 register and stops by writing
"0".
In STOP status, the counter data is maintained until the counter is reset or is set in the next RUN status.
When STOP status changes to RUN status, the data that has been maintained can be used for resuming
the count.
Same as above, the timer 1 counter is controlled by the PTRUN1 register.
At initial reset, these registers are set to "0".
CHSEL: TOUT output channel selection register (FFC1H•D3)
Selects the channel used for TOUT signal output.
When "1" is written: Timer 1
When "0" is written: Timer 0
Reading: Valid
This register selects which timer's underflow (timer 0 or timer 1) is used to generate a TOUT signal. When
"0" is written to the CHSEL register, timer 0 is selected and when "1" is written, timer 1 is selected.
At initial reset, this register is set to "0".
PTOUT: TOUT output control register (FFC1H•D2)
Turns TOUT signal output ON and OFF.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
PTOUT is the output control register for the TOUT signal. When "1" is written to the register, the TOUT
signal is output from the output port terminal R02 and when "0" is written, the terminal goes to a high
(VDD) level. However, the data register R02 must always be "1" and the high impedance control register
R02HIZ must always be "0" (data output state).
At initial reset, this register is set to "0".
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EIPT0: Timer 0 interrupt mask register (FFE2H•D0)
EIPT1: Timer 1 interrupt mask register (FFE2H•D1)
These registers are used to select whether to mask the programmable timer interrupt or not.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
Timer 0 and timer 1 interrupts can be masked individually by the interrupt mask registers EIPT0 (timer 0)
and EIPT1 (timer 1).
At initial reset, these registers are set to "0".
IPT0: Timer 0 interrupt factor flag (FFF2H•D0)
IPT1: Timer 1 interrupt factor flag (FFF2H•D1)
These flags indicate the status of the programmable timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags IPT0 and IPT1 correspond to timer 0 and timer 1 interrupts, respectively. The
software can judge from these flags whether there is a programmable timer interrupt. However, even if
the interrupt is masked, the flags are set to "1" by the underflows of the corresponding counters.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
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4.10.9 Programming notes
(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.
Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec
(when fOSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge
of the input clock after writing to the PTRUN0/PTRUN1 register. Consequently, when "0" is written to
the PTRUN0/PTRUN1 register, the timer enters STOP status at the point where the counter is
decremented (-1). The PTRUN0/PTRUN1 register maintains "1" for reading until the timer actually
stops.
Figure 4.10.9.1 shows the timing chart for the RUN/STOP control.
Input clock
PTRUN0/PTRUN1 (RD)
PTRUN0/PTRUN1 (WR)
PTD0X/PTD1X
"1" (RUN)
writing
42H
"0" (STOP)
writing
41H 40H 3FH 3EH
3DH
Fig. 4.10.9.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned ON and OFF by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
4.11.1 Configuration of serial interface
The S1C63466 has a synchronous clock type 8 bits serial interface built-in.
The configuration of the serial interface is shown in Figure 4.11.1.1.
The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal. Moreover, via
the same 8-bit shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/output may be set by selecting by software any one of three
types of master mode (internal clock mode: when the S1C63466 is to be the master for serial input/
output) and a type of slave mode (external clock mode: when the S1C63466 is to be the slave for serial
input/output).
Also, when the serial interface is used at slave mode, SRDY signal which indicates whether or not the
serial interface is available to transmit or receive can be output to the SRDY terminal.
SD0–SD7
SIN
(P10)
Shift register (8 bits)
Output
latch
SOUT
(P11)
SCPS
SCS0 SCS1
SCLK
or
SCLK
(P12)
Serial clock
selector
Serial clock
generator
Serial clock
counter
Serial I/F interrupt
control circuit
Interrupt
request
fOSC1
Programmable
timer 1 underflow
signal
Serial I/F
activating
circuit
SRDY
or
SRDY
(P13)
SCTRG
Fig. 4.11.1.1 Configuration of serial interface
The input/output ports of the serial interface are shared with the I/O ports P10–P13, and function of
these ports can be selected through the software.
P10–P13 terminals and serial input/output correspondence are as follows:
Master mode
P10 = SIN (I)
P11 = SOUT (O)
P12 = SCLK (O)
P13 = I/O port (I/O)
Slave mode
P10 = SIN (I)
P11 = SOUT (O)
P12 = SCLK (I)
P13 = SRDY (O)
Note: At initial reset, P10–P13 are set to I/O ports.
When using the serial interface, switch the function (ESIF = "1") in the initial routine.
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4.11.2 Mask option
(1) Terminal specification
Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13), the
mask option that selects the output specification for the I/O port is also applied to the serial interface.
The output specification of the terminals SOUT, SCLK (during the master mode) and SRDY (during
the slave mode) that are used as output in the input/output port of the serial interface is respectively
selected by the mask options of P11, P12 and P13. Either complementary output or N-channel open
drain output can be selected as the output specification. However, when N-channel open drain output
is selected, do not apply a voltage exceeding the power supply voltage to the terminal.
Furthermore, the pull-up resistor for the SIN terminal and the SCLK terminal (during slave mode)
that are used as input terminals can be selected by the mask options of P10 and P12.
When "without pull-up" is selected, take care that the floating status does not occur.
(2) Polarity of synchronous clock and ready signal
Polarity of the synchronous clock and the ready signal that is output in the slave mode can be selected
from either positive polarity (high active, SCLK & SRDY) or negative polarity (low active, SCLK &
SRDY).
When operating the serial interface in the slave mode, the synchronous clock is input from a external
device. Be aware that the terminal specification is pull-up only and a pull-down resistor cannot be
built in if positive polarity is selected.
In the following explanation, it is assumed that negative polarity (SCLK, SRDY) has been selected.
4.11.3 Master mode and slave mode of serial interface
The serial interface of the S1C63466 has two types of operation mode: master mode and slave mode.
The master mode uses an internal clock as the synchronous clock for the built-in shift register, and
outputs this internal clock from the SCLK (P12) terminal to control the external (slave side) serial device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input
from the SCLK (P12) terminal and it is used as the synchronous clock for the built-in shift register.
The master mode and slave mode are selected by writing data to the SCS1 and SCS0 registers.
When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in
Table 4.11.3.1.
Table 4.11.3.1 Synchronous clock selection
SCS1
1
1
SCS0
1
0
Mode
Master mode
0
1
0
0
Slave mode
∗ The maximum clock is limited to 1 MHz.
Synchronous clock
OSC1
OSC1 /2
Programmable timer ∗
External clock ∗
When the programmable timer is selected, the signal that is generated by dividing the underflow signal
of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. In this case, the programmable timer must be controlled before operating the serial interface. Refer to Section 4.10, "Programmable
Timer" for the control of the programmable timer.
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8-bit serial data, is controlled as
follows:
• In the master mode, after output of 8 clocks from the SCLK (P12) terminal, clock output is automatically suspended and the SCLK (P12) terminal is fixed at high level.
• In the slave mode, after input of 8 clocks to the SCLK (P12) terminal, subsequent clock inputs are
masked.
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A sample basic serial input/output portion connection is shown in Figure 4.11.3.1.
S1C63466
External
serial device
S1C63466
External
serial device
SCLK
CLK
SCLK
CLK
SOUT
SOUT
SOUT
SOUT
SIN
SIN
SIN
Input terminal
SIN
SRDY
READY
(a) Master mode
Input terminal
(b) Slave mode
Fig. 4.11.3.1 Sample basic connection of serial input/output section
4.11.4 Data input/output and interrupt function
The serial interface of S1C63466 can input/output data via the internal 8-bit shift register. The shift
register operates by synchronizing with either the synchronous clock output from the SCLK (P12)
terminal (master mode), or the synchronous clock input to the SCLK (P12) terminal (slave mode).
The serial interface generates an interrupt on completion of the 8-bit serial data input/output. Detection
of serial data input/output is done by counting of the synchronous clock SCLK; the clock completes
input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates an
interrupt.
The serial data input/output procedure is explained below:
(1) Serial data output procedure and interrupt
The S1C63466 serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to the data registers SD0–SD3 (FF72H) and SD4–SD7 (FF73H) and writing
"1" to SCTRG bit (FF70H•D1), it synchronizes with the synchronous clock and the serial data is output
to the SOUT (P11) terminal. The synchronous clock used here is as follows: in the master mode,
internal clock which is output to the SCLK (P12) terminal while in the slave mode, external clock
which is input from the SCLK (P12) terminal.
Shift timing of serial data is as follows:
• When negative polarity is selected for the synchronous clock (mask option):
The serial data output to the SOUT (P11) terminal changes at the falling edge of the clock input or
output from/to the SCLK (P12) terminal. The data in the shift register is shifted at the falling edge of
the SCLK signal when the SCPS register (FF71H•D2) is "1" and is shifted at the rising edge of the
SCLK signal when the SCPS register is "0".
• When positive polarity is selected for the synchronous clock (mask option):
The serial data output to the SOUT (P11) terminal changes at the rising edge of the clock input or
output from/to the SCLK (P12) terminal. The data in the shift register is shifted at the rising edge of
the SCLK signal when the SCPS register is "1" and is shifted at the falling edge of the SCLK signal
when the SCPS register is "0".
When the output of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF
(FFF3H•D0) is set to "1" and an interrupt occurs. Moreover, the interrupt can be masked by the
interrupt mask register EISIF (FFE3H•D0). However, regardless of the interrupt mask register setting,
the interrupt factor flag is set to "1" after output of the 8-bit data.
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(2) Serial data input procedure and interrupt
The S1C63466 serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is
sequentially read in the 8-bit shift register. As in the above item (1), the synchronous clock used here is
as follows: in the master mode, internal clock which is output to the SCLK (P12) terminal while in the
slave mode, external clock which is input from the SCLK (P12) terminal.
Shift timing of serial data is as follows:
• When negative polarity is selected for the synchronous clock (mask option):
The serial data is read into the built-in shift register at the falling edge of the SCLK signal when the
SCPS register is "1" and is read at the rising edge of the SCLK signal when the SCPS register is "0". The
shift register is sequentially shifted as the data is fetched.
• When positive polarity is selected for the synchronous clock (mask option):
The serial data is read into the built-in shift register at the rising edge of the SCLK signal when the
SCPS register is "1" and is read at the falling edge of the SCLK signal when the SCPS register is "0".
The shift register is sequentially shifted as the data is fetched.
When the input of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to
"1" and an interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask
register EISIF. However, regardless of the interrupt mask register setting, the interrupt factor flag is
set to "1" after input of the 8-bit data.
The data input in the shift register can be read from data registers SD0–SD7 by software.
(3) Serial data input/output permutation
The S1C63466 allows the input/output permutation of serial data to be selected by the SDP register
(FF71H•D3) as to either LSB first or MSB first. The block diagram showing input/output permutation
in case of LSB first and MSB first is provided in Figure 4.11.4.1. The SDP register should be set before
setting data to SD0–SD7.
SIN
Address [FF73H]
Address [FF72H]
SD7 SD6 SD5 SD4
SD3 SD2 SD1 SD0
Output
latch
SOUT
Output
latch
SOUT
(LSB first)
SIN
Address [FF72H]
Address [FF73H]
SD0 SD1 SD2 SD3
SD4 SD5 SD6 SD7
(MSB first)
Fig. 4.11.4.1 Serial data input/output permutation
(4) SRDY signal
When the S1C63466 serial interface is used in the slave mode (external clock mode), SRDY signal is
used to indicate whether the internal serial interface is available to transmit or receive data for the
master side (external) serial device. SRDY signal is output from the SRDY (P13) terminal.
Output timing of SRDY signal is as follows:
• When negative polarity is selected (mask option):
SRDY signal goes "0" (low) when the S1C63466 serial interface is available to transmit or receive data;
normally, it is at "1" (high).
SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0" to
"1" when "0" is input to the SCLK (P12) terminal (i.e., when the serial input/output begins transmitting or receiving data). Moreover, when high-order data is read from or written to SD4–SD7, the SRDY
signal returns to "1".
• When positive polarity is selected (mask option):
SRDY signal goes "1" (high) when the S1C63466 serial interface is available to transmit or receive data;
normally, it is at "0" (low).
SRDY signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to
"0" when "1" is input to the SCLK (P12) terminal (i.e., when the serial input/output begins transmitting or receiving data). Moreover, when high-order data is read from or written to SD4–SD7, the SRDY
signal returns to "0".
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(5) Timing chart
The S1C63466 serial interface timing charts are shown in Figures 4.11.4.2 and 4.11.4.3.
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
(a) When SCPS = "1"
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
(b) When SCPS = "0"
Fig. 4.11.4.2 Serial interface timing chart (when synchronous clock is negative polarity SCLK)
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
(a) When SCPS = "1"
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
(b) When SCPS = "0"
Fig. 4.11.4.3 Serial interface timing chart (when synchronous clock is positive polarity SCLK)
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4.11.5 I/O memory of serial interface
Table 4.11.5.1 shows the I/O addresses and the control bits for the serial interface.
Table 4.11.5.1 Control bits of serial interface
Address
Register
D3
D2
PUL13
D1
PUL12
D0
PUL11
PUL10
Name
PUL13
Init ∗1
1
PUL12
1
PUL11
1
PUL10
1
0 ∗3
0 ∗3
SCTRG
– ∗2
– ∗2
0
FF45H
R/W
0
0
SCTRG
ESIF
FF70H
R
SDP
R/W
SCPS
SCS1
SCS0
ESIF
SDP
SCPS
0
0
0
SCS1
SCS0
SD3
SD2
SD1
SD0
SD7
SD6
SD5
SD4
0 ∗3
0 ∗3
0 ∗3
EISIF
0 ∗3
0 ∗3
0 ∗3
ISIF
0
0
– ∗2
– ∗2
– ∗2
– ∗2
– ∗2
– ∗2
– ∗2
– ∗2
– ∗2
– ∗2
– ∗2
0
– ∗2
– ∗2
– ∗2
0
FF71H
R/W
SD3
SD2
SD1
SD0
SD5
SD4
0
EISIF
FF72H
R/W
SD7
SD6
FF73H
R/W
0
0
FFE3H
R
0
0
R/W
0
ISIF
FFF3H
R
R/W
1
On
0
Off
Comment
P13 pull-up control register
functions as a general-purpose register when SIF (slave) is selected
Off
On
P12 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-up control register when SIF (slave) is selected
Off
On
P11 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Off
On
P10 pull-up control register (ESIF=0)
SIN pull-up control register when SIF is selected
Unused
Unused
Trigger Invalid Serial I/F clock trigger (writing)
Run
Stop Serial I/F clock status (reading)
SIF
Serial I/F enable (P1 port function selection)
I/O
MSB first LSB first Serial I/F data input/output permutation
Serial I/F clock phase selection
–Negative polarity (mask option)
0
1
[SCS1, 0]
–Positive polarity (mask option)
Slave
PT
Clock
Serial I/F
2
3
[SCS1, 0]
clock mode selection
OSC1/2 OSC1
Clock
High
MSB
Low
High
Low
Serial I/F transmit/receive data (low-order 4 bits)
High
Low
High
LSB
Low
High
MSB
Low
High
Low
Serial I/F transmit/receive data (high-order 4 bits)
High
Low
High
LSB
Low
Unused
Unused
Unused
Enable Mask Interrupt mask register (Serial I/F)
(R)
Unused
(R)
Yes
Unused
No
(W)
(W) Unused
Reset Invalid Interrupt factor flag (Serial I/F)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
ESIF: Serial interface enable register (P1 port function selection) (FF70H•D0)
Sets P10–P13 to the input/output port for the serial interface.
When "1" is written: Serial interface
When "0" is written: I/O port
Reading: Valid
When "1" is written to the ESIF register, P10, P11, P12 and P13 function as SIN, SOUT, SCLK, SRDY,
respectively.
In the slave mode, the P13 terminal functions as SRDY output terminal, while in the master mode, it
functions as the I/O port terminal.
At initial reset, this register is set to "0".
Note: After setting ESIF to "1", wait at least 10 µsec before starting actual data transfer since a hazard
may be generated from the P12 (SCLK) terminal when ESIF is set to "1".
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PUL10: SIN (P10) pull-up control register (FF45H•D0)
PUL12: SCLK (P12) pull-up control register (FF45H•D2)
Sets the pull-up of the SIN terminal and the SCLK terminals (in the slave mode).
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
Reading: Valid
Sets the pull-up resistor built into the SIN (P10) and SCLK (P12) terminals to ON or OFF. (Pull-up resistor
is only built in the port selected by mask option.)
SCLK pull-up is effective only in the slave mode. In the master mode, the PUL12 register can be used as a
general purpose register.
At initial reset, these registers are set to "1" and pull-up goes ON.
SCS1, SCS0: Clock mode selection register (FF71H•D0, D1)
Selects the synchronous clock (SCLK) for the serial interface.
Table 4.11.5.2 Synchronous clock selection
SCS1
1
1
0
0
SCS0
1
0
1
0
Mode
Master mode
Slave mode
Synchronous clock
OSC1
OSC1 /2
Programmable timer ∗
External clock ∗
∗ The maximum clock is limited to 1 MHz.
Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and
external clock.
When the programmable timer is selected, the signal that is generated by dividing the underflow signal
of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. In this case, the programmable timer must be controlled before operating the serial interface. Refer to Section 4.10, "Programmable
Timer" for the control of the programmable timer.
At initial reset, external clock is selected.
SCPS: Clock phase selection register (FF71H•D2)
Selects the timing for reading in the serial data input from the SIN (P10) terminal.
• When negative polarity is selected:
When "1" is written: Falling edge of SCLK
When "0" is written: Rising edge of SCLK
Reading: Valid
• When positive polarity is selected:
When "1" is written: Rising edge of SCLK
When "0" is written: Falling edge of SCLK
Reading: Valid
Select whether the fetching for the serial input data to registers (SD0–SD7) at the rising edge or falling
edge of the synchronous signal.
Pay attention to the polarity of the synchronous clock selected by the mask option because the selection
content is different.
The input data fetch timing may be selected but output timing for output data is fixed at the falling edge
of SCLK (when negative polarity is selected) or at the rising edge of SCLK (when positive polarity is
selected).
At initial reset, this register is set to "0".
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SDP: Data input/output permutation selection register (FF71H•D3)
Selects the serial data input/output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
Reading: Valid
Select whether the data input/output permutation will be MSB first or LSB first.
At initial reset, this register is set to "0".
SCTRG: Clock trigger/status (FF70H•D1)
This is a trigger to start input/output of synchronous clock (SCLK).
• When writing
When "1" is written: Trigger
When "0" is written: No operation
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK)
input/output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial interface with the ESIF
register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from performing trigger input multiple times, as leads to malfunctioning.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
• When reading
When "1" is read: RUN (during input/output the synchronous clock)
When "0" is read: STOP (the synchronous clock stops)
Writing: Invalid
When this bit is read, it indicates the status of serial interface clock.
After "1" is written to SCTRG, this value is latched till serial interface clock stops (8 clock counts). Therefore, if "1" is read, it indicates that the synchronous clock is in input/output operation.
When the synchronous clock input/output is completed, this latch is reset to "0".
At initial reset, this bit is set to "0".
SD0–SD3, SD4–SD7: Serial interface data register (FF72H, FF73H)
These registers are used for writing and reading serial data.
• When writing
When "1" is written: High level
When "0" is written: Low level
Write data to be output in these registers. The register data is converted into serial data and output from
the SOUT (P11) terminal; data bits set at "1" are output as high (VDD) level and data bits set at "0" are
output as low (VSS) level.
• When reading
When "1" is read: High level
When "0" is read: Low level
The serial data input from the SIN (P10) terminal can be read from these registers.
The serial data input from the SIN (P10) terminal is converted into parallel data, as a high (VDD) level bit
into "1" and as a low (VSS) level bit into "0", and is loaded to these registers. Perform data reading only
while the serial interface is not running (i.e., the synchronous clock is neither being input or output).
At initial reset, these registers are undefined.
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EISIF: Interrupt mask register (FFE3H•D0)
Masking the interrupt of the serial interface can be selected with this register.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
With this register, it is possible to select whether the serial interface interrupt is to be masked or not.
At initial reset, this register is set to "0".
ISIF: Interrupt factor flag (FFF3H•D0)
This flag indicates the occurrence of serial interface interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
From the status of this flag, the software can decide whether the serial interface interrupt.
This flag is set to "1" after an 8-bit data input/output even if the interrupt is masked.
This flag is reset to "0" by writing "1" to it.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, this flag is set to "0".
4.11.6 Programming notes
(1) Perform data writing/reading to the data registers SD0–SD7 only while the serial interface is not
running (i.e., the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be
performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial
interface with the ESIF register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from
performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous
clock SCLK is external clock, start to input the external clock after the trigger.
(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source of the programmable timer or in the slave mode.
(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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4.12 Sound Generator
4.12.1 Configuration of sound generator
The S1C63466 has a built-in sound generator for generating buzzer signals.
Hence, generated buzzer signals (BZ) can be output from the BZ terminal.
Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it
permits the adding of a digital envelope by means of duty ratio control. It also has a one-shot output
function for outputting key operated sounds.
Figure 4.12.1.1 shows the configuration of the sound generator.
fOSC1
256 Hz
BZFQ0–BZFQ2
BDTY0–BDTY2
ENON
Programmable
dividing circuit
Duty ratio
control circuit
Envelope
addition circuit
ENRTM
Buzzer output
control circuit
BZ
output circuit
One-shot buzzer
control circuit
BZSHT
ENRST
BZE
BZSTP
SHTPW
Fig. 4.12.1.1 Configuration of sound generator
Note: The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and
times that are described in this section are the values in the case of crystal oscillation (32.768 kHz,
Typ.), they differ when CR oscillation (60 kHz, Typ.) is selected.
4.12.2 Mask option
Polarity of the BZ signal output from the BZ terminal can be selected as either positive polarity or
negative polarity by mask option. Figure 4.12.2.1 shows each output circuit configuration and the output
waveform.
When positive polarity is selected, the BZ terminal goes to a low (VSS) level when the BZ signal is OFF.
Select positive polarity when driving a piezo buzzer by externally connecting an NPN transistor.
When negative polarity is selected, the BZ terminal goes to a high (VDD) level when the BZ signal is OFF.
Select negative polarity when driving a piezo buzzer by externally connecting a PNP transistor.
VDD
VDD
BZ terminal
BZ signal
BZ terminal
BZ signal
VSS
VSS
(a) When positive polarity is selected
(b) When negative polarity is selected
Fig. 4.12.2.1 Configuration of output circuit
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4.12.3 Control of buzzer output
The BZ signal generated by the sound generator is output from the BZ terminal by setting "1" for the
buzzer output enable register BZE. When "0" is set to BZE register, the output terminal shifts to the low
(VSS) level (negative polarity) or high (VDD) level (positive polarity).
BZE register "0"
"1"
"0"
BZ output/BZ terminal
(Negative polarity)
BZ output/BZ terminal
(Positive polarity)
Fig. 4.12.3.1 Buzzer signal output timing chart
Note: Since it generates a BZ signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes ON/OFF due to the setting of the BZE register.
4.12.4 Setting of buzzer frequency and sound level
The divided signal of the OSC1 oscillation clock (32.768 kHz) is used for the buzzer (BZ) signal and it is
set up such that 8 types of frequencies can be selected by changing this division ratio. Frequency selection
is done by setting the buzzer frequency selection registers BZFQ0–BZFQ2 as shown in Table 4.12.4.1.
Table 4.12.4.1 Buzzer signal frequency setting
BZFQ2
0
0
0
BZFQ1
0
0
1
BZFQ0
0
1
0
Buzzer frequency (Hz)
4096.0
3276.8
2730.7
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
2340.6
2048.0
1638.4
1365.3
1170.3
The buzzer sound level is changed by controlling the duty ratio of the buzzer signal.
The duty ratio can be selected from among the 8 types shown in Table 4.12.4.2 according to the setting of
the buzzer duty selection registers BDTY0–BDTY2.
Table 4.12.4.2 Duty ratio setting
Level
Level 1 (Max.)
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8 (Min.)
BDTY2 BDTY1 BDTY0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Duty ratio by buzzer frequency (Hz)
4096.0
3276.8
2730.7
2340.6
2048.0
1638.4
1365.3
1170.3
8/16
8/20
12/24
12/28
7/16
7/20
11/24
11/28
6/16
6/20
10/24
10/28
5/16
5/20
9/24
9/28
4/16
4/20
8/24
8/28
3/16
3/20
7/24
7/28
2/16
2/20
6/24
6/28
1/16
1/20
5/24
5/28
When the HIGH level output time has been made TH and when the LOW level output time has been made
TL due to the ratio of the pulse width to the pulse synchronization, the duty ratio becomes TL/(TH+TL)
for negative polarity or TH/(TH+TL) for positive polarity.
When BDTY0–BDTY2 have all been set to "0", the duty ratio becomes maximum and the sound level also
becomes maximum. Conversely, when BDTY0–BDTY2 have all been set to "1", the duty ratio becomes
minimum and the sound level also becomes minimum.
The duty ratio that can be set is different depending on the frequency that has been set, so see Table 4.12.4.2.
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TH TL
TL TH
Level 1 (Max.)
Level 1 (Max.)
Level 2
Level 2
Level 3
Level 3
Level 4
Level 4
Level 5
Level 5
Level 6
Level 6
Level 7
Level 7
Level 8 (Min.)
Level 8 (Min.)
(a) Negative polarity
(b) Positive polarity
Fig. 4.12.4.1 Duty ratio of the buzzer signal waveform
Note: When a digital envelope has been added to the buzzer signal, the BDTY0–BDTY2 settings will be
invalid due to the control of the duty ratio.
4.12.5 Digital envelope
A digital envelope for duty control can be added to the buzzer signal.
The envelope can be controlled by staged changing of the same duty envelope as detailed in Table
4.12.4.2 in the preceding item from level 1 (maximum) to level 8 (minimum).
The addition of an envelope to the buzzer signal can be done by writing "1" into ENON, but when "0" has
been written it is not added.
When a buzzer signal output is begun (writing "1" into BZE) after setting ENON, the duty ratio shifts to
level 1 (maximum) and changes in stages to level 8.
When attenuated down to level 8 (minimum), it is retained at that level. The duty ratio can be returned to
maximum, by writing "1" into register ENRST during output of a envelope attached buzzer signal.
The envelope attenuation time (time for changing of the duty ratio) can be selected by the register
ENRTM. The time for a 1 stage level change is 62.5 msec (16 Hz), when "0" has been written into ENRTM
and 125 msec (8 Hz), when to "1" has been written. However, there is also a max. 4 msec error from
envelope ON, up to the first change.
Figure 4.12.5.1 shows the timing chart of the digital envelope.
No change of duty level
BZFQ0–2
ENON
ENRST
ENRTM
BZE
BZ signal
duty ratio
Level 1 (Max.)
2
3
4
5
6
7
8 (Min.)
t01
t02
t03
t04
t05
t06
t07
t01
+0
62.5 –4
msec
t01 =
t02–07 = 62.5 msec
t11
t12
t13
t14
t15
t16
t17
+0
125 –4
t11 =
msec
t12–17 = 125 msec
Fig. 4.12.5.1 Timing chart for digital envelope
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)
4.12.6 One-shot output
The sound generator has a one-shot output function for outputting a short duration buzzer signal for key
operation sounds and similar effects. Either 125 msec or 31.25 msec can be selected by SHTPW register
for one-shot buzzer signal output time.
The output of the one-shot buzzer is controlled by writing "1" into the one-shot buzzer trigger BZSHT.
When this trigger has been assigned, a buzzer signal in synchronization with the internal 256 Hz signal is
output from the BZ terminal. Thereafter, when the set time has elapsed, a buzzer signal in synchronization with the 256 Hz signal goes off in the same manner as for the start of output.
The BZSHT also permits reading. When BZSHT is "1", the one-shot output circuit is in operation (during
one-shot output) and when it is "0", it shows that the circuit is in the ready (outputtable) status.
In addition, it can also terminate one-shot output prior to the elapsing of the set time. This is done by
writing a "1" into the one-shot buzzer stop BZSTP. In this case as well, the buzzer signal goes OFF in
synchronization with the 256 Hz signal.
When "1" is written to BZSHT again during a one-shot output, a new one-shot output for 125 msec or
31.25 msec starts from that point (in synchronization with the 256 Hz signal).
The one-shot output cannot add an envelope for short durations. However, the sound level can be set by
selecting the duty ratio, and the frequency can also be set.
One-shot output is invalid during normal buzzer output (during BZE = "1").
Figure 4.12.6.1 shows timing chart for one-shot output.
256 Hz
SHTPW
BZSHT (W)
BZSHT (R)
BZSTP
BZ output (Negative polarity)
BZ output (Positive polarity)
Fig. 4.12.6.1 Timing chart for one-shot output
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4.12.7 I/O memory of sound generator
Table 4.12.7.1 shows the I/O addresses and the control bits for the sound generator.
Table 4.12.7.1 Control bits of sound generator
Address
Register
D3
D2
ENRTM ENRST
FF6CH
R/W
W
0
BZSTP
R
W
0
BZFQ2
FF6DH
FF6EH
R
0
FF6FH
R
BDTY2
Name Init ∗1
1
0
ENRTM
0
1 sec 0.5 sec
ENON
BZE
ENRST∗3 Reset Reset Invalid
ENON
0
On
Off
R/W
BZE
0
Enable Disable
0 ∗3
– ∗2
BZSHT SHTPW BZSTP∗3
0
Stop
Invalid
BZSHT
0
Trigger Invalid
Busy Ready
R/W
SHTPW
0
125 msec 31.25 msec
0 ∗3
– ∗2
BZFQ1 BZFQ0
BZFQ2
0
BZFQ1
0
R/W
BZFQ0
0
0 ∗3
– ∗2
BDTY1 BDTY0
BDTY2
0
BDTY1
0
R/W
BDTY0
0
D1
Comment
D0
Envelope releasing time
Envelope reset (writing)
Envelope On/Off
Buzzer output enable
Unused
1-shot buzzer stop (writing)
1-shot buzzer trigger (writing)
1-shot buzzer status (reading)
1-shot buzzer pulse width setting
Unused
[BZFQ2, 1, 0]
0
1
2
3
Buzzer
Frequency (Hz) 4096.0 3276.8 2730.7 2340.6
frequency
[BZFQ2, 1, 0]
4
5
6
7
Frequency (Hz) 2048.0 1638.4 1365.3 1170.3
selection
Unused
Buzzer signal duty ratio selection
(refer to main manual)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
BZE: BZ output control register (FF6CH•D0)
Controls the buzzer (BZ) signal output.
When "1" is written: BZ output ON
When "0" is written: BZ output OFF
Reading: Valid
When "1" is written to BZE, the BZ signal is output from the BZ terminal.
When "0" is written, the BZ terminal goes to a high (VDD) level.
At initial reset, this register is set to "0".
BZFQ0–BZFQ2: Buzzer frequency selection register (FF6EH•D0–D2)
Selects the buzzer signal frequency.
Table 4.12.7.2 Buzzer signal frequency setting
BZFQ2
0
0
0
0
1
1
1
1
BZFQ1
0
0
1
1
0
0
1
1
BZFQ0
0
1
0
1
0
1
0
1
Buzzer frequency (Hz)
4096.0
3276.8
2730.7
2340.6
2048.0
1638.4
1365.3
1170.3
Select the buzzer frequency from among the above 8 types that have divided the oscillation clock.
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)
BDTY0–BDTY2: Duty level selection register (FF6FH•D0–D2)
Selects the duty ratio of the buzzer signal as shown in Table 4.12.7.3.
Table 4.12.7.3 Duty ratio setting
Level
BDTY2 BDTY1 BDTY0
Level 1 (Max.)
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8 (Min.)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Duty ratio by buzzer frequency (Hz)
4096.0
3276.8
2730.7
2340.6
2048.0
1638.4
1365.3
1170.3
8/16
8/20
12/24
12/28
7/16
7/20
11/24
11/28
6/16
6/20
10/24
10/28
5/16
5/20
9/24
9/28
4/16
4/20
8/24
8/28
3/16
3/20
7/24
7/28
2/16
2/20
6/24
6/28
1/16
1/20
5/24
5/28
The sound level of this buzzer can be set by selecting this duty ratio.
However, when the envelope has been set to ON (ENON = "1"), this setting becomes invalid.
At initial reset, this register is set to "0".
ENRST: Envelope reset (FF6CH•D2)
Resets the envelope.
When "1" is written: Reset
When "0" is written: No operation
Reading: Always "0"
Writing "1" into ENRST resets envelope and the duty ratio becomes maximum. If an envelope has not
been added (ENON = "0") and if no buzzer signal is being output, the reset becomes invalid. Writing "0"
is also invalid.
This bit is dedicated for writing, and is always "0" for reading.
ENON: Envelope ON/OFF control register (FF6CH•D1)
Controls the addition of an envelope onto the buzzer signal.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
Writing "1" into the ENON causes an envelope to be added during buzzer signal output. When a "0" has
been written, an envelope is not added.
At initial reset, this register is set to "0".
ENRTM: Envelope releasing time selection register (FF6CH•D3)
Selects the envelope releasing time that is added to the buzzer signal.
When "1" is written: 1.0 sec (125 msec × 7 = 875 msec)
When "0" is written: 0.5 sec (62.5 msec × 7 = 437.5 msec)
Reading: Valid
The releasing time of the digital envelope is determined by the time for converting the duty ratio.
When "1" has been written in ENRTM, it becomes 125 msec (8 Hz) units and when "0" has been written, it
becomes 62.5 msec (16 Hz) units.
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)
SHTPW: One-shot buzzer pulse width setting register (FF6DH•D0)
Selects the output time of the one-shot buzzer.
When "1" is written: 125 msec
When "0" is written: 31.25 msec
Reading: Valid
Writing "1" into SHTPW causes the one-short output time to be set at 125 msec, and writing "0" causes it
to be set to 31.25 msec. It does not affect normal buzzer output.
At initial reset, this register is set to "0".
BZSHT: One-shot buzzer trigger/status (FF6DH•D1)
Controls the one-shot buzzer output.
• When writing
When "1" is written: Trigger
When "0" is written: No operation
Writing "1" into BZSHT causes the one-short output circuit to operate and a buzzer signal to be output.
This output is automatically turned OFF after the time set by SHTPW has elapsed. The one-shot output is
only valid when the normal buzzer output is OFF (BZE = "0") and will be invalid when the normal buzzer
output is ON (BZE = "1"). When a re-trigger is assigned during a one-shot output, the one-shot output
time set with SHTPW is measured again from that point (time extension).
• When reading
When "1" is read: BUSY
When "0" is read: READY
During reading BZSHT shows the operation status of the one-shot output circuit. During one-shot
output, BZSHT becomes "1" and the output goes OFF, it shifts to "0".
At initial reset, this bit is set to "0".
BZSTP: One-shot buzzer stop (FF6DH•D2)
Stops the one-shot buzzer output.
When "1" is written: Stop
When "0" is written: No operation
Reading: Always "0"
Writing "1" into BZSTP permits the one-shot buzzer output to be turned OFF prior to the elapsing of the
time set by SHTPW. Writing "0" is invalid and writing "1" is also invalid except during one-shot output.
This bit is dedicated for writing, and is always "0" for reading.
4.12.8 Programming notes
(1) Since it generates a BZ signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes ON/OFF due to the setting of the BZE register.
(2) The one-shot output is only valid when the normal buzzer output is OFF (BZE = "0") and will be
invalid when the normal buzzer output is ON (BZE = "1").
(3) The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and times
that are described in this section are the values in the case of crystal oscillation (32.768 kHz, Typ.),
they differ when CR oscillation (60 kHz, Typ.) is selected.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.13 SVD (Supply Voltage Detection) Circuit
4.13.1 Configuration of SVD circuit
The S1C63466 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the
source voltage lowers. It is possible to check an external voltage drop, other than the supply voltage, by
mask option.
Turning the SVD circuit ON/OFF and the SVD criteria voltage setting can be done with software.
Figure 4.13.1.1 shows the configuration of the SVD circuit.
VDD
SVD circuit
Detection output
SVDDT
Data bus
SVD
terminal
SVDON
VSS
SVDS3
|
SVDS0
Criteria voltage
setting circuit
Fig. 4.13.1.1 Configuration of SVD circuit
4.13.2 Mask option
Besides the supply voltage (VDD terminal–VSS terminal) drop detection, the SVD circuit can detect the
external voltage (SVD terminal–VSS terminal) input from the SVD terminal by comparing it with the
detected voltage (1.05 V). This function can select whether or not to use with the mask option.
4.13.3 SVD operation
The SVD circuit compares the criteria voltage set by software and the supply voltage (VDD terminal–VSS
terminal) or the external voltage (SVD terminal–VSS terminal) and sets its results into the SVDDT latch.
By reading the data of this SVDDT latch, it can be determined by means of software whether the supply
voltage is normal or has dropped.
The criteria voltage can be set for the 16 types shown in Table 4.13.3.1 by the SVDS3–SVDS0 registers.
When "0" is written to the SVDS3–SVDS0 register, the supply voltage detection voltage is set to 1.85 V.
However, when "External voltage detection" is selected by mask option, the SVD circuit does not compare
the supply voltage (VDD terminal–VSS terminal) but compares between the external voltage (SVD terminal–VSS terminal) input from the SVD terminal and 1.05 V.
Table 4.13.3.1 Criteria voltage setting
SVDS3 SVDS2 SVDS1 SVDS0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
S1C63466 TECHNICAL MANUAL
1
0
1
0
1
0
1
0
Criteria
voltage (V)
2.50
2.40
2.30
2.20
2.10
2.00
1.90
1.85/1.05
SVDS3 SVDS2 SVDS1 SVDS0
1
1
1
1
1
1
1
1
EPSON
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Criteria
voltage (V)
3.30
3.20
3.10
3.00
2.90
2.80
2.70
2.60
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
When the SVDON register is set to "1", source voltage or external voltage detection by the SVD circuit is
executed. As soon as the SVDON register is reset to "0", the result is loaded to the SVDDT latch and the
SVD circuit goes OFF.
To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the SVD
detection result, follow the programming sequence below.
1.
2.
3.
4.
Set SVDON to "1"
Maintain for 100 µsec minimum
Set SVDON to "0"
Read SVDDT
When the SVD circuit is ON, the IC draws a large current, so keep the SVD circuit off unless it is.
4.13.4 I/O memory of SVD circuit
Table 4.13.4.1 shows the I/O addresses and the control bits for the SVD circuit.
Table 4.13.4.1 Control bits of SVD circuit
Address
FF04H
FF05H
Register
Name Init ∗1
SVDS3
0
SVDS3 SVDS2 SVDS1 SVDS0
SVDS2
0
SVDS1
0
R/W
SVDS0
0
0 ∗3
– ∗2
0
0
SVDDT SVDON
0 ∗3
– ∗2
SVDDT
0
R
R/W
SVDON
0
D3
D2
D1
D0
1
0
Low
On
Comment
SVD criteria voltage setting
[SVDS3–0] 0
1
2
3
4
5
6
7
Voltage(V) 1.85/1.05 1.90 2.00 2.10 2.20 2.30 2.40 2.50
[SVDS3–0] 8
9
10
11
12
13
14
15
Voltage(V) 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30
Unused
Unused
Normal SVD evaluation data
Off
SVD circuit On/Off
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
SVDS3–SVDS0: SVD criteria voltage setting register (FF04H)
Criteria voltage for SVD is set as shown in Table 4.13.3.1.
At initial reset, this register is set to "0".
SVDON: SVD control (ON/OFF) register (FF05H•D0)
Turns the SVD circuit ON and OFF.
When "1" is written: SVD circuit ON
When "0" is written: SVD circuit OFF
Reading: Valid
When the SVDON register is set to "1", a source voltage detection is executed by the SVD circuit. As soon
as SVDON is reset to "0", the result is loaded to the SVDDT latch. To obtain a stable detection result, the
SVD circuit must be ON for at least l00 µsec.
At initial reset, this register is set to "0".
SVDDT: SVD data (FF05H•D1)
This is the result of supply voltage detection.
When "0" is read: Supply voltage (VDD–VSS) ≥ Criteria voltage
When "1" is read: Supply voltage (VDD–VSS) < Criteria voltage
Writing: Invalid
The result of supply voltage detection at time of SVDON is set to "0" can be read from this latch.
At initial reset, SVDDT is set to "0".
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4.13.5 Programming notes
(1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the
SVD detection result, follow the programming sequence below.
1.
2.
3.
4.
Set SVDON to "1"
Maintain for 100 µsec minimum
Set SVDON to "0"
Read SVDDT
(2) The SVD circuit should normally be turned OFF because SVD operation increase current consumption.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.14 Interrupt and HALT
<Interrupt types>
The S1C63466 provides the following interrupt functions.
External interrupt: • Input interrupt
(2 systems)
Internal interrupt: • Watchdog timer interrupt
• Programmable timer interrupt
• Serial interface interrupt
• Timer interrupt
• Stopwatch timer interrupt
(NMI, 1 system)
(2 systems)
(1 system)
(4 systems)
(2 systems)
To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask
registers must be set to "1" (enable).
When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are
inhibited.
The watchdog timer interrupt is an NMI (non-maskable interrupt), therefore, the interrupt is generated
regardless of the interrupt flag setting. Also the interrupt mask register is not provided. However, it is
possible to not generate NMI since software can stop the watchdog timer operation.
Figure 4.14.1 shows the configuration of the interrupt circuit.
Note: After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of
them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the
other one is set.
<HALT>
The S1C63466 has HALT functions that considerably reduce the current consumption when it is not
necessary.
The CPU enters HALT status when the HALT instruction is executed.
In HALT status, the operation of the CPU is stopped. However, timers continue counting since the
oscillation circuit operates. Reactivating the CPU from HALT status is done by generating a hardware
interrupt request including NMI.
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IPT0
NMI
interrupt request
Watchdog timer
EIPT0
IPT1
EIPT1
ISIF
Interrupt
vector
generation
circuit
EISIF
K00
Program counter
(low-order 4 bits)
KCP00
SIK00
K01
KCP01
INT
interrupt request
SIK01
IK0
K02
EIK0
KCP02
Interrupt flag
SIK02
K03
KCP03
SIK03
K10
KCP10
SIK10
K11
KCP11
Interrupt factor flag
SIK11
IK1
K12
Interrupt mask register
EIK1
KCP12
Input comparison register
SIK12
Interrupt selection register
K13
KCP13
SIK13
IT3
EIT3
IT2
EIT2
IT1
EIT1
IT0
EIT0
ISW1
EISW1
ISW10
EISW10
Fig. 4.14.1 Configuration of the interrupt circuit
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4.14.1 Interrupt factor
Table 4.14.1.1 shows the factors for generating interrupt requests.
The interrupt flags are set to "1" depending on the corresponding interrupt factors.
The CPU operation is interrupted when an interrupt factor flag is set to "1" if the following conditions are
established.
• The corresponding mask register is "1" (enabled)
• The interrupt flag is "1" (EI)
The interrupt factor flag is reset to "0" when "1" is written.
At initial reset, the interrupt factor flags are reset to "0".
∗ Since the watchdog timer's interrupt is NMI, the interrupt is generated regardless of the setting above,
and no interrupt factor flag is provided.
Table 4.14.1.1 Interrupt factors
Interrupt factor
Programmable timer 1 (counter = 0)
Programmable timer 0 (counter = 0)
Serial interface (8-bit data input/output completion)
K00–K03 input (falling edge or rising edge)
K10–K13 input (falling edge or rising edge)
Clock timer 1 Hz (falling edge)
Interrupt factor flag
(FFF2H•D1)
IPT1
(FFF2H•D0)
IPT0
(FFF3H•D0)
ISIF
(FFF4H•D0)
IK0
Clock timer 2 Hz (falling edge)
Clock timer 8 Hz (falling edge)
Clock timer 32 Hz (falling edge)
IT2
IT1
IT0
(FFF5H•D0)
(FFF6H•D3)
(FFF6H•D2)
(FFF6H•D1)
(FFF6H•D0)
Stopwatch timer (1 Hz)
Stopwatch timer (10 Hz)
ISW1
ISW10
(FFF7H•D1)
(FFF7H•D0)
IK1
IT3
Note: After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be
sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to
the interrupt enabled state.
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4.14.2 Interrupt mask
The interrupt factor flags can be masked by the corresponding interrupt mask registers.
The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is
written to them, and masked (interrupt inhibited) when "0" is written to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.14.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.
Table 4.14.2.1 Interrupt mask registers and interrupt factor flags
Interrupt mask register
(FFE2H•D1)
EIPT1
(FFE2H•D0)
EIPT0
EISIF
EIK0
EIK1
(FFE3H•D0)
ISIF
(FFE4H•D0)
(FFE5H•D0)
IK0
(FFE 6H•D3)
EIT3
EIT2
EIT1
(FFE6H•D2)
(FFE6H•D1)
(FFE6H•D0)
EIT0
EISW1
EISW10
Interrupt factor flag
(FFF2H•D1)
IPT1
(FFF2H•D0)
IPT0
(FFE7H•D1)
(FFE7H•D0)
IK1
IT3
IT2
IT1
IT0
ISW1
ISW10
(FFF3H•D0)
(FFF4H•D0)
(FFF5H•D0)
(FFF6H•D3)
(FFF6H•D2)
(FFF6H•D1)
(FFF6H•D0)
(FFF7H•D1)
(FFF7H•D0)
4.14.3 Interrupt vector
When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program
being executed is terminated, the interrupt processing is executed in the following order.
1
The content of the flag register is evacuated, then the I flag is reset.
2
The address data (value of program counter) of the program to be executed next is saved in the stack
area (RAM).
3
The interrupt request causes the value of the interrupt vector (0100H–010EH) to be set in the program
counter.
4
The program at the specified address is executed (execution of interrupt processing routine by
software).
Table 4.14.3.1 shows the correspondence of interrupt requests and interrupt vectors.
Table 4.14.3.1 Interrupt request and interrupt vectors
Interrupt vector
Interrupt factor
0100H
Watchdog timer
0104H
Programmable timer
0106H
Serial interface
0108H
010AH
010CH
K00–K03 input
K10–K13 input
Clock timer
010EH
Stopwatch timer
Priority
High
Low
The four low-order bits of the program counter are indirectly addressed through the interrupt request.
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4.14.4 I/O memory of interrupt
Tables 4.14.4.1(a) and (b) show the I/O addresses and the control bits for controlling interrupts.
Table 4.14.4.1(a) Control bits of interrupt (1)
Address
Register
D3
D2
D1
D0
SIK03
SIK02
SIK01
SIK00
FF20H
R/W
KCP03 KCP02 KCP01 KCP00
FF22H
R/W
SIK13
SIK12
SIK11
SIK10
FF24H
R/W
KCP13 KCP12 KCP11 KCP10
FF26H
R/W
0
0
EIPT1
EIPT0
FFE2H
R
0
R/W
0
0
EISIF
FFE3H
R
0
R/W
0
0
EIK0
FFE4H
R
0
R/W
0
0
EIK1
FFE5H
R
EIT3
R/W
EIT2
EIT1
EIT0
FFE6H
R/W
0
0
EISW1 EISW10
FFE7H
R
R/W
1
Name Init ∗1
SIK03
0
Enable
SIK02
0
Enable
SIK01
0
Enable
SIK00
0
Enable
KCP03
1
KCP02
1
KCP01
1
KCP00
1
SIK13
0
Enable
SIK12
0
Enable
SIK11
0
Enable
SIK10
0
Enable
KCP13
1
KCP12
1
KCP11
1
KCP10
1
– ∗2
0 ∗3
0 ∗3
– ∗2
EIPT1
0
Enable
EIPT0
0
Enable
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
EISIF
0
Enable
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
EIK0
0
Enable
0 ∗3
– ∗2
0 ∗3
– ∗2
0 ∗3
– ∗2
EIK1
0
Enable
EIT3
0
Enable
EIT2
0
Enable
EIT1
0
Enable
EIT0
0
Enable
0 ∗3
– ∗2
0 ∗3
– ∗2
EISW1
0
Enable
EISW10
0
Enable
0
Disable
Disable
Disable
Disable
Comment
K00–K03 interrupt selection register
K00–K03 input comparison register
Disable
Disable
Disable
Disable
K10–K13 interrupt selection register
K10–K13 input comparison register
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Unused
Unused
Interrupt mask register (Programmable timer 1)
Interrupt mask register (Programmable timer 0)
Unused
Unused
Unused
Interrupt mask register (Serial I/F)
Unused
Unused
Unused
Interrupt mask register (K00–K03)
Unused
Unused
Unused
Interrupt mask register (K10–K13)
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 8 Hz)
Interrupt mask register (Clock timer 32 Hz)
Unused
Unused
Interrupt mask register (Stopwatch timer 1 Hz)
Interrupt mask register (Stopwatch timer 10 Hz)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
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Table 4.14.4.1(b) Control bits of interrupt (2)
Address
Register
D3
D2
D1
D0
0
0
IPT1
IPT0
FFF2H
R
0
R/W
0
0
ISIF
FFF3H
R
0
R/W
0
0
IK0
FFF4H
R
0
R/W
0
0
IK1
FFF5H
R
IT3
R/W
IT2
IT1
IT0
ISW1
ISW10
FFF6H
R/W
0
0
FFF7H
R
R/W
Name
0 ∗3
0 ∗3
IPT1
IPT0
0 ∗3
0 ∗3
0 ∗3
ISIF
0 ∗3
0 ∗3
0 ∗3
IK0
0 ∗3
0 ∗3
0 ∗3
IK1
IT3
IT2
IT1
IT0
0 ∗3
0 ∗3
ISW1
ISW10
Init *1
– ∗2
– ∗2
0
0
– ∗2
– ∗2
– ∗2
0
– ∗2
– ∗2
– ∗2
0
– ∗2
– ∗2
– ∗2
0
0
0
0
0
– ∗2
– ∗2
0
0
1
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
0
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
Comment
Unused
Unused
Interrupt factor flag (Programmable timer 1)
Interrupt factor flag (Programmable timer 0)
Unused
Unused
Unused
Interrupt factor flag (Serial I/F)
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
Unused
Unused
Unused
Interrupt factor flag (K10–K13)
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 32 Hz)
Unused
Unused
Interrupt factor flag (Stopwatch timer 1 Hz)
Interrupt factor flag (Stopwatch timer 10 Hz)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
EIPT1, EIPT0: Interrupt mask registers (FFE2H•D1, D0)
IPT1, IPT0: Interrupt factor flags (FFF2H•D1, D0)
Refer to Section 4.10, "Programmable Timer".
EISIF: Interrupt mask register (FFE3H•D0)
ISIF: Interrupt factor flag (FFF3H•D0)
Refer to Section 4.11, "Serial Interface".
KCP03–KCP00, KCP13–KCP10:
SIK03–SIK00, SIK13–SIK10:
EIK0, EIK1:
IK0, IK1:
Input comparison registers (FF22H, FF26H)
Interrupt selection registers (FF20H, FF24H)
Interrupt mask registers (FFE4H•D0, FFE5H•D0)
Interrupt factor flags (FFF4H•D0, FFF5H•D0)
Refer to Section 4.4, "Input Ports".
EIT3–EIT0: Interrupt mask registers (FFE6H)
IT3–IT0: Interrupt factor flags (FFF6H)
Refer to Section 4.8, "Clock Timer".
EISW1, EISW10: Interrupt mask registers (FFE7H•D1, D0)
ISW1, ISW10: Interrupt factor flags (FFF7H•D1, D0)
Refer to Section 4.9, "Stopwatch Timer".
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4.14.5 Programming notes
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is
set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one
is set.
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CHAPTER
5 SUMMARY OF NOTES
5.1 Notes for Low Current Consumption
The S1C63466 contains control registers for each of the circuits so that current consumption can be
reduced.
These control registers reduce the current consumption through programs that operate the circuits at the
minimum levels.
The following lists the circuits that can control operation and their control registers. Refer to these when
programming.
Table 5.1.1 Circuits and control registers
Circuit (and item)
CPU
Control register
HALT instruction
CPU operating frequency
Oscillation system voltage regulator
CLKCHG, OSCC
VDC
LCD system voltage circuit
SVD circuit
LPWR
SVDON
Refer to Chapter 7, "Electrical Characteristics" for current consumption.
Below are the circuit statuses at initial reset.
CPU: Operating status
CPU operating frequency: Low speed side (CLKCHG = "0")
OSC3 oscillation circuit is in OFF status (OSCC = "0")
Oscillation system voltage regulator: Low speed side 1.3 V (VDC = "0")
However, it is fixed at 2.2 V when the CR oscillation circuit has
been selected as the OSC1 oscillation circuit. Whether the VDC
register value is "0" or "1" does not matter.
LCD system voltage circuit: OFF status (LPWR = "0")
SVD circuit: OFF status (SVDON = "0")
Also, be careful about panel selection because the current consumption can differ by the order of several
µA on account of the LCD panel characteristics.
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5.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category. Keep these notes well in mind when
programming.
Memory and stack
(1) Memory is not implemented in unused areas within the memory map. Further, some non-implementation areas and unused (access prohibition) areas exist in the display memory area and the peripheral
I/O area. If the program that accesses these areas is generated, its operation cannot be guaranteed.
Refer to Section 4.7.5, "Display memory", for the display memory, and the I/O memory maps shown
in Tables 4.1.1 (a)–(e) for the peripheral I/O area.
(2) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay
attention not to overlap the data area and stack area.
(3) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C63466 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access.
After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and
SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts
including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must
be done as a pair.
Watchdog timer
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.
(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled
state (not used) before generating an interrupt (NMI) if it is not used.
Oscillation circuit
(1) When switching the CPU system clock from OSC1 to OSC3, first set VD1. After that maintain 2.5 msec
or more, and then turn the OSC3 oscillation ON.
When switching from OSC3 to OSC1, set VD1 after switching to OSC1 and turning the OSC3 oscillation OFF. However, when the CR oscillation circuit has been selected as the OSC1 oscillation circuit, it
is not necessary to set VD1.
(2) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(3) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation OFF. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(4) When the CR oscillation circuit has been selected as the OSC1 oscillation circuit by mask option, it is
not necessary to switch the operating voltage VD1 using the VDC register and the VD1 voltage is fixed
at 2.2 V. The VD1 level does not change even if any data is written to the VDC register.
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Input port
(1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is
delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate waiting time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 330 kΩ
(2) The K13 terminal functions as the clock input terminal for the programmable timer, and the input
signal is shared with the input port and the programmable timer. Therefore, when the K13 terminal is
set to the clock input terminal for the programmable timer, take care of the interrupt setting.
Output port
(1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output).
Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R02 and R03 registers when the special output has been selected.
Be aware that the output terminal shifts into high impedance status when "1" is written to the high
impedance control register (R02HIZ, R03HIZ).
(2) A hazard may occur when the FOUT signal and the TOUT signal are turned ON and OFF.
(3) When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes.
I/O port
(1) When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 330 kΩ
(2) When special output (CL, FR) has been selected, a hazard may occur when the signal is turned ON or
OFF.
LCD driver
(1) When a program that access no memory mounted area (F078H–F0FFH, F178H–F1FFH, F201H, F203H,
· · ·, F277H) is made, the operation is not guaranteed.
(2) Because at initial reset, the contents of display memory and LC3–LC0 (LCD contrast) are undefined,
there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF
because these are set so that the display goes OFF.
Clock timer
(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–TM7).
(2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequencies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function.
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Stopwatch timer
(1) When data of the counter is read at run mode, perform the reading after suspending the counter once
and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976
µsec (1/4 cycle of 256 Hz).
(2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequencies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, this timer can not be used for the stopwatch function.
Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.
Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec
(when fOSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of
the input clock after writing to the PTRUN0/PTRUN1 register. Consequently, when "0" is written to the
PTRUN0/PTRUN1 register, the timer enters STOP status at the point where the counter is decremented
(-1). The PTRUN0/PTRUN1 register maintains "1" for reading until the timer actually stops.
Figure 5.2.1 shows the timing chart for the RUN/STOP control.
Input clock
PTRUN0/PTRUN1 (RD)
PTRUN0/PTRUN1 (WR)
PTD0X/PTD1X
"1" (RUN)
writing
42H
"0" (STOP)
writing
41H 40H 3FH 3EH
3DH
Fig. 5.2.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned ON and OFF by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
Serial interface
(1) Perform data writing/reading to the data registers SD0–SD7 only while the serial interface is halted
(i.e., the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be
performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial
interface with the ESIF register before the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from
performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous
clock SCLK is external clock, start to input the external clock after the trigger.
(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source of the programmable timer or in the slave mode.
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Sound generator
(1) Since it generates a BZ signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes ON/OFF due to the setting of the BZE register.
(2) The one-shot output is only valid when the normal buzzer output is OFF (BZE = "0") and will be
invalid when the normal buzzer output is ON (BZE = "1").
(3) The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and times
that are described in this section are the values in the case of crystal oscillation (32.768 kHz, Typ.),
they differ when CR oscillation (60 kHz, Typ.) is selected.
SVD circuit
(1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the
SVD detection result, follow the programming sequence below.
1.
2.
3.
4.
Set SVDON to "1"
Maintain for 100 µsec minimum
Set SVDON to "0"
Read SVDDT
(2) The SVD circuit should normally be turned OFF because SVD operation increase current consumption.
Interrupt
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is
set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one
is set.
S1C63466 TECHNICAL MANUAL
EPSON
107
CHAPTER 6: BASIC EXTERNAL WIRING DIAGRAM
CHAPTER
6 BASIC EXTERNAL WIRING DIAGRAM
• When negative polarity is selected for buzzer output (mask option selection)
SVD
CA
CB
CC
CD
CE
CF
TEST
VDD
C2
C3
+
CP
C4
C9
VD1
VREF
CGX
OSC1
RCR1
P00–P03
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P20
S1C63466
P21
P22 (CL)
[The potential of the substrate
P23 (FR)
(back of the chip) is VSS.]
C1
X'tal
Output
R00
R01
R02 (TOUT)
R03 (FOUT)
R10–R13
R20–R23
OSC2
*1
OSC3
CGC
CR
OSC4
CDC
*3
VSS
*2
CRES
∗1: Crystal oscillation
∗2: CR oscillation
∗3: Ceramic oscillation
C8
C7
C6
Piezo
C5
BZ
VC1
VC2
VC3
VC4
VC5
RESET
*2
(1.8 V)
2.2 V
|
6.4 V
RCR2
I/O
K00–K03
K10–K13
COM0
|
COM16
Input
SEG0
|
SEG59
LCD panel 60 × 17
Coil
X'tal
CGX
RCR1
CR
CGC
CDC
RCR2
C1–C8
C9
CP
CRES
Crystal oscillator
Trimmer capacitor
Resistor for OSC1 CR oscillation
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for OSC3 CR oscillation
Capacitor
Capacitor
Capacitor
RESET terminal capacitor
32.768 kHz, CI (Max.) = 34 kΩ
5–25 pF
600 kΩ (60 kHz)
4 MHz (3.0 V)
30 pF
30 pF
47 kΩ (1.8 MHz)
0.2 µF
0.1 µF
3.3 µF
0.1 µF
Note: The above table is simply
an example, and is not
guaranteed to work.
Note: • In order to prevent unstable operation of the OSC3 oscillation circuit due to current leak between OSC3
and VDD, please keep enough distance between VDD and other signals on the board pattern.
• In order to get a stable frequency for ceramic oscillation, please use maker's recommendatory value for
CGC and CDC.
• Precautions for Visible Radiation
Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this
IC to malfunction. When developing products which use this IC, consider the following precautions to
prevent malfunctions caused by visible radiations.
(1) Design the product and implement the IC on the board so that it is shielded from visible radiation in
actual use.
(2) The inspection process of the product needs an environment that shields the IC from visible radiation.
(3) As well as the face of the IC, shield the back and side too.
108
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
CHAPTER
7 ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Rating
(VSS=0V)
Item
Rated value
Unit
Symbol
Supply voltage
-0.5 to 7.0
V
VDD
Input voltage (1)
VI
-0.5 to VDD + 0.3
V
Input voltage (2)
VIOSC
-0.5 to VD1 + 0.3
V
Permissible total output current ∗1 ΣIVDD
10
mA
Operating temperature
Topr
-20 to 70
°C
Storage temperature
Tstg
-65 to 150
°C
Soldering temperature / time
Tsol
260°C, 10sec (lead section)
–
Permissible dissipation ∗2
PD
250
mW
∗1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the
output pin (or is drawn in).
∗2 In case of plastic package (QFP8-144pin, QFP17-144pin, QFP5-128pin).
7.2 Recommended Operating Conditions
Item
Supply voltage
Symbol
VSS=0V
VDD
Oscillation frequency
fOSC1
fOSC3
SVD terminal input voltage
S1C63466 TECHNICAL MANUAL
SVD
Condition
OSC3 oscillation OFF
OSC1 CR oscillation
OSC3 oscillation ON
Crystal oscillation
CR oscillation
CR oscillation
Ceramic oscillation
VSS=0V, SVD≤VDD
EPSON
Min.
1.8
2.2
2.2
–
40
0
(Ta=-20 to 70°C)
Typ.
Max. Unit
3.0
6.4
V
3.0
6.4
V
3.0
6.4
V
32.768
–
kHz
60
80
kHz
1,800
2,250 kHz
4,100 kHz
6.4
V
109
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.3 DC Characteristics
Unless otherwise specified:
VDD=3.0V, VSS=0V, fOSC1=32.768kHz, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF
Min.
Typ.
Condition
Item
Symbol
0.8·VDD
K00–03, K10–13
High level input voltage (1) VIH1
P00–03, P10–13, P20–23
RESET, TEST
0.9·VDD
High level input voltage (2) VIH2
VIL1
K00–03, K10–13
0
Low level input voltage (1)
P00–03, P10–13, P20–23
VIL2
RESET, TEST
0
Low level input voltage (2)
IIH
K00–03, K10–13
VIH=3.0V
0
High level input current
P00–03, P10–13, P20–23
RESET, TEST
IIL1
K00–03, K10–13
VIL1=VSS
-0.5
Low level input current (1)
No Pull-up
P00–03, P10–13, P20–23
RESET, TEST
IIL2
K00–03, K10–13
VIL2=VSS
-7
-12
Low level input current (2)
With Pull-up
P00–03, P10–13, P20–23
RESET, TEST
R00–03, R10–13, R20–23
VOH1=0.9·VDD
High level output current (1) IOH1
P00–03, P10–13, P20–23
BZ
VOH2=0.9·VDD
High level output current (2) IOH2
VOL1=0.1·VDD
R00–03, R10–13, R20–23
3
Low level output current (1) IOL1
P00–03, P10–13, P20–23
BZ
VOL2=0.1·VDD
3
Low level output current (2) IOL2
VOH3=VC5-0.05V COM0–16
IOH3
Common output current
IOL3
VOL3=VSS+0.05V
25
VOH4=VC5-0.05V SEG0–59
IOH4
Segment output current
IOL4
VOL4=VSS+0.05V
10
Unless otherwise specified:
VDD=5.0V, VSS=0V, fOSC1=32.768kHz, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF
Min.
Typ.
Condition
Item
Symbol
0.8·VDD
K00–03, K10–13
High level input voltage (1) VIH1
P00–03, P10–13, P20–23
RESET, TEST
0.9·VDD
High level input voltage (2) VIH2
VIL1
K00–03, K10–13
0
Low level input voltage (1)
P00–03, P10–13, P20–23
VIL2
RESET, TEST
0
Low level input voltage (2)
IIH
K00–03, K10–13
VIH=5.0V
0
High level input current
P00–03, P10–13, P20–23
RESET, TEST
IIL1
K00–03, K10–13
VIL1=VSS
-0.5
Low level input current (1)
No Pull-up
P00–03, P10–13, P20–23
RESET, TEST
IIL2
K00–03, K10–13
VIL2=VSS
-12
-20
Low level input current (2)
With Pull-up
P00–03, P10–13, P20–23
RESET, TEST
R00–03, R10–13, R20–23
VOH1=0.9·VDD
High level output current (1) IOH1
P00–03, P10–13, P20–23
BZ
VOH2=0.9·VDD
High level output current (2) IOH2
R00–03, R10–13, R20–23
VOL1=0.1·VDD
7.5
Low level output current (1) IOL1
P00–03, P10–13, P20–23
BZ
VOL2=0.1·VDD
7.5
Low level output current (2) IOL2
IOH3
VOH3=VC5-0.05V COM0–16
Common output current
VOL3=VSS+0.05V
IOL3
25
IOH4
VOH4=VC5-0.05V SEG0–59
Segment output current
IOL4
VOL4=VSS+0.05V
10
110
EPSON
Max.
VDD
Unit
V
VDD
0.2·VDD
V
V
0.1·VDD V
0.5
µA
0
µA
-5
µA
-2
mA
-2
mA
mA
-25
-10
mA
µA
µA
µA
µA
Max.
VDD
Unit
V
VDD
0.2·VDD
V
V
0.1·VDD V
0.5
µA
0
µA
-9
µA
-5
mA
-5
mA
mA
-25
-10
mA
µA
µA
µA
µA
S1C63466 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.4 Analog Circuit Characteristics and Power Current Consumption
Unless otherwise specified:
VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF
Condition
Item
Symbol
Min.
Typ.
Max. Unit
Connect 1 MΩ load resistor
LC0–3="0"
LCD drive voltage
VC1
0.975
V
(when VC1 standard is selected)
LC0–3="1"
between VSS and VC1
0.990
(without panel load)
LC0–3="2"
1.005
LC0–3="3"
1.020
LC0–3="4"
1.035
LC0–3="5"
1.050
LC0–3="6"
1.065
LC0–3="7"
Typ.
1.080
Typ.
LC0–3="8"
×0.88 1.095 ×1.12
LC0–3="9"
1.110
LC0–3="10"
1.125
LC0–3="11"
1.140
LC0–3="12"
1.155
LC0–3="13"
1.170
LC0–3="14"
1.185
LC0–3="15"
1.200
Connect 1 MΩ load resistor between VSS and VC2
VC2
2·VC1
2·VC1
V
(without panel load)
×0.9
VC4
Connect 1 MΩ load resistor between VSS and VC4
3·VC1
3·VC1
V
(without panel load)
×0.9
VC5
Connect 1 MΩ load resistor between VSS and VC5
4·VC1
4·VC1
V
(without panel load)
×0.9
LCD drive voltage
VC1
Connect 1 MΩ load resistor between VSS and VC1
1/2·VC2
1/2·VC2 V
(when VC2 standard is selected)
(without panel load)
×0.95
+0.1
VC2
Connect 1 MΩ load resistor
LC0–3="0"
1.95
V
between VSS and VC2
LC0–3="1"
1.98
(without panel load)
LC0–3="2"
2.01
LC0–3="3"
2.04
LC0–3="4"
2.07
LC0–3="5"
2.10
LC0–3="6"
2.13
LC0–3="7"
Typ.
Typ.
2.16
LC0–3="8"
×0.88
×1.12
2.19
LC0–3="9"
2.22
LC0–3="10"
2.25
LC0–3="11"
2.28
LC0–3="12"
2.31
LC0–3="13"
2.34
LC0–3="14"
2.37
LC0–3="15"
2.40
VC4
Connect 1 MΩ load resistor between VSS and VC4
3/2·VC2
3/2·VC2 V
(without panel load)
×0.95
VC5
Connect 1 MΩ load resistor between VSS and VC5
2·VC2
2·VC2
V
(without panel load)
×0.95
S1C63466 TECHNICAL MANUAL
EPSON
111
CHAPTER 7: ELECTRICAL CHARACTERISTICS
Unless otherwise specified:
VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, RCR1=600kΩ, RCR2=47kΩ, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage,
C1–C8=0.2µF
Item
Symbol
Min.
Typ.
Max. Unit
Condition
SVD voltage
VSVD1 SVDS0–3="0" (internal)
1.85
V
1.90
SVDS0–3="1"
2.00
SVDS0–3="2"
2.10
SVDS0–3="3"
2.20
SVDS0–3="4"
2.30
SVDS0–3="5"
2.40
SVDS0–3="6"
Typ.
2.50
Typ.
SVDS0–3="7"
×0.93
2.60
×1.07
SVDS0–3="8"
2.70
SVDS0–3="9"
2.80
SVDS0–3="10"
2.90
SVDS0–3="11"
3.00
SVDS0–3="12"
3.10
SVDS0–3="13"
3.20
SVDS0–3="14"
3.30
SVDS0–3="15"
VSVD2 SVDS0–3="0" (external)
SVD voltage (external) ∗4
0.95
1.05
1.15
V
tSVD
SVD circuit response time
100
µs
IOP
Current consumption
1
2
µA
During HALT (32 kHz crystal oscillation),
LCD power OFF
∗1, ∗2, ∗3
6
12
µA
During HALT (32 kHz crystal oscillation),
∗1, ∗2, ∗3
LCD power ON (VC1 standard)
During HALT (32 kHz crystal oscillation),
4
8
µA
LCD power ON (VC2 standard)
∗1, ∗2, ∗3
During HALT (60 kHz CR oscillation),
23
45
µA
LCD power OFF
∗1, ∗3
During HALT (60 kHz CR oscillation),
30
60
µA
LCD power ON (VC1 standard)
∗1, ∗3
During HALT (60 kHz CR oscillation),
26
50
µA
LCD power ON (VC2 standard)
∗1, ∗3
During execution (32 kHz crystal oscillation),
10
19
µA
LCD power ON (VC1 standard)
∗1, ∗2, ∗3
During execution (60 kHz CR oscillation),
45
80
µA
LCD power ON (VC1 standard)
∗1, ∗3
During execution (2 MHz ceramic oscillation),
600
800
µA
LCD power ON (VC1 standard)
∗1
During execution (4 MHz ceramic oscillation),
1,200 1,400 µA
LCD power ON (VC1 standard)
∗1
During execution (1,800 kHz CR oscillation),
800
1,000 µA
LCD power ON (VC1 standard)
∗1
SVD circuit current (during supply voltage detection)
1
7
µA
VDD=1.85 to 6.4 V
SVD circuit current (during external voltage detection) 0.5
3
µA
VDD=1.85 to 6.4 V
∗1 Without panel load. The SVD circuit is OFF.
∗2 VDC = "0"
∗3 OSCC = "0"
∗4 Please input the voltage, which is within the range between VSS and VDD, into the SVD terminal.
112
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.5 Oscillation Characteristics
The oscillation characteristics change depending on the conditions (components used, board pattern,
etc.). Use the following characteristics as reference values.
OSC1 crystal oscillation circuit
Unless otherwise specified:
VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, CD=built-in, Ta=-20 to 70°C
Item
Symbol
Condition
tsta≤3sec (VDD)
Oscillation start voltage
Vsta
Oscillation stop voltage
Vstp
tstp≤10sec (VDD)
Built-in capacitance (drain)
CD
Including the parasitic capacitance inside the IC (in chip)
without VDC switching
Frequency/voltage deviation ∂f/∂V VDD=2.2 to 6.4V
with VDC switching
∂f/∂IC
Frequency/IC deviation
Frequency adjustment range ∂f/∂CG CG=5 to 25pF
CG=5pF (VDD)
Harmonic oscillation start voltage Vhho
Permitted leak resistance
Rleak
Between OSC1 and VSS
Min.
1.8
1.8
Typ.
Max.
14
-10
10
6.4
200
5
10
10
20
Unit
V
V
pF
ppm
ppm
ppm
ppm
V
MΩ
OSC1 CR oscillation circuit
Unless otherwise specified:
VDD=3.0V, VSS=0V, RCR1=600kΩ, Ta=-20 to 70°C
Item
Symbol
Oscillation frequency dispersion fOSC1
Oscillation start voltage
Vsta
(VDD)
Oscillation start time
tsta
VDD=2.2 to 6.4V
Oscillation stop voltage
Vstp
(VDD)
Condition
Min.
-30
2.2
Typ.
60kHz
Max.
30
3
2.2
Unit
%
V
ms
V
OSC3 ceramic oscillation circuit
Unless otherwise specified:
VDD=3.0V, VSS=0V, Ceramic oscillator: 4MHz, CGC=CDC=30pF, Ta=-20 to 70°C
Item
Symbol
Condition
Oscillation start voltage
Vsta
(VDD)
Oscillation start time
tsta
VDD=2.2 to 6.4V
Oscillation stop voltage
Vstp
(VDD)
Min.
2.2
Typ.
Max.
5
2.2
Unit
V
ms
V
OSC3 CR oscillation circuit
Unless otherwise specified:
VDD=3.0V, VSS=0V, RCR2=47kΩ, Ta=-20 to 70°C
Item
Symbol
Oscillation frequency dispersion fOSC3
(VDD)
Oscillation start voltage
Vsta
Oscillation start time
VDD=2.2 to 6.4V
tsta
Oscillation stop voltage
Vstp
(VDD)
S1C63466 TECHNICAL MANUAL
Condition
Min.
-25
2.2
Typ.
Max.
1,800kHz 25
3
2.2
EPSON
Unit
%
V
ms
V
113
CHAPTER 7: ELECTRICAL CHARACTERISTICS
OSC1 CR oscillation frequency-resistance characteristic
The oscillation characteristics change depending on the conditions (components used, board pattern,
etc.). Use the following characteristics as reference values and evaluate the characteristics on the actual
product.
120k
VDD = 2.2 to 6.4 V
VSS = 0 V
Ta = 25°C
Typ. value
CR oscillation frequency fOSC1 [Hz]
110k
100k
90k
80k
70k
60k
50k
40k
30k
20k
300k
400k
500k
600k
700k
800k
900k
1M
Resistor value for CR oscillation RCR1 [Ω]
OSC3 CR oscillation frequency-resistance characteristic
The oscillation characteristics change depending on the conditions (components used, board pattern,
etc.). Use the following characteristics as reference values and evaluate the characteristics on the actual
product.
2.2M
VDD = 2.2 to 6.4 V
VSS = 0 V
Ta = 25°C
Typ. value
CR oscillation frequency fOSC3 [Hz]
2.1M
2.0M
1.9M
1.8M
1.7M
1.6M
1.5M
1.4M
1.3M
1.2M
1.1M
30k
40k
50k
60k
70k
80k
90k
100k
110k
120k
Resistor value for CR oscillation RCR2 [Ω]
114
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.6 Serial Interface AC Characteristics
Clock synchronous master mode
• During 32 kHz operation
Condition: VDD=3.0V, VSS=0V, Ta=25°C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD
Min.
Typ.
Item
Symbol
tsmd
Transmitting data output delay time
10
tsms
Receiving data input set-up time
tsmh
5
Receiving data input hold time
Max.
5
Unit
µs
µs
µs
Max.
200
Unit
ns
ns
ns
Max.
10
Unit
µs
µs
µs
Max.
500
Unit
ns
ns
ns
• During 1 MHz operation
Condition: VDD=3.0V, VSS=0V, Ta=25°C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD
Item
Symbol
Min.
Typ.
Transmitting data output delay time
tsmd
Receiving data input set-up time
400
tsms
Receiving data input hold time
tsmh
200
Note that the maximum clock frequency is limited to 1 MHz.
Clock synchronous slave mode
• During 32 kHz operation
Condition: VDD=3.0V, VSS=0V, Ta=25°C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD
Item
Symbol
Min.
Typ.
Transmitting data output delay time
tssd
tsss
Receiving data input set-up time
10
Receiving data input hold time
tssh
5
• During 1 MHz operation
Condition: VDD=3.0V, VSS=0V, Ta=25°C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD
Min.
Typ.
Item
Symbol
tssd
Transmitting data output delay time
400
tsss
Receiving data input set-up time
tssh
200
Receiving data input hold time
Note that the maximum clock frequency is limited to 1 MHz.
<Master mode>
SCLK OUT
SOUT
VOH
VOL
tsmd
VOH
VOL
tsms
tsmh
VIH1
VIL1
SIN
<Slave mode>
SCLK IN
SOUT
VIH1
VIL1
tssd
VOH
VOL
tsss
SIN
S1C63466 TECHNICAL MANUAL
tssh
VIH1
VIL1
EPSON
115
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.7 Timing Chart
System clock switching
∗ 1 instruction execution time or longer
∗
VDC
2.5 msec min.
∗
OSCC
5 msec min.
CLKCHG
Note: When the OSC1 oscillation circuit has been selected as the CR oscillation circuit, it is not necessary to set the VDC register. Whether the VDC register value is "1" or "0" does not matter.
116
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 8: PACKAGE
CHAPTER
8 PACKAGE
8.1 Plastic Package
QFP8-144pin
(Unit: mm)
31.2±0.4
28±0.1
108
73
31.2±0.4
72
28±0.1
109
INDEX
37
3.35±0.1
1
36
0.65
0.3±0.1
0.15±0.05
0°
10°
0.6±0.2
0.1
3.65max
144
1.6
The dimensions are subject to change without notice.
S1C63466 TECHNICAL MANUAL
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117
CHAPTER 8: PACKAGE
QFP17-144pin
(Unit: mm)
22±0.4
20±0.1
108
73
20±0.1
22±0.4
72
109
INDEX
37
144
0.5
3max
2.7±0.1
1
+0.1
36
0.2–0.05
0.1
0.15±0.05
0°
10°
0.5±0.2
1
The dimensions are subject to change without notice.
118
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 8: PACKAGE
QFP5-128pin
(Unit: mm)
23.6±0.4
20±0.1
102
65
14±0.1
INDEX
39
128
1
38
0.2±0.05
0.1 2.7±0.1
0.5
3max
17.6±0.4
64
103
0.15±0.05
0°
10°
0.8±0.2
1.8
The dimensions are subject to change without notice.
S1C63466 TECHNICAL MANUAL
EPSON
119
CHAPTER 8: PACKAGE
8.2 Ceramic Package for Test Samples
QFP8-144pin
(Unit: mm)
36.93±0.30
28.00±0.28
73
72
144
37
28.00±0.28
109
1
36
0.30±0.05
0.15
0.20 Typ.
3.05 Max.
0.65±0.05
120
36.93±0.30
108
1.20 Typ.
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 8: PACKAGE
QFP17-144pin
(Unit: mm)
22.00±0.25
19.20±0.19
73
72
144
37
19.20±0.19
109
1
22.00±0.25
108
36
0.20
0.15
2.80 Max
0.50
0.50±0.20
S1C63466 TECHNICAL MANUAL
EPSON
121
CHAPTER 8: PACKAGE
QFP5-128pin
(Unit: mm)
23.90 ±0.30
20.00 ±0.18
102
65
64
128
39
14.00 ±0.14
17.91 ±0.30
103
1
38
0.2
0.40 ±0.08
CERAMIC
0.15
0.95 ±0.08
0.76 ±0.08
2.79 MAX
0.5
122
0.20 TYP
GLASS
EPSON
0.80 ±0.20
S1C63466 TECHNICAL MANUAL
CHAPTER 9: PAD LAYOUT
CHAPTER
9 PAD LAYOUT
9.1 Diagram of Pad Layout
35
30
25
20
15
10
5
1
140
Die No.
40
135
45
130
125
55
X
(0, 0)
120
5.14 mm
Y
50
60
115
65
110
70
75
80
85
90
95
100
105
5.44 mm
Chip thickness: 400 µm
Pad opening:
100 µm
S1C63466 TECHNICAL MANUAL
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123
CHAPTER 9: PAD LAYOUT
9.2 Pad Coordinates
Unit: µm
No. Pad name
X
Y
No. Pad name
X
Y
No. Pad name
X
Y
No. Pad name
X
Y
1
2
N.C.
N.C.
2218
2058
2445
2445
36
37
N.C.
N.C.
-2440
-2595
2445
2293
71
72
N.C.
N.C.
-2595
-2595
-2256
-2416
106
107
SEG14
SEG13
2145
2595
-2445
-2011
3
4
R23
R22
1903
1773
2445
2445
38
39
SVD
VC1
-2595
-2595
2163
2033
73
74
SEG47
SEG46
-2144
-2014
-2445
-2445
108
109
SEG12
SEG11
2595
-1881
5
6
R21
R20
1643
1513
2445
2445
40
41
VC2
-2595
-2595
1903
1773
75
76
SEG45
SEG44
-1884
-1754
-2445
-2445
110
111
SEG10
SEG9
2595
2595
-1751
-1621
7
8
R13
R12
1383
1253
2445
2445
42
43
VC4
1643
1513
77
78
SEG43
SEG42
-1624
-1494
-2445
-2445
112
113
SEG8
SEG7
2595
2595
-1491
-1361
VC5
-2595
-2595
9
10
R11
R10
1123
993
2445
2445
44
45
CF
-2595
1383
79
SEG41
-1364
-2445
114
SEG6
2595
2595
-1231
-1101
11
12
13
14
15
16
17
R03
R02
R01
R00
P23
P22
P21
863
733
603
473
321
191
61
2445
2445
2445
2445
2445
2445
2445
46
47
48
49
50
51
52
CE
CD
CC
CB
CA
COM8
-2595
-2595
-2595
-2595
-2595
-2595
1253
1123
993
863
733
603
80
81
82
83
84
85
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
-1234
-1104
-974
-844
-714
-584
-2445
-2445
-2445
-2445
-2445
-2445
115
116
117
118
119
120
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
2595
2595
-971
-841
COM9
COM10
-2595
-2595
473
343
86
87
SEG34
SEG33
-454
-324
-2445
-2445
121
122
COM7
COM6
18
19
P20
P13
-68
-198
2445
2445
53
54
P12
P11
-328
-458
2445
2445
55
56
-588
-718
-848
-978
-1108
-1241
-1371
-1501
-1631
-1761
-1891
2445
2445
2445
2445
2445
2445
2445
2445
2445
2445
2445
57
58
59
60
61
62
63
64
65
66
67
88
89
90
91
92
93
94
95
96
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
-194
-64
65
195
325
455
585
715
845
-2445
-2445
-2445
-2445
-2445
-2445
-2445
-2445
-2445
123
124
125
126
127
128
129
130
131
COM5
COM4
COM3
COM2
COM1
COM0
BZ
VSS
201
331
P10
P03
P02
P01
P00
K13
K12
K11
K10
K03
K02
213
83
-46
-176
-306
-436
-581
-711
-841
2595
2595
22
23
24
25
26
27
28
29
30
31
32
-2595
-2595
-2595
-2595
-2595
-2595
-2595
-2595
-2595
-711
-581
-451
-321
-188
-58
71
20
21
COM11
COM12
COM13
COM14
COM15
COM16
SEG59
SEG58
SEG57
2595
2595
2595
2595
2595
2595
2595
2595
2595
461
591
SEG56
SEG55
-2595
-2595
-971
-1101
97
98
SEG23
SEG22
975
1105
-2445
-2445
132
133
SEG54
SEG53
-2595
-2595
-1231
-1361
99
100
SEG21
SEG20
1235
1365
-2445
-2445
134
135
33
34
35
K01
K00
N.C.
-2021
-2151
-2281
2445
2445
2445
68
69
70
SEG52
SEG51
SEG50
SEG49
SEG48
-2595
-2595
-2595
-2595
-2595
-1491
-1621
-1751
-1881
-2011
101
102
103
104
105
SEG19
SEG18
SEG17
SEG16
SEG15
1495
1625
1755
1885
2015
-2445
-2445
-2445
-2445
-2445
136
137
138
139
140
2595
2595
2595
2595
2595
2595
2595
2595
2595
2595
2595
721
865
995
1125
1255
1385
1515
1645
1775
2032
2162
2595
2595
2292
2442
VC3
OSC1
OSC2
VD1
OSC3
OSC4
VDD
RESET
TEST
VREF
N.C.
N.C. : No Connection
124
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S1C63466 TECHNICAL MANUAL
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
APPENDIX
S5U1C63000P MANUAL
(PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
This manual describes how to use the Peripheral Circuit Board for the S1C63404/454/455/458/466/P466
(S5U1C63000P), which provides emulation functions when mounted on the debugging tool for the S1C63
Family of 4-bit single-chip microcomputers, the ICE (S5U1C63000H1/S5U1C63000H2).
This description of the S1C63 Family Peripheral Circuit Board (S5U1C63000P) provided in this document
assumes that circuit data for the S1C63404/454/455/458/466/P466 has already been downloaded to the
board. For information on downloading various circuit data and on common board specifications, please
see the S5U1C63000P Manual (S1C63 Family Peripheral Circuit Board) included with the product. Please
refer to the user’s manual provided with your ICE for detailed information on its functions and method
of use.
A.1 Names and Functions of Each Part
The following explains the names and functions of each part of the board (S5U1C63000P).
(9)
(8)
(11)
IOSEL2
(10)
CLK
VC5
(2)
(1)
VLCD VSVD
D E
1 3
(7)
XC4062XLA
RESET
(3)
PRG
(6)
(10)
(4)
(5)
CN3 connector (Unused)
CN2 connector (Unused)
CN1 connector
(1) VLCD
Unused.
(2) VSVD
This control allows you to vary the power supply voltage artificially in order to verify the operation of
the power supply voltage detect function (SVD). Keep in mind that a single control position indicates
two voltage values.
SVD levels
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
(For example, SVD levels 0 and 8 are at the same control position.)
(3) Register monitor LEDs
These LEDs correspond one-to-one to the registers listed below. The LED lights when the data is logic
"1" and goes out when the data is logic "0".
VDC, OSCC, CLKCHG, SVDS0–3∗, SVDON∗, LPWR, VCCHG
∗ SVDS0–3, SVDON: Used for the S1C63404/458/466/P466
S1C63466 TECHNICAL MANUAL
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125
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
(4) Register monitor pins
These pins correspond one-to-one to the registers listed below. The pin outputs a high for logic "1"
and a low for logic "0".
Monitor
LED
Pin No.
Name
LED No.
Name
2
1
1
DONE *1
1
DONE *1
2
4
2
–
2
–
3
3
VDC
3
VDC
4
6
5
4
OSCC
4
OSCC
6
5
CLKCHG
5
CLKCHG
8
7
6
–
6
–
8
10
7
–
7
–
9
8
–
8
–
10
12
11
9
–
9
–
12
14
10
SVDS0 *2
10
SVDS0 *2
13
*2
*2
11
SVDS1
11
SVDS1
14
16
12
SVDS2 *2
12
SVDS2 *2
15
13
SVDS3 *2
13
SVDS3 *2
16
*2
14
SVDON
14
SVDON *2
15
LPWR
15
LPWR
Monitor pin
16
VCCHG
16
VCCHG
∗1 DONE: The monitor pin outputs a high while the LED lights when
initialization of this board completes without problems.
∗2 SVDS0–3, SVDON:
Used for the S1C404/458/466/P466.
1
3
5
7
9
11
13
15
LED
(5) CR oscillation frequency adjusting control
When OSC1 and OSC3 respectively are set for a CR oscillation circuit and a CR/ceramic oscillation
circuit by a mask option, this control allows you to adjust the oscillation frequency. The oscillation
frequency can be adjusted in the range of approx. 20 kHz to 500 kHz for OSC1 and approx. 100 kHz to
8 MHz for OSC3. Note that the actual IC does not operate with all of these frequencies; consult the
technical manual for the S1C63404/454/455/458/466/P466 to select the appropriate operating
frequency.
OSC1 rough adjustment
OSC1 fine adjustment
OSC3 rough adjustment
OSC3 fine adjustment
(6) CR oscillation frequency monitor pins
These pins allow you to monitor the clock waveform from the CR oscillation circuit with an oscilloscope. Note that these pins always output a signal waveform whether or not the oscillation circuit is
operating.
RESET
OSC3 monitor pin (red)
OSC1 monitor pin (red)
GND pin (black)
126
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S1C63466 TECHNICAL MANUAL
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
(7) RESET switch
This switch initializes the internal circuits of this board and feeds a reset signal to the ICE.
(8) Monitor pins and external part connecting socket
These parts are currently unused.
(9) IOSEL2
When downloading circuit data, set IOSEL2 to the "E" position. Otherwise, set to the "D" position.
(10) CLK and PRG switch
If power to the ICE is shut down before circuit data downloading is complete, the circuit configuration in this board will remain incomplete, and the debugger may not be able to start when you power
on the ICE once again. In this case, temporarily power off the ICE and set CLK to the 32K position and
the PRG switch to the Prog position, then switch on power for the ICE once again. This should allow
the debugger to start up, allowing you to download circuit data. After downloading the circuit data,
temporarily power off the ICE and reset CLK and PRG to the LCLK and the Norm position, respectively. Then power on the ICE once again.
(11) VC5
This control allows fine adjustment of the LCD drive voltage when the internal LCD power supply is
selected by mask option. Note, however, that only the LCD contrast register can adjust the LCD drive
voltage in the actual IC.
S1C63466 TECHNICAL MANUAL
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127
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
A.2 Connecting to the Target System
This section explains how to connect the S5U1C63000P to the target system.
To connect this board (S5U1C63000P) to the target system, use the I/O connecting cables supplied with
the board (80-pin/40-pin × 2, flat type). Take care when handling the connectors, since they conduct
electrical power (VDD = +3.3 V).
mark
I/O connection cable
CN1-1
(40-pin)
CN1-2
(40-pin)
To target board
Fig. A.2.1 Connecting the S5U1C63000P to the target system
128
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S1C63466 TECHNICAL MANUAL
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
Table A.2.1 I/O connector pin assignment
40-pin CN1-1 connector
40-pin CN1-2 connector
No.
Pin name
No.
Pin name
1
VDD (=3.3 V)
1
VDD (=3.3 V)
2
VDD (=3.3 V)
2
VDD (=3.3 V)
3
K00
3
R00
4
K01
4
R01
5
K02
5
R02
6
K03
6
R03
7
K10 *1
7
R10 *1
8
K11 *1
8
R11 *1
9
K12 *1
9
R12 *1
10
K13 *1
10
R13 *1
11
VSS
11
VSS
12
12
VSS
VSS
13
13
P00
R20 *1
14
14
P01
R21 *1
15
15
P02
R22 *1
16
16
P03
R23 *1
17
17
P10
Cannot be connected
18
18
P11
Cannot be connected
19
19
P12
Cannot be connected
20
20
P13
Cannot be connected
21
21
VDD (=3.3 V)
VDD (=3.3 V)
22
22
VDD (=3.3 V)
VDD (=3.3 V)
23
23
P20 *1
Cannot be connected
24
24
P21 *1
Cannot be connected
25
25
P22 *1
Cannot be connected
26
26
P23 *1
Cannot be connected
27
27
Cannot be connected
Cannot be connected
28
28
Cannot be connected
Cannot be connected
29
29
Cannot be connected
Cannot be connected
30
30
Cannot be connected
Cannot be connected
31
31
VSS
VSS
32
32
VSS
VSS
33
Cannot be connected
33
VC1 *2
34
Cannot be connected
34
VC2 *2
35
Cannot be connected
35
VC3 *2
36
Cannot be connected
36
VC4 *2
37
Cannot be connected
37
VC5 *2
38
BZ
38
RESET
39
VSS
39
VSS
40
VSS
40
VSS
∗1: Can be used only for the S1C63404/458/466/P466
∗2: Can be used only for the S1C63404/454/458/466/P466
S1C63466 TECHNICAL MANUAL
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129
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
A.3 Usage Precautions
To ensure correct use of this board (S5U1C63000P), please observe the following precautions.
A.3.1 Operational precautions
(1) Before inserting or removing cables, turn off power to all pieces of connected equipment.
(2) Do not turn on power or load mask option data if all of the input ports (K00–K03) are held low. Doing
so may activate the multiple key entry reset function.
(3) Before debugging, always be sure to load mask option data.
A.3.2 Differences with the actual IC
(1) Differences in I/O
<Interface power supply>
This board and target system interface voltage is set to +3.3 V. To obtain the same interface voltage as
in the actual IC, attach a level shifter circuit, etc. on the target system side to accommodate the
required interface voltage.
<Each output port’s drive capability>
The drive capability of each output port on this board is higher than that of the actual IC. When
designing application system and software, refer to the technical manual for the S1C63404/454/455/
458/466/P466 to confirm each output port’s drive capability.
<Each port’s protective diode>
All I/O ports incorporate a protective diode for VDD and VSS, and the interface signals between this
board and the target system are set to +3.3 V. Therefore, this board and the target system cannot be
interfaced with voltages exceeding VDD by setting the output ports for open-drain mode.
<Pull-up resistance value>
The pull-up resistance values on this board are set to 220 kΩ which differ from those for the actual IC.
For the resistance values on the actual IC, refer to the technical manual for the S1C63404/454/455/
458/466/P466.
Note that when using pull-up resistors to pull the input pins high, the input pins may require a
certain period to reach a valid high level. Exercise caution if a key matrix circuit is configured using a
combination of output and input ports, since rise delay times on these input ports differ from those of
the actual IC.
(2) Differences in current consumption
The amount of current consumed by this board differs significantly from that of the actual IC. Inspecting the LEDs on this board may help you keep track of approximate current consumption. The
following factors/components greatly affect device current consumption:
<Those which can be verified by LEDs and monitor pins>
a) Run and Halt execution ratio (verified by LEDs and monitor pins on the ICE)
b) CPU operating voltage select circuit (VDC)
c) OSC3 oscillation on/off circuit (OSCC)
d) CPU clock change circuit (CLKCHG)
e) SVD circuit on/off circuit (SVDON) ∗ Available only for the S1C63404/458/466/P466.
f) LCD power supply on/off circuit (LPWR)
g) LCD constant-voltage change circuit (VCCHG)
<Those that can only be counteracted by system or software>
h) Current consumed by the internal pull-up resistors
i) Input ports in a floating state
130
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S1C63466 TECHNICAL MANUAL
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
(3) Functional precautions
<LCD power supply circuit>
- There is a finite delay time from the point at which the LCD power supply circuit (LPWR) turns on
until an LCD drive waveform is output. On this board, this delay is set to approx. 125 msec, which
differs from that of the actual IC. Refer to the technical manual for the S1C63404/454/455/458/466/
P466.
- When the LCD driver is turned OFF in external power supply mode using the LPWR register, the
SEG and COM terminals go to the VSS level. In this board with the LCD board, the SEG terminals go
to the VSS level and the COM terminals go to the VC1 level.
<Oscillation circuit>
- A wait time is required before oscillation stabilizes after the OSC3 oscillation control circuit (OSCC)
is turned on. On this board, even when OSC3 oscillation is changed (CLKCHG) without a wait time,
OSC3 will function normally. Refer to the technical manual for the S1C63404/454/455/458/466/
P466 when setting the appropriate wait time for the actual IC.
- Use separate instructions to switch the clock from OSC3 to OSC1 and to turn off the OSC3 oscillation
circuit. If executed simultaneously with a single instruction, these operations, although good with
this board, may not function properly well with the actual IC.
- Because the logic level of the oscillation circuit is high, the timing at which the oscillation starts on
this board differs from that of the actual IC.
- This board contains oscillation circuits for OSC1 and OSC3. Keep in mind that even though the
actual IC may not have a resonator connected to its OSC3, its emulator can operate with the OSC3
circuit.
- Do not turn on the OSC3 oscillation circuit when the voltage-regulating circuit for high-speed
operation remains idle.
<Access to undefined address space>
If any undefined space in the S1C63404/454/455/458/466/P466's internal ROM/RAM or I/O is
accessed for data read or write operations, the read/written value is indeterminate. Additionally, it is
important to remain aware that indeterminate state differs between this board and the actual IC. Note
that the ICE (S5U1C63000H1/S5U1C63000H2) incorporates the program break function caused by
accessing to an undefined address space.
<Reset circuit>
Keep in mind that the operation sequence from when the ICE and this board are powered on until the
time at which the program starts running differs from the sequence from when the actual IC is
powered on till the program starts running. This is because this board becomes capable of operating
as a debugging system after the user program and optional data are downloaded. When operating the
ICE after placing it in free-running mode, always apply a system reset. A system reset can be performed by pressing the reset switch on this board, by a reset pin input, or by holding the input ports
low simultaneously.
<Internal power supply circuit>
- Although this board contains VDC register, it does not actually exercise power supply control by this
register. Be sure to refer to the technical manual for the S1C63404/454/455/458/466/P466 when
setting the correct voltage. Also, when switching the control voltages, consult the technical manual
to determine the appropriate wait time to be inserted.
- Note that the LCD drive voltage on this board may not be identical to that on the actual IC.
- Since the usable operating frequency range depends on the device's internal operating voltage,
consult the technical manual for the S1C63404/454/455/458/466/P466 to ensure that the device will
not be operated with an inappropriate combination of the operating frequency and the internal
power supply.
S1C63466 TECHNICAL MANUAL
EPSON
131
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)
<SVD circuit>∗1
When this tool is used for the S1C63404/458/466/P466:
- Although the S1C63404/458/466/P466 has a function for detecting externally sourced voltages, this
board is unable to detect externally sourced voltages. The SVD function is realized by artificially
varying the power supply voltage using the VSVD control on this board.
- There is a finite delay time from when the power to the SVD circuit turns on until actual detection of
the voltage. On this board, this delay is set to 61–92 µsec, which differs from that of the actual IC.
Refer to the technical manual for the S1C63404/458/466/P466 when setting the appropriate wait
time for the actual IC.
<I/O port input circuit>∗2
When this tool is used for the S1C63454/455:
This board does not support Schmitt trigger input for the I/O port that is available by mask option
in the actual IC. If the target system needs Schmitt trigger input ports, it should be configured with
an external circuit.
<LCD drive circuit>∗3
When this tool is used for the S1C63455:
- Be sure to set the LDUTY0 and LDUTY1 bits (FF60H•D2, D3) as LDUTY0 = 0 and LDUTY1 = 1 or
LDUTY0 = 1 and LDUTY1 = 1, and maintain this status during debugging. This board is configured
as a 1/17 duty LCD driver after an initial reset.
- Do not change the value of the LPAGE bit (FF61H•D0) initialized to 0 as rewriting cause a malfunction.
∗1: Applied when this board is used for the S1C63404/458/466/P466
∗2: Applied when this board is used for the S1C63454/455
∗3: Applied when this board is used for the S1C63455
132
EPSON
S1C63466 TECHNICAL MANUAL
International Sales Operations
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
EPSON (CHINA) CO., LTD.
- HEADQUARTERS -
23F, Beijing Silver Tower 2# North RD DongSanHuan
ChaoYang District, Beijing, CHINA
Phone: 64106655
Fax: 64107319
150 River Oaks Parkway
San Jose, CA 95134, U.S.A.
Phone: +1-408-922-0200
Fax: +1-408-922-0238
SHANGHAI BRANCH
4F, Bldg., 27, No. 69, Gui Jing Road
Caohejing, Shanghai, CHINA
Phone: 21-6485-5552
Fax: 21-6485-0775
- SALES OFFICES West
1960 E. Grand Avenue
EI Segundo, CA 90245, U.S.A.
Phone: +1-310-955-5300
Fax: +1-310-955-5400
Central
101 Virginia Street, Suite 290
Crystal Lake, IL 60014, U.S.A.
Phone: +1-815-455-7630
Fax: +1-815-455-7633
Northeast
301 Edgewater Place, Suite 120
Wakefield, MA 01880, U.S.A.
Phone: +1-781-246-3600
Fax: +1-781-246-5443
EPSON HONG KONG LTD.
20/F., Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
Phone: +852-2585-4600 Fax: +852-2827-4346
Telex: 65542 EPSCO HX
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
10F, No. 287, Nanking East Road, Sec. 3
Taipei
Phone: 02-2717-7360
Fax: 02-2712-9164
Telex: 24444 EPSONTB
HSINCHU OFFICE
Southeast
3010 Royal Blvd. South, Suite 170
Alpharetta, GA 30005, U.S.A.
Phone: +1-877-EEA-0020 Fax: +1-770-777-2637
13F-3, No. 295, Kuang-Fu Road, Sec. 2
HsinChu 300
Phone: 03-573-9900
Fax: 03-573-9169
EPSON SINGAPORE PTE., LTD.
No. 1 Temasek Avenue, #36-00
Millenia Tower, SINGAPORE 039192
Phone: +65-337-7911
Fax: +65-334-2716
EUROPE
EPSON EUROPE ELECTRONICS GmbH
SEIKO EPSON CORPORATION KOREA OFFICE
- HEADQUARTERS Riesstrasse 15
80992 Munich, GERMANY
Phone: +49-(0)89-14005-0
Fax: +49-(0)89-14005-110
SALES OFFICE
Altstadtstrasse 176
51379 Leverkusen, GERMANY
Phone: +49-(0)2171-5045-0
Fax: +49-(0)2171-5045-10
UK BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
Bracknell, Berkshire RG12 8PE, ENGLAND
Phone: +44-(0)1344-381700
Fax: +44-(0)1344-381701
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: 02-784-6027
Fax: 02-767-3677
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
Electronic Device Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5816
Fax: +81-(0)42-587-5624
ED International Marketing Department Europe & U.S.A.
FRENCH BRANCH OFFICE
1 Avenue de l' Atlantique, LP 915 Les Conquerants
Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE
Phone: +33-(0)1-64862350
Fax: +33-(0)1-64862355
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Testa, Avda. Alcalde Barrils num. 64-68
E-08190 Sant Cugat del Vallès, SPAIN
Phone: +34-93-544-2490
Fax: +34-93-544-2491
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5812
Fax: +81-(0)42-587-5564
ED International Marketing Department Asia
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814
Fax: +81-(0)42-587-5110
S1C63466
Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epsondevice.com
First issue July, 1998
Printed October, 2001 in Japan
M
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