datasheet for PUMA68E4001A by Apta Group

datasheet for PUMA68E4001A by Apta Group
128K x 32 EEPROM Module
PUMA 68E4001/A-12/15/20
Issue 4.3 : May 2001
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Description
The PUMA 68E4001/A is a 4Mbit CMOS
EEPROM module in a JEDEC 68 pin surface
mount PLCC. The plastic device is screened to
ensure high reliability. Access times of 120, 150
and 200ns are available.The output width is user
configurable as 8, 16, or 32 bits wide using CS1-4
and is available in two pinout options, single WE
or WE1-4 (version /A) . Page write (128 bytes) is
performed in 5 ms (typical). The device also
features both hardware and software data protection with DATA polling and Toggle bit indication of
end of write . Write cycle endurance is 10,000
Erase/Write cycles with a data retention time of 10
years.
4,194,304 bit CMOS EEPROM Module
Features
· Access Times of 120/150/200 ns.
· User Configurable as 8 / 16 / 32 bit wide output.
· Commercial, Industrial, or Military grades.
· Operating Power
490 / 913 / 1760 mW (max).
· JEDEC 68 pin surface mount PLCC, available in two
pinouts : Single WE, WE1~4 is version A.
· High reliability plastic design
· Hardware and Software Data Protection.
· Endurance of 104 Erase/Write Cycles and Data
Retention Time of 10 years.
Pin Definition
(see page 11 for Block Diagram of option /A)
(see page 11 for option /A Pinout)
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
VCC
Block Diagram
A0~A16
OE
WE
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
VIEW
18
52
19
51
FROM
20
50
ABOVE
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68E4001
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
NC
NC
NC
NC
NC
GND
NC
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
Pin Functions
A0~16 Address Inputs
CS1~4 Chip Select
WE Write Enable (WE1~4 on version A)
VCC Power (+5V)
D0~31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
ISSUE 4.3 : May 2001
PUMA 68E4001/A-12/15/17/20
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Operating Temperature
Storage Temperature
Input voltages (including N.C. pins) with Respect to GND
Output voltages with respect to GND
TOPR
TSTG
VIN
VOUT
°
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to VCC+0.6
C
C
V
V
°
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
VCC
VIL
VIH
TA
TAI
TAM
min
typ
max
4.5
-1.0
2.0
0
-40
-55
5.0
-
5.5
0.8
VCC+1
70
85
125
V
V
V
°
C
°
C (I Suffix)
°
C (M Suffix)
DC Electrical Characteristics (TA=-55°C to +125°C,VCC=5V ± 10%)
Parameter
Symbol
Test Condition
min
Input Leakage Current
Output Leakage Current
ILI1
32 bit ILO
VIN = GND to VCC +1
Operating Supply Current
32 bit ICC32
16 bit ICC16
8 bit ICC8
CS(1)=OE=VIL, WE=VIH, IOUT=0mA, ƒ=5MHz(2)
max
Unit
-
40
40
µA
µA
-
320
166
89
mA
mA
mA
-
12
1.2
mA
mA
2.4
0.45
-
(1)
VI/O = GND to VCC, CS =VIH
As above
As above
Standby Supply Current TTL levels ISB1
CMOS levels ISB2
CS(1) = 2.0V to VCC+1V
Output Low Voltage
Output High Voltage
IOL = 2.1mA.
(1)
CS = VCC-0.3V to VCC+1V
VOL
VOH
IOH = -400µA.
V
V
Notes (1) CS above are accessed through CS1-4. These inputs must be operated simultaneously for 32 bit operation, in pairs
in 16 bit mode and singly for 8 bit mode.
(2) Also for WE1~4 on the PUMA 68E4001A version. Additionally, WE1~4 are accessed as in note (1) above.
Capacitance (TA=25°C,ƒ=1MHz) Note: These parameters are calculated, not measured.
Parameter
Input Capacitance
Symbol
CS1~4, WE1~4(1)
Other Inputs
Output Capacitance
CIN1
CIN2
COUT
Test Condition
typ
max Unit
VIN=0V
VIN=0V
-
20
22
pF
pF
VOUT=0V
-
22
pF
Notes: (1) On the PUMA 68E4001A version only.
2
PUMA 68E4001/A-12/15/17/20
ISSUE 4.3 May 2001
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symnbol min
12
max
min
15
max
20
min
max
Unit
Read Cycle Time
tRC
120
-
150
-
200
-
ns
Address Access Time
tAA
-
120
-
150
-
200
ns
Chip Select Access Time
tCS
-
120
-
150
-
200
ns
Output Enable Access Time
tOE
0
60
0
70
0
80
ns
Chip Select High to High Z Output (1)
tHZ
0
50
0
50
0
50
ns
Output Enable High to High Z Output (1) tOHZ
0
50
0
50
0
50
ns
Chip Select Low to Active Output (1)
tLZ
0
-
0
-
0
-
ns
Output Enable Low to Active Output (1)
tOLZ
0
-
0
-
0
-
ns
Output Hold from Address Change
tOH
0
-
0
-
0
-
ns
Notes: (1) tHZ max. and tOLZ max. are measured with CL = 5pF, from the point when Chip Select or Output Enable return high
(whichever occurs first) to the time when the outputs are no longer driven. tHZ and tOHZ are shown for reference only:
they are characterized and not tested.
Write Cycle
Parameter
Symbol
min
typ
max
Unit
Write Cycle Time
tWC
-
-
10
ms
Address Set-up Time
tAS
0
-
-
ns
Address Hold Time
tAH
50
-
-
ns
Output Enable Set-up Time
tOES
0
-
-
ns
Output Enable Hold Time
tOEH
0
-
-
ns
Chip Select Set-up Time
tCS
0
-
-
ns
Chip Select Hold Time
tCH
0
-
-
ns
Write Pulse Width
tWP
100
-
-
ns
Write Enable High Recovery
tWPH
50
-
-
ns
Data Set-up Time
tDS
50
-
-
ns
Data Hold Time
tDH
0
-
-
ns
Delay to Next Write
tDW
10
-
-
µs
Byte Load Cycle
tBLC
-
-
150
µs
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 10ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* VCC=5V±10%
Output Test Load
I/O Pin
645 Ω
1.76V
100pF
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ISSUE 4.3 : May 2001
PUMA 68E4001/A-12/15/17/20
Read Cycle Timing Waveform
tRC
Address Valid
A0~A16
tAA
CS1~4
tOHZ
tCS
tOE
tOHZ
OE
tOH
tOLZ
Data
Output
Valid
HIGH Z
tCLZ
AC Write Waveform - WE Controlled
t WC
Address
t AS
t AH
t WPH
t WP
WE
t CS
t CH
CS1~4
t OES
OE
t OEH
DATA
t DS
4
t DH
PUMA 68E4001/A-12/15/17/20
ISSUE 4.3 May 2001
AC Write Waveform - CS Controlled
t WC
Address
t AS
t CS
t AH
t CH
WE
t WP
CS1~4
t WPH
t OES
OE
t OEH
DATA
t DS
t DH
Page Mode Write Waveform
OE
CS1~4
tWPH
tWP
tBLC
WE
tAS
A0-A16
tAH
tDH
Valid
Add
tDS
Data
Valid
Data
Byte 0
Byte 1
Byte 2
Byte 3
Byte 126
Byte 127
tWC
Note: A8 through A16 must specify the page address during each high to low transition of Write Enable (or Chip select).
Output Enable must be high only when Write Enable and Chip Select are both low.
1998
ISSUE 4.3 : May 2001
PUMA 68E4001/A-12/15/17/20
DATA Polling Waveform
WE/WE1~4
CS1~4
tOEH
OE
tDH
tWR
tOE
High Z
D7,D15,
D23,D31
tDW
An
A0-A16
An
An
An
An
Toggle Bit Waveform
WE/WE1~4
CS1~4
tOEH
OE
tOE
tDH
D6,D14,
D22,D30
tWR
HIGH Z
tDW
Software Protected Write Waveform
OE
CS1~4
tWP
t BLC
WE/WE1~4
tAS
tWPH
tAH
A0~A6
BYTE ADDRESS
05555
02AAA
05555
A7~A16
PAGE ADDRESS
tDS
Data
AA
tDH
55
tWC
A0
Byte 0
6
Byte 126
Byte 127
PUMA 68E4001/A-12/15/17/20
ISSUE 4.3 May 2001
Device Operation
The following description deals with the PUMA 68E4001 device, with the references to WE meaning WE1~4
on the PUMA 68E4001A part.
Read
The PUMA 68E4001 read operations are initiated by both Output Enable and Chip Select LOW. The read operation
is terminated by either Chip Select or Output Enable returning HIGH. This 2-line control architecture eliminates
bus contention in a system environment. The data bus will be in a high impendence state when either Output Enable
or Chip Select is HIGH.
Write
Write operations are initiated when both Chip Select and Write Enable are LOW and Output Enable is HIGH. The
PUMA 68E4001 supports both a Chip Select and Write Enable controlled write cycle. That is, the address is latched
by the falling edge of either Chip Select or Write Enable, whichever occurs last. Similarly, the data is latched
internally by the rising edge of either Chip Select or Write Enable, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion, typically within 5 ms.
Page Mode Write
The page write feature of the PUMA 68E4001 allows the entire memory to be written in 5 seconds. Page Write
allows 128 bytes of data to be written prior to the internal programming cycle. The host can fetch data from another
location within the system during a page write operation (change the source address), but the page address (A8
through A16) for each subsequent valid write cycle to the part during this operation must be the same as the initial
page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can
write up to 128 bytes in the same manner as the first byte written. Each successive byte load cycle, started by
the Write Enable HIGH to LOW transition, must begin within 150 µs of the falling edge of the preceding Write Enable.
If a subsequent Write Enable HIGH to LOW transition is not detected within 150 µs, the internal automatic
programming cycle will commence.
DATA Polling
The PUMA 68E4001 features DATA Polling to indicate if the write cycle is completed. During the internal
programming cycle, any attempt to read the last byte written will produce the compliment of that data on D7. Once
the programming is complete, D7 will reflect the true data. Note: If the the PUMA 68E4001 is in a protected state
and an illegal write operation is attempted DATA Polling will not operate.
TOGGLE bit
In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write
operation successive attempts to read data will result in D6 toggling between 1 and 0. Once a write is complete,
this toggling will stop and valid data will be read.
Hardware Data Protection
The PUMA 68E4001 provides three hardware features to protect non-volalitile data from inadvertent writes.
•
•
•
Noise Protection - A Write Enable pulse less than 15 ns will not initiate a write cycle.
Default VCC Sence - All functions are inhibited when VCC < 3.6 V.
Write Inhibit - Holding either Output Enable LOW, Write Enable HIGH or Chip Select HIGH will prevent an
inadvertent write cycle during power on or power off, maintaining data integrity.
1998
ISSUE 4.3 : May 2001
PUMA 68E4001/A-12/15/17/20
Software Data Protection
The PUMA 68E4001 can be automatically protected during power-up and power-down without the need for external
circuits by employing the software data protect feature. The internal software data protection circuit is enabled after
the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of
the device unless the reset command is issued.
Once the software protection is enabled, the PUMA 68E4001 is also protected against inadvertent and accidental
writes in that, the software algorithm must be issued prior to writing additional data to the device.
Operating Modes
The table below shows the logic inputs required to control the operation of the PUMA 68E4001.
MODE
Read
Write
Standby
Write Inhibit
CS1~4 OE
0
0
1
X
X
0
I
X
X
0
WE
OUTPUTS
1
0
Data Out
Data in
Floating
X
1
X
0 = VIL : 1 = VIH : X = VIH or VIL
8
PUMA 68E4001/A-12/15/17/20
ISSUE 4.3 May 2001
Software Algorithms
Selecting the software data protection mode requires the host system to precede datawrite operations by a series
of three write operations to three specfic addresses. The three byte sequence opens the page write window
enabling the host to write from from 1 to 128 bytes of data. Once the page load cycle has been completed, the device
will automatically be returned to the data protected state
Software Data Protection Algorithm
Regardless of wheather the device has been protected or not, once the software data protected aglorithm is used
and the data is written, the PUMA 68E4001 will automatically disable further writes unless another command is
issued to cancel it. If no further commands are issued the PUMA 68E4001 will be write protected during powerdown and any subsequent power-up.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES
ENABLED (2)
LOAD DATA XX
TO
ANY ADDRESS (4)
LAST BYTE / WORD
TO
LAST ADDRESS
ENTER DATA
PROTECT
STATE
Notes:
(1) Data Format I/O7-I/O0 (Hex);
Once initiated, this sequence of write operations should not be interrupted.
(2) Enable Write Protect state will be initiated at end of write even if no other data is loaded.
(3) Disable Write Protect state will be initiated at end of write period even if no other data is loaded.
(4) 1 to 128 bytes of data may be loaded.
1998
ISSUE 4.3 : May 2001
PUMA 68E4001/A-12/15/17/20
Software Data Protect Disable
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an
E2PROM programmer. The following six step algorithm will reset the internal protection circuit. After tWC, the PUMA
68E4001 will be in standard operating mode.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS (4)
LAST BYTE / WORD
TO
LAST ADDRESS
10
EXIT DATA
PROTECT
STATE (3)
PUMA 68E4001/A-12/15/17/20
ISSUE 4.3 May 2001
Block Diagram 'A' version
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE1
A6
A7
A8
A9
A10
VCC
Pin Definifion 'A' version
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
VIEW
18
52
19
51
FROM
20
50
ABOVE
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CS2
NC
WE2
WE3
WE4
NC
GND
NC
CS1
OE
PUMA 68E4001A
Vcc
A11
A12
A13
A14
A15
A16
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
A0~A16
OE
WE4
WE3
WE2
WE1
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
1998
ISSUE 4.3 : May 2001
PUMA 68E4001/A-12/15/17/20
Package Information
Dimensions in mm(inches)
Plastic 68 Pin JEDEC Surface mount PLCC
25.40 (1.000)
24.89 (0.980)
1.27
(0.050) Typ.
0.43
(0.017) Typ.
24.13 (0.950)
23.11 (0.910)
5.08 (0.200)
Max.
1.02 (0.040)
Typ.
Ordering Information
PUMA 68E4001AM-15E
Endurance
Blank
E
=
=
10k Cycles
100k Cycles
12
15
20
=
=
=
120ns
150ns
200ns
Temperature range
Blank
I
M
=
=
=
Commercial Temperature
Industrial Temperature
Military Temperature
Special Features
Blank
A
=
=
WE
WE1~4
4001
=
128K x 32, user configurable
as 256K x 16 and 512K x 8
E
=
EEPROM
PUMA 67
=
68 pin "J" Leaded PLCC
Speed
Organisation
Memory Type
Package
12
PUMA 68E4001/A-12/15/17/20
ISSUE 4.3 May 2001
Visual Inspection Standard
All devices inspected to ANSI/J-STD-001B Class 2 standard
Moisture Sensitivity
Devices are moisture sensitive.
Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH).
After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow,
or equivalent processing (peak package body temp 220OC) must be :
A : Mounted within 72 Hours at factory conditions of <30OC/60% RH
OR
B : Stored at <20% RH
If these conditions are not met or indicator card is >20% when read at 23OC +/-5% devices require baking
as specified below.
If baking is required, devices may be baked for :A : 24 hours at 125OC +/-5% for high temperature device containers
OR
B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers.
Packaging Standard
Devices packaged in dry nitrogen, JED-STD-020.
Packaged in trays as standard.
Tape and reel available for shipment quantities exceeding 200pcs upon request.
Soldering Recomendations
IR/Convection -
Ramp Rate
Temp. exceeding 183OC
Peak Temperature
Time within 5OC of peak
Ramp down
6OC/sec max.
150 secs. max.
225OC
20 secs max.
6OC/sec max.
Vapour Phase -
Ramp up rate
Peak Temperature
Time within 5OC of peak
Ramp down
6OC/sec max.
215 - 219OC
60 secs max.
6OC/sec max.
The above conditions must not be exceeded.
Note : The above recommendations are based on standard industry practice. Failure to comply with
the above recommendations invalidates product warranty.
1998
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