datasheet for PUMA84FV256006 by Apta Group

datasheet for PUMA84FV256006 by Apta Group
Description
The PUMA 84 range of devices provide a high
density, surface mount memory solution with
density up to twice that of standard monolithic
devices.
The PUMA 84 may accomodate various memory
technologies including SRAM, FLASH and
EEPROM. The devices are designed to offer a
defined upgrade path and may be user configured
as 8, 16 or 32 bits wide.
The PUMA 84FV256006 is a 8M x 32, 3.3V FLASH
Module in a 84 ‘J’ Leaded package which complies
with the JEDEC 84 PLCC standard.
Issue 5.3 July 2001
Block Diagram
A0 ~A21
/WE
/OE
/RESET
4M x 8
FLASH
D0 ~ 7
4M x 8
FLASH
D0 ~ 7
4M x 8
FLASH
D8 ~ 15
4M x 8
FLASH
D16 ~ 23
4M x 8
FLASH
D24 ~ 31
/CS5
/CS1
4M x 8
FLASH
D8 ~ 15
/CS6
/CS2
4M x 8
FLASH
D16 ~ 23
Access times of 90/120/150 ns are available.
The 3.3V device is available to commercial and
industrial temperature grade.
Features
• Access times of 90, 120 and 150ns.
• 3.3V + 10% VCC.
• Commercial and Industrial temperature grades
• JEDEC Standard 84 ‘J’ Lead surface mount
package.
• May be organised as 8M x 32, 16M x 16 and
32M x 8
• Flexible Sector (64 KByte) Architecture.
• Embedded Algorithms.
• Multiple Ground pins for maximum noise
immunity.
Package Details
PUMA 84 - Plastic 84 ‘J’ Leaded Package.
Max. Dimensions - 30.35 x 30.35 x 6.00 (nom)
All Dimensions in mm.
/CS7
/CS3
4M x 8
FLASH
/CS4
D24 ~ 31
/CS8
Pin Definition
See page 2.
Pin Functions
Description
Signal
Address Input
Data Input/Output
Chip Select
Write Enable
Output Enable
Hardware Reset
No Connect
Power
Ground
A0~A21
D0~D31
/CS1~8
/WE
/OE
/RESET
NC
VCC
GND
Elm Road, West Chirton Industrial Estate, North Shields, NE29 8SE, England.
TEL +44 (0191) 2930500. FAX +44 (0191) 2590997 E-mail: [email protected]
8M x 32 FLASH Module
hmp
PUMA 84FV256006 - 90/12/15
11
Pin Definition - PUMA84FV256006
1
84
75
74
12
PAGE 2
Pin
Signal
Pin
Signal
1
VCC
43
VCC
2
NC
44
A13
3
/CS1
45
A12
4
/CS2
46
A11
5
/CS3
47
A10
6
/CS4
48
A9
7
A17
49
A8
8
A18
50
A7
9
D16
51
D0
10
A19
52
NC
11
A20
53
NC
12
A21
54
NC
13
NC
55
NC
14
D17
56
D1
15
D18
57
D2
16
D19
58
D3
17
GND
59
GND
18
D20
60
D4
19
D21
61
D5
20
D22
62
D6
21
D23
63
D7
22
VCC
64
VCC
23
D24
65
D8
24
D25
66
D9
25
D26
67
D10
26
D27
68
D11
27
GND
69
GND
28
D28
70
D12
29
D29
71
D13
30
D30
72
D14
31
NC
73
NC
32
NC
74
NC
33
/RESET
75
D15
34
NC
76
A14
35
D31
77
A15
36
A6
78
A16
37
A5
79
/WE
38
A4
80
/OE
39
A3
81
/CS5
40
A2
82
/CS6
41
A1
83
/CS7
42
A0
84
/CS8
VIEW
FROM
ABOVE
54
32
33
53
Issue 5.3 July 2001
Absolute Maximum Ratings(1)
Symbol
Min
Typ
Max
Unit
Supply Voltage
V CC
-2.0
-
+7.0
V
Voltage on V CC relative to GND
VT
-0.5
-
+4.0
V
Voltage on A9, /OE, /RESET
relative to GND
V A9
-0.5
-
+12.5
V
All other pins relative to GND
V AA
-0.5
-
V CC +0.5V
Storage Temperature
T STG
-65
-
V
O
+100
C
Notes : (1) Minimum DC Voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot GND to 2.0V for periods of up to 20ns . See Maximum DC Voltage on output and I/O pins is VCC+0.5V. During Voltage
transitions, outputs may overshoot to VCC+2.0V for periods up to 20ns.
(2) Minimum DC input voltage on A9, /OE, /RESET pins is -0.5V. During voltage transitions, A9 ,/OE and /RESET
pins may overshoot GND to -2.0V for periods of up to 20ns. Maximum DC Input voltage on A9, /OE and /RESET
is 12.5V which may overshoot to 13.5V fo periods up to 20ns.
(3) No more than one output shorted at a time. Duration of a short circuit should not be greater than one second.
Stresses Greater than those listed in this section may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this of this specification is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
3.0
3.3
3.6
V
Input High Voltage
VIH
VCCx 0.7
-
VCC+0.3
V
Input Low Voltage
VIL
-0.5
-
0.8
Operating Temperature (Commercial)
TA
0
TAI
(Industrial)
-
-40
-
V
70
O
85
O
C
C
(I Suffix)
Capacitance
(VCC = 3.3V, TA = 25OC, F=1MHz.)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Input Capacitance
CIN
VIN=0V
-
6
7.5
pF
Output Capacitance
COUT
VOUT=0V
-
8.5
12
pF
Note : These Parameters are calculated not measured.
Test Conditions
•
•
•
•
•
•
Input pulse levels : 0V to 3.0V
Input rise and fall times : 20ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
Module tested in 32 bit mode.
VCC = 3.3V+10%
PAGE 3
Output Load
I/O Pin
166Ω
1.76V
30pF
Issue 5.3 July 2001
DC Operating Conditions
Parameter
DC Electrical Characteristics
(VCC=3.3V+10%, TA=-40OC to 85OC)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
-8
-
+8
µA
-
-
280
µA
-8
-
+8
µA
Input Load Current
ILI1
V IN = GND to V CC, V CC = V CC max
A9 Input Load Current
ILI2
V CC = V CC max ; A9 = 12.5 V
Output Leakage Current
ILO
V OUT = GND to V CC , V CC = V CC
max
32 Bit
ICCR32
/CS# = V IL, /OE = V IH, 5MHZ
-
-
77
mA
16 Bit
ICCR16
As Above
-
-
39
mA
8 Bit
ICCR8
As Above
-
-
20
mA
32 Bit
ICCW32 /CS# = V IL, /OE = V IH
-
-
144
mA
16 Bit
ICCW16 As Above
-
-
72
mA
8 Bit
ICCW8
-
-
36
mA
-
-
40
µA
40
µA
40
µA
V CC Active Read
(1,2)
V CC Active Write
(1,3,5)
Standby Supply Current
V CC Reset Current
(1)
TTL
(1)
Automatic Sleep Mode
ISB
As Above
V CC=V CCmax,/CS=V IH
(1)
/OE=V IH
ICCRES /RESET = GND ± 0.3 V,
V
(1,4)
=V
± 0.3 V;
CC
ICCASM V IH = GND
± 0.3 V
IL
Autoselect and Temporary Sector
Unprotect Voltage
V ID
V CC = 3.3 V
Output Voltage Low
V OL
IOL=12mA, V CC = V CC Min
V OH1
IOH=-2.5mA, V CC = V CC Min
Output Voltage High
Low V CC Lock-Out Voltage
(5)
V LKO
11.5
-
12.5
V
-
-
0.45
V
2.4
-
-
V
2.3
-
2.5
V
Notes:
1. Maximum ICC specifications are tested with VCC = VCC max.
2. The ICC current listed is typically is less than 2 mA/MHz, with /OE at VIH . Typical specifications
are for VCC = 3.0 V.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode. Typical sleep mode current is 200 nA.
5. Not 100% tested.
PAGE 4
Issue 5.3 July 2001
90
Parameter
120
150
Symbol Min Max Min Max Min Max Units
Read Cycle Time
tRC
90
-
120
-
150
-
ns
Address to Output Delay
tACC
-
90
-
120
-
150
ns
Chip Select to Output
tCE
-
90
-
120
-
150
ns
Output Enable to Output
tOE
-
40
-
50
-
55
ns
Output Enable to Output High Z
tDF
-
30
-
30
-
35
ns
Output Hold From Address
/CS or /OE whichever occurs first
tOH
0
-
0
-
0
-
ns
Erase/Program
Parameter
Symbol Min
90
120
150
Typ Max Min
Typ Max Min Typ. Max Units
Write Cycle Time
tWC
90
-
-
120
-
-
150
-
-
ns
Address Setup Time
tAS
0
-
-
0
-
-
0
-
-
ns
Address Hold Time
tAH
45
-
-
50
-
-
55
-
-
ns
Data Setup Time
tDS
45
-
-
50
-
-
55
-
-
ns
Data Hold Time
tDH
0
-
-
0
-
-
0
-
-
ns
Read Recover before
Write
tGHWL
0
-
-
0
-
-
0
-
-
ns
/CS Setup Time
tCS
0
-
-
0
-
-
0
-
-
ns
/CS Hold Time
tCH
0
-
-
0
-
-
0
-
-
ns
/WE Pulse Width
tWP
45
-
-
50
-
-
55
-
-
ns
/WE Pulse Width High
tWPH
30
-
-
30
-
-
30
-
-
ns
Programming
(2)
Operation
tWHWH1
-
9
-
-
9
-
-
9
-
µs
Sector Erase
(2)
Operation
tWHWH2
-
-
0.7
-
-
0.7
-
-
0.7
s
VCC Setup Time
tVCS
50
-
-
50
-
-
50
-
-
µs
Notes : (1) Not 100% tested.
(2) This does not include the preprogramming time.
PAGE 5
Issue 5.3 July 2001
AC Operating Conditions
Read Cycle
Erase/Program Alternate /CS controlled Writes
Parameter
Symbol Min
(1)
90
120
150
Typ Max Min
Typ Max Min Typ. Max Units
Write Cycle Time
tWC
90
-
-
120
-
-
150
-
-
ns
Address Setup Time
tAS
0
-
-
0
-
-
0
-
-
ns
Address Hold Time
tAH
45
-
-
50
-
-
55
-
-
ns
Data Setup Time
tDS
45
-
-
50
-
-
55
-
-
ns
Data Hold Time
tDH
0
-
-
0
-
-
0
-
-
ns
Read Recover before
Write
tGHEL
0
-
-
0
-
-
0
-
-
ns
/WE Setup Time
tWS
0
-
-
0
-
-
0
-
-
ns
/WE Hold Time
tWH
0
-
-
0
-
-
0
-
-
ns
/CS Pulse Width
tCP
45
-
-
50
-
-
55
-
-
ns
/CS Pulse Width High
tCPH
30
-
-
30
-
-
30
-
-
ns
Programming
(2)
Operation
tWHWH1
-
9
-
-
9
-
-
9
-
µs
Sector Erase
(2)
Operation
tWHWH2
-
0.7
-
-
0.7
-
-
0.7
-
s
Notes : (1) Not 100% tested.
(2) This does not include the preprogramming time.
Hardware Reset (/RESET)
Description
Test Setup
All Speed
Options
Unit
tREADY
/RESET Pin Low (NOT During
Embedded Algorithms) to Read or Write*
Max
500
ns
tRP
/RESET Pulse Width
Min
500
ns
tRH
/RESET High Time before Read*
Min
50
ns
Parameter
*Note : Not 100% tested
PAGE 6
Issue 5.3 July 2001
(Figure 1)
Timing Waveforms
Read Operations Timings
tRC
Addresses
Addresses Stable
tACC
/CS1~8
tDF
tOE
/OE
tOEH
/WE
tCE
tOH
High Z
High Z
Output Valid
Outputs
/RESET
RESET Timings
(Figure 2)
/CS1~8,
/OE
tRH
/RESET
tRP
tREADY
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
/CS1~8,
/OE
/RESET
tRP
PAGE 7
Issue 5.3 July 2001
Program Operation Timings
Program Command Sequence (last two cycles)
(Figure 3)
tAS
tWC
Addresses
Read Status Data (last two cycles)
XXXh
PA
PA
PA
tAH
/CS1~8
tCH
/OE
tWHWH1
tWP
/WE
tWPH
tDH
tCS
tDS
PD
A0h
Data
Status
DOUT
tVCS
VCC
Note : PA = Program Address, PD = Program Data, DOUT is the true data at the program address.
Chip/Sector Erase Operation Timings
(Figure 4)
Erase Command Sequence (last two cycles)
tAS
tWC
XXXh
Addresses
Read Status Data
SA
VA
XXXh for chip erase
VA
tAH
/CS1~8
tCH
/OE
tWHWH2
tWP
/WE
tWPH
tCS
tDS
tDH
55h
Data
tVCS
30h
In
Progress
Complete
10 for Chip Erase
VCC
Note : SA=Sector Address. VA=Valid Address for reading status data.
PAGE 8
Issue 5.3 July 2001
Data Polling Timings (During Embedded Algorithms)
(Figure 5)
tRC
Addresses
VA
VA
VA
tACC
tCE
/CS1~8
tCH
tOE
/OE
tDF
tOEH
/WE
tOH
D7
Complement
D0~D6
Status Data
Complement
Status Data
Valid
Data
True
Valid
Data
True
High Z
High Z
Note :
VA = Valid Address. Illustration shows first status cycle after command sequence,
last status read cycle, and array data read cycle.
Toggle Bit Timings (During Embedded Algorithms)
(Figure 6)
tRC
Addresses
VA
VA
VA
VA
tACC
/CS1~8
tCH
tCE
tOE
/OE
tOEH
tDF
/WE
tOH
High Z
D6/D2
VS
VS
(first read)
(second read)
VS
VD
(stops toggling)
Note :
VA=Valid Address; not required for D6. Illustration shows first two status cycle after
command sequence, last status read cycle, and array data read cycle.
VS=Valid Status, VD=Valid Data
PAGE 9
Issue 5.3 July 2001
D2 vs D6
(Figure 7)
Enter
Embedded
Erasing
/WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase Complete
D6
D2
Note : The system can use /OE or /CS1~8 to toggle D2/D6. D2 toggles only when read at an address
within an erase-suspended sector.
Sector Protect/Unprotect Timing Diagram
(Figure 8)
VID
/RESET
VIH
SA,A6,
A1,A0
Valid*
Valid*
Sector/Sector Block Protect/Unprotect
60h
Data
60h
Valid*
Verify
40h
Status
1µs
/CS1~8
Sector/Sector Block Protect : 150µs
Sector/Sector Block Unprotect : 15ms
/WE
/OE
Note : For Sector Protect, A6=0, A1=1, A0=0. For Sector Unprotect, A6=1, A1=1, A0=0.
PAGE 10
Issue 5.3 July 2001
Temporary Sector/Sector Block Unprotect Timing Diagram
(Figure 9)
12V
/RESET
0 to 5V
0 to 5V
tVDIR
tVDIR
Program or Erase Command Sequence
/CS1~8
/WE
tRSP
Alternate /CS Controlled Write Operation Timings
(Figure 10)
PA for program
XXX for program SA for sector erase
XXX for chip erase
XXX for erase
Data Polling
PA
Addresses
tWC
tAS
tAH
tWH
/WE
tGHEL
/OE
tCP
/CS1~8
tWHWH1 or 2
tCPH
tDH
tWS
tDS
D7
Data
DOUT
tRH
/RESET
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA =Program Address, PD=Program Data, SA=Sector Address,
D7=Compliment of Data Input, DOUT=Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
PAGE 11
Issue 5.3 July 2001
Algorithms
Program Operation
START
(Figure 11)
Write Program
Command Sequence
Data Poll
From System
Embedded
Program
Algorithm
In Progress
Verify Data
No
Yes
No
Last Address
Increment address
Yes
Programming
Completed
Note :
See the appropriate Command definitions table for program command sequence
Erase Operation
START
(Figure 12)
Write Erase
Command Sequence
Data Poll
From System
Embedded
Erase
Algorithm
In Progress
Data =FFh?
No
Yes
Erasure
Completed
Note :
1. See the appropriate Command definitions table for erase command sequence.
2. See ’D3 : Sector Erase Timer’ For more information.
PAGE 12
Issue 5.3 July 2001
Temporary Sector Unprotect Operation
(Figure 13)
START
RESET = VID (1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotect Completed(2)
Notes :
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
PAGE 13
Issue 5.3 July 2001
In-System Sector Protect/Unprotect Algorithms
(Figure 14)
START
Protect All Sectors :
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector unprotect
address
START
PLSCNT = 1
RESET# = VID
PLSCNT = 1
RESET# = VID
Wait 1µs
Wait 1µs
Temporary Sector
Unprotect Mode
No
First Write
Cycle=60h?
All sectors
protected?
Setup Sector
Address
Yes
Setup First Sector
Address
Sector Protect :
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0.
Sector Unprotect :
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0.
Wait 150µs
Wait 15ms
Verify Sector
Protect : Write 40h
to Sector Address
with A6 = 0,A1 = 1,
A0 = 0.
Reset
PLSCNT = 1
Verify Sector
Unprotect :
Write 40h
to Sector Address
with A6 = 1,A1 = 1,
A0 = 0.
Increment
PLSCNT
Read from
sector address
with A6 = 0,
A1 = 1,A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1,A0 = 0
No
PLSCNT = 25?
Yes
Device Failed
No
No
Data = 01h?
PLSCNT
= 1000?
Yes
Protect Another
Sector?
No
Yes
Yes
Device Failed
Remove VID
from RESET#
Data = 00h?
Yes
Last Sector
Verified?
No
Yes
Write reset
command
Sector Protect
complete
Sector Unprotect
Algorithm
PAGE 14
No
Set up
next sector
address
Remove VID
from RESET#
Write reset
command
Sector Protect
Algorithm
Temporary Sector
Unprotect Mode
Yes
First Write
Cycle=60h?
Yes
Increment
PLSCNT
No
Sector Unprotect
complete
Issue 5.3 July 2001
Data Polling Algorithm
START
(Figure 15)
Read D7~D0
Addr=VA
Yes
D7=Data?
No
D5=1?
No
Yes
Read D7~D0
Addr = VA
Yes
D7=Data?
No
FAIL
PASS
Note :
1. VA = Valid Address for programming. During a sector erase operartion, a valid adddress
is an address within any sector selected for erasure. During chip erase, a valid address is
any non-protected sector address.
2. D7 should be rechecked even if D5 = ’1’ beceause D7 may change simultaneously with D5.
Toggle Bit Algorithm
START
(Figure 16)
Read D7~D0
(Note 1.)
Read D7~D0
No
Toggle Bit
= Toggle?
Yes
D5=1?
No
Yes
Read D7~D0
Twice
(Notes 1,2)
No
Toggle Bit
= Toggle?
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command.
Program/Erase
Operation Complete
Note :
1. Read Toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as D5 changes to ’1’ . See text.
PAGE 15
Issue 5.3 July 2001
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the /CS# and
/OE pins to VIL . /CS# is the power control and selects the device. /OE
is the output control and gates array data to the output pins. /WE should
remain at VIH .
The internal state machine is set for reading array data upon device
power-up, or after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses on the device
address inputs produce valid data on the device data outputs. The
device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read
Operations table for timing specifications and to Figure 1 for the timing
diagram. ICCR32/ICCR16/ICCR8 in the DC Characteristics table represents the
active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of memory), the
system must drive /WE and /CS# to VIL , and /OE to VIH .
The device features an Unlock Bypass mode to facilitate faster
programming. Once the device enters theUnlock Bypass mode, only two
write cycles are required to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on programming
data to the device using both standard and Unlock Bypass command
sequences.
An erase operation can erase one sector, multiple sectors, or the entire
device. Table indicates the address space that each sector occupies. A
“sector address” consists of the address bits required to uniquely select
a sector. The “Writing specific address and data commands or
sequences into the command register initiates device operations. Table
9 defines the valid register command sequences. Writing incorrect
address and data values or writing them in the improper sequence resets
the device to reading array data.” section has details on erasing a sector
or the entire chip, or suspending/resuming the erase operation.
PAGE 16
Issue 5.3 July 2001
Device Bus Operations
This section describes the requirements and use ofthe device bus
operations, which are initiated through the internal command register.
The command register itself does not occupy any addressable memory
location.The register is composed of latches that store the commands,
along with the address and data information needed to execute the
command. The contents of the register serve as inputs to the internal
state machine.The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control
levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
After the system writes the autoselect command sequence, the device
enters the autoselect mode. The system can then read autoselect codes
from the internal register (which is separate from the memory array) on
D7–D0. Standard read cycle timings apply in this mode. Refer to the
Autoselect Mode and Autoselect Command Sequence sections for
more information. ICCW32/ICCW16/ICCW8 in the DC Characteristics table
represents the active current specification for the write mode. The “AC
Characteristics” section contains timing specification tables and timing
diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status
of the operation by reading the status bits on D7–D0. Standard read
cycle timings and ICCR32/ICCR16/ICCR8 read specifications apply. Refer to
“Write Operation Status” for more information, and to “AC
Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the
device in the standby mode. Inthis mode, current consumption is greatly
reduced, and the outputs are placed in the high impedance state,
independent of the /OE input.
The device enters the CMOS standby mode when the /CS# and /RESET
pins are both held at VCC ± 0.3 V. (Note that this is a more restricted
voltage range than VIH .) If /CS# and /RESET are held at VIH , but not
within VCC ± 0.3 V, the device will be in the standby mode, but the standby
current will be greater. The device requires standard access time (tCE )
for read access when the device is in either of these standby modes,
before it is ready to read data.
The device also enters the standby mode when the /RESET pin is driven
low. Refer to the next section, “/RESET: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device
draws active current until the operation is completed.
ISB in the DC Characteristics table represents the standby current
specification.
PAGE 17
Issue 5.3 July 2001
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is
i ndependent of the /CS#, /WE, and /OE control signals. Standard
address access timings provide new data when addresses are changed.
While in sleep mode, output data is latched and always available to the
system. ICCRES in the DC Characteristics table represents the automatic
sleep mode current specification.
/RESET: Hardware Reset Pin
The /RESET pin provides a hardware method of resetting the device to
reading array data. When the /RESET pin is driven low for at least a
period of tRP , the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands
for the duration of the /RESET pulse. The device also resets the internal
state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the /RESET pulse. When /RESET
is held at GND ± 0.3V, the device draws CMOS standby current (ICCRES).
If /RESET is held at VIL but not within GND ± 0.3 V, the standby current
will be greater.
The /RESET pin may be tied to the system reset circuitry. A system reset
would thus also reset the Flash memory, enabling the system to read the
boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for /RESET parameters and to
Figure 2 for the timing diagram.
Output Disable Mode
When the /OE input is at VIH , output from the device is disabled. The
output pins are placed in the high impedance state.
PAGE 18
Issue 5.3 July 2001
Autoselect Mode
The autoselect mode provides manufacturer and device identification,
and sector protection verification, through identifier codes output on D7–
D0. This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID
(11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must
be as shown in Table 3. In addition, when verifying sector protection, the
sector address must appear on the appropriate highest order address
bits (see Table ). Table 3 shows the remaining address bits that are don’t
care. When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier
code on D7-D0.
To access the autoselect codes in-system, the host system can issue
the autoselect command via the command register, as shown in Table
9. This method does not require VID . See “Writing specific address and
data commands or sequences into the command register initiates
device operations. Table 9 defines the valid register command
sequences. Writing incorrect address and data values or writing them in
the improper sequence resets the device to reading array data.” for
details on using the autoselect mode.
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term “sector” applies to both
sectors and sector blocks. A sector block consists of two or more
adjacent sectors that are protected or unprotected at the same time see
Table 4).
The hardware sector protection feature disables both program and
erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previously
protected sectors. Sector protection/unprotection can be implemented
via two methods.
The primary method requires VID on the /RESET pin only, and can be
implemented either in-system or via programming equipment. Figure 14
shows the algorithms and Figure 8 shows the timing diagram. This
method uses standard microprocessor bus cycleing. For sector
unprotect, all unprotected sectors must first be protected prior to the first
sector unprotect write cycle.
The alternate method intended only for programming equipment
requires VID on address pin A9 and /OE. The device is shipped with all
sectors unprotected. It is possible to determine whether a sector is
protected or unprotected. See “Autoselect Mode” for details.
PAGE 19
Issue 5.3 July 2001
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector” applies to both
sectors and sector blocks. A sector block consists of two or more
adjacent sectors that are protected or unprotected at the same time, see
Table 4).
This feature allows temporary unprotection of previously protected
sectors to change data in-system. The Sector Unprotect mode is
activated by setting the /RESET pin to VID. During this mode, formerly
protected sectors can be programmed or erased by selecting the sector
addresses. Once VID is removed from the /RESET pin, all the previously
protected sectors are protected again. Figure 13 shows the algorithm,
and Figure 9 shows the timing diagrams, for this feature.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming
or erasing provides data protection against inadvertent writes (refer to
Table 9 for command definitions). In addition, the following hardware
data protection measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO , the device does not accept any write cycles.
This protects data during VCC power-up and power-down. The command
register and all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC is greater than
VLKO . The system must provide the proper signals to the control pins to
prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on /OE, /CS# or /WE do not initiate
a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of /OE = VIL , /CS# = VIH or
/WE = VIH . To initiate a write cycle, /CS# and /WE must be a logical zero
while /OE is a logical one.
Power-Up Write Inhibit
If /WE = /CS# = VIL and /OE = VIH during power up, the device does not
accept commands on the rising pro-edge of /WE. The internal state
machine is automatically reset to reading array data on power-up.
PAGE 20
Issue 5.3 July 2001
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-lines device and
host system software interrogation handshake, which allows specific
vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC IDindependent, and forward-and-backward-compatible for the specified
flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI
Query command, 98h, to address 55h, any time the device is ready to
read array data. The system can read CFI information at the addresses
given in Tables 5–8. To terminate reading CFI data, the system must
write the reset command.
The system can also write the CFI query command when the device is
in the autoselect mode. The device enters the CFI query mode, and the
system can read CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the device to the
autoselect mode.
PAGE 21
Issue 5.3 July 2001
Reading Array Data
The device is automatically set to reading array data after device powerup. No commands are required to retrieve data. The device is also ready
to read array data after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command, the device enters
the Erase Suspend mode. The system can read array data using the
standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the system may
once again read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more information on this
mode.
The system must issue the reset command to re-enable the device for
reading array data if D5 goes high, or while in the autoselect mode. See
the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the “Device Bus
Operations” section for more information. The Read Operations table
provides the read parameters, and Figure 1 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading
array data. Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an
erase command sequence before erasing begins. This resets the device
to reading array data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a
program command sequence before programming begins. This resets
the device to reading array data (also applies to programming in Erase
Suspend mode). Once programming begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an
autoselect command sequence. Once in the autoselect mode, the reset
command must be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If D5 goes high during a program or erase operation, writing the reset
command returns the device to reading array data (also applies during
Erase Suspend).
PAGE 22
Issue 5.3 July 2001
Command Definitions
Writing specific address and data commands or sequences into the
command register initiates device operations. Table 9 defines the valid
register command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the device to
reading array data. All addresses are latched on the falling edge of /WE#
or /CS#, whichever happens later. All data is latched on the rising edge
of /WE or /CS#, whichever happens first. Refer to the appropriate timing
diagrams in the “AC Characteristics” section.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access
the manufacturer and devices codes, and determine whether or not a
sector is protected. Table 9 shows the address and data requirements.
This method is an alternative to that shown in Table 3, which is intended
for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock
cycles, followed by the autoselect command. The device then enters the
autoselect mode, and the system may read at any address any number
of times, without initiating another command sequence. A read cycle at
address XX00h retrieves the manufacturer code. A read cycle at
address XX01h returns the device code. A read cycle containing a sector
address (SA) and the address 02h returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to Table for valid sector addresses.
The system must write the reset command to exit the autoselect mode
and return to reading array data.
Byte Program Command Sequence
The device programs one byte of data for each program operation. The
command sequence requires four bus cycles, and is initiated by writing
two unlock write cycles, followed by the program set-up command. The
program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide
further controls or timings. The device automatically generates the
program pulses and verifies the programmed cell margin. Table 9 shows
the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the device then
returns to reading array data and addresses are no longer latched. The
system can determine the status of the program operation by using D7
or D6. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program
Algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. The Byte Program command
sequence should be reinitiated once the device has reset to reading
array data, to ensure data integrity. Programming is allowed in any
sequence and across sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt the operation and
set D5 to “1,” or cause the Data Polling algorithm to indicate the operation
was successful. However, a succeeding read will show that the data is
still “0”. Only erase operations can convert a “0” to a “1”.
PAGE 23
Issue 5.3 July 2001
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes to the
device faster than using the standard program command sequence. The
unlock bypass command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing the unlock
bypass command, 20h. The device then enters the unlock bypass mode.
A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this sequence
contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed
in the same manner. This mode dispenses with the initial two unlock
cycles required in the standard program command sequence, resulting
in faster total programming time. Table 9 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock By-pass Program and
Unlock Bypass Reset commands are valid. To exit the unlock bypass
mode, the system must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the data 90h; the
second cycle the data 00h. Addresses are don’t cares for both cycles.
The device then returns to reading array data.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command
sequence is initiated by writing two unlock cycles, followed by a set-up
command. Two additional unlock write cycles are then followed by the
chip erase command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or
timings during these operations. Table 9 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm
are ignored. Note that a hardware reset during the chip erase operation
immediately terminates the operation. The Chip Erase command
sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase operation by using D7,
D6 or D2. See “Write Operation Status” for information on these status
bits. When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer latched.
Figure 12 illustrates the algorithm for the erase operation. See the Erase
Program Operations tables in “AC Characteristics” for parameters, and
to Figure 4 for timing diagrams.
PAGE 24
Issue 5.3 July 2001
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command
sequence is initiated by writing two unlock cycles, followed by a set-up
command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector erase command.
Table 9 shows the address and data requirements for the sector erase
command sequence.
The device does not require the system to preprogram the memory prior
to erase. The Embedded Erase algorithm automatically programs and
verifies the sector for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of 50 µs
begins. During the time-out period, additional sector addresses and
sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from
one sector to all sectors. The time between these additional cycles must
be less than 50µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor
interrupts be disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the system need not
monitor D3. Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device to reading
array data. The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor D3 to determine if the sector erase timer has
timed out. (See the “D3: Sector Erase Timer” section.) The time-out
begins from the rising edge of the final /WE pulse in the command
sequence.
Once the sector erase operation has begun, only the Erase Suspend
command is valid. All other commands are ignored. Note that a
hardware reset during the sector erase operation immediately
terminates the operation. The Sector Erase command sequence should
be reinitiated once the device has returned to reading array data, to
ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched. The system can
determine the status of the erase operation by using D7, D6 or D2. (Refer
to “Write Operation Status” for information on these status bits.)
Figure 12 illustrates the algorithm for the erase operation. Refer to the
Erase/Program Operations tables in the “AC Characteristics” section for
parameters, and to Figure 4 for timing diagrams.
PAGE 25
Issue 5.3 July 2001
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector
erase operation and then read data from, or program data to, any sector
not selected for erasure. This command is valid only during the sector
erase operation, including the time-out period 50 µs during the sector
erase command sequence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded Program
algorithm. Writing the Erase Suspend command during the Sector Erase
time-out immediately terminates the time-out period and suspends the
erase operation. Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a sector erase
operation, the device requires a maximum of 20 µs to suspend the erase
operation. However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the
time-out period and suspends the erase operation.
After the erase operation has been suspended, the system can read
array data from or program data to any sector not selected for erasure.
(The device “erase suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply. Reading at any
address within erase-suspended sectors produces status data on D7–
D0. The system can use D7, or D6 and D2 together, to determine if a sect
or is actively erasing or is erase-suspended. See “Write Operation
Status” for information on these status bits.
After an erase-suspended program operation is complete, the system
can once again read array data within non-suspended sectors. The
system can deter mine the status of the program operation using the D7
or D6 status bits, just as in the standard program operation. See “Write
Operation Status” for more information.
The system may also write the autoselect command sequence when the
device is in the Erase Suspend mode. The device allows reading
autoselect codes even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend mode, and is
ready for another valid operation. See “Autoselect Command
Sequence” for more information.
The system must write the Erase Resume command (address bits are
“don’t care”) to exit the erase suspend mode and continue the sector
erase operation. Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after the device has
resumed erasing.
PAGE 26
Issue 5.3 July 2001
D7: Data Polling
The Data Polling bit, D7, indicates to the host system whether an
Embedded Algorithm is in progress or completed, or whether the device
is in Erase Suspend. Data Polling is valid after the rising edge of the final
/WE pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device outputs on D7 the
complement of the datum programmed to D7. This D7 status also
applies to programming during Erase Suspend. When the Embedded
Program algorithm is complete, the device outputs the datum
programmed to D7. The system must provide the program address to
read valid status information on D7. If a program address falls within a
protected sector, Data Polling on D7 is active for approximately 1 µs,
then the device returns to reading array data.
During the Embedded Erase algorithm, Data Polling produces a “0” on
D7. When the Embedded Erase algorithm is complete, or if the device
enters the Erase Suspend mode, Data Polling produces a “1” on D7. This
is analogous to the complement/true datum output described for the
Embedded Program algorithm: the erase function changes all the bits in
a sector to “1”; prior to this, the device outputs the “complement,” or “0.”
The system must provide an address within any of the sectors selected
for erasure to read valid status information on D7.
After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on D7 is active for approximately
100µs, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors that are
protected.
When the system detects D7 has changed from the complement to true
data, it can read valid data at D7–D0 on the following read cycles. This
is because D7 may change asynchronously with D0–D6 while Output
Enable (/OE) is asserted low. Figure 5, Data Polling Timings (During
Embedded Algorithms), in the “AC Characteristics” section illustrates
this.Table 10 shows the outputs for Data Polling on D7. Figure 15 shows
the Data Polling algorithm.
PAGE 27
Issue 5.3 July 2001
Write Operation Status
The device provides several bits to determine the status of a write
operation: D2, D3, D5, D6 and D7. Table 10 and the following
subsections describe the functions of these bits. D7 and D6 each offer
a method for determining whether a program or erase operation is
complete or in progress. These three bits are discussed first.
D6: Toggle Bit I
Toggle Bit I on D6 indicates whether an Embedded Program or Erase
algorithm is in progress or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be read at any address, and
is valid after the rising edge of the final /WE pulse in the command
sequence (prior to the program or erase operation), and during the
sector erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause D6 to toggle (The system
may use either /OE or/CS to control the read cycles). When the operation
is complete, D6 stops toggling.
After an erase command sequence is written, if all sectors selected for
erasing are protected, D6 toggles for approximately 100 µs, then returns
to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
The system can use D6 and D2 together to determine whether a sector
is actively erasing or is erase-suspended. When the device is actively
erasing (that is, the Embedded Erase algorithm is in progress), D6
toggles. When the device enters the Erase Suspend mode, D6 stops
toggling. However, the system must also use D2 to determine which
sectors are erasing or erase-suspended. Alternatively, the system can
use D7 (see the subsection on D7: Data Polling).
If a program address falls within a protected sector, D6 toggles for
approximately 1 µs after the program command sequence is written,
then returns to reading array data.
D6 also toggles during the erase-suspend-program mode, and stops
toggling once the Embedded Program algorithm is complete.
Table 10 shows the outputs for Toggle Bit I on D6. Figure 16 shows the
toggle bit algorithm in flowchart form, and the section “Reading Toggle
Bits D6/D2” explains the algorithm. Figure 6 in the “AC Characteristics”
section shows the toggle bit timing diagrams. Figure 7 shows the
differences between D2 and D6 in graphical form. See also the
subsection on D2: Toggle Bit II.
PAGE 28
Issue 5.3 July 2001
D2: Toggle Bit II
The “Toggle Bit II” on D2, when used with D6, indicates whether a
particular sector is actively erasing (that is, the Embedded Erase
algorithm is in progress), or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the final /WE pulse in the
command sequence.
D2 toggles when the system reads at addresses within those sectors
that have been selected for erasure. (The system may use either /OE or
/CS# to control the read cycles.) But D2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. D6, by comparison,
indicates whether the device is actively erasing, or is in Erase Suspend,
but cannot distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to Table
10 to compare outputs for D2 and D6.
Figure 16 shows the toggle bit algorithm in flowchart form, and the
section “Reading Toggle Bits D6/D2” explains the algorithm. See also
the D6: Toggle Bit I subsection. Figure 6 shows the toggle bit timing
diagram. Figure 7 shows the differences between D2 and D6 in graphical
form.
Reading Toggle Bits D6/D2
Refer to Figure 16 for the following discussion. Whenever the system
initially begins reading toggle bit status, it must read D7–D0 at least twice
in a row to determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit after the first read.
After the second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can read array
data on D7–D0 on the following read cycle.
However, if after the initial two read cycles, the system determines that
the toggle bit is still toggling, the system also should note whether the
value of D5 is high (see the section on D5). If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as D5 went high.If the toggle bit is no
longer toggling, the device has successfully completed the program or
erase operation. If it is still toggling, the device did not completed the
operation successfully, and the system must write the reset command
to return to reading array data.
The remaining scenario is that the system initially determines that the
toggle bit is toggling and D5 has not gone high. The system may continue
to monitor the toggle bit and D5 through successive read cycles,
determining the status as described in the previous paragraph.
Alternatively, it may choose to perform other system tasks. In this case,
the system must start at the beginning of the algorithm when it returns
to determine the status of the operation (top of Figure 16).
Table 10 shows the outputs for Toggle Bit I on D6. Figure 16 shows the
toggle bit algorithm. Figure 6 in the “AC Characteristics” section shows
the toggle bit timing diagrams. Figure 7 shows the differences between
D2 and D6 in graphical form. See also the subsection on D2: Toggle Bit
II.
PAGE 29
Issue 5.3 July 2001
D5: Exceeded Timing Limits
D5 indicates whether the program or erase time has exceeded a
specified internal pulse count limit. Under these conditions D5 produces
a “1.” This is a failure condition that indicates the program or erase cycle
was not successfully completed.
The D5 failure condition may appear if the system tries to program a “1”
to a location that is previously programmed to “0.” Only an erase
operation can change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has exceeded the
timing limits, D5 produces a “1” .
Under both these conditions, the system must issue the reset command
to return the device to reading array data.
D3: Sector Erase Timer
After writing a sector erase command sequence, the system may read
D3 to determine whether or not an erase operation has begun. (The
sector erase timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command. When the time-out
is complete, D3 switches from “0” to “1.” If the time between additional
sector erase commands from the system can be assumed to be less than
50 µs, the system need not monitor D3. See also the “Sector Erase
Command Sequence” section.
After the sector erase command sequence is written, the system should
read the status on D7 (Data Polling) or D6 (Toggle Bit I) to ensure the
device has accepted the command sequence, and then read D3. If D3
is “1”, the internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the erase
operation is complete.If D3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been accepted, the
system software should check the status of D3 prior to and following
each subsequent sector erase command. If D3 is high on the second
status check, the last command might not have been accepted. Table 10
shows the outputs for D3.
PAGE 30
Issue 5.3 July 2001
Operation
/CS#
/OE
/WE
/RESET
Addresses
D0~D7
Read
L
L
H
H
AIN
DOUT
Write
L
H
L
H
AIN
DIN
VCC+0.3V
X
X
VCC+0.3V
X
HIGH-Z
Output Disable
L
H
H
H
X
HIGH-Z
Hardware Reset
X
X
X
L
X
HIGH-Z
Sector/Sector
(1)
Block Protect
L
H
L
VID
SA, A6=L,
A1=H, A0=L
DIN, DOUT
Sector/Sector
(1)
Block Unprotect
L
H
L
VID
SA, A6=H,
A1=H, A0=L
DIN, DOUT
Temporary
Sector/Sector
Block Unprotect
X
X
X
VID
AIN
DIN
Standby
Legend:
L = Logic Low = VIL , H = Logic High = VIH , VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In,
DIN = Data In, DOUT = Data Out, SA = Sector Addresses.
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment.
See the “Sector/Sector Block Protection and Unprotection” section.
PAGE 31
Issue 5.3 July 2001
Tables
Table 1 - Device Bus Operations
Table 2 - Sector Address Table
Sector
A21
A20
A19
A18
A17
A16
Address Range
SA0
0
0
0
0
0
0
000000~00FFFF
SA1
0
0
0
0
0
1
010000~01FFFF
SA2
0
0
0
0
1
0
020000~02FFFF
SA3
0
0
0
0
1
1
030000~03FFFF
SA4
0
0
0
1
0
0
040000~04FFFF
SA5
0
0
0
1
0
1
050000~05FFFF
SA6
0
0
0
1
1
0
060000~06FFFF
SA7
0
0
0
1
1
1
070000~07FFFF
SA8
0
0
1
0
0
0
080000~08FFFF
SA9
0
0
1
0
0
1
090000~09FFFF
SA10
0
0
1
0
1
0
0A0000~0AFFFF
SA11
0
0
1
0
1
1
0B0000~0BFFFF
SA12
0
0
1
1
0
0
0C0000~0CFFFF
SA13
0
0
1
1
0
1
0D0000~0DFFFF
SA14
0
0
1
1
1
0
0E0000~0EFFFF
SA15
0
0
1
1
1
1
0F0000~0FFFFF
SA16
0
1
0
0
0
0
100000~10FFFF
SA17
0
1
0
0
0
1
110000~11FFFF
SA18
0
1
0
0
1
0
120000~12FFFF
SA19
0
1
0
0
1
1
130000~13FFFF
SA20
0
1
0
1
0
0
140000~14FFFF
SA21
0
1
0
1
0
1
150000~15FFFF
SA22
0
1
0
1
1
0
160000~16FFFF
SA23
0
1
0
1
1
1
170000~17FFFF
SA24
0
1
1
0
0
0
180000~18FFFF
SA25
0
1
1
0
0
1
190000~19FFFF
SA26
0
1
1
0
1
0
1A0000~1AFFFF
SA27
0
1
1
0
1
1
1B0000~1BFFFF
SA28
0
1
1
1
0
0
1C0000~1CFFFF
SA29
0
1
1
1
0
1
1D0000~1DFFFF
SA30
0
1
1
1
1
0
1E0000~1EFFFF
SA31
0
1
1
1
1
1
1F0000~1FFFFF
Continued overleaf.
PAGE 32
Issue 5.3 July 2001
Table 2 - Sector Address Table (continued)
Sector
A21
A20
A19
A18
A17
A16
Address Range
SA32
1
0
0
0
0
0
200000~20FFFF
SA33
1
0
0
0
0
1
210000~21FFFF
SA34
1
0
0
0
1
0
220000~02FFFF
SA35
1
0
0
0
1
1
230000~23FFFF
SA36
1
0
0
1
0
0
240000~24FFFF
SA37
1
0
0
1
0
1
250000~25FFFF
SA38
1
0
0
1
1
0
260000~26FFFF
SA39
1
0
0
1
1
1
070000~27FFFF
SA40
1
0
1
0
0
0
280000~28FFFF
SA41
1
0
1
0
0
1
290000~29FFFF
SA42
1
0
1
0
1
0
2A0000~2AFFFF
SA43
1
0
1
0
1
1
2B0000~2BFFFF
SA44
1
0
1
1
0
0
2C0000~2CFFFF
SA45
1
0
1
1
0
1
2D0000~2DFFFF
SA46
1
0
1
1
1
0
2E0000~2EFFFF
SA47
1
0
1
1
1
1
2F0000~2FFFFF
SA48
1
1
0
0
0
0
300000~30FFFF
SA49
1
1
0
0
0
1
310000~31FFFF
SA50
1
1
0
0
1
0
320000~32FFFF
SA51
1
1
0
0
1
1
330000~33FFFF
SA52
1
1
0
1
0
0
340000~34FFFF
SA53
1
1
0
1
0
1
350000~35FFFF
SA54
1
1
0
1
1
0
360000~36FFFF
SA55
1
1
0
1
1
1
370000~37FFFF
SA56
1
1
1
0
0
0
380000~38FFFF
SA57
1
1
1
0
0
1
390000~39FFFF
SA58
1
1
1
0
1
0
3A0000~3AFFFF
SA59
1
1
1
0
1
1
3B0000~3BFFFF
SA60
1
1
1
1
0
0
3C0000~3CFFFF
SA61
1
1
1
1
0
1
3D0000~3DFFFF
SA62
1
1
1
1
1
0
3E0000~3EFFFF
SA63
1
1
1
1
1
1
3F0000~3FFFFF
PAGE 33
Issue 5.3 July 2001
Table 3 - Autoselect Codes (High Voltage Method)
Description
Sector
Protection
Verification
/CS#
/OE
L
L
/WE
H
A20
to
A16
SA
A15
to
A10
X
A9
VID
A8
to
A7
X
A6
L
A5
to
A2
X
A1
H
A0
L
D7 to D0
01h
(protected)
00h
(unprotected)
L = Logic Low = VIL , H = Logic High = VIH , SA = Sector Address, X = Don’t care.
Table 4 - Sector Block Addresses for Protection/Unprotection.
PAGE 34
Sector/Sector Block
A21~A16
Sector/Sector Block Size
SA0
000000
64 Kbytes
SA1~SA3
000001,000010,000011
192 (3 x 64) Kbytes
SA4~SA7
000100, 000101, 000110, 000111
256 (4 x 64) Kbytes
SA8~SA11
001000, 001001, 001010, 001011
256 (4 x 64) Kbytes
SA12~SA15
001100, 001101, 001110, 001111
256 (4 x 64) Kbytes
SA16~SA19
010000, 010001, 010010, 010011
256 (4 x 64) Kbytes
SA20~SA23
010100, 010101, 010110, 010111
256 (4 x 64) Kbytes
SA24~SA27
011000, 011001, 011010, 011011
256 (4 x 64) Kbytes
SA28~SA31
011100, 011101, 011110, 011111
256 (4 x 64) Kbytes
SA32~SA35
100000, 100001, 100010, 100011
256 (4 x 64) Kbytes
SA36~SA39
100100, 100101, 100110, 100111
256 (4 x 64) Kbytes
SA40~SA43
101000, 101001, 101010, 101011
256 (4 x 64) Kbytes
SA44~SA47
101100, 101101, 101110, 101111
256 (4 x 64) Kbytes
SA48~SA51
110000, 110001, 110010, 110011
256 (4 x 64) Kbytes
SA52~SA55
110100, 110101, 110110, 110111
256 (4 x 64) Kbytes
SA56~SA59
111000, 11101, 111010, 111011
256 (4 x 64) Kbytes
SA60~SA62
111100, 111101, 111110
192 (3 x 64) Kbytes
SA63
111111
64 Kbytes
Issue 5.3 July 2001
Table 5 - CFI Query Identification String
Addresses
Data
10h
51h
11h
52h
12h
59h
13h
02h
14h
00h
15h
40h
16h
00h
17h
00h
18h
00h
19h
00h
1Ah
00h
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address For Primary Extended Table
Alternate OEM Command Set (00h = None Exists)
Address for Alternate OEM Extended Table (00h = None Exists)
Table 6 - System Interface String
Addresses
Data
Description
1Bh
27h
VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt
1Ch
36h
VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt
1Dh
00h
VPP Min. voltage (00h = no VPP pin present)
1Eh
00h
VPP Max. voltage (00h = no VPP pin present)
1Fh
04h
Typical timeout per single byte/word write 2 µs
20h
00h
Typical timeout for Min. size buffer write 2 µs (00h = not supported)
21h
0Ah
Typical timeout per individual block erase 2 N ms
22h
00h
Typical timeout for full chip erase 2 ms (00h = not supported)
23h
05h
Max. timeout for byte/word write 2 times typical
24h
00h
Max. timeout for buffer write 2 times typical
25h
04h
Max. timeout per individual block erase 2 times typical
26h
00h
Max. timeout for full chip erase 2 times typical (00h = not supported)
PAGE 35
N
N
N
N
N
N
N
Issue 5.3 July 2001
Table 7 - Device Geometry Definition
PAGE 36
Addresses
Data
Description
27h
16h
Device Size = 2 byte
28h
00h
29h
00h
FLASH Device Interface Description
(refer to CFI Publication 100)
2Ah
00h
2Bh
00h
Max. Number of Byte in multi-byte write = 2
(00h = Not supported)
2Ch
01h
Number of Erase Block Regions within Device.
2Dh
3Fh
2Eh
00h
2Fh
00h
30h
01h
31h
00h
32h
00h
33h
00h
34h
00h
35h
00h
36h
00h
37h
00h
38h
00h
39h
00h
3Ah
00h
3Bh
00h
3Ch
00h
N
N
Erase Block Region 1 Information
(Refer to CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Issue 5.3 July 2001
Table 8 - Primary Vendor Specific Extended Query
Addresses
Data
40h
50h
41h
52h
42h
49h
43h
31h
Major version number, ASCII
44h
30h
Minor version number, ASCII
45h
01h
Address Sensitive Unlock : 0 = Required, 1 = Not Required
46h
02h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
01h
Sector Protect : 0 = Not Supported, X = Number of Sectors in Group.
48h
04h
Sector Temporary Unprotect : 04 = Supported
49h
04h
Sector Protect/Unprotect Scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode.
4Ah
20h
Simultaneous Operation : 20 = Not Supported
4Bh
00h
Burst Mode Type : 00 = Not Supported, 01 = Supported
4Ch
00h
Page Mode Type :
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
PAGE 37
Description
Query-unique ASCII string “PRI”
Issue 5.3 July 2001
Command
(1)
Sequence
(5)
Read
Cycles.
Table 9 - Command Definitions
Bus Cycles
First
Second
Addr Data Addr Data
1
RA
RD
Reset
1
XXX
F0
Auto~
(9)
(7) SPV
select
4
Byte Program
4
XXX
AA
XXX
Unlock Bypass
3
XXX
AA
Unlock Bypass
(10)
Program
2
XXX
Unlock Bypass
(11)
Reset
2
Chip Erase
(6)
XXX
XXX
Third
Addr
Fourth
90
55
XXX
A0
XXX
55
XXX
20
A0
PA
PD
XXX
90
XXX
00
6
XXX
AA
XXX
55
XXX
Sector Erase
6
XXX
AA
XXX
55
XXX
Erase
(12)
Suspend
1
XXX
B0
Erase
(13)
Resume
1
XXX
30
1
XXX
98
CFI Query
(14)
XXX
55
XXX
Fifth
Sixth
Data Addr Data Addr Data Addr Data
0XXXXX or
2XXXXX
AA
(2-4)
00
(SA)
X02
01
PA
PD
80
XXX
AA
XXX
55
XXX
10
80
XXX
AA
XXX
55
SA
30
Legend:
X
RA
RD
PA
=
=
=
=
Don’t care
Address of the memory location to be read.
Data read from location RA during read operation.
Address of the memory location to be programmed. Addresses are latched on the falling edge of the
/WE or /CS# pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of /WE or /CS# pulse.
SA = Address of the sector to be erased or verified. Address bits A21–A16 uniquely select any sector.
SPV = Sector Protect Verify.
Notes:
1. See Table 1 for descriptions of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Address bits are don’t care for unlock and command cycles, except when PA or SA is required.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode when the device is in the autoselect mode or if
D5 goes high.
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. In the third and fourth cycles of the command sequence, set A21 to 0.
9. In the third cycle of the command sequence, address bit A21 must be set to 0 if verifying sectors 0–31, or
to 1 if verifying sectors 32–64. The data in the fourth cycle is 00h for an unprotected sector/sector block
and 01h for a protected sector/sector block.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
Unlock Bypass mode.
12. The system may read and program functions in non-erasing sectors, or enter the autoselect mode, when in
the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
13. The Erase Resume command is valid only during the Erase Suspend mode.
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
PAGE 38
Issue 5.3 July 2001
Table 10 - Write Operation Status
Operation
Embedded Program
Standard Algorithm
Mode
Embedded Erase Algorithm
Reading Within Erase
Suspended Sector
Erase
Suspend Reading Within Non-Erase
Suspended Sector
Mode
Erase-Suspend-Program
(2)
D7
D6
D5
(1)
D3
(2)
D2
D7
Toggle
0
N/A
No
Toggle
0
Toggle
0
1
Toggle
1
No Toggle
0
N/A
Toggle
Data
Data
Data
Data
Data
D7
Toggle
0
N/A
N/A
Notes:
1. D5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum
timing limits. See “D5: Exceeded Timing Limits” for more information.
2. D7 and D2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
PAGE 39
Issue 5.3 July 2001
Package Details
Package Details
PUMA 84 - Plastic 84 ‘J’ Leaded Package.
30.35 (1.195) sq.
0.90
(0.035)
typ.
30.10 (1.185) sq.
0.46
(0.018) typ.
29.20 (1.150)
28.20 (1.110)
1.27
(0.050) typ.
5.08
(0.200)
max
PAGE 40
Issue 5.3 July 2001
PUMA 84FV256006I - 90
Speed
Temperature Range
90 = 90ns
12 = 120ns
15 = 150ns
Blank = Commercial
I = Industrial
Memory Organisation
256006 = configurable as
8M x 32, 16M x 16 or
32M x 8
Power Consumption
V = 3.3V + 10% VCC
Technology
F = FLASH
Package
PUMA 84 = Plastic 84 ‘J’ Leaded
Package
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written
approval of a company director.
PAGE 41
Issue 5.3 July 2001
Ordering Information
Ordering Information
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