MRP01881503

MRP01881503
Not recommended for new designs. Please use SST39VF1601C
and SST39VF3201B.
16 Mbit / 32 Mbit / (x16) Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
The SST39VF1601/1602 and SST39VF3201/3202 devices are 1M x16 and 2M
x16, respectively, CMOS Multi-Purpose Flash Plus (MPF+) manufactured with
SST's proprietary, high performance CMOS SuperFlash technology. The splitgate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF1601/1602/
3201/3202 write (Program or Erase) with a 2.7-3.6V power supply. These devices
conforms to JEDEC standard pinouts for x16 memories.
Features
• Organized as 1M x16: SST39VF1601/1602
2M x16: SST39VF3201/3202
• Security-ID Feature
• Single Voltage Read and Write Operations
• Fast Read Access Time:
– SST: 128 bits; User: 128 bits
– 2.7-3.6V
– 70 ns
• Superior Reliability
• Latched Address and Data
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Fast Erase and Word-Program:
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST39VF1602/3202
– Bottom Block-Protection (bottom 32 KWord)
for SST39VF1601/3201
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
©2011 Silicon Storage Technology, Inc.
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
• All devices are RoHS compliant
www.microchip.com
DS25028A
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Product Description
The SST39VF160x and SST39VF320x devices are 1M x16 and 2M x16, respectively, CMOS MultiPurpose Flash Plus (MPF+) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability
and manufacturability compared with alternate approaches. The SST39VF160x/320x write (Program
or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16
memories.
Featuring high performance Word-Program, the SST39VF160x/320x devices provide a typical WordProgram time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of
Program operation. To protect against inadvertent write, they have on-chip hardware and Software
Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is
rated at greater than 100 years.
The SST39VF160x/320x devices are suited for applications that require convenient and economical
updating of program, configuration, or data memory. For all system applications, they significantly
improve performance and reliability, while lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for program, data, and configuration storage
applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39VF160x/320x are offered in 48-lead
TSOP and 48-ball TFBGA packages. See Figures 2 and 3 for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25028A
2
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Block Diagram
X-Decoder
Memory Address
SuperFlash
Memory
Address Buffer Latches
Y-Decoder
CE#
OE#
WE#
WP#
RESET#
I/O Buffers and Data Latches
Control Logic
DQ15 - DQ0
1223 B1.0
Figure 1: Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25028A
3
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Pin Assignment
SST39VF3201/3202
SST39VF160x/320x
SST39VF1601/1602
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
NC
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RST#
NC
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard Pinout
Top View
Die Up
1223 48-tsop P01.4
Figure 2: Pin Assignments for 48-lead TSOP
TOP VIEW (balls facing down)
TOP VIEW (balls facing down)
SST39VF1601/1602
6
5
4
3
2
1
A13 A12 A14
A9
A8
WE# RST#
A10
NC
NC WP# A18
A7
A17
A6
SST39VF3201/3202
A15 A16 NC DQ15 VSS
A11 DQ7 DQ14 DQ13 DQ6
A19 DQ5 DQ12 VDD DQ4
NC DQ2 DQ10 DQ11 DQ3
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
1223 48-tfbga B3K P02.0
6
5
4
3
2
1
A13 A12 A14
A15 A16 NC DQ15 VSS
A9
A8
A10
A11 DQ7 DQ14 DQ13 DQ6
WE# RST#
NC
A19 DQ5 DQ12 VDD DQ4
NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3
A7
A17
A6
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
1223 48-tfbga B3K P02a.2
Figure 3: pin assignments for 48-ball TFBGA
©2011 Silicon Storage Technology, Inc.
DS25028A
4
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Table 1: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply
To provide power supply voltage: 2.7-3.6V
VSS
Ground
NC
No Connection
Unconnected pins.
T1.2 25028
1. AMS = Most significant address
AMS = A19 for SST39VF1601/1602, and A20 for SST39VF3201/3202
©2011 Silicon Storage Technology, Inc.
DS25028A
5
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF160x/320x also have the Auto Low Power mode which puts the device in a near
standby mode after data has been accessed with a valid Read operation. This reduces the IDD active
read current from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD
active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition used to initiate another Read cycle, with
no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with
CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF160x/320x is controlled by CE# and OE#, both have to be low for
the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details (Figure 4).
Word-Program Operation
The SST39VF160x/320x are programmed on a word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program operation is accomplished in three steps.
The first step is the three-byte load sequence for Software Data Protection. The second step is to load
word address and word data. During the Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation,
once initiated, will be completed within 10 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to
perform additional tasks. Any commands issued during the internal Program operation are ignored.
During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF160x/320x offer both Sector-Erase and Block-Erase mode. The
sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on
uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The
Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the
falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of
the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase
operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11
©2011 Silicon Storage Technology, Inc.
DS25028A
6
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
for timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or
Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with EraseSuspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF160x/320x provide a Chip-Erase operation, which allows the user to erase the entire
memory array to the “1” state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid
read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence,
WP# should be statically held high or low.
Write Operation Status Detection
The SST39VF160x/320x provide two software means to detect the completion of a Write (Program or
Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after
the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
©2011 Silicon Storage Technology, Inc.
DS25028A
7
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Data# Polling (DQ7)
When the SST39VF160x/320x are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce
true data. Note that even though DQ7 may have valid data immediately following the completion of an internal
Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in
subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt
to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 7 for Data# Polling timing diagram and Figure 21 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check
whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status
bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart.
Table 2: Write Operation Status
Status
Normal Operation
Erase-Suspend Mode
DQ7
DQ6
DQ2
DQ7#
Toggle
No Toggle
Standard Erase
0
Toggle
Toggle
Read from Erase-Suspended Sector/Block
1
1
Toggle
Read from Non- Erase-Suspended Sector/Block
Data
Data
Data
Program
DQ7#
Toggle
N/A
Standard Program
T2.0 25028
Note: DQ7 and DQ2 require a valid address when reading status information.
Data Protection
The SST39VF160x/320x provide both hardware and software features to protect nonvolatile data from
inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
©2011 Silicon Storage Technology, Inc.
DS25028A
8
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Hardware Block Protection
The SST39VF1602/3202 support top hardware block protection, which protects the top 32 KWord
block of the device. The SST39VF1601/3201 support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table
3. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program
and Erase operations on that block.
Table 3: Boot Block Address Ranges
Product
Address Range
Bottom Boot Block
SST39VF1601/3201
000000H-007FFFH
Top Boot Block
SST39VF1602
0F8000H-0FFFFFH
SST39VF3202
1F8000H-1FFFFFH
T3.0 25028
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#
is driven high before a valid Read can take place (see Figure 16).
The Erase or Program operation that has been interrupted needs to be reinitiated after the device
resumes normal operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF160x/320x provide the JEDEC approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the
three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped
with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode
within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command
sequence.
Common Flash Memory Interface (CFI)
The SST39VF160x/320x also contain the CFI information to describe the characteristics of the device.
In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID
entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the
device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7
through 10. The system must write the CFI Exit command to return to Read mode from the CFI Query
mode.
©2011 Silicon Storage Technology, Inc.
DS25028A
9
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Product Identification
The Product Identification mode identifies the devices as the SST39VF1601, SST39VF1602,
SST39VF3201, or SST39VF3202, and manufacturer as SST. This mode may be accessed software
operations. Users may use the Software Product Identification operation to identify the part (i.e., using
the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 22 for the
Software ID Entry command sequence flowchart.
Table 4: Product Identification
Address
Data
0000H
BFH
SST39VF1601
0001H
234BH
SST39VF1602
0001H
234AH
SST39VF3201
0001H
235BH
SST39VF3202
0001H
235AH
Manufacturer’s ID
Device ID
T4.2 25028
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 6 for software command codes, Figure 14 for timing waveform, and Figures 22 and 23 for flowcharts.
Security ID
The SST39VF160x/320x devices offer a 256-bit Security ID space. The Secure ID space is divided into
two 128-bit segments - one factory programmed segment and one user programmed segment. The
first segment is programmed and locked at SST with a random 128-bit number. The user segment is
left un-programmed for the customer to program as desired.
To program the user segment of the Security ID, the user must use the Security ID Word-Program
command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once
this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables
any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID
command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details.
©2011 Silicon Storage Technology, Inc.
DS25028A
10
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Operations
Table 5: Operation Modes Selection
Mode
CE#
OE#
WE#
DQ
Address
Read
VIL
VIL
VIH
DOUT
AIN
Program
VIL
VIH
VIL
DIN
AIN
VIH
VIL
X1
Sector or block address,
XXH for Chip-Erase
Erase
VIL
Standby
VIH
X
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
Product Identification
Software Mode
See Table 6
T5.0 25028
1. X can be VIL or VIH, but no other value.
Table 6: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
Addr1
Addr1
Data2
3rd Bus
Write Cycle
4th Bus
Write Cycle
Data2 Addr1 Data2 Addr1
Data2
5th Bus
Write Cycle
Addr1
6th Bus
Write Cycle
Data2 Addr1 Data2
Word-Program
5555H
AAH
2AAAH
55H
5555H
A0H
WA3
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555
H
AAH
2AAAH
55H
SAX4
30H
Block-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555
H
AAH
2AAAH
55H
BAX4
50H
Chip-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555
H
AAH
2AAAH
55H
5555
H
10H
Erase-Suspend
XXXX
H
B0H
Erase-Resume
XXXX
H
30H
Query Sec ID5
5555H
AAH
2AAAH
55H
5555H
88H
User Security ID
Word-Program
5555H
AAH
2AAAH
55H
5555H
A5H
WA6
Data
User Security ID
Program Lock-Out
5555H
AAH
2AAAH
55H
5555H
85H
XXH6
0000
H
Software ID
Entry7,8
5555H
AAH
2AAAH
55H
5555H
90H
CFI Query Entry
5555H
AAH
2AAAH
55H
5555H
98H
Software ID
Exit9,10/CFI Exit/
Sec ID Exit
5555H
AAH
2AAAH
55H
5555H
F0H
Software ID
Exit9,10
/CFI Exit/Sec ID
Exit
XXH
F0H
Data
T6.6 25028
1. Address format A14-A0 (Hex).
Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST39VF1601/1602,
Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST39VF3201/3202,
©2011 Silicon Storage Technology, Inc.
DS25028A
11
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000010H to 000017H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF1601 Device ID = 234BH, is read with A0 = 1,
SST39VF1602 Device ID = 234AH, is read with A0 = 1,
SST39VF3201 Device ID = 235BH, is read with A0 = 1,
SST39VF3202 Device ID = 235AH, is read with A0 = 1,
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)
using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are
from 000000H-000007H and 000010H-000017H.
Table 7: CFI Query Identification String1 for SST39VF160x/320x
Address
Data
10H
0051H
11H
0052H
12H
0059H
13H
0001H
14H
0007H
15H
0000H
16H
0000H
17H
0000H
18H
0000H
19H
0000H
1AH
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T7.1 25028
1. Refer to CFI publication 100 for more details.
©2011 Silicon Storage Technology, Inc.
DS25028A
12
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Table 8: System Interface Information for SST39VF160x/320x
Address
Data
1BH
0027H
Data
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min. (00H = no VPP pin)
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0003H
Typical time out for Word-Program 2N µs (23 = 8 µs)
20H
0000H
Typical time out for min. size buffer program 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H
0005H
Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H
0001H
Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H
0000H
Maximum time out for buffer program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32
ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T8.3 25028
Table 9: Device Geometry Information for SST39VF1601/1602
Address
Data
27H
0015H
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
28H
0001H
Flash Device Interface description; 0001H = x16-only asynchronous interface
29H
0000H
2AH
0000H
Data
Maximum number of byte in multi-byte write = 2N (00H = not supported)
2BH
0000H
2CH
0002H
Number of Erase Sector/Block sizes supported by device
2DH
00FFH
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH
0001H
y = 511 + 1 = 512 sectors (01FF = 511
2FH
0010H
30H
0000H
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H
001FH
Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H
0000H
y = 31 + 1 = 32 blocks (001F = 31)
33H
0000H
34H
0001H
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.0 25028
©2011 Silicon Storage Technology, Inc.
DS25028A
13
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Table 10:Device Geometry Information for SST39VF3201/3202
Address
Data
27H
0016H
Device size = 2N Bytes (16H = 22; 222 = 4 MByte)
Data
28H
0001H
Flash Device Interface description; 0001H = x16-only asynchronous interface
29H
0000H
2AH
0000H
2BH
0000H
Maximum number of byte in multi-byte write = 2N (00H = not supported)
2CH
0002H
Number of Erase Sector/Block sizes supported by device
2DH
00FFH
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH
0003H
y = 1023 + 1 = 1024 (03FFH = 1023)
2FH
0010H
30H
0000H
z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H
003FH
Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H
0000H
y = 63 + 1 = 64 blocks (003FH = 63)
33H
0000H
34H
0001H
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T10.2 25028
©2011 Silicon Storage Technology, Inc.
DS25028A
14
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest
information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 11:Operating Range
Range
Commercial
Industrial
Ambient Temp
VDD
0°C to +70°C
2.7-3.6V
-40°C to +85°C
2.7-3.6V
T11.1 25028
Table 12:AC Conditions of Test1
Input Rise/Fall Time
Output Load
5ns
CL = 30 pF
T12.1 25028
1. See Figures 18 and 19
©2011 Silicon Storage Technology, Inc.
DS25028A
15
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Table 13:DC Operating Characteristics VDD = 2.7-3.6V1
Limits
Symbol Parameter
IDD
Power Supply Current
Max
Units
Read3
Program and Erase
Standby VDD Current
Auto Low Power
18
35
20
20
mA
mA
µA
µA
ILI
ILIW
Input Leakage Current
Input Leakage Current
on WP# pin and RST#
1
10
µA
µA
ILO
VIL
VILC
VIH
VIHC
VOL
VOH
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
10
0.8
0.3
µA
V
V
V
V
V
V
ISB
IALP
Min
0.7VDD
VDD-0.3
0.2
VDD-0.2
Test Conditions
Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
CE#=VIL, OE#=WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
CE#=VIHC, VDD=VDD Max
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
VIN=GND to VDD, VDD=VDD Max
WP#=GND to VDD or RST#=GND to
VDD
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VDD=VDD Max
VDD=VDD Max
VDD=VDD Max
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
T13.8 25028
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 18
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
Table 14:Recommended System Power-up Timings
Symbol
TPU-READ1
TPU-WRITE1
Parameter
Power-up to Read Operation
Power-up to Program/Erase Operation
Minimum
100
100
Units
µs
µs
T14.0 25028
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 15:Capacitance (TA = 25°C, f=1 MHz, other pins open)
Parameter
CI/O1
CIN1
Description
I/O Pin Capacitance
Input Capacitance
Test Condition
VI/O = 0V
VIN = 0V
Maximum
12 pF
6 pF
T15.0 25028
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 16:Reliability Characteristics
Symbol
NEND1,2
TDR1
ILTH1
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
10,000
Units
Cycles
Test Method
JEDEC Standard A117
100
100 + IDD
Years
mA
JEDEC Standard A103
JEDEC Standard 78
T16.2 25028
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
©2011 Silicon Storage Technology, Inc.
DS25028A
16
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
AC Characteristics
Table 17:Read Cycle Timing Parameters VDD = 2.7-3.6V
Symbol
Parameter
Min
Max
Units
TRC
Read Cycle Time
TCE
Chip Enable Access Time
70
70
ns
ns
TAA
Address Access Time
70
ns
TOE
Output Enable Access Time
35
ns
1
CE# Low to Active Output
0
ns
TOLZ1
OE# Low to Active Output
0
ns
TCHZ1
CE# High to High-Z Output
20
ns
TOHZ1
OE# High to High-Z Output
20
ns
TCLZ
TOH
1
Output Hold from Address Change
TRP1
TRHR
1
TRY1,2
0
ns
RST# Pulse Width
500
ns
RST# High before Read
50
RST# Pin Low to Read Mode
ns
20
µs
T17.3 25028
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.
This parameter does not apply to Chip-Erase operations.
Table 18:Program/Erase Cycle Timing Parameters
Symbol
Parameter
Min
Max
Units
TBP
Word-Program Time
TAS
Address Setup Time
0
10
ns
µs
TAH
Address Hold Time
30
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
40
ns
TWP
WE# Pulse Width
40
ns
TWPH1
WE# Pulse Width High
30
ns
1
CE# Pulse Width High
30
ns
TDS
Data Setup Time
30
ns
TDH1
TIDA1
Data Hold Time
0
Software ID Access and Exit Time
150
ns
TSE
Sector-Erase
25
ms
TBE
Block-Erase
25
ms
TSCE
Chip-Erase
50
TCPH
ns
ms
T18.1 25028
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
©2011 Silicon Storage Technology, Inc.
DS25028A
17
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
TRC
TAA
ADDRESS AMS-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
TCHZ
TOH
TCLZ
HIGH-Z
HIGH-Z
DQ15-0
DATA VALID
Note:
DATA VALID
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
1223 F03.3
Figure 4: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESS AMS-0
2AAA
5555
ADDR
TDH
TWP
WE#
TAS
TWPH
TDS
OE#
TCH
CE#
TCS
DQ15-0
Note:
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F04.4
Figure 5: WE# Controlled Program Cycle Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25028A
18
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
ADDRESS AMS-0
2AAA
5555
ADDR
TAH
TDH
TCP
CE#
TAS
TCPH
TDS
OE#
TCH
WE#
TCS
DQ15-0
Note:
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F05.4
Figure 6: CE# Controlled Program Cycle Timing Diagram
ADDRESS AMS-0
TCE
CE#
TOES
TOEH
OE#
TOE
WE#
DATA
DQ7
Note:
DATA#
DATA#
DATA
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
1223 F06.3
Figure 7: Data# Polling Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25028A
19
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
ADDRESS AMS-0
TCE
CE#
TOEH
TOES
TOE
OE#
WE#
DQ6 and DQ2
TWO READ CYCLES
WITH SAME OUTPUTS
Note:
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
1223 F07.4
Figure 8: Toggle Bits Timing Diagram
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
ADDRESS AMS-0
5555
2AAA
5555
5555
2AAA
5555
CE#
OE#
TWP
WE#
DQ15-0
Note:
XXAA
XX55
XX80
XXAA
XX55
XX10
SW0
SW1
SW2
SW3
SW4
SW5
This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
WP# must be held in proper logic state (VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F08.5
Figure 9: WE# Controlled Chip-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25028A
20
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
TBE
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS AMS-0
5555
2AAA
5555
5555
2AAA
BAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
BAX = Block Address
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F09.5
Figure 10:WE# Controlled Block-Erase Timing Diagram
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS AMS-0
5555
2AAA
5555
5555
2AAA
SAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
SAX = Sector Address
AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F10.5
Figure 11:WE# Controlled Sector-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25028A
21
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Three-Byte Sequence for Software ID Entry
5555
ADDRESS A14-0
2AAA
5555
0000
0001
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
Note:
TAA
XXAA
XX55
XX90
SW0
SW1
SW2
00BF
Device ID
Device ID = 234BH for 39VF1601, 234AH for 39VF1602, 235BH for 39VF3201, and 235AH for 39VF3202,
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1
Figure 12:Software ID Entry and Read
Three-Byte Sequence for CFI Query Entry
5555
ADDRESS A14-0
2AAA
5555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
Note:
TAA
XXAA
XX55
XX98
SW0
SW1
SW2
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F12.1
Figure 13:CFI Query Entry and Read
©2011 Silicon Storage Technology, Inc.
DS25028A
22
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
ADDRESS A14-0
2AAA
XXAA
DQ15-0
5555
XX55
XXF0
TIDA
CE#
OE#
TWP
WE#
TWHP
SW0
Note:
SW1
SW2
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F13.0
Figure 14:Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS AMS-0
5555
2AAA
5555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX88
SW0
SW1
SW2
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602 and A20 for SST39VF3201/3202
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value.
1223 F20.2
Figure 15:Sec ID Entry
©2011 Silicon Storage Technology, Inc.
DS25028A
23
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
TRP
RST#
CE#/OE#
TRHR
1223 F22.1
Figure 16:RST# Timing Diagram (When no internal operation is in progress)
TRP
RST#
TRY
CE#/OE#
End-of-Write Detection
(Toggle-Bit)
1223 F23.0
Figure 17:RST# Timing Diagram (During Program or Erase operation)
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1223 F14.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a
logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5
VDD). Input rise and fall times (10%  90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 18:AC Input/Output Reference Waveforms
TO TESTER
TO DUT
CL
1223 F15.0
Figure 19:A Test Load Example
©2011 Silicon Storage Technology, Inc.
DS25028A
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16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
1223 F16.0
X can be VIL or VIH, but no other value
Figure 20:Word-Program Algorithm
©2011 Silicon Storage Technology, Inc.
DS25028A
25
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Internal Timer
Toggle Bit
Data# Polling
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Wait TBP,
TSCE, TSE
or TBE
Read word
Read DQ7
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data
Yes
No
Does DQ6
match
Program/Erase
Completed
Yes
Program/Erase
Completed
1223 F17.0
Figure 21:Wait Options
©2011 Silicon Storage Technology, Inc.
DS25028A
26
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX98H
Address: 5555H
Load data: XX88H
Address: 5555H
Load data: XX90H
Address: 5555H
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Sec ID
Read Software ID
X can be VIL or VIH, but no other value
1223 F21.0
Figure 22:Software ID/CFI Entry Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS25028A
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08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Wait TIDA
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait TIDA
Return to normal
operation
X can be VIL or VIH, but no other value
1223 F18.1
Figure 23:Software ID/CFI Exit Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS25028A
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16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Address: SAX
Load data: XX50H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
X can be VIL or VIH, but no other value
1223 F19.0
Figure 24:Erase Command Sequence
©2011 Silicon Storage Technology, Inc.
DS25028A
29
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16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Product Ordering Information
SST
39 VF
XX XX
1601 XXXX -
70 XX -
4C
XX
-
EKE
XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
E = TSOP (type1, die up, 12mm x 20mm)
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
160 = 16 Mbit
320 = 32 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
©2011 Silicon Storage Technology, Inc.
DS25028A
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16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Valid Combinations for SST39VF1601
SST39VF1601-70-4C-EKE
SST39VF1601-90-4C-EKE
SST39VF1601-70-4I-EKE
SST39VF1601-90-4I-EKE
SST39VF1601-70-4C-B3KE
SST39VF1601-90-4C-B3KE
SST39VF1601-70-4I-B3KE
SST39VF1601-90-4I-B3KE
Valid Combinations for SST39VF1602
SST39VF1602-70-4C-EKE
SST39VF1602-90-4C-EKE
SST39VF1602-70-4I-EKE
SST39VF1602-90-4I-EKE
SST39VF1602-70-4C-B3KE
SST39VF1602-90-4C-B3KE
SST39VF1602-70-4I-B3KE
SST39VF1602-90-4I-B3KE
Valid Combinations for SST39VF3201
SST39VF3201-70-4C-EKE
SST39VF3201-90-4C-EKE
SST39VF3201-70-4I-EKE
SST39VF3201-90-4I-EKE
SST39VF3201-70-4C-B3KE
SST39VF3201-90-4C-B3KE
SST39VF3201-70-4I-B3KE
SST39VF3201-90-4I-B3KE
Valid Combinations for SST39VF3202
SST39VF3202-70-4C-EKE
SST39VF3202-90-4C-EKE
SST39VF3202-70-4I-EKE
SST39VF3202-90-4I-EKE
SST39VF3202-70-4C-B3KE
SST39VF3202-90-4C-B3KE
SST39VF3202-70-4I-B3KE
SST39VF3202-90-4I-B3KE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combinations.
©2011 Silicon Storage Technology, Inc.
DS25028A
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16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Packaging Diagrams
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0°- 5°
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
1mm
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
0.70
0.50
48-tsop-EK-8
Figure 25:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm
SST Package Code: EK
©2011 Silicon Storage Technology, Inc.
DS25028A
32
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16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
TOP VIEW
BOTTOM VIEW
5.60
8.00 0.10
0.45 0.05
(48X)
0.80
6
6
5
5
4.00
4
4
6.00 0.10
3
3
2
2
1
1
0.80
A B C D E F G H
A1 CORNER
SIDE VIEW
H G F E D C B A
A1 CORNER
1.10 0.10
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-5
Figure 26:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
©2011 Silicon Storage Technology, Inc.
DS25028A
33
08/11
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
A Microchip Technology Company
Not Recommended for New Designs
Table 19:Revision History
Number
00
01
02
03
04
Description
•
•
•
•
•
•
•
•
•
05
A
•
•
•
•
•
•
•
Date
Initial release
Corrected Pin 15 from A20 to NC for SST39VF160x in Figure 2 on
page 4
Changed data sheet title
2004 Data Book
Updated the B3K and B1K package diagrams
Added non-Pb MPNs and removed footnote. (See page 31)
Added RoHS compliance information on page 1 and in the “Product
Ordering Information” on page 30
Corrected the solder temperature profile in “Absolute Maximum Stress
Ratings” on page 15
Changed product status from “Preliminary Specifications” to “Data
Sheet”
Removed 90 ns Read Access Time globally
EOLed all lead (Pb) valid combinations. See S71223(02)
EOLed SST39VF6401 and SST39VF6402. See S71223(03)
Changed document status to “Not Recommended for New Designs”
Applied new document format
Released document under letter revision system
Updated Spec number from S71223 to DS25028
Mar 2003
Apr 2003
Jun 2003
Nov 2003
Nov 2005
June 2008
Aug 2011
ISBN:978-1-61341-355-5
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office locations and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
©2011 Silicon Storage Technology, Inc.
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