348_Manual_1964

348_Manual_1964

348 YJANUAL

TYPE 348 DISPLAY

I~lTERFACE

.r1ANUAL

TABLE OF CONTENTS;

IN'TRODUC''fION

~~\

I

LJ

Ul

~/

SECTION

I

SECTION

I I

SECTION

11J

SEC""l'ION

IV

SEc'rION

V

APPENDIX A.

I

APPENDIX B

PROGRAMMING

THEORY OF OPEPATION

MAINTEJ:lANCE

GLOSSlffiY

BLOCK S C'"rlElvlA TI CS

CAIt

LE S

CH.r~JULE

SECTION

:I

INTRODUCTION

The Type 348 Display

Interface allows operation of DEC

Type 30A or 30EDiaplays from a

PDP-6 computer. The

Display'

Interface utilizes DEC System Modules contained in two standard mounting panels'. In addition to the ,modules, the mounting panels contain the necE:ssary connectors for the PDP-6 IO bus and a.,S.o,.

pin

Amphenol connector for the

Iqcable to the . displ.ay.

The display interface accepts standard PDP-6 conditioning and data signais from the 10 bus and converts these into signs,ls t\cceptable by the

Type

30 display

~

,To the' display

I

the interface looks like a PDP-l

/ eomputer. Signals from the display ax.:,€Jconverted by the interface int.o signals that can be p~aced on the lObus and used by the PDP-6 Computer. ':f.lhe interface includes provisions for operating a

Light

Pen if one is available on the display.

This It'.anual is concerned only·.with the operation and

.maintenance of the d~splay_

.interface itself. Addition informationabout the

PDP~6 computer and the 'lype 30 Display can

,be obtained from the ?lPpropriate ref.erence' manuals.

S'ECTION II

INSTALLATION AND OPERATION

'llhe Type 348 can

.., be installed in. the ~ield as well as being factory installed during construction of a computer. since the dlspl~y interface consists of only two mounting panels, ·it is usually mounted in a bay containing other equirrment. As a

re-

sult, the physical location of the

'Type'

34S'wiil vary from system to system.

If the required space is not available, an additional bay, must be added to

the

system.

The 348 requires approximately one-half of the pov/er 'supplied by a Type

728 power supply. If the required power is not

(:l1t:~~9X a~~~J~~J»

..

E;" a

7~~, power supply must be added. If an ... tld~ ditional s'Upply is required, i t should be connected to an existing :t-o\</er ,control to provide for local or remote application of power to the Type 348.

The two logic. panels are mounted on the front (wiring side) of the s.elected cabinet. First remove the front doors and any interbay trim strips. Insert the mounting ftanels from the front

'side and's'ecl:lre them with screws through the mounting ;lange's·· into theriu-nut&prov:.ided, in the vertical framework of the

\

' cabinet}:"~:The mounting· panels. can be ·installed with the modu·les in' place. ,Af,ter . securing

,. mounting panels, replace thetr·im

, stri1:'s and front doors. If ltn additional power supply is required .•. i t is mounted'

,on :the inside of the ~lenum door at the back 0-£ theca-b.inet.

Power connection to the logic is made by means of the jumpers provided. In addition to the norlnal operating pO!N'er, connection should be made to the marginal check power supply to provide,. for lTl.a~ginal checking of the display .-interface logic. The pO~;1er \~irin9 fotlow8 standard PDP-6 practice.

Refer thcPDP-6

IIJ.anual fot details.

Connection to the PDP-6 10 Bus is.~ade by plugging the four IO Bus~:ablcs into one of the two sets of con..l1ectors in

~;, the upper mounting panel. If the ~isplay intefface is the last item on the bus

4 a terminator module must be. placed in these~"Ond

# connector. If the display inter;face is not to be the last item on the bus, the four 10 cables to the-"' next device are placed

".

in

the second set of 10 Bus connectors.

The 10 cable from the display is brought through the c&b-l-c· acaea& ll~l~' it);, t.~e~ bot1:om of the cabinet and plugged'>

• Iinto the

Amphenol

~nnedt6r mounted on the lower: logic pane'l.

This completes the installation of the Display Interface, and it is ready for operation.

No action other than application of power is required to prepare the Txpe.:·348 for operation. If the power control used is set up for remote operation, the display interface will

~he

Q\Q~ ~ ;bt~f

\ . is. turned on.· . In additioa • .,

-is.

Volt

signal

required for remote power operation of

"the."dieplay

.is ,supplied

to

,the display through the display

%0 cable.

-3-

SECT.ION IV

THEORY OF OPERATION

This section·describes the logical operation of the display interface. Standard

DEC

System Modules are used throughout.. Detailed information about individual~ modules can be obtained from the DEC. System Module Catalogue and. from theCircu~tDescription section of the PDP-6

~mintenance

Manual. The display interface

. logic is

ShO\vll in three Block Schematics. Reference to the ~ap­ propriate

~lock

Schematic is made in the detailed logic description below·. The Block

Schematics are contained in

AppendixB of this manual. Refer to the PDP-6 Maintenance Manual for a description of·the.syrobols and drawing conventions used. Appendix

A of this manual contains a glossary of the abbreviations and mnemonics used in the Block Schematics ,and the lo.gic descriptions below. gp;NERAL

OPE~TION

Figure 1 is a simplified Block Diagram of the

.Type

348 Display

Interfac~.

The unit· includes a connection to·the PDP-6 10

Bus, a co.nnection to. the display 10 cable and three groups of

LagdJ(!"', the Data Buffer (DB), the

ControX. Regis·ter

(eRr antI" ttJj~.

Co.ntrol'Logic (CL).

The 10 Bus supplies con\ro.l pulses to the control logic which in turn controls the transfer of data

'from the 10 Bus to the Data Buffer and the ,rtansfer of condition (status) infor-

;I

mation

,to. and from the 10 Bus and· the Control Register.

-4-

The Data Buffer, under control of,the

Contro-l

Logic,

BUP-

plies data to the display. This data consists of

C.t

10 Bit X coordinate word and a 10 Bit y, coordinate word which are used by the display to position the spot to be displayed on the CRT screen.

The Control Register contains several flip-flops tllat can be sensed, cleared and in some cases set, byPDP-6 IO commands.

'rhe control

Register supplies various control and information levels to the Control Logic and to;' the 10 Bus. Some of the CR

,

. flip-flops can be c~ntro11ed by signals from the dlspl:a~, pro:vidlng cO,ntrol and information levels that are' directly related to inte:r.nal.operations of the display itself.

The Control Logic utilizes pulses from the 10 ~us, levels from the Control Register and pulses from.the display to gen-

~,~at.e cQ~t::;pl pulses required for propex:, opera tion of

~bQ" ~nt.;i;;~E; display system.

The follo~!ing sub-s~ctions 'viII treat the

Data Buffer" the

Control ,Register and the

Control

L9gic in that order. 'l'he PDP-6

10 connections and the dis~lay 10 cable connections will be covered as they occur in descriptions of the three basic portions of the interface logic.

DAI'J.'A JlUEFERS

The Data Buf.£ers are shown on drawing No'. D-,348-0-4. since the two buffers· (x and Y) ar~ essentially identical, only the

X buffer will be described in detail. The between the two, buffers only real dif£.,erence

pe

the origins and destinations of the information that passes'through them. The X buffer accepts information from the lo~' order 10 Bits of the right half of a PDP-6

"-5- '

word and pas~es i t on to the horizontal (X coordinate) buffer of the Type 30 display. The Y buffer accepts information from the

1~J'l order

10 Bits of the left half of aPDP-6word and passes 'it on to the vertical (Y,coordinate) buffer of the

Type

30 display.

Note that since the displa.y intcl:facecontains flip";flop buffers for the X and Y information, this information is essen~ tiall~1 dpuhle buffered, and the displa;t interface· Data Duf:fe.l';s> may con~ain'coordinate information. for the next po~nt to be displayed \-lhile. the display itself is in the 'process .of displaY"ing information contained in its own horizontal and vertical bl~"f'fers.

The X'Data Buffer is made up of two 4220 modules. since oniy 10 stages are required, all eight. flip-flops of one module

(B 18) ar€:.used, and only two flip-flops on the other module

(B

17) are used. All flip-flops on both modules are

~ared to thei.r zero state by a clear X signal generated in the c'orttroI logic to be described below.

The desired display information is inserted into the Xbuffer by means of the built in capacitor diode gates. The con-. ditioning level at the capacitor diode gates'is supplied by

'COrl\

.

' \ . nection ,to. the

,PDP-6 10 Bus.

The set X pulse supplied by the:' \

Control Logic strobes the capacitor diode gates and sets the

da-

g;r~ed;

X buf£er flip-flop to

,the .one s~te.

Th'e output

c:if

t'l}Ef~.

Data

Buffer is supplied through buffering resistors to the display • . In' the display, th'e X,pataBuffer levels are

~

, applied to capacitor diode level inputs for the horizontal buffer. Note that these level inputs mqst be applied to the CD gates for

/ .

, . ' " appr·oximately three microseconds before theresa-in pulse to ell$ure proper transfer" into the display buffer. '

~6-

The outputs of the

X buffer' stages X1: .. and Xg aret:aken from ,the ground side of the flip-flop (i.e. ground equals logic.

1). The moat significant stage (X

O

) uses -3 Volts to represent a logic 1. This ~s required by the internal l09ic of the display itself and z:eference should

be

made to the

Type

30 manual. co~rROL fffiGISTER

The Control Re9ister logic is shown on dra\'ling D-348-0-3.

This portion of the logic, supplies

"most ,of

~he communication be-

,

" tween the

,'PDP-6

C01Jlputer and the display interface.

CONO .(Condit'ion Oui;) commands from the PDP-6 can set most of the flipflOps in 'the

Control

Register in

'order to establish" the operatingcondit,ions of the display interface. lOB status

(CONI or

Conditions In) commands from the PDl?-6 cansenae the state of all flip-flops in the Control Register in

order

to determine

~he current status of the display inte~f-a:ce.'

·There are fourteen flip-flops in the Control Register. All flip-flops are 'llype 4217 in modules in locations A3, A4,',and AS, pl\.\s two flip-flops on module

J.2.

'These are shown in area Bl through BS of the Control Register print. All of the Control

Rg9ister, flip-flops' are cleared by the DrI

CONO clear signal generated'in the control logic.

Por co:{),venience, the flip-flops in the Control Register

.will be d~acribed in left to right ord~r.

-7,-

, The DIS Busy (Display Busy) ,flop indica,tea t.he current status of the display itself. The flop is set by the LOP (Load Display

Pulse) signal and is cleared by the PDP (Display Done Pulse) signal., 'In other

'VJords, this flip-flop is set to the one condition whenever, the display is in the process 'of locating and intent;ify-'

" inga particular spot on the face of the CRT. Note that LDP is a signal, generated by the display interface,· that initiates action in the display itself. DDP is a signa1t generated by the display, that sig~a:ls the end of the display action.

LP· Status (Light Pen status) is a flip-flop that is set to the one condition by the

LPF

(Light Pen Flag) signal fromth-e display.

~Re,ference to the Type 3'0 Display

~mnualwill_,show that

-Ll?Fis generated only when the Light Pen has seen a spot of light during. the time the display is intensifying a particular point on the CRT • . T.aP status is cleared by the CLPS (Clear Light Pen Status) s.i:gnal.

'l'he CLPS signal is generated h:i. an J:OB

StatllA., s'±:Qu-e;~ ~orn the

PDP-6 10

Bus. Once LP Status has been set l i t "lill rema-:i:1l'"

±n.

this condition ,until

it

has been examined by the progrnm.

Such examination can cc:.me as the result of a priority interrupt (the

LP priority interrupt circuit is enabled by the one state of Lp·

Status), or by programmed examination of the status of the. display interface.

If the program does not exa~line tpe status of the display interface, the LP status flop will remain set until the~next lOB

CO:tlO clear of,

IOB

Re-set.

. Note that the bIS Busy and LP status flip-flop cannot be

, set· by

. from t

The other twelve flipflops in the Control Register can be set by 'means of built in

~< capacitor, diode gates.'

T~e qualifying levels .

',for the gates come

. ' from the indicated bits on the 10 Bus.

, J

-8-

The, re xt stage in the

'Control Registe:r is the DF! S:tatus

(Display Interface status) flip-flop. \'lhen this flip-flop is in the one state, it indicates that the display interface is free to accept another data, word from the computer. This con-

.

by

either a CONI command from the computer or through the priority interrupt system. DPI status i~·:;

DPI the one condition enable~the

DPI priority interrupt decoder ..

.... status is set to a one by the LOP signal. LDPis the 5ignaLtha.t.p~lacesi·the con:uen~s of tl;le

Data Buffers into the nisp~ay l7ll;1ffer. Since the contents of the Data Bpffers have b.cen passed on to the display, the

Data Buffers are now free to be cleared and reloaded with new data. Dl?I status on a one indicates thj s condition.

Dl~I status is set to a zero by DPI

DA~IAO clear. This signal is generated

by

a

DATAO

(Data out) signal from the PDP-6 Computer. DATAO Clear occurs: just before data from the com1?uter is loadeg into the Data Buffers.

E1rom thl$ .

. time until the next LOP signal, the display interface cannot accept another data word without destroying the information that bas been placed in the Data Buffers. This condition is i~dicated by

DPI Status in the zero state~

The Y Only and X Only flip-flops control the application of clear and set pulses to the Data Buffers. If one·of these fl'ip-flops is set to the one state, it will inhibit changes u in, the

.,o'therData Buffel.~.

For example,

~f y

9:'a1y is set, the'

XBuffe~~cannot

be changed.

The three Ilrr

(:tntensi~) flip-flops control the intensity of the' spot displayed on

.the CRT if the Type jo

Display include~ a variable'intensitYmod)£ication •. There are eight intensity levels:available, corresponding to the eight po'ssible states of the

-9-

three INT flip-flops. The tlu:ee flip-flop~ are treated asa two bit ~igned binary llt.:4'1tber.

Negative numbers are in two' s complement form. The most negative nUn'loer

(100) will produce the . least intensity. 'l'he largest positive nUJ.wer(Oll) results in greatest intensity. The outputs of the three ItiT flip-flops are used in the Control Logic to gt\te pulse amplifiers that produce pulses to set the intensity register in the display.

The;! three LP PIA (Li,gll.t, Pen Priority Interrupt

Assignme};lt). f;l±l?-fl~ps are used' td assign apri~rity interr/..lpt channel to the _ light pen signal.

Anyone of seven channels, corresponding to the octal numbers 1 through 7, may be assigned. Since there is no channel'zero available, octal zero re~ovesthe. ~.;l9h€ pen fro~ the priority interrupt 'system. The outputs 'of the. LP

P~_fliP;7 flops .are decoded by a Type 4151 module. In addition to the I..tP PIA inputs, the LP status flip-flop must be in the one state to generate an output from the 4151.The Otltput; \'/i11 appear as a ground level on one of seven lines corresponding to the octal number contained in the three LP P~. flip-flops. The 4151 output is placed on the 10 Bus and, under the proper conditions, will cause an interrupt in the

PDP~6

.computer. Refer to the' PDP-6 1-1aintenallce

Manual for "detailed information on operation of the Priority Interrupt System.

The three

DPZ PIA

~lip-flops are usedirl. the same manner as

\ the-

~ P.~A flip-flops. Note<, however, that the output from the

41,51 decoder in:th!s case depends upon theDPI Status flip-flop being in the one ~tate.

--10-

Note thZlt lOB bits 24 through 35 are

USE..>d as

,conditioning

levels

for the input gates to the control register flip-flops ..

This al1o\>IS b~e computer, under programmed control, ·to estab~i$h the· desired conditions in the display interface.

o

In addition,

. the condition of the Control Register flip-flops can be placed on the 10 hus using lOB bits 22 through 35. In this

",ay, the computer can determine the status of the display interface.

This is· accomplished through the Type

4657 gates shown in area

G1 th:roug'h. ca

'ofthe Control R(;gister Print. Each gate'

1;8' U'SS·O-" cia ted ~ith the control register flip-flop directly above it on the print

.l1.hen a gate receives the proper qualifying signal from its flip-flop, and an lOB s~atus cow·~nd ~~ re~eivedfro~

..... the

PDP-6" the stat~sof the flip-flop is tranSlllitted to the

PDP-6 through" the 10

BUG •

. The display interface Control Logic is shown on drawing n-348-0-2.

This portion of the interface utilizes pulses and levels front the PDP-6 Computer, levels from the control· register, and pulses from the display to generate signals 'that control the transfer of data ar.d status inforrnation to and from the computer and tlle display ..

Since the PDP-6 IO Bus is common to all

~put-output de- ' vices, eacll devi.ce· must continually sample the bus and deteruline when i t ha~ been aadresse9 by an

10 command. This function is performed by the

Type

4118 mdUule located in area C2·of the Contl:01 Logic print.

Bits 3.through 9 of the

PDP-6 10 commands are usea to select the desirjd IO device.

Depend~n9 on the. device

/"

0:-11-

nurnher assigned

(in this case 134)" the. zero - or oi'1e outputs from' the selected bits are fed into the 4118.

~fuen all of the 4118 inputs are at ground potential,' a negative level is generated which qualifies various input· gates and allows 10. signals to pass from the PDP-6 computer into the display interface. liote: Refer to the PDP-6 l..faintenance ~lanual for detailed information about the PDP-6 10 commands and their actions.

~here' are two signals from the 10 Bua wh:+ch do not r'equir'c device selection gating. One of these is the -15 volt signal

~lhich indicates that power has been turned on in the

Type

166

. Arithmetic Processor. This signa.l is fed directly

~o the display. to provide for., remote operation

?f the display po;er con-

, trol. The second signal is the lOB Reset which is fed into the

4606 pula~ amplifier. (BS) sho\vn in area 52 of the print.

-The normal operating sequence for- the display' inter,-Saoe starts wit~ a'

CONO

COlrunand from the.

PD~-6.·

This' is follo?.*lcd by one or 1U01;e

DATAO commands. lOB Status cOIfu~ndamay f~llow

(or be' interspersed with) the DATAO comn~nds.

The interface

Control Logic associated with each of these computer command$

\\'ill be ')described in the same order.

The CONO command is used to establish operating conditions within the display interface. The instruction in the PDP-6 generates" two pulses: lOB CONO clear, followed (after onem.icrosecondlby. lOB COHO set. These signals are shown corning from the

. IO Bus in area Bl of the

Contt"ol

Logic print •.

-12- .

lOB CONO Clear

I

gated 'by the device decoder" is applied to a

TYl:-ia 4606 pulse amplifier .and produces the DFI CONOClear signal. Note that lOB Reset is applied to the same pulse amplifier wi thout gating and produces the sar~e output signal. DPI

COx10

,

.

Clear clears all of the ·flip-flop.:: in the control

Register to the

zero

state.

In addition, it clears the l<10VE flip-flop is sllo'r/n in 'area_;D4 of the control

Logic print, and its action \&lill be described later •

(.p.art after gating, 1s applied to, another 4606 of rnod\1~.e

85) ana produces

DPI

Cono

S~t

J

This signal.. is' used in the Control Register to depos>!t the current status of tJle 1Q Bus illt.o the

Contro~

Regi'ster flip-flops. In t;llis way' the computer call establish operat~ng qonditions for the display interface.

The DP..TAq comr~~n4 from the computer also generates twq pulses: 1013 DATAOclear and lOB DJ.\TAO set. . Both of c these pulses are gated by the output from the device selector.

IOB DATAO olear produces DPI DATAO Clear which is applied through capacitor.diode gates to two type 4606 pulse amplifiers.

The qualifying levels for the CD gates are supplied by the Y

Only and x Only fli~flops1n thf:i

Control Register. The resulting

Clear X and Clear Y signals clear out the corresponding data buf-

. fe;cs·. liQ.te tba.,tei:tlu~xc one" or both of these clear

.

'

\.

. signals" mtiy be generated, depend.ing upon the .states of theY

Only and

X Only flip-:.flops.inthe contro~ Re.gister.

-13-

At this -point, theCONO comrnano has cleared the entire

S~lS­ tern and set the desired control register flip-flops to establish

-operating conditions. The DATAO Clear corrmand has cleared tm data registers and the system is ready to start tr_ans£erring in,:", forn~tion to the display interface.

'IOB DATA ,Set, gated by the device selector, is applied to a 4606 pulse alnplifier (36) shown in area C2 of the- Control

Logic pJ:il1t.

~he pulse amplifier output (DPI

D14'1~Q

Set) is applied thx:ough capacitor diode gates to

0.\10

4606, pulse an1plifiers. The qualifying levels for the CD gates are' suppliec" )by--the

Y only and X

Only flip-flops in the control Register.

~he resulting

Set X and Set Y signals are u~edl,to transfer infor~tion from the

10 Bus into the

Data Buffers. The outputs'of the buffer flip-flops are applied to capacitor diode gates at the input to the buffer reg-ist/er.s in the display. Approximately three microseconds are requir'ed between setting of the data buffer flip-flops and reading linto the display buffers. This allows for sufficient change. in cha.rge ..('In the CD 9ate.capa~itors to ensure proper tr~nsfer of information in-to the display buffers •

The three microsecond delay required by the display buffer input gates is generated by a Type 4301 delay module shown in area C5 ,of the control logic print (module

No.

B4). The delay. is triggered

by

DPI DATAO Set. The outputs of the delay module are a negative level (Pin

J) for the duratio'n of the delay time

~ and a negative:'pulse (Pin E) that occurs at the end of the delay time.>

The use of these signals will be.' described "below.

-14-

The

DPID~/r1:;O

Set signal is gat(~d by inverte}~:d' shot-tn in areas D6 and C6· of the contl.·ol logic print .'1'hese inverters are part of a Type 4105 module loca ted in B 10. The lo~wer' inverter arop~ifies and invexts the zero output from the ,Dis Busy flip-f.lop in the control regi.ster. t>'lhel'l

DIS Busy is a zero

(in other

\1ords the display is not in the process of displaying a point), the uppel." in.verter is qualified and the DPI

DAI'.r.,1\O set signal can pass through: ,it into a 4604 F}ulse amplifier module.. 'rhe 4604 (module Ell sh~A'11 in

-area

B7 of the print) . is, connected to provide a one microsecond negative pulse output.

This ,is the CDI' pulse which is fed tr..rough the display IO cable to the display \vhcre it generates' sigl1.als, to clear the display

,

, buffers.

, The 4604' output is also applied \to the

~ase input of one of the in\rerters· on module' alO. The emitter of this inverter is connected to the leve 1 outIJtl t 0'£ t:he 4301 d(~ la.y lTtodulE.!.

Si.nce the delay is in progress at this time, the inve~ter is cut off and the s~gnal path is closed.

DPI DATAO Set also sets the

l"lOVE

flip-flop to the one state.

This is accolnpliahed through a 4102 inverter

,Ir~odule

(AI) shown in area C4 of the print. The use of the )10VE flip-flop sigIlal will be desribed later.

When' the:

'

. three. m±c:r-cs~aoJ;l<i;; d~l'aY produced by the Type' 4:301 delay IrtOuul,e is completed, the negative output pulse is applied to ~n inver,ter on

,

With DIS 'Busy in the zero state, this inverter can conduct. and the pulse is amplified and inverted and applied to a

Type

46-06 pulse amplifier, (modu.le B9) shown in area C7.

The.~utPutof

,the PA

,; is the negative LOP signal.

IDP isapp~iedto thedispl.ay through the display 10 cab).e and to

~everalpOints in the diS!pl~y int~rface control' logic and control register.

-;15-

In the ~isplay, L.l)P is used to generate siglials that load the displ~y buffers and initiate all

~urther display actions.

At the end of the display actions, the display sends the DDP signal back to the display interface. Reier to the Type 30

Displ'lY Manual for details.

LDP is applied to the gated inputs of th.t"€e

Type

4606 pulse

-amplifiers (module B8) shown in areas AS and

P.\6

of the control logic prlnt.

The PA' s are g'ated by the three intensity flipflops in 'the control ,register. The

PPi outputs are fed through the display

10 cable to the display's intensity register.

LOP also clears the MOVE flip-flop in the control logic and sets',

~oth the DIS Busy and DPI

''',

Status flip-flops in the control register to the one state. DIS

Busy indicates that tlle display is in the proc~ss of displaying a point, Z\,nd DPI statu,s indicates that the display interface is free to ac;c~pt data .for·the next· point to be displayed.

The action described so far is typical of that pro~uced by the first DATAO command from the <.?omputer. Further action

v.:i11

be determined by

~ne of two possible situations: the display will complete its action before the display interface is "loaded with additional data or the display interface will'

be

loaded before the display completes its action.

First "consider the case wllen the display is completed bfe-fore the interface is reloaded. In this case the conditions at the end of

-

. the displa'l" w~11 be as indicated at the end of

~ the initial "action described above.

-16-

The DDJ?' signal generated at the e11d of the display a.ction i~:; applied to the pulse amplifier in the cont:r.~ol logic which ge~1erates

CDP (f£'ype 4604 module BII in area B7). The CDI' signal is generated and the display buffers are cleared. In addition,CDP (treated as a one micro~econd negative level rathe~r thana negative pulse) l)asses through an inverter and become'S

li

one l'nicrosecond wide ground leve 1. j;~ote that

'the signal cal?no'l.v pass through this inverter' since the

'J.'ype

4301 delay module~: is in its quiescent 'state and Pin

J will be at 'ground, placing: the emitter input of the lnvert(~r at ground.

jr-rhe

one

;,~'icrosecond wide ground level output of the inve~ter is applied to the pulse input of-the capacitor diode gate on the pulse amplifier which genera te6

L.T)I' e

(Type 4606 module, B 9 in area C7).

'rhe leve 1 i.nput of the CD gate is s'upplied, by the lone output of the IDVB flip-flop.

At this tirn1e, however, MOVE l a i n the zero state~ i the CD gate is not qu.alified, and no further action results.

Since no data has been loaded into the display interface, no action is desired.

Any further display signals from the I?Dp"·6 will

~~6d'ude the in! tial a.ction described above.

Now consider the case when the display interface buffers are loaded by a

DATAO cOTf'mand while the display is still in,the

, procese,;~of

,9isplayinga spot _, Again c,?nditions areas described at the end of the initial action. In particular, note that the

DXS n:u~y f,lj.~-flop is< s.E)t. to the one state.

TheDATAO Clear and

Set co~~nds result in the clearing and setting of the X and

Ybuff2rs, the setting of the

,..lOVE f~ipflop, 'and the

~ initiation of the three microsecond delay, all as described - above e"

-17- ,

The

DJ~S

Busy

(Dj~splay

Buay) . flop inc1icat(~s the' curren~ status of the display itself. The flop is set by the

IJ)~

(Load pisplay

Pulse)' signal and is cleared by the DDP

(Display

Done

Puls~) signal..

In other words, this flip-flop is set to the· one' condition whenever th~ display is in the process of locating and inteneify·-~, i41sra particular spot on the fa.ce of the CRT. Note that La.l)Pis a particular spot on the face' of the CRT.

Note that

IiOP is a e.i..gnal, generated l)y the display int·er face ,that initiates action in th(~ ;(j;.~play itself. DDE is. a, sigr~tL, g.encr~Lted b:! the dii1play, t.hat sigp.als th~ end of the display actj.on~-

LP Status (l.Jight Pen status) ····is a fllp-flop that is set to

).", ....

'-

..

,., the one condition

,by the LPE' (Light Pen l;'iag)""" s~gnal lrbm the

(: display.

Reference to the

Type

30

D~st)lay

Manual will show that

LP~ i is generated only when th L · .... :.,.. "I seen a spo t of li.ght during the time the d:i.splay .is ;n,t:eflsifl'iug

~ E~rticular point on the CRT. LP Status is cleared by the CL!)S (Clear J,.Iight Pen Status) signal. The CLPS signal is generated, by an lOB status sig-nal from the I?'DP-6 10 Bus., Once lJ? status has been sG't, 'it will .. ternain in

,A, this cc'ndition until it has been cxamlned by the program. Such examinz,ti.on can come as the result of a priority interrupt (the

LP priorit'y interrupt circuit is enabled by the on~ state of LP

Status), or by progr;arrencd examination of the status of the display interface. If the program does not examine the status of· the displaty' int.erfaca" 1.tlle

1...l"·

S:-ta~tu,a·

:fi.l'ap will

)'ZE-mamset until the

.

~ lOB CO NO clear of iOB Reset. ne;.'Ct

Note that the DIS

Busy~nd

LP Status flip-flops cannot be set by

G).

CQNO command from. the' computer •.

The other twelve fJip-

'fl~p~ in the 'Co'ntrol

Re

1

4-'s·ter can be set by means of built in

.capacit·or diode gates. } 'The qualifying levels for t'he gates' come .

..

-18-

,WP produces the actions described a.bove, and the dis'pl~ly is ageJin in the process of locating and inteusifyiu'g a Sl)ot.

I t i

' .,

1 e t1n t \,. n cou ld occur

1 i seconds after DP! DZl.'1'iiO

B,et. In this case DDP will c lear the

DIS Busy flip-flop and the display buffers, but will not generatel

~lith

DIS

Busy in the zero state, the pulse at the end of, tl,le thr€.:e microsecond delay will 'generilte 1..ol? and the display will again be placed in operation •.

There i.s one n:ore PDP-6 instruction which affects the dif'lpla~y j.nter face. This is the lOB Status or

CO!~I instl':.!:lction.

The asso~iat€d logic is sh~,fV'n in area Al through

A4 of the controllogic print.

'1'he lOB status slgnal is a neg-a.tive level approxirn~'3.tely

2.5

microseconds wide. It is applied; along with the dt~'Vice

'sel~!ctor gating level, to a Type 4113 . inverting And gate

(rfiOdule BI3). The

9at~d output is amplified and inverted by hiO inverters on a

'l~pa

4102R module {b14} an.d becomes lOB DPI(A) and lOB DPI(B). These sIgnals are applied to the Type 4657 in the control register and place the status of the control ter· flip-flops on the IO bus for the duration of the lOB Status

.

~igrial.

·In addition,

·IOB

DPI (A) is applied to the positive pulse input of a

4606 pulse an:plifier

(l·iodule

B9). The pulse, amplifier

~/ill respond to the poiitive going trailing edge of 'the input. signal

. sign~l

(CLPS)'M that clears the light pen atftuB flip-flop in the control register.

2

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