Mbm29dl640e

Mbm29dl640e
TM
SPANSION Flash Memory
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20887-3E
FLASH MEMORY
CMOS
64 M (8 M × 8/4 M × 16) BIT
Dual Operation
MBM29DL640E80/90/12
■ DESCRIPTION
The MBM29DL640E is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 M words
of 16 bits each. The device is offered in 48-pin TSOP (1) and 63-ball FBGA packages. This device is designed
to be programmed in system with 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
The device is organized into four physical banks: Bank A, Bank B, Bank C and Bank D, which can be considered
to be four separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu’s
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.
(Continued)
■ PRODUCT LINE UP
Part No.
Power Supply Voltage (V)
MBM29DL640E
80
VCC = 3.3 V
90
+0.3 V
−0.3 V
12
VCC = 3.0 V
+0.6 V
−0.3 V
Max Address Access Time (ns)
80
90
120
Max CE Access Time (ns)
80
90
120
Max OE Access Time (ns)
30
35
50
■ PACKAGES
48-pin plastic TSOP (1)
48-pin plastic TSOP (1)
63-pin plastic FBGA
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-63P-M02)
MBM29DL640E80/90/12
(Continued)
In the device, a new design concept called FlexBankTM *1 Architecture is implemented. Using this concept the
device can execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and
Bank 2, a bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1.
(Refer to FUNCTIONAL DESCRIPTION for Simultaneous Operation.)
The standard device offers access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed
microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write
enable (WE) and output enable (OE) controls.
This device consists of pin and command set compatible with JEDEC standard E2PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
the proper cell margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed) .
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once a program or erase cycle has been completed,
the device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the
Embedded ProgramTM *2 Algorithm or Embedded EraseTM *2 Algorithm, the device is automatically reset to the
read mode and have erroneous data stored in the address locations being programmed or erased. These
locations need rewriting after the Reset. Resetting the device enables the system’s microprocessor to read the
boot-up firmware from the Flash memory.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
*1: FlexBankTM is a trademark of Fujitsu Limited.
*2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MBM29DL640E80/90/12
■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Program operations (Dual Bank)
• FlexBankTM
Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)
Bank B : 24 Mbit (64 KB × 48)
Bank C : 24 Mbit (64 KB × 48)
Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)
Two virtual Banks are chosen from the combination of four physical banks (Refer to FlexBank® Architecture
and Example of Virtual Banks Combination tables. 10)
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase
Minimized system level power requirements
• Compatible with JEDEC-standard commands
Uses the same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (1) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)
63-ball FBGA (Package suffix : PBT)
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode
Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector group
protection/unprotection status
At VACC, increases program performance
• Embedded EraseTM Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
*1:FlexBank® is a rigistered trademark of Fujitsu Limited.
*2:Embedded EraseTM and Embedded programTM are trademarks of Advanced Micro Devices, Inc.
(Continued)
3
MBM29DL640E80/90/12
(Continued)
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, the device automatically switches itself to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
Suspends the program operation to allow a read in another byte
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
4
MBM29DL640E80/90/12
■ PIN ASSIGNMENTS
TSOP (1)
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
A21
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
Normal Bend
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16
(FPT-48P-M19)
A1
A2
A3
A4
A5
A6
A7
A17
A18
RY/BY
WP/ACC
A21
RESET
WE
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Reverse Bend
(FPT-48P-M20)
(Continued)
5
MBM29DL640E80/90/12
(Continued)
FBGA
(TOP VIEW)
(Marking Side)
A8
N.C.
B8
N.C.
A7
N.C.
B7
N.C.
A2
N.C.
A1
N.C.
C7
A13
D7
A12
E7
A14
F7
A15
G7
A16
H7
J7
K7
BYTEDQ15/A-1 VSS
C6
A9
D6
A8
E6
A10
F6
A11
G6
DQ7
H6
DQ14
J6
DQ13
K6
DQ6
C5
D5
E5
WE RESET A21
F5
A19
G5
DQ5
H5
DQ12
J5
VCC
K5
DQ4
C4
D4
E4
RY/BY WP/ACC A18
F4
A20
G4
DQ2
H4
DQ10
J4
DQ11
K4
DQ3
C3
A7
D3
A17
E3
A6
F3
A5
G3
DQ0
H3
DQ8
J3
DQ9
K3
DQ1
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
CE
J2
OE
K2
VSS
B1
N.C.
(BGA-63P-M02)
6
L8
N.C.
M8
N.C.
L7
N.C.
M7
N.C.
L2
N.C.
M2
N.C.
L1
N.C.
M1
N.C.
MBM29DL640E80/90/12
■ PIN DESCRIPTIONS
Table 1 MBM29DL640E Pin Configuration
Pin
Function
A21 to A0, A-1
Address Input
DQ15 to DQ0
Data Input/Output
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Hardware Reset Pin/Temporary Sector Group Unprotection
RY/BY
Ready/Busy Output
BYTE
Selects 8-bit or 16-bit mode
WP/ACC
Hardware Write Protection/Program Acceleration
VSS
Device Ground
VCC
Device Power Supply
N.C.
No Internal Connection
7
MBM29DL640E80/90/12
■ BLOCK DIAGRAM
VCC
Cell Matrix
8 Mbit
(Bank A)
A21 to A0
(A-1)
Cell Matrix
24 Mbit
(Bank B)
X-Decoder
Y-Gating
Bank A
address
Y-Gating
VSS
X-Decoder
Bank B Address
State
Control
&
Command
Register
RY/BY
DQ15
to
DQ0
Status
Control
Bank C Address
X-Decoder
Cell Matrix
8 Mbit
(Bank D)
Bank D
address
Y-Gating
X-Decoder
Cell Matrix
24 Mbit
(Bank C)
■ LOGIC SYMBOL
A-1
22
A21 to A0
16 or 8
DQ15 to DQ0
CE
OE
WE
RESET
BYTE
8
RY/BY
Y-Gating
RESET
WE
CE
OE
BYTE
WP/ACC
DQ15 to DQ0
MBM29DL640E80/90/12
■ DEVICE BUS OPERATION
Table 2 MBM29DL640E User Bus Operations (BYTE = VIH)
Operation
CE OE WE
A0
A1
A2
A3
A6
A9
DQ15 to
DQ0
RESET
WP/
ACC
Auto-Select Manufacturer
Code *1
L
L
H
L
L
L
L
L
VID
Code
H
X
Auto-Select Device Code *1
L
L
H
H
L
L
L
L
VID
Code
H
X
Extended Auto-Select Device
Code *1
L
L
H
L
H
H
H
L
VID
Code
H
X
L
L
H
H
H
H
H
L
VID
Code
H
X
L
L
H
A0
A1
A2
A3
A6
A9
DOUT
H
X
Standby
H
X
X
X
X
X
X
X
X
High-Z
H
X
Output Disable
L
H
H
X
X
X
X
X
X
High-Z
H
X
Write (Program/Erase)
L
H
L
A0
A1
A2
A3
A6
A9
DIN
H
X
Enable Sector Group
Protection *2, *4
L
VID
L
H
L
L
L
VID
X
H
X
Verify Sector Group Protection
*2, *4
L
L
H
L
H
L
L
L
VID
Code
H
X
Temporary Sector Group
Unprotection *5
X
X
X
X
X
X
X
X
X
X
VID
X
Reset (Hardware) /Standby
X
X
X
X
X
X
X
X
X
High-Z
L
X
Boot Block Sector Write
Protection *6
X
X
X
X
X
X
X
X
X
X
X
L
Read *
3
Legend : L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
*1: Manufacturer and device codes are accessed via a command register write sequence. SeeTable 4.
*2: Refer to section on Sector Group Protection.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = + 2.7 V to + 3.6V
*5: Also used for the extended sector group protection.
*6: Protect “outermost” 2 × 4 Kwords on both ends of the boot block sectors. (SA0, SA1, SA140 and SA141)
(Continued)
9
MBM29DL640E80/90/12
(Continued)
Table 3 MBM29DL640E User Bus Operations (BYTE = VIL)
Operation
CE OE WE
DQ15
/A-1
A0
A1
A2
A3
A6
A9 DQ7 to DQ0 RESET
WP/
ACC
Auto-Select
Manufacturer Code *1
L
L
H
L
L
L
L
L
L
VID
Code
H
X
Auto-Select Device
Code *1
L
L
H
L
H
L
L
L
L
VID
Code
H
X
Extended Auto-Select
Device Code *1
L
L
H
L
L
H
H
H
L
VID
Code
H
X
L
L
H
L
H
H
H
H
L
VID
Code
H
X
Read *3
L
L
H
A-1
A0
A1
A2
A3
A6
A9
DOUT
H
X
Standby
H
X
X
X
X
X
X
X
X
X
High-Z
H
X
Output Disable
L
H
H
X
X
X
X
X
X
X
High-Z
H
X
Write (Program/Erase)
L
H
L
A-1
A0
A1
A2
A3
A6
A9
DIN
H
X
Enable Sector Group
Protection *2, *4
L
VID
L
L
H
L
L
L
VID
X
H
X
Verify Sector Group
Protection *2, *4
L
L
H
L
L
H
L
L
L
VID
Code
H
X
Temporary Sector
Group Unprotection *5
X
X
X
X
X
X
X
X
X
X
X
VID
X
Reset (Hardware) /
Standby
X
X
X
X
X
X
X
X
X
X
High-Z
L
X
Boot Block Sector Write
Protection *6
X
X
X
X
X
X
X
X
X
X
X
X
L
Legend : L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
*1: Manufacturer and device codes may also be accessed via a command register write sequence. See Table 4.
*2: Refer to Sector Group Protection.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = + 2.7 V to + 3.6V
*5: Also used for extended sector group protection.
*6: Protects “outermost” 2 × 8 Kbytes on both ends of the boot block sectors. (SA0, SA1, SA140 and SA141)
10
MBM29DL640E80/90/12
Table 4 MBM29DL640E Command Definitions
Command
Sequence
Read/ *1
Reset
Read/ *1
Reset
Word
Byte
Word
Byte
Fourth Bus
Bus
First Bus Second Bus Third Bus
Fifth Bus
Sixth Bus
Write
Read/Write
Write Cycle Write Cycle Write Cycle
Write Cycle Write Cycle
CyCycle
cles
Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
1
3
555h
AAAh
3
Autoselect
Byte
Word
Byte
F0h
AAh
555h
Word
Program
XXXh
2AAh
555h
AAh
555h
AAAh
—
55h
2AAh
AAAh
4
—
55h
555h
AAh
2AAh
555h
55h
—
555h
AAAh
(BA)
555h
(BA)
AAAh
555h
AAAh
—
—
—
—
—
—
—
F0h
*7
RA
*7
RD
—
—
—
—
90h
*7
IA
*7
ID
—
—
—
—
A0h
PA
PD
—
—
—
—
Program
Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Program Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
Chip Erase
Sector
Erase
Word
Byte
Word
Byte
6
6
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
55h
555h
AAAh
555h
AAAh
80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
555h
AAAh
10h
55h
SA
30h
Erase Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Erase Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
Word
Set to
Fast Mode Byte
3
20h
—
—
—
—
—
—
Word
Fast
2
Program * Byte
2
Reset from Word
Fast Mode
Byte
*2
2
Extended
Sector
Group
Protection
*3
3
555h
AAAh
XXXh
XXXh
AAh
A0h
555h
PA
55h
555h
AAAh
PD
—
—
—
—
—
—
—
—
XXXh
*6
F0h
—
—
—
—
—
—
—
—
60h
SPA
60h
SPA
40h
*7
SPA
*7
SD
—
—
—
—
98h
—
—
—
—
—
—
—
—
—
—
BA
BA
2AAh
XXXh
90h
Word
XXXh
Byte
Word
Query *4
1
Byte
(BA)
55h
(BA)
AAh
(Continued)
11
MBM29DL640E80/90/12
(Continued)
Command
Sequence
Fourth Bus
Bus
First Bus Second Bus Third Bus
Fifth Bus
Sixth Bus
Write
Read/Write
Write Cycle Write Cycle Write Cycle
Write Cycle Write Cycle
CyCycle
cles
Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
HiddenROM Word
Entry
Byte
3
HiddenROM Word
Program *5
Byte
4
HiddenROM Word
Erase *5
Byte
6
HiddenROM
Exit *5
555h
AAAh
555h
AAAh
555h
AAAh
AAh
AAh
555h
Word
4
Byte
AAh
2AAh
555h
2AAh
555h
2AAh
555h
55h
55h
55h
2AAh
AAh
AAAh
55h
555h
555h
AAAh
555h
AAAh
555h
AAAh
(HRBA)
555h
(HRBA)
AAAh
88h
—
—
—
—
—
—
A0h
(HRA)
PA
PD
—
—
—
—
55h
HRA
30h
—
—
—
80h
90h
555h
AAAh
XXXh
AAh
00h
2AAh
555h
—
*1: Both of these reset commands are equivalent.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET = VID (except during HiddenROM mode).
*4: The valid address are A6 to A0.
*5: This command is valid during HiddenROM mode.
*6: The data “00h” is also acceptable.
*7: The fourth bus cycle is only for read.
Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector
Address (SA) , Bank Address (BA) and Sector Group Address (SPA) .
• Bus operations are defined in Tables 2 and 3.
• RA = Address of the memory location to be read
IA = Autoselect read address that sets both the bank address specified at (A21, A20, A19) and all the other
A6, A3, A2, A1, A0, (A-1).
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13 and
A12 will uniquely select any sector.
BA = Bank Address. Address setted by A21, A20, A19 will select Bank A, Bank B, Bank C and Bank D.
• RD = Data read from location RA during read operation.
ID = Device code/manufacture code for the address located by IA.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
• SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) =
(0, 0, 0, 1, 0) .
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
• HRA = Address of the HiddenROM area Word Mode : 000000h to 00007Fh
Byte Mode : 000000h to 0000FFh
• HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL)
• The system should generate the following address patterns:
Word Mode : 555h or 2AAh to addresses A10 to A0
Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• The command combinations not described in Table 4 are illegal.
• Command Combinations not described in Command Definitions table are illegal.
12
MBM29DL640E80/90/12
Table 5.1 MBM29DL640E Sector Group Protection Verify Autoselect Codes
Type
A21 to A12
A6
A3
A2
A1
A0
BA*3
VIL
VIL
VIL
VIL
VIL
BA*3
VIL
VIL
VIL
VIL
VIH
BA*3
VIL
VIH
VIH
VIH
VIL
BA*3
VIL
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIH
VIL
Byte
Manufacture’s
Code
Word
Byte
Device Code
Word
Byte
Word
Extended Device
Code*4
Byte
Word
Byte Sector Group
Word Addresses
Sector Group
Protection
A-1*1
Code (HEX)
VIL
04h
X
0004h
VIL
7Eh
X
227Eh
VIL
02h
X
2202h
VIL
01h
X
2201h
VIL
01h*2
X
0001h*2
*1 : A-1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address.
*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous
operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank
address needs to be indicated when Autoselect mode is read out at command mode, because then it enables
possible to activate simultaneous operation.
*4 : At WORD mode, a read cycle at address (BA) 01h (at BYTE mode, (BA) 02h) outputs device code. When 227Eh
(at BYTE mode, 7Eh) is output, it indicates that two additional codes, called Extended Device Codes, will be
required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA)
0Eh (at BYTE mode, (BA) 1Ch) , as well as at (BA) 0Fh (at BYTE mode, (BA) 1Eh) .
Table 5.2
Type
Manufacturer’s
Code
Device Code
Code
(B) *
Extended
Device Code
(B) *
DQ11
DQ10
DQ9
DQ8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
01h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(W) 2201h
Sector Group
Protection
DQ12
02h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(W) 2202h
(B) *
DQ13
7Eh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(W) 227Eh
(B) *
DQ14
04h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(W) 0004h
(B) *
DQ15
Extended Autoselect Code Table
0
0
1
0
0
0
1
0
01h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(W) 0001h
0
0
0
0
0
0
0
0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
(B) : Byte mode
(W) : Word mode
HI-Z : High-Z
* : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address.
13
MBM29DL640E80/90/12
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
Table 6.1 Sector Address Tables (Bank A)
Sector Address
Bank
Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sector
Size
(Kbytes/
Kwords)
( × 16)
Address Range
SA0
0
0
0
0
0
0
0
0
0
0
8/4
000000h to 001FFFh 000000h to 000FFFh
SA1
0
0
0
0
0
0
0
0
0
1
8/4
002000h to 003FFFh 001000h to 001FFFh
SA2
0
0
0
0
0
0
0
0
1
0
8/4
004000h to 005FFFh 002000h to 002FFFh
SA3
0
0
0
0
0
0
0
0
1
1
8/4
006000h to 007FFFh 003000h to 003FFFh
SA4
0
0
0
0
0
0
0
1
0
0
8/4
008000h to 009FFFh 004000h to 004FFFh
SA5
0
0
0
0
0
0
0
1
0
1
8/4
00A000h to 00BFFFh 005000h to 005FFFh
SA6
0
0
0
0
0
0
0
1
1
0
8/4
00C000h to 00DFFFh 006000h to 006FFFh
SA7
0
0
0
0
0
0
0
1
1
1
8/4
00E000h to 00FFFFh 007000h to 007FFFh
SA8
0
0
0
0
0
0
1
X
X
X
64/32
010000h to 01FFFFh 008000h to 00FFFFh
SA9
0
0
0
0
0
1
0
X
X
X
64/32
020000h to 02FFFFh 010000h to 017FFFh
SA10
Bank
SA11
A
SA12
0
0
0
0
0
1
1
X
X
X
64/32
030000h to 03FFFFh 018000h to 01FFFFh
0
0
0
0
1
0
0
X
X
X
64/32
040000h to 04FFFFh 020000h to 027FFFh
0
0
0
0
1
0
1
X
X
X
64/32
050000h to 05FFFFh 028000h to 02FFFFh
SA13
0
0
0
0
1
1
0
X
X
X
64/32
060000h to 06FFFFh 030000h to 037FFFh
SA14
0
0
0
0
1
1
1
X
X
X
64/32
070000h to 07FFFFh 038000h to 03FFFFh
SA15
0
0
0
1
0
0
0
X
X
X
64/32
080000h to 08FFFFh 040000h to 047FFFh
SA16
0
0
0
1
0
0
1
X
X
X
64/32
090000h to 09FFFFh 048000h to 04FFFFh
SA17
0
0
0
1
0
1
0
X
X
X
64/32
0A0000h to 0AFFFFh 050000h to 057FFFh
SA18
0
0
0
1
0
1
1
X
X
X
64/32
0B0000h to 0BFFFFh 058000h to 05FFFFh
SA19
0
0
0
1
1
0
0
X
X
X
64/32
0C0000h to 0CFFFFh 060000h to 067FFFh
SA20
0
0
0
1
1
0
1
X
X
X
64/32
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA21
0
0
0
1
1
1
0
X
X
X
64/32
0E0000h to 0EFFFFh 070000h to 077FFFh
SA22
0
0
0
1
1
1
1
X
X
X
64/32
0F0000h to 0FFFFFh 078000h to 07FFFFh
Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .
The address range is A21 : A0 if in word mode (BYTE = VIH) .
14
( × 8)
Address Range
MBM29DL640E80/90/12
Table 6.2 Sector Address Tables (Bank B)
Sector Address
Bank
Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sector
Size
(Kbytes/
Kwords)
( × 8)
Address Range
( × 16)
Address Range
SA23
0
0
1
0
0
0
0
X
X
X
64/32
100000h to 10FFFFh 080000h to 087FFFh
SA24
0
0
1
0
0
0
1
X
X
X
64/32
110000h to 11FFFFh 088000h to 08FFFFh
SA25
0
0
1
0
0
1
0
X
X
X
64/32
120000h to 12FFFFh 090000h to 097FFFh
SA26
0
0
1
0
0
1
1
X
X
X
64/32
130000h to 13FFFFh 098000h to 09FFFFh
SA27
0
0
1
0
1
0
0
X
X
X
64/32
140000h to 14FFFFh 0A0000h to 0A7FFFh
SA28
0
0
1
0
1
0
1
X
X
X
64/32
150000h to 15FFFFh 0A8000h to 0AFFFFh
SA29
0
0
1
0
1
1
0
X
X
X
64/32
160000h to 16FFFFh 0B0000h to 0B7FFFh
SA30
0
0
1
0
1
1
1
X
X
X
64/32
170000h to 17FFFFh 0B8000h to 0BFFFFh
SA31
0
0
1
1
0
0
0
X
X
X
64/32
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA32
0
0
1
1
0
0
1
X
X
X
64/32
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA33
0
0
1
1
0
1
0
X
X
X
64/32
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA34
0
0
1
1
0
1
1
X
X
X
64/32
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA35
0
0
1
1
1
0
0
X
X
X
64/32
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA36
0
0
1
1
1
0
1
X
X
X
64/32
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA37
Bank
SA38
B
SA39
0
0
1
1
1
1
0
X
X
X
64/32
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
0
0
1
1
1
1
1
X
X
X
64/32
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
0
1
0
0
0
0
0
X
X
X
64/32
200000h to 20FFFFh 100000h to 107FFFh
SA40
0
1
0
0
0
0
1
X
X
X
64/32
210000h to 21FFFFh 108000h to 10FFFFh
SA41
0
1
0
0
0
1
0
X
X
X
64/32
220000h to 22FFFFh 110000h to 117FFFh
SA42
0
1
0
0
0
1
1
X
X
X
64/32
230000h to 23FFFFh 118000h to 11FFFFh
SA43
0
1
0
0
1
0
0
X
X
X
64/32
240000h to 24FFFFh 120000h to 127FFFh
SA44
0
1
0
0
1
0
1
X
X
X
64/32
250000h to 25FFFFh 128000h to 12FFFFh
SA45
0
1
0
0
1
1
0
X
X
X
64/32
260000h to 26FFFFh 130000h to 137FFFh
SA46
0
1
0
0
1
1
1
X
X
X
64/32
270000h to 27FFFFh 138000h to 13FFFFh
SA47
0
1
0
1
0
0
0
X
X
X
64/32
280000h to 28FFFFh 140000h to 147FFFh
SA48
0
1
0
1
0
0
1
X
X
X
64/32
290000h to 29FFFFh 148000h to 14FFFFh
SA49
0
1
0
1
0
1
0
X
X
X
64/32
2A0000h to 2AFFFFh 150000h to 157FFFh
SA50
0
1
0
1
0
1
1
X
X
X
64/32
2B0000h to 2BFFFFh 158000h to 15FFFFh
SA51
0
1
0
1
1
0
0
X
X
X
64/32
2C0000h to 2CFFFFh 160000h to 167FFFh
SA52
0
1
0
1
1
0
1
X
X
X
64/32
2D0000h to 2DFFFFh 168000h to 16FFFFh
SA53
0
1
0
1
1
1
0
X
X
X
64/32
2E0000h to 2EFFFFh 170000h to 177FFFh
(Continued)
15
MBM29DL640E80/90/12
(Continued)
Sector Address
Bank
Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sector
Size
(Kbytes/
Kwords)
( × 16)
Address Range
SA54
0
1
0
1
1
1
1
X
X
X
64/32
2F0000h to 2FFFFFh 178000h to 17FFFFh
SA55
0
1
1
0
0
0
0
X
X
X
64/32
300000h to 30FFFFh 180000h to 187FFFh
SA56
0
1
1
0
0
0
1
X
X
X
64/32
310000h to 31FFFFh 188000h to 18FFFFh
SA57
0
1
1
0
0
1
0
X
X
X
64/32
320000h to 32FFFFh 190000h to 197FFFh
SA58
0
1
1
0
0
1
1
X
X
X
64/32
330000h to 33FFFFh 198000h to 19FFFFh
SA59
0
1
1
0
1
0
0
X
X
X
64/32
340000h to 34FFFFh 1A0000h to 1A7FFFh
SA60
0
1
1
0
1
0
1
X
X
X
64/32
350000h to 35FFFFh 1A8000h to 1AFFFFh
SA61
Bank
SA62
B
SA63
0
1
1
0
1
1
0
X
X
X
64/32
360000h to 36FFFFh 1B0000h to 1B7FFFh
0
1
1
0
1
1
1
X
X
X
64/32
370000h to 37FFFFh 1B8000h to 1BFFFFh
0
1
1
1
0
0
0
X
X
X
64/32
380000h to 38FFFFh 1C0000h to 1C7FFFh
SA64
0
1
1
1
0
0
1
X
X
X
64/32
390000h to 39FFFFh 1C8000h to 1CFFFFh
SA65
0
1
1
1
0
1
0
X
X
X
64/32
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA66
0
1
1
1
0
1
1
X
X
X
64/32
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA67
0
1
1
1
1
0
0
X
X
X
64/32
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA68
0
1
1
1
1
0
1
X
X
X
64/32
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA69
0
1
1
1
1
1
0
X
X
X
64/32
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA70
0
1
1
1
1
1
1
X
X
X
64/32
3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .
The address range is A21 : A0 if in word mode (BYTE = VIH) .
16
( × 8)
Address Range
MBM29DL640E80/90/12
Table 6.3 Sector Address Tables (Bank C)
Sector Address
Bank
Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sector
Size
(Kbytes/
Kwords)
( × 8)
Address Range
( × 16)
Address Range
SA71
1
0
0
0
0
0
0
X
X
X
64/32
400000h to 40FFFFh 200000h to 207FFFh
SA72
1
0
0
0
0
0
1
X
X
X
64/32
410000h to 41FFFFh 208000h to 20FFFFh
SA73
1
0
0
0
0
1
0
X
X
X
64/32
420000h to 42FFFFh 210000h to 217FFFh
SA74
1
0
0
0
0
1
1
X
X
X
64/32
430000h to 43FFFFh 218000h to 21FFFFh
SA75
1
0
0
0
1
0
0
X
X
X
64/32
440000h to 44FFFFh 220000h to 227FFFh
SA76
1
0
0
0
1
0
1
X
X
X
64/32
450000h to 45FFFFh 228000h to 22FFFFh
SA77
1
0
0
0
1
1
0
X
X
X
64/32
460000h to 46FFFFh 230000h to 237FFFh
SA78
1
0
0
0
1
1
1
X
X
X
64/32
470000h to 47FFFFh 238000h to 23FFFFh
SA79
1
0
0
1
0
0
0
X
X
X
64/32
480000h to 48FFFFh 240000h to 247FFFh
SA80
1
0
0
1
0
0
1
X
X
X
64/32
490000h to 49FFFFh 248000h to 24FFFFh
SA81
1
0
0
1
0
1
0
X
X
X
64/32
4A0000h to 4AFFFFh 250000h to 257FFFh
SA82
1
0
0
1
0
1
1
X
X
X
64/32
4B0000h to 4BFFFFh 258000h to 25FFFFh
SA83
1
0
0
1
1
0
0
X
X
X
64/32
4C0000h to 4CFFFFh 260000h to 267FFFh
SA84
1
0
0
1
1
0
1
X
X
X
64/32
4D0000h to 4DFFFFh 268000h to 26FFFFh
SA85
1
0
0
1
1
1
0
X
X
X
64/32
4E0000h to 4EFFFFh 270000h to 277FFFh
Bank SA86
C
SA87
1
0
0
1
1
1
1
X
X
X
64/32
4F0000h to 4FFFFFh 278000h to 27FFFFh
1
0
1
0
0
0
0
X
X
X
64/32
500000h to 50FFFFh 280000h to 287FFFh
SA88
1
0
1
0
0
0
1
X
X
X
64/32
510000h to 51FFFFh 288000h to 28FFFFh
SA89
1
0
1
0
0
1
0
X
X
X
64/32
520000h to 52FFFFh 290000h to 297FFFh
SA90
1
0
1
0
0
1
1
X
X
X
64/32
530000h to 53FFFFh 298000h to 29FFFFh
SA91
1
0
1
0
1
0
0
X
X
X
64/32
540000h to 54FFFFh 2A0000h to 2A7FFFh
SA92
1
0
1
0
1
0
1
X
X
X
64/32
550000h to 55FFFFh 2A8000h to 2AFFFFh
SA93
1
0
1
0
1
1
0
X
X
X
64/32
560000h to 56FFFFh 2B0000h to 2B7FFFh
SA94
1
0
1
0
1
1
1
X
X
X
64/32
570000h to 57FFFFh 2B8000h to 2BFFFFh
SA95
1
0
1
1
0
0
0
X
X
X
64/32
580000h to 58FFFFh 2C0000h to 2C7FFFh
SA96
1
0
1
1
0
0
1
X
X
X
64/32
590000h to 59FFFFh 2C8000h to 2CFFFFh
SA97
1
0
1
1
0
1
0
X
X
X
64/32
5A0000h to 5AFFFFh 2D0000h to 2D7FFFh
SA98
1
0
1
1
0
1
1
X
X
X
64/32
5B0000h to 5BFFFFh 2D8000h to 2DFFFFh
SA99
1
0
1
1
1
0
0
X
X
X
64/32
5C0000h to 5CFFFFh 2E0000h to 2E7FFFh
SA100
1
0
1
1
1
0
1
X
X
X
64/32
5D0000h to 5DFFFFh 2E8000h to 2EFFFFh
SA101
1
0
1
1
1
1
0
X
X
X
64/32
5E0000h to 5EFFFFh 2F0000h to 2F7FFFh
SA102
1
0
1
1
1
1
1
X
X
X
64/32
5F0000h to 5FFFFFh 2F8000h to 2FFFFFh
(Continued)
17
MBM29DL640E80/90/12
(Continued)
Sector Address
Bank
Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sector
Size
(Kbytes/
Kwords)
( × 16)
Address Range
SA103
1
1
0
0
0
0
0
X
X
X
64/32
600000h to 60FFFFh 300000h to 307FFFh
SA104
1
1
0
0
0
0
1
X
X
X
64/32
610000h to 61FFFFh 308000h to 30FFFFh
SA105
1
1
0
0
0
1
0
X
X
X
64/32
620000h to 62FFFFh 310000h to 317FFFh
SA106
1
1
0
0
0
1
1
X
X
X
64/32
630000h to 63FFFFh 318000h to 31FFFFh
SA107
1
1
0
0
1
0
0
X
X
X
64/32
640000h to 64FFFFh 320000h to 327FFFh
SA108
1
1
0
0
1
0
1
X
X
X
64/32
650000h to 65FFFFh 328000h to 32FFFFh
SA109
1
1
0
0
1
1
0
X
X
X
64/32
660000h to 66FFFFh 330000h to 337FFFh
Bank SA110
C
SA111
1
1
0
0
1
1
1
X
X
X
64/32
670000h to 67FFFFh 338000h to 33FFFFh
1
1
0
1
0
0
0
X
X
X
64/32
680000h to 68FFFFh 340000h to 347FFFh
SA112
1
1
0
1
0
0
1
X
X
X
64/32
690000h to 69FFFFh 348000h to 34FFFFh
SA113
1
1
0
1
0
1
0
X
X
X
64/32
6A0000h to 6AFFFFh 350000h to 357FFFh
SA114
1
1
0
1
0
1
1
X
X
X
64/32
6B0000h to 6BFFFFh 358000h to 35FFFFh
SA115
1
1
0
1
1
0
0
X
X
X
64/32
6C0000h to 6CFFFFh 360000h to 367FFFh
SA116
1
1
0
1
1
0
1
X
X
X
64/32
6D0000h to 6DFFFFh 368000h to 36FFFFh
SA117
1
1
0
1
1
1
0
X
X
X
64/32
6E0000h to 6EFFFFh 370000h to 377FFFh
SA118
1
1
0
1
1
1
1
X
X
X
64/32
6F0000h to 6FFFFFh 378000h to 37FFFFh
Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .
The address range is A21 : A0 if in word mode (BYTE = VIH) .
18
( × 8)
Address Range
MBM29DL640E80/90/12
Table 6.4 Sector Address Tables (Bank D)
Sector Address
Bank
Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sector
Size
(Kbytes/
Kwords)
( × 8)
Address Range
( × 16)
Address Range
SA119 1
1
1
0
0
0
0
X
X
X
64/32
700000h to 70FFFFh 380000h to 387FFFh
SA120 1
1
1
0
0
0
1
X
X
X
64/32
710000h to 71FFFFh 388000h to 38FFFFh
SA121 1
1
1
0
0
1
0
X
X
X
64/32
720000h to 72FFFFh 390000h to 397FFFh
SA122 1
1
1
0
0
1
1
X
X
X
64/32
730000h to 73FFFFh 398000h to 39FFFFh
SA123 1
1
1
0
1
0
0
X
X
X
64/32
740000h to 74FFFFh 3A0000h to 3A7FFFh
SA124 1
1
1
0
1
0
1
X
X
X
64/32
750000h to 75FFFFh 3A8000h to 3AFFFFh
SA125 1
1
1
0
1
1
0
X
X
X
64/32
760000h to 76FFFFh 3B0000h to 3B7FFFh
SA126 1
1
1
0
1
1
1
X
X
X
64/32
770000h to 77FFFFh 3B8000h to 3BFFFFh
SA127 1
1
1
1
0
0
0
X
X
X
64/32
780000h to 78FFFFh 3C0000h to 3C7FFFh
SA128 1
1
1
1
0
0
1
X
X
X
64/32
790000h to 79FFFFh 3C8000h to 3CFFFFh
SA129 1
Bank
SA130 1
D
SA131 1
1
1
1
0
1
0
X
X
X
64/32
7A0000h to 7AFFFFh 3D0000h to 3D7FFFh
1
1
1
0
1
1
X
X
X
64/32
7B0000h to 7BFFFFh 3D8000h to 3DFFFFh
1
1
1
1
0
0
X
X
X
64/32
7C0000h to 7CFFFFh 3E0000h to 3E7FFFh
SA132 1
1
1
1
1
0
1
X
X
X
64/32
7D0000h to 7DFFFFh 3E8000h to 3EFFFFh
SA133 1
1
1
1
1
1
0
X
X
X
64/32
7E0000h to 7EFFFFh 3F0000h to 3F7FFFh
SA134 1
1
1
1
1
1
1
0
0
0
8/4
7F0000h to 7F1FFFh 3F8000h to 3F8FFFh
SA135 1
1
1
1
1
1
1
0
0
1
8/4
7F2000h to 7F3FFFh 3F9000h to 3F9FFFh
SA136 1
1
1
1
1
1
1
0
1
0
8/4
7F4000h to 7F5FFFh 3FA000h to 3FAFFFh
SA137 1
1
1
1
1
1
1
0
1
1
8/4
7F6000h to 7F7FFFh 3FB000h to 3FBFFFh
SA138 1
1
1
1
1
1
1
1
0
0
8/4
7F8000h to 7F9FFFh 3FC000h to 3FCFFFh
SA139 1
1
1
1
1
1
1
1
0
1
8/4
7FA000h to 7FBFFFh 3FD000h to 3FDFFFh
SA140 1
1
1
1
1
1
1
1
1
0
8/4
7FC000h to 7FDFFFh 3FE000h to 3FEFFFh
SA141 1
1
1
1
1
1
1
1
1
1
8/4
7FE000h to 7FFFFFh 3FF000h to 3FFFFFh
Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .
The address range is A21 : A0 if in word mode (BYTE = VIH) .
19
MBM29DL640E80/90/12
Table 7 Sector Group Address Table
Sector Group
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
0
1
1
1
SA7
0
1
1
0
X
X
X
SA8 to SA10
1
1
SGA8
0
0
0
0
0
SGA9
0
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
0
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
0
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
0
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA15
0
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA16
0
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA17
0
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA18
0
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA19
0
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA20
0
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA21
0
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA22
0
1
1
1
0
X
X
X
X
X
SA63 to SA66
SGA23
0
1
1
1
1
X
X
X
X
X
SA67 to SA70
(Continued)
20
MBM29DL640E80/90/12
(Continued)
Sector Group
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA24
1
0
0
0
0
X
X
X
X
X
SA71 to SA74
SGA25
1
0
0
0
1
X
X
X
X
X
SA75 to SA78
SGA26
1
0
0
1
0
X
X
X
X
X
SA79 to SA82
SGA27
1
0
0
1
1
X
X
X
X
X
SA83 to SA86
SGA28
1
0
1
0
0
X
X
X
X
X
SA87 to SA90
SGA29
1
0
1
0
1
X
X
X
X
X
SA91 to SA94
SGA30
1
0
1
1
0
X
X
X
X
X
SA95 to SA98
SGA31
1
0
1
1
1
X
X
X
X
X
SA99 to SA102
SGA32
1
1
0
0
0
X
X
X
X
X
SA103 to SA106
SGA33
1
1
0
0
1
X
X
X
X
X
SA107 to SA110
SGA34
1
1
0
1
0
X
X
X
X
X
SA111 to SA114
SGA35
1
1
0
1
1
X
X
X
X
X
SA115 to SA118
SGA36
1
1
1
0
0
X
X
X
X
X
SA119 to SA122
SGA37
1
1
1
0
1
X
X
X
X
X
SA123 to SA126
SGA38
1
1
1
1
0
X
X
X
X
X
SA127 to SA130
0
0
0
1
X
X
X
SA131 to SA133
1
0
SGA39
1
1
1
1
1
SGA40
1
1
1
1
1
1
1
0
0
0
SA134
SGA41
1
1
1
1
1
1
1
0
0
1
SA135
SGA42
1
1
1
1
1
1
1
0
1
0
SA136
SGA43
1
1
1
1
1
1
1
0
1
1
SA137
SGA44
1
1
1
1
1
1
1
1
0
0
SA138
SGA45
1
1
1
1
1
1
1
1
0
1
SA139
SGA46
1
1
1
1
1
1
1
1
1
0
SA140
SGA47
1
1
1
1
1
1
1
1
1
1
SA141
21
MBM29DL640E80/90/12
Table 8 Common Flash Memory Interface Code
Description
Query-unique ASCII string “QRY”
Primary OEM Command Set
02h : AMD/FJ standard type
Address for Primary Extended Table
Alternate OEM Command Set
(00h = not applicable)
Address for Alternate OEM Extended
Table
VCC Min Voltage (write/erase)
DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV
VCC Max Voltage (write/erase)
DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV
VPP Min voltage
VPP Max voltage
Typical timeout per single byte/word write
2N µs
Typical timeout for Min size
buffer write 2N µs
Typical timeout per individual sector
erase 2N ms
Typical timeout for full chip erase 2N ms
Max timeout for byte/word write 2N times
typical
Max timeout for buffer write 2N times
typical
Max timeout per individual sector erase
2N times typical
Max timeout for full chip erase 2N times
typical
Device Size = 2N byte
Flash Device Interface
description 02h: ×8 / ×16
Max number of bytes in
multi-byte write = 2N
Number of Erase Block Regions within
device
Erase Block Region 1 Information
bit15 to bit0: y = number of sectors
bit31 to bit16: z = size
(z × 256 bytes)
Erase Block Region 2 Information
bit15 to bit0: y = number of sectors
bit31 to bit16: z = size
(z × 256 bytes)
Erase Block Region 3 Information
bit15 to bit0: y = number of sectors
bit31 to bit16: z = size
(z × 256 bytes)
22
A6 to A0 DQ15 to DQ0
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
1Bh
0027h
1Ch
0036h
1Dh
1Eh
0000h
0000h
1Fh
0004h
20h
0000h
21h
000Ah
22h
0000h
23h
0005h
24h
0000h
25h
0004h
26h
0000h
27h
28h
29h
2Ah
2Bh
0017h
0002h
0000h
0000h
0000h
2Ch
0003h
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
0007h
0000h
0020h
0000h
007Dh
0000h
0000h
0001h
0007h
0000h
0020h
0000h
Description
Query-unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
00h = Required
Erase Suspend
02h = To Read & Write
Sector Protection
00h = Not Supported
X = Number of sectors per group
Sector Temporary
Unprotection
01h = Supported
Sector Protection Algorithm
Dual Operation
00h = Not Supported
X = Total number of sectors in all banks
except Bank 1
Burst Mode Type
00h = Not Supported
Page Mode Type
00h = Not Supported
VACC (Acceleration) Supply
Minimum
DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV
VACC (Acceleration) Supply
Maximum
DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV
Boot Type
Program Suspend
00h = Not Supported
01h = Supported
Bank Organization
X = Total Number of Banks
Bank A Region Information
X = Number of sectors in Bank A
Bank B Region Information
X = Number of sectors in Bank B
Bank C Region Information
X = Number of sectors in Bank C
Bank D Region Information
X = Number of sectors in Bank D
A6 to A0 DQ15 to DQ0
40h
41h
42h
43h
44h
0050h
0052h
0049h
0031h
0033h
45h
0000h
46h
0002h
47h
0001h
48h
0001h
49h
0004h
4Ah
0077h
4Bh
0000h
4Ch
0000h
4Dh
0085h
4Eh
0095h
4Fh
0001h
50h
0001h
57h
0004h
58h
0017h
59h
0030h
5Ah
0030h
5Bh
0017h
MBM29DL640E80/90/12
■ FUNCTIONAL DESCRIPTION
Simultaneous Operation
The device features functions that enable reading of data from one memory bank while a program or erase
operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features
(read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank
address (A21, A20, A19) with zero latency. The device consists of the following four banks :
Bank A : 8 × 8 KB and 15 × 64 KB; Bank B : 48 × 64 KB; Bank C : 48 × 64 KB; Bank D : 8 × 8 KB and 15 × 64 KB.
The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks,
and Bank 2, a bank consisting of the three remaining banks. (See Table 9.) This is what we call a “FlexBank”,
for example, the rest of banks B, C and D to let the system read while Bank A is in the process of program (or
erase) operation. However, the different types of operations for the three banks are impossible, e.g. Bank A
writing, Bank B erasing, and Bank C reading out. With this “FlexBank”, as described in Table 10, the system
gets to select from four combinations of data volume for Bank 1 and Bank 2, which works well to meet the system
requirement. The simultaneous operation cannot execute multi-function mode in the same bank. Table 11 shows
the possible combinations for simultaneous operation. (Refer to Figure 11 Bank-to-Bank Read/Write Timing
Diagram.)
Table 9 FlexBankTM Architecture
Bank 1
Bank 2
Bank
Splits
Volume
Combination
Volume
Combination
1
8 Mbit
Bank A
56 Mbit
Bank B, C, D
2
24 Mbit
Bank B
40 Mbit
Bank A, C, D
3
24 Mbit
Bank C
40 Mbit
Bank A, B, D
4
8 Mbit
Bank D
56 Mbit
Bank A, B, C
Table 10
Bank 1
Bank
Splits Volume Combination
Example of Virtual Banks Combination
Bank 2
Sector Size
Volume Combination
Sector Size
Bank B
+
Bank C
+
Bank D
8 × 8 Kbyte/4 Kword
+
111 × 64 Kbyte/32 Kword
1
8 Mbit
Bank A
8 × 8 Kbyte/4 Kword
+
56 Mbit
15 × 64 Kbyte/32 Kword
2
16 Mbit
Bank A
+
Bank D
16 × 8 Kbyte/4 Kword
+
48 Mbit
30 × 64 Kbyte/32 Kword
Bank B
+
Bank C
96 × 64 Kbyte/32 Kword
16 × 8 Kbyte/4 Kword
+
78 × 64 Kbyte/32 Kword
8 × 8 Kbyte/4 Kword
+
63 × 64 Kbyte/32 Kword
3
24 Mbit
Bank B
48 × 64 Kbyte/32 Kword 40 Mbit
Bank A
+
Bank C
+
Bank D
4
32 Mbit
Bank A
+
Bank B
8 × 8 Kbyte/4 Kword
+
32 Mbit
63 × 64 Kbyte/32 Kword
Bank C
+
Bank D
Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which
a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,
neither Bank A nor Bank B is read out. They would output the sequence flag once they are selected.
Meanwhile the system would get to read from either Bank C or Bank D.
23
MBM29DL640E80/90/12
Table 11 Simultaneous Operation
Case
Bank 1 Status
Bank 2 Status
1
Read mode
Read mode
2
Read mode
Autoselect mode
3
Read mode
Program mode
4
Read mode
Erase mode *
5
Autoselect mode
Read mode
6
Program mode
Read mode
7
Erase mode *
Read mode
* : By writing erase suspend command on the bank address of sector being erased, the erase operation becomes
suspended so that it enables reading from or programming the remaining sectors.
Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. The Bank consists
of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the Banks.
Read Mode
The device has two control functions which are required in order to obtain data at the outputs. CE is the power
control and should be used for a device selection. OE is the output control and should be used to gate data to
the output pins.
Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access
time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable
access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses
have been stable for at least tACC-tOE time) . When reading out data without changing addresses after power-up,
it is necessary to input hardware reset or to change CE pin from “H” or “L”
Standby Mode
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and
the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET input held at VCC ± 0.3 V. Under
this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active
current (ICC2) is required even if CE = “H”. The device can be read with standard access time (tCE) from either of
these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V
(CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is
set high, the device requires tRH as a wake-up time for output to be valid for read access.
During standby mode, the output is in the high impedance state, regardless of OE input.
24
MBM29DL640E80/90/12
Automatic Sleep Mode
Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in
applications such as handy terminal, which requires low power consumption.
To activate this mode, the device automatically switches itself to low power mode when the device addresses
remain stable during access time of 150 ns. It is not necessary to control CE, WE and OE in this mode. In this
mode the current consumed is typically 1 µA (CMOS Level) .
During simultaneous operation, VCC active current (ICC2) is required.
Since the data are latched during this mode, the data are continuously read out. When the addresses are
changed, the mode is automatically canceled and the device reads the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH) , output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The Autoselect mode allows the reading out of a binary code and identifies its manufacturer and type.It is intended
for use by programming equipment for the purpose of automatically matching the device to be programmed with
its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force VID on address pin A9. Three identifier bytes may
then be sequenced from the device outputs by toggling addresses. All addresses are DON’T CARES except A6,
A3, A2, A1 and A0 (A-1) . (See Tables 2 and 3.)
The manufacturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is
illustrated in Table 4. (Refer to Autoselect Command section.)
In the command Autoselect mode, the bank addresses BA; (A21, A20, A19) must point to a specific bank during
the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while
array data can be read from the other bank.
In WORD mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle
at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended
Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes
at addresses of 0Eh and 0Fh. Notice that the above applies to WORD mode; the addresses and codes differ
from those of BYTE mode. (Refer to Sector Group Protection Verify Autoselect codes and Extended Autoselect
code Table. )
In the case of applying VID on A9, since both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation
cannot be executed.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as input to the internal state machine. The state machine output dictates the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever happens later, while data is latched on the rising edge of WE or CE, whichever
happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
25
MBM29DL640E80/90/12
Sector Group Protection
The device features hardware sector group protection. This feature will disable both program and erase operations in any combination of forty eight sector groups of memory. (See Table 7) . The user‘s side can use the
sector group protection using programming equipment. The device is shipped with all sector groups that are
unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE =
VIL and A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13 and
A12) should be set to the sector to be protected. Tables 6.1 to 6.4 define the sector address for each of the one
hundred forty-two (142) individual sectors, and Table 7 defines the sector group address for each of the forty
eight (48) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE
pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during
the WE pulse. See Figures 18 and 26 for sector group protection waveforms and algorithms.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14,
A13 and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logic “1” code at device output DQ0 for a
protected sector. Otherwise the device will produce “0” for unprotected sectors. In this mode, the lower order
addresses, except for A0, A1, A2, A3 and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for
Autoselect manufacturer and device codes. A-1 requires to apply VIL on byte mode.
Whether the sector group is protected in the system can be determined by writing an Autoselect command.
Performing a read operation at the address location (BA) XX02h, where the higher order addresses (A21, A20,
A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address, will produce a logical “1” at DQ0
for a protected sector group. Note that the bank addresses (A21, A20, A19) must be pointing to a specific bank
during the third write bus cycle of the Autoselect command. Then the Autoselect data can be read from that
bank while array data can still be read from the other bank. To read Autoselect data from the other bank, it must
be reset to read mode and then write the Autoselect command to the other bank. See Tables 5.1 and 5.2 for
Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the device in order to change
data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During
this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be
protected again. Refer to Figures 19 and 27.
Extended Sector Group Protection
In addition to normal sector group protection, the device has Extended Sector Group Protection as extended
function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command
sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins.
The extended sector group protection requires VID on RESET pin only. With this condition the operation is initiated
by writing the set-up command (60h) in the command register. Then the sector group addresses pins (A21, A20,
A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group
to be protected (setting VIL for the other addresses pins is recommended) , and an extended sector group
protection command (60h) should be written. A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12)
and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set a command (40h) should be written. Following the command
write, a logic “1” at device output DQ0 will produce a protected sector in the read operation. If the output is logic
“0”, write the extended sector group protection command (60h) again. To terminate the operation, it is necessary
to set RESET pin to VIH. (Refer to Figures 20 and 28.)
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MBM29DL640E80/90/12
RESET
Hardware Reset
The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to
be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process
of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after
the RESET pin is driven low. Furthermore, once the RESET pin goes high the device requires an additional “tRH”
before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the
duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program
or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal
should be ignored during the RESET pulse. See Figure 14 for the timing diagram. Refer to Temporary Sector
Group Unprotection for additional functionality.
Boot Block Sector Protection
The Write Protection function provides a hardware method of protecting certain boot sectors without using VID.
This function is one of two provided by the WP/ACC pin.
If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two
outermost 8 Kbytes on both ends of boot sectors (SA0, SA1, SA140, and SA141) independently of whether
those sectors are protected or unprotected using the method described in “Sector Group Protection.”
If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8 Kbyte on both
ends of boot sectors were last set to be protected or unprotected. Sector Group Protection or Unprotection for
these four sectors depends on whether they were last protected or unprotected using the method described in
“Sector Group Protection.”
Accelerated Program Operation
The device offers accelerated program operation which enables programming in high speed. If the system asserts
VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program
operation will reduce to about 60%. This function is primarily intended to allow high speed programming, so
caution is needed as the sector group will temporarily be unprotected.
The system would use a fast program command sequence when programming during acceleration mode.
Set command to fast mode and reset command from fast mode are not necessary. When the device enters the
acceleration mode, the device is automatically set to fast mode. Therefore, the present sequence could be used
for programming and detection of completion during acceleration mode.
Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/
ACC pin while programming. See Figure 21.
Erase operation at Acceleration mode is strictly prohibited.
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MBM29DL640E80/90/12
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Some
commands require Bank Address (BA) input. When command sequences are input into a bank reading, the
commands have priority over the reading. Table 4 shows the valid register command sequences. Note that the
Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is
in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the
Program operation is in progress. Moreover, Read/Reset commands are functionally equivalent, resetting the
device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits
are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/
Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the Read/Reset state. In this case a command sequence is not required
in order to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to AC Read Characteristics and Timing Diagram for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,
manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a higher voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and actual data from the memory cell can be read from another bank. The
higher order address (A21, A20, A19) required for reading out the manufacture and device codes demands the
bank address (BA) set at the third write cycle.
Following the command write, in WORD mode, a read cycle from address (BA) 00h returns the manufacturer’s
code (Fujitsu = 04h) . And a read cycle at address (BA) 01h outputs device code. When 227Eh was output, this
indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may
continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. Notice
that the above applies to WORD mode. The addresses and codes differ from those of BYTE mode. Refer to
Sector Group Protection Verify Autoselect code and Extended Autoselect code table.
The sector state (protection or unprotection) will be informed by address (BA) 02h for × 16 ( (BA) 04h for × 8) .
Scanning the sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1,
A0) = (0, 0, 0, 1, 0) will produce a logic “1” at device output DQ0 for a protected sector group. The programming
verification should be performed by verifying sector group protection on the protected sector. (See Tables 2 and 3.)
The manufacture and device codes can be read from the selected bank. To read the manufacture and device
codes and Sector Group Protection status from a non-selected bank, it is necessary to write the Read/Reset
command sequence into the register. Autoselect command should then be written into the bank to be read.
If the software (program code) for Autoselect command is stored in the Flash memory, the device and manufacture codes should be read from the other bank, which does not contain the software.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To
execute the Autoselect command during the operation, Read/Reset command sequence must be written before
the Autoselect command.
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MBM29DL640E80/90/12
Byte/Word Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts
programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required
to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit)
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched (see Table 12,
Hardware Sequence Flags). Therefore, the device requires that a valid address to the device be supplied by the
system in this particular instance. Hence, Data Polling must be performed at the memory location which is being
programmed.
If hardware reset occurs during the programming operation, the data being written is not guaranteed.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert from “0”s to “1”s.
Figure 22 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Program Suspend/Resume
The Program Suspend command allows the system to interrupt a program operation so that data can be read
from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation
immediately suspends the programming. The Program Suspend command may also be issued during a programming operation while an erase is suspended. The bank addresses of sector being programmed should be
set when writing the Program Suspend command.
When the Program Suspend command is written during a programming process, the device halts the program
operation within 1 µs and updates the status bits.
After the program operation has been suspended, the system can read data from any address. The data at
program-suspended address is not valid. Normal read timing and command definitions apply.
After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses
of sectors being suspended should be set when writing the Program Resume command. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program
operation. See “Write Operation Status” for more information.
The system may also write the Autoselect command sequence when the device in the Program Suspend mode.
The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are
not stored in the memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information.
The system must write the Program Resume command (address bits are “Bank Address”) to exit from the
Program Suspend mode and continue the programming operation. Further writes of the Resume command are
ignored. Another Program Suspend command can be written after the device has resumed programming.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence, the device will automatically program and verify the entire memory for an all29
MBM29DL640E80/90/12
zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence, and terminates when the data on DQ7 is “1” (see Write Operation Status section), at which time the
device returns to the read mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Figure 23 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever
happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE, whichever happens
first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation
begins.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 4. This sequence
is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than “tTOW”. Otherwise, that command will not be accepted and
erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee such
a condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out of “tTOW” from
the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector Erase command
(s) . If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out window, the
timer is reset (monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector
Erase Timer). Resetting the device once execution has begun will corrupt the data in the sector. In that case,
restart the erase on those sectors and allow them to complete (refer to Write Operation Status section for Sector
Erase Timer operation). Loading the sector erase buffer may be done in any sequence and with any number of
sectors (0 to 141) .
Sector erase does not require the user to program the device before erase. The device automatically programs
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
a sector, the rest remain unaffected. The system is not required to provide any controls or timings during these
operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) or
RY/BY.
The sector erase begins after the “tTOW” time-out from the rising edge of CE or WE, whichever happens first, for
the last sector erase command pulse and terminates when the data on DQ7 is “1” (see Write Operation Status
section), at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of
Sector Erase
In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which
sectors being erased belong cannot be performed.
Figure 23 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt Sector Erase operation and then reads data from or
programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation
which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector
Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.
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MBM29DL640E80/90/12
Writing the Erase Resume command (30h) resumes the erase operation. The bank address of sector being
erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum
of “tSPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the
RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must
use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode, except that the data must be read from
sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle (see the section on DQ2).
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, it is
the same as programming in the regular Program mode, except that the data must be programmed to sectors
that are not erase-suspended. Reading successively from the erase-suspended sector while the device is in the
erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is
detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6), which is the same as the
regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from
any address within bank being erase-suspended.
To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase
suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed erasing.
Extended Command
(1) Fast Mode
The device has a Fast Mode function. It dispenses with the initial two unclock cycles required in the standard
program command sequence by writing the Fast Mode command into the command register. In this mode, the
required bus cycle for programming consists of two bus cycles instead of four in standard program command.
The read operation is also executed after exiting from the fast mode. During the Fast mode, do not write any
commands other than the Fast program/Fast mode reset command. To exit from this mode, it is necessary to
write Fast Mode Reset command into the command register. The first cycle must contain the bank address (see
Figure 29) .The VCC active current is required even if CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, programming can be executed with two bus cycle operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) (see Figure 29) .
(3) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and the host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98h) into the command register. The bank address
should be set when writing this command. Then the device information can be read from the bank, and data
from the memory cell can be read from the another bank. The higher order address (A21, A20, A19) required for
reading out the CFI Codes requires that the bank address (BA) be set at the write cycle. Following the command
write, a read cycle from specific address retrieves device information. Please note that output data of upper byte
(DQ15 to DQ8) is “0” in word mode (16 bit) read. Refer to CFI code table (Table 12) . To terminate operation, it is
necessary to write the read/reset command sequence into the register.
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MBM29DL640E80/90/12
HiddenROM Region
The HiddenROM feature provides a Flash memory region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the HiddenROM region is protected, any further
modification of that region becomes impossible. This ensures the security of the ESN once the product is shipped
to the field.
The HiddenROM region is 256 bytes in length and is stored at the same address of the “outermost” 8 Kbyte
boot sector in Bank A. The device occupies the address of the byte mode 000000h to 0000FFh (word mode
000000h to 00007Fh) . After the system has written the Enter HiddenROM command sequence, the system
may read the HiddenROM region by using the addresses normally occupied by the boot sector (particular area
of SA0) . That is, the device sends all commands that would normally be sent to the boot sector (particular area
of SA0) to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM
command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the
device reverts to sending commands to the boot sector.
When reading the HiddenROM region, either change addresses or change CE pin from “H” to “L”. The same
procedure should be taken (changing addresses or CE pin from “H” to “L”) after the system issues the Exit
HiddenROM command sequence to read actual memory cell data.
HiddenROM Entry Command
The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and
to unable the change of the code once set. Programming is allowed in this area until it is protected. However,
once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required.
The HiddenROM area is 256 bytes. This area is normally the “outermost” 8 Kbyte boot block area in Bank A.
Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called
HiddenROM mode when the HiddenROM area appears.
Sectors other than the boot block area SA0 can be read during HiddenROM mode. Read/program of the
HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit
the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset
command sequence.
In HiddenROM mode, the simultaneous operation cannot be executed multi-function mode between the
HiddenROM area and the Bank A. Note that any other commands should not be issued other than the HiddenROM program/protection/reset commands during the HiddenROM mode. When you issue the other commands
including the suspend resume, send the HiddenROM reset command first to exit the HiddenROM mode and
then issue each command.
HiddenROM Program Command
To program the data to the HiddenROM area, write the HiddenROM program command sequence during
HiddenROM mode. This command is the same as the usual program command, except that it needs to write
the command during HiddenROM mode. Therefore the detection of completion method is the same as in the
past, using the DQ7 data polling, DQ6 toggle bit and RY/BY pin. You should pay attention to the address to be
programmed. If an address not in the HiddenROM area is selected, the previous data will be deleted.
During the write into the HiddenROM region, the program suspend command issuance is prohibited.
HiddenROM Protect Command
There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command
(60h) , set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the
sector group protect command (60h) during the HiddenROM mode. The same command sequence may be used
because it is the same as the extension sector group protect in the past, except that it is in the HiddenROM
mode and does not apply high voltage to the RESET pin. Please refer to “Function Explanation Extended Sector
Group Protection” for details of extension sector group protect setting.
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MBM29DL640E80/90/12
The other method is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area
and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the
protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address
in the HiddenROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear
on DQ0 if it is not protected. Apply write pulse again. The same command sequence could be used for the above
method because other than the HiddenROM mode, it is the same as the sector group protect previously mentioned. Refer to “Function Explanation Secor Group Protection” for details of the sector group protect setting.
Take note that other sector groups will be affected if an address other than those for the HiddenROM area is
selected for the sector group address, so please be careful. Pay close attention that once it is protected, protection
CANNOT BE CANCELLED.
Write Operation Status
Detailed in Hardware Sequence Flags are all the status flags which determine the status of the bank for the
current mode operation. The read operation from the bank which does not operate Embedded Algorithm returns
data of memory cells. These bits offer a method for determining whether an Embedded Algorithm is properly
completed. The information on DQ2 is address-sensitive. This means that if an address from an erasing sector
is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing
sector is consecutively read. This allows users to determine which sectors are in erase.
The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For
example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy
bank > , [2] < non-busy bank > , [3] < busy bank > , the DQ6 toggles in the case of [1] and [3]. In case of [2], the
data of memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not
be toggled in [1] and [3].
In the erase suspend read mode, DQ2 is toggled in [1] and [3]. In case of [2], the data of memory cell is output.
Table 12
Hardware Sequence Flags
Status
Embedded Program Algorithm
Embedded Erase Algorithm
Erase Suspend Read
(Erase Suspended Sector)
Erase
Erase Suspend Read
Suspended
(Non-Erase Suspended Sector)
Mode
In Progress
Erase Suspend Program
(Non-Erase Suspended Sector)
Program Suspend Read
(Program Suspended Sector)
Program
Suspended Program Suspend Read
Mode
(Non-Program Suspended
Sector)
Embedded Program Algorithm
Embedded Erase Algorithm
Exceeded
Time Limits Erase
Erase Suspend Program
Suspended
(Non-Erase Suspended Sector)
Mode
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle *1
1
1
0
0
Toggle
Data
Data
Data
Data
Data
DQ7
Toggle
0
0
1 *2
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
DQ7
Toggle
1
0
1
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
*1: Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.
*2: Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit.
33
MBM29DL640E80/90/12
DQ7
Data Polling
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a
complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to
read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an
attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in Figure 24.
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequences.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid.
If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change
asynchronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ7 at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples
the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm
operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to
DQ7 will be read on successive read attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 12.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop
toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If
all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into
read mode, having data kept remained.
Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause
DQ6 to toggle.
The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank
is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the
Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
34
MBM29DL640E80/90/12
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
these conditions DQ5 will produce “1”. This is a failure condition indicating that the program or erase cycle was
not successfully completed. Data Polling is only operating function of the device under this condition. The CE
circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins
will control the output disable functions as described in Tables 2 and 3.
The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In
this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset device with the command sequence.
DQ3
Sector Erase Timer
After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain
low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command
sequence.
If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to
determine whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase
cycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the
command has been accepted, the system software should check the status of DQ3 prior to and following each
subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have
been accepted.
See Table 12 : Hardware Sequence Flags.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase
suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows :
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 13 and Figure 12.
Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles
if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7 to DQ0 on the following read cycle.
35
MBM29DL640E80/90/12
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, the system may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine
the status of the operation. (Refer to Figure 25.)
Table 13
Toggle Bit Status
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle (Note) *1
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
DQ7
Toggle
1 (Note) *2
Mode
Program
Erase-Suspend Program
*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.
*2 : Reading from the non-erase suspend sector address indicates logic “1” at the DQ2 bit.
RY/BY
Ready/Busy
The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded
Algorithms are either in progress or have been completed. If output is low, the device is busy with either a program
or erase operation. If output is high, the device is ready to accept any read/write or erase operation. If the device
is placed in an Erase Suspend mode, RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY pin
is pulled high in standby mode.
Since this is an open-drain output, the Pull-up resistor needs to be connected to Vcc ; multiples of devices may
be connected to the host system via more than one RY/BY Pin in parallel.
Byte/Word Configuration
BYTE pin selects byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the device
operates in word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, the
device operates in byte (8-bit) mode. In this mode, the DQ15/A-1 pin becomes the lowest address bit, and DQ14
to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands
are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to Figures 15, 16 and 17 for the timing diagram.
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power-up, the device automatically resets the internal
state machine in Read mode. Also, with its control register architecture, alteration of memory contents only
occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
36
MBM29DL640E80/90/12
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above VLKO (Min) .
If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Group Protection
Device user is able to protect each Sector Group individually to store and protect data. Protection circuirvoids
both program and erase command that are address to protected sectors.
Any commands to Program or erase addressed to Protected sector are ignored (See FUNCTIONAL DESCRIPTION, Sector Group Protection)
37
MBM29DL640E80/90/12
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min
Max
Tstg
−55
+125
°C
TA
−40
+85
°C
VIN, VOUT
−0.5
VCC + 0.5
V
Power Supply Voltage *1
VCC
−0.5
+4.0
V
A9, OE, and RESET *1 *3
VIN
−0.5
+13.0
V
1 4
VACC
−0.5
+10.5
V
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins except A9,
OE, and RESET *1 *2
WP/ACC * *
*1 : Voltage is defined on the basis of VSS=GND=0V.
*2 : Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET
pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply
voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V
which may overshoot to +14.0 V for periods of up to 20 ns.
*4 : Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may undershoot
VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Ambient Temperature
Power Supply Voltage *
Symbol
TA
VCC
Part No.
Value
Unit
Min
Max
MBM29DL640E 80/90/12
−40
+85
°C
MBM29DL640E 80
+3.0
+3.6
V
MBM29DL640E 90/12
+2.7
+3.6
V
* : Voltage is defined on the basis of VSS=GND=0V.
Note : Operating ranges define those limits between which the proper device function is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
38
MBM29DL640E80/90/12
■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
20 ns
20 ns
+0.6 V
−0.5 V
−2.0 V
20 ns
Figure 1 Maximum Undershoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
+2.0 V
20 ns
Figure 2
20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC + 0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE and RESET.
Figure 3
Maximum Overshoot Waveform 2
39
MBM29DL640E80/90/12
■ DC CHARACTERISTICS
Parameter
Symbol
Value
Conditions
Min
Typ
Max
Input Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
−1.0

+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max
−1.0

+1.0
µA
A9, OE, RESET Inputs Leakage Current
ILIT
VCC = VCC Max,
A9, OE, RESET = 12.5 V


+35
µA
WP/ACC Accelerated Program Current
ILIA
VCC = VCC Max,
WP/ACC = VACC Max


20
mA
Byte


16
Word


18
Byte


7
Word


7
VCC Active Current *
1
ICC1
CE = VIL, OE = VIH,
f = 5 MHz
CE = VIL, OE = VIH,
f = 1 MHz
mA
mA
VCC Active Current *2
ICC2
CE = VIL, OE = VIH


40
mA
VCC Current (Standby)
ICC3
VCC = VCC Max, CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V,
WP/ACC = VCC ± 0.3 V

1
5
µA
VCC Current (Standby, Reset)
ICC4
VCC = VCC Max,
RESET = VSS ± 0.3 V

1
5
µA
VCC Current (Automatic Sleep Mode) *5
ICC5
VCC = VCC Max, CE = VSS ± 0.3 V,
RESET = VCC ± 0.3 V,
VIN = VCC ± 0.3 V or VSS ± 0.3 V

1
5
µA
VCC Active Current *6
(Read-While-Program)
ICC6
CE = VIL, OE = VIH
Byte


56
Word


58
VCC Active Current *6
(Read-While-Erase)
ICC7
CE = VIL, OE = VIH
Byte


56
Word


58
VCC Active Current
(Erase-Suspend-Program)
ICC8
CE = VIL, OE = VIH


40
mA
Input Low Voltage
VIL

−0.5

+ 0.6
V
Input High Voltage
VIH

2.0

VCC + 0.3
V
Voltage for Autoselect and Sector
Group Protection (A9, OE, RESET) *4
VID

11.5
12
12.5
V
Voltage for WP/ACC Sector Group
Protection/Unprotection and Program
Acceleration *3 *4
VACC

8.5
9.0
9.5
V
Output Low Voltage
VOL
IOL = 4 mA, VCC = VCC Min


0.45
V
VOH1
IOH = −2.0 mA, VCC = VCC Min
2.4


V
VOH2
IOH = −100 µA
Output High Voltage
Low VCC Lock-Out Voltage
VLKO

mA


V
2.3
2.4
2.5
V
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: This timing is only for Sector Protection Operation and Autoselect mode.
*4: Applicable for only VCC.
*5: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*6: Embedded Algorithm (program or erase) is in progress. (@5 MHz)
mA
VCC − 0.4
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
40
Unit
MBM29DL640E80/90/12
■ AC Characteristics
• Read Only Operations Characteristics
Value*
Symbol
Parameter
80
Condition
JEDEC Standard
90
12
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tAVAV
tRC

80

90

120

ns
Address to Output Delay
tAVQV
tACC
CE = VIL
OE = VIL

80

90

120
ns
Chip Enable to Output Delay
tELQV
tCE
OE = VIL

80

90

120
ns
Output Enable to Output Delay
tGLQV
tOE


30

35

50
ns
Chip Enable to Output High-Z
tEHQZ
tDF


25

30

30
ns
Output Enable to Output High-Z
tGHQZ
tDF


25

30

30
ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tAXQX
tOH

0

0
0

ns
RESET Pin Low to Read Mode

tREADY


20

20

20
µs
CE to BYTE Switching Low or High

tELFL
tELFH


5

5

5
ns
* : Test Conditions :
Output Load : 1 TTL gate and 30 pF (MBM29DL640E 80)
1 TTL gate and 100 pF (MBM29DL640E 90/120)
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or 3.0 V
Timing measurement reference level
Input : 1.5 V
Output : 1.5 V
3.3 V
Diode = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diode = 1N3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29DL640E80)
CL = 100 pF including jig capacitance (MBM29DL640E90/12)
Figure 4 Test Conditions
41
MBM29DL640E80/90/12
• Write/Erase/Program Operations
Value
Symbol
Parameter
JEDEC Standard
80
90
12
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Write Cycle Time
tAVAV
tWC
80


90


120


ns
Address Setup Time
tAVWL
tAS
0


0


0


ns

tASO
12


15


15


ns
tWLAX
tAH
45


45


50


ns

tAHT
0


0


0


ns
Data Setup Time
tDVWH
tDS
30


35


50


ns
Data Hold Time
tWHDX
tDH
0


0


0


ns
0


0


0


ns
10


10


10


ns
Address Setup Time to OE Low
During Toggle Bit Polling
Address Hold Time
Address Hold Time from CE or OE
High During Toggle Bit Polling
Read
Output
Enable
Toggle and Data
Hold Time Polling

tOEH
CE High During Toggle Bit Polling

tCEPH
20


20


20


ns
OE High During Toggle Bit Polling

tOEPH
20


20


20


ns
Read Recover Time Before Write
tGHWL
tGHWL
0


0


0


ns
Read Recover Time Before Write
tGHEL
tGHEL
0


0


0


ns
CE Setup Time
tELWL
tCS
0


0


0


ns
WE Setup Time
tWLEL
tWS
0


0


0


ns
CE Hold Time
tWHEH
tCH
0


0


0


ns
WE Hold Time
tEHWH
tWH
0


0


0


ns
Write Pulse Width
tWLWH
tWP
35


35


50


ns
CE Pulse Width
tELEH
tCP
35


35


50


ns
Write Pulse Width High
tWHWL
tWPH
25


30


30


ns
CE Pulse Width High
tEHEL
tCPH
25


30


30


ns
tWHWH1
tWHWH1

8


8


8

µs

16


16


16

µs
tWHWH2
tWHWH2

1


1


1

s

tVCS
50


50


50


µs

tVIDR
500


500


500


ns

tVACCR
500


500


500


ns

tVLHT
4


4


4


µs

tWPP
100


100


100


µs
Byte
Programming Operation
Sector Erase Operation *
Word
1
VCC Setup Time
Rise Time to VID *2
3
Rise Time to VACC *
Voltage Transition Time *
Write Pulse Width *2
2
(Continued)
42
MBM29DL640E80/90/12
(Continued)
Value
Symbol
Parameter
JEDEC Standard
80
90
12
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
OE Setup Time to WE Active *2

tOESP
4


4


4


µs
2
CE Setup Time to WE Active *

tCSP
4


4


4


µs
Recover Time from RY/BY

tRB
0


0


0


ns
RESET Pulse Width

tRP
500


500


500


ns
RESET High Level Period Before
Read

tRH
200


200


200


ns
BYTE Switching Low to Output
High-Z

tFLQZ


30


30


40
ns
BYTE Switching High to Output
Active

tFHQV


80


90


120
ns
Program/Erase Valid to RY/BY
Delay

tBUSY


90


90


90
ns
Delay Time from Embedded
Output Enable

tEOE


80


90


120
ns
Erase Time-out Time

tTOW
50


50

50


µs
Erase Suspend Transition Time

tSPD


20

20


20
µs

*1: This does not include preprogramming time.
*2: This timing is for Sector Group Protection operation.
*3: This timing is limited for Accelerated Program operation only.
43
MBM29DL640E80/90/12
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Min
Typ
Max
Sector Erase Time

1
10
s
Word Programming Time

16
360
µs
Byte Programming Time

8
300
µs
Chip Programming Time


200
s
100,000


cycle
Program/Erase Cycle
Comments
Excludes programming time
prior to erasure
Excludes system-level
overhead
Excludes system-level
overhead

■ TSOP (1) PIN CAPACITANCE
Parameter
Input Capacitance
Symbol
CIN
Condition
Value
Unit
Typ
Max
VIN = 0
6.0
7.5
pF
Output Capacitance
COUT
VOUT = 0
8.5
12.0
pF
Control Pin Capacitance
CIN2
VIN = 0
8.0
11.0
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0
9.0
11.0
pF
Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz
• DQ15/A-1 Pin capacitance is stipulated by output capacitance.
■ FBGA PIN CAPACITANCE
Parameter
Input Capacitance
Symbol
CIN
Condition
Unit
Typ
Max
VIN = 0
6.0
7.5
pF
Output Capacitance
COUT
VOUT = 0
8.5
12.0
pF
Control Pin Capacitance
CIN2
VIN = 0
8.0
11.0
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0
6.0
7.5
pF
Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz
• DQ15/A-1 Pin capacitance is stipulated by output capacitance.
44
Value
MBM29DL640E80/90/12
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will
Change
from H to L
May
Change
from L to H
Will
Change
from L to H
"H" or "L":
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
"Off" State
tRC
Address
Address Stable
tACC
CE
tOE
tDF
OE
tOEH
WE
tOH
tCE
High-Z
Outputs
Figure 5.1
Outputs Valid
High-Z
Read Operation Timing Diagram
45
MBM29DL640E80/90/12
tRC
Address
Address Stable
tACC
CE
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Outputs Valid
Figure 5.2 Hardware Reset/Read Operation Timing Diagram
46
MBM29DL640E80/90/12
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tRC
tAH
CE
tCS
tCH
tCE
OE
tGHWL
tWP
tOE
tWPH
tWHWH1
WE
Data
A0h
tOH
tDF
tDS tDH
PD
DQ7
DOUT
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)
Figure 6 Alternate WE Controlled Program Operation Timing Diagram
47
MBM29DL640E80/90/12
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
Data
A0h
tDH
PD
DQ7
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)
Figure 7 Alternate CE Controlled Program Operation Timing Diagram
48
MBM29DL640E80/90/12
555h
Address
tWC
2AAh
tAS
555h
555h
2AAh
SA*
tAH
CE
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAh
10h for Chip Erase
55h
80h
AAh
55h
10h/30h
Data
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
Note : These waveforms are for the × 16 mode. The addresses differ from × 8 mode.
Figure 8 Chip/Sector Erase Operation Timing Diagram
49
MBM29DL640E80/90/12
CE
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7
Data
DQ7
DQ7 =
Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
DQ6 to DQ0 =
Output Flag
Data
tBUSY
DQ6 to DQ0
Valid Data
High-Z
tEOE
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation) .
Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram
50
MBM29DL640E80/90/12
Address
tAHT tASO
tAHT tAS
CE
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tDH
DQ 6/DQ2
tOE
Toggle
Data
Data
tCE
Toggle
Data
Toggle
Data
*
Stop
Toggling
Output
Valid
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
51
MBM29DL640E80/90/12
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
Address
tAS
tACC
tAH
tAS
tAHT
tCE
CE
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
Valid
Output
DQ
tDH
Valid
Intput
(A0H)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1
BA2 : Address corresponding to Bank 2
Figure 11
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Bank-to-Bank Read/Write Timing Diagram
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
DQ6
DQ2*
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
Figure 12 DQ2 vs. DQ6
52
Erase
Erase
Complete
MBM29DL640E80/90/12
CE
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
Figure 13
RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
WE
RESET
tRP
tRB
RY/BY
tREADY
Figure 14 RESET, RY/BY Timing Diagram
53
MBM29DL640E80/90/12
CE
tCE
BYTE
Data Output
(DQ7 to DQ0)
DQ14 to DQ0
tELFH
Data Output
(DQ14 to DQ0)
tFHQV
A-1
DQ15/A-1
DQ15
Figure 15 Timing Diagram for Word Mode Configuration
CE
BYTE
DQ14 to DQ0
tELFL
Data Output
(DQ7 to DQ0)
Data Output
(DQ14 to DQ0)
tACC
DQ15/A-1
A-1
DQ15
tFLQZ
Figure 16 Timing Diagram for Byte Mode Configuration
Falling edge of the last write signal
CE or WE
Input
Valid
BYTE
tAS
tAH
Figure 17 BYTE Timing Diagram for Write Operations
54
MBM29DL640E80/90/12
A21, A20, A19
A18, A17, A16
A15, A14, A13
A12
SPAX
SPAY
A6, A3, A2, A0
A1
VID
VIH
A9
VID
VIH
OE
tVLHT
tVLHT
tVLHT
tVLHT
tWPP
WE
tOESP
tCSP
CE
01h
Data
tVCS
tOE
VCC
SPAX : Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
Note : A-1 is VIL on byte mode.
Figure 18 Sector Group Protection Timing Diagram
55
MBM29DL640E80/90/12
VCC
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CE
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Unprotection period
Figure 19 Temporary Sector Group Unprotection Timing Diagram
56
MBM29DL640E80/90/12
VCC
tVCS
VID
RESET
tVLHT
tVIDR
tWC
Address
tWC
SPAX
SPAX
SPAY
A6, A3,
A2, A0
A1
CE
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX : Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
Note : A-1 is VIL on byte mode.
Figure 20 Extended Sector Group Protection Timing Diagram
57
MBM29DL640E80/90/12
VCC
tVACCR
tVCS
tVLHT
VACC
VIH
WP/ACC
CE
WE
tVLHT
Program Command Sequence
RY/BY
Acceleration period
Figure 21 Accelerated Program Timing Diagram
58
tVLHT
MBM29DL640E80/90/12
■ FLOW CHART
EMBEDDED ALGORITHM
Start
Write Program
Command Sequence
(See Below)
Data Polling
No
No
Increment Address
Verify Data
?
Yes
Embedded
Program
Algorithm
in program
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Note : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 22
Embedded ProgramTM Algorithm
59
MBM29DL640E80/90/12
EMBEDDED ALGORITHM
Start
Write Erase
Command Sequence
(See Below)
Data Polling
No
Data = FFh
?
Yes
Embedded
Erase
Algorithm
in progress
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address
/30h
Sector Address
/30h
Sector Address
/30h
Additional sector
erase commands
are optional.
Note : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 23 Embedded EraseTM Algorithm
60
MBM29DL640E80/90/12
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
= Any of the sector addresses
within the sector not being
protected during sector erase or
multiple sector erases
operation.
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
*
No
Fail
Yes
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 24 Data Polling Algorithm
61
MBM29DL640E80/90/12
Start
VA = Bank address being executed
Embedded Algorithm.
Read DQ7 to DQ0
Addr. = VA
*1
Read DQ7 to DQ0
Addr. = VA
DQ6 =
Toggle?
No
Yes
No
DQ5 = 1?
Yes
*1, 2
Read DQ7 to DQ0
Addr. = VA
Read DQ7 to DQ0
Addr. = VA
DQ6 =
Toggle?
*1, 2
No
Yes
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation
Complete
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
Figure 25 Toggle Bit Algorithm
62
MBM29DL640E80/90/12
Start
Setup Sector Group Addr.
A21, A20, A19, A18, A17,
A16, A15, A14, A13, A12
(
)
PLSCNT = 1
OE = VID, A9 = VID
CE = VIL, RESET = VIH
A6 = A3 = A2 = A0 = VIL, A1 = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector Group
= SPA, A1 = VIH *
( AAddr.
6 = A3 = A2 = A0 = VIL )
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
No
Data = 01h?
Yes
Protect Another Sector
Group?
Yes
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Group Protection
Completed
* : A-1 is VIL in byte mode.
Figure 26
Sector Group Protection Algorithm
63
MBM29DL640E80/90/12
Start
RESET = VID
*1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector Group
Unprotection Completed
*2
*1 : All protected Sector Groups are unprotected.
*2 : All previously protected Sector Groups are reprotected.
Figure 27 Temporary Sector Group Unprotection Algorithm
64
MBM29DL640E80/90/12
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector Group
Unprotection Mode
No
Extended Sector Group
Protection Entry?
Yes
To Setup Sector Group Protection
Write XXXh/60h
PLSCNT = 1
To Protect Sector Group
Write 60h to Sector Address
(A6 = A3 = A2 = A0 = VIL, A1 = VIH)
Time out 250 µs
To Verify Sector Group Protection
Write 40h to Sector Address
(A6 = A3 = A2 = A0 = VIL, A1 = VIH)
Increment PLSCNT
Read from Sector Group Address
(Addr. = SPA, A0 = VIL,
A1 = VIH, A6 = VIL)
No
Setup Next Sector Group Address
PLSCNT = 25?
Yes
Remove VID from RESET
Write Reset Command
No
Data = 01h?
Yes
Yes
Protect Other Sector
Group?
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Group Protection
Completed
Figure 28 Extended Sector Group Protection Algorithm
65
MBM29DL640E80/90/12
FAST MODE ALGORITHM
Start
555h/AAh
Set Fast Mode
2AAh/55h
555h/20h
XXXh/A0h
Program Address/Program Data
In Fast Program
Data Polling
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming Completed
(BA) XXXh/90h
Reset Fast Mode
XXXh/F0h
Notes: • The sequence is applied for × 16 mode.
• The addresses differ from × 8 mode.
Figure 29
66
Embedded Programming Algorithm for Fast Mode
MBM29DL640E80/90/12
■ ORDERING INFORMATION
Part No.
Package
Access Time(ns)
MBM29DL640E80TN
MBM29DL640E90TN
MBM29DL640E12TN
48-Pin plastic TSOP(1)
(FPT-48-M19)
Normal Bend
80
90
120
MBM29DL640E80TR
MBM29DL640E90TR
MBM29DL640E12TR
48-Pin plastic TSOP(1)
(FPT-48-M20)
Reverse Bend
80
90
120
MBM29DL640E80PBT
MBM29DL640E90PBT
MBM29DL640E12PBT
63-Pin plastic FBGA
(BGA-63P-M02)
80
90
120
MBM29DL640
E
80
Remarks
TN
PACKAGE TYPE
TN = 48-Pin Thin Small Outline Package
(TSOP) Normal Bend
TR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
PBT = 63-Ball Fine pitch Ball Grid Array
Package (FBGA)
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
DEVICE NUMBER/DESCRIPTION
MBM29DL640
64 Mega-bit (8 M × 8-Bit or 4 M × 16-Bit) Flash Memory
3.0 V-only Read, Program, and Erase
67
MBM29DL640E80/90/12
■ PACKAGE DIMENSIONS
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15 (.006) MAX (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP (1)
(FPT-48P-M19)
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
* 12.00±0.20
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
"A"
0.10(.004)
(.472±.008)
+0.10
1.10 –0.05
+.004
.043 –.002
(Mounting
height)
+0.03
0.17 –0.08
+.001
.007 –.003
C
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
0.22±0.05
(.009±.002)
0.10(.004)
M
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
68
MBM29DL640E80/90/12
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15 (.006) MAX (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP (1)
(FPT-48P-M20)
LEAD No.
1
48
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
24
25
+0.03
0.17 –0.08
+.001
0.10(.004)
.007 –.003
0.50(.020)
0.22±0.05
(.009±.002)
M
0.10±0.05
(.004±.002)
(Stand off height)
+0.10
"A"
1.10 –0.05
* 18.40±0.20
(.724±.008)
20.00±0.20
(.787±.008)
C
0.10(.004)
+.004
.043 –.002
(Mounting height)
* 12.00±0.20(.472±.008)
2003 FUJITSU LIMITED F48030S-c-6-7
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
69
MBM29DL640E80/90/12
(Continued)
63-pin plastic FBGA
(BGA-63P-M02)
+0.15
11.00±0.10(.433±.004)
1.05 –0.10
(8.80(.346))
+.006
.041 –.004
(Mounting height)
(7.20(.283))
0.38±0.10
(.015±.004)
(Stand off)
(5.60(.220))
0.80(.031)TYP
8
7
6
10.00±0.10
(.394±.004)
5
(4.00(.157))
(5.60(.220))
4
3
2
1
M
L
K
J
H
G
F
E
INDEX AREA
D
C
B
A
INDEX BALL
63-ø0.45±0.05
(63-ø0.18±.002)
0.08(.003)
M
0.10(.004)
C
2001 FUJITSU LIMITED B63002S-c-3-2
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
70
MBM29DL640E80/90/12
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
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must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0305
 FUJITSU LIMITED Printed in Japan
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