datasheet for S29XS256R by Spansion

datasheet for S29XS256R by Spansion

S29VS/XS-R MirrorBit

®

Flash Family

S29VS256R, S29VS128R, S29XS256R, S29XS128R

256/128 Megabit (32/16 Megabyte)

1.8 V Burst 16-bit Data Bus, Simultaneous Read/Write,

Multiplexed MirrorBit Flash Memory

Data Sheet (Advance Information)

S29VS/XS-R MirrorBit ® Flash Family Cover Sheet

Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information,

Preliminary, or Full Production. See

Notice On Data Sheet Designations

for definitions.

Publication Number S29VS_XS-R_00 Revision 08 Issue Date July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion

Inc. therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion Inc.

The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”

Combination

Some data sheets contain a combination of products with different designations (Advance Information,

Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC

Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or V

IO

range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local sales office.

2 S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

S29VS/XS-R MirrorBit

®

Flash Family

S29VS256R, S29VS128R, S29XS256R, S29XS128R

256/128 Megabit (32/16 Megabyte)

1.8 V Burst 16-bit Data Bus, Simultaneous Read/Write,

Multiplexed MirrorBit Flash Memory

Data Sheet (Advance Information)

Features

Single 1.8 V supply for read/program/erase (1.70–1.95 V)

65 nm MirrorBit Technology

Address and Data Interface Options

– Address and Data Multiplexed for reduced I/O count

(ADM) S29VS-R

– Address-High, Address-Low, Data Multiplexed for minimum I/O count (AADM) S29XS-R

Simultaneous Read/Write operation

32-word Write Buffer

Bank architecture

– Eight-bank

Four 32-KB sectors at the top or bottom of memory array

255/127 of 128-KB sectors

Programmable linear (8/16-word) with wrap around and

continuous burst read modes

Secured Silicon Sector region consisting of 128 words each

for factory and customer

10-year data retention (typical)

Cycling Endurance: 100,000 cycles per sector (typical)

RDY output indicates data available to system

Command set compatible with JEDEC (42.4) standard

Hardware sector protection via V

PP

pin

Handshaking by monitoring RDY

Offered Packages

– 44-ball FBGA (6.2 mm x 7.7 mm x 1.0 mm)

Low V

CC

write inhibit

Write operation status bits indicate program and erase

operation completion

Suspend and Resume commands for Program and Erase

operations

Asynchronous program operation, independent of burst

control register settings

V

PP

input pin to reduce factory programming time

Support for Common Flash Interface (CFI)

General Description

The Spansion S29VS256/128R and S29XS256/128R are MirrorBit

®

Flash products fabricated on 65 nm process technology.

These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using multiplexed data and address pins. These products can operate up to 108 MHz and use a single V

CC of

1.7 V to 1.95 V that makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered power consumption. The S29VS256/128R operates in ADM mode, while the S29XS256/128R can operate in the AADM mode.

Performance Characteristics

Read Access Times

Speed Option (MHz)

Max. Synch. Latency, ns (t

IA)

Max. Synch. Burst Access, ns (t

BACC)

Max. Asynch. Access Time, ns (t

ACC

)

Max OE# Access Time, ns (t

OE

)

108

72.34

6.75

80

15

Current Consumption (typical values)

Continuous Burst Read @ 108 MHz

Simultaneous Operation @ 108 MHz

Program/Erase

Standby Mode

Typical Program & Erase Times

Single Word Programming

Effective Write Buffer Programming (V

CC

) Per Word

Effective Write Buffer Programming (V

PP

) Per Word

Sector Erase (16 Kword Sector)

Sector Erase (64 Kword Sector)

32 mA

71 mA

30 mA

30 µA

170 µs

14.1 µs

9 µs

350 ms

800 ms

Publication Number S29VS_XS-R_00 Revision 08 Issue Date July 30, 2012

This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.

4

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.

Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.

Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2

Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.

Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.

Address Space Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.1

Data Address & Quantity Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2

Flash Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.3

Address/Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5

Device ID and CFI (ID-CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.

Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.1

Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.2

Synchronous (Burst) Read Mode and Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.4

Blank Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.5

Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.6

Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.7

Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.8

Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9

Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.10

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.

Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1

Sector Lock/Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.2

Sector Lock Range Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.3

Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.4

SSR Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.5

Secure Silicon Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.

Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.2

Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.3

Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10.

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.2

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.3

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.4

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.5

AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.6

Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.7

V

CC

Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.8

CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.9

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.1

Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.2

Device ID and Common Flash Memory Interface Address Map . . . . . . . . . . . . . . . . . . . . . . 58

12.

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figures

Figure 3.1

Figure 4.1

Figure 4.2

Figure 7.1

Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

44-Ball Very Thin Fine-Pitch Ball Grid Array, Top View, Balls Facing Down . . . . . . . . . . . . . 10

VDJ044—44-Ball Very Thin Fine-Pitch Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Synchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10.1

Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 10.2

Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 10.3

Input Pulse and Test Point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 10.4

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 10.5

V

CC

Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 10.6

CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 10.7

Synchronous Read Mode - ADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 10.8

Asynchronous Mode Read - ADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 10.9

Asynchronous Program Operation Timings - ADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 10.10 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 10.11 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 10.12 Latency with Boundary Crossing into Bank Performing Embedded Operation . . . . . . . . . . . 52

Figure 10.13 Example of Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 10.14 Back-to-Back Read/Write Cycle Timings - ADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 11.1

Asynchronous Read - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 11.2

Asynchronous Read Followed By Read - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 11.3

Asynchronous Read Followed By Write - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 11.4

Asynchronous Write - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 11.5

Asynchronous Write Followed By Read - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 11.6

Asynchronous Write Followed By Write - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 11.7

Synchronous Read Wrapped Burst Address Low Only - AADM Interface . . . . . . . . . . . . . . .66

Figure 11.8

Synchronous Read Continuous Burst - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 11.9

Synchronous Read Wrapped Burst - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 11.10 Synchronous Read Followed By Read Burst - AADM Interface . . . . . . . . . . . . . . . . . . . . . . .67

Figure 11.11 Synchronous Read Followed By Write - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 11.12 Synchronous Write Followed By Read Burst - AADM Interface . . . . . . . . . . . . . . . . . . . . . . .68

Figure 11.13 Synchronous Write Followed By Write - AADM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 5

6

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Tables

Table 2.1

Table 6.1

Table 6.2

Table 6.3

Table 6.4

Table 6.5

Table 6.6

Table 6.7

Table 6.8

Table 7.1

Table 7.2

Table 7.3

Table 7.4

Table 7.5

Table 7.6

Table 7.7

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

System Versus Flash View of Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

S29VS/XS256R Sector and Memory Address Map (Top Boot) . . . . . . . . . . . . . . . . . . . . . . .15

S29VS/XS256R Sector and Memory Address Map (Bottom Boot) . . . . . . . . . . . . . . . . . . . . .15

S29VS/XS128R Sector and Memory Address Map (Top Boot) . . . . . . . . . . . . . . . . . . . . . . .16

S29VS/XS128R Sector and Memory Address Map (Bottom Boot) . . . . . . . . . . . . . . . . . . . . .16

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

ID-CFI Address Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Secured Silicon Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Initial Wait State vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Address Latency for 10 -13 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 7.8

Table 7.9

Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 7.10

Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 7.11

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 7.12

Status Register Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 7.13

Status Register - Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 7.14

Status Register - Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 7.15

Status Register - Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 7.16

Status Register - Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 7.17

Status Register - Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 7.18

Status Register - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 7.19

Status Register - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 7.20

Status Register - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 7.21

Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 7.22

Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 7.23

Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 7.24

Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 7.25

Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 7.26

Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 7.27

Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 7.28

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 8.1

Secured Silicon Region Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 8.2

Table 8.3

Secured Silicon Region Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Secured Silicon Region Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 10.1

V

CC

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 10.2

Warm-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 11.1

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 11.2

ID/CFI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

1.

Ordering Information

The ordering part number is formed by a valid combination of the following:

S29VS 256 R xx BH W 00 0

Packing Type

0

= Tray (standard; see note ( Note 1 ))

3 = 13-inch Tape and Reel

Model Number

00 = Top

01 = Bottom

Temperature Range

W = Wireless (–25°C to +85°C)

Package Type and Material

BH = Very Thin Fine-Pitch BGA, Low Halogen Lead (Pb)-Free Package

Speed Option (Burst Frequency)

0S = 83 MHz

AA = 104 MHz

AB = 108 MHz

Process Technology

R = 65 nm MirrorBit

®

Technology

Flash Density

256 = 256 Mb

128 = 128 Mb

Device Family

S29VS256R =1.8 Volt-only Simultaneous Read/Write, Burst-Mode Address and Data

Multiplexed Flash Memory

S29XS256R =1.8 Volt-only Simultaneous Read/Write, Burst-Mode Address Low,

Address High and Data Multiplexed Flash Memory

1.1

Valid Combinations

Valid Combination list configurations are planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Base Ordering

Part Number

S29VS256R

S29VS128R

S29XS256R

S29XS128R

S29VS-R Valid Combinations (1) (2)

Speed Option

0S, AA, AB

Package Type, Material, and Temperature Range

BHW (3)

Packing

Type

0, 3

(1)

Model

Numbers

00, 01

Package Type

(2)

6.2 mm x 7.7 mm, 44-ball

Notes:

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading S29 and packing type designator from ordering part number.

3. Industrial Temperature Range is also available. For device specification differences, please refer to the Specification Supplement with

Publication Number S29VS_XS-R_SP.

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 7

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

2.

Input/Output Descriptions & Logic Symbol

Table 2.1

identifies the input and output package connections provided on the device.

Symbol

Amax – A16

A/DQ15 – A/DQ0

CE#

OE#

WE#

V

CC

V

CCQ

V

SS

V

SSQ

NC

RDY

CLK

AVD#

RESET#

V

PP

RFU

Table 2.1 Input/Output Descriptions

I/O

Input

Input

Input

Supply

Supply

I/O

Type Description

Higher order address lines. Amax = A23 for VS256R, A22 for VS128R.

On the XS256R and XS128R, these inputs can be left unconnected in AADM mode.

Multiplexed Address/Data input/output

Flash Chip Enable. Asynchronous relative to CLK.

Output Enable. Asynchronous relative to CLK for the Burst mode.

Write Enable

Device Power Supply

Input/Output Power Supply (must be ramped simultaneously with V

CC

)

Ground

I/O Input/Output Ground

No Connect No Connected internally

Output Ready. Indicates when valid burst data is ready to be read

Input

Input

Input

Input

Reserved

The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access

Address Valid input. Indicates to device that the valid address is present on the address inputs

(address bits A15 – A0 are multiplexed, address bits Amax – A16 are address only).

V

IL

= for asynchronous mode, indicates valid address; for burst mode, cause staring address to be latched on rising edge of CLK.

V

IH

= device ignores address inputs

Hardware Reset. Low = device resets and returns to reading array data.

Accelerated input.

At V

HH

, accelerates programming; automatically places device in unlock bypass mode.

At V

IL

, disables all program and erase functions.

Should be at V

IH

for all other conditions.

Reserved for future use

8 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

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3.

Block Diagrams

Figure 3.1 Simultaneous Operation Circuit

V

CC

V

SS

V

SSQ

Bank Address

Bank 0

Amax–A0

X-Decoder

DQ15–DQ0

OE#

VPP

RESET#

WE#

CE#

AVD#

RDY

DQ15–DQ0

Amax–A0

STATE

CONTROL

&

COMMAND

REGISTER

Amax–A0

Bank Address

Bank Address

Bank 1

X-Decoder

Status

Control

X-Decoder

Bank (n-1)

DQ15–DQ0

DQ15–DQ0

DQ15–DQ0

Amax–A0

X-Decoder

Bank (n)

DQ15–DQ0

Bank Address

Notes:

1. Amax = A23 for S29VS/XS256R, A22 for S29VS/XS128R.

2. Bank(n) = 8 (S29VS/XS256/128R).

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 9

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

4.

Physical Dimensions/Connection Diagrams

This section shows the I/O designations and package specifications for the S29VS-R.

4.1

Related Documents

The following documents contain information relating to the S29VS-R devices. Click on the title or go to www.spansion.com

, or request a copy from your sales office.

 Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits

4.2

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above

150°C for prolonged periods of time.

4.2.1

44-Ball Very Thin Fine-Pitch Ball Grid Array, S29VS256R/S29XS256R/

S29VS128R/S29XS128R

A

Figure 4.1 44-Ball Very Thin Fine-Pitch Ball Grid Array, Top View, Balls Facing Down

1 2 3 4 5 6 7 8 9 10 11 12 13 14

NC NC

B

E

F

G

C

D

RDY A21 VSS CLK VCC WE# VPP A19 A17 A22

VCCQ A16 A20 AVD# A23 RESET# NC A18 CE# VSSQ

VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#

A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0

H

NC

Notes:

1. Ball D7 is NC for S29VS128R.

2. Balls D7, C12, C4, D5, C10, D10, C11, D4 are NC for S29XS256R and S29XS128R

NC

10 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

4.2.2

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

VDJ044-44-Ball Very Thin Fine-Pitch Ball Grid Array, 6.2mm x 7.7 mm

Figure 4.2 VDJ044—44-Ball Very Thin Fine-Pitch Ball Grid Array

SYMBOL

A

A1

A2

D

E

D1

E1

MD

ME

N

Ø b e

SD / SE

PACKAGE

JEDEC

VDJ 044

N/A

7.70 mm x 6.20 mm NOM

PACKAGE

MIN

0.86

NOM

0.93

MAX

1.00

0.18

0.64

7.60

6.10

0.23

0.71

7.70

6.20

4.50 BSC.

0.28

0.78

7.80

6.30

0.25

1.50 BSC.

10

4

44

0.30

0.50 BSC.

0.25 BSC.

0.35

NOTE

OVERALL THICKNESS

BALL HEIGHT

BODY THICKNESS

BODY SIZE

BODY SIZE

BALL FOOTPRINT

BALL FOOTPRINT

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

BALL DIAMETER

BALL PITCH

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010

EXCEPT AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3616 \ 16-039.27 \ 12.5.6

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 11

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

5.

Product Overview

The S29VS/XS-R family is 1.8-V only, simultaneous read/write, burst-mode, Flash devices. These devices have a 16 bit (word) wide data bus. All read accesses provide 16 bits of data on each bus transfer cycle. All writes take 16 bits of data from each bus transfer cycle.

Device

S29VS128R/S29XS128R

S29VS256R/S29XS256R

Mbits

128

256

Mbytes

16

32

Mwords

8

16

Banks

8

8

Mbytes / Bank

2

4

The Flash memory array is divided into banks. A bank is the address range within which one program, or erase operation may be in progress at the same time as one read operation is in progress in any other bank of the memory. This multiple bank structure enables Simultaneous Read and Write (SRW) so that code may be executed or data read from one bank while a group of data is programmed, or erased as a background task in one other bank.

Each bank is divided into sectors. A sector is the minimum address range of data which can be erased to an all Ones state. Most of the sectors are 128 KBytes each. Depending on the option ordered, either the top-4 sectors or the bottom-4 sectors are 32 KBytes each. These are called boot sectors because they are often used for holding boot code or parameters that need to be protected or erased separately from other data in the Flash array.

Programming is done via a 64 Byte write buffer. It is possible to program from one to 32 words (64 bytes) in each programming operation.

The S29VS/XS family is capable of continuous, synchronous (burst) read or linear read (8- or 16-word aligned group) with wrap around. A wrapped burst begins at the initial location and continues to the end of an

8, or 16-word aligned group then “wraps-around” to continue at the beginning of the 8, or 16-word aligned group. The burst completes with the last word before the initial location. Word wrap around burst is generally used for processor cache line fill.

12 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

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6.

Address Space Maps

There are five address spaces within each device:

 A Non-Volatile Flash Memory Array used for storage of data that may be randomly accessed by asynchronous or burst read operations.

 A Read Only Memory Array used for factory programmed permanent device characteristics information.

This area contains the Device Identification (ID) and Common Flash Interface (CFI) information.

 A One Time Programmable (OTP) Non-volatile Flash array used for factory programmed permanent data, and customer programmable permanent data. This is called the Secure Silicon Region (SSR).

 An OTP location used to permanently protect the SSR. This is call the SSR Lock.

 A volatile register used to configure device behavior options. This is called the Configuration Register.

The main Flash Memory Array is the primary and default address space but, it may be partially overlaid by the other four address spaces with one alternate address space available at any one time. The location where the alternate address space is overlaid is defined by the address provided in the command that enables each overlay. The portion of the command address that is sufficient to select a sector is used to select the sector that is overlaid by an alternate Address Space Overlay (ASO).

Any address range, within the overlaid sector, not defined by an overlay address map, is reserved for future use. All read accesses outside of an address map within the selected sector, return non-valid data. The locations will display actively driven data but the meaning of whatever ones or zeros appear are not defined.

There are three operation modes for each bank that determine what portions of the address space are readable at any given time:

 Read Mode

 Embedded Algorithm (EA) Mode

 Address Space Overlay (ASO) Mode

Each bank of the device can be in any operation mode but, only one bank can be in EA or ASO mode at any one time.

In Read Mode, a Flash Memory Array bank may be directly read by asynchronous or burst accesses from the host system bus. The Control Unit (CU) puts all banks in Read mode during Power-on, a Hardware Reset, after a Command Reset, or after a bank is returned to Read mode from EA mode.

In EA mode the Flash memory array data in a bank is stable but undefined, and effectively unavailable for read access from the host system. While in EA mode the bank is used by the CU in the execution of commands. Typical EA mode operations are programming or erasing of data in the Flash array. All other banks are available for read access while the one bank is in EA mode. This ability to read from one bank while another bank is used in the execution of a command is called Simultaneous Read and Write (SRW) and allows for continued operation of the system via the reading of data or execution of code from other banks while one bank is programming or erasing data as a relatively long time frame background task.

In ASO mode, one of the overlay address spaces are overlaid in a bank (entered). That bank is in ASO mode and no other bank may be in EA or ASO mode. All EA activity must be completed before entering any ASO mode. A command for entering an EA or ASO mode while another bank is in EA or ASO mode will be ignored.

While an ASO mode is active (entered) in a bank, a read for Flash array data to any other bank is allowed.

ASO mode selects a specific sector for the overlaid address space. Other sectors in the ASO bank still provide Flash array data and may be read during ASO mode.

The ASOs are functionally tied to the lowest address bank. The commands used to overlay (enter) these areas must select a sector address within the lowest address bank.

While SSR Lock, SSR, or Configuration Register is overlaid only the SSR Lock, SSR, or Configuration

Register respectively may be programmed in the overlaid sector. While any of these ASO areas are being programmed the ASO bank switches to EA mode. The ID/CFI and factory portion of the SSR ASO is not customer programmable.

The address nomenclature used in this document is a shorthand form that shows addresses are formed from a concatenation of high order bits, sufficient to select a Sector Address (SA), with low order bits to select a location within the sector. When in Read mode and reading from the Flash Array the entire address is used to

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 13

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n ) select a specific word for asynchronous read or the starting word address of a burst read. When writing a command, the address bits between SA and the command specified least significant bits must be Zero to allow for future extension of an overlay address map.

6.1

Data Address & Quantity Nomenclature

A Bit is a single One or Zero data value. A Byte is a group of 8 bits aligned on an 8 bit boundary. A Word is a group of 16 bits aligned on a 16 bit boundary.

Throughout this document quantities of data are generally expressed in terms of byte units. Example: most sectors have 128 Kilo Bytes of data and is written as 128 KBytes or 128 KB. Addresses are also

expressed in byte units. A 128 KByte sector has an address range from 00000h to 1FFFFh Byte locations.

Byte units are used because most host systems and software for these systems use byte resolution addresses. Software & hardware developers most often calculate code and data sizes in terms of bytes, so this is more familiar terminology than describing data sizes in bits or words. In general, data units will not be abbreviated if possible so that full unit names of Byte, Word, or bit are used. However, there may be cases where capital B is used for byte units and lower case b is used for bit units, in situations where space is limited such as in table column headers.

In some cases data quantities will also be expressed in word or bit units in addition to the quantity shown in bytes. This may be done as an aid to readers familiar with prior device generation documentation which often provided only word or bit unit values. Word units may also be used to emphasize that, in the memory devices described in this documentation, data is always exchanged with the host system in word units. Each bus cycle transfer of read or write data on the host system bus is a transfer 16 bits of data. A read bus cycle is always a16 bit wide transfer of data to the host system whether the host system chooses to look at all the bits or not. A write bus cycle is always a transfer of 16 bits to the memory device and the device will store all 16 bits to a register. In the case of a program operation all 16 bits of each word to be programmed will be stored in the Flash array.

Because data is always transferred in word units, the memory devices being discussed use only the address signals from the system necessary to select words. The host system byte address uses system address a0 to select bytes and a1 to select words. Flash memories with word wide data paths have traditionally started their address signal numbering with A0 being the selector for words because a byte select input is not needed. So, system address a-maximum to a1 are connected to Flash A-maximum to A0 (the documentation convention here is to use lower case for system address signal numbering and upper case for Flash address signals). In prior generation Flash documentation, address values used in commands to the flash were documented from the viewpoint of the Flash device - the bit pattern appearing on Flash address inputs A10 to A0. However, most software is written with addresses expressed in bytes. This means the address patterns shown in Flash command tables have traditionally been shifted by one bit to express them as byte address values in Flash control programs. Example: a prior generation Flash data sheet would show a command write of data value xxA0h to address 555h; this is an address pattern of 10101010101b on Flash address inputs A10 to A0; but software would define this as a byte address value of AAAh since the least significant address bit is not used by the Flash); which is 101010101010b on system address bus a11 to a0. Because system a11 to a1 is connected to Flash A10 to A0 the Flash word address of 555h and the system byte address of AAAh provides the same bit pattern on the same address inputs. Because all address values are being documented as system byte addresses, that are more familiar to software writers, the command tables have addresses that are shifted from those shown in prior generation devices.

14 S29VS/XS-R MirrorBit

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D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

6.2

Flash Memory Array

The Non-Volatile Flash Memory Array is organized as shown in the following tables. Devices are factory configured to have either all uniform size sectors or four smaller sectors at either the top of the device.

System Address Signals

System Byte Address Hex

Binary Pattern

Flash Word Address Hex

Flash Address Signals

Table 6.1 System Versus Flash View of Address a11 a10 a9 a8 a7 a6 a5 a4

A A

1

A10

0

5

A9

1

A8

0

A7

1

A6

5

0

A5

1

A4

0

A3 a3

1

A2

5 a2

0

A1

A a1

1

A0 a0

0

Table 6.2 S29VS/XS256R Sector and Memory Address Map (Top Boot)

Bank

Size

(Mbit)

32

Sector

Count

224

Sector Size

(KByte)

128

Bank

0

1

2

3

4

5

6

Sector

Range

SA000-SA031

SA032–SA063

SA064–SA095

SA096–SA127

SA128–SA159

SA160–SA191

SA192–SA223

SA224–SA254

SA255

SA256

SA257

SA258

Address

Range (word)

000000h–1FFFFFh

Address

Range (byte)

000000h–3FFFFFh

1C00000h–1FDFFFFh

1FE0000h–1FE7FFFh

1FE8000h-1FEFFFFh

1FF0000h–1FF7FFFh

1FF8000h–1FFFFFFh

Notes

Sector Starting

Address –

Sector Ending

Address

31

4

128

32

7

E00000h–FEFFFFh

FF0000h–FF3FFFh

FF4000h-FF7FFFh

FF8000h–FFBFFFh

FFC000h–FFFFFFh

Note:

All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the byte address pattern x000000h–x1FFFFh.

Table 6.3 S29VS/XS256R Sector and Memory Address Map (Bottom Boot)

Bank

Size

(Mbit)

32

Sector

Count

4

31

224

Sector Size

(Kbyte)

32

128

128

Bank

0

5

6

7

3

4

1

2

Sector

Range

SA000

SA001

SA002

SA003

SA004–SA034

SA035–SA066

SA067–SA098

SA099–SA130

SA131–SA162

SA163–SA194

SA195–SA226

SA227–SA258

Address

Range (word)

000000h–003FFFh

004000h–007FFFh

008000h–00BFFFh

00C000h–00FFFFh

010000h–1FFFFFh

Address

Range (byte)

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–3FFFFFh

Notes

Sector Starting

Address –

Sector Ending Address

E00000h–FFFFFFh 1C00000h–1FFFFFFh

Note:

All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the byte address pattern x000000h–x1FFFFh.

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Table 6.4 S29VS/XS128R Sector and Memory Address Map (Top Boot)

Bank

Size

(Mbit)

16

Sector

Count

112

Sector Size

(KByte)

128

Bank

0

1

2

3

4

5

6

Sector

Range

SA000-SA015

SA016–SA031

SA032–SA047

SA048–SA063

SA064–SA079

SA080–SA095

SA096–SA111

SA112–SA126

SA127

SA128

SA129

SA130

Address

Range (word)

000000h–0FFFFFh

Address

Range (byte)

000000h–1FFFFFh

E00000h–FDFFFFh

FE0000h–FE7FFFh

FE8000h-FEFFFFh

FF0000h–FF7FFFh

FF8000h–FFFFFFh

Notes

Sector Starting

Address –

Sector Ending

Address

15

4

128

32

7

700000h–7EFFFFh

7F0000h–7F3FFFh

7F4000h-7F7FFFh

7F8000h–7FBFFFh

7FC000h–7FFFFFh

Note:

All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the byte address pattern x000000h–x1FFFFh.

Table 6.5 S29VS/XS128R Sector and Memory Address Map (Bottom Boot)

Bank

Size

(Mbit)

16

Sector

Count

4

15

112

Sector Size

(Kbyte)

32

128

128

Bank

0

6

7

4

5

1

2

3

Sector

Range

SA000

SA001

SA002

SA003

SA004–SA018

SA019–SA034

SA035–SA050

SA051–SA066

SA067–SA082

SA083–SA098

SA099–SA114

SA115–SA130

Address

Range (word)

000000h–003FFFh

004000h–007FFFh

008000h–00BFFFh

00C000h–00FFFFh

010000h–0FFFFFh

Address

Range (byte)

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–1FFFFFh

Notes

Sector Starting

Address –

Sector Ending

Address

700000h–7FFFFFh E00000h–FFFFFFh

Note:

All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the byte address pattern x000000h–x1FFFFh.

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6.3

Address/Data Interface

There are two options for connection to the address and data buses.

 Address and Data Multiplexed (ADM) mode. On the S29VS-R devices, the upper address is supplied on separate signal inputs and the lower 16-bits of address are multiplexed with 16-bit data on the A/DQ15 to

A/DQ0 I/Os.

 Address-high, Address-low, and Data Multiplexed (AADM) mode. On the S29XS-R devices, the upper and lower address are multiplexed with 16-bit data on the A/DQ15 to A/D0 signal I/Os.

The two options allow use with the traditional address/data multiplexed NOR interface (S29NS family), or an address multiplexed/data multiplexed interface with the lowest signal count.

6.3.1

6.3.2

ADM Interface (S29VS256R and S29VS128R)

A number of processors use ADM interface as a way to reduce pin count. The system permanently connects the upper address bits (A[MAX:16] to the device. When AVD# is LOW it connects A[15:0] to DQ[15:0]. The address is latched on the rising edge of AVD#. When AVD# is HIGH, the system connects the data bus to

DQ[15:0]. This results in 16-pin savings from the traditional Address and Data in Parallel (ADP) interface.

AADM Interface (S29XS256R and S29XS128R)

Signal input and output (I/O) connections on a high complexity component such as an Application Specific

Integrated Circuit (ASIC) are a limited resource. Reducing signal count on any interface of the ASIC allows for either more features or lower package cost. The memory interface described in this section is intended to reduce the I/O signal count associated with the Flash memory interface with an ASIC.

The interface is called Address-High, Address-Low, and Data Multiplexed (AADM) because all address and data information is time multiplexed on a single 16-bit wide bus. This interface is electrically compatible with existing ADM 16-bit wide random access static memory interfaces but uses fewer address signals. In that sense AADM is a signal count subset of existing static memory interfaces. This interface can be implemented in existing memory controller designs, as an additional mode, with minimal changes. No new

I/O technology is needed and existing memory interfaces can continue to be supported while the electronics industry adopts this new interface. ASIC designers can reuse the existing memory address signals above

A15 for other functions when an AADM memory is in use.

By breaking up the memory address in to two time slots the address is naturally extended to be a 32-bit word address. But, using two bus cycles to transfer the address increases initial access latency by increasing the time address is using the bus. However, many memory accesses are to locations in memory nearby the previous access. Very often it is not necessary to provide both cycles of address. This interface stores the high half of address in the memory so that if the high half of address does not change from the previous access, only the low half of address needs to be sent on the bus. If a new upper address is not captured at the beginning of an access the last captured value of the upper address is used. This allows accesses within the same 128-KByte address range to provide only the lower address as part of each access.

In AADM mode two signal rising edges are needed to capture the upper and lower address portions in asynchronous mode or two signal combinations over two clocks is needed in synchronous mode. In asynchronous mode the upper address is captured by an AVD# rising edge when OE# is Low; the lower address is captured on the rising edge of AVD# with OE# High. In synchronous mode the upper address is captured at the rising clock edge when AVD# and OE# are Low; the lower address is captured at the rising edge of clock when AVD# is Low and OE# is High.

CE# going High at any time during the access or OE# returning High after RDY is first asserted High during an access, terminates the read access and causes the address/data bus direction to switch back to input mode. The address/data bus direction switches from input to output mode only after an Address-Low capture when AVD# is Low and OE# is High. This prevents the assertion of OE# during Address-High capture from causing a bus conflict between the host address and memory data signals. Note, in burst mode, this implies at least one cycle of CE# or OE# High before an Address-high for a new access may be placed on the bus so that there is time for the memory to recognize the end of the previous access, stop driving data outputs, and ignore OE# so that assertion of OE# with the new Address-high does not create a bus conflict with a new address being driven on the bus. At high bus frequencies more than one cycle may be need in order to allow time for data outputs to stop driving and new address to be driven (bus turn around time).

During a write access, the address/data bus direction is always in the input mode.

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6.3.3

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

The upper address is set to Zero or all Ones, for bottom or top boot respectively, during a Hardware Reset, operate in ADM mode during the early phase of boot code execution where only a single address cycle would be issued with the lower 16 bit of the address reaching the memory in AADM mode. The default high order address bits will direct the early boot accesses to the 128 Kbytes at the boot end of the device. Note that in

AADM interface mode this effectively requires that one of the boot sectors is selected for any address overlay mode because in the initial phase of AADM mode operation the host memory controller may only issue the low order address thus limiting the early boot time address space to the 128 Kbytes at the boot end of the device.

Default Access Mode

Upon power-up or hardware reset, the device defaults to the Asynchronous Access mode.

6.4

Bus Operations

Table 6.6

describes the required state of each input signal for each bus operation.

Operation

Standby (CE# deselect)

Hardware Reset

Table 6.6 Device Bus Operations

CE# OE# WE# CLK

Standby & Reset

H

X

X

X

X

X

X

X

AVD#

X

X

Asynchronous Mode Operations

A28-A16

X

X

Asynchronous Address Latch

(S29VS256R and S29VS128R)

Asynchronous Upper Address Latch

(S29XS256R and S29XS128R Only)

Asynchronous Lower Address Latch

(S29XS256R and S29XS128R Only)

Asynchronous Read

Asynchronous Write Latched Data

L

L

L

H

L

H

X

H

X

X

X

X

L

L

L

H

H X

X

Synchronous Mode Operations

H

H

Addr In

X

X

X

X

Latch Starting Burst Address by CLK

- ADM mode

Latch Upper Starting Burst Address by CLK

(S29XS256R and S29XS128R Only)

Latch Lower Starting Burst Address by CLK

(S29XS256R and S29XS128R Only)

Burst Read and advance to next address

(1)

L

L

L

L

H

L

H

L

H

H

H

H

L

L

L

H

Addr In

X

X

X

A/DQ 15-A/DQ0

High-Z

High-Z

Addr In

Data Output Valid

Data Input Valid

Addr In

Addr In

Addr In

Data Output Valid

RESET#

H

H

H

L

H

H

H

H

H

H

H

Terminate current Burst cycle X X X X X

Legend:

L = Logic 0, H = Logic 1, X = can be either V

IL

or V

IH

. = rising edge.

Note:

1. Data is delivered by a read operation only after the burst initial wait state count has been satisfied.

High-Z H

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6.5

Device ID and CFI (ID-CFI)

There are two traditional methods for systems to identify the type of Flash memory installed in the system.

One has been traditionally been called Autoselect and is now referred to as Device Identification (ID). A command is used to enable an address space overlay where up to 16 word locations can be read to get

JEDEC manufacturer identification (ID), device ID, and some configuration and protection status information from the Flash memory. The system can use the manufacturer and device IDs to select the appropriate driver software to use with the Flash device. The other method is called Common Flash Interface (CFI). It also uses a command to enable an address space overlay where an extendable table of standard information about how the Flash memory is organized and behaves can be read. With this method the driver software does not have to be written with the specifics of each possible memory device in mind. Instead the driver software is written in a more general way to handle many different devices but adjusts the driver behavior based on the information in the CFI table stored in the Flash memory. Traditionally these two address spaces have used separate commands and were separate overlays. However, the mapping of these two address spaces are non-overlapping and so can be combined in to a single address space and appear together in a single overlay. Either of the traditional commands used to access (enter) the Autoselect (ID) or CFI overlay will cause the now combined ID-CFI address map to appear.

A write at any sector address, in bank zero, having the least significant byte address value of AAh, with xx98h or xx90h data, switches the addressed sector to an overlay of the ID-CFI address map. These are called ID-

CFI Enter commands and are only valid when written to the specified bank when it is in read mode. The ID-

CFI address map appears within, and replaces Flash Array data of, the selected sector address range. The

ID-CFI enter commands use the same address and data values used on previous generation memories to access the JEDEC Manufacturer ID (Autoselect) and Common Flash Interface (CFI) information, respectively. While the ID-CFI address space is overlaid, any write with xxF0h data to the device will remove the overlay and return the selected sector to showing Flash memory array data. Thus, the ID-CFI address space and commands are backward compatible with standard memory discovery algorithms.

Within the ID-CFI address map there are two subsections:

Byte Address

(SA) + 00000h to 0001Fh

(SA) + 00020h to CEh h

Table 6.7 ID-CFI Address Map Overview

Size Allocated (Bytes) Description

JEDEC ID

(traditional Autoselect values)

CFI data structure

32

174

Read/Write

Read Only

Read Only

For the complete address map see Tables in

Section 11.2, Device ID and Common Flash Memory Interface

Address Map on page 58

.

6.5.1

JEDEC Device ID

The Joint Electron Device Engineering Council (JEDEC) standard JEP106T defines a method for reading the manufacturer ID and device ID of a compliant memory. This information is primarily intended for programming equipment to automatically match a device with the corresponding programming algorithm.

The JEDEC ID information is structured to work with any memory data bus width e.g. x8, x16, x32. The code values are always byte wide but are located at bus width address boundaries such that incrementing the device address inputs will read successive byte, word, or double word locations with the codes always located in the least significant byte location of the data bus. Because the data bus is word wide each code byte is located in the lower half of each word location and the high order byte is always zero.

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6.5.2

6.5.3

6.5.4

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Common Flash Memory Interface

The Common Flash Interface (CFI) specification defines a standardized data structure that may be read from a flash memory device, which allows vendor-specified software algorithms to be used for entire families of devices. The data structure contains information for system configuration such as various electrical and timing parameters, and special functions supported by the device. Software support can then be deviceindependent, JEDEC ID-independent, and forward-and-backward-compatible for the specified flash device families.

The system can read CFI information at the addresses within the selected sector as shown in

Section 11.2,

Device ID and Common Flash Memory Interface Address Map on page 58 .

Like the JEDEC Device ID information, CFI information is structured to work with any memory data bus width e.g. x8, x16, x32. The code values are always byte wide but are located at data bus width address boundaries such that incrementing the device address reads successive byte, word, or double word locations with the codes always located in the least significant byte location of the data bus. Because the data bus is word wide each code byte is located in the lower half of each word location and the high order byte is always zero.

For further information, please refer to the Spansion CFI Version 1.4 (or later) Specification and the Spansion

CFI Publication 100 (see also JEDEC publications JEP137-A and JESD68.01). Please contact JEDEC

(http://www.jedec.org) for their standards and the Spansion CFI Publications may be found at the Spansion

Web site ( http://www.spansion.com/Support/AppNotes/CFI_v1.4_VendorSpec_Ext_A1.pdf

at the time of this document’s publication).

Secured Silicon Region

The Secured Silicon region provides an extra Flash memory area that can be programmed once and permanently protected from further changes. The Secured Silicon Region is 512 bytes in length. It consists of

256 bytes for factory data and 256 bytes for customer-secured data.

The Secured Silicon Region (SSR) is overlaid in the sector address specified by the SSR enter command.

Byte Address Range

(SA) + 0000h to 00FFh

(SA) + 0100h to 01FFh

Table 6.8 Secured Silicon Region

Secure Silicon Region

Factory

Customer

Size

256 Bytes

256 Bytes

Configuration Register

The Configuration Register Enter command is only valid when written to a bank that is in Read mode. The configuration register mode address map appears within, and replaces Flash Array data of, the selected sector address range. The meaning of the configuration register bits is defined in the configuration register operation description. In configuration register mode, a write of 00F0h to any address will return the sector to

Read mode.

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7.

Device Operations

This section describes the read and write bus operations, program, erase, simultaneous read/write, handshaking, and reset features of the Flash devices.

The address space of the Flash Memory Array is divided into banks. There are three operation modes for each bank:

 Read Mode

 Embedded Algorithm (EA) Mode

 Address Space Overlay (ASO) Mode

Each bank of the device can be in any operation mode but, only one bank can be in EA or ASO mode at any one time.

In Read Mode a Flash Memory Array bank may be read by simply selecting the memory, supplying the address, and taking read data when it is ready. This is done by asynchronous or burst accesses from the host system bus. The CU puts all banks in Read mode during Power-on, a Hardware Reset, after a Command

Reset, or after a bank is returned to Read mode from EA mode.

During a burst read access valid read data is indicated by the RDY signal being High. When RDY is Low burst read data is not valid and wait states must be added. The use of the RDY signal to indicate when valid data is transferred on the system data bus is called handshaking or flow control.

EA and ASO modes are initiated by writing specific address and data patterns into command registers (see

Table 11.1 on page 56 ). The command registers do not occupy any memory locations; they are loaded by

write bus cycles with the address and data information needed to execute a command. The contents of the registers serve as input to the Control Unit (CU) and the CU dictates the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return all banks to Read mode.

The Flash memory array data in a bank that is in EA mode, is stable but undefined, and effectively unavailable for read access from the host system. While in EA mode the bank is used by the CU in the execution of commands. Typical command operations are programming or erasing of data in the Flash array.

All other banks are available for read access while the one bank is in EA mode. This ability to read from one bank while another bank is used in the execution of a command is called Simultaneous Read and Write

(SRW) and allows for continued operation of the system via the reading of data or code from other banks while one bank is programming or erasing data as a relatively long time frame background task. Only a status register read command can be used in a bank in EA mode to retrieve the EA status.

While any one of the overlay address spaces are overlaid in a bank (entered) that bank is in ASO mode and no other bank may be in EA or ASO mode. All EA activity must be completed or suspended before entering any ASO mode. A command for entering an EA or ASO mode while another bank is in EA or ASO mode will be ignored.

While an ASO mode is active (entered) in a bank, a read for Flash array data to any other bank is allowed.

ASO mode selects a specific sector for the overlaid address space. Other sectors in the ASO bank still provide Flash array data and may be read during ASO mode.

While SSR Lock, SSR, or Configuration Register is overlaid only the SSR Lock, SSR, or Configuration

Register respectively may be programmed in the overlaid sector. While any of these ASO areas are being programmed the ASO bank switches to EA mode. The ID/CFI and factory portion of the SSR ASO is not customer programmable. An attempt to program in these areas will fail.

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7.1

Asynchronous Read

The device defaults to reading array data asynchronously after device power-up or hardware reset. The device is in the Asynchronous mode when Bit 15 of the Configuration register is set to '1'. To read data from the memory array, the system must first assert CE# and AVD# to V

IL

with WE# at V

IH

and a valid address.

Address access time (t

ACC

) is equal to the delay from stable addresses to valid output data. The chip enable access time (t

CE

) is the delay from stable CE# to valid data at the outputs. See 10.9.2, AC Characteristics–

Asynchronous Read on page 49

. Any input on CLK is ignored while in Asynchronous mode.

7.1.1

7.1.2

S29VS-R ADM Access

With CE# at V

IL

, WE# at V

IH

, and OE# at V

IH

, the system presents the address to the device and drives AVD# to V

IL

. AVD# is kept at V

IL

for at least t

AVDP

ns. The address is latched on the rising edge of AVD#.

S29XS-R AADM Access

With CE# at V

IL

, WE# at V

IH

, and OE# at V

IL

, the system presents the upper address bits to DQ and drives

AVD# to V

IL

. The upper address bits are latched when AVD# transitions to V

IH

. The system then drives AVD# to V

IL

again, with OE# at V

IH

and the lower address bits on the DQ signals. The lower address bits are latched on the next rising edge of AVD#.

7.2

Synchronous (Burst) Read Mode and Configuration Register

The device is capable of continuous sequential burst operation and linear burst operation of a preset length.

In order to use Synchronous (Burst) Read Mode the configuration register bit 15 must be set to 0.

Prior to entering burst mode, the system should determine how many wait states are needed for the initial word of each burst access (see table below), what mode of burst operation is desired, how the RDY signal transitions with valid data, and output drive strength. The system would then write the configuration register command sequence. See

Configuration Register on page 26 for further details.

When the appropriate number of Wait States have occurred, data is output after the rising edge of the CLK.

Subsequent words are output t

BACC

after the rising edge of each successive clock cycle, which automatically increments the internal address counter. RDY indicates the initial latency and any subsequent waits.

7.2.1

7.2.2

S29VS-R ADM Access

To burst read data from the memory array in ADM mode, the system must assert CE# to V

IL

, and provide a valid address while driving AVD# to V

IL

for one cycle. OE# must remain at V

IH

during the one cycle that AVD# is at V

IL

. The data appears on A/DQ15 -A/DQ0 when CE# remains at V

IL

, after OE# is driven to V

IL

and the synchronous access times are satisfied. The next data in the burst sequence is read on each clock cycle that

OE# and CE# remain at V

IL

.

OE# does not terminate a burst access if it rises to V

IH

during a burst access. The outputs will go to high impedance but the burst access will continue until terminated by CE# going to V

IH

, or AVD# returns to V

IL with a new address to initiate a another burst access.

S29XS-R AADM Access

To burst read data from the memory array in AADM mode, the system must assert CE# to V

IL

, OE# must be driven to V

IL

with AVD# for one cycle while the upper address is valid. The rising edge of CLK when OE# and

AVD# are at V

IL

captures the upper 16 bits of address. The rising edge of CLK when OE# is at V

IH

and AVD# is at V

IL

latches the lower 16 bits of address. The data appears on A/DQ15 -A/DQ0 when CE# remains at V

IL

, after OE# is driven to V

IL

and the synchronous access times are satisfied. The next data in the burst sequence is read on each clock cycle that OE# and CE# remain at V

IL

.

Once OE# returns to V

IH

during a burst read the OE# no longer enables the outputs until after AVD# is at V

IL with OE# at V

IH

- which signals that address-low has been captured for the next burst access. This is so that

OE# at V

IL

may be used in conjunction with AVD# at V

IL

to indicate address-high on the A/DQ signals without enabling the A/DQ outputs, thus avoiding data output contention with Address-high.

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The device has a fixed internal address boundary that occurs every 256 Bytes (128 words). A boundary crossing latency of one or two additional wait states may be required. The device also reads data in 16 byte

(8 word) aligned and length groups. When the initial address is not aligned at the beginning of a 16 byte boundary, additional wait states may be needed when crossing the first 16 byte boundary. The number of additional wait states depends on the clock frequency and starting address location.

The following Tables show the latency for initial and boundary crossing wait state operation (note that ws = wait state).

Table 7.1 Initial Wait State vs. Frequency

Wait State

3

4

7

8

5

6

9

10

Note:

The default initial wait state delay after power on or reset is 13 wait states.

Frequency (Maximum MHz)

27

40

54

66

80

95

104

120

Table 7.2 Address Latency for 10 -13 Wait States

5

6

3

4

7

Word

0

1

2

Initial Wait

10 -13 wait states

D0

D1

D2

D3

D4

D5

D6

D7

Note:

1. This column applies to the 256 Byte boundary only.

D1

D2

D3

D4

D5

D6

D7

1 ws

D5

D6

D7

1 ws

1 ws

D2

Subsequent Clock Cycles After Initial Wait States

D3 D4 D5 D6 D7

D3

D4

D4

D5

D5

D6

D6

D7

D7

1 ws

1 ws

1 ws

D6

D7

1 ws

1 ws

1 ws

D7

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

+2 ws (1)

+2 ws

+2 ws

+2 ws

+2 ws

+2 ws

+2 ws

+2 ws

D8

D8

D8

D8

D8

D8

D8

D8

Table 7.3 Address Latency for 9 Wait States

Word

0

1

4

5

2

3

6

7

Initial Wait

9 wait states

D0

D1

D2

D3

D4

D5

D6

D7

Note:

1. This column applies to the 256 Byte boundary only.

D5

D6

D7

1 ws

D1

D2

D3

D4

D4

D5

D6

D7

D2

D3

Subsequent Clock Cycles After Initial Wait States

D3

D4

D4

D5

D5

D6

D6

D7

D7

1 ws

1 ws

1 ws

D5

D6

D7

1 ws

1 ws

1 ws

D6

D7

1 ws

1 ws

1 ws

1 ws

D7

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

+1 ws (1)

+1 ws

+1 ws

+1 ws

+1 ws

+1 ws

+1 ws

+1 ws

D8

D8

D8

D8

D8

D8

D8

D8

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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Flash Family 23

24

5

6

3

4

7

Word

0

1

2

Word

0

1

4

5

2

3

6

7

5

6

3

4

7

Word

0

1

2

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Initial Wait

8 wait states

Table 7.4 Address Latency for 8 Wait States

D3

D4

D5

D6

D7

D0

D1

D2

D1

D2

D3

D4

D5

D6

D7

1 ws

Subsequent Clock Cycles After Initial Wait States

D2 D3 D4 D5 D6

D3

D4

D4

D5

D5

D6

D6

D7

D7

1 ws

D5

D6

D7

1 ws

1 ws

D6

D7

1 ws

1 ws

1 ws

D7

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

D7

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

D8

D8

D8

D8

D8

D8

D8

D8

Initial Wait

7 wait states

Table 7.5 Address Latency for 7 Wait States

D4

D5

D6

D7

D0

D1

D2

D3

D5

D6

D7

1 ws

D1

D2

D3

D4

Subsequent Clock Cycles After Initial Wait States

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D4

D5

D6

D7

1 ws

1 ws

D5

D6

D7

1 ws

1 ws

1 ws

D6

D7

1 ws

1 ws

1 ws

1 ws

D7

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

D8

D8

D8

D8

D7

D8

D8

D8

D9

D9

D9

D9

D8

D9

D9

D9

Initial Wait

6 wait states

Table 7.6 Address Latency for 6 Wait States

D3

D4

D5

D6

D7

D0

D1

D2

D1

D2

D3

D4

D5

D6

D7

1 ws

Subsequent Clock Cycles After Initial Wait States

D2 D3 D4 D5 D6

D3

D4

D4

D5

D5

D6

D6

D7

D7

D8

D5

D6

D7

1 ws

1 ws

D6

D7

1 ws

1 ws

1 ws

D7

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

1 ws

D8

D8

D8

D8

D8

D9

D9

D9

D9

D9

D7

D8

D9

D8

D9

D10

D10

D10

D10

D10

D10

5

6

3

4

7

Word

0

1

2

Initial Wait

5 wait states

Table 7.7 Address Latency for 5 Wait States

D3

D4

D5

D6

D7

D0

D1

D2

D1

D2

D3

D4

D5

D6

D7

1 ws

Subsequent Clock Cycles After Initial Wait States

D2 D3 D4 D5 D6

D3

D4

D4

D5

D5

D6

D6

D7

D7

D8

D5

D6

D7

1 ws

1 ws

D6

D7

1 ws

1 ws

1 ws

D7

1 ws

1 ws

1 ws

1 ws

D8

D8

D8

D8

D8

D9

D9

D9

D9

D9

D7

D8

D9

D10

D10

D10

D10

D10

D8

D9

D10

D11

D11

D11

D11

D11

S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

5

6

3

4

7

Word

0

1

2

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Initial Wait

4 wait states

Table 7.8 Address Latency for 4 Wait States

D3

D4

D5

D6

D7

D0

D1

D2

D1

D2

D3

D4

D5

D6

D7

1 ws

Subsequent Clock Cycles After Initial Wait States

D2 D3 D4 D5 D6

D3

D4

D4

D5

D5

D6

D6

D7

D7

D8

D5

D6

D7

1 ws

1 ws

D6

D7

1 ws

1 ws

1 ws

D7

D8

D8

D8

D8

D8

D9

D9

D9

D9

D9

D10

D10

D10

D10

D7

D8

D9

D10

D11

D11

D11

D11

D8

D9

D10

D11

D12

D12

D12

D12

7.2.3

7.2.4

Word

0

1

4

5

2

3

6

7

Initial Wait

3 wait states

Table 7.9 Address Latency for 3 Wait States

D4

D5

D6

D7

D0

D1

D2

D3

D5

D6

D7

1 ws

D1

D2

D3

D4

Subsequent Clock Cycles After Initial Wait States

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D4

D5

D6

D7

1 ws

1 ws

D5

D6

D7

D8

D8

D8

D6

D7

D8

D9

D9

D9

D7

D8

D9

D10

D10

D10

D8

D9

D10

D11

D11

D11

D11

D12

D12

D12

D7

D8

D9

D10

D12

D13

D13

D13

D8

D9

D10

D11

Continuous Burst

The device continues to output sequential burst data from the memory array, wrapping around to address

0000000h after it reaches the highest addressable memory location, until the system drives CE# high,

RESET# low, or AVD# low in conjunction with a new address. See Table 6.6, Device Bus Operations on page 18

.

If the host system crosses a bank boundary while reading in burst mode, and the subsequent bank is not programming or erasing, an address boundary crossing latency might be required. If the host system crosses the bank boundary while the subsequent bank is programming or erasing, continuous burst halts (RDY will be disabled and data will continue to be driven).

8-, 16-Word Linear Burst with Wrap Around

Table 7.10 Burst Address Groups

Mode

8-word

16-word

Group Size

16 bytes

32 bytes

Group Byte Address Ranges

0-Fh, 10-1Fh, 20-2Fh,...

0-1Fh, 20-3Fh, 30-4Fh,...

The remaining two modes are fixed length linear burst with wrap around, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in

a single burst sequence for a given mode (see Table 7.10

).

As an example: if the starting address in the 8-word mode is system byte address 3Ch, the address range to be read would be byte address 30-3Fh, and the burst sequence would be 3C-3E-30-32-34-36-38-3Ah. The burst sequence begins with the starting address written to the device, wraps back to the first address in the selected group, and outputs a maximum of 8 words. No additional wait states will be required within the 8word burst. The 8th word will continue to be driven until the burst operation is aborted (CE# goes to V

IH

, a new address is latched in for a new burst operation, or a hardware reset). In a similar fashion, the 16-word

Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Additional wait states could be added the first time the

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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Flash Family 25

26

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n ) device crosses from one to the other group of 8 words in a 16-word burst. The number will depend on the starting address and the wait state set within the configuration register. See Table 7.3 on Page 21 to

Table 7.9 on page 25

. Note that in these two burst read modes the address pointer does not cross the

boundary that occurs every 128 words; thus, no 128-word address boundary crossing wait states are inserted for linear burst with wrap.

Figure 7.1 Synchronous Read

Load Initial Address

Address = RA

RA = Read Address

Wait Programmable

Wait State Setting

CR0.14 - CR0.11 sets initial access time

(from address latched to valid data) from 3 to 13 clock cycles

Read Initial Data

RD = DQ[15:0]

RD = Read Data

Wait X Clocks (if required):

Additional Latency Due to Starting

Address and Clock Frequency

Read Next Data

RD = DQ[15:0]

Yes

No

Crossing

Boundary?

No

End of Data?

Yes

Completed

7.2.5

Configuration Register

Configuration register (CR) sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the device defaults to the idle state, and the configuration register settings are in their default state. The host system should determine the proper settings for the configuration register, and then execute the Set Configuration Register command sequence, before attempting burst operations. The

Configuration Register can also be read using a command sequence (see

Table 11.1 on page 56 ). The table

below describes the register settings and indicates the default state of each bit after power-on or a hardware reset. The configuration register bits are not affected by a command reset.

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

CR BIt

CR.15

CR.14

CR.13

CR.12

CR.11

CR.6

CR.5

CR.4

CR.3

CR.2

CR.1

CR.0

CR.10

CR.9

CR.8

CR.7

Function

Device Read Mode

Programmable

Read Wait States

RDY Polarity

Reserved

RDY Timing

Output Drive Strength

Reserved

Reserved

Reserved

Reserved

Burst Length

Table 7.11 Configuration Register

Settings (Binary)

0 = Synchronous Read Mode

1 = Asynchronous Read Mode (Default)

0000 = Reserved

0001 =

0010 =

Initial data is valid on the

3rd

4th

0011 =

.

..

.

..

5th rising CLK edge after addresses are latched

1011 =

1100 = Reserved

1101 = Reserved

1110 = Reserved

13th (Default)

1111 = Reserved

0 = RDY signal is active low

1 = RDY signal is active high (Default)

0 = Reserved

1 = Reserved (Default)

0 = RDY active one clock cycle before data

1 = RDY active with data (Default)

0 = Full Drive= Current Driver Strength (Default)

1 = Half Drive

0 = Reserved

1 = Reserved (Default)

0 = Reserved (Default)

1 = Reserved

0 = Reserved (Default)

1 = Reserved

0 = Reserved

1 = Reserved (Default)

000 = Continuous (Default)

010 = 8-Word (16-Byte) Linear Burst with wrap around

011 = 16-Word (32-Byte) Linear Burst with wrap around

(All other bit settings are reserved)

7.2.5.1

Device Read Mode

Configuration Register bit 15 (CR.15) controls whether read accesses via the bus interface are in asynchronous or burst mode. Asynchronous mode is the default after power-on or hardware reset. Write accesses are always conducted with asynchronous mode timing, independent of the read mode.

7.2.5.2

Wait States

Configuration Register bits 14 to 11 (CR.[14..11]) define the number of delay cycles after the AVD# Low cycle that captures the initial address until the cycle that read data is valid. The bits from 14 to 11 are in most to least significant order. The random address access at the beginning of each read burst takes longer than the subsequent read cycles. The memory bus interface must be told how many cycles to wait before driving valid data then advancing to the next data word. The number of initial wait cycles will vary with the memory clock rate. The number of wait states is found in the wait state table information above. The minimum number of wait cycles is three. The maximum is 13. The default after power-on or hardware reset is 13 cycles.

When the appropriate number of Wait States have occurred, data is output after the rising edge of the CLK.

Subsequent words are output t

BACC

after the rising edge of each successive clock cycle, which automatically increments the internal address counter.

7.2.5.3

RDY Polarity

Configuration Register bit 10 (CR.10) controls whether the RDY signal indicates valid data when High or when Low. When this bit is zero the RDY signal indicates data is valid when the signal is Low. When this bit is one the RDY signal indicates data is valid when the signal is High. The default for this bit is set to one after power-on or a hardware reset.

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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Flash Family 27

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

7.2.5.4

RDY Timing

Configuration Register bit 8 (CR.8) controls whether the RDY signal indicates valid data on the same cycle that data is valid or one cycle before data is valid. When this bit is zero the RDY signal indicates data is valid in the same cycle the data is valid. When this bit is one the RDY signal indicates data is valid one cycle before data is valid. The default for this bit is set to one after power-on or a hardware reset.

7.2.5.5

Output Drive Strength

Configuration Register bit 7 (CR.7) controls whether the data outputs drive with full or half strength. When this bit is zero the data outputs drive with full strength. When this bit is one the data outputs drive with half strength. The default for this bit is cleared to zero after power-on or a hardware reset.

7.2.5.6

Burst Length

Configuration Register bits 2 to 0 (CR.[2..0]) define the length of burst read accesses. The bits from 2 to 0 are in most to least significant order. See the register table for code meaning & default value.

7.3

Status Register

The status of program and erase operations is provided by a status register. A status register read command is written followed by a read of the status register for each access of the status register information. The Clear

Status Register Command will reset the status register. The status register can be read in synchronous or asynchronous mode.

Table 7.12 Status Register Reset State

Bit 7

Device Ready

Bit.

Overall status

DRB

1 at Reset

Bit 6

Erase Suspend

Status Bit

ESSB

0 at Reset

Bit 5

Erase Status

Bit

Bit 4

Program

Status Bit

Bit 3

RFU

Bit 2

Program

Suspend

Status Bit

Bit 1

Sector Lock

Status Bit

ESB

0 at Reset

PSB

0 at Reset

RFU

0 at Reset

PSSB

0 at Reset

Notes:

1. Status bits higher than Bit 7 are undefined.

2. Bit 7 reflects the device status.

3. If the device is busy, Bit 0 is used to check whether the addressed bank is busy or some other bank is busy.

4. All the other bits reflect the status of the device.

SLSB

0 at Reset

Bit 0

Bank Status Bit

BSB

0 at Reset

Table 7.13 Status Register - Bit 7

Bit 7

Device Ready

Bit.

Overall status

Bit 6

Erase Suspend

Status Bit

Bit 5

Erase Status

Bit

Bit 4

Program

Status Bit

Bit 3

RFU

DRB

0

Device busy programming or erasing

1

Device ready

ESSB

Invalid

VALID

ESB

Invalid

VALID

PSB

Invalid

VALID

RFU

Invalid

VALID

Notes:

1. Bit 7 is set when there is no erase or program operation in progress in the device.

2. Bits 1 through 6 are valid if and only if Bit 7 is set.

Bit 2

Program

Suspend

Status Bit

PSSB

Invalid

VALID

Bit 1 Bit 0

Sector Lock

Status Bit

Bank Status Bit

SLSB BSB

Invalid VALID

VALID VALID

28 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Table 7.14 Status Register - Bit 6

Bit 7

Device Ready

Bit.

Overall status

Bit 6

Erase Suspend

Status Bit

ESSB DRB

1

Bits 6:1 only valid when Bit

7 = 1

1

Bit 6:1 only valid when Bit

7 = 1

0

No Erase in

Suspension

1

Erase in

Suspension

Bit 5

Erase Status

Bit

ESB

X

X

Bit 4

Program

Status Bit

PSB

X

X

Bit 3

RFU

RFU

X

X

Bit 2

Program

Suspend

Status Bit

PSSB

X

X

Bit 1

Sector Lock

Status Bit

SLSB

X

X

Bit 0

Bank Status Bit

BSB

X

X

Notes:

1. Upon issuing the “Erase Suspend” Command, the user must continue to read status until DRB becomes 1 before accessing another sector within the same bank.

2. Cleared by “Erase Resume” Command.

Table 7.15 Status Register - Bit 5

Bit 7

Device Ready

Bit.

Overall status

Bit 6

Erase Suspend

Status Bit

ESSB DRB

1

Bits 6:1 only valid when Bit

7 = 1

1

Bit 6:1 only valid when Bit

7 = 1

X

X

Bit 5

Erase Status

Bit

ESB

0

Erase successful

1

Erase error

Bit 4

Program

Status Bit

PSB

X

X

Bit 3

RFU

RFU

X

X

Notes:

1. ESB bit reflects “success” or “failure” of the most recent erase operation.

2. Cleared by “Clear Status Register” Command as well as by hardware reset.

Bit 2

Program

Suspend

Status Bit

PSSB

X

X

Bit 1 Bit 0

Sector Lock

Status Bit

Bank Status Bit

SLSB BSB

X

X

X

X

Table 7.16 Status Register - Bit 4

Bit 7

Device Ready

Bit.

Overall status

DRB

Bit 6

Erase Suspend

Status Bit

ESSB

1

Bits 6:1 only valid when Bit

7 = 1

1

Bit 6:1 only valid when Bit

7 = 1

X

X

Bit 5

Erase Status

Bit

ESB

X

X

Bit 4

Program

Status Bit

PSB

0

Program successful

1

Program fail

Bit 3

RFU

RFU

X

X

Notes:

1. PSB bit reflects “success” or “failure” of the most recent program operation.

2. Cleared by “Clear Status Register” Command as well as by hardware reset.

Bit 2

Program

Suspend

Status Bit

PSSB

X

X

Bit 1 Bit 0

Sector Lock

Status Bit

Bank Status Bit

SLSB BSB

X

X

X

X

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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Flash Family 29

30

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Table 7.17 Status Register - Bit 3

Bit 7

Device Ready

Bit.

Overall status

Bit 6

Erase Suspend

Status Bit

DRB

1

Bits 6:1 only valid when Bit

7 = 1

ESSB

X

Bit 5

Erase Status

Bit

ESB

X

Bit 4

Program

Status Bit

PSB

X

Bit 3

RFU

RFU

X

Notes:

1. This Register is reserved for future use.

2. Cleared by “Clear Status Register” Command as well as by hardware reset.

Bit 2

Program

Suspend

Status Bit

PSSB

X

Bit 1 Bit 0

Sector Lock

Status Bit

Bank Status Bit

SLSB BSB

X X

Table 7.18 Status Register - Bit 2

Bit 7

Device Ready

Bit.

Overall status

DRB

1

Bits 6:1 only valid when Bit

7 = 1

Bit 6

Erase Suspend

Status Bit

ESSB

X

Bit 5

Erase Status

Bit

ESB

X

Bit 4

Program

Status Bit

PSB

X

Bit 3

RFU

RFU

X

Bit 2

Program

Suspend

Status Bit

PSSB

0

No Program in suspension

Bit 1

Sector Lock

Status Bit

SLSB

X

Bit 0

Bank Status Bit

BSB

X

1

Bit 6:1 only valid when Bit

7 = 1

X X X X

1

Program in suspension

X X

Notes:

1. Upon issuing the “Program Suspend” Command, the user must continue to read status until DRB becomes 1 before accessing another sector within the same bank.

2. Cleared by “Program Resume” Command.

Table 7.19 Status Register - Bit 1

Bit 7

Device Ready

Bit.

Overall status

DRB

1

Bits 6:1 only valid when Bit

7 = 1

Bit 6

Erase Suspend

Status Bit

ESSB

X

Bit 5

Erase Status

Bit

ESB

X

Bit 4

Program

Status Bit

PSB

X

Bit 3

RFU

RFU

X

Bit 2

Program

Suspend

Status Bit

PSSB

X

Bit 1

Sector Lock

Status Bit

SLSB

0

Sector not locked during operation

Bit 0

Bank Status Bit

BSB

X

1

Bit 6:1 only valid when Bit

7 = 1

X X X X X

1

Sector locked error

X

Notes:

1. SLSB indicates that a program or erase operation failed to program or erase because the sector was locked or the operation was attempted on the protected Secure Silicon Region.

2. SLSB reflects the status of the most recent program or erase operation.

3. SLSB is cleared by “Clear Status Register” or by hardware reset.

S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

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Table 7.20 Status Register - Bit 0

Bit 7

Device Ready

Bit.

Overall status

DRB

Bit 6

Erase Suspend

Status Bit

ESSB

Bit 5

Erase Status

Bit

ESB

Bit 4

Program

Status Bit

PSB

Bit 3

RFU

RFU

0

Bits 6:1 only valid when Bit

7 = 1

X X X X

0

Bits 6:1 only valid when Bit

7 = 1

1

Bit 6:1 only valid when Bit

7 = 1

1

Bit 6:1 only valid when Bit

7 = 1

X

X

X

X

X

X

X

X

X

X

X

X

Note:

1. BSB is used to check if a program or erase operation in progress in the current bank.

Bit 2

Program

Suspend

Status Bit

PSSB

X

X

X

X

Bit 1

X

X

X

Bit 0

Sector Lock

Status Bit

Bank Status Bit

SLSB BSB

0

Program or

Erase op. in addressed

Bank

1

Program or

Erase op. in other Bank

0

No active

Program or

Erase op.

X

1 invalid

7.4

Blank Check

The Blank Check command will confirm if the selected sector is erased.

The Blank Check command does not allow for reads to the array during the Blank Check. Reads to the array while this command is executing will return unknown data.

 Blank Check is only functional in Asynchronous Read mode (Configuration Register - CR [15] = 1).

 To initiate a Blank Check on Sector X, write 33h to address 555h in Sector X. while the device is in the Idle state (not during program suspend, not during erase suspend, ...).

 The Blank Check command may not be written while the device is actively programming or erasing. Blank

Check does not support simultaneous operations.

 Use the Status Register read to confirm if the device is still busy and when compete if the sector is blank or not.

 Bit 5 of the Status Register will be cleared to zero if the sector is erased and set to one if not erased.

 Bit 7 & Bit 0 of the Status Register will show if the device is performing a Blank Check (similar to an erase operation).

 As soon as any bit is found to not be erased, the device will halt the operation and report the results.

 Once the Blank Check is completed, the device will to return to the Idle State.

7.5

Simultaneous Read/Write

The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank (note: programming to the sector being erased is not allowed).

Figure 10.14, Back-to-Back Read/Write Cycle Timings - ADM Interface on page 54 shows how

read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the

DC

Characteristics on page 45

table for read-while-program and read-while-erase current specification.

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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D a t a S h e e t

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7.6

Writing Commands/Command Sequences

The device accepts Asynchronous write bus operations. During an asynchronous write bus operation, the system must drive CE# and WE# to V

IL

and OE# to V

IH

when providing an address and data. While an address is valid, AVD# must be driven to V

IL

. Addresses are latched on the rising edge of AVD#, data is latched on the rising edge of WE#.

All writes to the memory are single word length and follow asynchronous timing. However, it is allowed to leave the host and memory interfaces in synchronous mode as long as the host synchronous timing for a single word synchronous write can meet the timing requirements of the memory device write cycle. Generally a synchronous write would include Clock toggling during the write but, it is also allowed for Clock to be at V

IL during the write.

If the device is in the Synchronous Read Mode (CR.15 = 0), the addresses are latched on the rising edge of

CLK when AVD# is at V

IL

, while data is latched on the rising edge of WE#. If CLK is held at V

IL

, addresses are latched on the rising edge of AVD#. CLK should not be held at V

IH

when writing commands while the device is in Synchronous Read Mode. See the

Table 6.6, Device Bus Operations on page 18

for the signal combinations that define each phase of a write bus operation to the device. Each write is a command or part of a command sequence to the device. The address provided in each write operation may be a bit pattern used to help identify the write as a command to the device. The upper portion of the address may also select the bank or sector in which the command operation is to be performed. A Bank Address (BA) is the set of address bits required to uniquely select a bank. Similarly, a Sector Address (SA) is the address bits required to uniquely select a sector. The data in each write identifies the command operation to be performed or

supplies information needed to perform the operation. See Table 11.1, Command Definitions on page 56 for

a listing of the commands accepted by the device. I

CC2

in DC Characteristics on page 45 represents the

active current specification for an Embedded Algorithm operation.

7.7

Program/Erase Operations

 When the Embedded Program algorithm is complete, the device returns to the calling routing (Erase

Suspend, SSR Lock, Secure Silicon Region, or Idle State).

 The system can determine the status of the program operation by reading the Status Register. Refer to

Status Register on page 28

for information on these status bits.

.

 A 0 cannot be programmed back to a 1. A succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1 old data new data results

0011

0101

0001

 Any commands written to the device during the Embedded Program Algorithm are ignored except the

Program Suspend, and Status Read command. Any commands written to the device during the Embedded

Erase Algorithm are ignored except Erase Suspend and Status Read command. Reading from a bank that is not programming or erasing is allowed.

 A hardware reset immediately terminates the program/erase operation and the program command sequence should be reinitiated once the device has returned to the idle state, to ensure data integrity.

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7.7.1

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Write Buffer Programming

Write Buffer Programming allows the system to write 1 to 64 bytes in one programming operation. The Write

Buffer Programming command sequence is initiated by first writing the Write Buffer Load command written at the Sector Address + 555h in which programming occurs. Next, the system writes the number of word

locations minus 1 at the Sector Address + 2AAh. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The Sector

Address must match during the Write Buffer Load command and during the Write Word Count command and the Sector must be unlocked or the operation will abort and return to the initiating state.

The write buffer is used to program data within a 64 byte page aligned on a 64 byte boundary. Thus, a full page Write Buffer programming operation must be aligned on a page boundary. Programming operations of less than a full page may start on any word boundary but may not cross a page boundary.

The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. The Sector address must match the Write

Buffer Load Sector Address or the operation will abort and return to the initiating state. All subsequent address/data pairs must be in sequential order. All write buffer addresses must be within the same page. If the system attempts to load data outside this range, the operation aborts after the Write to Buffer command is executed and the device will indicate a Program Fail in the Status Register at bit location 4 (PSB). A “Clear

Status Register” must be issued to clear the PSB status bit.

The counter decrements for each data load operation.

Once the specified number of write buffer locations have been loaded, the system must then write the

Program Buffer to Flash command at the Sector Address + 555h. The device then goes busy. The Embedded

Program algorithm automatically programs and verifies the data for the correct data pattern. The system is not required to provide any controls or timings during these operations. If the incorrect number of write buffer locations have been loaded and the Program Buffer to Flash command is issued, the Status Register will indicate a program fail at bit location 4 (PSB). A “Clear Status Register” must be issued to clear the PSB status bit.

The write-buffer embedded programming operation can be suspended using the Program Suspend command. When the Embedded Program algorithm is complete, the device then returns to Erase Suspend,

SSR Lock, Secure Silicon Region, or Idle state. The system can determine the status of the program

operation by reading the Status Register. Refer to Status Register on page 28

for information on these status bits.

The Write Buffer Programming Sequence can be Aborted in the following ways:

 Load a value greater than the buffer size during the Number of Locations step.

 Write an address that is outside the Page of the Starting Address during the write buffer data loading stage of the operation.

The Write Buffer Programming Sequence can be stopped and reset by the following: Hardware Reset or

Power cycle.

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D a t a S h e e t

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Software Functions and Sample Code

Table 7.21 Write Buffer Program

Cycle

1

2

Description

Write Buffer Load Command

Operation

Write

Byte Address

Sector Address + AAAh

Word Address

Sector Address + 555h

Write Word Count Write Sector Address + 555h Sector Address + 2AA

Number of words (N) loaded into the write buffer can be from 1 to 32 words.

Load Buffer Word N

Write Buffer to Flash

Write

Write

Program Address, Word N

Sector Address + AAAh Sector Address + 555h

Data

0025h

Word Count (N–1)h

3 to 34

Last

Word N

0029h

Notes:

1. Base = Base Address.

2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to

37.

3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.

The following is a C source code example of using the write buffer program function. Refer to the Spansion

Low Level Driver User’s Guide (available on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

/* Example: Write Buffer Programming Command */

/* NOTES: Write buffer programming limited to 32 words. */

/* All addresses to be written to the flash in */

/* one operation must be within the same flash */

/* page. A flash page begins at addresses */

/* evenly divisible by 0x20. */

UINT16 *src = source_of_data; /* address of source data */

UINT16 *dst = destination_of_data; /* flash destination address */

UINT16 wc = words_to_program -1; /* word count (minus 1) */

*( (UINT16 *)sector_address + 0x555 ) = 0x0025; /* write write buffer load command */

*( (UINT16 *)sector_address + 0x2AA) = wc; do{

/* write word count (minus 1) */

*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */

dst++; /* increment destination pointer */

src++; /* increment source pointer */ wc--; /* decrement word count */

}while ( wc >= 0 ); /* do it again */

*( (UINT16 *)sector_address + 0x555) = 0x0029; /* write confirm command */

/* poll for completion */

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7.7.2

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Program Suspend/Program Resume Commands

The Program Suspend command allows the system to interrupt an embedded programming operation or a

Write to Buffer programming operation so that data can read from any non-suspended sector. When the

Program Suspend command is written during a programming process, the device halts the programming operation within t

PSL

(program suspend latency) and updates the status bits. Addresses are don't-cares when writing the Program Suspend command.

After the programming operation has been suspended, the system can read array data from any nonsuspended sector and page. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase

Suspend or Program Suspend.

After the Program Resume command is written, the device reverts to programming and the status bits are updated. The system can determine the status of the program operation by reading the Status Register, just

as in the standard program operation. See Status Register on page 28

for more information.

The system must write the Program Resume command to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program

Suspend command can be written after the device has resumed programming.

Software Functions and Sample Code

Table 7.22 Program Suspend

Cycle

1

Operation

Write

Byte Address

Bank Address

Word Address

Bank Address

Data

0051h

The following is a C source code example of using the program suspend function. Refer to the Spansion Low

Level Driver User’s Guide (available on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

/* Example: Program suspend command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x0051; /* write suspend command */

Cycle

1

Operation

Write

Table 7.23 Program Resume

Byte Address

Sector Address + 000h

Word Address

Sector Address + 000h

Data

0050h

The following is a C source code example of using the program resume function. Refer to the Spansion Low

Level Driver User’s Guide (available on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

/* Example: Program resume command */

*( (UINT16 *)sector_address + 0x000 ) = 0x0050; /* write resume command */

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36

7.7.3

7.7.4

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Sector Erase

The sector erase function erases one sector in the memory array. (See Table 11.1 on page 56

) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations. Sector Erase requires 2 commands. Each of the

Sector Addresses must match, the lower addresses must be correct, and the sector must be unlocked previously by executing the Sector Unlock command and must not be locked by the Sector Lock Range command.

When the Embedded Erase algorithm is complete, the bank returns to idle state and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading the Status

Register. See Status Register on page 28 for information on these status bits.

Once the sector erase operation has begun, only reading from outside the erase bank, read of Status

Register, and the Erase Suspend command are valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence must be reinitiated once the device has returned to idle state, to ensure data integrity.

See

Program/Erase Operations on page 32 for parameters and timing diagrams.

Software Functions and Sample Code

Table 7.24 Sector Erase

Cycle

1

2

Description

Setup Command

Sector Erase Command

Operation

Write

Write

Byte Address

Sector Address + AAAh

Sector Address + 555h

Word Address

Sector Address + 555h

Sector Address + 2AA

Data

0080h

0030h

The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level

Driver User’s Guide (available on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

/* Example: Sector Erase Command */

*( (UINT16 *)sector_address + 0x555 ) = 0x0080; /* write setup command */

*( (UINT16 *)sector_address + 0x2AA) = 0x0030; /* write sector erase command */

Chip Erase

The chip erase function erases the complete memory array. (See

Table 11.1 on page 56 ). The device does

not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful chip erase, all locations within the device contain FFFFh. The system is not required to provide any controls or timings during these operations. Chip Erase requires 2 commands. Each of the Sector Addresses must match, the lower addresses must be correct, and Sector 0 must be unlocked previously by executing the

Sector Unlock command. If any sector has been locked by the Sector Lock Range command, the Chip Erase command will not start.

When the Embedded Erase algorithm is complete, the device returns to idle state and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can not read data from the device. The system can determine the status of the erase operation by reading the Status Register.

See

Status Register on page 28 for information on these status bits.

Once the chip erase operation has begun, only a Status Read, Hardware RESET or Power cycle are valid. All other commands are ignored. However, note that a Hardware Reset or Power Cycle immediately terminates the erase operation. If that occurs, the chip erase command sequence must be reinitiated once the device has returned to idle state, to ensure data integrity.

See

Program/Erase Operations on page 32 for parameters and timing diagrams.

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7.7.5

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Software Functions and Sample Code

Table 7.25 Chip Erase

Cycle

1

2

Description

Setup Command

Chip Erase Command

Operation

Write

Write

Byte Address

Base + AAAh

Base + 555h

Word Address

Base + 555h

Base + 2AA

Data

0080h

0010h

The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level

Driver User’s Guide (available on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

/* Example: Chip Erase Command */

/* Note: Cannot be suspended */

*( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0010; /* write chip erase command */

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the device. This command is valid only during the sector erase operation. The

Erase Suspend command is ignored if written during the chip erase operation.

When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of t

ESL

(erase suspend latency) to suspend the erase operation and update the status bits.

After the erase operation has been suspended, the bank enters the erase-suspend mode. The system can read data from or program data to the device. Reading at any address within erase-suspended sectors produces undetermined data. The system can read the Status Register to determine if a sector is actively

erasing or is erase-suspended. Refer to Status Register on page 28 for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the erase-suspend mode. The system can determine the status of the program operation by reading the Status Register, just as in the standard program operation.

To resume the sector erase operation, the system must write the Erase Resume command. The device will revert to erasing and the status bits will be updated. Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after the chip has resumed erasing.

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7.7.6

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Software Functions and Sample Code

Table 7.26 Erase Suspend

Cycle

1

Operation

Write

Byte Address

Bank Address

Word Address

Bank Address

Data

00B0h

The following is a C source code example of using the erase suspend function. Refer to the Spansion Low

Level Driver User’s Guide (available on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

/* Example: Erase suspend command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */

Cycle

1

Operation

Write

Table 7.27 Erase Resume

Byte Address

Sector Address + 000h

Word Address

Sector Address + 000h

Data

0030h

The following is a C source code example of using the erase resume function. Refer to the Spansion Low

Level Driver User’s Guide (available on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

/* Example: Erase resume command */

*( (UINT16 *)sector_address + 0x000 ) = 0x0030; /* write resume command */

/* The flash needs adequate time in the resume state */

Accelerated Program/Sector Erase

Accelerated write buffer programming, and sector erase operations are enabled through the V

PP

function.

This method is faster than the standard chip program and sector erase command sequences.

The accelerated write buffer program and sector erase functions must not be used more than 50

times per sector. In addition, accelerated write buffer program and sector erase should be performed at room temperature (30°C ±10°C).

If the system asserts V

HH

on V

PP

, the device automatically uses the higher voltage on the input to reduce the time required for program and erase operations. Removing V

HH

from the V

PP

input, upon completion of the embedded program or erase operation, returns the device to normal operation.

 Simultaneous operations are not supported while V

PP

is at V

HH

. The V

PP

pin must not be at V

HH

for operations other than accelerated write buffer programming, accelerated sector erase, and status register read or device damage may result.

 The V

PP

pin must not be left floating or unconnected; inconsistent behavior of the device may result.

 There is a minimum of 100 ms required between accelerated write buffer programming and a subsequent accelerated sector erase.

7.8

Handshaking

The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin, which is a dedicated output controlled by CE#.

When CE# input is Low, the RDY output signal is actively driven. When both of the CE# inputs are High the

RDY output is high-impedance. When CE# input and OE# input is Low, the A/DQ15-A/DQ0 output signals are actively driven. When both of the CE# inputs are High, or the OE# input is High, the A/DQ15-A/DQ0 outputs are high-impedance.

When the device is operated in synchronous mode, and OE# is low (active), the initial word of burst data becomes available after the rising edge of the RDY. CR.8 in the Configuration Register allows the host to specify whether RDY is active at the same time that data is ready, or one cycle before data is ready (see

Table 7.11 on page 27 ).

When the device is operated in asynchronous mode, RDY will be high when CE# is low (active).

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D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

7.9

Hardware Reset

The RESET# input provides a hardware method of resetting the device to idle state. When RESET# is driven low for at least a period of t

RP

, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset operation. The device also resets the internal state machine to idle state. Hardware Reset clears the AADM upper address register to zero.

To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence.

When RESET# is held at V

SS

, the device draws CMOS standby current (I

CC4

). If RESET# is held at V

IL

, but not at V

SS

, the standby current is greater.

See

Figure 10.10

for timing diagrams

7.10

Software Reset

Software reset is part of the command set (see Table 11.1 on page 56

) that also returns the device to idle state and must be used for the following conditions:

1. Exit ID/CFI mode

2. Exit Secure Silicon Region mode

3. Exit Configuration Register mode

4. Exit SSR Lock mode

Reset commands are ignored once programming/erasure has begun until the operation is complete.

Software Functions and Sample Code

Table 7.28 Reset

Cycle

Reset Command

Note:

Base = Base Address.

Operation

Write

Byte Address

Base + xxxh

Word Address

Base + xxxh

Data

00F0h

The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver

User’s Guide (available on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

/* Example: Reset (software reset of Flash state machine) */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;

8.

Sector Protection/Unprotection

The Sector Protection/Unprotection feature disables or enables programming or erase operations in one or multiple sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array.

8.1

Sector Lock/Unlock Command

The Sector Lock/Unlock command sequence allows the system to protect all sectors from accidental writes or, unprotect one sector to allow programming or erasing of the sector. When the device is first powered up, all sectors are unlocked. To lock all sectors (enter protected mode), a Sector Lock/Unlock command must be issued to any Sector Address. Once this command is issued, only one sector at a time can be unlocked until power is cycled. To unlock a sector, the system must write the Sector Lock/Unlock command sequence. Two cycles are first written: addresses are x555h and x2AAh, and data is 60h. During the third cycle, the sector address (SLA) and unlock command (60h) are written, while specifying with address A6 whether that sector should be locked (A6 = V

IL

) or unlocked (A6 = V

IH

).

A Program or Erase operation will check the unlocked Sector Address only at the beginning of the Program or

Erase operation. It is not necessary to keep the sector being Programmed or Erased unlocked during the

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D a t a S h e e t

( A d v a n c e I n f o r m a t i o n ) operation. The system can change the unlocked Sector after programming or erasing the sector has begun.

An Erase Resume or Program Resume command does not check the value of the unlocked Sector.

If A6 is set to V

IL

,then all sectors in the array will be locked. Only one sector at a time can be unlocked.

If a Sector Lock/Unlock command is issued to a sector that is protected by the Sector Lock Range command, all sectors in the part will be locked.

8.2

Sector Lock Range Command

This command allows a range of sectors to be protected from program or erase (locked) until a hardware reset or power is removed from the device. Once this command is issued, all sectors are protected and the

Sector Lock/Unlock command is ignored for the selected range of sectors. Sectors outside of the selected range must be unlocked one sector at a time using the Sector Unlock command in order to be erased/ programmed.

Two cycles are first written: addresses are x555h and x2AAh, and data is 60h. During the third cycle, the sector address (SLA) and load sector address command (61h) is written. This cycle sets the lower sector address of the range. During the fourth cycle, the sector address (SLA) and load sector address command

(61h) is written. This cycle sets the upper sector address of the range. The addresses reference a large sector address range (128 KB). If a sector address matches the location of the four small sectors, all of the small sectors will be protected as a group. The sectors selected by the lower and upper address, as well as all sectors between these sectors, are protected from program and erase until a hardware reset or power is removed. If the lower and upper sector addresses are for the same sector then only that one sector is locked.

Flash address input A6 (system byte address bit a7) during both address cycles must be zero (A6 = V

IL

) for the addresses to be accepted as valid.

If the first sector address cycle contains an address which is higher than the second sector address cycle, then the command sequence will be invalid. If A6 is set to one (A6 = V

IH

) on either address cycle, the command sequence will disable subsequent Sector Lock Range commands.

A valid Sector Lock Range command sequence is accepted only once after a Hardware Reset or initial power up. Additional Sector Lock Range commands will be ignored.

If a Sector Unlock command tries to unlock a Sector within the Sector Lock Range, the Sector will remain in locked state. Similarly, if a Sector that is currently unlocked by the Sector Unlock command is overlapped by a subsequent Sector Lock Range, that sector will be locked and program erase operations to that region will be ignored.

This command is generally used by trusted boot code. After power on reset boot code has the option to check for any need to update sectors before locking them for the remainder of power on time. Once boot code is satisfied with the content of sectors to be protected the Sector Lock Range command is used to lock sectors against any program or erase during normal system operation. This adds an extra layer of protection for critical data that must be protected against accidental or malicious corruption. Yet, maintains flexibility for trusted boot code to perform occasional updates of the data. It is important to issue the Sector Lock Range command even if no sectors are to be protected so that sectors that should remain available for update cannot be later locked by accidental or malicious code behavior.

8.3

Hardware Data Protection Methods

There are additional hardware methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods:

8.3.1

V

PP

Method

Once V

PP

input is set to V

IL

, all program and erase functions are disabled and hence all Sectors (including the

Secure Silicon Region) are protected.

8.3.2

Low V

CC

Write Inhibit

When V

CC

is less than V

LKO

, the device does not accept any write cycles. This protects data during V power-up and power-down.

CC

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8.3.3

8.3.4

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

The command register and all internal program/erase circuits are disabled. Subsequent writes are ignored until V

CC

is greater than V

LKO

. The system must provide the proper signals to the control inputs to prevent unintentional writes when V

CC

is greater than V

LKO

.

Write Pulse Glitch Protection

Noise pulses of less than 3 ns (typical) on OE#, WE#, or CE# do not initiate a write cycle.

Power-Up Write Inhibit

If CE# = RESET# = V

IL

and OE# = V

IH

during power up, the device does not accept write commands. The internal state machine is automatically reset to the idle state on power-up.

8.4

SSR Lock

The SSR Lock consists of two bits. The Customer Secure Silicon Region Protection Bit is bit 0. The Factory

Secure Silicon Region Protection Bit is bit 1. All other bits in this register return “1.” If the Customer Secure

Silicon Region Protection Bit is set to “0,” the Customer Secure Silicon Region is protected and can not be programmed. If this bit is set to “1,” the Customer Secure Silicon Region is available for programming. Once this area has been programmed, the SSR Lock bit 0 should be programmed to “0.”

8.5

Secure Silicon Region

The Secure Silicon Region provides an extra Flash memory region that may be programmed once and permanently protected from further programming or erase.

 Reads can be performed in the Asynchronous or Synchronous mode.

 Sector address supplied during the Secure Silicon Entry command selects the Flash memory array sector that is overlaid by the Secure Silicon Region address map.

 Continuous burst mode reads within Secure Silicon Region wrap from address FFh back to address 00h.

 Reads outside of the overlaid sector return memory array data.

 The Secure Silicon Region is not accessible when the device is executing an Embedded Algorithm (nor during Program Suspend, Erase Suspend, or while another AOS is active).

 See the Secure Silicon address map for address range of this area.

8.5.1

8.5.2

Factory Secure Silicon Region

The Factory Secure Silicon Region is always protected when shipped from the factory and has the Factory

SSR Lock Bit (bit 1) permanently set to a zero. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field.

Customer Secure Silicon Region

The Customer Secure Silicon Region is typically shipped unprotected, Customer SSR Lock Bit (bit 0) set to a one, allowing customers to utilize that sector in any manner they choose.

 The Customer Secure Silicon Region can be read any number of times, but each word CL can be programmed only once and the region locked only once. The Customer Secure Silicon Region lock must be used with caution as once locked, there is no procedure available for unlocking the Customer Secure

Silicon Region area and none of the bits in the Customer Secure Silicon Region memory space can be modified in any way. The Customer Indicator Bit is located in the SSR Lock at bit location 0.

 Once the Customer Secure Silicon Region area is protected, any further attempts to program in the area will fail with status indicating the area being programmed is protected.

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42

8.5.3

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Secure Silicon Region Entry and Exit Command Sequences

The system can access the Secure Silicon Region region by issuing the one-cycle Enter Secure Silicon

Region Entry command sequence from the IDLE State. The device continues to have access to the Secure

Silicon Region region until the system issues the Exit Secure Silicon Region command sequence, performs a

Hardware RESET, or until power is removed from the device.

See Command Definition Table [Secure Silicon Region Command Table, Appendix

Table 11.1 on page 56 for address and data requirements for both command sequences.

The Secure Silicon Region Entry Command allows the following commands to be executed

 Read customer and factory Secure Silicon Regions

 Program the customer Secure Silicon Region

 Read data out of all sectors not re-mapped to Secure Silicon Region

 Secure Silicon Region Exit

Software Functions and Sample Code

The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.spansion.com

) for general information on Spansion Flash memory software development guidelines.

Cycle

Entry Cycle

Table 8.1 Secured Silicon Region Entry

Operation

Write

Byte Address

Sector Address + AAAh

Word Address

Sector Address + 555h

Data

0088h

/* Example: SecSi Sector Entry Command */

*( (UINT16 *)sector_address + 0x555 ) = 0x0088; /* write Secsi Sector Entry Cmd */

Cycle

Program Setup

Write Word Count

Load Buffer Word N

Write Buffer to Flash

Table 8.2 Secured Silicon Region Program

Operation

Write

Byte Address

Sector Address + AAAh

Word Address

Sector Address + 555h

Write Sector Address + 555h Sector Address + 2AA

Number of words (N) loaded into the write buffer can be from 1 to 32 words.

Write

Write

Program Address, Word N

Sector Address + AAAh Sector Address + 555h

Data

0025h

Word Count (N–1)h

Word N

0029h

/* Once in the SecSi Sector mode, you program */

/* words using the programming algorithm. */

Cycle

Exit Cycle

Table 8.3 Secured Silicon Region Exit

Operation

Write

Byte Address

Base Address

Word Address

Base Address

Data

00F0h

/* Example: SecSi Sector Exit Command */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* write SecSi Sector Exit cycle */

S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

9.

Power Conservation Modes

9.1

Standby Mode

In the standby mode current consumption is greatly reduced, and the outputs (A/DQ15-A/DQ0) are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at V

CC

± 0.2 V. The device requires standard access time (t

CE or t

IA

) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I

CC3

in DC Characteristics on page 45

represents the standby current specification

9.2

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode and while the device is not in a suspended state. The device automatically enables this mode when addresses remain stable for t

ACC

+ 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings (t

ACC

or t

PACC

) provide new data when addresses are changed.

While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. I

CC6

in

DC Characteristics on page 45

represents the automatic sleep mode current specification.

9.3

Output Disable (OE#)

When the OE# input is at V

IH

, output (A/DQ15-A/DQ0) from the device is disabled and placed in the high impedance state. RDY is not controlled by OE#.

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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Flash Family 43

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

10. Electrical Specifications

10.1

Absolute Maximum Ratings

Storage Temperature Plastic Packages

Ambient Temperature with Power Applied

Voltage with Respect to Ground: All Inputs and I/Os except as noted below

(Note 1)

V

CC

(Note 1)

V

IO

V

PP

(Note 2)

Output Short Circuit Current

(Note 3)

–65°C to +150°C

–65°C to +125°C

–0.5 V to VIO + 0.5 V

–0.5 V to +2.5 V

–0.5 V to +2.5 V

–0.5 V to +9.5 V

100 mA

Notes:

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot V

SS

to –2.0 V for periods of up

to 20 ns. See Figure 10.1

. Maximum DC voltage on input or I/Os is V

CC

+ 0.5 V. During voltage transitions outputs may overshoot to V

CC

+ 2.0 V for periods up to 20 ns. See Figure 10.2

.

2. Minimum DC input voltage on pin V

PP

is -0.5V. During voltage transitions, V

PP

may overshoot V

SS

to –2.0 V for periods of up to 20 ns.

See

Figure 10.1

. Maximum DC voltage on pin V

PP

is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 10.1 Maximum Negative Overshoot Waveform

20 ns 20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 10.2 Maximum Positive Overshoot Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

1.0 V

20 ns

20 ns

10.2

Operating Ranges

Wireless (W) Devices

Ambient Temperature (T

A

)

Industrial (I) Devices

Ambient Temperature (T

A

)

(Refer to Publication Number S29VS_XS-R_SP for Industrial

Temperature specific differences)

Supply Voltages

–25°C to +85°C

–40°C to +85°C

V

CC

Supply Voltages +1.70 V to +1.95 V

+1.70 V to +1.95 V

V

IO

Supply Voltages

V

CC(min)

 V

IO(min)

- 200mV

Note:

Operating ranges define those limits between which the functionality of the device is guaranteed.

44 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

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10.3

DC Characteristics

10.3.1

CMOS Compatible

Parameter

I

I

I

I

I

LI

I

LO

CCB

IO1

IO2

CC1

V

V

V

V

CC

IO

IO

CC

Description

Input Load Current

Output Leakage Current

Active burst Read Current

Non-active Output

Standby

Active Asynchronous

Read Current

Test Conditions (Notes

1 & 2

)

V

IN

= V

SS

to V

CC

, V

CC

= V

CC max

V

OUT

= V

SS

to V

CC

, V

CC

= V

CC max

83 MHz

CE# = V

IL

, OE# = V

IH

,

WE# = V

IH

, burst length = 8

104 MHz

108 MHz

83 MHz

CE# = V

IL

, OE# = V

IH

,

WE# = V

IH

, burst length = 16

104 MHz

108 MHz

83 MHz

CE# = V

IL

, OE# = V

IH

,

WE# = V

IH

, burst length = Continuous

104 MHz

108 MHz

OE# = V

IH

, RDY = Tri-State

CE# = RESET# = V

CC

± 0.2V

CE# = V

IL

, OE# = V

IH

,

WE# = V

IH

10 MHz

5 MHz

1 MHz

Min Typ

35

39

28

32

28

32

20

2

40

20

10

Max

±1

±1

38

44

30

36

30

36

30

3

60

40

20

I

I

I

I

CC2

CC3

CC4

CC5

V

CC

Active Write Current

(3) (7)

V

V

V

CC

CC

CC

Standby Current

Reset Current

Active Current

(Read While Write)

(Continuous Burst) (6)

CE# = V

V

PP

IL

, OE# = V

IH

,

= V

IH

CE# = RESET# = V

CC

± 0.2 V

V

PP

V

CC

V

PP

V

CC

RESET# = V

IL,

CLK = V

IL

CE# = V

IL

, OE# = V

IH

, V

PP

= V

IH

83 MHz

104 MHz

108 MHz

1

30

1

30

150

65

71

5

40

5

40

250

70

76

I

I

CC6

PP

V

IL

V

IH

V

OL

V

OH

V

CC

Sleep Current

Input High Voltage

Output Low Voltage

(4)

Accelerated Program Current

(5)

Input Low Voltage

CE# = V

IL

, OE# = V

IH

CE# = V

V

PP

IL

, OE# = V

= 9.5 V

IH,

V

IO

= 1.8 V

V

IO

= 1.8 V

I

OL

= 100 µA, V

CC

= V

CC min

= V

IO

I

OH

= –100 µA, V

CC

= V

CC min

= V

IO

V

PP

V

CC

V

–0.2

IO

– 0.4

20

7

25

V

IO

40

10

28

0.4

+ 0.4

0.1

V

HH

Output High Voltage

Voltage for Accelerated

Program

Low V

CC

Lock-out Voltage

V

IO

– 0.1

8.5

9.5

V

LKO

1.0

1.1

Notes:

1. Maximum I

CC

specifications are tested with V

CC

= V

CC max.

2. V

CC

= V

IO

3. I

CC

active while Embedded Erase or Embedded Program is in progress.

4. Device enters automatic sleep mode when addresses are stable for t

ACC

+ 20 ns. Typical sleep mode current is equal to I

CC3

.

5. Total current during accelerated programming is the sum of V

PP

and V

CC

currents.

6. I

CC5

applies while reading the status register during program and erase operations.

7. Effect of status register polling during write not included.

Unit

µA

µA mA mA mA mA mA mA mA

µA mA mA

V

µA mA

µA

µA

µA

µA

µA mA mA mA

V

V

V

V

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 45

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

10.4

Capacitance

Symbol

C

C

IN

OUT

Description

Input Capacitance

(Address, CE#, OE#, WE#,

AVD#, WE#, CLK, RESET#)

Output Capacitance

(DQ, RDY)

Notes:

1. Test conditions T

A

= 25°C, f = 1.0 MHz

2. Sampled, not 100% tested.

V

Test Condition

Single Die

V

IN

= 0

Dual Die

OUT

= 0

Single Die

Dual Die

M in .

2.0

4.0

2.0

4.0

Typ.

4.5

9.0

4.5

9.0

10.5

AC Test Conditions

Operating Range

Input level

Input comparison level

Output data comparison level

Load capacitance (C

L

)

Transition time (t

T

) (input rise and fall times)

Transition time (t

T

) (CLK input rise and fall times)

83 MHz

104 MHz

108 MHz

83 MHz

104 MHz

108 MHz

V

IO

Figure 10.3 Input Pulse and Test Point

V

IO

/2

Input and Output

Test Point

V

IO

/2

0V

Device

Under

Test

Figure 10.4 Output Load

*C

L

= 30 pF including scope

and Jig capacitance

Max.

6.0

12.0

6.0

12.0

0.0 to V

IO

V

IO

/2

V

IO

/2

30 pF

2.50 ns

1.85 ns

1.85 ns

2.50 ns

1.85 ns

1.85 ns

Unit

pF pF pF pF

10.6

Key to Switching Waveforms

Waveform Inputs Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High-Z)

46 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

10.7

V

CC

Power Up

Table 10.1 V

CC

Power-up

Parameter Description

t

VCS t

VIOS t

RH

V

CC

Setup Time

V

IO

Setup Time

Time between RESET# (high) and CE# (low)

Notes:

1. RESET# must be high after V

CC

and V

IO are higher than V

CC

minimum.

2. V

CC

V

IO

– 200 mV during power-up.

3. V

CC

& V

IO

ramp rate could be non-linear

4. V

CC

and V

IO

are recommended to be ramped up simultaneously.

Test Setup

Min

Min

Min

.

V

CC

V

IO

Figure 10.5 V

CC

Power-up Diagram t

VCS

V

CC min t

VIOS

V

IO min

V

IH

RESET# t

RH

CE#

Speed

300

300

200

Unit

µs

µs ns

10.8

CLK Characterization

Parameter Description

Max

108 MHz

108 t f

CLK t

CLK

CL

/t

CH

CLK Frequency

CLK Period

CLK Low/High Time

Min

Min

Min

DC

(1)

9.26

0.40 t

CLK

Note:

1. DC for operations other than continuous and 16 word (32 byte) synchronous burst read. See

AC Characteristics Table.

Figure 10.6 CLK Characterization tCLK tCH tCL

Unit

MHz ns ns

CLK

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 47

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

10.9

AC Characteristics

10.9.1

AC Characteristics–Synchronous Burst Read

Parameter (Notes)

Clock Frequency

Symbol

CLK Min

83 MHz 104 MHz 108 MHz

DC (0) for operations other than continuous and

32 byte synchronous burst.

120 in 32 Byte burst

1000 in continuous burst

12 9.6

9.26

Clock Cycle

CLK Rise Time

CLK Fall Time

CLK High or Low Time

Internal Access Time

Burst Access Time Valid Clock to Output

Delay t

CLK t

CLKR t

CLKF

Min

Max t

CLKH/L

Min t

IA

Max t

BACC

Max

2.5

5

9

AVD# Setup Time to CLK

AVD# Hold Time from CLK

Address Setup Time to CLK

Address Hold Time from CLK

Data Hold Time from Next Clock Cycle

Output Enable to Data

CE# Disable to Output High-Z

OE# Disable to Output High-Z

(2)

(2)

t

AVDS t

AVDH t

ACS t

ACH t

BDH t

OE t

CEZ t

OEZ

Min

Min

Min

Min

Min

Max

Max

Max

3

CE# Setup Time to CLK

CLK to RDY valid

CE# low to RDY valid

AVD# Pulse Width t

CES

Min t

RACC

Max t

CR

Max t

AVDP

Min

9

Notes:

1. Not 100% tested.

2. If OE# is disabled before CE# is disabled, the output goes to High-Z by t

OEZ

.

If CE# is disabled before OE# is disabled, the output goes to High-Z by t

CEZ

.

If CE# and OE# are disabled at the same time, the output goes to High-Z by t

OEZ

.

3. AVD can not be low for 2 subsequent CLK cycles.

75

4

5

4

3

4

1.92

4

7.6

15

2

10

10

7.6

10

6

1.852

3.86

72.34

6.75

3.38

2.89

2.89

4.82

2

3.38

6.75

CE#

CLK t

AVDS

AVD#

Amax–

A16 t

ACS

A/DQ15–

A/DQ0

OE#

RDY

Hi-Z t

CR

1

AC t

ACH

AC

Figure 10.7 Synchronous Read Mode - ADM Interface t

CES

7 cycles for initial access is shown as an illustration.

2 3 4 5 t

AVDP t

AVDH t

OE t

IA

6 7 t

RACC

DC

DD t

BDH t

BACC

DE DB

Unit

KHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

48 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

10.9.2

AC Characteristics–Asynchronous Read

Parameter Symbol

Access Time from CE# Low

Asynchronous Access Time from address valid

Read Cycle Time

AVD# Low Time

Address Setup to rising edge of AVD#

Address Hold from rising edge of AVD#

Output Enable to Output Valid

CE# Setup to AVD# falling edge

CE# Disable to Output & RDY High-Z

OE# Disable to Output High-Z

AVD# High to OE# Low

CE# low to RDY valid

WE# Disable to AVD# Enable

WE# Disable to OE# Enable

(1)

(1)

t

CE t

ACC t

RC t

AVDP t

AAVDS t

AAVDH t

OE t

CAS t

CEZ t

OEZ t

AVDO t

CR t

WEA t

OEH

Notes:

1. Not 100% tested.

2. If OE# is disabled before CE# is disabled, the output goes to High-Z by t

OEZ

.

If CE# is disabled before OE# is disabled, the output goes to High-Z by t

CEZ

.

If CE# and OE# are disabled at the same time, the output goes to High-Z by t

OEZ

.

Figure 10.8 Asynchronous Mode Read - ADM Interface

4

9.6

0

4

Min

80

6

4

3.5

CE#

10

10

15

10

Max

80

80

OE# t

OE t

OEH

WE# t

CE t

OEZ

A/DQ15 –

A/DQ0

RA t

ACC

Valid RD

Amax

A16

RA t

AAVDH

AVD# t

CAS t

AVDP t

CR t

AAVDS t

CEZ

RDY

Hi-Z

Notes:

1. AVD# Transition occurs after CE# is driven to Low and Valid Address Transition occurs before AVD# is driven to Low.

2. VA = Valid Read Address, RD = Read Data.

Unit

ns

Hi-Z

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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50

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

10.9.3

AC Characteristics–Erase/Program Timing

Parameter

WE# Cycle Time (1)

AVD# low pulse width

Address Setup to rising edge of AVD#

Address Hold from rising edge of AVD#

Read Recovery Time Before Write

Data Setup to rising edge of WE#

Data Hold from rising edge of WE#

CE# Setup to falling edge of WE#

CE# Hold from rising edge of WE#

WE# Pulse Width

WE# Pulse Width High

Latency Between Read and Write Operations

AVD# Disable to WE# Disable

WE# Disable to AVD# Enable

CE# low to RDY valid

CE# Disable to Output High-Z

OE# Disable to WE# Enable

Erase Suspend Latency

Program Suspend Latency

Erase Resume to Erase Suspend

Program Resume to Program Suspend

Note:

1. Sampled, not 100% tested.

Symbol

t

WC t

AVDP t

DH t

CS

60

6 t

AAVDS t

AAVDH

3.5

t

GHWL t

DS

4

0

20 –

0

4

– t

CH t

WP

0 –

25 – t

WPH

20 – t

SRW

0 – t

VLWH

23.5

– t

WEA

9.6 –

– – t

CR t

CEZ t

WEH t

ESL

4 –

– t

PSL t

ERS t

PRS

30

30

Figure 10.9 Asynchronous Program Operation Timings - ADM Interface

Read Status Data

V

IH

CLK

V

IL

Program Command Sequence (last two cycles) t

AVDP

AVD#

Amax–

A16 t

AAVDS

PA tAAVDH t

VLWH

SA(555h)

BA(555h) BA

A/DQ15–

A/DQ0

PA t

CAS

PD

SA(555h)

29h t

DS t

DH

BA(555h)

70h

BA

CE#

Status

10

10

30

30

– ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

µs

µs

µs

µs t

CH

OE#

WE# t

WP t

CS t

WPH t

WC t

VCS

+ t

RH

V

CC

S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

10.9.4

Hardware Reset (Reset#)

Table 10.2 Warm-Reset

JEDEC

Parameter

Std

t

RP t

RH t

RPH

Description

RESET# Pulse

Width

Reset High Time

Before Read

RESET# Low to CE#

Low

Min

Min

Min

All Speed Options

50

200

10

Unit

ns ns us

CE#, OE#

RESET#

Figure 10.10 Reset Timings t

RH t

RP t

RPH

Address

(hex)

CLK

7C

Figure 10.11 Latency with Boundary Crossing

Address boundary occurs every 128 words, beginning at address

00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.

7D 7E 7F 7F 80 81 82 83

AVD#

(stays high)

RDY

(Note 1)

RDY

(Note 2)

Data

D124 D125 t

RACC

D126 t

RACC latency latency t

RACC t

RACC

D127 D128 D129 D130

OE#,

CE#

(stays low)

Notes:

1. RDY active with data (CR.8 = 1 in the Configuration Register).

2. RDY active one clock cycle before data (CR.8 = 0 in the Configuration Register).

3. Figure shows the device not crossing a bank in the process of performing an erase or program.

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 51

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 10.12 Latency with Boundary Crossing into Bank Performing Embedded Operation

Address boundary occurs every 128 words, beginning at address

00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.

Address

(hex)

CLK

7C 7D 7E 7F 7F 80 81 82 83

AVD#

(stays high)

RDY

(Note 1)

RDY

(Note 2)

Data

D124 D125 t

RACC

D126 t

RACC

D127

00h

00h

00h

OE#,

CE#

(stays low)

Notes:

1. RDY active with data (CR.8 = 1 in the Configuration Register).

2. RDY active one clock cycle before data (CR.8 = 0 in the Configuration Register).

3. Figure shows the device crossing a bank in the process of performing an erase or program.

00h

52 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

10.9.5

Wait State Configuration Register Setup

Figure 10.13 Example of Programmable Wait States

Data

AVD#

OE#

1

2 3

Total number of clock cycles following addresses being latched

4 5 6 7

D0 D1

Rising edge of next clock cycle following last wait state triggers next burst data

CLK

0

1 2

3

4

5 6

Total number of clock edges following addresses being latched

7

Configuration

Register

CR.14

CR.13

CR.12

CR.11

0000 =

0001 =

0010 =

0011 =

0100 =

0101 =

0110 =

0111 =

1000 =

.

.

.

1011 =

1100 =

1111 = initial data is valid on the

Reserved

Programmable Wait States

Reserved

3rd

4th

5th

6th

7th rising CLK edge after addresses are latched

8th

9th

10th

.

.

.

13th

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 53

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 10.14 Back-to-Back Read/Write Cycle Timings - ADM Interface

Last Cycle in

Program or

Sector Erase

Command Sequence t

WC

Read status (at least two cycles) in same bank and/or array data from other bank t

RC t

RC

Begin another write or program command sequence t

WC

CE#

OE# t

OE t

OEH t

GHWL

WE#

Data t

WPH t

WP t

DS

WD t

DH t

ACC

RD t

OEZ

RD 25h

Addresses

WA t

AAVDS t

SR/W

RA RA SA(555h)

AVD# t

AAVDH

Note:

Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the

program or erase operation in the busy bank. The system should read status twice to ensure valid information.

54 S29VS/XS-R MirrorBit

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D a t a S h e e t

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10.9.6

Erase and Programming Performance

Sector Erase Time

(Note 6)

Chip Erase Time

Parameter

(Note 6) ,

128 Kbyte

32 Kbyte

128 Kbyte

32 Kbyte

(Note 7)

V

V

V

V

V

V

CC

CC

PP

PP

CC

PP

Typ (Note 1)

0.8/1.3

0.35/0.6

0.8/1.3

0.35/0.6

78/126 (128 Mbit)

155/251 (256 Mbit)

78/126 (128 Mbit)

155/251 (256 Mbit)

Max (Note 2)

3.5/5.5

2.0/3.5

3.5/5.5

2.0/3.5

200/325 (128 Mbit)

400/650 (256 Mbit)

154/250 (128 Mbit)

308/500 (256 Mbit)

Unit

s

Comments

(Note 3)

Single Word Program Time (using

Program Buffer)

V

CC

170 800

Effective Word Programming Time using

Program Write Buffer

Total 32-Word Buffer Programming Time

Chip Programming Time

(using 32 word buffer)

V

V

V

V

V

V

CC

PP

CC

PP

CC

PP

14.1

9

450

288

118 (128 Mbit)

236 (256 Mbit)

76 (128 Mbit)

151 (256 Mbit)

94

48

3000

1540

157 (128 Mbit)

315 (256 Mbit)

80 (128 Mbit)

160 (256 Mbit)

30

µs s

Excludes system level overhead

(Note 4)

Excludes system level overhead

(Note 4)

Erase Suspend/Erase Resume (t

ESL

)

Program Suspend/Program Resume

(t

PSL

)

Blank Check

30

µs

µs

1 ms

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V

CC

, 10,000 cycles. Additionally, programming typically assumes a checkerboard pattern.

2. Under worst case conditions of –25°C, V

CC

= 1.70 V, 100,000 cycles.

3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

4. System-level overhead is the time required to execute the bus-cycle sequence for the program command. See

Table 11.1 on page 56 for

further information on command definitions.

5. The device has a minimum erase and program cycle endurance of 10,000 cycles.

6. The first value excludes pre-programming time, while the second value is inclusive of pre-programming time for the FFFFh pattern, with status polling rate as 400 ns.

7. The erase time is calculated from the time of issuing erase command to the completion of erase operation (indicated by status register)

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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Flash Family 55

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

11. Appendix

This section contains information relating to software control or interfacing with the Flash device.

11.1

Command Definitions

All values are in hexadecimal. The S29VS-R family of devices are 16-bit word address oriented. Most system address buses, regardless of data bus size, are byte oriented. It is common practice for system designers to shift the address busses. That is, Flash Address A0 is connected to system Address A1, etc. To accommodate the system designers, addresses are listed in both word address and byte address where applicable. The flash address (word) is listed above the system address (byte).

Table 11.1 Command Definitions (Sheet 1 of 2)

Command Sequence Addr

Read RA

Reset 1 X

Write Buffer Load

(8)

3-34

(SA) 555

(SA) AAA

First

Buffer to Flash

Chip Erase

Sector Erase

Read Status Register

Clear Status Register

Program Suspend

Program Resume

Erase Suspend

Erase Resume

Blank Check

(6)

(6)

(13)

Sector Lock/Unlock

Sector Lock Range

(5)

(5)

1

2

2

2

1

1

1

1

1

1

3

4

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

XXX

(SA) 000

XXX

(SA) 000

(SA) 555

(SA) AAA

555

AAA

555

AAA

Data

RD

F0

25

29

80

80

70

71

33

51

50

B0

30

Addr

(SA) 2AA

(SA) 554

(SA) 2AA

(SA) 554

(SA) 2AA

(SA) 554

(SA)

Second

Bus Cycles (Notes

1 – 4 )

Data

WC

10

30

RR

60

2AA

554

60

60

2AA

554

60

ID/CFI Command Definitions

Addr

(SA) PA

(11)

SLA

SLA

Third Fourth

Data Addr Data

PD

60

61

PA (12)

SLA

PD

61

ID/CFI Entry

ID/CFI Read

ID/CFI Exit

(7) (10)

1

1

1

(SA) X55

(SA) XAA

(SA) RA

XXX

90 or 98 data

FO

Configuration Command Definitions

Configuration Register

Entry (7) (10)

Write Buffer Load

Buffer to Flash

(Configuration Register)

Configuration Register

Read

Configuration Register Exit

1

3

1

1

1

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) X00

XXX

D0

25

29

RR

FO

(SA) 2AA

(SA) 554

0 (SA) X00 PD

56 S29VS/XS-R MirrorBit

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D a t a S h e e t

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Command Sequence

SSR Lock Entry

(7) (10)

Write Buffer Load (8)

Buffer to Flash

SSR Lock Read

SSR Lock Exit

Secure Silicon Region Entry

(7) (10)

1

Write Buffer Load (8)

Buffer to Flash

1

3

1

1

1

3-34

1

Table 11.1 Command Definitions (Sheet 2 of 2)

Addr

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) XXX

XXX

40

25

29

(SA) 2AA

(SA) 554

0

RR

F0

Secure Silicon Region Command Definitions

(SA) 00

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) 555

(SA) AAA

(SA) RA

XXX

First

Data Addr

Second

Bus Cycles (Notes 1 – 4 )

Third Fourth

Data

SSR Lock Command Definitions

Addr Data Addr Data

88

25

29

RD

F0

(SA) 2AA

(SA) 554

WC (SA) PA

PD

PD (SA) PA PD

Secure Silicon Region Read 1

Secure Silicon Region Exit 1

Legend:

X = Don’t care

RA = Address of the location to be read.

RD = Read Data from location RA during read operation.

RR = Read Register value

PA = Address of the memory location to be programmed.

PD = Data to be programmed at location PA.

BA = Address bits sufficient to select a bank

SA = Address bits sufficient to select a sector

SLA = Sector Lock Address

WBL = Write Buffer Location. Address must be within the same write buffer page as PA.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See

Section 7., Device Operations on page 21 for description of bus operations.

2. Except for the following, all bus cycles are write cycle: read cycle during Read, ID/CFI Read (Manufacturing ID, Device ID, Indicator Bits), Configuration Register read, Secure Silicon Region Read, SSR Lock Read, and 2nd cycle of Status Register Read.

3. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, and WD.

4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data.

5. The Program Resume command is valid only during the Program Suspend mode/state.

6. The Erase Resume command is valid only during the Erase Suspend mode/state.

7. Command is valid when all banks are ready to read array data.

8. The total number of cycles in the command sequence is determined by the number of words written to the write buffer.

9. V

PP

must be at V

HH

during the entire operation of this command.

10. Entry commands are needed to enter a specific mode to enable instructions only available within that mode.

11. Must be the lowest word address of the words being programmed within the 32 word write buffer page. This is not necessarily the lowest address of the page.

Data words are loaded into the write page buffer in sequential order from lowest to highest address.

12. Subsequent addresses must fall within the same Sector and Page as the initial starting address.

13. Blank Check is only functional in Asynchronous Read mode (Configuration Register - CR [15] = 1).

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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D a t a S h e e t

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11.2

Device ID and Common Flash Memory Interface Address Map

The Device ID fields occupy the first 32 bytes of address space followed by the Common Flash Interface data structure. The Common Flash Interface (CFI) specification defines a standardized data structure containing device specific parameter, structure, and feature set information, which allows vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent,

JEDEC ID-independent, and forward- and back-ward-compatible for the specified flash device families. Flash driver software can be standardized for long-term compatibility.

This device enters the ID/CFI mode when the system writes the ID/CFI Query command, 90h or 98h, to address (SA)55h any time all banks are in read mode (the CU is in Idle State). The system can then read ID and CFI information at the addresses, within the selected sector, given in the following tables. To terminate reading ID/CFI, the system must write the reset command.

Word Offset Address

(SA) + 00h

(SA) + 01h

(SA) + 02h

(SA) + 03h

(SA) + 04h

(SA) + 05h

(SA) + 06h

(SA) + 07h

(SA) + 08h

(SA) + 09h

(SA) + 0Ah

(SA) + 0Bh

(SA) + 0Ch

(SA) + 0Dh

(SA) + 0Eh

(SA) + 0Fh

Byte Offset Address

(SA) + 00h

(SA) + 02h

(SA) + 04h

(SA) + 06h

(SA) + 08h

(SA) + 0Ah

(SA) + 0Ch

(SA) + 0Eh

(SA) + 10h

(SA) + 12h

(SA) + 14h

(SA) + 16h

(SA) + 18h

(SA) + 1Ah

(SA) + 1Ch

(SA) + 1Eh

Table 11.2 ID/CFI Data (Sheet 1 of 5)

007Eh

(Top/Bottom)

DATA

VS256R/XS256R VS128R/XS128R

0001h

007Eh

(Top/Bottom)

Reserved

Reserved

Reserved

Reserved

0010h

DQ15 - DQ8 = Reserved

DQ7 - Factory Lock Bit: 1 = Locked;

0 = Not Locked

DQ6 - Customer Lock Bit: 1 = Locked;

0 = Not locked

DQ5 - DQ0 = Reserved

Reserved

Reserved

Reserved

Reserved

Description

Spansion Manufacturer ID

Device ID, Word 1 Extended ID address code. Indicates an extended two byte device ID is located at byte address

1Ch and 1Eh.

Reserved

Reserved

Reserved

Reserved

ID Version

Indicator Bits

Reserved

Reserved

Reserved

Reserved

05h

Bit 0 - Status Register Support

1 = Status Register Supported

0 = Status register not Supported

Bit 1 - DQ Polling Support

1 = DQ bits polling supported

0 = DQ bits polling not supported

Bit 3-2 - Command Set Support

11 = Reserved

10 = Reserved

01 = Reduced Command Set

00 = Old Command Set

Bit 4- F - Reserved

Lower Software Bits

Reserved

Upper Software Bits

Reserved

0064h/Top;

0066h/Bottom

0001h

(Top/Bottom)

0063h/Top;

0065h/Bottom

0001h

(Top/Bottom)

High Order Device ID, Word 2

Low Order Device ID, Word 3

58 S29VS/XS-R MirrorBit

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D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

(SA) + 1Dh

(SA) + 1Eh

(SA) + 1Fh

(SA) + 20h

(SA) + 21h

(SA) + 22h

(SA) + 23h

(SA) + 24h

(SA) + 25h

(SA) + 26h

Word Offset Address

(SA) + 10h

(SA) + 11h

(SA) + 12h

(SA) + 13h

(SA) + 14h

(SA) + 15h

(SA) + 16h

(SA) + 17h

(SA) + 18h

(SA) + 19h

(SA) + 1Ah

(SA) + 1Bh

(SA) + 1Ch

Byte Offset Address

(SA) + 20h

(SA) + 22h

(SA) + 24h

(SA) + 26h

(SA) + 28h

(SA) + 2Ah

(SA) + 2Ch

(SA) + 2Eh

(SA) + 30h

(SA) + 32h

(SA) + 34h

(SA) + 36h

(SA) + 38h

(SA) + 3Ah

(SA) + 3Ch

(SA) + 3Eh

(SA) + 40h

(SA) + 42h

(SA) + 44h

(SA) + 46h

(SA) + 48h

(SA) + 4Ah

(SA) + 4Ch

Table 11.2 ID/CFI Data (Sheet 2 of 5)

DATA

VS256R/XS256R VS128R/XS128R

CFI Query Identification String

0051h

0052h

0059h

0002h

0000h

0040h

0000h

0000h

0000h

0000h

0000h

System Interface String

Description

Query Unique ASCII string “QRY”

Primary Algorithm Command Set (Spansion = 0002h)

Address for Primary Extended Table

Alternate Algorithm Command Set (00h = none exists)

Address for Secondary Algorithm extended Query Table

(00h = none exists)

0012h

0017h

0019h

0085h

0095h

0008h

0009h

000Ah

0003h

0003h

0003h

0003h

0011h

V

CC

Logic Supply Minimum Program/Erase or Write voltage

D7-D4: Volt

D3-D0: 100 millivolt

V

CC

Logic Supply Maximum Program/Erase or Write voltage

D7-D4: Volt

D3-D0: 100 millivolt

V

PP

[Programming] Supply Minimum Program/Erase voltage (00h = no V

PP

pin present)

V

PP

[Programming] Supply Maximum Program/Erase voltage (00h = no V

PP

pin present)

Typical Word Programming Time per single word 2

N

(e.g. < or = 32 s)

s

Typical Program Time for programming the complete buffer 2

N

s (e.g. < or = 256 s) (00h = not supported)

Typical Time for Sector Erase 2

N ms

Typical Time for full chip erase 2

N

(00h = not supported)

s

Max. Program Time per single word

[2

N

times typical value]

Max. Program Time using buffer [2

N

times typical value]

Max. Time for sector erase [2

N

times typical value]

Max. Time for full chip erase [2

N

times typical value]

(00h = not supported)

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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Flash Family 59

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Word Offset Address

(SA) + 27h

(SA) + 28h

(SA) + 29h

(SA) + 2Ah

(SA) + 2Bh

(SA) + 2Ch

(SA) + 2Dh

(SA) + 2Eh

(SA) + 2Fh

(SA) + 30h

(SA) + 31h

(SA) + 32h

(SA) + 33h

(SA) + 34h

Byte Offset Address

(SA) + 4Eh

(SA) + 50h

(SA) + 52h

(SA) + 54h

(SA) + 56h

(SA) + 58h

(SA) + 5Ah

(SA) + 5Ch

(SA) + 5Eh

(SA) + 60h

(SA) + 62h

(SA) + 64h

(SA) + 66h

(SA) + 68h

Table 11.2 ID/CFI Data (Sheet 3 of 5)

DATA

VS256R/XS256R VS128R/XS128R

Device Geometry Definition

0019h 0018h

00FEh

(Top Boot)

0003h

(Bottom Boot)

0001h

0000h

0006h

0000h

0002h

007Eh

(Top Boot)

0003h

(Bottom Boot)

Description

Device Size = 2

N

byte

Flash Device Interface

0h = x8

1h = x16

2h = x8/x16

3h = x32 [lower byte]

[upper byte] (00h = not supported)

Max. number of bytes in multi-byte buffer write = 2

N

[lower byte]

[upper byte] (00h = not supported)

Number of Erase Block Regions within device

(Number of regions within the device containing one or more contiguous Erase Blocks of the same size)

Erase Block Region 1 information

[lower byte] - Number of Erase sectors of identical size within the Erase Block Region.

00h = 1 sector;

01h = 2 sectors

02h = 3 sectors

03h = 4 sectors

[upper byte] 0000h

0000h (Top Boot)

0080h (Bottom Boot)

0002h (Top Boot)

0000h (Bottom Boot)

0003h

(Top Boot)

0003h

(Top Boot)

00FEh

(Bottom Boot)

007Eh

(Bottom Boot)

0000h

0080h (Top Boot)

0000h (Bottom Boot)

0000h (Top Boot)

0002h (Bottom Boot)

[lower byte] - Sector Size in bytes divided by 256

(n [bytes]h = sector size / 256)

[upper byte]

Erase block Region 2 Information

[upper byte]

[lower byte] - Sector Size in bytes divided by 256

(n [bytes]h = sector size / 256)

[upper byte]

60 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Word Offset Address

(SA) + 40h

(SA) + 41h

(SA) + 42h

(SA) + 43h

(SA) + 44h

(SA) + 45h

(SA) + 46h

(SA) + 47h

(SA) + 48h

(SA) + 49h

(SA) + 4Ah

(SA) + 4Bh

(SA) + 4Ch

(SA) + 4Dh

(SA) + 4Eh

(SA) + 4Fh

(SA) + 50h

Table 11.2 ID/CFI Data (Sheet 4 of 5)

Byte Offset Address

(SA) + 80h

(SA) + 82h

(SA) + 84h

(SA) + 86h

(SA) + 88h

(SA) + 8Ah

(SA) + 8Ch

(SA) + 8Eh

(SA) + 90h

(SA) + 92h

(SA) + 94h

(SA) + 96h

(SA) + 98h

(SA) + 9Ah

(SA) + 9Ch

(SA) + 9Eh

(SA) + A0h

DATA

VS256R/XS256R VS128R/XS128R Description

Primary Algorithm-Specific Extended Query

0050h

0052h

0049h

Query Unique ASCII string “PRI”

0031h

0034h

0020h

0002h

Major CFI version number, ASCII

Minor CFI version number, ASCII

Address Sensitive Unlock (Bits 1-0):

00b = Required

01b = Not required

Process Technology (Bits 5-2)

0011b = 130 nm Floating-Gate Technology

0100b = 110 nm MirrorBit Technology

0101b = 90 nm Floating-Gate Technology

0110b = 90 nm MirrorBit Technology

1000b = 65 nm MirrorBit Technology

Erase Suspend

0= Not supported

1 = To Read Only

2 = To Read & Write

00E0h

0001h

0000h

0009h

0001h

0000h

0085h

0095h

03h (Top Boot)

02h (Bottom Boot)

0001h

0070h

Sector Protection per Group

0 = not Supported

X = number of sectors in per group

Sector Temporary Unprotect

00h = Not Supported

01h = Supported

Sector Protect/Unprotect scheme

08h = Advanced Sector Protection

09h = Single-Sector Lock + Sector Lock Range

Simultaneous Operations

Number of Sectors in all banks except Boot Bank

Burst Mode Type

00h = Not Supported

01h = Supported

Page Mode Type

00h = Not Supported

01h = 4-Word Page

02h = 8-Word Page

04h = 16-Word Page

V

PP

(Acceleration) Supply Minimum

00h = Not Supported

D7-D4: Volt

D3-D0: 100 millivolt

V

PP

(Acceleration) Supply Maximum

00h = Not Supported

D7-D4: Volt

D3-D0: 100 millivolt

Top/Bottom Sector Flag

00h = Uniform

01h = Dual Boot

02h = Bottom boot

03h = Top boot

Program Suspend

00h = Not Supported

01h= Supported

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Word Offset Address

(SA) + 51h

(SA) + 52h

(SA) + 53h

(SA) + 54h

(SA) + 55h

(SA) + 56h

(SA) + 57h

(SA) + 58h

(SA) + 59h

(SA) + 5Ah

(SA) + 5Bh

(SA) + 5Ch

(SA) + 5Dh

(SA) + 5Eh

(SA) + 5Fh

Byte Offset Address

(SA) + A2h

(SA) + A4h

(SA) + A6h

(SA) + A8h

(SA) + AAh

(SA) + ACh

(SA) + AEh

(SA) + B0h

(SA) + B2h

(SA) + B4h

(SA) + B6h

(SA) + B8h

(SA) + BAh

(SA) + BCh

(SA) + BEh

Table 11.2 ID/CFI Data (Sheet 5 of 5)

DATA

VS256R/XS256R VS128R/XS128R

0020h

(Top Boot)

0023h

(Bottom Boot)

0000h

0008h

000Eh

000Eh

0005h

0005h

0008h

0010h

(Top Boot)

0013h

(Bottom Boot)

Description

Unlock Bypass

00h = Not Supported

01h = Supported

Secure Silicon Region (Customer SSR Area) Size 2

N bytes

Hardware Reset Low Time-out until reset is completed during an embedded algorithm - Maximum 2

N

ns

(e.g. 10 s => n = E)

Hardware Reset Low Time-out until reset is completed not during an embedded algorithm - Maximum 2

N

ns

(e.g. 10 s => n = E)

Erase Suspend Time-out Maximum 2

N

µs

Program Suspend Time-out Maximum 2

N

µs

Bank Organization: X= Number of banks

Bank 0 Region Information.

X= Number of sectors in bank

0020h

0020h

0020h

0020h

0020h

0020h

0010h

0010h

0010h

0010h

0010h

0010h

Bank 1 Region Information.

X= Number of sectors in bank

Bank 2 Region Information.

X= Number of sectors in bank

Bank 3 Region Information.

X= Number of sectors in bank

Bank 4 Region Information.

X= Number of sectors in bank

Bank 5 Region Information.

X= Number of sectors in bank

Bank 6 Region Information.

X= Number of sectors in bank

0020h

(Bottom Boot)

0023h

(Top Boot)

0010h

(Bottom Boot)

0013h

(Top Boot)

Bank 7 Region Information.

X= Number of sectors in bank

62 S29VS/XS-R MirrorBit

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Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 11.1 Asynchronous Read - AADM Interface

CLK may be at V

IL

or V

IH

or Active

CLK

CE#

AVD# t

AAVDS t

CAS t

AVDP t

AVDP t

AVDP t

AAVDS t

AAVDH t

AAVDH

OE#

WE#

OE# low with AVD# low signals the presence of Address-High.

The Address-High cycle is optional. When the high part of address does not change only the Address-Low cycle is needed.

OE# enables data output only after the Address-Low cycle in which AVD# is Low and OE# is High

OE# is ignored after OE# returns high between accesses until the next Address-Low is received t

ACC

A/DQ15-

A/DQ0 t

AAVDS t

AAVDH t

AAVDS t

OE t

AAVDH

Add-Hi Add-Low t

CR t

CE t

ACC

Data t t t

CEZ

OEZ

CR

RDY

Figure 11.2 Asynchronous Read Followed By Read - AADM Interface

CLK

CLK may be at V

IL

or V

IH

or Active

CE# t

CAS t t

AVDP

AVD# t

AVDO t

AAVDS t

AAVDH

OE# t

WEA t

OEH

WE# t

ACC t

CE t

ACC t

OE

A/DQ15-

A/DQ0

AH t

AAVDS tAAVDH

AL t

CR

RDY

D t

OEZ

AH t

AAVDS t

AAVDH

AL t

AVDO t

ACC t

OE t

ACC

D t

CEZ t

OEZ t

CEZ

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

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Flash Family 63

64

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 11.3 Asynchronous Read Followed By Write - AADM Interface

CLK

CLK may be at VIL or VIH or Active

CE# t

CAS t

AVDP

AVD# t

AVDO t

AAVDS t

AAVDH

OE# t

AAVDS t

AAVDH t

CS t

WEA t

OEH t

WPH t

VLWH t

WP t

WC

WE# t

CE t

OE t

ACC t

ACC

A/DQ15-

A/DQ0 t

AAVDS t

AAVDH

AH AL t

CR

D t

OEZ

AH AL t

DS

D

RDY t

CH t

DH t

CEZ t

CEZ

Figure 11.4 Asynchronous Write - AADM Interface

CLK may be at V

IL

or V

IH

or Active

CLK

CE#

AVD#

OE#

WE#

A/DQ15-

A/DQ0

RDY t

CAS t

AVDP

OE# low with AVD# low signals the presence of Address-High. The Address-High cycle is optional.

When the high part of address does not change only the Address-Low cycle is needed.

OE# enables data output only after the Address-Low cycle in which AVD# is Low and OE# is High.

OE# is ignored after OE# returns high between accesses until the next Address-Low is received.

t

AVDP t

AVDP t

AAVDS t

AAVDH t

WEA t

CS t

WPH t

WP t

VLWH t

WC t

CH t

AAVDS

Add-High t

AAVDH t

CR t

AAVDS t

AAVDH

Add-Low t

DS

Data t

DH t

CEZ

S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

CLK

CE#

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 11.5 Asynchronous Write Followed By Read - AADM Interface

CLK may be at V

IL

or V

IH

or Active

AVD#

OE# t

CAS t

AVDP t

AAVDS t

AAVDH t

WEA t

CS t

WPH t

WC t

VLWH t

WP t

OEH t

AVDO

WE#

A/DQ15-

A/DQ0

RDY t

AAVDS t

AAVDH

AH AL t

CR t

DS

D t

DH

AH AL t

CH t

OE t

ACC t

ACC

D t

OEZ t

CEZ t

CEZ

Figure 11.6 Asynchronous Write Followed By Write - AADM Interface

CLK

CLK may be at VIL or VIH or Active

CE# t

CAS t

AVDP

AVD# t

AAVDS t

AAVDH t

AAVDS t

AAVDH

OE# t

CS t

VLWH t

WP t

WEA t

WPH t

WC t

VLWH t

WP

WE#

A/DQ15-

A/DQ0 t

CR

AH t

AAVDS t

AAVDH t

AAVDS t

AAVDH

AL t

DS

D t

DH

AH AL t

DS

D

RDY t

CH t

DH t

CEZ

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 65

A/DQ15 - A/DQ0

RDY(with data)

RDY(before data)

CLK

CE#

AVD#

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 11.7 Synchronous Read Wrapped Burst Address Low Only - AADM Interface t

IA t

CES t

AVDS t

AVDP t

AVDH t

AVDS t

AVDH

OE# low with AVD# low signals the presence of Address-High.

The Address-High cycle is optional. When the high part of address does not change only the Address-Low cycle is needed.

Address-Low only cycle

OE# enables data output only after the Address-Low cycle in which AVD# is Low and OE# is High.

OE# is ignored after OE# returns high between accesses until the next Address-Low is received.

OE#

WE# t

ACS t

ACH

AH AL t

RACC t

CR t

OE t

BACC t

BDH t

RACC t

RACC t

OEZ t

RACC t

RACC

AL t

OE t

BDH t

BACC t

OEZ t

CEZ t

RACC t

RACC

CLK

CE#

A/DQ15-A/DQ0

RDY(with data)

RDY(before data)

AVD#

OE#

WE#

Figure 11.8 Synchronous Read Continuous Burst - AADM Interface tIA tCES tIA

In continuous burst, wait states equal to the internal access time are inserted between the end of one cache line and the start of the next cache line tAVDS tAVDH tAVDP tAVDS tAVDH tBACC tACS tACH tRACC tCR tOE tBACC tBDH tRACC tRACC tRACC tRACC tRACC tOEZ tCEZ

66 S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

A/DQ15-A/DQ0

RDY(with data)

RDY(before data)

CLK

CE#

AVD#

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n ) t

CES

Figure 11.9 Synchronous Read Wrapped Burst - AADM Interface t

IA

15 initial access cycles setting shown. t

IA

measured from CLK rising edge during AVD# Low to CLK rising edge at beginning of first data out.

t

AVDS t

AVDP t

AVDH

OE# low with AVD# low signals the presence of Address-High.

The Address-High cycle is optional. When the high part of address does not change only the Address-Low cycle is needed. t

AVDS t

AVDH

OE# enables data output only after the Address-Low cycle in which AVD# is Low and OE# is High.

OE# is ignored after OE# returns high between accesses until the next Address-Low is received.

OE#

WE# t

BACC t

BDH t

ACS t

ACH

AH AL t

RACC t

CR t

OE t

RACC t

RACC

CLK

CE#

A/DQ15 - A/DQ0

RDY(with data)

RDY(before data)

AVD#

OE#

WE# t

OEZ

Figure 11.10 Synchronous Read Followed By Read Burst - AADM Interface t

IA t

IA t

CES t

AVDS t

AVDP t

AVDH t

AVDS t

AVDH t

ACS t

ACH

AH AL t

RACC t

CR t

OE t

BACC t

BDH t

OEZ t

RACC t

RACC t

RACC t

RACC

AH AL

ASIC_t

CO t

OE t

BACC t

RACC t

RACC t

OEZ t

CEZ t

CEZ t

CEZ

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 67

CLK

CE#

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 11.11 Synchronous Read Followed By Write - AADM Interface t

IA t

CES t

AVDP t

AVDH t

AVDS t

AVDP

AVD#

OE#

A/DQ15-A/DQ0

RDY(with data)

RDY(before data)

WE# t

WEA t

OEH t

ACS t

ACH

AH t

RACC t

CR

AL t

OE t

WPH t

WC t

RACC t t

BACC t

BDH t

BACC

RACC t

RACC t

RACC t

OEZ

AH t t

VLWH

WP t

CH

AL t

RACC t

RACC t

DS

Write Data t

DH t

CEZ

Figure 11.12 Synchronous Write Followed By Read Burst - AADM Interface t

IA

CLK

CE# t

CAS t

AVDP t

CES

AVD#

OE#

A/DQ15-A/DQ0

RDY(with data)

RDY(before data)

WE# t

VLWH t

WPH t

WEA

Address-High

Cycles Optional t

WC t

WP# t

AAVDS t

AAVDH

AH AL t

CR t

RACC t

DS

Write Data t

CR t

RACC t

AVDH t

AVDS t

OEH

Address-High

Cycles Optional t

DH

AH t

RACC

AL t

RACC t

OE t

BACC t

BDH t

BACC t

RACC t

OEZ t

CEZ

68 S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 11.13 Synchronous Write Followed By Write - AADM Interface

CLK

CE#

AVD#

OE#

WE#

A/DQ15-

A/DQ0

RDY t

CAS t

AVDP t

AAVDS t

AAVDH t

AAVDS t

AAVDH t

CS t t

VLWH

WP t

WC t

AAVDS t

AAVDH

AH AL t

CR t

RACC t

DS

Write Data t

DH t

RACC t

WEA t

WPH t

WC t

VLWH t

WP t

CH t

AAVDS t

AAVDH

AH AL t

RACC t

DS

Write Data t

DH t

CEZ

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 69

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

12. Revision History

Section

Revision 01 (May 15, 2008)

Description

Initial release

Revision 02 (August 1, 2008)

DC Characteristics

Device ID and Common Flash Memory

Interface Address Map

Memory Address Map

Revision 03 (September 12, 2008)

Physical Dimensions/Connection

Diagrams

Revision 04 (March 10, 2009)

Blank Check Command

DC Characteristics

Global

Revision 05 (May 26, 2010)

Global

Features

Ordering Information and Valid

Combinations

Address/Data Interface

Device Bus Operations Table

Changed some values in the CMOS Compatible table

Changed some values in the ID/CFI Data table

Added memory address map

Updated ball positions

Functional in Asynchronous Read Mode only

Changed some I

CCB

values

Added 108 MHz; removed 66 MHz

Modified document title

Clarified some points

Added Industrial Temperature range option

Corrected typo

Corrected A/DQ15-A/DQ0 column information for Asynchronous Read

Asynchronous Read

S29XS-R AADM Access

S29VS-R ADM Access

S29XS-R AADM Access

Clarified asynchronous read operation.

Clarified asynchronous AADM read access.

Standardized logic Low and High descriptions to V

IL

and V

IH access and internal boundary crossings.

. Clarified wait states required by initial

Standardized logic Low and High descriptions to V

IL access and internal boundary crossings.

and V

IH

. Clarified wait states required by initial

Writing Commands/Command

Sequences

Program/Erase Operations

Sector Lock Range Command

Figure Synchronous Read Mode

Figure Asynchronous Mode Read

Figure Asynchronous Program

Operation Timings

Figure Back-to-Back Read/Write Cycle

Timings

Clarified device behavior.

Removed redundant information.

Clarified Sector Lock Range behavior

Added “ADM Interface” label

Added “ADM Interface” label

Added “ADM Interface” label

Added “ADM Interface” label

Figure Latency with Boundary Crossing Corrected CR8 setting in Notes 1 and 2

Figure Latency with Boundary Crossing into Bank Performing Embedded

Operation

Corrected CR8 setting in Notes 1 and 2

Figures Asynchronous Read - AADM

Interface to Asynchronous Write

Followed By Write - AADM Interface

Clarified CLK waveform behavior

Figure Synchronous Write Followed By

Read Burst - AADM Interface

ADM Interface (S29VS256R and

S29VS128R)

Table Wait State vs. Frequency

Corrected Figure title

Clarified traditional interface

Modified title and added note

70 S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Section

Table Address Latency for 10 -13 Wait

States

Added note

Table Address Latency for 9 Wait States Added note

Figure Synchronous Read

CLK Characterization

Erase and Programming Performance

Revision 06 (July 22, 2010)

DC Characteristics

Performance Characteristics

Removed note 1

Removed note 2

Corrected note 2

Changed I

CC

Description

Read test conditions to OE#=H with relevant values

Updated tables

Changed typical programming times Erase and Programming Performance

Revision 07 (November 18, 2010)

Erase and Programming Performance

ID/CFI Data

Changed maximum chip erase times

Corrected Data and Description for Word Offset 03h, 55h, 56h

Corrected Data for Word Offset 1Dh, 1Eh, 52h

Revision 08 (July 30, 2012)

Command Definitions Corrected number of cycles for Write Buffer Load

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 71

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document.

Copyright © 2008-2012 Spansion Inc. All rights reserved. Spansion

®

, the Spansion logo, MirrorBit

®

, MirrorBit

®

Eclipse™, ORNAND™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.

72 S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

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