NB100LVEP222 D

NB100LVEP222 D
NB100LVEP222
2.5 V/3.3 V 2:1:15
Differential ECL/PECL ÷1/÷2
Clock Driver
The NB100LVEP222 is a low skew 2:1:15 differential ÷1/÷2 ECL
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be used in a differential
configuration or single−ended (with VBB output reference bypassed
and connected to the unused input of a pair). Either of two fully
differential clock inputs may be selected. Each of the four output
banks of 2, 3, 4, and 6 differential pairs may be independently
configured to fanout 1X or 1/2X of the input frequency. When the
output banks are configured with the B1 mode, data can also be
distributed. The LVEP222 specifically guarantees low output to output
skew. Optimal design, layout, and processing minimize skew within a
device and from lot to lot. This device is an improved version of the
MC100LVE222 with higher speed capability and reduced skew.
The fsel pins and CLK_Sel pin are asynchronous control inputs.
Any changes may cause indeterminate output states requiring an MR
pulse to resynchronize any 1/2X outputs (See Figure 4). Unused
output pairs should be left unterminated (open) to reduce power and
switching noise.
The NB100LVEP222, as with most ECL devices, can be operated
from a positive VCC/VCC0 supply in LVPECL mode. This allows the
LVEP222 to be used for high performance clock distribution in
+2.5/3.3 V systems. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power
supplies. For more information on using PECL, designers should refer
to Application Note AN1406/D. For a SPICE model, refer to
Application Note AN1560/D.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended LVPECL input conditions, the
unused differential input is connected to VBB as a switching reference
voltage. VBB may also rebias AC coupled inputs. When used, decouple
VBB and VCC/VCC0 via a 0.01 mF capacitor and limit current sourcing
or sinking to 0.5 mA. When not used, VBB should be left open.
Single−ended CLK input operation is limited to a VCC/VCC0 ≥ 3.0 V in
LVPECL mode, or VEE v −3.0 V in NECL mode.
Features
•
•
•
•
•
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MARKING
DIAGRAMS*
52
1
NB100
LVEP222
AWLYYWWG
LQFP−52
FA SUFFIX
CASE 848H
52
1
1
NB100
LVEP222
AWLYYWWG
52
QFN−52
MN SUFFIX
CASE 485M
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
20 ps Output−to−Output Skew
85 ps Part−to−Part Skew
Selectable 1x or 1/2x Frequency Outputs
LVPECL Mode Operating Range:
VCC/VCC0 = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC/VCC0 = 0 V with VEE = −2.375 V to −3.8 V
Internal Input Pulldown Resistors
•
• Performance Upgrade to ON Semiconductor’s MC100LVE222
• VBB Output
• These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2015
April, 2015− Rev. 13
1
Publication Order Number:
NB100LVEP222/D
Qc0
Qc1
Qc1
Qc2
Qc2
Qc3
Qc3
VCC0
NC
NC
39
40
38
37
36
35
34
33
32
31
30
29
28
VCC0
Qc0
VCC0
VCC0
NB100LVEP222
27
26
Qd0
Qb2
41
25
Qd0
Qb2
42
24
Qd1
Qb1
43
23
Qd1
Qb1
44
22
Qd2
Qb0
45
21
Qd2
Qb0
46
20
Qd3
VCC0
47
19
Qd3
Qa1
48
18
Qd4
Qa1
49
17
Qd4
Qa0
50
16
Qd5
Qa0
51
15
Qd5
VCC0
52
14
VCC0
5
6
7
8
9
10
11
12
CLK0
CLK_Sel
CLK1
CLK1
VBB
fselc
fseld
13
VEE
4
CLK0
MR
3
fselb
2
fsela
1
VCC
NB100LVEP222
All VCC, VCC0, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation.VCC pin internally
connected to VCC0 pins. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a
heat−sinking conduit. This exposed pad is electrically connected to VEE internally.
Figure 1. 52−Lead LQFP Pinout (Top View)
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2
CLK0*, CLK0**
CLK1*, CLK1**
CLK_Sel*
MR*
Qa0:1, Qa0:1
Qb0:2, Qb0:2
Qc0:3, Qc0:3
Qd0:5, Qd0:5
fseln*
VBB
VCC, VCC0
VEE***
NC
Qa0
Qa1
Qa1
VCC0
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
50
49
48
47
46
45
44
43
42
41
VCC0
Qa0
51
VCC
1
39
VCC0
MR
2
38
Qc0
fsela
3
37
Qc0
fselb
4
36
Qc1
CLK0
5
35
Qc1
CLK0
6
34
Qc2
CLK_SEL
7
33
Qc2
CLK1
8
32
Qc3
CLK1
9
31
Qc3
VBB
10
30
VCC0
fselc
11
29
NC
fseld
12
28
NC
VEE
13
27
VCC0
16
17
18
19
20
21
22
23
24
25
Qd5
Qd4
Qd4
Qd3
Qd3
Qd2
Qd2
Qd1
Qd1
Qd0
26
15
Qd5
Qd0
14
VCC0
NB100LVEP222
Figure 2. QFN−52 Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
Exposed Pad (EP)
40
VCC0
52
NB100LVEP222
Table 2. FUNCTION TABLE
Function
FUNCTION
ECL Differential Input Clock
ECL Differential Input Clock
ECL Clock Select
ECL Master Reset
ECL Differential Outputs
ECL Differential Outputs
ECL Differential Outputs
ECL Differential Outputs
ECL 1 or 2 Select
Reference Voltage Output
Positive Supply, VCC = VCC0
Negative Supply
No Connect
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the package is
electrically connected to VEE internally.
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3
Input
L
H
MR
CLK_Sel
fseln
Active
CLK0
÷1
Reset
CLK1
÷2
NB100LVEP222
MR
CLK0
CLK0
÷1
CLK1
2
÷2
Qa0:1
Qa0:1
CLK1
CLK_SEL
VBB
fsela
3
Qb0:2
Qb0:2
fselb
4
Qc0:3
Qc0:3
VCC/VCC0
VEE
fselc
6
Qd0:5
Qd0:5
fseld
Figure 3. Logic Diagram
CLK
MR
Q (B2)
Q (B1)
Figure 4. Master Reset (MR) Timing Diagram
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4
NB100LVEP222
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP−52
QFN−52
Flammability Rating
Oxygen Index: 28 to 34
Pb Pkg
Pb−Free Pkg
Level 2
−
Level 3
Level 2
UL 94 V−O @ 0.125 in
Transistor Count
821 Devices
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
VCC/VCC0
PECL Mode Power Supply
VEE
Condition 1
Condition 2
Rating
Unit
VEE = 0 V
6
V
NECL Mode Power Supply
VCC/VCC0 = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC/VCC0 = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
±0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(See Application Information)
0 lfpm
500 lfpm
LQFP−52
LQFP−52
35.6
30
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(See Application Information)
0 lfpm
500 lfpm
LQFP−52
LQFP−52
3.2
6.4
°C/W
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
(Note )
0 lfpm
500 lfpm
QFN−52
QFN−52
25
19.6
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note )
2S2P
QFN−52
21
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI ≤ VCC/VCC0
VI ≥ VEE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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NB100LVEP222
Table 5. LVPECL DC CHARACTERISTICS VCC = VCC0 = 2.5 V; VEE = 0 V (Note 2)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
100
125
150
104
130
156
112
140
168
mA
VOH
Output HIGH Voltage (Note 3)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 3)
555
680
900
555
680
900
555
680
900
mV
VIH
Input HIGH Voltage (Single−Ended)
(Note 4)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 4)
555
900
555
900
555
900
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 5) (Figure 6)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
Symbol
Characteristic
150
CLK
CLK
0.5
−150
150
0.5
−150
mA
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
2. Input and output parameters vary 1:1 with VCC/VCC0. VEE can vary + 0.125 V to −1.3 V.
3. All loading with 50 W to VCC/VCC0 − 2.0 V.
4. Do not use VBB Pin #10 at VCC/VCC0 < 3.0 V (see AND8066).
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the
differential input signal.
Table 6. LVPECL DC CHARACTERISTICS VCC = VCC0 = 3.3 V; VEE = 0.0 V (Note 6)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
100
125
150
104
130
156
112
140
168
mA
VOH
Output HIGH Voltage (Note 7)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 7)
1355
1480
1700
1355
1480
1700
1355
1480
1700
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1355
1700
1355
1700
1355
1700
mV
VBB
Output Reference Voltage (Note 8)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9) (Figure 6)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1875
150
CLK
CLK
0.5
−150
1875
150
0.5
−150
0.5
−150
1875
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input and output parameters vary 1:1 with VCC/VCC0. VEE can vary + 0.925 V to −0.5 V.
7. All loading with 50 W to VCC/VCC0−2.0 V.
8. Single−Ended input operation is limited VCC/VCC0 ≥ 3.0 V in LVPECL mode.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the
differential input signal.
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NB100LVEP222
Table 7. LVNECL DC CHARACTERISTICS VCC = VCC0 = 0.0 V; VEE = −3.8 V to −2.375 V (Note 10)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
100
125
150
104
130
156
112
140
168
mA
Output HIGH Voltage (Note 11)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
Output LOW Voltage (Note 11)
−1945
−1820
−1600
−1945
−1820
−1600
−1945
−1820
−1600
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1945
−1600
−1945
−1600
−1945
−1600
mV
VBB
Output Reference Voltage (Note 12)
−1525
−1325
−1525
−1325
−1525
−1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13) (Figure 6)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current CLK
CLK
Symbol
Characteristic
IEE
Power Supply Current
VOH
VOL
−1425
VEE + 1.2
0.0
VEE + 1.2
150
0.5
−150
−1425
0.0
VEE + 1.2
150
0.5
−150
−1425
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
10. Input and output parameters vary 1:1 with VCC/VCC0.
11. All loading with 50 W to VCC/VCC0 − 2.0 V.
12. Single−Ended input operation is limited VEE ≤ −3.0 V in NECL mode.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the
differential input signal.
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NB100LVEP222
Table 8. AC CHARACTERISTICS VCC = VCC0 = 2.375 to 3.8 V; VEE = 0.0 V or VCC = VCC0 = 0.0 V; VEE = −2.375 to −3.8 V
(Note 14)
−40°C
25°C
Min
Typ
fout = 50 MHz
fout = 0.8 GHz
fout = 1.0 GHz
500
550
500
600
650
650
tPLH
tPHL
Propagation Delay (Differential Configuration)
CLKx−QX
MR−QXX
650
700
800
900
900
1200
tskew
Within−Device Skew (Note 15)
(÷1 Mode)
− Qa[0:1]
− Qb[0:2]
− Qc[0:3]
− Qd[0:5]
10
10
20
10
− QaN, QbN, QdN
− All Outputs
Symbol
VOpp
tskew
Min
Typ
500
525
425
600
650
650
700
700
875
900
1000
1200
40
40
60
40
10
10
20
10
10
20
40
60
− Qa[0:1]
− Qb[0:2]
− Qc[0:3]
− Qd[0:5]
15
15
20
15
− QaN, QbN, QdN
− All Outputs
Characteristic
Differential Output Voltage
(Figure 5)
Max
85°C
Max
Min
Typ
Max
500
500
400
600
650
600
850
700
975
900
1150
1200
40
40
60
40
10
10
20
10
40
40
60
40
10
20
40
60
10
20
40
60
70
70
70
70
10
10
20
10
40
40
50
40
15
10
15
15
70
40
70
70
15
20
70
70
10
20
40
50
15
15
70
70
Unit
mV
Within−Device Skew (Note 15)
(÷2 Mode)
ps
ps
ps
tskew
Device−to−Device Skew (Differential
Configuration) (Note 16)
85
300
85
300
85
300
ps
tJITTER
Random Clock Jitter (Figure 5) (RMS)
1
5
1
4
1
5
ps
VPP
Input Swing (Differential Configuration)
(Note 17) (Figure 6)
150
800
1200
150
800
1200
150
800
1200
mV
DCO
Output Duty Cycle
49.5
50
50.5
49.5
50
50.5
49.5
50
50.5
%
tr/tf
Output Rise/Fall Time 20%−80%
100
200
300
100
200
300
150
250
350
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
14. Measured with LVPECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC/VCC0 − 2.0 V.
15. Skew is measured between outputs under identical transitions and operating conditions.
16. Device−to−Device skew for identical transitions at identical VCC/VCC0 levels.
17. VPP is the differential configuration input voltage swing required to maintain AC characteristics including tPD and device−to−device skew.
10
9.0
800
Q AMP (÷ 2)
700
8.0
7.0
6.0
600
Q AMP (÷ 1)
5.0
500
4.0
400
3.0
RMS JITTER
RMS JITTER (ps)
VOPP, OUTPUT VOLTAGE (mV)
900
2.0
300
1.0
200
0.1
0.5
1.0
INPUT FREQUENCY (GHz)
1.5
0
2.0
Figure 5. Output Voltage (VOPP) versus Input Frequency and Random Clock Jitter (tJITTER) @ 255C
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NB100LVEP222
VCC/VCC0(LVPECL)
VIH(DIFF)
VPP
VIHCMR
VIL(DIFF)
VEE
Figure 6. LVPECL Differential Input Levels
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NB100LVEP222
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
NB100LVEP222
The NB100LVEP222 uses a thermally enhanced 52−lead
LQFP package. The package is molded so that a portion of
the leadframe is exposed at the surface of the package
bottom side. This exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the NB100LVEP222 high−speed bipolar integrated circuit
and will ease the power management task for the system
design. In multilayer board designs, a thermal land pattern
on the printed circuit board and thermal vias are
recommended to maximize both the removal of heat from
the package and electrical performance of the
NB100LVEP222. The size of the land pattern can be larger,
smaller, or even take on a different shape than the exposed
pad on the package. However, the solderable area should be
at least the same size and shape as the exposed pad on the
package. Direct soldering of the exposed pad to the thermal
land will provide an efficient thermal conduit. The thermal
vias will connect the exposed pad of the package to internal
copper planes of the board. The number of vias, spacing, via
diameters and land pattern design depend on the application
and the amount of heat to be removed from the package.
Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern.
The recommended thermal land design for
NB100LVEP222 applications on multi−layer boards
comprises a 4 X 4 thermal via array using a 1.2 mm pitch as
shown in Figure 7 providing an efficient heat removal path.
the solder joints. The attachment process for the exposed pad
package is equivalent to standard surface mount packages.
Figure 8, “Recommended solder mask openings”, shows a
recommended solder mask opening with respect to a 4 X 4
thermal via array. Because a large solder mask opening may
result in a poor rework release, the opening should be
subdivided as shown in Figure 8. For the nominal package
standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should
be considered.
All Units mm
0.2
1.0
1.0
4.6
0.2
4.6
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
Exposed Pad
Land Pattern
Figure 8. Recommended Solder Mask Openings
Proper thermal management is critical for reliable system
operation. This is especially true for high−fanout and high
output drive capability products.
For thermal system analysis and junction temperature
calculation the thermal resistance parameters of the package
is provided:
All Units mm
4.6
Table 9. Thermal Resistance *
4.6
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
lfpm
qJA 5C/W
qJC 5C/W
0
35.6
3.2
100
32.8
4.9
500
30.0
6.4
* Junction to ambient and Junction to board, four−conductor
layer test board (2S2P) per JESD 51−8
These recommendations are to be used as a guideline,
only. It is therefore recommended that users employ
sufficient thermal modeling analysis to assist in applying the
general recommendations to their particular application to
assure adequate thermal performance. The exposed pad of
the NB100LVEP222 package is electrically shorted to the
substrate of the integrated circuit and VEE. The thermal land
should be electrically connected to VEE.
Exposed Pad
Land Pattern
Figure 7. Recommended Thermal Land Pattern
The via diameter should be approximately 0.3 mm with
1 oz. copper via barrel plating. Solder wicking inside the via
may result in voiding during the solder process and must be
avoided. If the copper plating does not plug the vias, stencil
print solder paste onto the printed circuit pad. This will
supply enough solder paste to fill those vias and not starve
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10
NB100LVEP222
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1642/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ORDERING INFORMATION
Package
Shipping†
NB100LVEP222FAG
LQFP−52
(Pb−Free)
160 Units / Tray
NB100LVEP222FARG
LQFP−52
(Pb−Free)
1500 / Tape & Reel
NB100LVEP222MNG
QFN−52
(Pb−Free)
260 Units / Tray
NB100LVEP222MNR2G
QFN−52
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
11
NB100LVEP222
PACKAGE DIMENSIONS
LQFP 52 LEAD EXPOSED PAD
CASE 848H
ISSUE B
4 PL
M
M/2
−Z−
0.20 (0.008) T X-Y Z
AJ AJ
52
40
39
1
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
PLATING
−X−
AA
−Y−
L
B
AB
B/2
L/2
J
D
REF
13
27
0.08 (0.003)
26
14
M
Y T-U
DETAIL AJ−AJ
A/2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MM.
3. DATUM PLANE “E" IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING PLANE.
4. DATUM “X", “Y" AND “Z" TO BE DETERMINED AT
DATUM PLANE DATUM “E".
BASE
METAL 5. DIMENSIONS M AND L TO BE DETERMINED AT
SEATING PLANE DATUM “T".
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLAND “E".
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM D DIMENSION
BY MORE THAN 0.08 (0.003). DAMBAR CANNOT
Z
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION
AND ADJACENT LEAD OR PROTRUSION 0.07
(0.003).
0.20 (0.008) E X-Y Z
A
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
V
W
AA
AB
AC
AD
AE
DETAIL AH
−E−
−T−
AG
G
SEATING
PLANE
AG
48 PL
D
0.10 (0.004) T
52 PL
0.08 (0.003)
M
T X-Y
V
Z
0.05 (0.002)
R
S
AC
AD
EXPOSED PAD
14
26
S
C
27
13
W
N
K
P
F
H
AE
MILLIMETERS
MIN
MAX
10.00 BSC
10.00 BSC
1.30
1.50
0.22
0.40
0.45
0.75
0.65 BSC
1.00 REF
0.09
0.20
0.05
0.20
12.00 BSC
12.00 BSC
0.20 REF
0_
7_
0_
----1.70
12 _ REF
12 _ REF
0.20
0.35
0.07
0.16
0.08
0.20
4.58
4.78
4.58
4.78
INCHES
MIN
MAX
0.394 BSC
0.394 BSC
0.051
0.059
0.009
0.016
0.018
0.030
0.026 BSC
0.039 BSC
0.004
0.008
0.002
0.008
0.472 BSC
0.472 BSC
0.008 REF
0_
7_
0_
----0.067
12 _ REF
12 _ REF
0.008
0.014
0.003
0.006
0.003
0.008
0.180
0.188
0.180
0.188
0.25
GAGE
PLANE
RECOMMENDED
SOLDERING FOOTPRINT
DETAIL AH
12.36
52X
52
1.18
4.80
39
1
40
VIEW AG−AG
4.80
PKG
OUTLINE
www.onsemi.com
12
0.65
PITCH
12.36
52X
0.40
DIMENSIONS: MILLIMETERS
NB100LVEP222
PACKAGE DIMENSIONS
52 PIN QFN 8x8, 0.5P
CASE 485M
ISSUE C
D
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
PIN ONE
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
K
L
E
2X
0.15
C
2X
0.15 C
A2
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.60
0.80
0.20 REF
0.18
0.30
8.00 BSC
6.50
6.80
8.00 BSC
6.50
6.80
0.50 BSC
0.20
--0.30
0.50
0.10 C
A
0.08 C
A3
A1
REF
SEATING PLANE
RECOMMENDED
SOLDERING FOOTPRINT
C
D2
14
8.30
52X
26
0.62
6.75
52 X
L
27
13
E2
6.75
39
1
52 X
K
8.30
52
40
e
52 X
b
NOTE 3
0.10 C A B
PKG
OUTLINE
0.05 C
0.50
PITCH
52X
0.30
DIMENSIONS: MILLIMETERS
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
13
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB100LVEP222/D
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