An Autotuning Digital Controller for DC–DC Power Converters Based on Online

An Autotuning Digital Controller for DC–DC Power Converters Based on Online
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
An Autotuning Digital Controller for DC–DC
Power Converters Based on Online
Frequency-Response Measurement
Mariko Shirazi, Student Member, IEEE, Regan Zane, Senior Member, IEEE,
and Dragan Maksimovic, Senior Member, IEEE
Abstract—This paper describes a hardware-descriptionlanguage-coded autotuning algorithm for digital PID-controlled
dc–dc power converters based on online frequency-response
measurement. The algorithm determines the PID controller parameters required to maximize the closed-loop bandwidth of the
feedback control system while maintaining user-specified stability
margins and integral-based no-limit-cycling criteria, as well as ensuring single-crossover-frequency operation and sufficiently high
loop gain magnitude at low frequencies. Experimental results are
provided for five different pulsewidth-modulated dc–dc converters, including a well-damped synchronous buck, a lightly damped
synchronous buck with and without a poorly damped input filter, a boost operating in continuous-conduction mode, and a boost
operating in discontinuous-conduction mode.
Index Terms—DC–DC power conversion, digital control, frequency response, identification, pulsewidth-modulated (PWM)
power converters, switched-mode power supplies (SMPS), tuning.
I. INTRODUCTION
ONVENTIONAL offline design of controllers for dc–dc
power converters is complicated by unknown load characteristics, as well as uncertainties within the converter itself.
The converter component values are subject to manufacturing
tolerances, and converter parasitics are notoriously difficult
to model. In light of these uncertainties, the designer must
make some assumptions regarding the expected range of load
and core converter dynamics, and design a controller that
will maintain acceptable stability margins under worst-case
conditions. A robust design capable of handling wide variations
in dynamics will be overly conservative by design over most
of the expected range, resulting in degraded performance. The
benefit of an autotuning controller is the ability to perform
online control design in the presence of actual system dynamics,
resulting in a more optimal design over the full range of system
characteristics. The ability to embed such algorithms into the
existing feedback controller represents a significant advantage
of digital controllers for switched-mode power supplies (SMPS)
over their analog counterparts.
The terminology adopted in this paper is consistent with that
used in [1] and [2], namely the term automatic tuning, or au-
C
Manuscript received March 7, 2009; revised May 21, 2009. Current version
published December 18, 2009. Recommended for publication by Associate
Editor C. K. Kong Tse.
The authors are with the Colorado Power Electronics Center, University
of Colorado, Boulder, CO 80309 USA (e-mail: [email protected];
[email protected]; [email protected]).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2009.2029691
totuning, refers to a tuning process that executes, upon startup,
event detection, regularly scheduled interval, or external command. The resulting controller parameters are then held constant
until the next time the process is run. In contrast, the term adaptation, or adaptive control, refers to the process of continuously
updating the controller parameters in a feedback loop to accommodate changing system dynamics or external disturbances. The
same adaptive methods can be used in an autotuning context if
enabled only at discrete intervals; however, there also exist dedicated open-loop autotuning methods. The distinction between
the two is pointed out here in order to facilitate a discussion
of the recent applications of these techniques to SMPS and to
motivate the autotuning work described in this paper.
Adaptive control techniques based on model reference adaptive control (MRAC) [1] have been successfully applied to PIDcontrolled continuous-conduction mode (CCM) buck converters
in [3]–[5], and CCM, as well as discontinuous-conduction mode
(DCM) buck converters, in [6]. In these works, small oscillations
are injected into the duty cycle command with the converter operating in closed loop, and the PID controller parameters are
adjusted in an adaptive feedback loop to achieve crossover frequency and phase margin specifications. Adaptive control using
the self-tuning regulator (STR) concept [1], [7], [8] has been
used to tune predictive controllers for a CCM buck converter
in [9] and a phase-controlled rectifier in [10]. The STR concept
has also been applied in an autotuning context to deadbeatcontrolled CCM buck converters in [11].
A challenge associated with any adaptive control scheme is
the selection of the parameter update algorithms that ensure stability of the adaptive loop, and therefore, convergence of controller parameters. As the loop dynamics depend on the openloop plant being controlled, it is clear that sufficient a priori
knowledge of the expected range of plant dynamics is required
to select parameter update rates and dynamics that ensure stability over the entire range. Particular care must be taken with
nonminimum phase (NMP) systems. Another question specific
to MRAC techniques is how the loop will behave if, for the given
plant dynamics and compensator structure, there is no solution
in terms of compensator parameters that will cause the closedloop system to have the desired dynamics. In contrast, open-loop
autotuning techniques can be applied that require little a priori
knowledge of the plant being controlled.
Open-loop autotuning methods based on inducing limit-cycle
oscillations (LCOs) have been successfully applied to PIDcontrolled CCM buck converters in [3], and [12]–[14], as well
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SHIRAZI et al.: AUTOTUNING DIGITAL CONTROLLER FOR DC–DC POWER CONVERTERS
Fig. 1. Digitally controlled PWM converter with integrated frequencyresponse measurement and autotuning capabilities.
as PID-controlled CCM boost converters in [12] and [15]. The
amplitude and the frequency of the LCOs provide information regarding the loop frequency response, and compensator
parameters can be tuned to achieve specified crossover frequency and phase margin. One limitation common to all LCObased autotuning techniques, as well as the single-frequency
injection MRAC schemes of [4]–[6], is that the knowledge of
the loop frequency response can be obtained only at the frequencies at which the system is excited. In particular, none of
these methods are able to measure or take into account gain
margin specifications. In addition, multiple crossover frequencies and undesirable flattening of the loop gain magnitude at
low values before the crossover frequency can neither be detected nor avoided. The MRAC approaches are further unable
to address no-limit-cycling considerations, while in the LCObased approaches such considerations can be incorporated only
as a final check on the controller design. Autotuning methods based on online identification of the converter control-tooutput frequency response can overcome these limitations Such
methods have been successfully applied to CCM buck converters in [14], [16], and [17]. In [16], the frequency response is
parametrically identified, and then, a compensator is designed
offline using model inversion techniques. The nonparametric
frequency response is used in [17] to design a PID compensator
offline using time- and frequency-domain simulations iterated
within an optimization framework to meet multiple design criteria. PID compensator parameters are iterated and loop frequency response data are computed online in [14] to maximize
crossover frequency subject to phase margin and integral-based
no-limit-cycling constraints.
The autotuning approach presented in this paper is an extension of the identification-based autotuning work presented
in [14]. An overall block diagram of the system is depicted in
Fig. 1. As described in [18] and [19], the system-identification
algorithm injects a pseudorandom binary sequence (PRBS) perturbation, stores the resulting output voltage perturbations, and
computes and stores the converter open-loop frequency response. In Fig. 1, the input stimulus dstim [n] is injected into
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the digital pulsewidth modulator (DPWM) on top of the compensator output dcomp [n], which is frozen at its steady-state
value during identification. With the converter open-loop frequency response stored in memory, the autotuning algorithm
can construct the entire loop frequency response for any arbitrary compensator structure and parameters. For example, the
PID parameters can be iterated computationally to force the loop
frequency response to meet specifications at arbitrary frequencies, without the need for further system perturbations. The final
PID parameters are then exported to the programmable digital
PID controller. Section II of this paper gives an overview of
the autotuning procedure. Experimental results, including the
autotuning controller hardware implementation, are presented
in Section III. In order to demonstrate the versatility of this autotuning approach, results are provided for five different PWM
dc–dc converters, including a well-damped synchronous buck,
a lightly damped synchronous buck with and without a poorly
damped input filter, a boost operating in CCM, and a boost operating in DCM. The conclusions, including a summary of the
relative merits of the autotuning method presented here with
respect to MRAC-based techniques, are given in Section IV.
II. AUTOTUNING ALGORITHM
The digital PID control law of Fig. 1 was obtained by application of the backward rectangular version of Euler’s method to
the continuous-time PID differential equation. The Z-transform
of this control law can be expressed in either parallel or cascade
form as follows:
KI
+ KD 1 − z −1
Gc (z) = KP +
1 − z −1
1 − z1 z −1 1 − z2 z −1
.
(1)
= Kcomp
(1 − z −1 )
The three independent PID parameters have different interpretations depending on whether the PID is expressed in parallel or cascade form. In the parallel form, the parameters KP ,
KI , and KD represent the proportional, integral, and derivative
gains, respectively. In the cascade form, the parameters are expressed as the gain Kcomp , and the discrete-time zero locations
z1 = e−2π f z 1 T s and z2 = e−2π f z 2 T s , where Fs = 1/Ts is the
sampling frequency, which is also equal to the converter switching frequency. Since the autotuning method implemented here
is a loop-shaping method, it is most convenient to work with
the cascade form and iterate zero locations. For any given converter operating with a PID feedback controller, the locations
of the PID zeros determine the phase margin of the closed-loop
system. However, the solution is not unique. In this paper, an
a priori decision is made to place fz 1 , the frequency of the
first PID zero, at the frequency f−90 ◦ , where the phase of the
measured open-loop frequency response Hv Gv d (ej ω T s ) first
drops below −90◦ . The variables Gv d (ej ω T s ) and Hv are the
converter open-loop frequency response and the sensing gain,
respectively, as shown in Fig. 1. The frequency of the second
PID zero fz 2 then uniquely determines the phase margin. The
goal of the autotuning algorithm is to maximize the closed-loop
bandwidth of the feedback control system, as indicated by the
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
Fig. 2. Analytical Bode plots for an exemplary tuning case. (a) Converter control-to-output transfer function G v d (z). (b) PID controller G c (z). (c) Resulting
loop transfer function T (z). Square: f−9 0 ◦ ; circle: fc ; upward pointing triangle: fz 1 ; downward pointing triangle: fz 2 ; PM: phase margin; GM: gain margin.
loop-transfer-function crossover frequency fc , while maintaining user-specified stability margins and integral-based no-limitcycling criteria, as well as ensuring single-crossover-frequency
operation and sufficiently high loop gain magnitude at low frequencies. To this end, the algorithm iteratively reduces the target
crossover frequency fc,targ until it reaches one for which PID
parameters exist, which ensure that the resulting closed-loop
system meets specifications. The target crossover frequency is
initialized at Fs /8. Then, the basic autotuning procedure is as
follows: the first PID zero is placed at f−90 ◦ , constraints are
placed on the second PID zero to ensure that the integral gain
remains sufficiently low to satisfy the integral-based no-limitcycling criteria [20], [21], and then, the second PID zero is
iterated over its allowable range to attempt to provide the required phase lead at fc,targ to meet the phase margin specification. If the phase margin specification cannot be met, the target
crossover frequency is reduced and the procedure repeated. If a
suitable zero is found, the compensator gain Kcomp is computed
to ensure that the actual crossover frequency occurs at fc,targ .
Finally, the complete loop frequency response is constructed. A
check is then run to measure the gain margin, and detect multiple crossover frequencies and insufficient loop gain magnitude
at low frequencies. If the conditions are not met, the procedure
is repeated using a reduced target crossover frequency. Fig. 2
shows relevant tuning variables graphically displayed on analytically derived Bode plots of the converter control-to-output
transfer function Gv d (z), PID controller Gc (z), and the resulting loop transfer function T (z) of an exemplary tuning case.
Details of the autotuning procedure, which, in many aspects,
resembles the approach a designer would follow, are discussed
in the following sections.
A. Allowance for Integral-Only Control
If fc,targ iterates down to a value less than f−90 ◦ , where no
phase lead is required to meet the phase margin specification,
then the controller reverts to an integral-only controller, as the
inclusion of a zero at f−90 ◦ in this case would only reduce the
loop gain roll-off. The integral-only test is expressed as
Gv d ej 2π f c , targ T s ≥ ϕm − 90◦
(2)
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SHIRAZI et al.: AUTOTUNING DIGITAL CONTROLLER FOR DC–DC POWER CONVERTERS
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TABLE I
INTEGRAL-BASED NO-LIMIT-CYCLING CONSTRAINTS
TABLE II
HARDWARE REQUIREMENTS FOR SYSTEM-IDENTIFICATION AND AUTOTUNING ALGORITHMS
where ϕm is the desired phase margin. In this case, both z1 and
z2 are set to zero, and the algorithm skips to computation of
Kcomp .
B. Embedding Integral-Based No-Limit-Cycling Criteria Early
in the Design Process
Under certain conditions, due to quantization effects, a digitally controlled converter can exhibit generally undesirable limit
cycling [20], [21]. To avoid limit cycling, it has been shown
in [20] and [21] that the controller integral gain Ki must not be
too high, i.e., it should satisfy
Fig. 3.
CCM buck converter hardware prototype.
Fig. 4.
CCM/DCM boost converter hardware prototype.
Ki Hv Gv d0 < α
(3)
j 0 where α < 1 is a safety factor and Gv d0 = Gv d e is the
dc gain of the control-to-output transfer function. It is possible to design a compensator, and then check to see whether
the criterion (3) is satisfied. Instead, the tuning algorithm presented here embeds this criterion much earlier in the design
process by using it to constrain the target crossover frequency
or the PID zero locations. The relevant constraint depends on
whether fz 2 is less than or greater than fc,targ . For cases where
fz 2 < fc,targ , these constraints are in the form of a maximum
allowed frequency for fz 2 . For cases where fz 2 ≥ fc,targ , these
constraints
are
in the form
of a minimum allowed magnitude
of Hv Gv d ej 2π f c , targ T s . In both cases, the location of fz 1
relative to fc,targ dictates the expression to use according to the
results shown in Table I. A derivation of these expressions is
given in the Appendix.
In implementing these constraints, since the location of fz 1
has been fixed, the current fc,targ immediately dictates whether
case 1 or 2 holds. In order to determine whether the A or B case
holds, fz 2 is initially placed at fc,targ , and the loop frequency
response at fc,targ is constructed using the measured frequency
response, and by computing the real and imaginary parts of a Gc
with the specified zeros, and setting Kcomp = 1 for simplicity.
The loop data can then be checked to see whether the phase
margin is low or high with fz 2 = fc,targ . If the phase margin is
high, or within the specified range, then fz 2 must be placed at
or above fc,targ , and case B1 or B2 holds. If the phase margin is
low, then fz 2 must be placed below fc,targ , and case A1 or A2
holds. Details of how fz 2 is iterated are described next.
C. Iterating the Second PID Zero Location
If case B1 or B2 holds, thenthe relevant
expressionin Table I
is evaluated and compared to Hv Gv d ej 2π f c , targ T s in order
to determine whether the integral-based no-limit-cycling criteria
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
Fig. 5. Experimental loop frequency responses. (a) Buck #1. (b) Buck #2. (c) Buck #3. (d) Boost #4. (e) Boost #2. In all plots, the experimental loop frequency
response data (gray dots) are plotted against the loop transfer function obtained using the autotuned PID parameters and a discrete model of the converter (black
line).
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SHIRAZI et al.: AUTOTUNING DIGITAL CONTROLLER FOR DC–DC POWER CONVERTERS
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TABLE III
COMPONENT VALUES
TABLE IV
DISCRETE-TIME CONTROL-TO-OUTPUT TRANSFER FUNCTIONS
D. Computing Kcomp , and Checking Gain Margin and Other
Loop Gain Constraints
Once the PID zeros have been specified, the gain Kcom p is
computed as
Kcomp =
1
.
Hv Gv d (ej 2π f c , targ T s )Gc,K comp =1 (ej 2π f c , targ T s )
(4)
Finally, the entire loop frequency response can be constructed
as
T ej 2π f T s = Hv Gv d ej 2π f T s Gc ej 2π f T s .
can be met at this fc,targ with fz 2 adjusted to meet the phase
margin specification. If the no-limit-cycling criteria cannot be
met, then fc,targ is reduced and the fc,targ loop reiterated. If
the no-limit-cycling criteria can be met, then the maximum
allowed fz 2 is initialized to Fs /2, the minimum allowed fz 2
initialized to fc,targ , and fz 2 itself initialized to the maximum
value. The phase margin is checked at each value of fz 2 , and
fz 2 is adjusted as necessary to increase or decrease the phase
margin. If the phase margin matches the specification, or if
the phase margin is high, but fz 2 is saturated at its maximum
allowed value, then the algorithm proceeds to compute Kcomp .
If the phase margin is low or high, but fz 2 has not saturated, then
fz 2 is iterated using the bisection method. If the phase margin is
high, then the minimum allowed fz 2 is set equal to the current
fz 2 , and if the phase margin is low, then the maximum allowed
fz 2 is set equal to the current fz 2 . The next fz 2 is computed as
fz 2 ,next = (fz 2 ,max + fz 2 ,min )/2.
If case A1 or A2 holds, the relevant expression in Table I is
evaluated and the maximum allowed fz 2 is initialized to this
value. The minimum allowed fz 2 is initialized at (1/64)Fs , and
fz 2 is itself initialized to the minimum value. If the phase margin
is low with fz 2 placed at this minimum value, then there is
no fz 2 location that can meet phase margin specifications. In
this case, fc,targ is reduced and the fc,targ loop reiterated. In
all other cases, fz 2 is iterated, as described previously for the
B cases.
(5)
Gain margin is checked by finding the −180◦ frequency
(where the real part is negative and the imaginary part first becomes positive) and computing the magnitude. The presence of
multiple crossover frequencies is detected by checking whether
the magnitude of the loop frequency response drops below 1
for frequencies less than fc,targ or rises above 1 for frequencies
greater than fc,targ . Insufficient loop gain magnitude at low frequencies is detected by searching for the first −45◦ frequency
(identified by positive real part, negative imaginary part, and
magnitude of the real part becoming greater than the imaginary
part). If this frequency is less than fc,targ , then the loop gain
begins to flatten since the PID includes an integrator. Flattening
of the loop gain at frequencies below the crossover frequency is
undesirable because, for many systems, it results in insufficient
loop gain magnitude at frequencies below fc,targ , which results
in a lower effective closed-loop bandwidth than expected. If
insufficient gain margin, multiple crossover frequencies, or flattening of the low-frequency loop gain is detected, then fc,targ
is reduced and the fc,targ loop reiterated. The only exception is
the case where only the gain margin specification cannot be met
and fz 2 = Fs /2. In this case, the zero z2 is directly set equal to
zero and the specifications are rechecked.
III. EXPERIMENTAL RESULTS
A. Controller Hardware Implementation
In general, the system-identification procedure to compute
the converter frequency responses and the autotuning algorithm
described in Section II could be implemented using a microcontroller or dedicated logic gates. The experimental prototypes described in this paper are based on dedicated logic gate
implementation coded in Verilog on a Xilinx Virtex-IV fieldprogrammable gate array (FPGA) clocked at 25 MHz. Logic
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TABLE V
MEAN VALUES OF AUTOTUNING RESULTS OVER 100 AUTOTUNING REPETITIONS
Fig. 6. Experimental reference steps. (a) Buck #1: 1.5–1.75 V; time: 400 µs/division; ch. 1: output voltage, 250 mV/division, dc coupled; ch. 2: reference step
enable. (b) Buck #2: 1.5–1.75 V; time: 400 µs/division; ch. 1: output voltage, 250 mV/division, dc coupled; ch. 2: reference step enable. (c) Buck #3: 1.5–1.75 V;
time: 400 µs/division; ch. 1: output voltage, 250 mV/division, dc coupled; ch. 2: reference step enable. (d) Boost #1: 30–35 V; time: 400 µs/division; ch. 1: output
voltage, 5.0 V/division, dc coupled; ch. 2: reference step enable. (e) Boost #2: 30–35 V; time: 400 µs/division; ch. 1: output voltage, 5.0 V/division, dc coupled;
ch. 2: reference step enable.
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SHIRAZI et al.: AUTOTUNING DIGITAL CONTROLLER FOR DC–DC POWER CONVERTERS
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Fig. 7. Experimental load steps. (a) Buck #1: 0–9 A; time: 200 µs/division; ch. 1: output voltage, 20 mV/division, ac coupled; ch. 2: load step enable. (b) Buck
#2: 0–9 A; time: 200 µs/division; ch. 1: output voltage, 50 mV/division, ac coupled; ch. 2: load step enable. (c) Buck #3: 0–9 A; time: 400 µs/division; ch. 1: output
voltage, 200 mV/division, ac coupled; ch. 2: load step enable. (d) Boost #1: 0.3–0.6 A; time: 200 µs/division; ch. 1: output voltage, 2.0 V/division, ac coupled; ch.
2: load step enable. (e) Boost #2: 0.3–0.6 A; time: 200 µs/division; ch. 1: output voltage, 1.0 V/division, ac coupled; ch. 2: load step enable.
gate and memory (RAM and ROM) requirements to compute
the frequency response are given in [18]. In particular, for a
PRBS based on a 10-bit shift register, the system-identification
algorithm requires four 1024 × 18-bit RAM blocks to compute and store the frequency response, a 256 × 16-bit ROM
block for the complex exponential lookup table (LUT), and a
512 × 16-bit ROM block for the discrete-zero LUT. The autotuning algorithm shares these memory blocks. The algorithm
accesses the frequency response stored in one RAM pair and
stores the computed loop frequency response in the other RAM
pair. To provide finer tuning, the autotuning algorithm extends
the discrete-zero LUT to 2048 × 16 bits to achieve four times
the frequency resolution of the discrete-zero LUT used by the
system-identification algorithm. In addition, the autotuning algorithm requires a 512 × 24-bit LUT for the imaginary part of
the discrete integrator (the real part is exactly equal to −0.5
for all frequencies except dc). All calculations were performed
using fixed-point arithmetic, and require one unsigned 16 × 16
multiplier, two signed 16 × 16 bit multipliers, and one unsigned
16-bit divider. The multipliers are shared with those used by
the system-identification algorithms, but no effort was made to
share the unsigned 16-bit divider. Resource requirements are
listed in Table II.
B. Autotuning Results
Hardware prototypes for the three buck configurations and
the two boost configurations are shown in Figs. 3 and 4, respectively. Table III lists the component values. In Table III, and
in all the following figures and tables, buck #1, buck #2, and
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buck #3 refer to the well-damped buck, lightly damped buck,
and lightly damped buck with poorly damped input filter, respectively. Similarly, boost #1 and boost #2 refer to the CCM
boost and DCM boost converters, respectively. All converters
are operated at Fs = 195 kHz.
The buck converter prototype uses Vishay Siliconix Si
4888DY MOSFETs. A Texas Instruments THS1230 A/D converter (ADC) samples the output voltage once-per-switching
cycle, 1.08 µs prior to the rising of the trailing-edge DPWM
signal. The THS1230 is a 12-bit ADC, but only 9 bits are
used. The sensing gain is Hv = 1 and the quantization interval is qAD,buck = 7.8 mV. The boost converter prototype uses
a Fairchild Semiconductor NDT3055 JFET and a Fairchild
Semiconductor SS16 Schottky diode. An Analog Devices
AD7822BR ADC samples the output voltage 720 ns prior to the
rising of the trailing-edge DPWM signal. As shown in Fig. 4,
the sensing gain Hv = 12/406 for an effective quantization interval qAD,boost = 262 mV. The DPWM and digital PID were
implemented on the same FPGA as the system-identification and
autotuning algorithms. The DPWM is a 12-bit hybrid DPWM
clocked at 25 MHz. With Fs = 195 kHz and the PRBS generated by a 10-bit shift register, the resolution of the measured
frequency response is ∆f = 191 Hz.
For all autotuning results, the phase margin requirement is
50◦ , the gain margin requirement is 10 dB, and the integral-based
no-limit-cycling safety factor α is set equal to 0.7. Fig. 5(a)–(e)
shows the experimentally computed loop frequency responses
of the well-damped buck, lightly damped buck, lightly damped
buck with poorly damped input filter, CCM boost, and DCM
boost, respectively. These results are compared to plots of the
loop transfer function obtained using the PID coefficients from
the FPGA and a discrete-time model of the converter [22], [23].
For the buck with input filter, the extra-element theorem is
applied to the converter averaged model to obtain an averaged continuous-time model [24], which is then converted to
discrete-time model using the impulse invariant mapping [25].
The discrete-time control-to-output transfer functions for each
of the converters are listed in Table IV as a reference.
The complete system-identification and autotuning procedure
was run 100 times for each converter. Table V gives the mean values of compensator parameters and the mean values of crossover
frequency, stability margins, and integral-based no-limit-cycling
measures, based both on the measured open-loop frequency response, as well as the converter discrete-time model, over the
100 runs.
The standard deviation of the crossover frequencies based on
the analytical Gv d is 0.117, 1.022, 0.020, 0.085, and 0.482 kHz
for the well-damped buck, lightly damped buck, buck with input
filter, CCM boost, and DCM boost, respectively. Table V reveals the bandwidth-limiting specification(s) for each case. The
well-damped buck is limited primarily by the integral-based nolimit-cycling criterion, while the lightly damped buck is limited
both by the no limit cycling and the gain margin constraint. In
both of these cases, although the phase margin itself is near the
specification, the second PID zero has not saturated anywhere
near its lower limit, indicating that the bandwidth could have
been pushed higher if it was not otherwise limited. Further-
TABLE VI
MAXIMUM DURATIONS OF SYSTEM-IDENTIFICATION AND COMPLETE
AUTOTUNING PROCEDURE OVER 100 REPS
more, the bandwidth for the lightly damped tuning is at or near
the maximum allowed Fs /8. Both the buck with poorly damped
input filter and the CCM boost require integral-only control with
very low bandwidths to meet all specifications. In particular, the
phase margin constraint pushes the bandwidth near, but not necessarily below, the converter resonance(s). The bandwidth is
then pushed even lower, to well below the resonances, in order
to avoid multiple crossover frequencies and meet gain margin
constraints. Finally, the DCM boost bandwidth is limited by the
integral-based no-limit-cycling criterion. For the buck with filter, the gain margin computed using the analytical Gv d is much
lower than the gain margin predicted by the tuning algorithm.
This is due to the finite-frequency resolution of the measured
frequency responses coupled with the high Q-factor of the input
filter.
Fig. 6(a)–(e) shows reference steps of 1.5–1.75 V for the buck
converters and 30–35 V for the boost converters. Fig. 7(a)–(e)
shows load steps of 0–9 A for the buck converters and 0.3–0.6 A
for the boost converters. As expected, Fig. 7(c) and (d) shows
that the closed-loop output impedance of the buck with poorly
damped input filter, as well as the CCM boost, share the same
dynamics as the respective open-loop output impedance due to
bandwidth being less than the resonant frequency (or frequencies in the case of the buck with input filter) of the converter.
An additional reason for the large output voltage deviations for
both boost cases is the very small output capacitance of these
prototypes (1.8 µF). The small output capacitance was chosen
to present a challenging tuning case for the CCM boost, i.e., a
case that requires the crossover frequency be pushed to a very
low frequency below the resonant frequency to meet all specifications.
Finally, Table VI shows the maximum duration of system
identification, as well as complete autotuning duration (including system identification), for each converter over 100
repetitions.
IV. CONCLUSION
This paper has described a hardware description language
(HDL) coded autotuning algorithm for digital PID controlled
dc–dc power converters based on online identification of
control-to-output frequency response. The algorithm determines the PID controller parameters required to maximize the
closed-loop bandwidth of the feedback control system while
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SHIRAZI et al.: AUTOTUNING DIGITAL CONTROLLER FOR DC–DC POWER CONVERTERS
maintaining user-specified stability margins and integral-based
no-limit-cycling criteria, as well as ensuring single-crossoverfrequency operation and sufficiently high loop gain magnitude at
low frequencies. The combined Verilog-coded implementation
of the identification and self-tuning algorithms requires 84000
logic gates and 15 kB of memory.
Versatility of the proposed autotuning method was demonstrated by applications to several experimental prototypes. The
exact same identification and tuning algorithms are able to
successfully tune, in 350 ms or less, five different digitally
controlled PWM dc–dc converters, including a well-damped
synchronous buck, lightly damped synchronous buck, lightly
damped synchronous buck with a poorly damped input filter, CCM boost, and DCM boost, covering a representative
range of dynamics commonly encountered in dc–dc power
converters: well-damped second-order system, lightly damped
second-order system, fourth-order system with a lightly damped
plus a nearly undamped resonance, non-minimum-phase
lightly-damped second-order system and first order system,
respectively.
Compared to alternative autotuning or adaptive tuning approaches, advantages of the proposed method include the
ability to take into account multiple design criteria: stability
margin specifications, no-limit-cycle criteria, single-crossoverfrequency operation, and sufficiently large low-frequency loop
gain magnitude, which can be ensured without requiring specific a priori information regarding converter power stages. On
the other hand, it is also clear that adequate stability margins
must still be maintained to account for the expected variation in measured frequency response due to A/D quantization
noise. Furthermore, the disruption of normal operation during frequency-response identification prohibits this technique
from continuously running, and thus, from being able to easily track system dynamics that change over time. In contrast,
the MRAC techniques of [4]–[6] are not only better suited
to tracking system dynamics over time, but they also enjoy
greater signal-to-noise ratios, and generally lead to simpler
implementations.
The autotuning and adaptive control schemes are indeed complementary. If sufficient a priori knowledge were already available, an adaptive only control scheme would suffice. If changes
in system dynamics could be detected, allowing retriggering of
the autotuning procedure, an autotuning-only control scheme
could be implemented. But, in the most general case, they could
be used in combination. In this case, the autotuning algorithm
executes upon converter start-up to initialize the controller, and
provide the necessary a priori information regarding converter
dynamics and achievable bandwidth/phase margin constraints
to the adaptive algorithm, which can then take over to fine tune
the controller and adapt to changes in system dynamics.
APPENDIX
DERIVATION OF THE INTEGRAL-BASED NO-LIMIT-CYCLING
EXPRESSIONS OF TABLE I
The results of Table I are derived by first converting (3) into an
expression for the maximum allowed 0-dB crossing frequency
2587
TABLE VII
G c (ej 2 π f c , targ T s ) BASED ON BODE STRAIGHT-LINE ASYMPTOTES
of the integral asymptote of the PID. At very low frequencies,
the PID behaves like an integrator whose magnitude response
crosses 0 dB at fk
Ki
Ki
Ki
(6)
1 − ej 2π f k T s ≈ 2πfk Ts = 1 ⇒ fk = 2π Fs .
The fk frequency is still relevant even if the magnitude response of the actual PID never reaches 0 dB due to large integral
gain and/or low placement of the first PID zero—in this case,
fk is the projected 0-dB crossing of the integral asymptote.
However, for such a high-gain PID, it is possible that the approximation made in (6), which holds only for fk Fs , may no
longer be valid. Fortunately, the whole point of implementing
these constraints is to prevent fk from being too large, i.e., the
assumption is made that fk Fs and the resulting constraints
on PID zero locations will ensure that the assumption holds.
The constraint in (3) can now be expressed as
fk <
α
Fs .
2πHv Gv d0
(7)
Knowing that fk and fz 1 both lie on a −20-dB/decade asymptote, with magnitude equal to 0 dB at fk (whether or not the
asymptotes of the complete PID pass through this point) allows
the construction of approximate expressions, based on Bode
straight-line asymptotes, for the magnitude of the PID controller
Gc (ej 2π f c , targ T s ) in terms of fk , fc,targ , fz 1 , and fz 2 . It can
be shown that the resulting expressions, shown in Table VII,
hold no matter what the relationship of fk to fc,targ , fz 1 , and
fz 2 . The expressions of Table VII will be used here to illustrate
the concept; in practice, however, appropriate scaling factors are
applied to account for the deviation of the exact magnitude plots
from the asymptotes at and near the locations of the zeros.
The expressions of Table VII, along with the required inequality of (7), impose design constraints when inserted into
the defining equation for crossover frequency
Hv Gv d ej 2π f c , targ T s Gc ej 2π f c , targ T s = 1. (8)
For the B1 and B2 cases, where fz 2 ≥ fc,targ , these constraints
are in the formof a minimum allowed magnitude
of Hv Gv d ej 2π f c , targ T s . For the A1 and A2 cases, where
fz 2 < fc,targ , these constraints are in the form of a maximum
allowed frequency for fz 2 . Table I lists the results.
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Mariko Shirazi (S’09) received the B.S. degree
in mechanical engineering from the University of
Alaska, Fairbanks, in 1996, and the M.S. degree in
electrical engineering in 2007 from the University of
Colorado, Boulder, where she is currently working
toward the Ph.D. degree in electrical engineering.
From 1996 to 2004, she was an Engineer at the National Wind Technology Center, National Renewable
Energy Laboratory, where she was involved in the
design and deployment of hybrid wind-diesel power
systems for village power applications. Her current
research interests include system identification and autotuning of digitally controlled switched-mode power supplies.
Regan Zane (S’98–M’00–SM’07) received the B.S,
M.S., and Ph.D. degrees in electrical engineering
from the University of Colorado, Boulder, in 1996,
1998, and 1999, respectively.
From 1999 to 2001, he was with the GE Global Research Center, Niskayuna, NY, where he developed
custom IC controllers for power electronic circuits
and systems. From 2001 to 2007, he was an Assistant Professor of electrical and computer engineering
at the University of Colorado, where he has been an
Associate Professor since 2008. He is engaged in research programs in energy-efficient lighting systems, adaptive algorithms and
digital control techniques in power electronics systems, and low power energy
harvesting for wireless devices.
Dr. Zane received the 2004 National Science Foundation CAREER Award,
the 2005 IEEE Microwave Best Paper Prize, the 2008 IEEE POWER ELECTRONICS SOCIETY (PELS) TRANSACTIONS Prize Letter Award, and the 2008 IEEE
PELS Richard M. Bass Outstanding Young Power Electronics Engineer Award.
He received the 2006 Inventor of the Year award, the 2006 Provost Faculty
Achievement Award, and the 2008 John and Mercedes Peebles Innovation in
Teaching Award, all from the University of Colorado. He is currently an Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS LETTERS
and a Member-At-Large of the IEEE PELS AdCom.
Dragan Maksimovic (M’89–SM’04) received the
B.S. and M.S. degrees in electrical engineering from
the University of Belgrade, Belgrade, Yugoslavia, in
1984 and 1986, respectively, and the Ph.D. degree
from California Institute of Technology, Pasadena, in
1989.
From 1989 to 1992, he was with the University of
Belgrade. Since 1992, he has been with the Department of Electrical and Computer Engineering, University of Colorado, Boulder, where he is currently
a Professor and the Director of the Colorado Power
Electronics Center. His research interests include digital control techniques and
mixed-signal IC design for power electronics.
Prof. Maksimovic received the National Science Foundation CAREER
Award in 1997, the IEEE POWER ELECTRONICS SOCIETY TRANSACTIONS Prize
Paper Award in 1997, the Bruce Holland Excellence in Teaching Award in 2004,
and the University of Colorado Inventor of the Year Award in 2006.
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