datasheet for EN29LV160C by Eon Silicon Solution

datasheet for EN29LV160C by Eon Silicon Solution
EN29LV160C
EN29LV160C
16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
• 3.0V, single power supply operation
- Minimizes system level power requirements
• High performance
- Access times as fast as 70 ns
• Low power consumption (typical values at 5
MHz)
- 9 mA typical active read current
- 20 mA typical program/erase current
- Less than 1 μA current in standby or automatic
sleep mode.
• Flexible Sector Architecture:
- One 16-Kbyte, two 8-Kbyte, one 32-Kbyte,
and thirty-one 64-Kbyte sectors (byte mode)
- One 8-Kword, two 4-Kword, one 16-Kword
and thirty-one 32-Kword sectors (word mode)
• Sector protection :
- Hardware locking of sectors to prevent
program or erase operations within individual
sectors
- Additionally, temporary Sector Group
Unprotect allows code changes in previously
locked sectors.
• Secured Silicon Sector
- Provides a 128-words area for code or data
that can be permanently protected.
- Once this sector is protected, it is prohibited
to program or erase within the sector again.
•
-
High performance program/erase speed
Byte/Word program time: 8µs typical
Sector erase time: 100ms typical
Chip erase time: 4s typical
• JEDEC Standard program and erase
commands
• JEDEC standard DATA# polling and toggle
bits feature
• Single Sector and Chip Erase
• Sector Unprotect Mode
• Embedded Erase and Program Algorithms
• Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
• Support JEDEC Common Flash Interface
(CFI)
• Triple-metal double-poly triple-well CMOS
Flash Technology
• Low Vcc write inhibit < 2.5V
• minimum 100K program/erase endurance
cycle
•
-
Package Options
48-pin TSOP (Type 1)
48 ball 6mm x 8mm TFBGA
48-ball 4mm x 6mm WFBGA
• Industrial Temperature Range
GENERAL DESCRIPTION
The EN29LV160C is a 16-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 2,097,152 bytes or 1,048,576 words. Any byte can be programmed typically in 8µs. The
EN29LV160C features 3.0V voltage read and write operation, with access times as fast as 70ns to
eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29LV160C has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)
controls, which eliminate bus contention issues. This device is designed to allow either single Sector or
full chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K
program/erase cycles on each Sector.
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
1
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard
TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
48-Ball TFBGA
Top View, Balls Facing Down
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
2
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
WFBGA
Top View, Balls Facing Down
A6
A2
A5
A1
A4
A0
A3
CE#
A2
VSS
B6
A4
B5
A3
B4
A5
B3
DQ8
B2
OE#
B1
DQ0
C6
A6
C5
A7
D6
A17
E6
NC
F6
NC
G6
WE#
H6
Reset#
H5
D5
WP
NC
#/A
NC
C4
DQ1
A10
J3
DQ10
C1
J5
A8
C3
DQ9
A9
J4
A18
C2
J6
DQ4
H2
D2
NC
A19
D1
DQ2
E1
DQ3
F1
VDD
G1
DQ12
H1
DQ13
J2
DQ5
J1
DQ14
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
3
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
K6
A11
K5
A13
K4
A12
K3
DQ11
K2
DQ6
K1
DQ15
L5
A14
L4
A15
L3
A16
L2
DQ7
L1
VSS
www.eonssi.com
EN29LV160C
TABLE 1. PIN DESCRIPTION
Pin Name
A0-A19
FIGURE 1. LOGIC DIAGRAM
EN29LV160C
Function
20 Addresses
DQ0 – DQ15
(A-1)
A0 – A19
DQ0-DQ14
15 Data Inputs/Outputs
DQ15 / A-1
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
Reset#
CE#
Chip Enable
OE#
OE#
Output Enable
WE#
RESET#
Hardware Reset Pin
RY/BY#
Ready/Busy Output
WE#
Write Enable
Vcc
Supply Voltage
(2.7-3.6V)
Vss
Ground
NC
Not Connected to anything
BYTE#
Byte/Word Mode
CE#
RY/BY#
Byte#
Note:
RY/BY# and BYTE# are not supported on 48-ball 4mm x 6mm WFBGA package.
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
4
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
Table 2A. Top Boot Sector Address Tables (EN29LV160CT)
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
64/32
Byte mode (x8)
000000–00FFFF
Word Mode
(x16)
00000–07FFF
64/32
010000–01FFFF
08000–0FFFF
X
64/32
020000–02FFFF
10000–17FFF
X
X
64/32
030000–03FFFF
18000–1FFFF
X
X
64/32
040000–04FFFF
20000–27FFF
X
X
X
64/32
050000–05FFFF
28000–2FFFF
X
X
X
64/32
060000–06FFFF
30000–37FFF
1
X
X
X
64/32
070000–07FFFF
38000–3FFFF
0
X
X
X
64/32
080000–08FFFF
40000–47FFF
0
1
X
X
X
64/32
090000–09FFFF
48000–4FFFF
0
1
0
X
X
X
64/32
0A0000–0AFFFF
50000–57FFF
0
1
1
X
X
X
64/32
0B0000–0BFFFF
58000–5FFFF
1
1
0
0
X
X
X
64/32
0C0000–0CFFFF
60000–67FFF
1
1
0
1
X
X
X
64/32
0D0000–0DFFFF
68000–6FFFF
0
1
1
1
0
X
X
X
64/32
0E0000–0EFFFF
70000–77FFF
SA15
0
1
1
1
1
X
X
X
64/32
0F0000–0FFFFF
78000–7FFFF
SA16
1
0
0
0
0
X
X
X
64/32
100000–10FFFF
80000–87FFF
SA17
1
0
0
0
1
X
X
X
64/32
110000–11FFFF
88000–8FFFF
SA18
1
0
0
1
0
X
X
X
64/32
120000–12FFFF
90000–97FFF
SA19
1
0
0
1
1
X
X
X
64/32
130000–13FFFF
98000–9FFFF
SA20
1
0
1
0
0
X
X
X
64/32
140000–14FFFF
A0000–A7FFF
SA21
1
0
1
0
1
X
X
X
64/32
150000–15FFFF
A8000–AFFFF
SA22
1
0
1
1
0
X
X
X
64/32
160000–16FFFF
B0000–B7FFF
SA23
1
0
1
1
1
X
X
X
64/32
170000–17FFFF
B8000–BFFFF
SA24
1
1
0
0
0
X
X
X
64/32
180000–18FFFF
C0000–C7FFF
SA25
1
1
0
0
1
X
X
X
64/32
190000–19FFFF
C8000–CFFFF
SA26
1
1
0
1
0
X
X
X
64/32
1A0000–1AFFFF
D0000–D7FFF
SA27
1
1
0
1
1
X
X
X
64/32
1B0000–1BFFFF
D8000–DFFFF
SA28
1
1
1
0
0
X
X
X
64/32
1C0000–1CFFFF
E0000–E7FFF
SA29
1
1
1
0
1
X
X
X
64/32
1D0000–1DFFFF
E8000–EFFFF
SA30
1
1
1
1
0
X
X
X
64/32
1E0000–1EFFFF
F0000–F7FFF
Sector
SA0
A19
0
A18
0
A17
0
A16
0
A15
0
A14
X
A13
X
A12
X
SA1
0
0
0
0
1
X
X
X
SA2
0
0
0
1
0
X
X
SA3
0
0
0
1
1
X
SA4
0
0
1
0
0
X
SA5
0
0
1
0
1
SA6
0
0
1
1
0
SA7
0
0
1
1
SA8
0
1
0
0
SA9
0
1
0
SA10
0
1
SA11
0
1
SA12
0
SA13
0
SA14
SA31
1
1
1
1
1
0
X
X
32/16
1F0000–1F7FFF
F8000–FBFFF
SA32
1
1
1
1
1
1
0
0
8/4
1F8000–1F9FFF
FC000–FCFFF
SA33
1
1
1
1
1
1
0
1
8/4
1FA000–1FBFFF
FD000–FDFFF
SA34
1
1
1
1
1
1
1
X
16/8
1FC000–1FFFFF
FE000–FFFFF
Table 2B. Top Boot Security Sector Address (EN29LV160CT)
Sector Address
A19 ~ A12
Sector Size
(bytes / words)
Address Range (h)
Byte mode (x8)
Address Range (h)
Word Mode (x16)
11111111
256 / 128
1FFF00–1FFFFF
0FFF80–0FFFFF
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
5
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
Table 2C. Bottom Boot Sector Address Tables (EN29LV160CB)
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
16/8
Byte mode (x8)
000000–003FFF
Word Mode
(x16)
00000–01FFF
8/4
004000–005FFF
02000–02FFF
Sector
SA0
A19
0
A18
0
A17
0
A16
0
A15
0
A14
0
A13
0
A12
X
SA1
0
0
0
0
0
0
1
0
SA2
0
0
0
0
0
0
1
1
8/4
006000–007FFF
03000–03FFF
SA3
0
0
0
0
0
1
X
X
32/16
008000–00FFFF
04000–07FFF
SA4
0
0
0
0
1
X
X
X
64/32
010000–01FFFF
08000–0FFFF
SA5
0
0
0
1
0
X
X
X
64/32
020000–02FFFF
10000–17FFF
SA6
0
0
0
1
1
X
X
X
64/32
030000–03FFFF
18000–1FFFF
SA7
0
0
1
0
0
X
X
X
64/32
040000–04FFFF
20000–27FFF
SA8
0
0
1
0
1
X
X
X
64/32
050000–05FFFF
28000–2FFFF
SA9
0
0
1
1
0
X
X
X
64/32
060000–06FFFF
30000–37FFF
SA10
0
0
1
1
1
X
X
X
64/32
070000–07FFFF
38000–3FFFF
SA11
0
1
0
0
0
X
X
X
64/32
080000–08FFFF
40000–47FFF
SA12
0
1
0
0
1
X
X
X
64/32
090000–09FFFF
48000–4FFFF
SA13
0
1
0
1
0
X
X
X
64/32
0A0000–0AFFFF
50000–57FFF
SA14
0
1
0
1
1
X
X
X
64/32
0B0000–0BFFFF
SA15
0
1
1
0
0
X
X
X
64/32
0C0000–0CFFFF
58000–5FFFF
60000–67FFF
SA16
0
1
1
0
1
X
X
X
64/32
0D0000–0DFFFF
68000–6FFFF
SA17
0
1
1
1
0
X
X
X
64/32
0E0000–0EFFFF
70000–77FFF
SA18
0
1
1
1
1
X
X
X
64/32
0F0000–0FFFFF
78000–7FFFF
SA19
1
0
0
0
0
X
X
X
64/32
100000–10FFFF
80000–87FFF
SA20
1
0
0
0
1
X
X
X
64/32
110000–11FFFF
88000–8FFFF
SA21
1
0
0
1
0
X
X
X
64/32
120000–12FFFF
90000–97FFF
SA22
1
0
0
1
1
X
X
X
64/32
130000–13FFFF
98000–9FFFF
SA23
1
0
1
0
0
X
X
X
64/32
140000–14FFFF
A0000–A7FFF
SA24
1
0
1
0
1
X
X
X
64/32
150000–15FFFF
A8000–AFFFF
SA25
1
0
1
1
0
X
X
X
64/32
160000–16FFFF
B0000–B7FFF
SA26
1
0
1
1
1
X
X
X
64/32
170000–17FFFF
B8000–BFFFF
SA27
1
1
0
0
0
X
X
X
64/32
180000–18FFFF
C0000–C7FFF
SA28
1
1
0
0
1
X
X
X
64/32
190000–19FFFF
C8000–CFFFF
SA29
1
1
0
1
0
X
X
X
64/32
1A0000–1AFFFF
D0000–D7FFF
SA30
1
1
0
1
1
X
X
X
64/32
1B0000–1BFFFF
D8000–DFFFF
SA31
1
1
1
0
0
X
X
X
64/32
1C0000–1CFFFF
E0000–E7FFF
SA32
1
1
1
0
1
X
X
X
64/32
1D0000–1DFFFF
E8000–EFFFF
SA33
1
1
1
1
0
X
X
X
64/32
1E0000–1EFFFF
F0000–F7FFF
SA34
1
1
1
1
1
X
X
X
64/32
1F0000–1FFFFF
F8000–FFFFF
Table 2D. Bottom Boot Security Sector Address (EN29LV160CB)
Sector Address
A19 ~ A12
Sector Size
(bytes / words)
Address Range (h)
Byte mode (x8)
Address Range (h)
Word Mode (x16)
00000000
256 / 128
000000–0000FF
000000–00007F
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
6
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
PRODUCT SELECTOR GUIDE
Product Number
EN29LV160C
Speed
-70
Max Access Time, ns (tacc)
70
Max CE# Access, ns (tce)
70
Max OE# Access, ns (toe)
30
BLOCK DIAGRAM
RY/BY#
Vcc
Vss
DQ0-DQ15 (A-1)
Block Protect Switches
Erase Voltage Generator
Input/Output Buffers
State
Control
WE#
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
Vcc Detector
Timer
Address Latch
STB
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A19
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
7
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
TABLE 3. OPERATING MODES
16M FLASH USER MODE TABLE
Operation
Read
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary
Sector Unprotect
CE#
L
L
Vcc 0.3V
H
L
X
OE#
L
H
X
X
H
X
WE#
H
L
X
X
H
X
Reset#
H
H
Vcc 0.3V
H
H
L
A0A19
AIN
AIN
X
X
X
X
X
X
X
VID
AIN
Notes:
L=logic low= VIL, H=Logic High= VIH, VID = 9
DQ0-DQ7
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
DQ8-DQ15
Byte#
Byte#
= VIL
= VIH
DOUT
High-Z
DIN
High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
DIN
DIN
X
0.5V, X=Don’t Care (either L or H, but not floating!),
DIN=Data In, DOUT=Data Out, AIN=Address In
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
8
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
TABLE 4. Autoselect Codes (Using High Voltage, VID)
16M FLASH MANUFACTURER/DEVICE ID TABLE
Description
CE#
OE#
WE#
L
H
A19
to
A12
A11
to
A10
A9
X
VID
2
A8
A7
A6
A5
to
A2
A1
A0
X
L
X
L
L
DQ8
to
DQ15
DQ7
to
DQ0
L
Manufacturer ID:
Eon
L
Device
ID
Word
L
(top boot
block)
Byte
L
L
H
Device
ID
Word
L
L
H
(bottom
boot
block)
Byte
X
1
7FH
X
H
L
1CH
H
X
X
L
L
H
L
L
H
X
VID
X
X
X
VID
X
X
L
L
X
L
X
22h
C4H
X
C4H
22h
49H
X
49H
H
L
H
X
Sector Protection
Verification
SA
X
VID
X
X
L
X
H
L
X
01h
(Protected)
00h
(Unprotected)
16M FLASH SECURED SILICON SECTOR TABLE3
Description
CE#
OE#
WE#
A21
to
A12
A11
to
A10
A9
2
P
P
A8
A7
A6
A5
to
A2
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
Secured Silicon
X
X
V ID
X
X
L
X
H
L
X
X
L
V ID
4
Sector Lock
Secured Silicon
X1h
Sector Lock Bit
(Locked)
L
L
H
X
X
V ID
X
X
L
X
H
L
X
Verification
X0h
4
(DQ0)
(Unlocked)
L=logic low= VIL, H=Logic High= VIH, VID = 9 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector
Addresses
Note:
1. A8 = H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output
a configuration code 7Fh.
2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect
Mode.
3. 16M FLASH SECURED SILICON SECTOR TABLE is valid only in Secured Silicon Sector.
4.
AC Waveform for Secured Silicon Sector Lock / Verification Operations Timings
VID
B
B
B
B
B
B
Vcc
0V
0V
tVIDR
tVIDR
A6, A1, A0
Valid
Valid
Valid
Valid
Verify
>0.4 s
>1 s
Lock : 150 s
VID
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
9
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
USER MODE DEFINITIONS
Word / Byte Configuration
The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the
byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word
configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.
On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only
data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are
tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The EN29LV160C has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical).
It is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.5. RESET# and BYTE# pin
must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which
reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin
is at VIH. When in standby modes, the outputs are in a high-impedance state independent of the OE#
input.
Automatic Sleep Mode
The EN29LV160C has an automatic sleep mode, which minimizes power consumption. The devices
will enter this mode automatically when the states of address bus remain stable for tacc + 30ns. ICC5
in the DC Characteristics table shows the current specification. With standard access times, the
device will output new data when addresses change.
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required
to retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See “Erase Suspend/Erase Resume Commands” for more additional information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset Command” additional details.
Output Disable Mode
When the CE# or OE# pin is at a logic high level (VIH), the output from the EN29LV160C is disabled.
The output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VID (8.5 V to 9.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when
verifying sector protection, the sector address must appear on the appropriate highest order address
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EN29LV160C
bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the
remaining address bits that are don’t-care. When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ15–DQ0.
To access the autoselect codes in-system; the host system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
“Command Definitions” for details on using the autoselect mode.
Write Mode
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up command. The program address and data are
written next, which in turn initiate the Embedded Program algorithm. The system is not required to
provide further controls or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. The Command Definitions in Table 5 show the
address and data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and
addresses are no longer latched. The system can determine the status of the program operation by
using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be
programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”,
or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding
read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously
protected sectors.
There are two methods to enabling this hardware protection circuitry. The first one requires only that
the RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable
this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.
When doing Sector Unprotect, all the other sectors should be protected first.
The second method is meant for programming equipment. This method requires VID be applied to
both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in
a separate document called EN29LV160C Supplement, which can be obtained by contacting a
representative of Eon Silicon Solution, Inc.
Temporary Sector Unprotect
Start
This feature allows temporary unprotection of previously protected
sector groups to change data while in-system. The Sector
Unprotect mode is activated by setting the RESET# pin to VID.
During this mode, formerly protected sectors can be programmed
or erased by simply selecting the sector addresses. Once is
removed from the RESET# pin, all the previously protected sectors
are protected again.
See accompanying figure and timing
diagrams for more details.
Notes:
1. All protected sectors unprotected.
2. Previously protected sectors protected
again.
Reset#=VID (note 1)
Perform Erase or Program
Operations
Reset#=VIH
Temporary Sector
Unprotect Completed (note 2)
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or modifications due to changes in technical specifications.
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EN29LV160C
COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their
existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array
data.
The system can read CFI information at the addresses given in Tables 5-8. In word mode, the upper
address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The
device enters the CFI query mode and the system can read CFI data at the addresses given in Tables
5–8. The system must write the reset command to return the device to the autoselect mode.
Table 5. CFI Query Identification String
Adresses
(Word Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
Adresses
(Byte Mode)
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
Addresses
(Word Mode)
Addresses
(Byte Mode)
1Bh
36h
0027h
1Ch
38h
0036h
1Dh
1Eh
1Fh
3Ah
3Ch
3Eh
0000h
0000h
0004h
20h
40h
0000h
21h
22h
23h
24h
25h
42h
44h
46h
48h
4Ah
000Ah
0000h
0005h
0000h
0004h
26h
4Ch
0000h
Data
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists
Table 6. System Interface String
Data
Description
Vcc Min (write/erase)
D7-D4: volt, D3 –D0: 100 millivolt
Vcc Max (write/erase)
D7-D4: volt, D3 –D0: 100 millivolt
Vpp Min. voltage (00h = no Vpp pin present)
Vpp Max. voltage (00h = no Vpp pin present)
Typical timeout per single byte/word write 2^N s
Typical timeout for Min, size buffer write 2^N s (00h = not
supported)
Typical timeout per individual block erase 2^N ms
Typical timeout for full chip erase 2^N ms (00h = not supported)
Max. timeout for byte/word write 2^N times typical
Max. timeout for buffer write 2^N times typical
Max. timeout per individual block erase 2^N times typical
Max timeout for full chip erase 2^N times typical (00h = not
supported)
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or modifications due to changes in technical specifications.
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EN29LV160C
Table 7. Device Geometry Definition
Addresses
(Word mode)
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
Addresses
(Byte Mode)
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
Data
0015h
0002h
0000h
0000h
0000h
0004h
0000h
0000h
0040h
0000h
0001h
0000h
0020h
0000h
0000h
0000h
0080h
0000h
001Eh
0000h
0000h
0001h
Description
Device Size = 2^N byte
Flash Device Interface description (refer to CFI publication
100)
Max. number of byte in multi-byte write = 2^N
(00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification of CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Table 8. Primary Vendor-specific Extended Query
Addresses
(Word Mode)
40h
41h
42h
43h
44h
Addresses
(Byte Mode)
80h
82h
84h
86h
88h
Data
0050h
0052h
0049h
0031h
0030h
45h
8Ah
0000h
46h
8Ch
0002h
47h
8Eh
0001h
48h
90h
0001h
49h
92h
0004h
4Ah
94h
0000h
4Bh
96h
0000h
4Ch
98h
0000h
Description
Query-unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
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EN29LV160C
Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
SECURED SILICON SECTOR
The EN29LV160C features an OTP memory region where the system may access through a command
sequence to create a permanent part identification as so called Electronic Serial Number (ESN) in the
device. Once this region is programmed and then locked by writing the Secured Silicon Sector Lock
command (refer to Table 4 on page 9), any further modification in the region is impossible. The secured
silicon sector is 128 words in length, and the Secured Silicon Sector Lock Bit (DQ0) is used to indicate
whether the Secured Silicon Sector is locked or not.
The system accesses the Secured Silicon Sector through a command sequence (refer to “Enter
Secured Silicon/ Exit Secured Silicon Sector command Sequence which are in Table 9 on page 15).
After the system has written the Enter Secured Silicon Sector command sequence, it may read the
Secured Silicon Sector by using the address normally occupied by the last sector SA34 (for
EN29LV160CT) or first sector SA0 (for EN29LV160CB). Once entry the Secured Silicon Sector the
operation of boot sectors and main sectors are disabled, the system must write Exit Secured Silicon
Sector command sequence to return to read and write within the remainder of the array. This mode of
operation continues until the system issues the Exit Secured Silicon Sector command sequence, or
until power is removed from the device. On power-up, or following a hardware reset, the device reverts
to sending command to sector SA0.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
VLKO.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write
cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all
logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with
CE# = VIL, WE#= VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#.
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EN29LV160C
COMMAND DEFINITIONS
The operations of the EN29LV160C are selected by one or more commands written into the command
register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase,
Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at
specific addresses via the command register. The sequences for the specified operation are defined in
the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper
sequences will reset the device to Read Mode.
Table 9. EN29LV160C Command Definitions
Cycles
Bus Cycles
Command
Sequence
Read
Reset
Autoselect
Manufacturer
ID
1
1
Word
Device ID
Bottom Boot
Word
Program
Chip Erase
Sector Erase
Enter Secured
Silicon Sector
Exit Secured
Silicon Sector
4
555
Write Cycle
Add
Data
2AA
555
2AA
555
2AA
555
55
555
AAA
10
55
SA
30
55
555
AA
AA
2AA
555
2AA
90
AAA
55
55
555
AAA
555
555
AAA
Word
555
2AA
555
4
Word
Byte
Word
Byte
Word
Byte
6
6
1
1
Word
Byte
Word
Byte
Word
Byte
AA
AAA
4
1
3
4
555
AAA
555
AAA
555
AAA
xxx
xxx
55
AA
555
AAA
555
AAA
th
6
Write Cycle
Add
Data
AAA
Byte
th
5
Write Cycle
Add
Data
AA
555
AAA
th
4
Write Cycle
Add
Data
RD
F0
AAA
4
rd
3
Write Cycle
Add
Data
Byte
Erase Suspend
Erase Resume
CFI Query
RA
xxx
4
Word
Byte
nd
2
555
Byte
Device ID
Top Boot
Sector Protect
Verify
st
1
Write Cycle
Add
Data
55
555
AA
AA
AA
2AA
555
2AA
555
2AA
555
90
90
90
AAA
55
55
55
555
AAA
555
AAA
555
AAA
A0
80
80
000
100
000
200
x01
x02
7F
1C
7F
1C
x01
2249
x02
(SA)
X02
49
XX00
XX01
00
01
08
(SA)
X04
PA
555
AAA
555
AAA
22C4
C4
PD
AA
AA
B0
30
98
AA
AA
2AA
555
2AA
555
55
55
555
AAA
555
AAA
88
90
xxx
xxx
00
00
Address and Data values indicated in hex
RA = Read Address: address of the memory location to be read. This is a read cycle.
RD = Read Data: data read from location RA during Read operation. This is a read cycle.
PA = Program Address: address of the memory location to be programmed. X = Don’t-Care
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased or verified. Address bits A19-A12 uniquely select any
Sector.
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EN29LV160C
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array
data using the standard read timings, with the only difference in that if it reads at an address within
erase suspended sectors, the device outputs status data. After completing a programming operation in
the Erase Suspend mode, the system may once again read array data with the same exception.
The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See next section for details on Reset.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’tcare for this command.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is complete. The reset command may be written
between the sequence cycles in a program command sequence before programming begins. This
resets the device to reading array data (also applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices
codes, and determine whether or not a sector is protected. The Command Definitions table shows the
address and data requirements. This is an alternative to the method that requires VID on address bit A9
and is intended for PROM programmers.
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.
Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number
of times, without needing another command sequence.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Word / Byte Programming Command
The device can be programmed by byte or by word, depending on the state of the Byte# Pin.
Programming the EN29LV160C is performed by using a four-bus-cycle operation (two unlock write
cycles followed by the Program Setup command and Program Data Write cycle). When the program
command is executed, no additional CPU controls or timings are necessary. An internal timer
terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#,
whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.
Programming status can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit).
When the program operation is successfully completed, the device returns to read mode and the user
can read the data programmed to the device at that address. Note that data can not be programmed
from a “0” to a “1”. Only an erase operation can change a data from “0” to “1”. When programming time
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EN29LV160C
limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read
mode.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not
require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and addresses are no longer latched.
Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables
in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing
waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing
two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed
by the address of the sector to be erased, and the sector erase command. The Command Definitions
table shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by using
DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4
illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the
“AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for
timing waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. This command is valid only during
the sector erase operation. The Erase Suspend command is ignored if written during the chip erase
operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase
Suspend command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation
Status” for information on these status bits.
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EN29LV160C
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for
more information. The Autoselect command is not supported during Erase Suspend Mode.
The system must write the Erase Resume command (address bits are don’t-care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command are
ignored. Another Erase Suspend command can be written after the device has resumed erasing.
WRITE OPERATION STATUS
DQ7
DATA# Polling
The EN29LV160C provides DATA# polling on DQ7 to indicate the status of the embedded operations.
The DATA# polling feature is active during Byte Programming, Sector Erase, Chip Erase, and Erase
Suspend. (See Table 10)
When the embedded Programming is in progress, an attempt to read the device will produce the
complement of the data written to DQ7. Upon the completion of the Byte Programming, an attempt to
read the device will produce the true data written to DQ7. For the Byte Programming, DATA# polling is
valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7
output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output
during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE#
or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of the WE# or
CE# pulse for chip erase or sector erase.
DATA# Polling must be performed at any address within a sector that is being programmed or erased
and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used
is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable (OE#) is low. This means that the device is driving status information on DQ7 at one
instant of time and valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data
on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing
diagram is shown in Figure 8.
RY/BY#: Ready/Busy
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together
in parallel with a pull-up resistor to Vcc.
In the output-low period, signifying Busy, the device is actively erasing or programming. This includes
programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is
ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
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EN29LV160C
DQ6
Toggle Bit I
The EN29LV160C provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming
and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device at
any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the
embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read
on the next successive attempts. During embedded Programming, the Toggle Bit is valid after the rising
edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid
after the rising edge of the sixth WE# pulse for sector erase or chip erase.
In embedded Programming, if the sector being written to is protected, DQ6 will toggles for about 2 μs,
then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected sectors are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read
mode without changing data in all protected sectors.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown
in Figure 9.
DQ5 Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or
erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the
device has successfully completed its operation and has returned to read mode, the user must check
again to see if the DQ6 is toggling after detecting a “1” on DQ5.
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition,
the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a
“1.” Under both these conditions, the system must issue the reset command to return the device to
reading array data.
DQ3 Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be used to determine whether
or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) When sector erase starts, DQ3 switches from “0” to “1.” This device does not support
multiple sector erase command sequences so it is not very meaningful since it immediately shows as a
“1” after the first 30h command. Future devices may support this feature.
DQ2 Erase Toggle Bit II
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2
toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 5 to
compare outputs for DQ2 and DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical
form.
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
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EN29LV160C
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle
bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive
read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose
to perform other system tasks. In this case, the system must start at the beginning of the algorithm
when it returns to determine the status of the operation (top of Flowchart 6).
Write Operation Status
Standar
d Mode
Erase
Suspend
Mode
Operation
DQ7
DQ6
DQ5
DQ3
DQ2
RY/BY#
Embedded Program
Algorithm
DQ7#
Toggle
0
N/A
No
toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
1
No
Toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend Program
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EN29LV160C
Table 10. Status Register Bits
DQ
Name
Logic Level
‘1’
7
DATA#
POLLING
6
TOGGLE
BIT
5
TIME OUT BIT
3
ERASE TIME
OUT BIT
‘0’
DQ7
DQ7#
‘-1-0-1-0-1-0-1-’
DQ6
‘-1-1-1-1-1-1-1-‘
‘1’
‘0’
‘1’
‘0’
‘-1-0-1-0-1-0-1-’
2
TOGGLE
BIT
DQ2
Definition
Erase Complete or
erase Sector in Erase suspend
Erase On-Going
Program Complete or
data of non-erase Sector
during Erase Suspend
Program On-Going
Erase or Program On-going
Read during Erase Suspend
Erase Complete
Program or Erase Error
Program or Erase On-going
Erase operation start
Erase timeout period on-going
Chip Erase, Erase or Erase
suspend on currently
addressed
Sector. (When DQ5=1, Erase
Error due to currently
addressed Sector. Program
during Erase Suspend ongoing at current address
Erase Suspend read on
non Erase Suspend Sector
Notes:
DQ7 DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for
Program or Erase Success.
DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive
reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5 Time Out Bit: set to “1” if failure in programming or erase
DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
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EN29LV160C
EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program
Command Sequence
(shown below)
Data# Poll Device
No
Verify Data?
Yes
Increment
Address
No
Last
Address?
Yes
Programming Done
Flowchart 2. Embedded Program Command Sequence
See the Command Definitions section for more information.
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
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EN29LV160C
Flowchart 3. Embedded Erase
START
Write Erase
Command Sequence
Data# Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
Flowchart 4. Embedded Erase Command Sequence
See the Command Definitions section for more information.
Chip Erase
Sector Erase
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
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EN29LV160C
Flowchart 5. DATA# Polling Algorithm
Start
Read Data
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read Data (1)
Notes:
(1) This second read is necessary in case the
first read was done at the exact instant when the
status data was in transition.
Yes
DQ7 = Data?
No
Fail
Flowchart 6. Toggle Bit Algorithm
Pass
Sta rt
Re ad D ata t wic e
No
DQ 6 = Togg le?
Ye s
No
D Q5 = 1 ?
Ye s
Rea d Dat a twice (2)
Notes:
(2) This second set of reads is necessary in case
the first set of reads was done at the exact instant
when the status data was in transition.
DQ 6 = Togg le?
No
Ye s
Fail
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EN29LV160C
Flowchart 7a. In-System Sector Protect Flowchart
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
No
Temporary Sector
Unprotect Mode
First Write
Cycle =
60h?
Yes
Set up sector
address
Sector Protect: Write 60h
to sector addr with
A6 = 0, A1 = 1, A0 = 0
Wait 150 μs
Verify Sector Protect:
Write 40h to sector
address with
A6 = 0, A1 = 1, A0 = 0
Increment
PLSCNT
Reset
PLSCNT = 1
Wait 0.4 μs
Read from sector
address with
A6 = 0, A1 = 1, A0 = 0
No
PLSCNT = 25?
No
Data = 01h?
Yes
Yes
Device failed
Protect another
sector?
Yes
No
Remove VID
from RESET#
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
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EN29LV160C
Flowchart 7b. In-System Sector Unprotect Flowchart
START
PLSCNT = 1
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector unprotect
address (see
Diagram 7a.)
RESET# = VID
Wait 1 μs
No
Temporary Sector
Unprotect Mode
First Write
Cycle = 60h?
Yes
No
All sectors
protected?
Yes
Set up first sector
address
Sector Unprotect: Write 60H to
sector address with A6 = 1,
A1 = 1, A0 = 0
Wait 15 ms
Increment
PLSCNT
Verify Sector Unprotect:
Write 40h to sector address
with A6 = 1, A1 = 1, A0 =0
Wait 0.4 μS
No
PLSCCNT =
1000?
Sector
Unprotect
Algorithm
Yes
Device failed
Read from sector address with
A6 = 1, A1 = 1, A0 = 0
No
Set up next sector
address
Data = 00h?
Yes
Last sector
verified?
No
Yes
Remove VID from
RESET#
Write reset
command
Sector Unprotect
complete
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EN29LV160C
Table 11. DC Characteristics
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
ILI
Input Leakage Current
ILO
Output Leakage Current
Active Read Current ( Byte mode)
ICC1
Active Read Current ( Word mode)
ICC2
Supply Current (StandbyCMOS)
ICC3
Supply Current (Program or Erase)
ICC4
Reset Current
B
B
Max
Unit
0V≤ VIN ≤ Vcc
±5
µA
0V≤ VOUT ≤ Vcc
±5
µA
CE# = VIL ; OE# = VIH ;
f = 5MHZ
CE# = BYTE# =
RESET# = Vcc ± 0.3V
(Note 1)
Byte program, Sector or
Chip Erase in progress
RESET# = Vss ± 0.3V
VIH = Vcc ± 0.3V
B
ICC5
B
B
Automatic Sleep Mode
Min
B
VIL = Vss ± 0.3V
B
Typ
9
16
mA
9
16
mA
1
5.0
µA
20
30
mA
1
5.0
µA
1
5.0
µA
0.8
Vcc +
0.3
0.45
V
B
VIL
Input Low Voltage
-0.5
0.7 x
Vcc
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 4.0 mA
VOH
Output High Voltage CMOS
IOH = -100μA
VID
A9 Voltage (Electronic Signature)
IID
A9 Current (Electronic Signature)
VLKO
Supply voltage (Erase and
Program lock-out)
Vcc 0.4V
8.5
A9 = VID
2.3
V
V
V
9.5
V
100
µA
2.5
V
Notes
1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that they
draw power if not at full CMOS supply voltages.
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EN29LV160C
Test Conditions
Test Specifications
-70
Unit
Output Load Capacitance, CL
Test Conditions
30
pF
Input Rise and Fall times
5
ns
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
0.0-3.0
V
1.5
V
1.5
V
B
B
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EN29LV160C
AC CHARACTERISTICS
Hardware Reset (Reset#)
Paramete
r Std
tRP1
tRP2
tRH
tRB1
tRB2
tREADY1
tREADY2
Min
Min
Min
Min
Min
Speed
-70
10
500
50
0
50
Max
20
us
Max
500
ns
Test
Setup
Description
RESET# Pulse Width (During Embedded Algorithms)
RESET# Pulse Width (NOT During Embedded Algorithms)
Reset# High Time Before Read
RY/BY# Recovery Time ( to CE#, OE# go low)
RY/BY# Recovery Time ( to WE# go low)
Reset# Pin Low (During Embedded Algorithms)
to Read or Write
Reset# Pin Low (NOT During Embedded Algorithms)
to Read or Write
Unit
us
ns
ns
ns
ns
Figure 1. AC Waveforms for RESET#
Reset# Timings
tRB1
CE#, OE#
WE#
tREADY1
tRB2
RY/BY#
RESET#
tRP1
Reset Timing during Embedded Algorithms
CE#, OE#
tRH
RY/BY#
RESET#
tRP2
tREADY2
Reset Timing NOT during Embedded Algorithms
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EN29LV160C
AC CHARACTERISTICS
Word / Byte Configuration (Byte#)
Std
Parameter
tBCS
tCBH
tRBH
Description
Byte# to CE# switching setup time
CE# to Byte# switching hold time
RY/BY# to Byte# switching hold time
Speed
Test
Setup
-70
Min
Min
Min
0
0
0
Unit
ns
ns
ns
Figure 2. AC Waveforms for BYTE#
CE#
OE#
Byte#
tCBH
tBCS
Byte# timings for Read Operations
CE#
WE#
Byte#
tBCS
tRBH
RY/BY#
Byte #timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
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EN29LV160C
Table 12. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
JEDEC
Standard
Speed
Test Setup
Description
Unit
-70
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable To Output Delay
tGLQV
tOE
tEHQZ
Min
70
ns
CE# = VIL
OE#= VIL
Max
70
ns
OE#= VIL
Max
70
ns
Output Enable to Output Delay
Max
30
ns
tDF
Chip Enable to Output High Z
Max
20
ns
tGHQZ
tDF
Output Enable to Output High Z
Max
20
ns
tAXQX
tOH
Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first
Min
0
ns
Output Enable
Hold Time
MIn
0
ns
tOEH
Min
10
ns
Read
Toggle and
DATA# Polling
Notes:
1. High Z is Not 100% tested.
2. For - 70
Vcc = 2.7V – 3.6V
Output Load : 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
Figure 3. AC Waveforms for READ Operations
tBRCB
Addresses
Addresses Stable
tBACC
CE#
tBDF
tBOEB
OE#
tBOEHB
WE#
tBOH
tBCEB
Outputs
HIGH Z
Output Valid
HIGH Z
RESET#
RY/BY#
0V
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EN29LV160C
Table 13. AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter
Symbols
Speed
Description
Unit
-70
JEDEC
Standard
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tWLAX
tAH
Address Hold Time
Min
45
ns
tDVWH
tDS
Data Setup Time
Min
30
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
MIn
0
ns
tOEH
Output Enable
Hold Time
Min
10
ns
Min
0
ns
tGHWL
tGHWL
Read
Toggle and
DATA# Polling
Read Recovery Time before Write (OE#
High to WE# Low)
tELWL
tCS
CE# SetupTime
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
20
ns
tWHWH1
tWHWH1
Programming Operation
(Word AND Byte Mode)
Typ
8
µs
Max
200
µs
tWHWH2
tWHWH2
Erase Operation
Sector
Typ
0.1
s
(Note 2)
Chip
Max
4
s
tVCS
Vcc Setup Time
Min
50
µs
t BUSY
WE# High to RY/BY# Low
Max
70
ns
tRB
Recovery Time from RY/BY#
Min
0
ns
B
1. Not 100% tested.
2. See Erase and Programming Performance for more information.
This Data Sheet may be revised by subsequent versions
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EN29LV160C
Table 14. AC CHARACTERISTICS
Write (Erase/Program) Operations
Alternate CE# Controlled Writes
Parameter
Symbols
Speed
Description
Unit
-70
JEDEC
Standard
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
ns
tAVEL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
30
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Output Enable
Hold Time
Read
Min
0
ns
tOEH
Toggle and Data Polling
Min
10
ns
tGHEL
tGHEL
Read Recovery Time before Write
(OE# High to CE# Low)
Min
0
ns
tWLEL
tWS
WE# SetupTime
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
Write Pulse Width
Min
35
ns
tEHEL
tCPH
Write Pulse Width High
Min
20
ns
tWHWH1
tWHWH1
Typ
8
µs
Max
200
µs
tWHWH2
tWHWH2
Programming Operation
(Byte AND word mode) (Note 2)
Erase Operation
Sector
Typ
0.1
s
(Note 2)
Chip
Typ
4
s
tVCS
Vcc Setup Time
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
ns
1. Not 100% tested.
2. See Erase and Programming Performance for more information.
This Data Sheet may be revised by subsequent versions
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EN29LV160C
Table 15. ERASE AND PROGRAMMING PERFORMANCE
Typ
Limits
Max
Unit
Sector Erase Time
0.1
2
sec
Chip Erase Time
4
35
sec
Byte Programming Time
8
200
µs
Word Programming Time
8
200
µs
Byte
16.8
50.4
Word
8.4
25.2
Parameter
Chip Programming
Time
Erase/Program Endurance
Comments
Excludes 00h programming prior
to erasure
Excludes system level overhead
sec
100K
Minimum 100K cycles
cycles
Notes: Maximum program and erase time assume the following conditions Vcc = 2.7 V , 85°C
Table 16. 48-PIN TSOP AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
B
B
COUT
B
B
CIN2
B
B
Output Capacitance
Control Pin Capacitance
B
Package
Typ
Max
TSOP
6
7.5
BGA
1.2
1.2
TSOP
8.5
12
BGA
1.1
1.2
TSOP
7.5
9
BGA
1.0
1.3
B
VOUT = 0
B
B
VIN = 0
B
B
Unit
pF
pF
pF
Note: Test conditions are Temperature = 25°C and f = 1.0 MHz.
Table 17. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Data Retention Time
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EN29LV160C
AC CHARACTERISTICS
Figure 4. AC Waveforms for Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles)
tAS
tWC
Addresses
0x2AA
Read Status Data (last two cycles)
tAH
SA
VA
VA
0x555 for chip
erase
CE#
tGHWL
tCH
OE#
tWP
WE#
tWPH
tCS
0x55
Data
tDS
tWHWH2
0x30
tDH
Status
10 for chip
erase
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address.
2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command
sequence.
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EN29LV160C
Figure 5. Program Operation Timings
Program Command Sequence (last 2 cycles)
tAS
tWC
Addresses
0x555
Program Command Sequence (last 2 cycles)
tAH
PA
PA
PA
CE#
tGHWL
OE#
tCH
tWP
WE#
tWPH
tWHWH1
tCS
Data
OxA0
tDS
RY/BY#
Status
PD
tDH
DOUT
tBUSY
tRB
tVCS
VCC
Notes:
1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address.
2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command
sequence.
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EN29LV160C
Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
tRC
Addresses
VA
VA
VA
tACC
tCH
tCE
CE#
tOE
OE#
tOEH
tDF
WE#
tOH
DQ[7]
Complement
DQ[6:0]
Status Data
Comple
-ment
Status
Data
Valid Data
True
True
Valid Data
tBUSY
RY/BY#
Notes:
1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
tRC
VA
Addresses
tCH
VA
VA
VA
tACC
tCE
CE#
tOE
OE#
tOEH
WE#
tDF
tOH
Valid Status
DQ6, DQ2
tBUSY
(first read)
Valid Status
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
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EN29LV160C
Figure 8. Alternate CE# Controlled Write Operation Timings
0x555 for Program
0x2AA for Erase
PA for Program
SA for Sector Erase
0x555 for Chip Erase
Addresses
VA
tWC
tAS
tAH
WE#
tWH
tGHEL
OE#
tCP
tWS
CE#
tDS
tCPH
tWHWH1 / tWHWH2
tBUSY
tDH
Status
Data
0xA0 for
Program
0x55 for Erase
DOUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
RY/BY
tRH
Reset#
Notes:
PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
Dout = array data read at VA
Shown above are the last two cycles of the program or erase command sequence and the last status read cycle
Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 9. DQ2 vs. DQ6
Enter
Embedded
Erase
WE#
Enter Erase
Suspend
Program
Erase
Suspend
Erase
Enter
Suspend
Read
Erase
Resume
Enter
Suspend
Program
Erase
Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
38
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
Table 19. Temporary Sector Unprotect
Parameter
Std
tVIDR
VID Rise and Fall Time
RESET# Setup Time for Temporary
Sector Unprotect
tRSP
Speed Option
-70
Unit
Min
500
ns
Min
4
µs
Description
Notes: tRSP is Not 100% tested.
Figure 10. Temporary Sector Unprotect Timing Diagram
VID
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
Figure 11. Sector Protect/Unprotect Timing Diagram
VID
RESET#
Vcc
0V
0V
tVIDR
tVIDR
SA,
A6,A1,A0
Data
60h
Valid
Valid
Valid
60h
40h
Status
Sector Protect/Unprotect
CE#
Verify
>0.4μs
WE#
>1μS
Sector Protect: 150 us
Sector Unprotect: 15 ms
OE#
Notes:
Use standard microprocessor timings for this device for read and write cycles.
For Sector Protect, use A6=0, A1=1, A0=0. For Sector Unprotect, use A6=1, A1=1, A0=0.
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
39
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
FIGURE 12. 48L TSOP 12mm x 20mm package outline
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
40
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
FIGURE 13. 48L TFBGA 6mm x 8mm package outline
SYMBOL
DIMENSION IN MM
MIN.
NOR
MAX
A
---
---
1.30
A1
0.23
0.29
0.35
A2
0.84
0.91
0.95
D
7.90
8.00
8.10
E
5.90
6.00
6.10
D1
---
5.60
---
E1
---
4.00
---
e
---
0.80
---
b
0.35
0.40
Note : 1. Coplanarity: 0.1 mm
0.45
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
41
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
Figure 14. 48L WFBGA 4mm x 6mm package outline
Note : Controlling dimensions are in millimeters (mm).
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
42
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Storage Temperature
-65 to +150
C
Plastic Packages
-65 to +125
C
-55 to +125
C
200
mA
A9, OE#, Reset# 2
-0.5 to +11.5
V
All other pins 3
-0.5 to Vcc+0.5
V
Vcc
-0.5 to + 4.0
V
Ambient Temperature
With Power Applied
Output Short Circuit Current1
Voltage with
Respect to Ground
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC input voltage on A9, OE#, RESET# pins is –0.5V. During voltage transitions, A9, OE#, RESET# pins may
undershoot Vss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input
voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.
3.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5
V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.
4.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
RECOMMENDED OPERATING RANGES1
Parameter
Value
Ambient Operating Temperature
Industrial Devices
Operating Supply Voltage
Vcc
3.
-40 to 85
Full Voltage Range:
2.7 to 3.6V
Unit
C
V
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot
Waveform
Maximum Positive Overshoot
Waveform
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
43
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ New Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code:
XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
44
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
ORDERING INFORMATION
EN29LV160C
T
-
70
T
I
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
T = 48-pin TSOP
B = 48-Ball Thin Fine Pitch Ball Grid Array (TFBGA)
0.80mm pitch, 6mm x 8mm package
N = 48-Ball Very-Very-Thin-Profile Fine Pitch
Ball Grid Array (WFBGA)
0.5mm pitch, 4mm x 6mm package
SPEED
70 = 70ns
BOOT CODE SECTOR ARCHITECTURE
T = Top boot Sector
B = Bottom boot Sector
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
29LV = FLASH, 3V Read Program Erase
160 = 16 Megabit (2M x 8 / 1M x 16)
C = version identifier
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
45
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
www.eonssi.com
EN29LV160C
Revisions List
Revision No Description
Date
A
2011/01/07
B
Initial Release
1. Update Secured Silicon Sector length from 32 words to 128 words.
(The related table 2B and table 2D on page 4 and page 5.)
2. Update VID from 10.5-11.5V to 8.5-9.5V.
3. Update Table 11. DC Characteristics on page 26.
1. Correct the typo of VIH (max.) = Vcc + 0.3V on page 26.
2. Add BGA PACKAGE CAPACITANCE on page 33.
1. Add Support JEDEC Common Flash Interface (CFI) information on
page 1.
2. Add Automatic Sleep Mode description on page 9.
Add 48-Ball WFBGA 0.5mm pitch, 4mm x 6mm package option.
2011/06/09
B
C
D
E
This Data Sheet may be revised by subsequent versions
© 2012 Eon Silicon Solution, Inc.,
46
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/09/07
2011/10/26
2012/03/30
2012/09/07
www.eonssi.com
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