datasheet for PIC16(L)F1946 by Microchip Technology Inc.

datasheet for PIC16(L)F1946 by Microchip Technology Inc.

PIC16(L)F1946/1947

Data Sheet

64-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

LCD Driver and nanoWatt XLP Technology

2010-2012 Microchip Technology Inc.

DS41414D

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE

.

Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

ISO/TS 16949

DS41414D-page 2

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

K

EE

L

OQ

, K

EE

L

OQ

logo, MPLAB, PIC, PICmicro, PICSTART,

PIC

32

logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2010-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 9781620760840

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC ® DSCs, K

EE

L

OQ

® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

LCD Driver and nanoWatt XLP Technology

High-Performance RISC CPU:

• Only 49 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 32 MHz oscillator/clock input

- DC – 125 ns instruction cycle

• Up to 16K x 14 Words of Flash Program Memory

• Up to 1024 Bytes of Data Memory (RAM)

• Interrupt Capability with Automatic Context

Saving

• 16-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

• Processor Read Access to Program Memory

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range from

32 MHz to 31 kHz

• Power-Saving Sleep mode

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Reset (BOR):

- Selectable between two trip points

- Disable in Sleep option

• Multiplexed Master Clear with Pull-up/Input Pin

• Programmable Code Protection

• High Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

• Wide Operating Voltage Range:

- 1.8V-5.5V (PIC16F1946/47)

- 1.8V-3.6V (PIC16LF1946/47)

PIC16LF1946/47 Low-Power Features:

• Standby Current:

- 60 nA @ 1.8V, typical

• Operating Current:

- 7.0

A @ 32 kHz, 1.8V, typical

- 35

A/MHz, 1.8V, typical

• Timer1 Oscillator Current:

- 600 nA @ 32 kHz, 1.8V, typical

• Low-Power Watchdog Timer Current:

- 500 nA @ 1.8V, typical

Peripheral Features:

• 54 I/O Pins (1 Input-only pin):

- High-current source/sink for direct LED drive

- Individually programmable Interrupt-on-pin change pins

- Individually programmable weak pull-ups

• Integrated LCD Controller:

- Up to 184 segments

- Variable clock input

- Contrast control

- Internal voltage reference selections

• Capacitive Sensing (CSM) Module (mTouch

TM

):

- 17 selectable channels

• A/D Converter:

- 10-bit resolution and 17 channels

- Selectable 1.024/2.048/4.096V voltage reference

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Enhanced Timer1:

- Dedicated low-power 32 kHz oscillator driver

- 16-bit timer/counter with prescaler

- External Gate Input mode with toggle and single shot modes

- Interrupt-on-gate completion

• Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period

Register, Prescaler and Postscaler

• Two Capture, Compare, PWM Modules (CCP):

- 16-bit Capture, max. resolution 125 ns

- 16-bit Compare, max. resolution 125 ns

- 10-bit PWM, max. frequency 31.25 kHz

• Three Enhanced Capture, Compare, PWM

Modules (ECCP):

- 3 PWM time-base options

- Auto-shutdown and auto-restart

- PWM steering

- Programmable Dead-band Delay

2010-2012 Microchip Technology Inc.

DS41414D-page 3

PIC16(L)F1946/47

Peripheral Features (Continued):

• Two Master Synchronous Serial Ports (MSSPs) with SPI and I

2

C

TM

with:

- 7-bit address masking

- SMBus/PMBus TM compatibility

- Auto-wake-up on start

• Two Enhanced Universal Synchronous:

Asynchronous Receiver Transmitters (EUSARTs)

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

• SR Latch (555 Timer):

- Multiple Set/Reset input options

- Emulates 555 Timer applications

• Three Comparators:

- Rail-to-rail inputs/outputs

- Power mode control

- Software enable hysteresis

• Voltage Reference Module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive and negative reference selection

PIC16(L)F193X/194X Family Types

Device

PIC16(L)F1933

PIC16(L)F1934

PIC16(L)F1936

PIC16(L)F1937

PIC16(L)F1938

PIC16(L)F1939

(1)

(2)

(2)

(2)

(3)

(3)

4096

4096

8192

8192

16384

16384

256

256

256

256

256

256

256

256

512

512

1024

1024

25

36

25

36

25

36

11

14

11

14

11

14

8

16

8

16

8

16

2

2

2

2

2

2

4/1

4/1

4/1

4/1

4/1

4/1

1

1

1

1

1

1

1

1

1

1

1

1

3

3

3

3

3

3

2

2

2

2

2

2

4/16/60

(3)

4/24/96

4/16/60

(3)

4/24/96

4/16/60

(3)

4/24/96

I/H

I/H

I/H

I/H

I/H

I/H

PIC16(L)F1946 (4)

PIC16(L)F1947 (4)

Note 1:

2:

8192

16384

256

256

512 54

1024 54

17

17

17

17

3

3

4/1

4/1

2

2

2

2

I – Debugging, Integrated on Chip; H – Debugging, Requires Debug Header.

One pin is input-only.

3

3

3:

2

2

4/46/184

4/46/184

I

I

Y

Y

COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multiplex displays.

Data Sheet Index:

(Unshaded devices are described in this document.)

1:

DS41575 PIC16(L)F1933 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.

2:

3:

4:

DS41364 PIC16(L)F1934/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.

DS41574

DS41414

PIC16(L)F1938/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.

PIC16(L)F1946/1947 Data Sheet, 64-Pin Flash, 8-bit Microcontrollers.

Y

Y

Y

Y

Y

Y

2010-2012 Microchip Technology Inc.

DS41414D-page 4

Pin Diagram – 64-Pin TQFP/QFN

(

PIC16(L)F1946/47)

64-pin TQFP, QFN

PIC16(L)F1946/47

RE1

RE0

RG0

RG1

RG2

RG3

V

PP

/MCLR/RG5

RG4

V

SS

V

DD

RF7

RF6

RF5

RF4

RF3

RF2

64 63 62 61

60 59 58 57 56 55 54 53 52 51 50 49

10

11

12

13

8

9

6

7

1

4

5

2

3

14

15

16

PIC16(L)F1946/47

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

37

36

35

34

33

42

41

40

39

38

48

47

46

45

44

43

RB0

RB1

RB2

RB3

RB4

RB5

RB6

V

SS

RA6

RA7

V

DD

RB7

RC5

RC4

RC3

RC2

Note 1:

2:

3:

Pin location selected by APFCON register setting. Default location.

Pin function can be moved using the APFCON register. Alternate location.

QFN package orientation is the same. No leads are present on the QFN package.

2010-2012 Microchip Technology Inc.

DS41414D-page 5

PIC16(L)F1946/47

TABLE 1: 64-PIN SUMMARY(PIC16(L)F1946/47)

RA0

RA1

RA2

RA3

RA4

RA5

RA6

28

27

40

24

23

22

21

Y

Y

Y

Y

Y

AN0

AN1

AN2

AN3

AN4

V

REF

-

V

REF

+

CPS0

CPS1

CPS2

CPS3

CPS4

RA7 39 —

RB0 48 —

RB1

RB2

RB3

RB4

RB5

RB6

47

46

45

44

43

42

RB7 37

T0CKI

SRI

T1G

FLT0

— — —

RC0 30

RC1 29

RC2 33

RC3 34

RC4 35

RC5

RC6

36

31

RC7 32

RD0

RD1

RD2

RD3

RD4

RD5

58

55

54

53

52

51

RD6 50

Note 1:

2:

3:

4:

— — — — — — T1OSO/

T1CKI

T1OSI

— — — SEG40

— —

CCP2

(1)

/

P2A

(1)

CCP1

/

P1A

SEG32

SEG13

P2D

(2)

P2C

(2)

P2B

(2)

TX1/

CK1

RX1/

DT1

SCK1/

SCL1

SDI1/

SDA1

SDO1

SEG17

SEG16

SEG12

SEG27

SEG28

SEG0

SEG1

SEG2

SEG3

P3C

(2)

P3B

(2)

P1C

(2)

P1B

(2)

SDO2

SDI2

SDA2

SCK2/

SCL2

SEG4

SEG5

SEG6

Pin functions can be moved using the APFCON register(s). Default location.

Pin function can be moved using the APFCON register. Alternate location.

Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.

See

Section 8.0 “Low Dropout (LDO) Voltage Regulator”

.

SEG33

SEG18

SEG34

SEG35

SEG14

SEG15

SEG36

SEG37

SEG30

SEG8

SEG9

SEG10

SEG11

SEG29

SEG38

INT/

IOC

IOC

IOC

IOC

IOC

IOC

IOC

— SEG39 IOC

Y

Y

Y

Y

Y

Y

Y

Y

ICSP-

CLK/

ICDCLK

ICSP-

DAT/

ICDDAT

OSC2/

CLK-

OUT

OSC1/

CLKIN

DS41414D-page 6

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

TABLE 1: 64-PIN SUMMARY(PIC16(L)F1946/47) (Continued)

63

62

61

60

49

2

1

64

59

RD7

RE0

RE1

RE2

RE3

RE4

RE5

RE6

RE7

RF0 18

RF1

RF2

RF3

17

16

15

RF4

RF5

14

13

RF6

RF7

12

11

RG0 3

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

AN16

AN6

AN7

AN8

AN9

AN10

DACOUT

AN11

AN5

CPS16

CPS6

CPS7

CPS8

CPS9

CPS10

CPS11

CPS5

C1IN0-

C2IN0-

C2OUT

C1OUT

C1IN2-

C2IN2-

C3IN2-

C2IN+

C1IN1-

C2IN1-

C1IN+

C1IN3-

C2IN3-

C3IN3-

SRNQ

SRQ

Y AN15 RG1 4

RG2 5 Y AN14

CPS15 C3OUT

CPS14 C3IN+

RG3

RG4

6

8

RG5 7

Y AN13

Y AN12

— —

CPS13 C3IN0-

CPS12 C3IN1-

— —

P2D

(1)

P2C

(1)

P2B

(1)

P3C

(1)

P3B

(1)

P1C

(1)

P1B

(1)

CCP2

(2)

/

P2A

(2)

CCP3

P3A

CCP4

P3D

CCP5

P1D

TX2/

CK2

RX2/

DT2

SS2 SEG7

VLCD1

VLCD2

VLCD3

COM0

COM1

COM2

COM3

SEG31

SEG41

SEG19

SEG20

SEG21

SEG22

SEG23

SS1

SEG24

SEG25

SEG42

SEG43

SEG44

SEG45

SEG26

V

DD

V

SS

AV

DD

AV

SS

Note

10

26

38

57

9

25

41

56

19

20

1:

2:

3:

4:

Pin functions can be moved using the APFCON register(s). Default location.

Pin function can be moved using the APFCON register. Alternate location.

Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.

See

Section 8.0 “Low Dropout (LDO) Voltage Regulator”

.

Y

(3)

MCLR/

V

PP

V

DD

V

CAP

(4)

— V

SS

AV

DD

AV

SS

2010-2012 Microchip Technology Inc.

DS41414D-page 7

PIC16(L)F1946/47

Table of Contents

5.0

6.0

7.0

8.0

1.0

2.0

3.0

4.0

Device Overview ........................................................................................................................................................................ 11

Enhanced Mid-Range CPU ........................................................................................................................................................ 19

Memory Organization ................................................................................................................................................................. 21

Device Configuration .................................................................................................................................................................. 55

Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 61

Resets ........................................................................................................................................................................................ 79

Interrupts .................................................................................................................................................................................... 87

Low Dropout (LDO) Voltage Regulator .................................................................................................................................... 103

9.0

Power-Down Mode (Sleep) ...................................................................................................................................................... 105

10.0 Watchdog Timer ....................................................................................................................................................................... 107

11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 111

12.0 I/O Ports ................................................................................................................................................................................... 127

13.0 Interrupt-On-Change ................................................................................................................................................................ 153

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 157

15.0 Temperature Indicator Module ................................................................................................................................................. 159

16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 161

17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 175

18.0 Comparator Module.................................................................................................................................................................. 179

19.0 SR Latch................................................................................................................................................................................... 189

20.0 Timer0 Module ......................................................................................................................................................................... 195

21.0 Timer1 Module with Gate Control............................................................................................................................................. 199

22.0 Timer2/4/6 Modules.................................................................................................................................................................. 211

23.0 Capture/Compare/PWM Modules ............................................................................................................................................ 215

24.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module .............................................................................................. 243

25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 297

26.0 Capacitive Sensing (CPS) Module ........................................................................................................................................... 327

27.0 Liquid Crystal Display (LCD) Driver Module ............................................................................................................................. 335

28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 371

29.0 Instruction Set Summary .......................................................................................................................................................... 375

30.0 Electrical Specifications............................................................................................................................................................ 389

31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 421

32.0 Development Support............................................................................................................................................................... 455

33.0 Packaging Information.............................................................................................................................................................. 459

Appendix A: Data Sheet Revision History.......................................................................................................................................... 465

Appendix B: Migrating From Other PIC

®

Devices.............................................................................................................................. 465

Index .................................................................................................................................................................................................. 467

The Microchip Web Site ..................................................................................................................................................................... 475

Customer Change Notification Service .............................................................................................................................................. 475

Customer Support .............................................................................................................................................................................. 475

Reader Response .............................................................................................................................................................................. 476

Product Identification System............................................................................................................................................................. 477

2010-2012 Microchip Technology Inc.

DS41414D-page 8

PIC16(L)F1946/47

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at

[email protected]

or fax the

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in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.

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to receive the most current information on all of our products.

2010-2012 Microchip Technology Inc.

DS41414D-page 9

PIC16(L)F1946/47

NOTES:

DS41414D-page 10

2010-2012 Microchip Technology Inc.

1.0

DEVICE OVERVIEW

The PIC16(L)F1946/47 are described within this data sheet. They are available in 64-pin packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1946/47 devices.

Table 1-2

shows the pinout descriptions.

Reference device.

Table 1-1

for peripherals available per

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

ADC

Capacitive Sensing (CPS) Module

Data EEPROM

Digital-to-Analog Converter (DAC)

Fixed Voltage Reference (FVR)

LCD

SR Latch

Capture/Compare/PWM Modules

ECCP1

ECCP2

ECCP3

CCP4

CCP5

Comparators

C1

C2

C3

EUSARTS

Master Synchronous Serial Ports

MSSP1

MSSP2

Timers

EUSART1

EUSART2

Timer0

Timer1

Timer2

Timer4

Timer6

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

DS41414D-page 11

PIC16(L)F1946/47

FIGURE 1-1: PIC16(L)F1946/47 BLOCK DIAGRAM

Program

Flash Memory

OSC2/CLKOUT

OSC1/CLKIN

Timing

Generation

INTRC

Oscillator

MCLR

CPU

Figure 2-1

RAM

SR

Latch

ADC

10-Bit

Timer0 Timer1 Timer2 Timer4 Timer6 Comparators

EEPROM

PORTA

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

LCD ECCP1 ECCP2 ECCP3 CCP4 CCP5

MSSPx

EUSARTx

Note 1:

See applicable chapters for more information on peripherals.

2010-2012 Microchip Technology Inc.

DS41414D-page 12

PIC16(L)F1946/47

TABLE 1-2:

Name

PIC16(L)F1946/47 PINOUT DESCRIPTION

Function

Input

Type

Output

Type

Description

RA0/AN0/CPS0/SEG33 RA0

AN0

CPS0

SEG33

TTL

AN

AN

CMOS General purpose I/O.

AN

A/D Channel input.

Capacitive sensing input 0.

LCD Analog output.

RA1/AN1/CPS1/SEG18

RA2/AN2/V

RA3/AN3/V

REF

REF

-/CPS2/SEG34

+/CPS3/SEG35

RA4/T0CKI/SEG14

RA1

AN1

CPS1

SEG18

RA2

AN2

V

REF

-

CPS2

SEG34

RA3

AN3

V

REF

+

CPS3

SEG35

RA4

AN

TTL

AN

AN

AN

TTL

TTL

AN

AN

TTL

AN

AN

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

AN LCD Analog output.

CMOS General purpose I/O.

A/D Channel input.

A/D Negative Voltage Reference input.

AN

Capacitive sensing input.

LCD Analog output.

CMOS General purpose I/O.

— A/D Channel input.

A/D Voltage Reference input.

Capacitive sensing input.

AN LCD Analog output.

CMOS General purpose I/O.

RA5/AN4/CPS4/SEG15

RA6/OSC2/CLKOUT/SEG36

T0CKI

SEG14

RA5

AN4

CPS4

SEG5

RA6

OSC2

AN

TTL

ST

TTL

AN

AN

Timer0 clock input.

LCD Analog output.

CMOS General purpose I/O.

— A/D Channel input.

AN

Capacitive sensing input.

LCD Analog output.

CMOS General purpose I/O.

XTAL Crystal/Resonator (LP, XT, HS modes).

RA7/OSC1/CLKIN/SEG37

RB0/INT/SRI/FLT0/SEG30

CLKOUT

SEG36

RA7

OSC1

CLKIN

SEG37

RB0

TTL

XTAL

CMOS

TTL

CMOS F

OSC

/4 output.

AN LCD Analog output.

CMOS General purpose I/O.

— Crystal/Resonator (LP, XT, HS modes).

AN

External clock input (EC mode).

LCD Analog output.

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

— External interrupt.

ST

SR Latch input.

ECCP Auto-shutdown Fault input.

INT

SRI

FLT0

ST

ST

RB1/SEG8

SEG30

RB1

TTL

AN LCD analog output.

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

SEG8 — AN LCD Analog output.

Legend:

Note 1:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I

OD

2

= Open Drain

C™ = Schmitt Trigger input with I

2

C

XTAL = Crystal levels

Pin function is selectable via the APFCON register.

2010-2012 Microchip Technology Inc.

DS41414D-page 13

PIC16(L)F1946/47

TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED)

Name Function

Input

Type

Output

Type

Description

RB2/SEG9

RB3/SEG10

RB2

SEG9

RB3

TTL

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN LCD Analog output.

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN LCD Analog output.

RB4/SEG11

RB5/T1G/SEG29

RB6/ICSPCLK/ICDCLK/SEG38

RB7/ICSPDAT/ICDDAT/SEG39

RC0/T1OSO/T1CKI/SEG40

RC1/T1OSI/P2A

(1)

/CCP2

(1)

/

SEG32

RC2/CCP1/P1A/SEG13

RC3/SCK/SCL/SEG17

SEG10

RB4

SEG11

RB5

T1G

SEG29

RB6

ICSPCLK

ICDCLK

SEG38

RB7

ICSPDAT

ICDDAT

SEG39

RC0

T1OSO

T1CKI

SEG40

RC1

T1OSI

P2A

CCP2

SEG32

RC2

CCP1

P1A

SEG13

RC3

SCK

SCL

SEG17

TTL

TTL

ST

TTL

ST

ST

TTL

ST

ST

ST

ST

ST

XTAL

ST

ST

XTAL

ST

ST

ST

I

2

C

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN LCD Analog output.

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

— Timer1 Gate input.

AN LCD Analog output.

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN

XTAL

AN

Serial Programming Clock.

In-Circuit Debug Clock.

AN LCD Analog output.

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

CMOS ICSP™ Data I/O.

CMOS In-Circuit Data I/O.

LCD Analog output.

CMOS General purpose I/O.

XTAL

Timer1 oscillator connection.

Timer1 clock input.

AN LCD Analog output.

CMOS General purpose I/O.

Timer1 oscillator connection.

CMOS PWM output.

CMOS Capture/Compare/PWM.

LCD Analog output.

CMOS General purpose I/O.

CMOS Capture/Compare/PWM.

CMOS PWM output.

AN LCD Analog output.

CMOS General purpose I/O.

CMOS SPI clock.

OD

AN

I

2

C™ clock.

LCD Analog output.

RC4/SDI1/SDA1/SEG16 RC4

SDI1

SDA1

SEG16

ST

ST

I

2

C

CMOS General purpose I/O.

OD

AN

SPI data input.

I

2

C™ data input/output.

LCD Analog output.

Legend:

Note 1:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I

OD

2

= Open Drain

C™ = Schmitt Trigger input with I

2

C

XTAL = Crystal levels

Pin function is selectable via the APFCON register.

2010-2012 Microchip Technology Inc.

DS41414D-page 14

PIC16(L)F1946/47

TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED)

Name Function

Input

Type

Output

Type

Description

RC5/SDO1/SEG12

RC6/TX1/CK1/SEG27

RC7/RX1/DT1/SEG28

RD0/P2D

RD1/P2C

(1)

(1)

/SEG0

/SEG1

RX

DT1

SEG28

RD0

P2D

SEG0

RD1

P2C

RC5

SDO1

SEG12

RC6

TX1

CK1

SEG27

RC7

ST

ST

ST

ST

ST

ST

ST

ST

CMOS General purpose I/O.

CMOS SPI data output.

AN LCD Analog output.

CMOS General purpose I/O.

CMOS USART1 asynchronous transmit.

CMOS USART1 synchronous clock.

AN LCD Analog output.

CMOS General purpose I/O.

— USART1 asynchronous input.

CMOS USART1 synchronous data.

AN LCD Analog output.

CMOS General purpose I/O.

CMOS PWM output.

AN LCD Analog output.

CMOS General purpose I/O.

CMOS PWM output.

RD2/P2B

RD3/P3C

(1)

(1)

/SEG2

/SEG3

RD4/SDO2/P3B

(1)

/SEG4

SEG1

RD2

P2B

SEG2

RD3

P3C

SEG3

RD4

ST

ST

ST

AN LCD Analog output.

CMOS General purpose I/O.

CMOS PWM output.

AN LCD Analog output.

CMOS General purpose I/O.

CMOS PWM output.

AN LCD analog output.

CMOS General purpose I/O.

RD5/SDI2/SDA2/P1C

RD6/SCK2/SCL2/P1B

(1)

(1)

/SEG5

/SEG6

SDO2

P3B

SEG4

RD5

SDI2

SDA2

P1C

SEG5

RD6

SCK2

SCL2

P1B

ST

ST

I

2

C

ST

ST

I

2

C

CMOS SPI data output.

CMOS PWM output.

AN

CMOS General purpose I/O.

OD

LCD analog output.

SPI data input.

I

2

C™ data input/output.

CMOS PWM output.

AN LCD analog output.

CMOS General purpose I/O.

CMOS SPI clock.

OD I

2

C™ clock.

CMOS PWM output.

RD7/SS2/SEG7

SEG6

RD7

SS2

SEG7

ST

ST

AN LCD analog output.

CMOS General purpose I/O.

AN

Slave Select input.

LCD analog output.

RE0/P2D

(1)

/VLCD1 RE0

P2D

ST

CMOS General purpose I/O.

CMOS PWM output.

VLCD1 AN — LCD analog input.

Legend:

Note 1:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I

OD

2

= Open Drain

C™ = Schmitt Trigger input with I

2

C

XTAL = Crystal levels

Pin function is selectable via the APFCON register.

2010-2012 Microchip Technology Inc.

DS41414D-page 15

PIC16(L)F1946/47

TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED)

Name Function

Input

Type

Output

Type

Description

RE1/P2C

RE2/P2B

RE3/P3C

RE4/P3B

RE5/P1C

RE6/P1B

(1)

(1)

(1)

(1)

(1)

(1)

RE7/CCP2

/VLCD2

/VLCD3

/COM0

/COM1

/COM2

/COM3

(1)

/P2A

(1)

/SEG31

RF0/AN16/CPS16/C12IN0-/

SEG41/V

CAP

RF1/AN6/CPS6/C2OUT/SRNQ/

SEG19

RF2/AN7/CPS7/C1OUT/SRQ/

SEG20

COM0

RE4

P3B

COM1

RE5

P1C

COM2

RE6

RE1

P2C

VLCD2

RE2

P2B

VLCD3

RE3

P3C

P1B

COM3

RE7

CCP2

P2A

SEG31

RF0

AN16

CPS16

C1IN0-

C2IN0-

SEG41

V

CAP

RF1

AN6

CPS6

C2OUT

SRNQ

SEG19

RF2

AN7

CPS7

C1OUT

SRQ

ST

AN

ST

AN

ST

ST

ST

ST

ST

ST

ST

AN

AN

AN

ST

AN

AN

AN

Power

ST

AN

AN

CMOS General purpose I/O.

CMOS PWM output.

CMOS General purpose I/O.

CMOS PWM output.

CMOS General purpose I/O.

CMOS PWM output.

AN

CMOS General purpose I/O.

CMOS PWM output.

AN

CMOS General purpose I/O.

CMOS PWM output.

AN

LCD analog input.

LCD analog input.

LCD Analog output.

LCD Analog output.

LCD Analog output.

General purpose I/O.

CMOS PWM output.

AN LCD Analog output.

CMOS General purpose I/O.

CMOS Capture/Compare/PWM.

CMOS PWM output.

AN LCD analog output.

CMOS General purpose I/O.

— A/D Channel input.

Capacitive sensing input.

Comparator negative input.

AN

Comparator negative input.

LCD Analog output.

Power Filter capacitor for Voltage Regulator.

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

CMOS Comparator output.

CMOS SR Latch inverting output.

AN LCD Analog output.

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

CMOS Comparator output.

CMOS SR Latch non-inverting output.

SEG20 — AN LCD Analog output.

Legend:

Note 1:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I

OD

2

= Open Drain

C™ = Schmitt Trigger input with I

2

C

XTAL = Crystal levels

Pin function is selectable via the APFCON register.

2010-2012 Microchip Technology Inc.

DS41414D-page 16

PIC16(L)F1946/47

TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED)

Name Function

Input

Type

Output

Type

Description

RF3/AN8/CPS8/C123IN2-/

SEG21

RF4/AN9/CPS9/C2IN+/SEG22

RF5/AN10/CPS10/C12IN1-/

DACOUT/SEG23

AN9

CPS9

C2IN+

SEG22

RF5

AN10

CPS10

C1IN1-

RF3

AN8

CPS8

C1IN2-

C2IN2-

C3IN2-

SEG21

RF4

ST

AN

AN

AN

AN

AN

ST

AN

AN

AN

ST

AN

AN

AN

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

Comparator negative input.

Comparator negative input.

Comparator negative input.

AN LCD Analog output.

CMOS General purpose I/O.

AN

A/D Channel input.

Capacitive sensing input.

Comparator positive input.

LCD Analog output.

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

Comparator negative input.

RF6/AN11/CPS11/C1IN+/SEG24

C2IN1-

DACOUT

SEG23

RF6

AN11

CPS11

C1IN+

SEG24

AN

ST

AN

AN

AN

AN

Comparator negative input.

Voltage Reference output.

AN LCD Analog output.

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

AN

Comparator positive input.

LCD Analog output.

RF7/AN5/CPS5/C123IN3-/SS1/

SEG25

RF7

AN5

CPS5

C1IN3-

ST

AN

AN

AN

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

Comparator negative input.

RG0/CCP3/P3A/SEG42

RG1/AN15/CPS15/TX2/CK2/

C3OUT/SEG43

C2IN3-

C3IN3-

SS1

SEG25

RG0

CCP3

P3A

SEG42

RG1

AN15

CPS15

TX2

CK2

C3OUT

AN

AN

ST

ST

ST

ST

AN

AN

ST

AN

CMOS General purpose I/O.

CMOS Capture/Compare/PWM.

CMOS PWM output.

AN

CMOS General purpose I/O.

Comparator negative input.

Comparator negative input.

Slave Select input.

LCD Analog output.

LCD Analog output.

A/D Channel input.

Capacitive sensing input.

CMOS USART2 asynchronous transmit.

CMOS USART2 synchronous clock.

CMOS Comparator output.

SEG43 — AN LCD Analog output.

Legend:

Note 1:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I

OD

2

= Open Drain

C™ = Schmitt Trigger input with I

2

C

XTAL = Crystal levels

Pin function is selectable via the APFCON register.

2010-2012 Microchip Technology Inc.

DS41414D-page 17

PIC16(L)F1946/47

TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED)

Name Function

Input

Type

Output

Type

Description

RG2/AN14/CPS14/RX2/DT2/

C3IN+/SEG44

RG3/AN13/CPS13/C3IN0-/

CCP4/P3D/SEG45

RG4/AN12/CPS12/C3IN1-/

CCP5/P1D/SEG26

RG2

AN14

CPS14

RX2

DT2

C3IN+

SEG44

RG3

AN13

CPS13

C3IN0-

CCP4

P3D

SEG45

RG4

AN12

ST

AN

AN

ST

ST

AN

ST

AN

AN

AN

ST

AN

AN

AN

ST

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

USART2 asynchronous input.

CMOS USART2 synchronous data.

— Comparator positive input.

AN LCD Analog output.

CMOS General purpose I/O.

A/D Channel input.

Capacitive sensing input.

— Comparator negative input.

CMOS Capture/Compare/PWM.

CMOS PWM output.

AN LCD Analog output.

CMOS General purpose I/O.

— A/D Channel input.

Capacitive sensing input.

Comparator negative input.

RG5/MCLR/V

PP

CPS12

C3IN1-

CCP5

P1D

SEG26

RG5

MCLR

V

PP

ST

ST

ST

HV

CMOS Capture/Compare/PWM.

CMOS PWM output.

AN

LCD Analog output.

General purpose input.

Master Clear with internal pull-up.

Programming voltage.

V

DD

V

SS

V

V

DD

SS

Power

Power

Positive supply.

Ground reference.

Legend:

Note 1:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I

OD

2

= Open Drain

C™ = Schmitt Trigger input with I

2

C

XTAL = Crystal levels

Pin function is selectable via the APFCON register.

DS41414D-page 18

2010-2012 Microchip Technology Inc.

2.0

ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

Relative addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See

Section 7.5 “Automatic Context Saving”

,

for more information.

2.2

16-level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a soft-

ware Reset. See section

Section 3.5 “Stack”

for more

details.

2.3

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing”

for more details.

2.4

Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 29.0 “Instruction Set Summary”

for more

details.

PIC16(L)F1946/1947

2010-2012 Microchip Technology Inc.

DS41414D-page 19

PIC16(L)F1946/1947

FIGURE 2-1: CORE BLOCK DIAGRAM

15

Configuration

15

Program Counter

Flash

Program

Memory

16-Level Stack

(15-bit)

Program

Bus

14

Program Memory

Read (PMR)

Instruction Reg

Direct Addr 7

15

15

8

Data Bus

RAM

8

5

12

RAM Addr

Addr MUX

12

Indirect

Addr

12

FSR0 Reg

STATUS Reg

3

MUX

OSC1/CLKIN

OSC2/CLKOUT

Instruction

Decode and

Control

Timing

Generation

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

8

ALU

W reg

Internal

Oscillator

Block

V

DD

V

SS

2010-2012 Microchip Technology Inc.

DS41414D-page 20

3.0

MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

- User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

• Data EEPROM memory

(1)

Note 1:

The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in

Section 11.0 “Data EEPROM and Flash

Program Memory Control”

.

PIC16(L)F1946/1947

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

• Stack

• Indirect Addressing

3.1

Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space.

Table 3-1 shows the memory sizes

implemented for the PIC16(L)F1946/47 family.

Accessing a location above these boundaries will cause a wrap-around within the implemented memory space.

The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures

3-1 and 3-2 ).

TABLE 3-1:

Device

PIC16(L)F1946

PIC16(L)F1947

DEVICE SIZES AND ADDRESSES

Program Memory Space (Words)

8,192

16,384

Last Program Memory Address

1FFFh

3FFFh

2010-2012 Microchip Technology Inc.

DS41414D-page 21

PIC16(L)F1946/1947

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1946

PC<14:0>

CALL, CALLW

RETURN, RETLW

Interrupt

, RETFIE

15

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

0000h

Interrupt Vector

Page 0

On-chip

Program

Memory

Page 1

Page 2

Page 3

Rollover to Page 0

0004h

0005h

07FFh

0800h

0FFFh

1000h

17FFh

1800h

1FFFh

2000h

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1947

PC<14:0>

CALL, CALLW

RETURN, RETLW

Interrupt

, RETFIE

15

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

Interrupt Vector

Page 0

On-chip

Program

Memory

Page 1

Page 2

Page 3

Page 4

0000h

0004h

0005h

07FFh

0800h

0FFFh

1000h

17FFh

1800h

1FFFh

2000h

Page 7

Rollover to Page 0

3FFFh

4000h

Rollover to Page 3

7FFFh

Rollover to Page 7

7FFFh

2010-2012 Microchip Technology Inc.

DS41414D-page 22

3.1.1

READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in program memory. The first method is to use tables of

RETLW

instructions. The second method is to set an

FSR to point to the program memory.

3.1.1.1

RETLW

Instruction

The

RETLW

instruction can be used to provide access to tables of constants. The recommended way to create

such a table is shown in Example 3-1 .

EXAMPLE 3-1:

constants

BRW

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

RETLW

INSTRUCTION

;Add Index in W to

;program counter to

;select data

;Index0 data

;Index1 data my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

CALL constants

;… THE CONSTANT IS IN W

The

BRW

instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the

BRW instruction is not available so the older table read method must be used.

PIC16(L)F1946/1947

2010-2012 Microchip Technology Inc.

DS41414D-page 23

PIC16(L)F1946/1947

3.1.1.2

Indirect Read with FSR

The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The

MOVIW

instruction will place the lower 8 bits of the addressed word in the W register.

Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete.

Example 3-2

demonstrates accessing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

constants

RETLW DATA0

RETLW DATA1

RETLW DATA2

;Index0 data

;Index1 data

RETLW DATA3 my_function

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF

MOVLW

FSR1L

HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.2

Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of

(

Figure 3-3

):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘

0

’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select

Registers (FSR). See

Section 3.6 “Indirect

Addressing”

for more information.

Data Memory uses a 12-bit address. The upper 7-bits of the address define the Bank address and the lower

5-bits select the registers/RAM in that bank.

3.2.1

CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These reg-

isters are listed below in Table 3-2 . For detailed infor-

mation, see

Table 3-4

.

TABLE 3-2: CORE REGISTERS

Addresses

x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh

BANKx

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

2010-2012 Microchip Technology Inc.

DS41414D-page 24

PIC16(L)F1946/1947

3.2.1.1

STATUS Register

The STATUS register, shown in

Register 3-1

, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than intended.

3.3

Register Definitions: Status

REGISTER 3-1: STATUS: STATUS REGISTER

bit 7

U-0

U-0

U-0

R-1/q

TO

For example,

CLRF STATUS

will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘

000u u1uu

’ (where u

= unchanged).

It is recommended, therefore, that only

BCF, BSF,

SWAPF

and

MOVWF

instructions are used to alter the

STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to

Section 29.0

“Instruction Set Summary”

).

Note 1:

The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction.

R-1/q

PD

R/W-0/u

Z

R/W-0/u

DC

(1)

R/W-0/u

C

(1)

bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0

Unimplemented:

Read as ‘

0

TO:

Time-out bit

1

= After power-up,

CLRWDT

instruction or

SLEEP

instruction

0

= A WDT time-out occurred

PD:

Power-down bit

1

= After power-up or by the

CLRWDT

instruction

0

= By execution of the

SLEEP

instruction

Z:

Zero bit

1

= The result of an arithmetic or logic operation is zero

0

= The result of an arithmetic or logic operation is not zero

DC:

Digit Carry/Digit Borrow bit (

ADDWF

,

ADDLW,SUBLW,SUBWF

instructions)

(1)

1

= A carry-out from the 4th low-order bit of the result occurred

0

= No carry-out from the 4th low-order bit of the result

C:

Carry/Borrow bit

(1)

(

ADDWF

,

ADDLW, SUBLW, SUBWF instructions)

(1)

1

= A carry-out from the Most Significant bit of the result occurred

0

= No carry-out from the Most Significant bit of the result occurred

Note 1:

For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (

RRF

,

RLF

) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

2010-2012 Microchip Technology Inc.

DS41414D-page 25

PIC16(L)F1946/1947

3.3.1

SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.

3.3.2

GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1

Linear Access to GPR

The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify

access to large memory structures. See

Section 3.6.2

“Linear Data Memory”

for more information.

3.3.3

COMMON RAM

There are 16 bytes of common RAM accessible from all banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

7-bit Bank Offset

Memory Region

00h

Core Registers

(12 bytes)

0Bh

0Ch

Special Function Registers

(20 bytes maximum)

1Fh

20h

General Purpose RAM

(80 bytes maximum)

6Fh

70h

7Fh

Common RAM

(16 bytes)

3.3.4

DEVICE MEMORY MAPS

The memory maps for the device family are as shown in

Table 3-3

.

TABLE 3-3:

Device

PIC16(L)F1946/47

MEMORY MAP TABLES

Banks

0-7

8-15

16-23

23-31

Table No.

Table 3-4

Table 3-5

, Table 3-8

Table 3-6

Table 3-7

, Table 3-9

2010-2012 Microchip Technology Inc.

DS41414D-page 26

TABLE 3-4:

BANK 0

PIC16(L)F1946/47 MEMORY MAP, BANKS 0-7

BANK 1 BANK 2 BANK 3

00Eh

00Fh

010h

011h

012h

013h

014h

015h

016h

017h

018h

019h

01Ah

01Bh

01Ch

01Dh

01Eh

007h

008h

009h

00Ah

00Bh

00Ch

00Dh

000h

001h

002h

003h

004h

005h

006h

01Fh

020h

PORTC

PORTD

PORTE

PIR1

PIR2

PIR3

PIR4

TMR0

TMR1L

TMR1H

T1CON

T1GCON

TMR2

PR2

T2CON

CPSCON0

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

PORTA

PORTB

CPSCON1

08Eh

08Fh

090h

091h

092h

093h

094h

095h

096h

097h

098h

099h

09Ah

09Bh

09Ch

09Dh

09Eh

087h

088h

089h

08Ah

08Bh

08Ch

08Dh

080h

081h

082h

083h

084h

085h

086h

09Fh

0A0h

TRISC

TRISD

TRISE

PIE1

PIE2

PIE3

PIE4

OPTION_REG

PCON

WDTCON

OSCTUNE

OSCCON

OSCSTAT

ADRESL

ADRESH

ADCON0

ADCON1

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

TRISA

TRISB

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

100h

101h

102h

103h

104h

105h

106h

11Fh

120h

LATC

LATD

LATE

CM1CON0

CM1CON1

CM2CON0

CM2CON1

CMOUT

BORCON

FVRCON

DACCON0

DACCON1

SRCON0

SRCON1

APFCON

CM3CON0

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

LATA

LATB

CM3CON1

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

180h

181h

182h

183h

184h

185h

186h

19Fh

1A0h

ANSELE

EEADRL

EEADRH

EEDATL

EEDATH

EECON1

EECON2

RC1REG

TX1REG

SP1BRGL

SP1BRGH

RC1STA

TX1STA

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

ANSELA

BAUD1CON

06Fh

070h

07Fh

Legend:

Note 1:

General

Purpose

Register

96 Bytes

0EFh

0F0h

General

Purpose

Register

80 Bytes

16Fh

170h

General

Purpose

Register

80 Bytes

Accesses

70h – 7Fh

Accesses

70h – 7Fh

0FFh 17Fh

= Unimplemented data memory locations, read as ‘

0

’.

Not available on PIC16F1946.

1EFh

1F0h

1FFh

General

Purpose

Register

80 Bytes

Accesses

70h – 7Fh

20Eh

20Fh

210h

211h

212h

213h

214h

215h

216h

217h

218h

219h

21Ah

21Bh

21Ch

21Dh

21Eh

207h

208h

209h

20Ah

20Bh

20Ch

20Dh

200h

201h

202h

203h

204h

205h

206h

21Fh

220h

26Fh

270h

27Fh

BANK 4

SSP1BUF

SSP1ADD

SSP1MSK

SSP1STAT

SSP1CON1

SSP1CON2

SSP1CON3

SSP2BUF

SSP2ADD

SSP2MSK

SSP2STAT

SSP2CON1

SSP2CON2

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

WPUB

SSP2CON3

28Eh

28Fh

290h

291h

292h

293h

294h

295h

296h

297h

298h

299h

29Ah

29Bh

29Ch

29Dh

29Eh

287h

288h

289h

28Ah

28Bh

28Ch

28Dh

280h

281h

282h

283h

284h

285h

286h

29Fh

2A0h

General

Purpose

Register

80 Bytes

2EFh

2F0h

Accesses

70h – 7Fh

2FFh

BANK 5

CCPR1L

CCPR1H

CCP1CON

PWM1CON

CCP1AS

PSTR1CON

CCPR2L

CCPR2H

CCP2CON

PWM2CON

CCP2AS

PSTR2CON

CCPTMRS0

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

PORTF

PORTG

CCPTMRS1

General

Purpose

Register

80 Bytes

Accesses

70h – 7Fh

BANK 6

30Eh

30Fh

310h

311h

312h

313h

314h

315h

316h

317h

318h

319h

31Ah

31Bh

31Ch

31Dh

31Eh

307h

308h

309h

30Ah

30Bh

30Ch

30Dh

300h

301h

302h

303h

304h

305h

306h

CCPR3L

CCPR3H

CCP3CON

PWM3CON

CCP3AS

PSTR3CON

CCPR4L

CCPR4H

CCP4CON

CCPR5L

CCPR5H

CCP5CON

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

TRISF

TRISG

31Fh —

320h General Purpose

Register

32Fh

16 Bytes

330h General Purpose

36Fh

Register

64 Bytes

(1)

370h

Accesses

70h – 7Fh

37Fh

38Eh

38Fh

390h

391h

392h

393h

394h

395h

396h

397h

398h

399h

39Ah

39Bh

39Ch

39Dh

39Eh

387h

388h

389h

38Ah

38Bh

38Ch

38Dh

380h

381h

382h

383h

384h

385h

386h

39Fh

3A0h

3EFh

3F0h

3FFh

General

Purpose

Register

80 Bytes

(1)

Accesses

70h – 7Fh

BANK 7

IOCBP

IOCBN

IOCBF

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

LATF

LATG

TABLE 3-5:

BANK 8

PIC16(L)F1946/47 MEMORY MAP, BANKS 8-15

BANK 9 BANK 10 BANK 11

41Bh

41Ch

41Dh

41Eh

41Fh

420h

414h

415h

416h

417h

418h

419h

41Ah

40Dh

40Eh

40Fh

410h

411h

412h

413h

406h

407h

408h

409h

40Ah

40Bh

40Ch

400h

401h

402h

403h

404h

405h

TMR4

PR4

T4CON

TMR6

PR6

T6CON

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

ANSELF

ANSELG

RC2REG

TX2REG

SP2BRGL

SP2BRGH

RC2STA

TX2STA

BAUD2CON

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

WPUG

494h

495h

496h

497h

498h

499h

49Ah

48Dh

48Eh

48Fh

490h

491h

492h

493h

49Bh

49Ch

49Dh

49Eh

49Fh

4A0h

486h

487h

488h

489h

48Ah

48Bh

48Ch

480h

481h

482h

483h

484h

485h

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

514h

515h

516h

517h

518h

519h

51Ah

50Dh

50Eh

50Fh

510h

511h

512h

513h

51Bh

51Ch

51Dh

51Eh

51Fh

520h

506h

507h

508h

509h

50Ah

50Bh

50Ch

500h

501h

502h

503h

504h

505h

594h

595h

596h

597h

598h

599h

59Ah

58Dh

58Eh

58Fh

590h

591h

592h

593h

59Bh

59Ch

59Dh

59Eh

59Fh

5A0h

586h

587h

588h

589h

58Ah

58Bh

58Ch

580h

581h

582h

583h

584h

585h

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

General

Purpose

Register

80 Bytes

(1)

General

Purpose

Register

80 Bytes

(1)

General

Purpose

Register

80 Bytes

(1)

General

Purpose

Register

80 Bytes

(1)

5EFh

5F0h

46Fh

470h

47Fh

Legend:

Note 1:

4EFh

4F0h

56Fh

570h

Accesses

70h – 7Fh

Accesses

70h – 7Fh

Accesses

70h – 7Fh

4FFh 57Fh

= Unimplemented data memory locations, read as ‘

0

Not available on PIC16F1946.

5FFh

Accesses

70h – 7Fh

BANK 12

600h

INDF0

601h

602h

INDF1

PCL

603h

604h

STATUS

FSR0L

605h

606h

607h

FSR0H

FSR1L

FSR1H

608h

609h

BSR

WREG

60Ah

60Bh

PCLATH

INTCON

60Ch

60Dh

60Eh

60Fh

610h

611h

612h

613h

614h

615h

616h

617h

618h

619h

61Ah

61Bh

61Ch

61Dh

61Eh

61Fh

620h General Purpose

Register

48 Bytes

(1)

694h

695h

696h

697h

698h

699h

69Ah

68Dh

68Eh

68Fh

690h

691h

692h

693h

69Bh

69Ch

69Dh

69Eh

69Fh

6A0h

686h

687h

688h

689h

68Ah

68Bh

68Ch

680h

681h

682h

683h

684h

685h

Unimplemented

Read as ‘

0

BANK 13

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

66Fh

670h

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

67Fh

6EFh

6F0h

6FFh

Accesses

70h – 7Fh

714h

715h

716h

717h

718h

719h

71Ah

70Dh

70Eh

70Fh

710h

711h

712h

713h

71Bh

71Ch

71Dh

71Eh

71Fh

720h

706h

707h

708h

709h

70Ah

70Bh

70Ch

700h

701h

702h

703h

704h

705h

76Fh

770h

77Fh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

BANK 14

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

794h

795h

796h

797h

798h

799h

79Ah

78Dh

78Eh

78Fh

790h

791h

792h

793h

79Bh

79Ch

79Dh

79Eh

79Fh

7A0h

786h

787h

788h

789h

78Ah

78Bh

78Ch

780h

781h

782h

783h

784h

785h

7EFh

7F0h

7FFh

See Table 3-8

Accesses

70h – 7Fh

BANK 15

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

TABLE 3-6:

80Eh

80Fh

810h

811h

812h

813h

814h

815h

816h

817h

818h

819h

81Ah

81Bh

81Ch

81Dh

81Eh

81Fh

820h

807h

808h

809h

80Ah

80Bh

80Ch

80Dh

800h

801h

802h

803h

804h

805h

806h

BANK 16

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

PIC16(L)F1946/47 MEMORY MAP, BANKS 16-23

88Eh

88Fh

890h

891h

892h

893h

894h

895h

896h

897h

898h

899h

89Ah

89Bh

89Ch

89Dh

89Eh

89Fh

8A0h

887h

888h

889h

88Ah

88Bh

88Ch

88Dh

880h

881h

882h

883h

884h

885h

886h

BANK 17

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

90Eh

90Fh

910h

911h

912h

913h

914h

915h

916h

917h

918h

919h

91Ah

91Bh

91Ch

91Dh

91Eh

91Fh

920h

907h

908h

909h

90Ah

90Bh

90Ch

90Dh

900h

901h

902h

903h

904h

905h

906h

BANK 18

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

98Eh

98Fh

990h

991h

992h

993h

994h

995h

996h

997h

998h

999h

99Ah

99Bh

99Ch

99Dh

99Eh

99Fh

9A0h

987h

988h

989h

98Ah

98Bh

98Ch

98Dh

980h

981h

982h

983h

984h

985h

986h

BANK 19

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

A0Eh

A0Fh

A10h

A11h

A12h

A13h

A14h

A15h

A16h

A17h

A18h

A19h

A1Ah

A1Bh

A1Ch

A1Dh

A1Eh

A1Fh

A20h

A07h

A08h

A09h

A0Ah

A0Bh

A0Ch

A0Dh

A00h

A01h

A02h

A03h

A04h

A05h

A06h

BANK 20

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

A8Eh

A8Fh

A90h

A91h

A92h

A93h

A94h

A95h

A96h

A97h

A98h

A99h

A9Ah

A9Bh

A9Ch

A9Dh

A9Eh

A9Fh

AA0h

A87h

A88h

A89h

A8Ah

A8Bh

A8Ch

A8Dh

A80h

A81h

A82h

A83h

A84h

A85h

A86h

BANK 21

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

B0Eh

B0Fh

B10h

B11h

B12h

B13h

B14h

B15h

B16h

B17h

B18h

B19h

B1Ah

B1Bh

B1Ch

B1Dh

B1Eh

B1Fh

B20h

B07h

B08h

B09h

B0Ah

B0Bh

B0Ch

B0Dh

B00h

B01h

B02h

B03h

B04h

B05h

B06h

BANK 22

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

BANK 23

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

B8Eh

B8Fh

B90h

B91h

B92h

B93h

B94h

B95h

B96h

B97h

B98h

B99h

B9Ah

B9Bh

B9Ch

B9Dh

B9Eh

B9Fh

BA0h

B87h

B88h

B89h

B8Ah

B8Bh

B8Ch

B8Dh

B80h

B81h

B82h

B83h

B84h

B85h

B86h

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

86Fh

870h

87Fh

Legend:

8EFh

8F0h

96Fh

970h

Accesses

70h – 7Fh

Accesses

70h – 7Fh

Accesses

70h – 7Fh

8FFh 97Fh

= Unimplemented data memory locations, read as ‘

0

’.

9EFh

9F0h

9FFh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

A6Fh

A70h

A7Fh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

AEFh

AF0h

AFFh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

B6Fh

B70h

B7Fh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

BEFh

BF0h

BFFh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

TABLE 3-7:

BANK 24

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

C16h

C17h

C18h

C19h

C1Ah

C1Bh

C1Ch

C1Dh

C1Eh

C1Fh

C20h

C0Fh

C10h

C11h

C12h

C13h

C14h

C15h

C00h

C01h

C02h

C03h

C04h

C05h

C06h

C07h

C08h

C09h

C0Ah

C0Bh

C0Ch

C0Dh

C0Eh

PIC16(L)F1946/47 MEMORY MAP, BANKS 24-31

C96h

C97h

C98h

C99h

C9Ah

C9Bh

C9Ch

C9Dh

C9Eh

C9Fh

CA0h

C8Fh

C90h

C91h

C92h

C93h

C94h

C95h

C80h

C81h

C82h

C83h

C84h

C85h

C86h

C87h

C88h

C89h

C8Ah

C8Bh

C8Ch

C8Dh

C8Eh

BANK 25

D16h

D17h

D18h

D19h

D1Ah

D1Bh

D1Ch

D1Dh

D1Eh

D1Fh

D20h

D0Fh

D10h

D11h

D12h

D13h

D14h

D15h

D00h

D01h

D02h

D03h

D04h

D05h

D06h

D07h

D08h

D09h

D0Ah

D0Bh

D0Ch

D0Dh

D0Eh

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

BANK 26

D96h

D97h

D98h

D99h

D9Ah

D9Bh

D9Ch

D9Dh

D9Eh

D9Fh

DA0h

D8Fh

D90h

D91h

D92h

D93h

D94h

D95h

D80h

D81h

D82h

D83h

D84h

D85h

D86h

D87h

D88h

D89h

D8Ah

D8Bh

D8Ch

D8Dh

D8Eh

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

BANK 27

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

E16h

E17h

E18h

E19h

E1Ah

E1Bh

E1Ch

E1Dh

E1Eh

E1Fh

E20h

E0Fh

E10h

E11h

E12h

E13h

E14h

E15h

E00h

E01h

E02h

E03h

E04h

E05h

E06h

E07h

E08h

E09h

E0Ah

E0Bh

E0Ch

E0Dh

E0Eh

BANK 28

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

E96h

E97h

E98h

E99h

E9Ah

E9Bh

E9Ch

E9Dh

E9Eh

E9Fh

EA0h

E8Fh

E90h

E91h

E92h

E93h

E94h

E95h

E80h

E81h

E82h

E83h

E84h

E85h

E86h

E87h

E88h

E89h

E8Ah

E8Bh

E8Ch

E8Dh

E8Eh

BANK 29

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

BANK 30

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

F16h

F17h

F18h

F19h

F1Ah

F1Bh

F1Ch

F1Dh

F1Eh

F1Fh

F20h

F0Fh

F10h

F11h

F12h

F13h

F14h

F15h

F00h

F01h

F02h

F03h

F04h

F05h

F06h

F07h

F08h

F09h

F0Ah

F0Bh

F0Ch

F0Dh

F0Eh

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

C6Fh

C70h

CFFh

Legend:

CEFh

CF0h

D6Fh

D70h

Accesses

70h – 7Fh

Accesses

70h – 7Fh

Accesses

70h – 7Fh

CFFh D7Fh

= Unimplemented data memory locations, read as ‘

0

’.

DEFh

DF0h

DFFh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

E6Fh

E70h

E7Fh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

EEFh

EF0h

EFFh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

F6Fh

F70h

F7Fh

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

FEFh

FF0h

FFFh

F96h

F97h

F98h

F99h

F9Ah

F9Bh

F9Ch

F9Dh

F9Eh

F9Fh

FA0h

F8Fh

F90h

F91h

F92h

F93h

F94h

F95h

F80h

F81h

F82h

F83h

F84h

F85h

F86h

F87h

F88h

F89h

F8Ah

F8Bh

F8Ch

F8Dh

F8Eh

BANK 31

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

See Table 3-9

Accesses

70h – 7Fh

TABLE 3-8: PIC16(L)F1946/47 MEMORY

MAP, BANK 15

Bank 15

LCDCON

LCDPS

LCDREF

LCDCST

LCDRL

LCDSE0

LCDSE1

LCDSE2

LCDSE3

LCDSE4

LCDSE5

LCDDATA0

LCDDATA1

LCDDATA2

LCDDATA3

LCDDATA4

LCDDATA5

LCDDATA6

LCDDATA7

LCDDATA8

LCDDATA9

LCDDATA10

LCDDATA11

LCDDATA12

LCDDATA13

LCDDATA14

LCDDATA15

LCDDATA16

LCDDATA17

LCDDATA18

LCDDATA19

LCDDATA20

LCDDATA21

LCDDATA22

LCDDATA23

791h

792h

793h

794h

795h

796h

797h

798h

799h

79Ah

79Bh

79Ch

79Dh

79Eh

7ACh

7ADh

7AEh

7AFh

7B0h

7B1h

7B2h

7B3h

7B4h

7B5h

7B6h

7B7h

79Fh

7A0h

7A1h

7A2h

7A3h

7A4h

7A5h

7A6h

7A7h

7A8h

7A9h

7AAh

7ABh

7B8h

Unimplemented

Read as ‘

0

Legend:

7EFh

= Unimplemented data memory locations, read as ‘

0

’.

PIC16(L)F1946/1947

TABLE 3-9: PIC16(L)F1946/47 MEMORY

MAP, BANK 31

FEAh

FEBh

FECh

FEDh

FEEh

FEFh

Legend:

F93h

F94h

F95h

F96h

F97h

F98h

F99h

F9Ah

F8Ch

F8Dh

F8Eh

F8Fh

F90h

F91h

F92h

FA2h

FA3h

FA4h

FA5h

FA6h

FA7h

FA8h

FA9h

FAAh

FABh

F9Bh

F9Ch

F9Dh

F9Eh

F9Fh

FA0h

FA1h

FDFh

FC0h

FDFh

FE0h

FE1h

FE2h

FE3h

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

Bank 31

STATUS_SHAD

WREG_SHAD

BSR_SHAD

PCLATH_SHAD

FSR0L_SHAD

FSR0H_SHAD

FSR1L_SHAD

FSR1H_SHAD

STKPTR

TOSL

TOSH

= Unimplemented data memory locations, read as ‘

0

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 31

PIC16(L)F1946/1947

3.3.5

SPECIAL FUNCTION REGISTERS

SUMMARY

The Special Function Register Summary for the device family are as follows:

Device

PIC16(L)F1946/1947

Bank(s)

5

6

7

8

9-14

15

16-30

31

2

3

4

0

1

Page No.

41

43

44

38

39

40

46

47

33

34

35

36

37

DS41414D-page 32

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 0

000h

001h

(2)

(2)

002h

(2)

003h

(2)

004h

(2)

005h

(2)

006h

(2)

007h

(2)

008h

(2)

009h

(2)

00Ah

(1, 2)

00Bh

(2)

00Ch

00Dh

00Eh

00Fh

010h

011h

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

PORTA

PORTB

PORTC

PORTD

PORTE

PIR1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

— —

PD

BSR<4:0>

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE TMR0IF

PORTA Data Latch when written: PORTA pins when read

PORTB Data Latch when written: PORTB pins when read

PORTC Data Latch when written: PORTC pins when read

PORTD Data Latch when written: PORTD pins when read

PORTE Data Latch when written: PORTE pins when read

TMR1GIF ADIF RCIF TXIF SSPIF

OSFIF

C2IF

CCP5IF

Timer0 Module Register

C1IF

CCP4IF

RC2IF

EEIF

CCP3IF

TX2IF

BCLIF

TMR6IF

Z DC

INTF

C

IOCIF xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx xxxx uuuu

0000 0000 0000 0000

012h

013h

014h

015h

016h

017h

018h

019h

PIR2

PIR3

PIR4

TMR0

TMR1L

TMR1H

T1CON

T1GCON

CCP1IF

LCDIF

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TMR1CS<1:0>

TMR1GE T1GPOL

T1CKPS<1:0>

T1GTM T1GSPM

T1OSCEN

T1GGO/

DONE

T1SYNC

T1GVAL

TMR2IF

C3IF

TMR4IF

BCL2IF

TMR1IF

CCP2IF

SSP2IF

TMR1ON

T1GSS<1:0>

0000 0000 0000 0000

-000 0-0- -000 0-0-

--00 --00 --00 --00 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

0000 00-0 uuuu uu-u

0000 0x00 uuuu uxuu

01Ah

01Bh

TMR2

PR2

Timer 2 Module Register

Timer 2 Period Register

0000 0000 0000 0000

1111 1111 1111 1111

01Ch

01Dh

T2CON

Unimplemented

T2OUTPS<3:0> TMR2ON T2CKPS<1:0>

-000 0000 -000 0000

— —

01Eh

01Fh

Legend:

Note 1:

2:

3:

CPSCON0 CPSON CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS

00-- 0000 00-- 0000

CPSCON1 — — — CPSCH<4:0>

---0 0000 ---0 0000 x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

Shaded locations are unimplemented, read as ‘

0

’.

0

’, r

= reserved.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 33

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 1

080h

081h

(2)

(2)

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

082h

(2)

083h

(2)

084h

(2)

085h

(2)

086h

(2)

087h

(2)

088h

(2)

089h

(2)

08Ah

(1, 2)

08Bh

(2)

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

— —

PD

BSR<4:0>

Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE

Z

TMR0IF

DC

INTF

C

IOCIF

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

08Ch

08Dh

TRISA

TRISB

PORTA Data Direction Register

PORTB Data Direction Register

1111 1111 1111 1111

1111 1111 1111 1111

08Eh

08Fh

TRISC

TRISD

PORTC Data Direction Register

PORTD Data Direction Register

1111 1111 1111 1111

1111 1111 1111 1111

090h

091h

092h

093h

094h

095h

096h

097h

098h

099h

09Ah

09Bh

09Ch

09Dh

09Eh

09Fh

Legend:

Note 1:

2:

3:

TRISE

PIE1

PIE2

PIE3

PIE4

OPTION_REG

PCON

WDTCON

OSCTUNE

OSCCON

OSCSTAT

ADRESL

PORTE Data Direction Register

TMR1GIE

OSFIE

WPUEN

STKOVF

SPLLEN

T1OSCR

ADIE

C2IE

CCP5IE

INTEDG

STKUNF

PLLR

A/D Result Register Low

RCIE

C1IE

CCP4IE

RC2IE

T0CS

OSTS

TXIE

EEIE

CCP3IE

TX2IE

T0SE

IRCF<3:0>

HFIOFR

SSPIE

BCLIE

TMR6IE

PSA

RMCLR

WDTPS<4:0>

TUN<5:0>

HFIOFL

CCP1IE

LCDIE

RI

MFIOFR

TMR2IE

C3IE

TMR4IE

BCL2IE

PS<2:0>

POR

TMR1IE

CCP2IE

SSP2IE

BOR

SWDTEN

SCS<1:0>

LFIOFR

HFIOFS

1111 1111 1111 1111

0000 0000 0000 0000

0000 0000 0000 0000

-000 0-0- -000 0-0-

--00 --00 --00 --00

1111 1111 1111 1111

00-- 11qq qq-- qquu

--01 0110 --01 0110

--00 0000 --00 0000

0011 1-00 0011 1-00

00q0 0q0- qqqq qq0xxxx xxxx uuuu uuuu

ADRESH

ADCON0

ADCON1

A/D Result Register High

ADFM

Unimplemented

ADCS<2:0>

CHS<4:0>

— ADNREF xxxx xxxx uuuu uuuu

GO/DONE ADON

-000 0000 -000 0000

ADPREF1 ADPREF0

0000 -000 0000 -000

— — x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 34

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 2

100h

101h

(2)

(2)

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

102h

(2)

103h

(2)

104h

(2)

105h

(2)

106h

(2)

107h

(2)

108h

(2)

109h

(2)

10Ah

(1, 2)

10Bh

(2)

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

— —

PD

BSR<4:0>

Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE

Z

TMR0IF

DC

INTF

C

IOCIF

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

10Ch

10Dh

LATA

LATB

PORTA Data Latch

PORTB Data Latch xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

10Eh

10Fh

LATC

LATD

PORTC Data Latch

PORTD Data Latch xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

LATE

CM1CON0

CM1CON1

CM2CON0

CM2CON1

CMOUT

BORCON

FVRCON

DACCON0

DACCON1

SRCON0

SRCON1

PORTE Data Latch

C1ON

C1INTP

C2ON

C2INTP

SBOREN

FVREN

DACEN

SRLEN

SRSPE

C1OUT

C1INTN

C2OUT

C2INTN

Unimplemented

FVRRDY

DACLPS

SRCLK2

SRSCKE

C1OE

C1PCH1

C2OE

C2PCH1

TSEN

DACOE

SRCLK1

SRSC2E

C1POL

C1PCH0

C2POL

C2PCH0

TSRNG

SRCLK0

SRSC1E

CDAFVR1 CDAFVR0

DACPSS<1:0>

SRQEN

DACR<4:0>

SRNQEN

SRRPE

C1SP

C2SP

MC3OUT

SRRCKE

C1HYS

C2HYS

C1SYNC

C1NCH<1:0>

C2SYNC

C2NCH<1:0>

MC2OUT MC1OUT xxxx xxxx uuuu uuuu

0000 -100 0000 -100

0000 --00 0000 --00

0000 -100 0000 -100

0000 --00 0000 --00

---- -000 ---- -000

— BORRDY

1--- ---q u--- ---u

ADFVR<1:0>

0q00 0000 0q00 0000

— DACNSS

000- 00-0 000- 00-0

SRPS

SRRC2E

SRPR

SRRC1E

---0 0000 ---0 0000

0000 0000 0000 0000

0000 0000 0000 0000

— —

11Dh APFCON P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL

0000 0000 0000 0000

11Eh

11Fh

Legend:

Note 1:

2:

3:

CM3CON0 C3ON C3OUT C3OE C3POL — C3SP C3HYS C3SYNC

0000 -100 0000 -100

CM3CON1 C3INTP C3INTN C3PCH1 C3PCH0 — — C3NCH<1:0>

0000 --00 0000 --00 x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 35

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 3

180h

181h

(2)

(2)

182h

(2)

183h

(2)

184h

(2)

185h

(2)

186h

(2)

187h

(2)

188h

(2)

189h

(2)

18Ah

(1, 2)

18Bh

(2)

18Ch

18Dh

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

ANSELA

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

— —

PD Z

BSR<4:0>

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE TMR0IF

Unimplemented

— ANSA5 — ANSA3 ANSA2

DC

INTF

ANSA1

C

IOCIF

ANSA0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

--1- 1111 --1- 1111

— —

18Eh

18Fh

Unimplemented

Unimplemented

190h

191h

192h

193h

194h

195h

196h

197h

198h

ANSELE

EEADRL

EEADRH

EEDATL

EEDATH

EECON1

EECON2

— — — — — ANSE2

EEPROM / Program Memory Address Register Low Byte

(3)

EEPROM / Program Memory Address Register High Byte

EEPROM / Program Memory Read Data Register Low Byte

EEPGD

Unimplemented

Unimplemented

CFGS

EEPROM / Program Memory Read Data Register High Byte

EEPROM control register 2

LWLO FREE WRERR WREN

ANSE1

WR

ANSE0

RD

---- -111 ---- -111

0000 0000 0000 0000

1000 0000 1000 0000 xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

0000 x000 0000 q000

0000 0000 0000 0000

199h RC1REG USART Receive Data Register

0000 0000 0000 0000

19Ah TX1REG USART Transmit Data Register

0000 0000 0000 0000

19Bh SP1BRGL EUSART1 Baud Rate Generator, Low Byte

0000 0000 0000 0000

19Ch SP1BRGH EUSART1 Baud Rate Generator, High Byte

0000 0000 0000 0000

19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

0000 000x 0000 000x

19Eh

19Fh

Legend:

Note 1:

2:

3:

TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

0000 0010 0000 0010

BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN

01-0 0-00 01-0 0-00 x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 36

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 4

200h

201h

(2)

(2)

202h

(2)

203h

(2)

204h

(2)

205h

(2)

206h

(2)

207h

(2)

208h

(2)

209h

(2)

20Ah

(1, 2)

20Bh

(2)

20Ch

20Dh

20Eh

20Fh

210h

211h

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

WPUB

SSP1BUF

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

PD Z

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

— — BSR<4:0>

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE TMR0IF

Unimplemented

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2

Unimplemented

Unimplemented

Unimplemented

DC

INTF

WPUB1

C

IOCIF

WPUB0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

— —

1111 1111 1111 1111

Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

212h SSP1ADD

ADD<7:0> 0000 0000 0000 0000

213h

214h

215h

216h

217h

218h

219h

SSP1MSK

SSP1STAT

SSP1CON1

SSP1CON2

SSP1CON3

SSP2BUF

SMP

WCOL

GCEN

ACKTIM

Unimplemented

CKE

SSPOV

ACKSTAT

PCIE

D/A

SSPEN

ACKDT

SCIE

MSK<7:0>

P

CKP

ACKEN

BOEN

S

RCEN

SDAHT

R/W

SSPM<3:0>

PEN

SBCDE

UA

RSEN

AHEN

BF

SEN

DHEN

1111 1111 1111 1111

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

— —

Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

21Ah SSP2ADD

ADD<7:0> 0000 0000 0000 0000

21Bh SSP2MSK

MSK<7:0>

1111 1111 1111 1111

21Ch SSP2STAT SMP CKE D/A P S R/W UA BF

0000 0000 0000 0000

21Dh SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0>

0000 0000 0000 0000

21Eh

21Fh

Legend:

Note 1:

2:

3:

SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

0000 0000 0000 0000

SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

0000 0000 0000 0000 x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 37

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 5

280h

281h

(2)

(2)

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

282h

(2)

283h

(2)

284h

(2)

285h

(2)

286h

(2)

287h

(2)

288h

(2)

289h

(2)

28Ah

(1, 2)

28Bh

(2)

28Ch

28Dh

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

PORTF

PORTG

Program Counter (PC) Least Significant Byte

— — —

TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

PD

BSR<4:0>

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE

PORTF Data Latch when written: PORTF pins when read

— — RG5 RG4 RG3

Z

TMR0IF

RG2

DC

INTF

RG1

C

IOCIF

RG0

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

— — 28Eh

28Fh

290h

291h

CCPR1L

Unimplemented

Unimplemented

Unimplemented

Capture/Compare/PWM Register 1 (LSB)

292h

293h

294h

295h

296h

297h

CCPR1H

CCP1CON

PWM1CON

CCP1AS

PSTR1CON

Capture/Compare/PWM Register 1 (MSB)

P1M<1:0> DC1B<1:0>

P1RSEN

CCP1ASE

Unimplemented

CCP1AS<2:0>

— STR1SYNC

P1DC<6:0>

PSS1AC<1:0>

STR1D

CCP1M<3:0>

STR1C

PSS1BD<1:0>

STR1B STR1A xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

---0 0001 ---0 0001

— —

298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

29Ah CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0>

0000 0000 0000 0000

29Bh

29Ch

29Dh

29Eh

PWM2CON

CCP2AS

PSTR2CON

CCPTMRS0

P2RSEN

CCP2ASE

C4TSEL1

C4TSEL0

CCP2AS<2:0>

C3TSEL1

STR2SYNC

C3TSEL0

P2DC<6:0>

PSS2AC<1:0>

STR2D

C2TSEL1

STR2C

C2TSEL0

0000 0000 0000 0000

PSS2BD<1:0>

0000 0000 0000 0000

STR2B STR2A

---0 0001 ---0 0001

C1TSEL1 C1TSEL0

0000 0000 0000 0000

29Fh

Legend:

Note 1:

2:

3:

CCPTMRS1 — — — — — — C5TSEL<1:0>

---- --00 ---- --00 x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 38

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 6

300h

301h

(2)

(2)

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

302h

(2)

303h

(2)

304h

(2)

305h

(2)

306h

(2)

307h

(2)

308h

(2)

309h

(2)

30Ah

(1, 2)

30Bh

(2)

30Ch

30Dh

30Eh

30Fh

310h

311h

312h

313h

314h

315h

316h

317h

318h

319h

31Ah

31Bh

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

TRISF

TRISG

CCPR3L

CCPR3H

CCP3CON

PWM3CON

CCP3AS

PSTR3CON

CCPR4L

CCPR4H

CCP4CON

Program Counter (PC) Least Significant Byte

Working Register

P3RSEN

CCP3ASE

Unimplemented

Capture/Compare/PWM Register 4 (LSB)

Capture/Compare/PWM Register 4 (MSB)

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Capture/Compare/PWM Register 3 (LSB)

CCP3AS<2:0>

TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

PD

BSR<4:0>

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE

PORTF Data Direction Register

— — TRISG5 TRISG4

Capture/Compare/PWM Register 3 (MSB)

P3M<1:0> DC3B<1:0>

STR3SYNC

DC4B<1:0>

TRISG3

STR3D

Z

TMR0IF

TRISG2

DC

INTF

TRISG1

CCP3M<1:0>

P3DC<6:0>

PSS3AC<1:0>

STR3C

PSS3BD<1:0>

STR3B

CCP4M<3:0>

C

IOCIF

TRISG0

STR3A

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

1111 1111 1111 1111

--11 1111 --11 1111

— —

— xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

---0 0001 ---0 0001

— — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

--00 0000 --00 0000

— —

31Ch

31Dh

31Eh

31Fh

Legend:

Note 1:

2:

3:

CCPR5L

CCPR5H

Capture/Compare/PWM Register 5 (LSB)

Capture/Compare/PWM Register 5 (MSB) xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

CCP5CON

Unimplemented

— DC5B<1:0> CCP5M<3:0>

--00 0000 --00 0000

— — x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 39

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 7

380h

381h

(2)

(2)

382h

(2)

383h

(2)

384h

(2)

385h

(2)

386h

(2)

387h

(2)

388h

(2)

389h

(2)

38Ah

(1, 2)

38Bh

(2)

38Ch

38Dh

38Eh

38Fh

390h

391h

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

LATF

LATG

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

— —

PD Z

BSR<4:0>

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE TMR0IF

PORTF Data Latch

— — LATG5 LATG4 LATG3 LATG2

DC

INTF

LATG1

C

IOCIF

LATG0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

— —

392h

393h

394h

395h

396h

397h

398h

399h

39Ah

39Bh

39Ch

39Dh

IOCBP

IOCBN

IOCBF

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

IOCBP7

IOCBN7

IOCBP6

IOCBN6

IOCBF7 IOCBF6

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

IOCBP5

IOCBN5

IOCBF5

IOCBP4

IOCBN4

IOCBF4

IOCBP3

IOCBN3

IOCBF3

IOCBP2

IOCBN2

IOCBF2

IOCBP1

IOCBN1

IOCBF1

IOCBP0

IOCBN0

IOCBF0

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

— —

39Eh

39Fh

Legend:

Note 1:

2:

3:

Unimplemented

Unimplemented

— x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 40

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 8

400h

401h

(2)

(2)

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

402h

(2)

403h

(2)

404h

(2)

405h

(2)

406h

(2)

407h

(2)

408h

(2)

409h

(2)

40Ah

(1, 2)

40Bh

(2)

40Ch

40Dh

40Eh

40Fh

410h

411h

412h

413h

414h

415h

416h

417h

418h

419h

41Ah

41Bh

41Ch

41Dh

41Eh

41Fh

Legend:

Note 1:

2:

3:

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

ANSELF

ANSELG

TMR4

PR4

T4CON

TMR6

PR6

T6CON

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

— — — TO PD Z DC C

---1 1000 ---q quuu

Indirect Data Memory Address 0 Low Pointer

0000 0000 uuuu uuuu

Indirect Data Memory Address 0 High Pointer

0000 0000 0000 0000

Indirect Data Memory Address 1 Low Pointer

0000 0000 uuuu uuuu

Indirect Data Memory Address 1 High Pointer

0000 0000 0000 0000

— — — BSR<4:0>

---0 0000 ---0 0000

Working Register

0000 0000 uuuu uuuu

ANSELF7

Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE

ANSELF6

Unimplemented

TMR0IE

ANSELF5

INTE

ANSELF4

ANSELG4

IOCIE

ANSELF3

ANSELG3

-000 0000 -000 0000

TMR0IF INTF

ANSELG2 ANSELG1

IOCIF

0000 000x 0000 000u

ANSELF2 ANSELF1 ANSELF0

1111 1111 1111 1111

---1 111- ---1 111-

— —

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Timer 4 Module Register

Timer 4 Period Register

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Timer 6 Module Register

Timer 6 Period Register

Unimplemented

T4OUTPS<3:0>

T6OUTPS<3:0>

TMR4ON

TMR6ON

T4CKPS

T6CKPS

<1:0>

<1:0>

0000 0000 0000 0000

1111 1111 1111 1111

-000 0000 -000 0000

0000 0000 0000 0000

1111 1111 1111 1111

-000 0000 -000 0000

— x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 41

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 9

480h

481h

(2)

(2)

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

482h

(2)

483h

(2)

404h

(2)

485h

(2)

486h

(2)

487h

(2)

488h

(2)

489h

(2)

48Ah

(1, 2)

48Bh

(2)

48Ch

48Dh

48Eh

48Fh

490h

491h

492h

493h

494h

495h

496h

497h

498h

499h

49Ah

49Bh

49Ch

49Dh

49Eh

49Fh

Legend:

Note 1:

2:

3:

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

Program Counter (PC) Least Significant Byte

Working Register

TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

PD Z

BSR<4:0>

DC C

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

PCLATH

INTCON

WPUG

RC2REG

TX2REG

SP2BRGL

SP2BRGH

RC2STA

TX2STA

BAUD2CON

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE

Unimplemented

Unimplemented

Unimplemented

Unimplemented

TMR0IE

WPUG5

USART Receive Data Register

USART Transmit Data Register

SPEN

CSRC

ABDOVF

RX9

TX9

RCIDL

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

EUSART2 Baud Rate Generator, Low Byte

EUSART2 Baud Rate Generator, High Byte

SREN

TXEN

INTE

CREN

SYNC

SCKP

IOCIE

ADDEN

SENDB

BRG16

TMR0IF

FERR

BRGH

INTF

OERR

TRMT

WUE

IOCIF

RX9D

TX9D

ABDEN

-000 0000 -000 0000

0000 000x 0000 000u

— —

--1- ---- --1- ----

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 000x 0000 000x

0000 0010 0000 0010

01-0 0-00 01-0 0-00

Unimplemented — x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 42

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

x03h/ x83h

(2)

x04h/ x84h

(2)

x05h/ x85h

(2)

x06h/ x86h

(2)

Banks 10-14

x00h/ x80h

(2)

INDF0

INDF1 x00h/ x81h

(2)

x02h/ x82h

(2)

PCL

STATUS

FSR0L

FSR0H

FSR1L

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu x07h/ x87h

(2)

x08h/ x88h

(2)

FSR1H

BSR

Indirect Data Memory Address 1 High Pointer

— — — BSR<4:0>

0000 0000 0000 0000

---0 0000 ---0 0000 x09h/ x89h

(2)

WREG x0Ah/ x8Ah

(1),(2)

PCLATH

INTCON x0Bh/ x8Bh

(2)

x0Ch/ x8Ch

— x1Fh/ x9Fh

Legend:

Note 1:

2:

3:

Working Register

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE

Unimplemented

TMR0IE INTE IOCIE TMR0IF INTF IOCIF

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

— x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 43

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 15

780h

781h

(2)

(2)

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

782h

(2)

783h

(2)

784h

(2)

785h

(2)

786h

(2)

787h

(2)

788h

(2)

789h

(2)

78Ah

(1, 2)

78Bh

(2)

78Ch

78Dh

78Eh

78Fh

790h

791h

792h

793h

794h

795h

796h

797h

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

LCDCON

LCDPS

LCDREF

LCDCST

LCDRL

Program Counter (PC) Least Significant Byte

— — —

WERR

LCDA

LCDIRI

LRLBP

TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

Unimplemented

Unimplemented

Unimplemented

LCDEN SLPEN

WFT

LCDIRE

BIASMD

LCDIRS

LRLAP

<1:0>

Unimplemented

Unimplemented

WA

<1:0>

PD

Z

BSR<4:0>

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE TMR0IF

Unimplemented

Unimplemented

DC

INTF

LCDCST

<2:0>

LRLAT

<2:0>

C

IOCIF

CS

<1:0>

VLCD3PE

LMUX

<1:0>

LP

<3:0>

VLCD2PE VLCD1PE —

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

000- 0011 000- 0011

0000 0000 0000 0000

000- 000- 000- 000-

---- -000 ---- -000

0000 -000 0000 -000

798h

799h

LCDSE0

LCDSE1

SE<7:0>

SE<15:8>

0000 0000 uuuu uuuu

0000 0000 uuuu uuuu

79Ah

79Bh

79Ch

79Dh

79Eh

79Fh

7A0h

7A1h

7A2h

7A3h

7A4h

7A5h

Legend:

Note 1:

2:

3:

LCDSE2

LCDSE3

SE<23:16>

SE<31:24>

0000 0000 uuuu uuuu

0000 0000 uuuu uuuu

LCDSE4

LCDSE5

LCDDATA0

LCDDATA1

LCDDATA2

LCDDATA3

LCDDATA4

LCDDATA5

Unimplemented

Unimplemented

SEG7

COM0

SEG15

COM0

SEG23

COM0

SEG7

COM1

SEG15

COM1

SEG23

COM1

SEG6

COM0

SEG14

COM0

SEG22

COM0

SEG6

COM1

SEG14

COM1

SEG22

COM1

SEG5

COM0

SEG13

COM0

SEG21

COM0

SEG5

COM1

SEG13

COM1

SEG21

COM1

SE<39:32>

SEG4

COM0

SEG12

COM0

SEG20

COM0

SEG4

COM1

SEG12

COM1

SEG20

COM1

SE<45:40>

SEG3

COM0

SEG11

COM0

SEG19

COM0

SEG3

COM1

SEG11

COM1

SEG19

COM1

SEG2

COM0

SEG10

COM0

SEG18

COM0

SEG2

COM1

SEG10

COM1

SEG18

COM1

SEG1

COM0

SEG9

COM0

SEG17

COM0

SEG1

COM1

SEG9

COM1

SEG17

COM1

SEG0

COM0

SEG8

COM0

SEG16

COM0

SEG0

COM1

SEG8

COM1

SEG16

COM1

0000 0000 uuuu uuuu

--00 0000 --uu uuuu

— xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 44

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 15 (Continued)

7A6h

7A7h

7A8h

7A9h

7AAh

7ABh

7ACh

7ADh

7AEh

7AFh

7B0h

7B1h

7B2h

7B3h

7B4h

7B5h

7B6h

7B7h

LCDDATA6

LCDDATA7

LCDDATA8

LCDDATA9

LCDDATA10

LCDDATA11

LCDDATA12

LCDDATA13

LCDDATA14

LCDDATA15

LCDDATA16

LCDDATA17

LCDDATA18

LCDDATA19

LCDDATA20

LCDDATA21

LCDDATA22

LCDDATA23

SEG7

COM2

SEG15

COM2

SEG23

COM2

SEG7

COM3

SEG15

COM3

SEG23

COM3

SEG31

COM0

SEG39

COM0

SEG31

COM1

SEG39

COM1

SEG31

COM2

SEG39

COM2

SEG31

COM3

SEG39

COM3

SEG6

COM2

SEG14

COM2

SEG22

COM2

SEG6

COM3

SEG14

COM3

SEG22

COM3

SEG30

COM0

SEG38

COM0

SEG30

COM1

SEG38

COM1

SEG30

COM2

SEG38

COM2

SEG30

COM3

SEG38

COM3

SEG45

COM0

SEG29

COM1

SEG37

COM1

SEG45

COM1

SEG29

COM2

SEG37

COM2

SEG45

COM2

SEG29

COM3

SEG37

COM3

SEG45

COM3

SEG5

COM2

SEG13

COM2

SEG21

COM2

SEG5

COM3

SEG13

COM3

SEG21

COM3

SEG29

COM0

SEG37

COM0

SEG44

COM0

SEG28

COM1

SEG36

COM1

SEG44

COM1

SEG28

COM2

SEG36

COM2

SEG44

COM2

SEG28

COM3

SEG36

COM3

SEG44

COM3

SEG4

COM2

SEG12

COM2

SEG20

COM2

SEG4

COM3

SEG12

COM3

SEG20

COM3

SEG28

COM0

SEG36

COM0

SEG43

COM0

SEG27

COM1

SEG35

COM1

SEG43

COM1

SEG27

COM2

SEG35

COM2

SEG43

COM2

SEG27

COM3

SEG35

COM3

SEG43

COM3

SEG3

COM2

SEG11

COM2

SEG19

COM2

SEG3

COM3

SEG11

COM3

SEG19

COM3

SEG27

COM0

SEG35

COM0

SEG42

COM0

SEG26

COM1

SEG34

COM1

SEG42

COM1

SEG26

COM2

SEG34

COM2

SEG42

COM2

SEG26

COM3

SEG34

COM3

SEG42

COM3

SEG2

COM2

SEG10

COM2

SEG18

COM2

SEG2

COM3

SEG10

COM3

SEG18

COM3

SEG26

COM0

SEG34

COM0

SEG41

COM0

SEG25

COM1

SEG33

COM1

SEG41

COM1

SEG25

COM2

SEG33

COM2

SEG41

COM2

SEG25

COM3

SEG33

COM3

SEG41

COM3

SEG1

COM2

SEG9

COM2

SEG17

COM2

SEG1

COM3

SEG9

COM3

SEG17

COM3

SEG25

COM0

SEG33

COM0

SEG40

COM0

SEG24

COM1

SEG32

COM1

SEG40

COM1

SEG24

COM2

SEG32

COM2

SEG40

COM2

SEG24

COM3

SEG32

COM3

SEG40

COM3

SEG0

COM2

SEG8

COM2

SEG16

COM2

SEG0

COM3

SEG8

COM3

SEG16

COM3

SEG24

COM0

SEG32

COM0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

7B8h

7EFh

Legend:

Note 1:

2:

3:

Unimplemented — x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 45

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

x03h/ x83h

(2)

x04h/ x84h

(2)

x05h/ x85h

(2)

x06h/ x86h

(2)

Banks 16-30

x00h/ x80h

(2)

INDF0

INDF1 x00h/ x81h

(2)

x02h/ x82h

(2)

PCL

STATUS

FSR0L

FSR0H

FSR1L

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu x07h/ x87h

(2)

x08h/ x88h

(2)

FSR1H

BSR

Indirect Data Memory Address 1 High Pointer

— — — BSR<4:0>

0000 0000 0000 0000

---0 0000 ---0 0000 x09h/ x89h

(2)

WREG x0Ah/ x8Ah

(1),(2)

PCLATH

INTCON x0Bh/ x8Bh

(2)

x0Ch/ x8Ch

— x1Fh/ x9Fh

Legend:

Note 1:

2:

3:

Working Register

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE

Unimplemented

TMR0IE INTE IOCIE TMR0IF INTF IOCIF

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

— x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

DS41414D-page 46

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/1947

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 31

F80h

F81h

(2)

(2)

INDF0

INDF1

F82h

(2)

F83h

(2)

F84h

(2)

F85h

(2)

F86h

(2)

F87h

(2)

F88h

(2)

F89h

(2)

)

F8Ah

(1),(2

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

Working Register

— —

PD

Write Buffer for the upper 7 bits of the Program Counter

Z

BSR<4:0>

DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

F8Bh

(2)

F8Ch

FE3h

FE4h

INTCON

GIE PEIE

Unimplemented

TMR0IE INTE IOCIE TMR0IF INTF IOCIF

0000 000x 0000 000u

— —

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

STATUS_

SHAD

WREG_

SHAD

BSR_

SHAD

PCLATH_

SHAD

FSR0L_

SHAD

FSR0H_

SHAD

FSR1L_

SHAD

FSR1H_

SHAD

Working Register Normal (Non-ICD) Shadow

Z

Bank Select Register Normal (Non-ICD) Shadow

Program Counter Latch High Register Normal (Non-ICD) Shadow

Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow

DC C

---- -xxx ---- -uuu xxxx xxxx uuuu uuuu

---x xxxx ---u uuuu

-xxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

FECh — Unimplemented — —

FEDh

FEEh

FEFh

Legend:

Note 1:

2:

3:

STKPTR

— — — Current Stack Pointer

---1 1111 ---1 1111

TOSL

Top of Stack Low byte xxxx xxxx uuuu uuuu

TOSH

— Top of Stack High byte

-xxx xxxx -uuu uuuu x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 47

PIC16(L)F1946/1947

3.4

PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any

Reset, the PC is cleared.

Figure 3-4 shows the five

situations for the loading of the PC.

FIGURE 3-4:

PCLATH

PC

14

PCH

6

7

LOADING OF PC IN

DIFFERENT SITUATIONS

PCL

0

Instruction with

PCL as

Destination

0

8

ALU Result

PC

14

PCH

6

4

PCLATH

PC

14

PCH

7

PCLATH

6

PC

14 PCH

0

11

OPCODE <10:0>

PCL 0

0

PCL

8

W

PCL

15

PC + W

PC

14

PCH PCL

15

PC + OPCODE <8:0>

0

GOTO, CALL

0

0

CALLW

BRW

BRA

3.4.1

MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

3.4.2

COMPUTED

GOTO

A computed

GOTO

is accomplished by adding an offset to the program counter (

ADDWF PCL

). When performing a table read using a computed

GOTO

method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application

Note AN556,

“Implementing a Table Read”

(DS00556).

3.4.3

COMPUTED FUNCTION CALLS

A computed function

CALL

allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function

CALL

, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the

CALL

instruction, the PCH<2:0> and PCL registers are loaded with the operand of the

CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The

CALLW

instruction enables computed calls by combining PCLATH and W to form the destination address.

A computed

CALLW

is accomplished by loading the W register with the desired address and executing

CALLW

.

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

3.4.4

BRANCHING

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses page boundaries. There are two forms of branching,

BRW

and

BRA

. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.

If using

BRW

, load the W register with the desired unsigned address and execute

BRW

. The entire PC will be loaded with the address PC + 1 + W.

If using

BRA

, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the

BRA

instruction.

2010-2012 Microchip Technology Inc.

DS41414D-page 48

PIC16(L)F1946/1947

3.5

Stack

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figures 3-4

and 3-5 ). The stack space is

not part of either program or data space. The PC is

PUSHed onto the stack when

CALL

or

CALLW

instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a

RETURN

,

RETLW

or a

RETFIE

instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN bit is programmed to ‘

0

‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The

STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled.

Note 1:

There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the

CALL, CALLW

,

RETURN

,

RETLW

and

RETFIE

instructions or the vectoring to an interrupt address.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

3.5.1

ACCESSING THE STACK

The stack is available through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.

Note:

Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation,

CALL, CALLW

and

Interrupts will increment STKPTR while

RETLW

,

RETURN

, and

RETFIE

will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a

CALL

or

CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STK-

PTR.

Reference

Figure through Figure

accessing the stack.

for examples of

TOSH:TOSL

TOSH:TOSL

0x0A

0x09

0x08

0x07

0x06

0x05

0x0F

0x0E

0x0D

0x0C

0x0B

0x04

0x03

0x02

0x01

0x00

0x1F 0x0000

STKPTR = 0x1F

Stack Reset Disabled

(STVREN =

0

)

Initial Stack Configuration:

After Reset, the stack is empty. The empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL registers will return ‘

0

’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F.

STKPTR = 0x1F

Stack Reset Enabled

(STVREN =

1

)

2010-2012 Microchip Technology Inc.

DS41414D-page 49

PIC16(L)F1946/1947

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

TOSH:TOSL

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x0F

0x0E

0x0D

0x0C

0x0B

0x02

0x01

0x00 Return Address

This figure shows the stack configuration after the first

If a

RETURN

CALL

or a single interrupt.

instruction is executed, the return address will be placed in the

Program Counter and the Stack Pointer decremented to the empty state (0x1F).

STKPTR = 0x00

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

TOSH:TOSL

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x0F

0x0E

0x0D

0x0C

0x0B

0x03

0x02

0x01

0x00

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

After seven

CALL s or six

CALL s and an interrupt, the stack looks like the figure on the left. A series of

RETURN

instructions will repeatedly place the return addresses into the Program Counter and pop the stack.

STKPTR = 0x06

2010-2012 Microchip Technology Inc.

DS41414D-page 50

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

PIC16(L)F1946/1947

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

When the stack is full, the next

CALL

or an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will not be overwritten.

STKPTR = 0x10

TOSH:TOSL

3.5.2

OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is programmed to ‘

1

’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits

(STKOVF or STKUNF, respectively) in the PCON register.

3.6

Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘

0

’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

2010-2012 Microchip Technology Inc.

DS41414D-page 51

PIC16(L)F1946/1947

FIGURE 3-9: INDIRECT ADDRESSING

0x0000

0x0000

Traditional

Data Memory

0x0FFF

0x1000

0x1FFF

0x2000

0x0FFF

Reserved

Linear

Data Memory

FSR

Address

Range

0x29AF

0x29B0

0x7FFF

0x8000

Reserved

0x0000

Program

Flash Memory

0xFFFF 0x7FFF

Note:

Not all memory regions are completely implemented. Consult device memory tables for memory limits.

2010-2012 Microchip Technology Inc.

DS41414D-page 52

PIC16(L)F1946/1947

3.6.1

TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

4 BSR

Direct Addressing

0 6

Bank Select

From Opcode

0

Location Select

00000 00001 00010

0x00

7

0 0 0

FSRxH

0

Indirect Addressing

0 7 FSRxL

Bank Select

11111

0

Location Select

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

2010-2012 Microchip Technology Inc.

DS41414D-page 53

PIC16(L)F1946/1947

3.6.2

LINEAR DATA MEMORY

The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of

GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY

MAP

7

0 0

FSRnH

1

0 7

FSRnL 0

Location Select

0x2000

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Bank 2

0x16F

3.6.3

PROGRAM FLASH MEMORY

To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via

INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the

FSR/INDF interface will require one additional instruction cycle to complete.

FIGURE 3-12:

7

1

FSRnH 0

PROGRAM FLASH

MEMORY MAP

7

FSRnL 0

Location Select

0x8000

0x0000

Program

Flash

Memory

(low 8 bits)

0x29AF

0xF20

Bank 30

0xF6F

0xFFFF

0x7FFF

DS41414D-page 54

2010-2012 Microchip Technology Inc.

4.0

DEVICE CONFIGURATION

Device Configuration consists of Configuration Words,

Code Protection and Device ID.

4.1

Configuration Words

There are several Configuration Word bits that allow different oscillator and memory protection options.

These are implemented as Configuration Word 1 at

8007h and Configuration Word 2 at 8008h.

Note:

The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '

1

'.

PIC16(L)F1946/1947

2010-2012 Microchip Technology Inc.

DS41414D-page 55

PIC16(L)F1946/1947

4.2

Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1

FCMEN bit 13

R/P-1

IESO

R/P-1

CLKOUTEN

R/P-1 R/P-1

BOREN<1:0>

R/P-1

CPD bit 8 bit 7

R/P-1

CP

Legend:

R = Readable bit

‘0’ = Bit is cleared

R/P-1

MCLRE

R/P-1

PWRTE

R/P-1

P = Programmable bit

‘1’ = Bit is set

R/P-1

WDTE<1:0>

R/P-1 R/P-1

FOSC<2:0>

U = Unimplemented bit, read as ‘1’

-n = Value when blank or after Bulk Erase

R/P-1 bit 0 bit 13 bit 12 bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5

Note 1:

2:

3:

FCMEN:

Fail-Safe Clock Monitor Enable bit

1

= Fail-Safe Clock Monitor is enabled

0

= Fail-Safe Clock Monitor is disabled

IESO:

Internal External Switchover bit

1

= Internal/External Switchover mode is enabled

0

= Internal/External Switchover mode is disabled

CLKOUTEN:

Clock Out Enable bit

If FOSC configuration bits are set to LP, XT, HS modes:

This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.

All other FOSC modes:

1

= CLKOUT function is disabled. I/O function on the CLKOUT pin.

0

= CLKOUT function is enabled on the CLKOUT pin

BOREN<1:0>:

Brown-out Reset Enable bits

(1)

11

= BOR enabled

10

= BOR enabled during operation and disabled in Sleep

01

= BOR controlled by SBOREN bit of the BORCON register

00

= BOR disabled

CPD:

Data Code Protection bit

(2)

1

= Data memory code protection is disabled

0

= Data memory code protection is enabled

CP:

Code Protection bit

(3)

1

= Program memory code protection is disabled

0

= Program memory code protection is enabled

MCLRE:

MCLR/V

PP

Pin Function Select bit

If LVP bit =

1

:

This bit is ignored.

If LVP bit =

0

:

1

= MCLR/V

PP

pin function is MCLR; Weak pull-up enabled.

0

= MCLR/V

PP

pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUG5 bit.

PWRTE:

Power-up Timer Enable bit

(1)

1

= PWRT disabled

0

= PWRT enabled

Enabling Brown-out Reset does not automatically enable Power-up Timer.

The entire data EEPROM will be erased when the code protection is turned off during

The entire program memory will be erased when the code protection is turned off.

2010-2012 Microchip Technology Inc.

DS41414D-page 56

PIC16(L)F1946/1947

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED)

bit 4-3 bit 2-0

Note 1:

2:

3:

WDTE<1:0>:

Watchdog Timer Enable bit

11

= WDT enabled

10

= WDT enabled while running and disabled in Sleep

01

= WDT controlled by the SWDTEN bit in the WDTCON register

00

= WDT disabled

FOSC<2:0>:

Oscillator Selection bits

111

= ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin

110

= ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin

101

= ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin

100

= INTOSC oscillator: I/O function on CLKIN pin

011

= EXTRC oscillator: External RC circuit connected to CLKIN pin

010

= HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins

001

= XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins

000

= LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Enabling Brown-out Reset does not automatically enable Power-up Timer.

The entire data EEPROM will be erased when the code protection is turned off during

The entire program memory will be erased when the code protection is turned off.

2010-2012 Microchip Technology Inc.

DS41414D-page 57

PIC16(L)F1946/1947

REGISTER 4-2:

bit 7

U-1

U-1

CONFIG2: CONFIGURATION WORD 2

R/P-1

LVP

(1)

bit 13

R/P-1

DEBUG

(2)

U-1

U-1

R/P-1/1

VCAPEN

U-1

R/P-1

BORV

U-1

(3)

R/P-1

STVREN

R/P-1

PLLEN bit 8

R/P-1 R/P-1

WRT<1:0> bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

-n = Value when blank or after Bulk Erase bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-5 bit 4 bit 3-2 bit 1-0

Note 1:

2:

3:

LVP:

Low-Voltage Programming Enable bit

(1)

1

= Low-voltage programming enabled

0

= High-voltage on MCLR must be used for programming

DEBUG:

In-Circuit Debugger Mode bit

(2)

1

= In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins

0

= In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

Unimplemented:

Read as ‘

1

BORV:

Brown-out Reset Voltage Selection bit

(3)

1

= Brown-out Reset voltage (

Vbor

), low trip point selected.

0

= Brown-out Reset voltage (

Vbor

), high trip point selected.

STVREN:

Stack Overflow/Underflow Reset Enable bit

1

= Stack Overflow or Underflow will cause a Reset

0

= Stack Overflow or Underflow will not cause a Reset

PLLEN:

PLL Enable bit

1

= 4xPLL enabled

0

= 4xPLL disabled

Unimplemented:

Read as ‘

1

VCAPEN:

Voltage Regulator Capacitor Enable bits

0

= V

CAP

functionality is enabled on RF0

1

= No capacitor on V

CAP

pin

Unimplemented:

Read as ‘

1

WRT<1:0>:

Flash Memory Self-Write Protection bits

8 kW Flash memory (PIC16(L)F1946):

11

= Write protection off

10

= 000h to 1FFh write-protected, 200h to 1FFFh may be modified by EECON control

01

= 000h to FFFh write-protected, 1000h to 1FFFh may be modified by EECON control

00

= 000h to 1FFFh write-protected, no addresses may be modified by EECON control

16 kW Flash memory (PIC16(L)F1947):

11

= Write protection off

10

= 000h to 1FFh write-protected, 200h to 3FFFh may be modified by EECON control

01

= 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by EECON control

00

= 000h to 3FFFh write-protected, no addresses may be modified by EECON control

The LVP bit cannot be programmed to ‘

0

’ when Programming mode is entered via LVP.

The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘

1

’.

See

Vbor

parameter for specific trip point voltages.

2010-2012 Microchip Technology Inc.

DS41414D-page 58

4.3

Code Protection

Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently.

Internal access to the program memory and data

EEPROM are unaffected by any code protection setting.

4.3.1

PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP bit in Configuration

Words. When CP =

0

, external reads and writes of program memory are inhibited and a read will return all

0

’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See

Section 4.4 “Write

Protection”

for more information.

4.3.2

DATA EEPROM PROTECTION

The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD =

0

, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data

EEPROM regardless of the protection bit settings.

4.4

Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected.

4.5

User ID

Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See

Section 4.6 “Device ID and Revision ID”

for more

information on accessing these memory locations.

For more information on checksum calculation, see the

PIC16F193X/LF193X/PIC16F194X/LF194X Memory

Programming Specification

” (DS41397).

PIC16(L)F1946/1947

2010-2012 Microchip Technology Inc.

DS41414D-page 59

PIC16(L)F1946/1947

4.6

Device ID and Revision ID

The memory location 8006h is where the Device ID and

Revision ID are stored. The upper nine bits hold the

Device ID. The lower five bits hold the Revision ID. See

Section 11.5 “User ID, Device ID and Configuration

Word Access”

for more information on accessing

these memory locations.

Development tools, such as device programmers and debuggers, may be used to read the Device ID and

Revision ID.

4.7

Register Definitions: Device ID

REGISTER 4-3: DEVICEID: DEVICE ID REGISTER

R R R

DEV<8:3> bit 13

R

R R R

REV<4:0>

R bit 7

Legend:

R = Readable bit

‘1’ = Bit is set

R

DEV<2:0>

R

‘0’ = Bit is cleared

R

R

-n = Value when blank or after Bulk Erase bit 13-5

DEV<8:0>:

Device ID bits bit 4-0

Device

PIC16F1946

PIC16F1947

PIC16LF1946

PIC16LF1947

DEVICEID<13:0> Values

DEV<8:0>

10 0011 001

10 0011 010

10 0011 011

10 0011 100

REV<4:0>

x xxxx x xxxx x xxxx x xxxx

REV<4:0>:

Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

R

R bit 8 bit 0

2010-2012 Microchip Technology Inc.

DS41414D-page 60

5.0

OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

5.1

Overview

The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption.

Figure 5-1

illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and

Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external or internal sources via software.

• Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution.

• Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources

PIC16(L)F1946/47

The oscillator module can be configured in one of eight clock modes.

1.

2.

3.

4.

5.

6.

7.

8.

ECL – External Clock Low Power mode

(0 MHz to 0.5 MHz)

ECM – External Clock Medium Power mode

(0.5 MHz to 4 MHz)

ECH – External Clock High Power mode

(4 MHz to 32 MHz)

LP – 32 kHz Low-Power Crystal mode.

XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode (up to 4 MHz)

HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz)

RC – External Resistor-Capacitor (RC).

INTOSC – Internal oscillator (31 kHz to 32 MHz).

Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered.

The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency.

The INTOSC internal oscillator block produces low, medium, and high frequency clock sources, designated

LFINTOSC, MFINTOSC, and HFINTOSC. (see

Internal Oscillator Block,

Figure 5-1

). A wide selection of device clock frequencies may be derived from these three clock sources.

2010-2012 Microchip Technology Inc.

DS41414D-page 61

PIC16(L)F1946/47

FIGURE 5-1: SIMPLIFIED PIC

®

MCU CLOCK SOURCE BLOCK DIAGRAM

External

Oscillator

LP, XT, HS, RC, EC

OSC2

Sleep

4 x PLL

OSC1

T1OSO

T1OSI

Oscillator

Timer1

T1OSCEN

Enable

Oscillator

FOSC<2:0> =

100

T1OSC

Internal Oscillator

Internal

Oscillator

Block

HFPLL

16 MHz

(HFINTOSC)

500 kHz

Source

31 kHz

Source

500 kHz

(MFINTOSC)

IRCF<3:0>

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

250 kHz

125 kHz

62.5 kHz

31.25 kHz

31 kHz

Clock

Control

Sleep

FOSC<2:0> SCS<1:0>

Clock Source Option for other modules

CPU and

Peripherals

31 kHz (LFINTOSC)

WDT, PWRT, Fail-Safe Clock Monitor

Two-Speed Start-up and other modules

DS41414D-page 62

2010-2012 Microchip Technology Inc.

5.2

Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.

Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Lock Loop

(HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency

Internal Oscillator (HFINTOSC), 500 kHZ (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator

(LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Select

(SCS) bits in the OSCCON register. See

Section 5.3

“Clock Switching”

for additional information.

5.2.1

EXTERNAL CLOCK SOURCES

An external clock source can be used as the device system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in the Configuration

Words to select an external clock source that will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to:

- Timer1 oscillator during run-time, or

- An external clock source determined by the value of the FOSC bits.

See

Section 5.3 “Clock Switching”

for more informa-

tion.

5.2.1.1

EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input.

OSC2/CLKOUT is available for general purpose I/O or

CLKOUT. Figure 5-2 shows the pin connections for EC

mode.

EC mode has 3 power modes to select from through

Configuration Words:

• High power, 4-32 MHz (FOSC =

111

)

• Medium power, 0.5-4 MHz (FOSC =

110

)

• Low power, 0-0.5 MHz (FOSC =

101

)

PIC16(L)F1946/47

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC

®

MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will resume operation as if no time had elapsed.

FIGURE 5-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Clock from

Ext. System

F

OSC

/4 or I/O

(1)

OSC1/CLKIN

PIC

®

MCU

OSC2/CLKOUT

Note 1:

Output depends upon CLKOUTEN bit of the

Configuration Words.

5.2.1.2

LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to

OSC1 and OSC2 ( Figure 5-3 ). The three modes select

a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.

LP

Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals).

XT

Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a medium drive level specification.

HS

Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting.

Figure 5-3 and Figure 5-4

show typical circuits for quartz crystal and ceramic resonators, respectively.

2010-2012 Microchip Technology Inc.

DS41414D-page 63

PIC16(L)F1946/47

FIGURE 5-3:

C1

Quartz

Crystal

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

PIC

®

MCU

OSC1/CLKIN

R

F

(2)

To Internal

Logic

Sleep

C2

R

S

(1)

OSC2/CLKOUT

Note 1:

2:

A series resistor (R

S

) may be required for quartz crystals with low drive level.

The value of R

F

varies with the Oscillator mode selected (typically between 2 M

to 10 M



.

Note 1:

2:

Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

Always verify oscillator performance over the V

DD

and temperature range that is expected for the application.

3:

For oscillator design assistance, reference the following Microchip Applications Notes:

• AN826, “

Crystal Oscillator Basics and

Crystal Selection for rfPIC

®

and PIC

®

Devices

” (DS00826)

• AN849, “

Basic PIC

®

Oscillator Design

(DS00849)

• AN943, “

Practical PIC

®

Oscillator

Analysis and Design

” (DS00943)

• AN949, “

Making Your Oscillator Work

(DS00949)

FIGURE 5-4:

C1

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

R

P

(3)

PIC

®

MCU

OSC1/CLKIN

R

F

(2)

To Internal

Logic

Sleep

C2 Ceramic

Resonator

R

S

(1)

OSC2/CLKOUT

Note 1:

2:

3:

A series resistor (R

S

) may be required for ceramic resonators with low drive level.

The value of R

F

varies with the Oscillator mode selected (typically between 2 M

to 10 M



.

An additional parallel feedback resistor (R

P

) may be required for proper ceramic resonator operation.

5.2.1.3

Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module.

In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see

Section 5.4

“Two-Speed Clock Start-up Mode”

).

5.2.1.4

4x PLL

The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL

Clock Timing Specifications in

Section 30.0

“Electrical Specifications”

.

The 4x PLL may be enabled for use by one of two methods:

1.

2.

Program the PLLEN bit in Configuration Words to a ‘

1

’.

Write the SPLLEN bit in the OSCCON register to a ‘

1

’. If the PLLEN bit in Configuration Words is programmed to a ‘

1

’, then the value of SPLLEN is ignored.

2010-2012 Microchip Technology Inc.

DS41414D-page 64

5.2.1.5

TIMER1 Oscillator

The Timer1 Oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.

The Timer1 Oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to

Section 5.3 “Clock

Switching”

for more information.

FIGURE 5-5: QUARTZ CRYSTAL

OPERATION (TIMER1

OSCILLATOR)

C1

C2

32.768 kHz

Quartz

Crystal

T1OSI

PIC

®

MCU

To Internal

Logic

T1OSO

Note 1:

Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2:

3:

Always verify oscillator performance over the V

DD

and temperature range that is expected for the application.

For oscillator design assistance, reference the following Microchip Applications Notes:

• AN826, “

Crystal Oscillator Basics and

Crystal Selection for rfPIC

®

and PIC

®

Devices

” (DS00826)

• AN849, “

Basic PIC

®

Oscillator Design

(DS00849)

• AN943, “

Practical PIC

®

Oscillator

Analysis and Design

” (DS00943)

• AN949, “

Making Your Oscillator Work

(DS00949)

• TB097, “

Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS

” (DS91097)

• AN1288, “

Design Practices for

Low-Power External Oscillators

(DS01288)

PIC16(L)F1946/47

5.2.1.6

External RC Mode

The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required.

The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the

CLKOUTEN bit in Configuration Words.

Figure 5-6 shows the external RC mode connections.

FIGURE 5-6: EXTERNAL RC MODES

R

EXT

V

DD

PIC

®

MCU

OSC1/CLKIN

Internal

Clock

C

EXT

V

SS

F

OSC

/4 or I/O

(1)

OSC2/CLKOUT

Recommended values: 10 k

 

R

EXT

100 k

, <3V

3 k

 

R

EXT

100 k

, 3-5V

C

EXT

> 20 pF, 2-5V

Note 1:

Output depends upon CLKOUTEN bit of the

Configuration Words.

The RC oscillator frequency is a function of the supply voltage, the resistor (R

EXT

) and capacitor (C

EXT

) values and the operating temperature. Other factors affecting the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due to tolerance of external RC components used.

2010-2012 Microchip Technology Inc.

DS41414D-page 65

PIC16(L)F1946/47

5.2.2

INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions:

• Program the FOSC<2:0> bits in Configuration

Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See

Section 5.3

“Clock Switching”

for more information.

In

INTOSC

mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words.

The internal oscillator block has two independent oscillators and a dedicated Phase-Lock Loop, HFPLL that can produce one of three internal system clock sources.

1.

2.

3.

The

HFINTOSC

(High-Frequency Internal

Oscillator) is factory calibrated and operates at

16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (

Register 5-3 ).

The

MFINTOSC

(Medium-Frequency Internal

Oscillator) is factory calibrated and operates at

500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the

OSCTUNE register (

Register 5-3

).

The

LFINTOSC

(Low-Frequency Internal

Oscillator) is uncalibrated and operates at

31 kHz.

5.2.2.1

HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via

software using the OSCTUNE register ( Register 5-3 ).

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1 ). One of multiple

frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the

OSCCON register. See

Section 5.2.2.7 “Internal

Oscillator Clock Switch Timing”

for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

• FOSC<2:0> =

100

, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘

1x

’.

A fast start-up oscillator allows internal circuits to power-up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit

(HFIOFR) of the OSCSTAT register indicates when the

HFINTOSC is running.

The High-Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value.

The High-Frequency Internal Oscillator Stable bit

(HFIOFS) of the OSCSTAT register indicates when the

HFINTOSC is running within 0.5% of its final value.

5.2.2.2

MFINTOSC

The Medium-Frequency Internal Oscillator

(MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register

(

Register 5-3

).

The output of the MFINTOSC connects to a postscaler and multiplexer (see

Figure 5-1 ). One of nine

frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the

OSCCON register. See

Section 5.2.2.7 “Internal

Oscillator Clock Switch Timing”

for more information.

The MFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

• FOSC<2:0> =

100

, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘

1x

The Medium-Frequency Internal Oscillator Ready bit

(MFIOFR) of the OSCSTAT register indicates when the

MFINTOSC is running.

2010-2012 Microchip Technology Inc.

DS41414D-page 66

5.2.2.3

Internal Oscillator Frequency

Adjustment

The 500 kHz internal oscillator is factory calibrated.

This internal oscillator can be adjusted in software by writing to the OSCTUNE register (

Register 5-3

). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘

0

’. The value is a 6-bit two’s complement number. A value of

1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency.

When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are

not

affected by the change in frequency.

5.2.2.4

LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1

). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON

register. See

Section 5.2.2.7 “Internal Oscillator

Clock Switch Timing”

for more information. The

LFINTOSC is also the frequency for the Power-up Timer

(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock

Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register =

000)

as the system clock source (SCS bits of the OSCCON register = enabled:

1x

), or when any of the following are

• Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and

• FOSC<2:0> =

100

, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘

1x

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running.

PIC16(L)F1946/47

5.2.2.5

Internal Oscillator Frequency

Selection

The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see

Figure 5-1

). The Internal Oscillator Frequency

Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software:

• HFINTOSC

- 32 MHz (requires 4x PLL)

- 16 MHz

- 8 MHz

- 4 MHz

- 2 MHz

- 1 MHz

- 500 kHz (default after Reset)

- 250 kHz

- 125 kHz

- 62.5 kHz

- 31.25 kHz

• LFINTOSC

- 31 kHz

Note:

Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to ‘

0111

’ and the frequency selection is set to

500 kHz. The user can modify the IRCF bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.

2010-2012 Microchip Technology Inc.

DS41414D-page 67

PIC16(L)F1946/47

5.2.2.6

32 MHz Internal Oscillator

Frequency Selection

The Internal Oscillator Block can be used with the 4x

PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source:

• The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<2:0> =

100

).

• The SCS bits in the OSCCON register must be cleared to use the clock determined by

FOSC<2:0> in Configuration Words

(SCS<1:0> =

00

).

• The IRCF bits in the OSCCON register must be set to the 8 MHz HFINTOSC set to use

(IRCF<3:0> =

1110

).

• The SPLLEN bit in the OSCCON register must be set to enable the 4xPLL, or the PLLEN bit of the

Configuration Words must be programmed to a

1

’.

Note:

When using the PLLEN bit of the

Configuration Words, the 4xPLL cannot be disabled by software and the 8 MHz

HFINTOSC option will no longer be available.

The 4xPLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘

1x

’. The SCS bits must be set to ‘

00

’ to use the 4xPLL with the internal oscillator.

5.2.2.7

Internal Oscillator Clock Switch

Timing

5.

6.

7.

When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be

shut down to save power (see Figure 5-7 ). If this is the

case, there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC,

MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows:

1.

2.

3.

4.

IRCF<3:0> bits of the OSCCON register are modified.

If the new clock is shut down, a clock start-up delay is started.

Clock switch circuitry waits for a falling edge of the current clock.

The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock.

The new clock is now active.

The OSCSTAT register is updated as required.

Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in

Table 5-1

.

Start-up delay specifications are located in the oscillator tables of

Section 30.0 “Electrical

Specifications”

DS41414D-page 68

2010-2012 Microchip Technology Inc.

INTERNAL OSCILLATOR SWITCH TIMING

PIC16(L)F1946/47

FIGURE 5-7:

HFINTOSC/

MFINTOSC

HFINTOSC/

MFINTOSC

LFINTOSC (FSCM and WDT disabled)

Start-up Time

2-cycle Sync

LFINTOSC

IRCF <3:0>



0



0

System Clock

Running

HFINTOSC/

MFINTOSC

HFINTOSC/

MFINTOSC

LFINTOSC (Either FSCM or WDT enabled)

2-cycle Sync

LFINTOSC

IRCF <3:0>



0



0

System Clock

Running

LFINTOSC

LFINTOSC

HFINTOSC/MFINTOSC

Start-up Time 2-cycle Sync

HFINTOSC/

MFINTOSC

IRCF <3:0>

=

0

0

System Clock

LFINTOSC turns off unless WDT or FSCM is enabled

Running

2010-2012 Microchip Technology Inc.

DS41414D-page 69

PIC16(L)F1946/47

5.3

Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits:

• Default system oscillator determined by FOSC bits in Configuration Words

• Timer1 32 kHz crystal oscillator

• Internal Oscillator Block (INTOSC)

5.3.1

SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals.

• When the SCS bits of the OSCCON register =

00

, the system clock source is determined by value of the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register =

01

, the system clock source is the Timer1 oscillator.

• When the SCS bits of the OSCCON register =

1x

, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always cleared.

Note:

Any automatic clock switch, which may occur from Two-Speed Start-up or

Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the

OSCSTAT register to determine the current system clock source.

When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 5-1 .

5.3.2

OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration

Words, or from the internal clock source. In particular,

OSTS indicates that the Oscillator Start-up Timer

(OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 oscillator.

5.3.3

TIMER1 OSCILLATOR

The Timer1 oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.

The Timer1 oscillator is enabled using the T1OSCEN control bit in the T1CON register. See

Section 21.0

“Timer1 Module with Gate Control”

for more information about the Timer1 peripheral.

5.3.4

TIMER1 OSCILLATOR READY

(T1OSCR) BIT

The user must ensure that the Timer1 oscillator is ready to be used before it is selected as a system clock source. The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator.

2010-2012 Microchip Technology Inc.

DS41414D-page 70

PIC16(L)F1946/47

5.4

Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT, or HS modes.

The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source.

If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed

Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after

POR or an exit from Sleep.

If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short.

Note:

Executing a

SLEEP

instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear.

TABLE 5-1:

Switch From

Sleep/POR

Sleep/POR

LFINTOSC

Sleep/POR

Any clock source

OSCILLATOR SWITCHING DELAYS

Any clock source

Any clock source

PLL inactive

Note 1:

PLL inactive.

Switch To

LFINTOSC

(1)

MFINTOSC

(1)

HFINTOSC

(1)

EC, RC

(1)

EC, RC

(1)

Timer1 Oscillator

LP, XT, HS

(1)

MFINTOSC

(1)

HFINTOSC

(1)

LFINTOSC

(1)

Timer1 Oscillator

PLL active

Frequency

31 kHz

31.25 kHz-500 kHz

31.25 kHz-16 MHz

DC – 32 MHz

DC – 32 MHz

32 kHz-20 MHz

31.25 kHz-500 kHz

31.25 kHz-16 MHz

31 kHz

32 kHz

16-32 MHz

5.4.1

TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is configured by the following settings:

• IESO (of the Configuration Words) =

1

; Internal/External Switchover bit (Two-Speed Start-up mode enabled).

• SCS (of the OSCCON register) =

00

.

• FOSC<2:0> bits in the Configuration Words configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

Oscillator Delay

Oscillator Warm-up Delay (T

WARM

)

2 cycles

1 cycle of each

1024 Clock Cycles (OST)

2

 s (approx.)

1 cycle of each

1024 Clock Cycles (OST)

2 ms (approx.)

2010-2012 Microchip Technology Inc.

DS41414D-page 71

PIC16(L)F1946/47

5.4.2

1.

2.

3.

4.

5.

6.

7.

TWO-SPEED START-UP

SEQUENCE

Wake-up from Power-on Reset or Sleep.

Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register.

OST enabled to count 1024 clock cycles.

OST timed out, wait for falling edge of the internal oscillator.

OSTS is set.

System clock held low until the next falling edge of new clock (LP, XT or HS mode).

System clock is switched to external clock source.

FIGURE 5-8: TWO-SPEED START-UP

INTOSC

OSC1

0 1

T

OST

1022 1023

OSC2

Program Counter PC - N PC

System Clock

5.4.3

CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the

FOSC<2:0> bits in the Configuration Words, or the internal oscillator.

PC + 1

DS41414D-page 72

2010-2012 Microchip Technology Inc.

5.5

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1

Oscillator and RC).

FIGURE 5-9:

External

Clock

FSCM BLOCK DIAGRAM

Clock Monitor

Latch

S Q

LFINTOSC

Oscillator

31 kHz

(~32

 s)

÷ 64

488 Hz

(~2 ms)

Sample Clock

R Q

Clock

Failure

Detected

5.5.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 5-9 . Inside the fail

detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low.

5.5.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation.

The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.

PIC16(L)F1946/47

5.5.3

FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, executing a

SLEEP

instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the

INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the

OSFIF flag will again become set by hardware.

5.5.4

RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.

Note:

Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate amount of time, the user should check the

Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed.

2010-2012 Microchip Technology Inc.

DS41414D-page 73

PIC16(L)F1946/47

FIGURE 5-10:

Sample Clock

System

Clock

Output

Clock Monitor Output

(Q)

OSCFIF

FSCM TIMING DIAGRAM

Oscillator

Failure

Failure

Detected

Note:

Test

Test Test

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.

DS41414D-page 74

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

5.6

Register Definitions: Oscillator Control

REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0

SPLLEN bit 7

R/W-0/0 R/W-1/1 R/W-1/1

IRCF<3:0>

R/W-1/1 U-0

R/W-0/0 R/W-0/0

SCS<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-3 bit 2 bit 1-0

Note 1:

SPLLEN:

Software PLL Enable bit

If PLLEN in Configuration Words =

1

:

SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Words =

0

:

1

= 4x PLL Is enabled

0 = 4x PLL is disabled

IRCF<3:0>:

Internal Oscillator Frequency Select bits

1111

= 16 MHz HF

1110

= 8 MHz or 32 MHz HF(see

Section 5.2.2.1 “HFINTOSC”

)

1101

= 4 MHz HF

1100

= 2 MHz HF

1011

= 1 MHz HF

1010

= 500 kHz HF

(1)

1001

= 250 kHz HF

(1)

1000

= 125 kHz HF

(1)

0111

= 500 kHz MF (default upon Reset)

0110

= 250 kHz MF

0101

= 125 kHz MF

0100

= 62.5 kHz MF

0011

= 31.25 kHz HF

(1)

0010

= 31.25 kHz MF

000x

= 31 kHz LF

Unimplemented:

Read as ‘

0

SCS<1:0>:

System Clock Select bits

1x

= Internal oscillator block

01

= Timer1 oscillator

00

= Clock determined by FOSC<2:0> in Configuration Words

Duplicate frequency derived from HFINTOSC.

2010-2012 Microchip Technology Inc.

DS41414D-page 75

PIC16(L)F1946/47

REGISTER 5-2:

R-1/q

T1OSCR bit 7

OSCSTAT: OSCILLATOR STATUS REGISTER

R-0/q

PLLR

R-q/q

OSTS

R-0/q

HFIOFR

R-0/q

HFIOFL

R-q/q

MFIOFR

R-0/0

LFIOFR

R-0/q

HFIOFS bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets q = Conditional

T1OSCR:

Timer1 Oscillator Ready bit

If T1OSCEN =

1

:

1

= Timer1 oscillator is ready

0

= Timer1 oscillator is not ready

If T1OSCEN = 0:

1

= Timer1 clock source is always ready

PLLR

4x PLL Ready bit

1

= 4x PLL is ready

0

= 4x PLL is not ready

OSTS:

Oscillator Start-up Time-out Status bit

1

= Running from the clock defined by the FOSC<2:0> bits of the Configuration Words

0

= Running from an internal oscillator (FOSC<2:0> =

100

)

HFIOFR:

High Frequency Internal Oscillator Ready bit

1

= HFINTOSC is ready

0

= HFINTOSC is not ready

HFIOFL:

High Frequency Internal Oscillator Locked bit

1

= HFINTOSC is at least 2% accurate

0

= HFINTOSC is not 2% accurate

MFIOFR:

Medium Frequency Internal Oscillator Ready bit

1

= MFINTOSC is ready

0

= MFINTOSC is not ready

LFIOFR:

Low Frequency Internal Oscillator Ready bit

1

= LFINTOSC is ready

0

= LFINTOSC is not ready

HFIOFS:

High Frequency Internal Oscillator Stable bit

1

= HFINTOSC is at least 0.5% accurate

0

= HFINTOSC is not 0.5% accurate

2010-2012 Microchip Technology Inc.

DS41414D-page 76

PIC16(L)F1946/47

REGISTER 5-3:

bit 7

U-0

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TUN<5:0>

R/W-0/0 R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Unimplemented:

Read as ‘

0

TUN<5:0>:

Frequency Tuning bits

100000

= Minimum frequency

111111

=

000000

= Oscillator module is running at the factory-calibrated frequency.

000001

=

011110

=

011111

= Maximum frequency

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON

OSCSTAT

OSCTUNE

PIE2

PIR2

T1CON

Legend:

Note 1:

SPLLEN

T1OSCR

OSFIE

OSFIF

PLLR

C2IE

C2IF

IRCF<3:0>

OSTS

C1IE

C1IF

HFIOFR

EEIE

EEIF

HFIOFL

MFIOFR

TUN<5:0>

BCLIE

LCDIE

BCLIF LCDIF

LFIOFR

C3IE

C3IF

TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by clock sources.

PIC16F1947 only.

SCS<1:0>

HFIOFS

CCP2IE

CCP2IF

(1)

(1)

TMR1ON

Register on Page

75

76

77

94

98

207

TABLE 5-3:

Name Bits

SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

CONFIG2

Legend:

Note 1:

13:8 — — FCMEN IESO CLKOUTEN

7:0

13:8

CP

MCLRE

PWRTE

LVP

WDTE<1:0>

DEBUG — BORV

7:0 — — — VCAPEN — —

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by clock sources.

PIC16F1946/47 only.

BOREN<1:0> CPD

FOSC<2:0>

STVREN PLLEN

WRT<1:0>

Register on Page

56

58

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

NOTES:

DS41414D-page 78

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

6.0

RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• MCLR Reset

• WDT Reset

RESET

instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow V

DD

to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event.

A simplified block diagram of the On-Chip Reset Circuit is shown in

Figure 6-1

.

FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Programming Mode Exit

RESET

Instruction

MCLR

Stack

Pointer

Stack Overflow/Underflow Reset

External Reset

MCLRE

Sleep

WDT

Time-out

V

DD

Power-on

Reset

Brown-out

Reset

BOR

Enable

Device

Reset

Zero

LFINTOSC

PWRT

64 ms

PWRTEN

2010-2012 Microchip Technology Inc.

DS41414D-page 79

PIC16(L)F1946/47

6.1

Power-on Reset (POR)

The POR circuit holds the device in Reset until V

DD

has reached an acceptable level for minimum operation.

Slow rising V

DD

, fast operating speeds or analog performance may require greater than minimum V

DD

.

The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met.

6.1.1

POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the V

DD

to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration

Words.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note

AN607,

“Power-up Trouble Shooting”

(DS00607).

6.2

Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when V

DD reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Table 6-1 for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words.

A V

DD

noise rejection filter prevents the BOR from triggering on small events. If V

DD

falls below V

BOR

for a duration greater than parameter T

BORDC

, the device

will reset. See Figure 6-2 for more information.

TABLE 6-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

Instruction Execution upon:

Release of POR or Wake-up from Sleep

Waits for BOR ready

(1)

(BORRDY =

1

)

11 X

X Active

Awake Active

10 X

Waits for BOR ready (BORRDY =

1

)

Sleep Disabled

1

X Active Waits for BOR ready

(1)

(BORRDY =

1

)

01

0

X Disabled

X Disabled

Begins immediately (BORRDY = x

)

00 X

Note 1:

In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY =

1

), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits.

6.2.1

When the BOREN bits of Configuration Words are programmed to ‘

11

’, the BOR is always on. The device start-up will be delayed until the BOR is ready and V

DD is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

6.2.2

BOR IS ALWAYS ON

BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are programmed to ‘

10

’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and V

DD

is higher than the BOR threshold.

BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.

6.2.3

BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are programmed to ‘

01

’, the BOR is controlled by the SBO-

REN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the V

DD level.

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

2010-2012 Microchip Technology Inc.

DS41414D-page 80

FIGURE 6-2:

V

DD

BROWN-OUT SITUATIONS

Internal

Reset

V

DD

Internal

Reset

V

DD

< T

T

PWRT

PWRT

(1)

T

PWRT

(1)

Internal

Reset

Note 1:

T

PWRT

delay only if PWRTE bit is programmed to ‘

0

’.

T

PWRT

(1)

PIC16(L)F1946/47

V

BOR

V

BOR

V

BOR

6.3

Register Definitions: BOR Control

REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u

SBOREN bit 7

U-0

U-0

U-0

U-0

U-0

U-0

R-q/u

BORRDY bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6-1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition

SBOREN:

Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Words

01

:

SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Words =

01

:

1

= BOR Enabled

0

= BOR Disabled

Unimplemented:

Read as ‘

0

BORRDY:

Brown-out Reset Circuit Ready Status bit

1

= The Brown-out Reset circuit is active

0

= The Brown-out Reset circuit is inactive

2010-2012 Microchip Technology Inc.

DS41414D-page 81

PIC16(L)F1946/47

6.4

MCLR

The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the

MCLRE bit of Configuration Words and the LVP bit of

Configuration Words ( Table 6-2 ).

TABLE 6-2:

MCLRE

0

1 x

MCLR CONFIGURATION

LVP

0

0

1

MCLR

Disabled

Enabled

Enabled

6.4.1

MCLR ENABLED

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to

V

DD

through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

Note:

A Reset does not drive the MCLR pin low.

6.4.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See

Section 12.15 “PORTG

Registers”

for more information.

6.5

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a

CLRWDT

instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See

Section 10.0

“Watchdog Timer (WDT)”

for more information.

6.6

RESET

Instruction

A

RESET

instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘

0

’. See

Table 6-4

for default conditions after a

RESET

instruction has occurred.

6.7

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration

Words. See

Section 3.5.2 “Overflow/Underflow

Reset”

for more information.

6.8

Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

6.9

Power-Up Timer

The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow V

DD

to stabilize before allowing the device to start running.

The Power-up Timer is controlled by the PWRTE bit of

Configuration Words.

6.10

Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1.

2.

Power-up Timer runs to completion (if enabled).

Oscillator start-up timer runs to completion (if required for oscillator source).

MCLR must be released (if enabled).

3.

The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module (With Fail-Safe

Clock Monitor)”

for more information.

The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device

will begin execution immediately (see Figure 6-3

). This is useful for testing purposes or to synchronize more than one device operating in parallel.

2010-2012 Microchip Technology Inc.

DS41414D-page 82

PIC16(L)F1946/47

FIGURE 6-3: RESET START-UP SEQUENCE

V

DD

Internal POR

Power Up Timer

MCLR

Internal RESET

External Crystal

Oscillator Start Up Timer

Oscillator

F

OSC

Oscillator Modes

Internal Oscillator

Oscillator

F

OSC

External Clock (EC)

CLKIN

F

OSC

T

PWRT

T

MCLR

T

OST

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DS41414D-page 83

PIC16(L)F1946/47

6.11

Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON register are updated to indicate the cause of the

Reset.

Table 6-3 and Table 6-4 show the Reset

conditions of these registers.

TABLE 6-3:

u u

0 u

0

0

0 u

1 u u u

0

0

1 u

1 x

0 u u u

0 u

0

1

1

0

1

0 x u u u

1 u u u

0 u x x x u u u u u u u u u

0

0

0 u u u u u u u

1 u

1

1

1

0 u u u u u u

1 u

1

1

1 u u

0

0 u u u

0 u

0

0

0 u u u u

1

RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RMCLR RI POR BOR TO PD Condition

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

RESET

Instruction Executed

Stack Overflow Reset (STVREN =

1

)

Stack Underflow Reset (STVREN =

1

)

TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

(2)

Condition

Program

Counter

STATUS

Register

PCON

Register

Power-on Reset 0000h

---1 1000 00-- 110x

MCLR Reset during normal operation 0000h

---u uuuu uu-- 0uuu

MCLR Reset during Sleep 0000h

---1 0uuu uu-- 0uuu

WDT Reset 0000h

---0 uuuu uu-- uuuu

WDT Wake-up from Sleep PC + 1

---0 0uuu uu-- uuuu

Brown-out Reset

Interrupt Wake-up from Sleep

0000h

PC + 1

(1)

---1 1uuu

---1 0uuu

00-- 11u0 uu-- uuuu

RESET

Instruction Executed

Stack Overflow Reset (STVREN =

1

)

0000h

0000h

---u uuuu

---u uuuu uu-- u0uu

1u-- uuuu

Stack Underflow Reset (STVREN =

1

) 0000h

---u uuuu u1-- uuuu

Legend:

Note 1:

u

= unchanged, x

= unknown,

-

= unimplemented bit, reads as ‘

0

’.

When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

2:

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

If a Status bit is not implemented, that bit will be read as ‘

0

’.

2010-2012 Microchip Technology Inc.

DS41414D-page 84

PIC16(L)F1946/47

6.12

Power Control (PCON) Register

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

• Stack Overflow Reset (STKOVF)

• Stack Underflow Reset (STKUNF)

• MCLR Reset (RMCLR)

The PCON register bits are shown in

Register 6-2 .

6.13

Register Definitions: Power Control

REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q

STKOVF bit 7

R/W/HS-0/q

STKUNF

U-0

U-0

R/W/HC-1/q

RMCLR

R/W/HC-1/q

RI

R/W/HC-q/u

POR

R/W/HC-q/u

BOR bit 0

Legend:

HC = Bit is cleared by hardware

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared bit 7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0

HS = Bit is set by hardware

U = Unimplemented bit, read as ‘0’

-m/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition

STKOVF:

Stack Overflow Flag bit

1

= A Stack Overflow occurred

0

= A Stack Overflow has not occurred or set to ‘

0

’ by firmware

STKUNF:

Stack Underflow Flag bit

1

= A Stack Underflow occurred

0

= A Stack Underflow has not occurred or set to ‘

0

’ by firmware

Unimplemented:

Read as ‘

0

RMCLR:

MCLR Reset Flag bit

1

= A MCLR Reset has not occurred or set to ‘

1

’ by firmware

0

= A MCLR Reset has occurred (set to ‘

0

’ in hardware when a MCLR Reset occurs)

RI:

RESET

Instruction Flag bit

1

= A

RESET

instruction has not been executed or set to ‘

1

’ by firmware

0

= A

RESET

instruction has been executed (set to ‘

0

’ in hardware upon executing a

RESET

instruction)

POR:

Power-on Reset Status bit

1

= No Power-on Reset occurred

0

= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR:

Brown-out Reset Status bit

1

= No Brown-out Reset occurred

0

= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)

2010-2012 Microchip Technology Inc.

DS41414D-page 85

PIC16(L)F1946/47

TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

BORCON

PCON

SBOREN

STKOVF

STKUNF

RMCLR

RI

POR

BORRDY

BOR

81

85

STATUS — — — TO PD Z DC C

25

WDTCON

Legend:

Note 1:

— — WDTPS<4:0> SWDTEN

109

— = unimplemented, read as ‘

0

’. Shaded cells are not used by Resets.

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS41414D-page 86

2010-2012 Microchip Technology Inc.

7.0

INTERRUPTS

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from

Sleep mode.

This chapter contains the following information for

Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

• INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 7-1 .

FIGURE 7-1: INTERRUPT LOGIC

Peripheral Interrupts

(TMR1IF) PIR1<0>

(TMR1IF) PIR1<0>

PIRn<7>

PIEn<7>

TMR0IF

TMR0IE

INTF

INTE

IOCIF

IOCIE

PEIE

GIE

PIC16(L)F1946/47

Wake-up

(If in Sleep mode)

Interrupt to CPU

2010-2012 Microchip Technology Inc.

DS41414D-page 87

PIC16(L)F1946/47

7.1

Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIE1, PIE2, PIE3 and PIE4 registers)

The INTCON, PIR1, PIR2, PIR3 and PIR4 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the

GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the stack

• Critical registers are automatically saved to the shadow registers (See

Section 7.5 “Automatic

Context Saving” .”

)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.

The

RETFIE

instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupt’s operation, refer to its peripheral chapter.

Note 1:

2:

Individual interrupt flag bits are set, regardless of the state of any other enable bits.

All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

7.2

Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles,

depending on when the interrupt occurs. See Figure 7-2

and Figure 7-3 for more details.

2010-2012 Microchip Technology Inc.

DS41414D-page 88

PIC16(L)F1946/47

FIGURE 7-2: INTERRUPT LATENCY

OSC1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKOUT

Interrupt Sampled during Q1

Interrupt

GIE

PC PC-1 PC

Execute

1 Cycle Instruction at PC

Inst(PC)

PC+1

NOP

0004h

NOP

0005h

Inst(0004h)

Interrupt

GIE

PC

PC-1 PC

Execute 2 Cycle Instruction at PC

PC+1/FSR

ADDR

Inst(PC)

New PC/

PC+1

NOP

0004h

NOP

0005h

Inst(0004h)

Interrupt

GIE

PC PC-1 PC

Execute 3 Cycle Instruction at PC

FSR ADDR

INST(PC)

Interrupt

GIE

PC

PC-1 PC

Execute 3 Cycle Instruction at PC

FSR ADDR

INST(PC)

PC+1

NOP

PC+1

NOP

PC+2

NOP

0004h

NOP

0005h

Inst(0004h) Inst(0005h)

NOP

PC+2

NOP

0004h

NOP

0005h

Inst(0004h)

2010-2012 Microchip Technology Inc.

DS41414D-page 89

PIC16(L)F1946/47

FIGURE 7-3: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

(3)

(4)

INT pin

INTF

(1)

(5)

(1)

Interrupt Latency

(2)

GIE

INSTRUCTION FLOW

PC

Instruction

Fetched

PC

Inst (PC)

PC + 1

Inst (PC + 1)

PC + 1

0004h

Inst (0004h)

0005h

Inst (0005h)

Instruction

Executed

Inst (PC – 1) Inst (PC)

Dummy Cycle Dummy Cycle

Inst (0004h)

Note 1:

2:

3:

4:

5:

INTF flag is sampled here (every Q1).

Asynchronous interrupt latency = 3-5 T

CY

. Synchronous latency = 3-4 T

CY

, where T

CY

= instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

CLKOUT not available in all Oscillator modes.

For minimum width of INT pulse, refer to AC specifications in

Section 30.0 “Electrical Specifications”

.

INTF is enabled to be set any time during the Q4-Q1 cycles.

DS41414D-page 90

2010-2012 Microchip Technology Inc.

7.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the

SLEEP

instruction. The instruction directly after the

SLEEP

instruction will always be executed before branching to the ISR. Refer to the

Section 9.0 “Power-

Down Mode (Sleep)”

for more details.

7.4

INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The

INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and

INTE bits are also set, the processor will redirect program execution to the interrupt vector.

7.5

Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the value will be restored when exiting the ISR. The

Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.

PIC16(L)F1946/47

2010-2012 Microchip Technology Inc.

DS41414D-page 91

PIC16(L)F1946/47

7.6

Register Definitions: Interrupt Control

REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

GIE bit 7

R/W-0/0

PEIE

R/W-0/0

TMR0IE

R/W-0/0

INTE

R/W-0/0

IOCIE

R/W-0/0

TMR0IF

R/W-0/0

INTF

R-0/0

IOCIF bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Note 1:

GIE:

Global Interrupt Enable bit

1

= Enables all active interrupts

0

= Disables all interrupts

PEIE:

Peripheral Interrupt Enable bit

1

= Enables all active peripheral interrupts

0

= Disables all peripheral interrupts

TMR0IE:

Timer0 Overflow Interrupt Enable bit

1

= Enables the Timer0 interrupt

0

= Disables the Timer0 interrupt

INTE:

INT External Interrupt Enable bit

1

= Enables the INT external interrupt

0

= Disables the INT external interrupt

IOCIE:

Interrupt-on-Change Enable bit

1

= Enables the interrupt-on-change

0

= Disables the interrupt-on-change

TMR0IF:

Timer0 Overflow Interrupt Flag bit

1

= TMR0 register has overflowed

0

= TMR0 register did not overflow

INTF:

INT External Interrupt Flag bit

1

= The INT external interrupt occurred

0

= The INT external interrupt did not occur

IOCIF:

Interrupt-on-Change Interrupt Flag bit

1

= When at least one of the interrupt-on-change pins changed state

0

= None of the interrupt-on-change pins have changed state

The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register have been cleared by software.

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

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DS41414D-page 92

PIC16(L)F1946/47

REGISTER 7-2:

R/W-0/0

TMR1GIE bit 7

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0

ADIE

R/W-0/0

RCIE

R/W-0/0

TXIE

R/W-0/0

SSPIE

R/W-0/0

CCP1IE

R/W-0/0

TMR2IE

R/W-0/0

TMR1IE bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

TMR1GIE:

Timer1 Gate Interrupt Enable bit

1

= Enables the Timer1 Gate Acquisition interrupt

0

= Disables the Timer1 Gate Acquisition interrupt

ADIE:

A/D Converter (ADC) Interrupt Enable bit

1

= Enables the ADC interrupt

0

= Disables the ADC interrupt

RCIE:

USART1 Receive Interrupt Enable bit

1

= Enables the USART1 receive interrupt

0

= Disables the USART1 receive interrupt

TXIE:

USART1 Transmit Interrupt Enable bit

1

= Enables the USART1 transmit interrupt

0

= Disables the USART1 transmit interrupt

SSPIE:

Synchronous Serial Port (MSSP1) Interrupt Enable bit

1

= Enables the MSSP1 interrupt

0

= Disables the MSSP1 interrupt

CCP1IE:

CCP1 Interrupt Enable bit

1

= Enables the CCP1 interrupt

0

= Disables the CCP1 interrupt

TMR2IE:

TMR2 to PR2 Match Interrupt Enable bit

1

= Enables the Timer2 to PR2 match interrupt

0

= Disables the Timer2 to PR2 match interrupt

TMR1IE:

Timer1 Overflow Interrupt Enable bit

1

= Enables the Timer1 overflow interrupt

0

= Disables the Timer1 overflow interrupt

Note:

Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

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DS41414D-page 93

PIC16(L)F1946/47

REGISTER 7-3:

R/W-0/0

OSFIE bit 7

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

C2IE

R/W-0/0

C1IE

R/W-0/0

EEIE

R/W-0/0

BCLIE

R/W-0/0

LCDIE

R/W-0/0

C3IE

R/W-0/0

CCP2IE bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

OSFIE:

Oscillator Fail Interrupt Enable bit

1

= Enables the Oscillator Fail interrupt

0

= Disables the Oscillator Fail interrupt

C2IE:

Comparator C2 Interrupt Enable bit

1

= Enables the Comparator C2 interrupt

0

= Disables the Comparator C2 interrupt

C1IE:

Comparator C1 Interrupt Enable bit

1

= Enables the Comparator C1 interrupt

0

= Disables the Comparator C1 interrupt

EEIE:

EEPROM Write Completion Interrupt Enable bit

1

= Enables the EEPROM Write Completion interrupt

0

= Disables the EEPROM Write Completion interrupt

BCLIE:

MSSP1 Bus Collision Interrupt Enable bit

1

= Enables the MSSP1 Bus Collision Interrupt

0

= Disables the MSSP1 Bus Collision Interrupt

LCDIE:

LCD Module Interrupt Enable bit

1

= Enables the LCD module interrupt

0

= Disables the LCD module interrupt

C3IE:

Comparator C3 Interrupt Enable bit

1

= Enables the Comparator C3 interrupt

0

= Disables the Comparator C3 interrupt

CCP2IE:

CCP2 Interrupt Enable bit

1

= Enables the CCP2 interrupt

0

= Disables the CCP2 interrupt

Note:

Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

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DS41414D-page 94

PIC16(L)F1946/47

REGISTER 7-4:

bit 7

U-0

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

R/W-0/0

CCP5IE

R/W-0/0

CCP4IE

R/W-0/0

CCP3IE

R/W-0/0

TMR6IE

U-0

R/W-0/0

TMR4IE

U-0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Unimplemented:

Read as ‘

0

CCP5IE:

CCP5 Interrupt Enable bit

1

= Enables the CCP5 interrupt

0

= Disables the CCP5 interrupt

CCP4IE:

CCP4 Interrupt Enable bit

1

= Enables the CCP4 interrupt

0

= Disables the CCP4 interrupt

CCP3IE:

CCP3 Interrupt Enable bit

1

= Enables the CCP3 interrupt

0

= Disables the CCP3 interrupt

TMR6IE:

TMR6 to PR6 Match Interrupt Enable bit

1

= Enables the TMR6 to PR6 Match interrupt

0

= Disables the TMR6 to PR6 Match interrupt

Unimplemented:

Read as ‘

0

TMR4IE:

TMR4 to PR4 Match Interrupt Enable bit

1

= Enables the TMR4 to PR4 Match interrupt

0

= Disables the TMR4 to PR4 Match interrupt

Unimplemented:

Read as ‘

0

Note:

Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

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DS41414D-page 95

PIC16(L)F1946/47

REGISTER 7-5:

bit 7

U-0

PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4

U-0

R/W-0/0

RC2IE

R/W-0/0

TX2IE

U-0

U-0

R/W-0/0

BCL2IE

R/W-0/0

SSP2IE bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5 bit 4 bit 3-2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Unimplemented:

Read as ‘

0

RC2IE:

USART2 Receive Interrupt Enable bit

1

= Enables the USART2 receive interrupt

0

= Disables the USART2 receive interrupt

TX2IE:

USART2 Transmit Interrupt Enable bit

1

= Enables the USART2 transmit interrupt

0

= Disables the USART2 transmit interrupt

Unimplemented:

Read as ‘

0

BCL2IE:

MSSP2 Bus Collision Interrupt Enable bit

1

= Enables the MSSP2 Bus Collision Interrupt

0

= Disables the MSSP2 Bus Collision Interrupt

SSP2IE:

Synchronous Serial Port (MSSP2) Interrupt Enable bit

1

= Enables the MSSP2 interrupt

0

= Disables the MSSP2 interrupt

Note:

Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

DS41414D-page 96

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

REGISTER 7-6:

R/W-0/0

TMR1GIF bit 7

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0

ADIF

R-0/0

RCIF

R-0/0

TXIF

R/W-0/0

SSPIF

R/W-0/0

CCP1IF

R/W-0/0

TMR2IF

R/W-0/0

TMR1IF bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

TMR1GIF:

Timer1 Gate Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

ADIF:

A/D Converter Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

RCIF:

USART1 Receive Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

TXIF:

USART1 Transmit Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

SSPIF:

Synchronous Serial Port (MSSP1) Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

CCP1IF:

CCP1 Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

TMR2IF:

Timer2 to PR2 Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

TMR1IF:

Timer1 Overflow Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

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DS41414D-page 97

PIC16(L)F1946/47

REGISTER 7-7:

R/W-0/0

OSFIF bit 7

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

C2IF

R/W-0/0

C1IF

R/W-0/0

EEIF

R/W-0/0

BCLIF

R/W-0/0

LCDIF

U-0

R/W-0/0

CCP2IF bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

OSFIF:

Oscillator Fail Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

C2IF:

Comparator C2 Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

C1IF:

Comparator C1 Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

EEIF:

EEPROM Write Completion Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

BCLIF:

MSSP1 Bus Collision Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

LCDIF:

LCD Module Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Unimplemented:

Read as ‘

0

CCP2IF:

CCP2 Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

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DS41414D-page 98

PIC16(L)F1946/47

REGISTER 7-8:

R/W-0/0

— bit 7

PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

R/W-0/0

CCP5IF

R/W-0/0

CCP4IF

R/W-0/0

CCP3IF

R/W-0/0

TMR6IF

R/W-0/0

R/W-0/0

TMR4IF

R/W-0/0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Unimplemented:

Read as ‘

0

CCP5IF:

CCP5 Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

CCP4IF:

CCP4 Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

CCP3IF:

CCP3 Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

TMR6IF:

TMR6 to PR6 Match Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Unimplemented:

Read as ‘

0

TMR4IF:

TMR4 to PR4 Match Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Unimplemented:

Read as ‘

0

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

2010-2012 Microchip Technology Inc.

DS41414D-page 99

PIC16(L)F1946/47

REGISTER 7-9:

bit 7

U-0

PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4

U-0

R/W-0/0

RC2IF

R/W-0/0

TX2IF

U-0

U-0

R/W-0/0

BCL2IF

R/W-0/0

SSP2IF bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5 bit 4 bit 3-2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Unimplemented:

Read as ‘

0

RC2IF:

USART2 Receive Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

TX2IF:

USART2 Transmit Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Unimplemented:

Read as ‘

0

BCL2IF:

MSSP2 Bus Collision Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

SSP2IF:

Synchronous Serial Port (MSSP2) Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

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DS41414D-page 100

PIC16(L)F1946/47

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE

OPTION_REG WPUEN

PIE1 TMR1GIE

INTEDG

ADIE

PIE2

PIE3

PIE4

PIR1

PIR2

PIR3

PIR4

Legend:

OSFIE

TMR1GIF

C2IE

CCP5IE

ADIF

TMR0IE

T0CS

RCIE

C1IE

CCP4IE

RC2IE

RCIF

INTE

T0SE

TXIE

EEIE

CCP3IE

TX2IE

TXIF

IOCIE

PSA

SSPIE

BCLIE

TMR6IE

SSPIF

TMR0IF

CCP1IE

LCDIE

CCP1IF

INTF

PS<2:0>

TMR2IE

C3IE

TMR4IE

BCL2IE

TMR2IF

OSFIF

C2IF

CCP5IF

C1IF

CCP4IF

EEIF

CCP3IF

BCLIF

TMR6IF

LCDIF

C3IF

TMR4IF

— — RC2IF TX2IF — — BCL2IF

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by Interrupts.

IOCIF

TMR1IE

CCP2IE

SSP2IE

TMR1IF

CCP2IF

SSP2IF

Register on Page

92

197

93

94

95

96

97

98

99

100

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DS41414D-page 101

PIC16(L)F1946/47

NOTES:

DS41414D-page 102

2010-2012 Microchip Technology Inc.

8.0

LOW DROPOUT (LDO)

VOLTAGE REGULATOR

The PIC16F1946/47 has an internal Low Dropout

Regulator (LDO) which provides operation above 3.6V.

The LDO regulates a voltage for the internal device logic while permitting the V

DD

and I/O pins to operate at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The

PIC16LF1946/47 operates at a maximum V

DD

of 3.6V

and does not incorporate an LDO.

A device I/O pin may be configured as the LDO voltage output, identified as the V

CAP

pin. Although not required, an external low-ESR capacitor may be connected to the V

CAP

pin for additional regulator stability.

The VCAPEN bit of Configuration Words enables or disables the V

CAP

pin. Refer to Table 8-1 .

TABLE 8-1:

VCAPEN

0

1

VCAPEN SELECT BIT

Pin

RF0

No Vcap

PIC16(L)F1946/47

On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information on the constant current rate, refer to the

LDO Regulator Characteristics Table in

Section 30.0

“Electrical Specifications”

.

TABLE 8-2:

Name Bits

SUMMARY OF CONFIGURATION WORD WITH LDO

Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2

CONFIG2

Legend:

13:8 — — LVP DEBUG — BORV

7:0 — — — VCAPEN — —

— = unimplemented locations read as ‘

0

’. Shaded cells are not used by LDO.

Bit 9/1

STVREN

WRT1

Bit 8/0

PLLEN

WRT0

Register on Page

58

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PIC16(L)F1946/47

NOTES:

DS41414D-page 104

2010-2012 Microchip Technology Inc.

9.0

POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a

SLEEP

instruction.

Upon entering Sleep mode, the following conditions exist:

2.

3.

4.

5.

1.

WDT will be cleared but keeps running, if enabled for operation during Sleep.

PD bit of the STATUS register is cleared.

TO bit of the STATUS register is set.

CPU clock is disabled.

31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in

Sleep.

6.

7.

Timer1 oscillator is unaffected and peripherals that operate from it may continue operation in

Sleep.

ADC is unaffected, if the dedicated FRC clock is selected.

Capacitive Sensing oscillator is unaffected.

8.

9.

I/O ports maintain the status they had before

SLEEP

was executed (driving high, low or highimpedance).

10. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Timer1 oscillator

I/O pins that are high-impedance inputs should be pulled to V

DD

or V

SS

externally to avoid switching currents caused by floating inputs.

Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See

Section 17.0 “Digital-to-Analog Converter (DAC) Module”

and

Section 14.0 “Fixed Voltage Reference (FVR)”

for more information on these

modules.

PIC16(L)F1946/47

9.1

Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

4.

5.

6.

1.

2.

3.

External Reset input on MCLR pin, if enabled

BOR Reset, if enabled

POR Reset

Watchdog Timer, if enabled

Any external interrupt

Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)

The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to

Section 6.11

“Determining the Cause of a Reset”

.

When the

SLEEP

instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the

SLEEP

instruction. If the GIE bit is enabled, the device executes the instruction after the

SLEEP

instruction, the device will then call the Interrupt

Service Routine. In cases where the execution of the instruction following

SLEEP is not desirable, the user should have a

NOP

after the

SLEEP

instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

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DS41414D-page 105

PIC16(L)F1946/47

9.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs

before

the execution of a

SLEEP

instruction

-

SLEEP

instruction will execute as a

NOP

.

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

- PD bit of the STATUS register will not be cleared.

• If the interrupt occurs

during or after

the execution of a

SLEEP

instruction

-

SLEEP

instruction will be completely executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared.

Even if the flag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to become set before the

SLEEP

instruction completes. To determine whether a

SLEEP

instruction executed, test the PD bit. If the PD bit is set, the

SLEEP

instruction was executed as a

NOP

.

FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

OSC1

(1)

CLKOUT

(2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

T

OST

(3)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Interrupt Latency

(4)

Instruction Flow

PC

Instruction

Fetched

Instruction

Executed

PC

Inst(PC) = Sleep

Inst(PC - 1)

PC + 1

Inst(PC + 1)

Sleep

PC + 2 PC + 2

Inst(PC + 2)

Inst(PC + 1)

PC + 2

Forced

NOP

0004h

Inst(0004h)

Forced

NOP

0005h

Inst(0005h)

Inst(0004h)

Note 1:

2:

3:

4:

XT, HS or LP Oscillator mode assumed.

CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.

T

OST

= 1024 T

OSC

(drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.

GIE =

1

assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE =

0

, execution will continue in-line.

Name

INTCON

IOCBF

IOCBN

IOCBP

PIE1

PIE2

PIE3

PIE4

PIR1

PIR2

PIR3

PIR4

STATUS

WDTCON

Legend:

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

GIE

IOCBF7

IOCBN7

IOCBP7

TMR1GIE

OSFIE

PEIE

IOCBF6

IOCBN6

IOCBP6

ADIE

C2IE

CCP5IE

TMR0IE

IOCBF5

IOCBN5

IOCBP5

RCIE

C1IE

CCP4IE

INTE

IOCBF4

IOCBN4

IOCBP4

TXIE

EEIE

CCP3IE

IOCIE

IOCBF3

IOCBN3

IOCBP3

SSPIE

BCLIE

TMR6IE

TMR0IF

IOCBF2

IOCBN2

IOCBP2

CCP1IE

LCDIE

TMR1GIF

OSFIF

ADIF

C2IF

CCP5IF

RC2IE

RCIF

C1IF

CCP4IF

TX2IE

TXIF

EEIF

CCP3IF

SSPIF

BCLIF

TMR6IF

CCP1IF

LCDIF

BCL2IE

TMR2IF

C3IF

TMR4IF

RC2IF

TX2IF

TO

PD

Z

— — WDTPS<4:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used in Power-Down mode.

BCL2IF

DC

INTF

IOCBF1

IOCBN1

IOCBP1

TMR2IE

C3IE

TMR4IE

Bit 0

IOCIF

IOCBF0

IOCBN0

IOCBP0

TMR1IE

CCP2IE

SSP2IE

TMR1IF

CCP2IF

SSP2IF

C

SWDTEN

Register on

Page

96

97

98

99

100

25

109

92

155

155

155

93

94

95

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

10.0

WATCHDOG TIMER (WDT)

The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a

CLRWDT instruction within the time-out period. The Watchdog

Timer is typically used to recover the system from unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256 seconds (nominal)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM

WDTE<1:0> =

01

SWDTEN

WDTE<1:0> =

11

WDTE<1:0> =

10

Sleep

LFINTOSC

23-bit Programmable

Prescaler WDT

WDTPS<4:0>

WDT Time-out

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PIC16(L)F1946/47

10.1

Independent Clock Source

The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See

Section 30.0 “Electrical Specifications”

for the

LFINTOSC tolerances.

10.3

Time-Out Period

The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal).

After a Reset, the default time-out period is 2 seconds.

10.2

WDT Operating Modes

The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration

Words. See Table 10-1

.

10.2.1

WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to

11

’, the WDT is always on.

WDT protection is active during Sleep.

10.2.2

WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to

10

’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

10.2.3

WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to

01

’, the WDT is controlled by the SWDTEN bit of the

WDTCON register.

WDT protection is unchanged by Sleep. See

Table 10-1

for more details.

10.4

TABLE 10-1:

WDTE<1:0>

11

10

01

00

WDT OPERATING MODES

SWDTEN

Device

Mode

X

X

X

Awake

Sleep

1

0

X

X

X

WDT

Mode

Active

Active

Disabled

Active

Disabled

Disabled

TABLE 10-2: WDT CLEARING CONDITIONS

Conditions

WDTE<1:0> =

00

WDTE<1:0> =

01 and SWDTEN =

0

WDTE<1:0> =

10 and enter Sleep

CLRWDT

Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Change INTOSC divider (IRCF bits)

Clearing the WDT

The WDT is cleared when any of the following conditions occur:

• Any Reset

CLRWDT

instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail

• WDT is disabled

• Oscillator Start-up Timer (OST) is running

See Table 10-2

for more information.

10.5

Operation During Sleep

When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting.

When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See

Section 5.0 “Oscillator

Module (With Fail-Safe Clock Monitor)”

for more

information on the OST.

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the

STATUS register are changed to indicate the event. See

Section 3.0 “Memory Organization”

and STATUS register (

Register 3-1 )

for more information.

WDT

Cleared

Cleared until the end of OST

Unaffected

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

10.6

Register Definitions: Watchdog Control

REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

bit 7

U-0

U-0

R/W-0/0 R/W-1/1 R/W-0/0

WDTPS<4:0>

R/W-1/1 R/W-1/1 R/W-0/0

SWDTEN bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-m/n = Value at POR and BOR/Value at all other Resets

Unimplemented:

Read as ‘

0

WDTPS<4:0>:

Watchdog Timer Period Select bits

Bit Value = Prescale Rate

00000

= 1:32 (Interval 1 ms typ)

00001

= 1:64 (Interval 2 ms typ)

00010

= 1:128 (Interval 4 ms typ)

00011

= 1:256 (Interval 8 ms typ)

00100

= 1:512 (Interval 16 ms typ)

00101

= 1:1024 (Interval 32 ms typ)

00110

= 1:2048 (Interval 64 ms typ)

00111

= 1:4096 (Interval 128 ms typ)

01000

= 1:8192 (Interval 256 ms typ)

01001

= 1:16384 (Interval 512 ms typ)

01010

= 1:32768 (Interval 1s typ)

01011

= 1:65536 (Interval 2s typ) (Reset value)

01100

= 1:131072 (2

01101

= 1:262144 (2

17

18

) (Interval 4s typ)

01110

= 1:524288 (2

19

01111

= 1:1048576 (2

) (Interval 8s typ)

) (Interval 16s typ)

20

10000

= 1:2097152 (2

21

) (Interval 32s typ)

) (Interval 64s typ)

10001

= 1:4194304 (2

22

10010

= 1:8388608 (2

23

) (Interval 128s typ)

) (Interval 256s typ)

10011

= Reserved. Results in minimum interval (1:32)

11111

= Reserved. Results in minimum interval (1:32)

SWDTEN:

Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> =

00

:

This bit is ignored.

If WDTE<1:0> =

01

:

1

= WDT is turned on

0

= WDT is turned off

If WDTE<1:0> =

1x

:

This bit is ignored.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name

OSCCON

STATUS

WDTCON

Legend:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

— IRCF<3:0> — SCS<1:0>

75

— — — TO PD Z DC C

25

— — WDTPS<4:0> SWDTEN

109

x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by Watchdog Timer.

TABLE 10-4:

Name Bits

SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend:

13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0>

7:0 CP MCLRE PWRTE WDTE<1:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by Watchdog Timer.

FOSC<2:0>

CPD

Register on Page

56

DS41414D-page 110

2010-2012 Microchip Technology Inc.

11.0

DATA EEPROM AND FLASH

PROGRAM MEMORY

CONTROL

The data EEPROM and Flash program memory are readable and writable during normal operation (full V

DD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers

(SFRs). There are six SFRs used to access these memories:

• EECON1

• EECON2

• EEDATL

• EEDATH

• EEADRL

• EEADRH

When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EEDATL location being accessed.

These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh.

When accessing the program memory block, the EED-

ATH:EEDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the EEADRL and EEADRH registers form a 2-byte word that holds the 15-bit address of the program memory location being read.

The EEPROM data memory allows byte read and write.

An EEPROM byte write automatically erases the location and writes the new data (erase before write).

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations.

Depending on the setting of the Flash Program

Memory Self Write Enable bits WRT<1:0> of the

Configuration Words, the device may or may not be able to write certain blocks of the program memory.

However, reads from the program memory are always allowed.

When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.

PIC16(L)F1946/47

11.1

EEADRL and EEADRH Registers

The EEADRH:EEADRL register pair can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 32K words of program memory.

When selecting a program address value, the MSB of the address is written to the EEADRH register and the

LSB is written to the EEADRL register. When selecting a EEPROM address value, only the LSB of the address is written to the EEADRL register.

11.1.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for EE memory accesses.

Control bit EEPGD determines if the access will be a program or data memory access. When clear, any subsequent operations will operate on the EEPROM memory. When set, any subsequent operations will operate on the program memory. On Reset, EEPROM is selected by default.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature termination of a write operation.

The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine.

Interrupt flag bit EEIF of the PIR2 register is set when write is complete. It must be cleared in the software.

Reading EECON2 will read all ‘

0

’s. The EECON2 register is used exclusively in the data EEPROM write sequence. To enable writes, a specific pattern must be written to EECON2.

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11.2

Using the Data EEPROM

The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the

EEPROM without exceeding the total number of write cycles to a single byte. Refer to

Section 30.0 “Electrical Specifications”

. If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory.

11.2.1

READING THE DATA EEPROM

MEMORY

To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD and

CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation).

EXAMPLE 11-1: DATA EEPROM READ

BANKSEL EEADRL

MOVLW

;

DATA_EE_ADDR ;

MOVWF EEADRL ;Data Memory

;Address to read

BCF

BCF

BSF

MOVF

EECON1, CFGS ;Deselect Config space

EECON1, EEPGD;Point to DATA memory

EECON1, RD

EEDATL, W

;EE Read

;W = EEDATL

Note:

Data EEPROM can be read regardless of the setting of the CPD bit.

11.2.2

WRITING TO THE DATA EEPROM

MEMORY

To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte.

The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to

EECON2, then set the WR bit) for each byte. Interrupts should be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.

11.2.3

PROTECTION AGAINST SPURIOUS

WRITE

There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the

Power-up Timer (64 ms duration) prevents EEPROM write.

The write initiate sequence and the WREN bit together help prevent an accidental write during:

• Brown-out

• Power Glitch

• Software Malfunction

11.2.4

DATA EEPROM OPERATION

DURING CODE-PROTECT

Data memory can be code-protected by programming the CPD bit in the Configuration Words to ‘

0

’.

When the data memory is code-protected, only the

CPU is able to read and write data to the data

EEPROM. It is recommended to code-protect the program memory when code-protecting data memory.

This prevents anyone from replacing your program with a program that will access the contents of the data

EEPROM.

2010-2012 Microchip Technology Inc.

DS41414D-page 112

EXAMPLE 11-2: DATA EEPROM WRITE

BANKSEL EEADRL

MOVLW DATA_EE_ADDR

MOVWF

MOVLW

EEADRL

DATA_EE_DATA

MOVWF

BCF

BCF

BSF

EEDATL

EECON1, CFGS

EECON1, EEPGD

EECON1, WREN

;

;

;Data Memory Address to write

;

;Data Memory Value to write

;Deselect Configuration space

;Point to DATA memory

;Enable writes

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BSF

BCF

BTFSC

GOTO

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

INTCON, GIE

EECON1, WREN

EECON1, WR

$-2

;Disable INTs.

;

;Write 55h

;

;Write AAh

;Set WR bit to begin write

;Enable Interrupts

;Disable writes

;Wait for write to complete

;Done

PIC16(L)F1946/47

FIGURE 11-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Flash ADDR

Flash Data

PC PC + 1 EEADRH,EEADRL PC + 4 PC + 5

INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4)

INSTR(PC - 1) executed here

BSF EECON1,RD executed here

INSTR(PC + 1) executed here

Forced

NOP executed here

INSTR(PC + 3) executed here

INSTR(PC + 4) executed here

RD bit

EEDATH

EEDATL

Register

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PIC16(L)F1946/47

11.3

Flash Program Memory Overview

It is important to understand the Flash program memory structure for erase and programming operations.

Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software.

Flash program memory may only be written or erased if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of Configuration Words.

After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the EEDATH:EEDATL register pair.

Note:

If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase.

The number of data write latches may not be equivalent to the number of row locations. During programming, user software may need to fill the set of write latches and initiate a programming operation multiple times in order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times.

The size of a program memory row and the number of program memory write latches may vary by device.

See Table 11-1

for details.

11.3.1

READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must:

1.

2.

3.

Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair.

Clear the CFGS bit of the EECON1 register.

Set the EEPGD control bit of the EECON1 register.

Then, set control bit RD of the EECON1 register.

4.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “

BSF EECON1,RD

” instruction to be ignored. The data is available in the very next cycle, in the EEDATH:EEDATL register pair; therefore, it can be read as two bytes in the following instructions.

EEDATH:EEDATL register pair will hold this value until another read or until it is written to by the user.

Note 1:

2:

The two instructions following a program memory read are required to be

NOP s.

This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set.

Flash program memory can be read regardless of the setting of the CP bit.

TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE

Device

PIC16(L)F1946/47

Erase Block (Row) Size/Boundary

32 words, EEADRL<4:0> =

00000

Number of Write Latches/Boundary

32 words, EEADRL<4:0> =

00000

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

EXAMPLE 11-3: FLASH PROGRAM MEMORY READ

*

*

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI: PROG_ADDR_LO data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL

MOVLW

MOVWF

MOVLW

MOVWL

BCF

BSF

BCF

BSF

NOP

NOP

BSF

EEADRL

PROG_ADDR_LO

EEADRL

PROG_ADDR_HI

EEADRH

EECON1,CFGS

EECON1,EEPGD

INTCON,GIE

EECON1,RD

INTCON,GIE

MOVF

MOVWF

MOVF

MOVWF

EEDATL,W

PROG_DATA_LO

EEDATH,W

PROG_DATA_HI

; Select Bank for EEPROM registers

;

; Store LSB of address

;

; Store MSB of address

; Do not select Configuration Space

; Select Program Memory

; Disable interrupts

; Initiate read

; Executed (

Figure 11-1 )

; Ignored (

Figure 11-1 )

; Restore interrupts

; Get LSB of word

; Store in user location

; Get MSB of word

; Store in user location

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PIC16(L)F1946/47

11.3.2

ERASING FLASH PROGRAM

MEMORY

While executing code, program memory can only be erased by rows. To erase a row:

1.

2.

3.

4.

5.

6.

Load the EEADRH:EEADRL register pair with the address of new row to be erased.

Clear the CFGS bit of the EECON1 register.

Set the EEPGD, FREE, and WREN bits of the

EECON1 register.

Write 55h, then AAh, to EECON2 (Flash programming unlock sequence).

Set control bit WR of the EECON1 register to begin the erase operation.

Poll the FREE bit in the EECON1 register to determine when the row erase has completed.

See Example 11-4

.

After the “

BSF EECON1,WR

” instruction, the processor requires two cycles to set up the erase operation. The user must place two

NOP

instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.

11.3.3

WRITING TO FLASH PROGRAM

MEMORY

Program memory is programmed using the following steps:

1.

2.

3.

4.

Load the starting address of the word(s) to be programmed.

Load the write latches with data.

Initiate a programming operation.

Repeat steps 1 through 3 until all data is written.

Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See

Figure 11-2 (block writes to program memory with 16 write latches) for more details. The write latches are aligned to the address boundary defined by EEADRL

as shown in Table 11-1

. Write operations do not cross these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF.

The following steps should be completed to load the write latches and program a block of program memory.

These steps are divided into two parts. First, all write latches are loaded with data except for the last program memory location. Then, the last write latch is loaded and the programming sequence is initiated. A special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. This unlock sequence should not be interrupted.

1.

2.

3.

Set the EEPGD and WREN bits of the EECON1 register.

Clear the CFGS bit of the EECON1 register.

Set the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is ‘

1

’, the write sequence will only load the write latches and will not initiate the write to Flash program memory.

4.

5.

Load the EEADRH:EEADRL register pair with the address of the location to be written.

Load the EEDATH:EEDATL register pair with the program memory data to be written.

6.

7.

8.

Write 55h, then AAh, to EECON2, then set the

WR bit of the EECON1 register (Flash programming unlock sequence). The write latch is now loaded.

Increment the EEADRH:EEADRL register pair to point to the next location.

Repeat steps 5 through 7 until all but the last write latch has been loaded.

9.

Clear the LWLO bit of the EECON1 register.

When the LWLO bit of the EECON1 register is

0

’, the write sequence will initiate the write to

Flash program memory.

10. Load the EEDATH:EEDATL register pair with the program memory data to be written.

11. Write 55h, then AAh, to EECON2, then set the

WR bit of the EECON1 register (Flash programming unlock sequence). The entire latch block is now written to Flash program memory.

It is not necessary to load the entire write latch block with user program data. However, the entire write latch block will be written to program memory.

An example of the complete write sequence for eight

words is shown in Example 11-5

. The initial address is loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing.

Note:

The code sequence provided in

Example 11-5 must be repeated multiple

times to fully program an erased program memory row.

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DS41414D-page 116

PIC16(L)F1946/47

After the “

BSF EECON1,WR

” instruction, the processor requires two cycles to set up the write operation. The user must place two

NOP

instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will

FIGURE 11-2:

continue to run. The processor does not stall when

LWLO =

1

, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.

BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES

7 5 0 7 0

EEDATH

EEDATA

6

8

First word of block to be written

Last word of block to be written

14

14 14 14

EEADRL<4:0> =

00000

EEADRL<4:0> =

00001

Buffer Register

EEADRL<4:0> =

Buffer Register

00010

EEADRL<4:0> =

Buffer Register

11111

Buffer Register

Program Memory

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PIC16(L)F1946/47

EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY -

; This row erase routine assumes the following:

; 1. A valid address within the erase block is loaded in ADDRH:ADDRL

; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

BSF

BCF

BSF

BSF

MOVLW

MOVWF

INTCON,GIE

EEADRL

ADDRL,W

EEADRL

ADDRH,W

EEADRH

EECON1,EEPGD

EECON1,CFGS

EECON1,FREE

EECON1,WREN

; Disable ints so required sequences will execute properly

; Load lower 8 bits of erase address boundary

; Load upper 6 bits of erase address boundary

; Point to program memory

; Not configuration space

; Specify an erase operation

; Enable writes

55h

EECON2

MOVLW 0AAh

MOVWF EECON2

BSF

NOP

NOP

EECON1,WR

; Start of required sequence to initiate erase

; Write 55h

;

; Write AAh

; Set WR bit to begin erase

; Any instructions here are ignored as processor

; halts to begin erase sequence

; Processor will stop here and wait for erase complete.

BCF

BSF

EECON1,WREN

INTCON,GIE

; after erase processor continues with 3rd instruction

; Disable writes

; Enable interrupts

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PIC16(L)F1946/47

EXAMPLE 11-5: WRITING TO FLASH PROGRAM MEMORY

; This write routine assumes the following:

; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

;

BCF

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

MOVLW

MOVWF

INTCON,GIE

EEADRH

ADDRH,W

; Disable ints so required sequences will execute properly

; Bank 3

; Load initial address

EEADRH ;

ADDRL,W ;

EEADRL ;

LOW DATA_ADDR ; Load initial data address

FSR0L ;

MOVLW

MOVWF

BSF

BCF

BSF

BSF

HIGH DATA_ADDR ; Load initial data address

FSR0H ;

EECON1,EEPGD

EECON1,CFGS

; Point to program memory

; Not configuration space

EECON1,WREN

EECON1,LWLO

; Enable writes

; Only Load Write Latches

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

FSR0++ ; Load first data byte into lower

EEDATL ;

FSR0++ ; Load second data byte into upper

EEDATH ;

MOVF

XORLW

ANDLW

BTFSC

GOTO

EEADRL,W

0x07

; Check if lower bits of address are '000'

; Check if we're on the last of 8 addresses

0x07 ;

STATUS,Z ; Exit if last of eight words,

START_WRITE ;

MOVLW

MOVWF

BSF

NOP

55h

EECON2

MOVLW 0AAh

MOVWF EECON2

EECON1,WR

NOP

; Start of required write sequence:

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; Any instructions here are ignored as processor

; halts to begin write sequence

; Processor will stop here and wait for write to complete.

INCF

GOTO

START_WRITE

BCF

EEADRL,F

LOOP

; After write processor continues with 3rd instruction.

; Still loading latches Increment address

; Write next latches

MOVLW

MOVWF

MOVLW

MOVWF

BSF

NOP

NOP

BCF

BSF

EECON1,LWLO

EECON1,WREN

INTCON,GIE

; No more loading latches - Actually start Flash program

; memory write

55h

EECON2

; Start of required write sequence:

; Write 55h

0AAh ;

EECON2 ; Write AAh

EECON1,WR ; Set WR bit to begin write

; Any instructions here are ignored as processor

; halts to begin write sequence

; Processor will stop here and wait for write complete.

; after write processor continues with 3rd instruction

; Disable writes

; Enable interrupts

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11.4

Modifying Flash Program Memory

When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps:

1.

2.

3.

4.

5.

6.

7.

8.

Load the starting address of the row to be modified.

Read the existing data from the row into a RAM image.

Modify the RAM image to contain the new data to be written into program memory.

Load the starting address of the row to be rewritten.

Erase the program memory row.

Load the write latches with data from the RAM image.

Initiate a programming operation.

Repeat steps 6 and 7 as many times as required to reprogram the erased row.

11.5

User ID, Device ID and

Configuration Word Access

Instead of accessing program memory or EEPROM data memory, the User ID’s, Device ID/Revision ID and

Configuration Words can be accessed when CFGS =

1 in the EECON1 register. This is the region that would be pointed to by PC<15> =

1

, but not all addresses are accessible. Different access may exist for reads and writes. Refer to

Table 11-2 .

When read access is initiated on an address outside the

parameters listed in Table 11-2 , the EEDATH:EEDATL

register pair is cleared.

TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS =

1

)

Address

8000h-8003h

8006h

8007h-8008h

Function

User IDs

Device ID/Revision ID

Configuration Words 1 and 2

Read Access

Yes

Yes

Yes

Write Access

Yes

No

No

EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:

* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;

* PROG_DATA_HI, PROG_DATA_LO

BANKSEL

MOVLW

MOVWF

CLRF

BSF

BCF

BSF

NOP

NOP

BSF

EEADRL

PROG_ADDR_LO

EEADRL

EEADRH

EECON1,CFGS

INTCON,GIE

EECON1,RD

INTCON,GIE

MOVF

MOVWF

MOVF

MOVWF

EEDATL,W

PROG_DATA_LO

EEDATH,W

PROG_DATA_HI

; Select correct Bank

;

; Store LSB of address

; Clear MSB of address

; Select Configuration Space

; Disable interrupts

; Initiate read

; Executed (See

Figure 11-1

)

; Ignored (See

Figure 11-1

)

; Restore interrupts

; Get LSB of word

; Store in user location

; Get MSB of word

; Store in user location

2010-2012 Microchip Technology Inc.

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11.6

Write Verify

Depending on the application, good programming practice may dictate that the value written to the data

EEPROM or program memory should be verified (see

Example 11-6 ) to the desired value to be written.

Example 11-6 shows how to verify a write to EEPROM.

EXAMPLE 11-6: EEPROM WRITE VERIFY

BANKSEL EEDATL

MOVF EEDATL, W

BSF

;

;EEDATL not changed

;from previous write

EECON1, RD ;YES, Read the

XORWF

BTFSS

GOTO

:

EEDATL, W

STATUS, Z

WRITE_ERR

;value written

;

;Is data the same

;No, handle error

;Yes, continue

PIC16(L)F1946/47

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PIC16(L)F1946/47

11.7

Register Definitions: Data EEPROM Control

REGISTER 11-1: EEDATL: EEPROM DATA LOW BYTE REGISTER

R/W-x/u bit 7

R/W-x/u R/W-x/u R/W-x/u R/W-x/u

EEDAT<7:0>

R/W-x/u R/W-x/u

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

EEDAT<7:0>

: Read/write value for EEPROM data byte or Least Significant bits of program memory

REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER

bit 7

U-0

U-0

R/W-x/u R/W-x/u R/W-x/u R/W-x/u

EEDAT<13:8>

R/W-x/u R/W-x/u bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5-0

Unimplemented:

Read as ‘

0

EEDAT<13:8>

: Read/write value for Most Significant bits of program memory

R/W-x/u bit 0

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PIC16(L)F1946/47

REGISTER 11-3:

R/W-0/0

EEADRL: EEPROM ADDRESS LOW BYTE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

EEADR<7:0>

R/W-0/0 bit 7

R/W-0/0 R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

EEADR<7:0>

: Specifies the Least Significant bits for program memory address or EEPROM address

REGISTER 11-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER

bit 7

U-1

(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

EEADR<14:8>

R/W-0/0 R/W-0/0 R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-0

Unimplemented:

Read as ‘

1

EEADR<14:8>

: Specifies the Most Significant bits for program memory address or EEPROM address

Note 1:

Unimplemented, read as ‘

1

’.

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PIC16(L)F1946/47

REGISTER 11-5:

R/W-0/0

EEPGD bit 7

EECON1: EEPROM CONTROL 1 REGISTER

R/W-0/0

CFGS

R/W-0/0

LWLO

R/W/HC-0/0

FREE

R/W-x/q

WRERR

R/W-0/0

WREN

R/S/HC-0/0

WR

R/S/HC-0/0

RD bit 0

Legend:

R = Readable bit

S = Bit can only be set

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

EEPGD:

Flash Program/Data EEPROM Memory Select bit

1

= Accesses program space Flash memory

0

= Accesses data EEPROM memory

CFGS:

Flash Program/Data EEPROM or Configuration Select bit

1

= Accesses Configuration, User ID and Device ID Registers

0

= Accesses Flash Program or data EEPROM Memory

LWLO:

Load Write Latches Only bit

If CFGS =

1

(Configuration space)

OR

CFGS =

0

and EEPGD =

1

(program Flash):

1

= The next WR command does not initiate a write; only the program memory latches are updated.

0

= The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches.

If CFGS =

0

and EEPGD =

0

: (Accessing data EEPROM)

LWLO is ignored. The next WR command initiates a write to the data EEPROM.

FREE:

Program Flash Erase Enable bit

If CFGS =

1

(Configuration space)

OR

CFGS =

0

and EEPGD =

1

(program Flash):

1

= Performs an erase operation on the next WR command (cleared by hardware after completion of erase).

0

= Performs a write operation on the next WR command.

If EEPGD =

0 and CFGS =

0

: (Accessing data EEPROM)

FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.

WRERR:

EEPROM Error Flag bit

1

= Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘

1

’) of the WR bit).

0

= The program or erase operation completed normally.

WREN:

Program/Erase Enable bit

1

= Allows program/erase cycles

0

= Inhibits programming/erasing of program Flash and data EEPROM

WR:

Write Control bit

1

= Initiates a program Flash or data EEPROM program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

0

= Program/erase operation to the Flash or data EEPROM is complete and inactive.

RD:

Read Control bit

1

= Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software.

0

= Does not initiate a program Flash or data EEPROM data read.

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PIC16(L)F1946/47

REGISTER 11-6:

W-0/0

EECON2: EEPROM CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0

EEPROM Control Register 2 bit 7

W-0/0 W-0/0 W-0/0 bit 0

Legend:

R = Readable bit

S = Bit can only be set

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

Data EEPROM Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

EECON1 register. The value written to this register is used to unlock the writes. There are specific

timing requirements on these writes. Refer to

Section 11.2.2 “Writing to the Data EEPROM

Memory”

for more information.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EECON1

EECON2

EEADRL

EEADRH

EEDATL

EEDATH

INTCON

PIE2

PIR2

Legend:

*

Note 1:

EEPGD CFGS LWLO FREE WRERR WREN

EEPROM Control Register 2 (not a physical register)

EEADRL<7:0>

WR RD

(1)

EEADRH<6:0>

EEDATL<7:0>

GIE

OSFIE

OSFIF

PEIE

C2IE

C2IF

TMR0IE

C1IE

C1IF

INTE

EEIE

EEIF

EEDATH<5:0>

IOCIE

BCLIE

BCLIF

TMR0IF

LCDIE

LCDIF

INTF

C3IE

C3IF

= unimplemented location, read as ‘

0

’. Shaded cells are not used by data EEPROM module.

Page provides register information.

Unimplemented, read as ‘

1

’.

IOCIF

CCP2IE

CCP2IF

Register on

Page

122

122

92

94

98

124

111

*

123

123

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PIC16(L)F1946/47

NOTES:

DS41414D-page 126

2010-2012 Microchip Technology Inc.

12.0

I/O PORTS

Each port has three standard registers for its operation.

These registers are:

• TRISx registers (data direction)

• PORTx registers (reads the levels on the pins of the device)

• LATx registers (output latch)

Some ports may have one or more of the following additional registers. These registers are:

• ANSELx (analog select)

• WPUx (weak pull-up)

In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output.

However, the pin can still be read.

TABLE 12-1: PORT AVAILABILITY PER

DEVICE

Device

PIC16F1946

PIC16F1947

The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving.

A write operation to the LATx register has the same effect as a write to the corresponding PORTx register.

A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value.

Ports that support analog inputs have an associated

ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled.

Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in

Figure 12-1 .

PIC16(L)F1946/47

FIGURE 12-1: GENERIC I/O PORT

OPERATION

Read LATx

TRISx

D Q

Write LATx

Write PORTx

CK

Data Register

Data Bus

Read PORTx

To peripherals

ANSELx

V

DD

V

SS

I/O pin

EXAMPLE 12-1: INITIALIZING PORTA

; This code example illustrates

; initializing the PORTA register. The

; other ports are initialized in the same

; manner.

BANKSEL PORTA

CLRF PORTA

BANKSEL LATA

CLRF LATA

;

;Init PORTA

;Data Latch

;

; BANKSEL ANSELA

CLRF ANSELA

BANKSEL TRISA

MOVLW

;

B'00111000' ;Set RA<5:3> as inputs

MOVWF TRISA ;and set RA<2:0> as

;outputs

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12.1

Alternate Pin Function

The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in

Register 12-1 . For this device family, the

following functions can be moved between different pins.

• CCP3/P3C output

• CCP3/P3B output

• CCP2/P2D output

• CCP2/P2C output

• CCP2/P2B output

• CCP2/P2A output

• CCP1/P1C output

• CCP1/P1B output

These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.

DS41414D-page 128

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PIC16(L)F1946/47

12.2

Register Definitions: Alternate Pin Function Control

REGISTER 12-1:

R/W-0/0

P3CSEL bit 7

APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

R/W-0/0

P3BSEL

R/W-0/0

P2DSEL

R/W-0/0

P2CSEL

R/W-0/0

P2BSEL

R/W-0/0

CCP2SEL

R/W-0/0

P1CSEL

R/W-0/0

P1BSEL bit 0

Legend:

R = Readable bit u = bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

P3CSEL:

CCP3 PWM C Output Pin Selection bit

0

= P3C function is on RE3/P3C/COM0

1

= P3C function is on RD3/P3C/SEG3

P3BSEL:

CCP3 PWM B Output Pin Selection bit

0

= P3B function is on RE4/P3B/COM1

1

= P3B function is on RD4/P3B/SEG4

P2DSEL:

CCP2 PWM D Output Pin Selection bit

0

= P2D function is on RE0/P2D/VLCD1

1

= P2D function is on RD0/P2D/SEG0

P2CSEL:

CCP2 PWM C Output Pin Selection bit

0

= P2C function is on RE1/P2C/VLCD2

1

= P2C function is on RD1/P2C/SEG1

P2BSEL:

CCP2 PWM B Output Pin Selection bit

0

= P2B function is on RE2/P2B/VLCD3

1

= P2B function is on RD2/P2B/SEG2

CCP2SEL:

CCP2 Input/Output Pin Selection bit

0

= CCP2/P2A function is on RC1/CCP2/P2A/T1OSI/SEG32

1

= CCP2/P2A function is on RE7/CCP2/P2A/SEG31

P1CSEL:

CCP1 PWM C Output Pin Selection bit

0

= P1C function is on RE5/P1C/COM2

1

= P1C function is on RD5/P1C/SEG5

P1BSEL:

CCP1 PWM B Output Pin Selection bit

0

= P1B function is on RE6/P1B/COM3

1

= P1B function is on RD6/P1B/SEG6

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PIC16(L)F1946/47

12.3

PORTA Registers

PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA

(

Register 12-3 ). Setting a TRISA bit (=

1

) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (=

0

) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).

Example 12-1

shows how to initialize PORTA.

Reading the PORTA register (

Register 12-2

) reads the status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA).

The TRISA register (

Register 12-3 ) controls the

PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘

0

’.

12.3.1

ANSELA REGISTER

The ANSELA register (

Register 12-5

) is used to configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘

0

’ and allow analog functions on the pin to operate correctly.

The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

Note:

The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘

0

’ by user software.

12.3.2

PORTA FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 12-2 .

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input functions, such as ADC, comparator and

CapSense inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority list.

TABLE 12-2: PORTA OUTPUT PRIORITY

Pin

Name

Function Priority

(1)

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

Note 1:

SEG33 (LCD)

RA0

SEG18

RA1

SEG34 (LCD)

RA2

SEG35 (LCD)

RA3

SEG14 (LCD)

RA4

SEG15 (LCD)

RA5

OSC2 (enabled by Configuration Word)

CLKOUT (enabled by Configuration Word)

SEG36 (LCD)

RA6

OSC1/CLKIN (enabled by Configuration

Word)

SEG37 (LCD)

RA7

Priority listed from highest to lowest.

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12.4

Register Definitions: PORTA

REGISTER 12-2:

R/W-x/u

RA7 bit 7

PORTA: PORTA REGISTER

R/W-x/u

RA6

R/W-x/u

RA5

R/W-x/u

RA4

R/W-x/u

RA3

R/W-x/u

RA2

R/W-x/u

RA1

R/W-x/u

RA0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

RA<7:0>

: PORTA I/O Value bits

(1)

1

= Port pin is > V

IH

0

= Port pin is < V

IL

Note 1:

Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values.

REGISTER 12-3:

R/W-1/1

TRISA7 bit 7

TRISA: PORTA TRI-STATE REGISTER

R/W-1/1

TRISA6

R/W-1/1

TRISA5

R/W-1/1

TRISA4

R/W-1/1

TRISA3

R/W-1/1

TRISA2

R/W-1/1

TRISA1

R/W-1/1

TRISA0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

R/W-x/u

LATA7 bit 7

TRISA<7:0>:

PORTA Tri-State Control bit

1

= PORTA pin configured as an input (tri-stated)

0

= PORTA pin configured as an output

REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER

R/W-x/u

LATA6

R/W-x/u

LATA5

R/W-x/u

LATA4

R/W-x/u

LATA3

R/W-x/u

LATA2

R/W-x/u

LATA1

R/W-x/u

LATA0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

LATA<7:0>

: PORTA Output Latch Value bits

(1)

Note 1:

Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values.

2010-2012 Microchip Technology Inc.

DS41414D-page 131

PIC16(L)F1946/47

REGISTER 12-5:

bit 7

U-0

ANSELA: PORTA ANALOG SELECT REGISTER

U-0

R/W-1/1

ANSA5

U-0

R/W-1/1

ANSA3

R/W-1/1

ANSA2

R/W-1/1

ANSA1

R/W-1/1

ANSA0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5 bit 4 bit 3-0

Note 1:

Unimplemented:

Read as ‘

0

ANSA5

: Analog Select between Analog or Digital Function on pins RA<5>, respectively

0

= Digital I/O. Pin is assigned to port or digital special function.

1

= Analog input. Pin is assigned as analog input

(1)

. Digital input buffer disabled.

Unimplemented:

Read as ‘

0

ANSA<3:0>

: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively

0

= Digital I/O. Pin is assigned to port or digital special function.

1

= Analog input. Pin is assigned as analog input

(1)

. Digital input buffer disabled.

When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

ADCON0

ADCON1

ANSELA

CPSCON0

CPSCON1

DACCON0

LATA

LCDSE1

LCDSE2

LCDSE4

OPTION_REG

PORTA

TRISA

Legend:

ADFM

CPSON

DACEN

LATA7

SE15

SE23

SE39

WPUEN

CPSRM

DACLPS

LATA6

SE14

SE22

SE38

INTEDG

ADCS<2:0>

ANSA5

DACOE

LATA5

SE13

SE21

SE37

TMR0CS

CHS<4:0>

---

LATA4

SE12

SE20

SE36

TMR0SE

ANSA3

ANSA2

GO/DONE

CPSRNG1 CPSRNG0

CPSCH<4:0>

CPSOUT

DACPSS<1:0>

LATA3 LATA2

SE11

SE19

SE35

PSA

SE10

SE18

SE34

---

LATA1

SE9

SE17

SE33

PS<2:0>

ADON

ADPREF<1:0>

ANSA1 ANSA0

T0XCS

DACNSS

LATA0

SE8

SE16

SE32

168

169

RA7

TRISA7

RA6

TRISA6

RA5

TRISA5

RA4

TRISA4

RA3

TRISA3

RA2

TRISA2

RA1

TRISA1

RA0

TRISA0 x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTA.

197

131

131

132

333

334

178

131

341

341

341

TABLE 12-4:

Name Bits

SUMMARY OF CONFIGURATION WORD WITH PORTA

Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1

CONFIG1

Legend:

13:8 — — FCMEN IESO CLKOUTEN

7:0 CP MCLRE PWRTE WDTE<1:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by PORTA.

BOREN<1:0>

FOSC<2:0>

Bit 8/0

CPD

Register on Page

56

2010-2012 Microchip Technology Inc.

DS41414D-page 132

12.5

PORTB Registers

PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB

(

Register 12-7

). Setting a TRISB bit (=

1

) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (=

0

) will make the corresponding

PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).

Example 12-1 shows how to initialize an I/O port.

Reading the PORTB register ( Register 12-6

) reads the status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB).

The TRISB register ( Register 12-7 ) controls the PORTB

pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘

0

’.

12.5.1

WEAK PULL-UPS

Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or

disable each pull-up (see Register 12-9 ). Each weak

pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a

Power-on Reset by the WPUEN bit of the OPTION_REG register.

12.5.2

INTERRUPT-ON-CHANGE

All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:0> enable or disable the interrupt function for each pin.

The interrupt-on-change feature is disabled on a

Power-on Reset. Reference

Section 13.0

“Interrupt-On-Change”

for more information.

PIC16(L)F1946/47

12.5.3

PORTB FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 12-5 .

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.

Certain digital input functions, such as the EUSART RX signal, override other port functions and are included in the priority list.

TABLE 12-5: PORTB OUTPUT PRIORITY

Pin

Name

RB0

Function Priority

(1)

RB1

RB2

RB3

RB4

RB5

RB6

RB7

Note 1:

SEG12 (LCD)

SRI (SR Latch)

RB0

SEG8 (LCD)

RB1

SEG9 (LCD)

RB2

SEG10 (LCD)

RB3

SEG11 (LCD)

RB4

SEG29 (LCD)

RB5

ICSPCLK (Programming)

ICDCLK (enabled by Configuration Word)

SEG38 (LCD)

RB6

ICSPDAT (Programming)

ICDDAT (enabled by Configuration Word)

SEG39 (LCD)

RB7

Priority listed from highest to lowest.

2010-2012 Microchip Technology Inc.

DS41414D-page 133

PIC16(L)F1946/47

12.6

Register Definitions: PORTB

REGISTER 12-6:

R/W-x/u

RB7 bit 7

PORTB: PORTB REGISTER

R/W-x/u

RB6

R/W-x/u

RB5

R/W-x/u

RB4

R/W-x/u

RB3

R/W-x/u

RB2

R/W-x/u

RB1

R/W-x/u

RB0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

RB<7:0>

: PORTB I/O Pin bit

1

= Port pin is > V

IH

0

= Port pin is < V

IL

REGISTER 12-7:

R/W-1/1

TRISB7 bit 7

TRISB: PORTB TRI-STATE REGISTER

R/W-1/1

TRISB6

R/W-1/1

TRISB5

R/W-1/1

TRISB4

R/W-1/1

TRISB3

R/W-1/1

TRISB2

R/W-1/1

TRISB1

R/W-1/1

TRISB0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

TRISB<7:0>:

PORTB Tri-State Control bits

1

= PORTB pin configured as an input (tri-stated)

0

= PORTB pin configured as an output

REGISTER 12-8:

R/W-x/u

LATB7 bit 7

LATB: PORTB DATA LATCH REGISTER

R/W-x/u

LATB6

R/W-x/u

LATB5

R/W-x/u

LATB4

R/W-x/u

LATB3

R/W-x/u

LATB2

R/W-x/u

LATB1

R/W-x/u

LATB0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

LATB<7:0>

: PORTB Output Latch Value bits

(1)

Note 1:

Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values.

2010-2012 Microchip Technology Inc.

DS41414D-page 134

PIC16(L)F1946/47

REGISTER 12-9:

R/W-1/1

WPUB7 bit 7

WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1/1

WPUB6

R/W-1/1

WPUB5

R/W-1/1

WPUB4

R/W-1/1

WPUB3

R/W-1/1

WPUB2

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

R/W-1/1

WPUB1

R/W-1/1

WPUB0 bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

Note 1:

2:

WPUB<7:0>

: Weak Pull-up Register bits

1

= Pull-up enabled

0

= Pull-up disabled

Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

The weak pull-up device is automatically disabled if the pin is in configured as an output.

TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

INTCON

IOCBP

IOCBN

IOCBF

LATB

LCDSE1

LCDSE3

LCDSE4

GIE

IOCBP7

IOCBN7

IOCBF7

LATB7

SE15

SE31

SE39

PEIE

IOCBP6

IOCBN6

IOCBF6

LATB6

SE14

SE30

SE38

TMR0IE

IOCBP5

IOCBN5

IOCBF5

LATB5

SE13

SE29

SE37

INTE

IOCBP4

IOCBN4

IOCBF4

LATB4

SE12

SE28

SE36

IOCIE

IOCBP3

IOCBN3

IOCBF3

LATB3

SE11

SE27

SE35

TMR0IF

IOCBP2

IOCBN2

IOCBF2

LATB2

SE10

SE26

SE34

INTF

IOCBP1

IOCBN1

IOCBF1

LATB1

SE9

SE25

SE33

IOCIF

IOCBP0

IOCBN0

IOCBF0

LATB0

SE8

SE24

SE32

OPTION_REG

PORTB

T1GCON

TRISB

WPUB

Legend:

WPUEN

RB7

TMR1GE

TRISB7

INTEDG

RB6

T1GPOL

TRISB6

TMR0CS

RB5

T1GTM

TRISB5

TMR0SE

RB4

T1GSPM

TRISB4

PSA

RB3

T1GGO/DONE

TRISB3

RB2

T1GVAL

TRISB2

PS<2:0>

RB1

TRISB1

RB0

T1GSS<1:0>

TRISB0

197

134

208

134

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 x

= unknown, u

= unchanged,

-

= unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTB.

135

92

155

155

155

134

341

341

341

2010-2012 Microchip Technology Inc.

DS41414D-page 135

PIC16(L)F1946/47

12.7

PORTC Registers

PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC

(

Register 12-11

). Setting a TRISC bit (=

1

) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode).

Clearing a TRISC bit (=

0

) will make the corresponding

PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).

Example 12-1 shows how to initialize an I/O port.

Reading the PORTC register ( Register 12-10 ) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC).

The TRISC register ( Register 12-11 ) controls the

PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘

0

’.

12.7.1

PORTC FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 12-7 .

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.

Certain digital input functions override other port functions and are included in the priority list.

TABLE 12-7:

Pin Name

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

Note 1:

2:

PORTC OUTPUT PRIORITY

Function Priority

(1)

T1OSO (Timer1 Oscillator)

SEG40 (ICD)

RC0

T1OSI (Timer1 Oscillator)

CCP2

(2)

/P2A

(2)

SEG32 (ICD)

RC1

SEG13 (LCD)

CCP1/P1A

RC2

SEG17 (LCD)

SCL1 (MSSP1)

SCK1 (MSSP1)

RC3

SEG16 (LCD)

SDA1 (MSSP1)

RC4

SEG12 (LCD)

SDO1 (MSSP1)

RC5

SEG27 (LCD)

TX1 (EUSART1)

CK2 (EUSART1)

RC6

SEG28 (LCD)

DT1 (EUSART1)

RC7

Priority listed from highest to lowest.

Default pin (see APFCON register).

2010-2012 Microchip Technology Inc.

DS41414D-page 136

PIC16(L)F1946/47

12.8

Register Definitions: PORTC

REGISTER 12-10: PORTC: PORTC REGISTER

R/W-x/u

RC7 bit 7

R/W-x/u

RC6

R/W-x/u

RC5

R/W-x/u

RC4

R/W-x/u

RC3

R/W-x/u

RC2

R/W-x/u

RC1

R/W-x/u

RC0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

RC<7:0>

: PORTC General Purpose I/O Pin bits

1

= Port pin is > V

IH

0

= Port pin is < V

IL

REGISTER 12-11: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1

TRISC7 bit 7

R/W-1/1

TRISC6

R/W-1/1

TRISC5

R/W-1/1

TRISC4

R/W-1/1

TRISC3

R/W-1/1

TRISC2

R/W-1/1

TRISC1

R/W-1/1

TRISC0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

TRISC<7:0>:

PORTC Tri-State Control bits

1

= PORTC pin configured as an input (tri-stated)

0

= PORTC pin configured as an output

REGISTER 12-12: LATC: PORTC DATA LATCH REGISTER

R/W-x/u

LATC7 bit 7

R/W-x/u

LATC6

R/W-x/u

LATC5

R/W-x/u

LATC4

R/W-x/u

LATC3

R/W-x/u

LATC2

R/W-x/u

LATC1

R/W-x/u

LATC0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

LATC<7:0>

: PORTC Output Latch Value bits

(1)

Note 1:

Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values.

2010-2012 Microchip Technology Inc.

DS41414D-page 137

PIC16(L)F1946/47

APFCON

LATC

LCDSE1

LCDSE2

LCDSE3

LCDSE4

LCDSE5

PORTC

RC1STA

RC2STA

SSP1CON1

SSP2STAT

T1CON

TX1STA

TX2STA

TRISC

Legend:

TABLE 12-8:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL

LATC7

SE15

SE23

SE31

SE39

LATC6

SE14

SE22

SE30

SE38

LATC5

SE13

SE21

SE29

SE37

SE45

LATC4

SE12

SE20

SE28

SE36

SE44

LATC3

SE11

SE19

SE27

SE35

SE43

LATC2

SE10

SE18

SE26

SE34

SE42

LATC1

SE9

SE17

SE25

SE33

SE41

LATC0

SE8

SE16

SE24

SE32

SE40

RC7

SPEN

SPEN

WCOL

SMP

RC6

RX9

RX9

SSPOV

CKE

TMR1CS<1:0>

CSRC TX9

CSRC TX9

RC5

SREN

SREN

SSPEN

D/A

T1CKPS<1:0>

TXEN

TXEN

RC4

CREN

CREN

CKP

P

SYNC

SYNC

RC3

ADDEN

ADDEN

S

T1OSCEN

SENDB

SENDB

RC2

FERR

FERR

SSPM<3:0>

R/W

T1SYNC

BRGH

BRGH

RC1

OERR

OERR

UA

TRMT

TRMT

RC0

RX9D

RX9D

BF

TMR1ON

TX9D

TX9D

137

308

308

292

291

207

307

307

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 x = unknown, u = unchanged, - = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTC.

137

129

137

341

341

341

341

341

DS41414D-page 138

2010-2012 Microchip Technology Inc.

12.9

PORTD Registers

PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB

(

Register 12-13

). Setting a TRISD bit (=

1

) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode).

Clearing a TRISD bit (=

0

) will make the corresponding

PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).

Example 12-1 shows how to initialize an I/O port.

Reading the PORTD register (

Register 12-13 ) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATD).

The TRISD register ( Register 12-14

) controls the PORTD pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the

TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘

0

’.

PIC16(L)F1946/47

12.9.1

PORTD FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTD pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 12-5 .

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.

Certain digital input functions override other port functions and are included in the priority list.

TABLE 12-9:

Pin Name

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

Note 1:

2:

PORTD OUTPUT PRIORITY

Function Priority

(1)

SEG0 (LCD)

P2D

(2)

(CCP)

RD0

SEG1 (LCD)

P2C

(2)

(CCP)

RD1

P2B

(2)

(CCP)

SEG2 (LCD)

RD2

SEG3 (LCD)

P3C

(2)

(CCP)

RD3

SEG4 (LCD)

P3D

(2)

(CCP)

SDO2 (SSP2)

RD4

SEG5 (LCD)

P1C

(2)

(CCP)

SDA2 (SSP2)

RD5

SEG5 (LCD)

P1B

(2)

(CCP)

SCK2/SCL2 (SSP2)

RD6

SEG7 (LCD)

RD7

Priority listed from highest to lowest.

Alternate pin (see APFCON register).

2010-2012 Microchip Technology Inc.

DS41414D-page 139

PIC16(L)F1946/47

12.10 Register Definitions: PORTD

REGISTER 12-13: PORTD: PORTD REGISTER

R/W-x/u

RD7 bit 7

R/W-x/u

RD6

R/W-x/u

RD5

R/W-x/u

RD4

R/W-x/u

RD3

R/W-x/u

RD2

R/W-x/u

RD1

R/W-x/u

RD0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

RD<7:0>

: PORTD General Purpose I/O Pin bits

1

= Port pin is > V

IH

0

= Port pin is < V

IL

REGISTER 12-14: TRISD: PORTD TRI-STATE REGISTER

R/W-1/1

TRISD7 bit 7

R/W-1/1

TRISD6

R/W-1/1

TRISD5

R/W-1/1

TRISD4

R/W-1/1

TRISD3

R/W-1/1

TRISD2

R/W-1/1

TRISD1

R/W-1/1

TRISD0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

TRISD<7:0>:

PORTD Tri-State Control bits

1

= PORTD pin configured as an input (tri-stated)

0

= PORTD pin configured as an output

REGISTER 12-15: LATD: PORTD DATA LATCH REGISTER

R/W-x/u

LATD7 bit 7

R/W-x/u

LATD6

R/W-x/u

LATD5

R/W-x/u

LATD4

R/W-x/u

LATD3

R/W-x/u

LATD2

R/W-x/u

LATD1

R/W-x/u

LATD0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

LATD<7:0>

: PORTD Output Latch Value bits

(1)

Note 1:

Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on

Page

APFCON

CCPxCON

LATD

LCDCON

LCDSE0

PORTD

TRISD

Legend:

Note 1:

P3CSEL P3BSEL

PxM<1:0>

(1)

P2DSEL P2CSEL

DCxB<1:0>

P2BSEL CCP2SEL P1CSEL

CCPxM<3:0>

P1BSEL

129

238

LATD7

LCDEN

SE7

RD7

LATD6

SLPEN

SE6

RD6

LATD5

WERR

SE5

RD5

LATD4

SE4

RD4

LATD3

SE3

RD3

LATD2

CS<1:0>

SE2

RD2

LATD1

LMUX<1:0>

SE1

RD1

LATD0

SE0

RD0

140

337

341

140

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTD.

Applies to ECCP modules only.

140

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PIC16(L)F1946/47

12.11 PORTE Registers

PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a

TRISE bit (=

1

) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a

High-Impedance mode). Clearing a TRISE bit (=

0

) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).

Example 12-1

shows how to initialize an I/O port.

Reading the PORTE register ( Register 12-16 ) reads

the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch

(LATE).

12.11.1

ANSELE REGISTER

The ANSELE register (

Register 12-19

) is used to configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELE bit high will cause all digital reads on the pin to be read as ‘

0

’ and allow analog functions on the pin to operate correctly.

The state of the ANSELE bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

The TRISE register ( Register 12-17 ) controls the PORTE

pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the

TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘

0

’.

Note:

The ANSELE register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘

0

’.

12.11.2

PORTE FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 12-11

.

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet.

When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists.

Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.

Certain digital input functions, such as the EUSART RX signal, override other port functions and are included in the priority list.

TABLE 12-11: PORTE OUTPUT PRIORITY

Pin Name

RE0

RE1

RE2

RE3

RE4

RE5

RE6

RE7

Note 1:

2:

3:

Function Priority

(1)

P2D

(2)

(CCP)

RE0

P2C

(2)

(CCP)

RE1

P2B

(2)

(CCP)

RE2

P3C

(2)

(CCP)

COM0 (LCD)

RE3

P3B

(2)

(CCP)

COM1 (LCD)

RE4

P1C

(2)

(CCP)

COM32(LCD)

RE5

P1B

(2)

(CCP)

COM3 (LCD)

RE6

CCP2

(3)

/P2A

(3)

(CCP)

SEG31 (LCD)

RE7

Priority listed from highest to lowest.

Default pin (see APFCON register).

Alternate pin (see APFCON register).

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PIC16(L)F1946/47

12.12 Register Definitions: PORTE

REGISTER 12-16: PORTE: PORTE REGISTER

R/W-x/u

RE7 bit 7

R/W-x/u

RE6

R/W-x/u

RE5

R/W-x/u

RE4

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

RE<7:0>

: PORTE I/O Pin bits

1

= Port pin is > V

IH

0

= Port pin is < V

IL

R/W-x/u

RE3

R/W-x/u

RE2

R/W-x/u

RE1

R/W-x/u

RE0 bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

REGISTER 12-17: TRISE: PORTE TRI-STATE REGISTER

R/W-1

TRISE7 bit 7

R/W-1

TRISE6

R/W-1

TRISE5

R/W-1

TRISE4

R/W-1

TRISE3

R/W-1

TRISE2

R/W-1

TRISE1

R/W-1

TRISE0 bit 0

Legend:

R = Readable bit u = bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

TRISE<7:0>:

RE<7:0> Tri-State Control bits

1

= PORTE pin configured as an input (tri-stated)

0

= PORTE pin configured as an output

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PIC16(L)F1946/47

REGISTER 12-18: LATE: PORTE DATA LATCH REGISTER

bit 7

R/W-x/u

LATE7

R/W-x/u

LATE6

R/W-x/u

LATE5

R/W-x/u

LATE4

R/W-x/u

LATE3

R/W-x/u

LATE2

R/W-x/u

LATE1

R/W-x/u

LATE0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

LATE<7:0>

: PORTE Output Latch Value bits

(1)

Note 1:

Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values.

REGISTER 12-19: ANSELE: PORTE ANALOG SELECT REGISTER

bit 7

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

ANSE2

R/W-1

ANSE1

R/W-1

ANSE0 bit 0

Legend:

R = Readable bit u = bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

Note 1:

ANSE<7:0>

: Analog Select between Analog or Digital Function on Pins RE<7:0>, respectively

0

= Digital I/O. Pin is assigned to port or digital special function.

1

= Analog input. Pin is assigned as analog input

(1)

. Digital input buffer disabled.

When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

TABLE 12-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

APFCON

ANSELE

CCPxCON

LATE

LCDCON

LCDREF

LCDSE2

PORTE

TRISE

Legend:

Note 1:

P3CSEL

— —

PxM<1:0>

(1)

LATE7

LCDEN

LCDIRE

SE31

RE7

P3BSEL

LATE6

SLPEN

LCDIRS

SE30

RE6

P2DSEL

P2CSEL

DCxB<1:0>

LATE5

WERR

LCDIRI

SE29

RE5

LATE4

SE28

RE4

P2BSEL

LATE3 LATE2

CS<1:0>

VLCD3PE

SE27

CCP2SEL

ANSE2

VLCD2PE

SE26

P1CSEL

ANSE1

CCPxM<3:0>

LATE1

VLCD1PE

SE25

RE1

P1BSEL

ANSE0

LATE0

LMUX<1:0>

SE24

RE0

129

144

238

144

337

339

341

RE3 RE2

143

TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTE.

Applies to ECCP modules only.

143

2010-2012 Microchip Technology Inc.

DS41414D-page 144

12.13 PORTF Registers

PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF

(

Register 12-21

). Setting a TRISF bit (=

1

) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a High-Impedance mode).

Clearing a TRISF bit (=

0

) will make the corresponding

PORTF pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).

Example 12-1 shows how to initialize an I/O port.

Reading the PORTF register ( Register 12-13

) reads the status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATF).

The TRISF register (

Register 12-14 ) controls the

PORTF pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISF register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘

0

’.

12.13.1

ANSELF REGISTER

The ANSELF register (

Register 12-23 ) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELF bit high will cause all digital reads on the pin to be read as ‘

0

’ and allow analog functions on the pin to operate correctly.

The state of the ANSELF bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

Note:

The ANSELF register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘

0

’.

PIC16(L)F1946/47

12.13.2

PORTF FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTF pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 12-13

.

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.

Certain digital input functions override other port functions and are included in the priority list.

TABLE 12-13: PORTF OUTPUT PRIORITY

Pin Name Function Priority

(1)

RF0

RF1

RF2

RF3

RF4

RF5

RF6

RF7

Note 1:

SEG41 (LCD)

RF0

C2OUT (Comparator)

SRNQ (SR Latch)

SEG19 (LCD)

RF1

C1OUT (Comparator)

SEG20 (LCD)

SRQ (SR Latch)

RF2

SEG21 (LCD)

RF3

SEG22 (LCD)

RF4

DACOUT (DAC)

SEG23 (LCD)

RF5

SEG24 (LCD)

RF6

SEG25 (LCD)

RF7

Priority listed from highest to lowest.

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PIC16(L)F1946/47

12.14 Register Definitions: PORTF

REGISTER 12-20: PORTF: PORTF REGISTER

R/W-x/u

RF7 bit 7

R/W-x/u

RF6

R/W-x/u

RF5

R/W-x/u

RF4

R/W-x/u

RF3

R/W-x/u

RF2

R/W-x/u

RF1

R/W-x/u

RF0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

RF<7:0>

: PORTF General Purpose I/O Pin bits

1

= Port pin is > V

IH

0

= Port pin is < V

IL

REGISTER 12-21: TRISF: PORTF TRI-STATE REGISTER

R/W-1/1

TRISF7 bit 7

R/W-1/1

TRISF6

R/W-1/1

TRISF5

R/W-1/1

TRISF4

R/W-1/1

TRISF3

R/W-1/1

TRISF2

R/W-1/1

TRISF1

R/W-1/1

TRISF0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

TRISF<7:0>:

PORTF Tri-State Control bits

1

= PORTF pin configured as an input (tri-stated)

0

= PORTF pin configured as an output

REGISTER 12-22: LATF: PORTF DATA LATCH REGISTER

R/W-x/u

LATF7 bit 7

R/W-x/u

LATF6

R/W-x/u

LATF5

R/W-x/u

LATF4

R/W-x/u

LATF3

R/W-x/u

LATF2

R/W-x/u

LATF1

R/W-x/u

LATF0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

LATF<7:0>

: PORTF Output Latch Value bits

(1)

Note 1:

Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return of actual I/O pin values.

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PIC16(L)F1946/47

REGISTER 12-23: ANSELF: PORTF ANALOG SELECT REGISTER

R/W-1/1

ANSF7 bit 7

R/W-1/1

ANSF6

R/W-1/1

ANSF5

R/W-1/1

ANSDF4

R/W-1/1

ANSF3

R/W-1/1

ANSF2

R/W-1/1

ANSDF1

R/W-1/1

ANSF0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

ANSF<7:0>

: Analog Select between Analog or Digital Function on Pins RF<7:0>, respectively

0

= Digital I/O. Pin is assigned to port or digital special function.

1

= Analog input. Pin is assigned as analog input

(1)

. Digital input buffer disabled.

Note 1:

When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

TABLE 12-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on

Page

ADCON0

ANSELF

CCPxCON

CMOUT

CM1CON1

CM2CON1

CPSCON0

CPSCON1

DACCON0

LATF

LCDCON

LCDSE2

LCDSE3

LCDSE5

PORTF

SRCON0

TRISF

Legend:

Note 1:

ANSF7 ANSF6

PxM<1:0>

(1)

— —

C1INTP

C2INTP

CPSON

C1INTN

C2INTN

CPSRM

ANSF5

C1PCH1

C2PCH1

CHS<4:0>

ANSF4

DCxB<1:0>

— —

C1PCH0

C2PCH0

ANSF3

ANSF2

CCPxM<3:0>

MC3OUT

GO/DONE

ANSF1

MC2OUT

ADON

ANSF0

MC1OUT

C1NCH<1:0>

C2NCH<1:0>

168

147

DACEN

LATF7

LCDEN

DACLPS

LATF6

SLPEN

DACOE

LATF5

WERR

LATF4

CPSRNG<1:0> CPSOUT T0XCS

LATF3 LATF2

CS<1:0>

CPSCH<3:0>

DACPSS<1:0> — DACNSS

LATF1 LATF0

LMUX<1:0>

SE23

SE31

SE22

SE30

RF6

SRCLK2

SE21

SE29

SE45

SE20

SE28

SE44

SE19

SE27

SE43

SE18

SE26

SE42

SE17

SE25

SE41

SE16

SE24

SE40

RF7

SRLEN

RF5

SRCLK1

RF4

SRCLK0

RF3

SRQEN

RF2

SRNQEN

RF1

SRPS

RF0

SRPR

146

192

TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTF.

Applies to ECCP modules only.

146

337

341

341

341

238

186

186

186

333

334

178

140

TABLE 12-15: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH PORTF

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG2

Legend:

13:8 — — LVP DEBUG — BORV

7:0 — — — VCAPEN — —

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by clock sources.

STVREN PLLEN

WRT<1:0>

Register on Page

58

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PIC16(L)F1946/47

12.15 PORTG Registers

PORTG is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISG

(

Register 12-25

). Setting a TRISG bit (=

1

) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a High-Impedance mode).

Clearing a TRISG bit (=

0

) will make the corresponding

PORTG pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).

The exception is RG5, which is input only and its TRIS bit will always read as ‘

1

’.

Example 12-1 shows how to

initialize an I/O port.

Reading the PORTG register ( Register 12-24

) reads the status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATG). RG5 reads ‘

0

’ when

MCLRE =

1.

The TRISG register ( Register 12-25 ) controls the

PORTG pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISG register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘

0

’.

12.15.1

ANSELG REGISTER

The ANSELG register (

Register 12-27 ) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELG bit high will cause all digital reads on the pin to be read as ‘

0

’ and allow analog functions on the pin to operate correctly.

The state of the ANSELG bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

Note:

The ANSELG register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘

0

’.

12.15.2

PORTG FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTG pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 12-16

.

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.

Certain digital input functions override other port functions and are included in the priority list.

TABLE 12-16: PORTG OUTPUT PRIORITY

Pin Name Function Priority

(1)

RG0

RG1

RG2

RG3

RG4

RG5

Note 1:

CCP3 (CCP)

P3A (CCP)

SEG42 (LCD)

RG0

TX2 (EUSART)

CK2 (EUSART)

C3OUT (Comparator)

SEG43 (LCD)

RG1

DT2

SEG44 (LCD)

RG2

CCP4 (CCP)

P3D (CCP)

SEG45 (LCD)

RG3

CCP5 (CCP)

P1D (CCP)

SEG26 (LCD)

RG4

Input-only pin

Priority listed from highest to lowest.

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PIC16(L)F1946/47

12.16 Register Definitions: PORTG

REGISTER 12-24: PORTG: PORTG REGISTER

U-0

U-0

R/W-x/u

RG5

R/W-x/u

RG4 bit 7

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

R/W-x/u

RG3

R/W-x/u

RG2

R/W-x/u

RG1

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

R/W-x/u

RG0 bit 0 bit 7-6 bit 5-0

Unimplemented: Read as ‘

0

’.

RG<5:0>

: PORTG General Purpose I/O Pin bits

1

= Port pin is > V

IH

0

= Port pin is < V

IL

REGISTER 12-25: TRISG: PORTG TRI-STATE REGISTER

U-0

U-0

R-1/1

TRISG5

R/W-1/1

TRISG4

R/W-1/1

TRISG3 bit 7

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

R/W-1/1

TRISG2

R/W-1/1

TRISG1

R/W-1/1

TRISG0 bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5 bit 4-0

Unimplemented: Read as ‘

0

’.

TRISG5:

PORTG Tri-State Control bit

This bit (RG5 pin) is an input only and always read as ‘

1

’.

TRISG<4:0>:

PORTG Tri-State Control bits

1

= PORTG pin configured as an input (tri-stated)

0

= PORTG pin configured as an output

REGISTER 12-26: LATG: PORTG DATA LATCH REGISTER

U-0

U-0

R/W-x/u

LATG5

R/W-x/u

LATG4

R/W-x/u

LATG3 bit 7

R/W-x/u

LATG2

R/W-x/u

LATG1

R/W-x/u

LATG0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5-0

Note 1:

Unimplemented: Read as ‘

0

’.

LATG<5:0>

: PORTG Output Latch Value bits

Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is return of actual

I/O pin values.

2010-2012 Microchip Technology Inc.

DS41414D-page 149

PIC16(L)F1946/47

REGISTER 12-27: ANSELG: PORTG ANALOG SELECT REGISTER

bit 7

U-0

U-0

U-0

R/W-1/1

ANSG4

R/W-1/1

ANSG3

R/W-1/1

ANSG2

R/W-1/1

ANSG1

U-0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-5 bit 4-1 bit 0

Note 1:

Unimplemented: Read as ‘

0

’.

ANSG<4:1>

: Analog Select between Analog or Digital Function on Pins RG<4:0>, respectively

0

= Digital I/O. Pin is assigned to port or digital special function.

1

= Analog input. Pin is assigned as analog input

(1)

. Digital input buffer disabled.

Unimplemented: Read as ‘

0

’.

When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

REGISTER 12-28: WPUG: WEAK PULL-UP PORTG REGISTER

bit 7

U-0

U-0

R/W-1/1

WPUG5

U-0

U-0

U-0

U-0

U-0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5 bit 4-0

Note 1:

2:

Unimplemented: Read as ‘

0

’.

WPUG5

: Weak Pull-up Register bits

1

= Pull-up enabled

0

= Pull-up disabled

Unimplemented: Read as ‘

0

’.

Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

The weak pull-up device is automatically disabled if the pin is in configured as an output.

2010-2012 Microchip Technology Inc.

DS41414D-page 150

PIC16(L)F1946/47

TABLE 12-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on

Page

ADCON0

ANSELG

CCPxCON

CMOUT

CM1CON1

CM2CON1

CPSCON0

— —

PxM<1:0>

(1

)

— —

C1INTP

C2INTP

CPSON

C1INTN

C2INTN

CPSRM

DCxB<1:0>

— —

C1PCH1

C2PCH1

C1PCH0

C2PCH0

CHS<4:0>

ANSG4

ANSG3

ANSG2

MC3OUT

CPSRNG<1:0>

GO/DONE

ANSG1

CCPxM<3:0>

MC2OUT

CPSOUT

ADON

MC1OUT

C1NCH<1:0>

C2NCH<1:0>

T0XCS

168

150

CPSCON1

LATG

LCDCON

LCDSE5

PORTG

TRISG

WPUG

Legend:

Note 1:

LCDEN

SLPEN

WERR

SE45

RG5

LATG4

SE44

RG4

LATG3

SE43

RG3

CPSCH<3:0>

LATG2

CS<1:0>

SE42

RG2

LATG1 LATG0

LMUX<1:0>

SE41

RG1

SE40

RG0

334

149

337

341

149

— —

TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0

149

— — WPUG5 — — — — — x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTG.

Applies to ECCP modules only.

150

238

186

186

186

333

2010-2012 Microchip Technology Inc.

DS41414D-page 151

PIC16(L)F1946/47

NOTES:

DS41414D-page 152

2010-2012 Microchip Technology Inc.

13.0

INTERRUPT-ON-CHANGE

The PORTB pins can be configured to operate as

Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features:

• Interrupt-on-change enable (Master Switch)

• Individual pin configuration

• Rising and falling edge detection

• Individual pin interrupt flags

Figure 13-1 is a block diagram of the IOC module.

13.1

Enabling the Module

To allow individual PORTB pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated.

13.2

Individual Pin Configuration

For each PORTB pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCBPx bit of the IOCBP register is set. To enable a pin to detect a falling edge, the associated IOCBNx bit of the IOCBN register is set.

A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively.

PIC16(L)F1946/47

13.3

Interrupt Flags

The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits.

13.4

Clearing Interrupt Flags

The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written.

In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed.

EXAMPLE 13-1:

MOVLW

XORWF

ANDWF

CLEARING INTERRUPT

FLAGS

(PORTA EXAMPLE)

0xff

IOCAF, W

IOCAF, F

13.5

Operation in Sleep

The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep.

2010-2012 Microchip Technology Inc.

DS41414D-page 153

PIC16(L)F1946/47

FIGURE 13-1:

IOCBNx

INTERRUPT-ON-CHANGE BLOCK DIAGRAM

Q4Q1

D

CK

R

Q edge detect

RBx

IOCBPx

D

CK

R

Q data bus =

0 or

1 write IOCBFx

D

S

CK

Q to data bus

IOCBFx

IOCIE

Q2 from all other

IOCBFx individual pin detectors

Q1

Q2

Q3

Q4

Q4Q1

Q4

Q4Q1

Q1

Q2

Q3

Q4

Q4Q1

Q1

Q2

Q3

Q4

Q4Q1

IOC interrupt to CPU core

DS41414D-page 154

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

13.6

Register Definitions: Interrupt-on-Change Control

REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER

R/W-0/0

IOCBP7 bit 7

R/W-0/0

IOCBP6

R/W-0/0

IOCBP5

R/W-0/0

IOCBP4

R/W-0/0

IOCBP3

R/W-0/0

IOCBP2

R/W-0/0

IOCBP1

R/W-0/0

IOCBP0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

IOCBP<7:0>:

Interrupt-on-Change PORTB Positive Edge Enable bits

1

= Interrupt-on-change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge.

0

= Interrupt-on-change disabled for the associated pin.

REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER

R/W-0/0

IOCBN7 bit 7

R/W-0/0

IOCBN6

R/W-0/0

IOCBN5

R/W-0/0

IOCBN4

R/W-0/0

IOCBN3

R/W-0/0

IOCBN2

R/W-0/0

IOCBN1

R/W-0/0

IOCBN0 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

IOCBN<7:0>:

Interrupt-on-Change PORTB Negative Edge Enable bits

1

= Interrupt-on-change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge.

0

= Interrupt-on-change disabled for the associated pin.

REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER

R/W/HS-0/0

IOCBF7 bit 7

R/W/HS-0/0

IOCBF6

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

IOCBF5 IOCBF4 IOCBF3

R/W/HS-0/0

IOCBF2

R/W/HS-0/0

IOCBF1

R/W/HS-0/0

IOCBF0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

IOCBF<7:0>:

Interrupt-on-Change PORTB Flag bits

1

= An enabled change was detected on the associated pin.

Set when IOCBPx =

1

and a rising edge was detected on RBx, or when IOCBNx = edge was detected on RBx.

0

= No change was detected, or the user cleared the detected change.

1

and a falling

2010-2012 Microchip Technology Inc.

DS41414D-page 155

PIC16(L)F1946/47

TABLE 13-1:

Name

INTCON

IOCBF

IOCBN

IOCBP

TRISB

Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GIE PEIE

IOCBF7 IOCBF6

IOCBN7

IOCBP7

IOCBN6

IOCBP6

TMR0IE

IOCBF5

IOCBN5

IOCBP5

INTE

IOCBF4

IOCBN4

IOCBP4

IOCIE

IOCBF3

IOCBN3

IOCBP3

TMR0IF

IOCBF2

IOCBN2

IOCBP2

INTF

IOCBF1

IOCBN1

IOCBP1

IOCIF

IOCBF0

IOCBN0

IOCBP0

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by interrupt-on-change.

Register on Page

92

155

155

155

134

DS41414D-page 156

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

14.0

FIXED VOLTAGE REFERENCE

(FVR)

The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of V

DD

, with 1.024V,

2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following:

• ADC input channel

• ADC positive reference

• Comparator positive input

• Comparator negative input

• Digital-to-Analog Converter (DAC)

• Capacitive Sensing (CPS) module

• LCD bias generator

The FVR can be enabled by setting the FVREN bit of the FVRCON register.

FIGURE 14-1:

14.1

Independent Gain Amplifiers

The output of the FVR supplied to the ADC,

Comparators, DAC and CPS module is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels.

The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference

Section 16.0 “Analog-to-Digital Converter

(ADC) Module”

for additional information.

The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the Comparators, DAC

and CPS module. Reference

Section 17.0 “Digital-to-

Analog Converter (DAC) Module”

,

Section 18.0

“Comparator Module”

and

Section 26.0 “Capacitive

Sensing (CPS) Module”

for additional information.

14.2

FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See

Section 30.0 “Electrical Specifications”

for the minimum delay requirement.

VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

2

X

1

X

2

X

4

FVR BUFFER1

(To ADC Module)

CDAFVR<1:0>

2

X

1

X

2

X

4

FVR BUFFER2

(To Comparators, DAC, CPS)

FVR VREF

(To LCD Bias Generator)

FVREN

+

_

1.024V Fixed

Reference

FVRRDY

Any peripheral requiring the

Fixed Reference

(See

Table 14-1

)

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

14.3

Register Definitions: FVR Control

REGISTER 14-1:

R/W-0/0

FVREN bit 7

FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R-q/q

FVRRDY

(1)

R/W-0/0

TSEN

R/W-0/0

TSRNG

R/W-0/0 R/W-0/0

CDAFVR<1:0>

R/W-0/0 R/W-0/0

ADFVR<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition bit 7 bit 6 bit 5 bit 4 bit 3-2 bit 1-0

Note 1:

2:

3:

FVREN:

Fixed Voltage Reference Enable bit

1

= Fixed Voltage Reference is enabled

0

= Fixed Voltage Reference is disabled

FVRRDY:

Fixed Voltage Reference Ready Flag bit

(1)

1

= Fixed Voltage Reference output is ready for use

0

= Fixed Voltage Reference output is not ready or not enabled

TSEN:

Temperature Indicator Enable bit

(3)

1

= Temperature Indicator is enabled

0

= Temperature Indicator is disabled

TSRNG:

Temperature Indicator Range Selection bit

(3)

1

= V

OUT

= V

DD

- 4V

T

(High Range)

0

= V

OUT

= V

DD

- 2V

T

(Low Range)

CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit

11

= Comparator and DAC and CPS Fixed Voltage Reference Peripheral output is 4x (4.096V)

(2)

10

= Comparator and DAC and CPS Fixed Voltage Reference Peripheral output is 2x (2.048V)

(2)

01

= Comparator and DAC and CPS Fixed Voltage Reference Peripheral output is 1x (1.024V)

00

= Comparator and DAC and CPS Fixed Voltage Reference Peripheral output is off

ADFVR<1:0>:

ADC Fixed Voltage Reference Selection bit

11

= ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)

(2)

10

= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)

(2)

01

= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)

00

= ADC Fixed Voltage Reference Peripheral output is off

FVRRDY is always ‘

1

’ on PIC16F1946/47 only.

Fixed Voltage Reference output cannot exceed V

DD

.

See

Section 15.0 “Temperature Indicator Module”

for additional information.

TABLE 14-1:

Name

FVRCON

Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

FVREN FVRRDY TSEN TSRNG

Shaded cells are not used with the Fixed Voltage Reference.

CDAFVR<1:0>

Bit 1 Bit 0

ADFVR<1:0>

Register on page

158

2010-2012 Microchip Technology Inc.

DS41414D-page 158

15.0

TEMPERATURE INDICATOR

MODULE

This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.

The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application

Note AN1333, “

Use and Calibration of the Internal

Temperature Indicator

” (DS01333) for more details regarding the calibration process.

15.1

Circuit Operation

Figure 15-1

shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions.

Equation 15-1

describes the output characteristics of the temperature indicator.

EQUATION 15-1: V

OUT

RANGES

High Range: V

OUT

= V

DD

- 4V

T

Low Range: V

OUT

= V

DD

- 2V

T

The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See

Section 14.0 “Fixed Voltage Reference (FVR)”

for

more information.

The circuit is enabled by setting the TSEN bit of the

FVRCON register. When disabled, the circuit draws no current.

The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher V

DD

is needed.

The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.

PIC16(L)F1946/47

FIGURE 15-1: TEMPERATURE CIRCUIT

DIAGRAM

V

DD

TSEN

TSRNG

V

OUT

To ADC

15.2

Minimum Operating V

DD

When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications.

When the temperature circuit is operated in high range, the device operating voltage, V

DD

, must be high enough to ensure that the temperature circuit is correctly biased.

Table 15-1

shows the recommended minimum V

DD

vs.

range setting.

TABLE 15-1: RECOMMENDED V

DD

VS.

RANGE

Min. V

DD

, TSRNG =

1

3.6V

Min. V

DD

, TSRNG =

0

1.8V

15.3

Temperature Output

The output of the circuit is measured using the internal

Analog-to-Digital Converter. A channel is reserved for

the temperature circuit output. Refer to

Section 16.0

“Analog-to-Digital Converter (ADC) Module”

for

detailed information.

Note:

Every time the ADC MUX is changed to the temperature indicator output selection

(CHS bit in the ADCCON0 register), wait

500

 sec for the sampling capacitor to fully charge before sampling the temperature indicator output.

2010-2012 Microchip Technology Inc.

DS41414D-page 159

PIC16(L)F1946/47

15.4

ADC Acquisition Time

To ensure accurate temperature measurements, the user must wait at least 200

 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200

 s between sequential conversions of the temperature indicator output.

TABLE 15-2:

Name

FVRCON

Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

FVREN FVRRDY TSEN TSRNG —

Shaded cells are unused by the temperature indicator module.

Bit 2

Bit 1 Bit 0

ADFVR<1:0>

Register on page

118

DS41414D-page 160

2010-2012 Microchip Technology Inc.

16.0

ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 16-1

shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep.

PIC16(L)F1946/47

2010-2012 Microchip Technology Inc.

DS41414D-page 161

PIC16(L)F1946/47

FIGURE 16-1: ADC BLOCK DIAGRAM

V

REF

-

ADNREF =

1

ADNREF =

0

V

DD

V

SS

V

REF

+

ADPREF =

00

ADPREF =

11

ADPREF =

10

AN0

AN1

V

REF

-/AN2

V

REF

+/AN2

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

AN16

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

GO/DONE

ADON

Ref+ Ref-

ADC

V

SS

10

ADFM

0

= Left Justify

1

= Right Justify

16

ADRESH ADRESL

Temp Indicator

DAC Output

FVR Buffer1

11101

11110

11111

CHS<4:0>

Note:

When ADON =

0

, all multiplexer inputs are disconnected.

2010-2012 Microchip Technology Inc.

DS41414D-page 162

16.1

ADC Configuration

When configuring and using the ADC the following functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Result formatting

16.1.1

PORT CONFIGURATION

The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to

Section 12.0 “I/O Ports”

for more information.

Note:

Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.

16.1.2

CHANNEL SELECTION

There are 20 selections available:

• AN<16:0> pins

• Temperature Indicator

• DAC Output

• FVR (Fixed Voltage Reference) Output

Refer to

Section 15.0 “Temperature Indicator Module”

,

Section 17.0 “Digital-to-Analog Converter

(DAC) Module”

and

Section 14.0 “Fixed Voltage

Reference (FVR)”

for more information on these channel selections.

The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit.

When changing channels, a delay is required before starting the next conversion. Refer to

Section 16.2

“ADC Operation”

for more information.

16.1.3

ADC VOLTAGE REFERENCE

The ADPREF bit of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be:

• V

REF

+ pin

• V

DD

The ADNREF bit of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be:

• V

REF

- pin

• V

SS

See

Section 14.0 “Fixed Voltage Reference (FVR)”

for more details on the fixed voltage reference.

PIC16(L)F1946/47

16.1.4

CONVERSION CLOCK

The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options:

• F

OSC

/2

• F

OSC

/4

• F

OSC

/8

• F

OSC

/16

• F

OSC

/32

• F

OSC

/64

• F

RC

(dedicated internal oscillator)

The time to complete one bit conversion is defined as

T

AD

. One full 10-bit conversion requires 11.5 T

AD

peri-

ods as shown in Figure 16-2 .

For correct conversion, the appropriate T

AD

specification must be met. Refer to the A/D conversion requirements in

Section 30.0 “Electrical Specifications”

for

more information. Table 16-1

gives examples of appropriate ADC clock selections.

Note:

Unless using the F

RC

, any changes in the system clock frequency will change the

ADC clock frequency, which may adversely affect the ADC result.

2010-2012 Microchip Technology Inc.

DS41414D-page 163

PIC16(L)F1946/47

TABLE 16-1: ADC CLOCK PERIOD (T

AD

) V

S

. DEVICE OPERATING FREQUENCIES

ADC Clock Period (T

AD

) Device Frequency (F

OSC

)

ADC

Clock Source

ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz

Fosc/2

Fosc/4

Fosc/8

Fosc/16

Fosc/32

Fosc/64

F

RC

Legend:

Note 1:

2:

3:

4:

000

100

001

101

010

110

62.5ns

125 ns

0.5

 s

(2)

(2)

(2)

800 ns

1.0

 s

2.0

 s

1.0-6.0

 s

(1,4)

100 ns

200 ns

400 ns

(2)

(2)

(2)

800 ns

1.6

 s

3.2

 s

1.0-6.0

 s

(1,4)

125 ns

(2)

250 ns

(2)

0.5

 s

(2)

1.0

 s

2.0

 s

4.0

 s

1.0-6.0

 s

(1,4)

250 ns

(2)

500 ns

(2)

1.0

 s

2.0

 s

4.0

 s

8.0

 s

(3)

1.0-6.0

 s

(1,4)

500 ns

(2)

1.0

 s

2.0

 s

4.0

 s

8.0

 s

(3)

16.0

 s

(3)

1.0-6.0

 s

(1,4)

2.0

 s

4.0

 s

8.0

 s

(3)

16.0

 s

(3)

32.0

 s

(3)

64.0

 s

(3)

1.0-6.0

 s

(1,4)

x11

Shaded cells are outside of recommended range.

The F

RC

source has a typical T

AD

time of 1.6

 s for V

DD

.

These values violate the minimum required T

AD

time.

For faster conversion times, the selection of another clock source is recommended.

The ADC clock period (T

AD

) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock F

OSC

. However, the F

RC

clock source must be used when conversions are to be performed with the device in Sleep mode.

FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION T

AD

CYCLES

T

CY

- T

AD

T

AD

1 T

AD

2 T

AD

3 T

AD

4 T

AD

5 T

AD

6 T

AD

7 T

AD

8 b9 b8 b7 b6 b5 b4 b3

T

AD

9 T

AD

10 T

AD

11 b2 b1 b0

Conversion starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

On the following cycle:

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

DS41414D-page 164

2010-2012 Microchip Technology Inc.

16.1.5

INTERRUPTS

The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be cleared in software.

Note 1:

2:

The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled.

The ADC operates during Sleep only when the F

RC

oscillator is selected.

This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the

SLEEP

instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the

INTCON register are enabled, execution will switch to the Interrupt Service Routine.

PIC16(L)F1946/47

16.1.6

RESULT FORMATTING

The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.

Figure 16-3

shows the two output formats.

FIGURE 16-3: 10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

(ADFM =

0

) MSB bit 7

(ADFM =

1

) bit 0

10-bit A/D Result bit 7

Unimplemented: Read as ‘

0

MSB bit 0

ADRESL bit 7

LSB bit 0

Unimplemented: Read as ‘

0

’ bit 7

LSB bit 0

10-bit A/D Result

2010-2012 Microchip Technology Inc.

DS41414D-page 165

PIC16(L)F1946/47

16.2

ADC Operation

16.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘

1

’. Setting the GO/

DONE bit of the ADCON0 register to a ‘

1

’ will start the

Analog-to-Digital conversion.

Note:

The GO/DONE bit should not be set in the same instruction that turns on the ADC.

Refer to

Section 16.3.2 “A/D Conversion Procedure”

.

16.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

• Update the ADRESH and ADRESL registers with new conversion result

16.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The

ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.

16.3

ADC Operation During Sleep

The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F

RC option. When the F

RC

clock source is selected, the

ADC waits one additional instruction before starting the conversion. This allows the

SLEEP

instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set.

When the ADC clock source is something other than

F

RC

, a

SLEEP

instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.

16.3.1

SPECIAL EVENT TRIGGER

The Special Event Trigger of the CCPx/ECCPX module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero.

TABLE 16-2: SPECIAL EVENT TRIGGER

Device

PIC16(L)F1946/47

CCPx/ECCPx

CCP5

Using the Special Event Trigger does not assure proper

ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met.

Refer to

Section 23.0 “Capture/Compare/PWM

Modules”

for more information.

DS41414D-page 166

2010-2012 Microchip Technology Inc.

4.

5.

6.

16.3.2

A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to perform an Analog-to-Digital conversion:

1.

2.

3.

7.

8.

Configure Port:

• Disable pin output driver (Refer to the TRIS register)

• Configure pin as analog (Refer to the ANSEL register)

Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt

(1)

Wait the required acquisition time

(2)

.

Start conversion by setting the GO/DONE bit.

Wait for ADC conversion to complete by one of the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts enabled)

Read ADC Result.

Clear the ADC interrupt flag (required if interrupt is enabled).

Note 1:

2:

The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution.

Refer to

Section 16.5 “A/D Acquisition

Requirements”

.

PIC16(L)F1946/47

EXAMPLE 16-1: A/D CONVERSION

;This code block configures the ADC

;for polling, Vdd and Vss references, Frc

;clock and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

BANKSEL

MOVLW

ADCON1 ;

B’11110000’ ;Right justify, Frc

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

CALL

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

BANKSEL

MOVF

MOVWF

ADCON1

TRISA

TRISA,0

ANSEL

ANSEL,0

ADCON0

;clock

;Vdd and Vss Vref

;

;Set RA0 to input

;

;Set RA0 to analog

;

B’00000001’ ;Select channel AN0

ADCON0

SampleTime

;Turn ADC On

;Acquisiton delay

ADCON0,ADGO ;Start conversion

ADCON0,ADGO ;Is conversion done?

$-1

ADRESH

;No, test again

;

ADRESH,W

RESULTHI

ADRESL

ADRESL,W

RESULTLO

;Read upper 2 bits

;store in GPR space

;

;Read lower 8 bits

;Store in GPR space

2010-2012 Microchip Technology Inc.

DS41414D-page 167

PIC16(L)F1946/47

16.4

Register Definitions: ADC Control

REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0

bit 7

U-0

R/W-0/0 R/W-0/0 R/W-0/0

CHS<4:0>

R/W-0/0 R/W-0/0 R/W-0/0

GO/DONE

R/W-0/0

ADON bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-2 bit 1 bit 0

Unimplemented:

Read as ‘

0

CHS<4:0>:

Analog Channel Select bits

11111

= FVR (Fixed Voltage Reference) Buffer 1 Output

(2)

11110

= DAC output

(1)

11101

= Temperature Indicator

(3)

11100

= Reserved. No channel connected.

10001

= Reserved. No channel connected.

10000

= AN16

01111

= AN15

01110

= AN14

01101

= AN13

01100

= AN12

01011

= AN11

01010

= AN10

01001

= AN9

01000

= AN8

00111

= AN7

00110

= AN6

00101

= AN5

00100

= AN4

00011

= AN3

00010

= AN2

00001

= AN1

00000

=AN0

GO/DONE:

A/D Conversion Status bit

1

= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0

= A/D conversion completed/not in progress

ADON:

ADC Enable bit

1

= ADC is enabled

0

= ADC is disabled and consumes no operating current

Note 1:

2:

3:

See

Section 17.0 “Digital-to-Analog Converter (DAC) Module”

for more information.

See

Section 14.0 “Fixed Voltage Reference (FVR)”

for more information.

See

Section 15.0 “Temperature Indicator Module”

for more information.

2010-2012 Microchip Technology Inc.

DS41414D-page 168

PIC16(L)F1946/47

REGISTER 16-2:

R/W-0/0

ADFM bit 7

ADCON1: A/D CONTROL REGISTER 1

R/W-0/0 R/W-0/0

ADCS<2:0>

R/W-0/0 U-0

R/W-0/0

ADNREF

R/W-0/0 R/W-0/0

ADPREF<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-4 bit 3 bit 2 bit 1-0

Note 1:

ADFM:

A/D Result Format Select bit

1

= Right justified. Six Most Significant bits of ADRESH are set to ‘

0

’ when the conversion result is loaded.

0

= Left justified. Six Least Significant bits of ADRESL are set to ‘

0

’ when the conversion result is loaded.

ADCS<2:0>:

A/D Conversion Clock Select bits

111

= F

RC

(clock supplied from a dedicated RC oscillator)

110

= F

OSC

/64

101

= F

OSC

/16

100

= F

OSC

/4

011

= F

RC

(clock supplied from a dedicated RC oscillator)

010

= F

OSC

/32

001

= F

OSC

/8

000

= F

OSC

/2

Unimplemented:

Read as ‘

0

1

0

ADNREF:

A/D Negative Voltage Reference Configuration bit

= V

REF

- is connected to external V

REF

- pin

(1)

= V

REF

- is connected to V

SS

ADPREF<1:0>:

A/D Positive Voltage Reference Configuration bits

11

= V

REF

+ is connected to internal Fixed Voltage Reference (FVR) module

(1)

10

= V

REF

+ is connected to external V

REF

+ pin

(1)

01

= Reserved

00

= V

REF

+ is connected to V

DD

When selecting the FVR or the V

REF

+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See

Section 30.0 “Electrical Specifications”

for details.

2010-2012 Microchip Technology Inc.

DS41414D-page 169

PIC16(L)F1946/47

REGISTER 16-3:

R/W-x/u

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM =

R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<9:2>

R/W-x/u

0

R/W-x/u bit 7

R/W-x/u bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

ADRES<9:2>

: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 16-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM =

0

R/W-x/u R/W-x/u

ADRES<1:0> bit 7

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

ADRES<1:0>

: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

Reserved

: Do not use.

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

DS41414D-page 170

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

REGISTER 16-5:

R/W-x/u

— bit 7

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM =

1

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u R/W-x/u

ADRES<9:8> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-2 bit 1-0

Reserved

: Do not use.

ADRES<9:8>

: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

REGISTER 16-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM =

1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<7:0>

R/W-x/u R/W-x/u bit 7

R/W-x/u bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

ADRES<7:0>

: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

2010-2012 Microchip Technology Inc.

DS41414D-page 171

PIC16(L)F1946/47

16.5

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge holding capacitor (C

HOLD

) must be allowed to fully charge to the input channel voltage level. The Analog

Input model is shown in Figure 16-4

. The source impedance (R

S

) and the internal sampling switch (R

SS

) impedance directly affect the time required to charge the capacitor C

HOLD

. The sampling switch (R

SS

) impedance varies over the device voltage (V

DD

), refer to

Figure 16-4 .

The maximum recommended impedance for analog sources is 10 k

.

As the

EQUATION 16-1: ACQUISITION TIME EXAMPLE

source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time,

Equation 16-1

may be used. This equation assumes that 1/2 LSb error is used

(1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.

Assumptions:

Temperature = 50°C and external impedance of 10k

5.0V V

DD

T

ACQ

=

=

=

Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

T

AMP

2µs +

+

T

C

T

C

+

+ T

COFF

 

Temperature - 25°C

 

0.05µs/°C

 

The value for T

C

can be approximated with the following equations:

V

AP P L I ED

1

--------------------------

2 n +

1

1

1

V

AP P L I ED

1

e

T

C

----------

RC

=

V

=

V

CH O L D

CH O L D

;[1] V

CHOLD

charged to within 1/2 lsb

;[2] V

CHOLD

charge response to V

APPLIED

V

AP P L I ED

1

e

Tc

---------

RC

=

V

A PP L I E D

1

--------------------------

2 n +

1

1

1

;combining [1] and [2]

Note: Where n = number of bits of the ADC.

Solving for T

C

:

T

C

=

=

C

HOL D

R

IC

10

pF

1

k

+

+

7

R

SS

+ k

+

R

S

ln(1/2047)

10

k

  ln

4.88

10

4

=

1.37

µs

Therefore:

T

A CQ

= 2µs + 1.37µs +

 

50°C- 25°C

 

0.05

µs/°C

 

= 4.62µs

2010-2012 Microchip Technology Inc.

DS41414D-page 172

PIC16(L)F1946/47

Note 1:

2:

3:

The reference voltage (V

REF

) has no effect on the equation, since it cancels itself out.

The charge holding capacitor (C

HOLD

) is not discharged after each conversion.

The maximum recommended impedance for analog sources is 10 k

. This is required to meet the pin leakage specification.

FIGURE 16-4: ANALOG INPUT MODEL

Rs

Analog

Input pin

V

DD

V

T

0.6V

R

IC

1k

Sampling

Switch

SS Rss

VA

C

PIN

5 pF

V

T

0.6V

I

LEAKAGE

(1)

C

HOLD

= 10 pF

V

SS

/V

REF

-

V

DD

6V

5V

4V

3V

2V

R

SS

Legend:

C

HOLD

C

PIN

I

LEAKAGE

R

IC

R

SS

SS

V

T

= Sample/Hold Capacitance

= Input Capacitance

= Leakage current at the pin due to various junctions

= Interconnect Resistance

= Resistance of Sampling Switch

= Sampling Switch

= Threshold Voltage

Note 1:

Refer to

Section 30.0 “Electrical Specifications”

.

5 6 7 8 9 10 11

Sampling Switch

(k

)

FIGURE 16-5: ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

V

REF

-

03h

02h

01h

00h

0.5 LSB

Zero-Scale

Transition

Full-Scale

Transition

Analog Input Voltage

1.5 LSB

V

REF

+

2010-2012 Microchip Technology Inc.

DS41414D-page 173

PIC16(L)F1946/47

TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Name

ADCON0

ADCON1

Bit 7

ADFM

Bit 6 Bit 5

ADCS<2:0>

Bit 4

CHS<4:0>

Bit 3

Bit 2

ADNREF

Bit 1 Bit 0

GO/DONE ADON

ADPREF<1:0>

Register on Page

168

169

ADRESH

ADRESL

ANSELA

ANSELF

ANSELG

CCP1CON

INTCON

PIE1

PIR1

TRISA

TRISB

TRISE

FVRCON

DACCON0

A/D Result Register High

A/D Result Register Low

ANSELF7

ANSELF6

P1M<1:0>

ANSA5

ANSELF5

ANSELF4

— ANSELG4

DC1B<1:0>

GIE

TMR1GIE

TMR1GIF

TRISA7

TRISB7

TRISE7

FVREN

DACEN

PEIE

ADIE

ADIF

TRISA6

TRISB6

TRISE6

FVRRDY

DACLPS

TMR0IE

RCIE

RCIF

TRISA5

TRISB5

TRISE5

TSEN

DACOE

INTE

TXIE

TXIF

TRISA4

TRISB4

TRISE4

TSRNG

ANSA3

ANSELF3

ANSELG3

IOCIE

SSPIE

SSPIF

TRISA3

TRISB3

TRISE3

ANSA2

ANSELF2

ANSA1

ANSELF1

ANSELG2 ANSELG1

CCP1M<3:0>

TMR0IF

CCP1IE

CCP1IF

TRISA2

TRISB2

TRISE2

CDAFVR<1:0>

DACPSS<1:0>

INTF

TMR2IE

TMR2IF

TRISA1

TRISB1

TRISE1

ANSA0

ANSELF0

IOCIF

TMR1IE

TMR1IF

TRISA0

TRISB0

TRISE0

ADFVR<1:0>

— DACNSS

170

170

132

147

150

238

92

93

97

131

134

143

158

178

DACCON1

Legend:

— — — DACR<4:0>

178

x

= unknown, u

= unchanged,

= unimplemented read as ‘

0

’, q

= value depends on condition. Shaded cells are not used for ADC module.

DS41414D-page 174

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

17.0

DIGITAL-TO-ANALOG

CONVERTER (DAC) MODULE

The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels.

The input of the DAC can be connected to:

• External V

REF

pins

• V

DD

supply voltage

• FVR (Fixed Voltage Reference)

The output of the DAC can be configured to supply a reference voltage to the following:

• Comparator positive input

• ADC input channel

• DACOUT pin

• Capacitive Sensing module (CPS)

The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register.

EQUATION 17-1: DAC OUTPUT VOLTAGE

IF DACEN = 1

V

OUT

=

V

SOURCE

+

V

SOURCE

-

 

-----------------------------

2

5

+

V

SOURCE

-

IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111

V

OUT

= V

SOURCE

+

17.1

Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.

The DAC output voltage is determined by the following equations:

IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000

V

OUT

= V

SOURCE

V

SOURCE

+ = V

DD

, V

REF

, or FVR BUFFER 2

V

SOURCE

- = V

SS

17.2

Ratiometric Output Level

The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value.

The value of the individual resistors within the ladder can be found in

Section 30.0 “Electrical

Specifications”

.

17.3

DAC Voltage Reference Output

The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to ‘

1

’.

Selecting the DAC reference voltage for output on the

DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for DAC reference voltage output will always return a ‘

0

’.

Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for

external connections to DACOUT. Figure 17-2 shows

an example buffering technique.

2010-2012 Microchip Technology Inc.

DS41414D-page 175

PIC16(L)F1946/47

FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

FVR BUFFER2

V

DD

V

REF

+

DACPSS<1:0>

DACEN

DACLPS

2

DACNSS

V

REF

-

V

SS

Digital-to-Analog Converter (DAC)

V

SOURCE+

32

Steps

R

R

R

R

R

R

R

R

5

DACR<4:0>

DAC Output (To Comparator, CPS and

ADC Modules)

DACOUT

DACOE

V

SOURCE-

FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC

®

MCU

DAC

Module

R

Voltage

Reference

Output

Impedance

DACOUT

+

Buffered DAC Output

2010-2012 Microchip Technology Inc.

DS41414D-page 176

PIC16(L)F1946/47

17.4

Low-Power Voltage State

In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected.

Either the positive voltage source, (V

SOURCE

+), or the negative voltage source, (V

SOURCE

-) can be disabled.

The negative voltage source is disabled by setting the

DACLPS bit in the DACCON0 register. Clearing the

DACLPS bit in the DACCON0 register disables the positive voltage source.

17.4.1

OUTPUT CLAMPED TO POSITIVE

VOLTAGE SOURCE

The DAC output voltage can be set to V

SOURCE

+ with the least amount of power consumption by performing the following:

• Clearing the DACEN bit in the DACCON0 register.

• Setting the DACLPS bit in the DACCON0 register.

• Configuring the DACPSS bits to the proper positive source.

• Configuring the DACR<4:0> bits to ‘

11111

’ in the

DACCON1 register.

FIGURE 17-3: OUTPUT VOLTAGE CLAMPING EXAMPLES

This is also the method used to output the voltage level from the FVR to an output pin. See

Section 17.5

“Operation During Sleep”

for more information.

Reference Figure 17-3

for output clamping examples.

17.4.2

OUTPUT CLAMPED TO NEGATIVE

VOLTAGE SOURCE

The DAC output voltage can be set to V

SOURCE

- with the least amount of power consumption by performing the following:

• Clearing the DACEN bit in the DACCON0 register.

• Clearing the DACLPS bit in the DACCON0 register.

• Configuring the DACNSS bits to the proper negative source.

• Configuring the DACR<4:0> bits to ‘

00000

’ in the

DACCON1 register.

This allows the comparator to detect a zero-crossing while not consuming additional current through the DAC module.

Reference Figure 17-3

for output clamping examples.

Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source

V

SOURCE

+

V

SOURCE

+

DACEN =

0

DACLPS =

1

R

R

DACR<4:0> =

11111

DAC Voltage Ladder

(see Figure 17-1 )

R

DACEN =

0

DACLPS =

0

R

R

DAC Voltage Ladder

(see

Figure 17-1

)

R

DACR<4:0> =

00000

V

SOURCE -

V

SOURCE -

17.5

Operation During Sleep

When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled.

17.6

Effects of a Reset

A device Reset affects the following:

• DAC is disabled.

• DAC output voltage is removed from the

DACOUT pin.

• The DACR<4:0> range select bits are cleared.

2010-2012 Microchip Technology Inc.

DS41414D-page 177

PIC16(L)F1946/47

17.7

Register Definitions: DAC Control

REGISTER 17-1:

R/W-0/0 bit 7

DACEN

DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0

DACLPS

R/W-0/0

DACOE

U-0

R/W-0/0 R/W-0/0

DACPSS<1:0>

U-0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3-2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

DACEN:

DAC Enable bit

1 = DAC is enabled

0 = DAC is disabled

DACLPS:

DAC Low-Power Voltage State Select bit

1 = DAC Positive reference source selected

0 = DAC Negative reference source selected

DACOE:

DAC Voltage Output Enable bit

1 = DAC voltage level is also an output on the DACOUT pin

0 = DAC voltage level is disconnected from the DACOUT pin

Unimplemented:

Read as ‘

0

DACPSS<1:0>:

DAC Positive Source Select bits

00 = V

DD

01 = V

REF

+ pin

10 =

FVR Buffer2 output

11 = Reserved, do not use

Unimplemented:

Read as ‘

0

DACNSS:

DAC Negative Source Select bits

1 = V

REF

-

0 = V

SS

R/W-0/0

DACNSS bit 0

REGISTER 17-2:

U-0

DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0

U-0

R/W-0/0 R/W-0/0 R/W-0/0

DACR<4:0>

R/W-0/0 bit 7

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-5 bit 4-0

Unimplemented:

Read as ‘

0

DACR<4:0>:

DAC Voltage Output Select bits

TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

FVRCON

DACCON0

FVREN

DACEN

FVRRDY

DACLPS

TSEN

DACOE

TSRNG

CDAFVR<1:0>

DACPSS<1:0>

ADFVR1

DACCON1

Legend:

— — — DACR<4:0>

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used with the DAC module.

Bit 0

ADFVR0

DACNSS

Register on page

158

178

178

2010-2012 Microchip Technology Inc.

DS41414D-page 178

18.0

COMPARATOR MODULE

Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes.

Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features:

• Independent comparator control

• Programmable input selection

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

• Wake-up from Sleep

• Programmable Speed/Power optimization

• PWM shutdown

• Programmable and fixed voltage reference

18.1

Comparator Overview

A single comparator is shown in

Figure 18-1 along with

the relationship between the analog input levels and the digital output. When the analog voltage at V

IN

+ is less than the analog voltage at V

IN

-, the output of the comparator is a digital low level. When the analog voltage at V

IN

+ is greater than the analog voltage at

V

IN

-, the output of the comparator is a digital high level.

The comparators available for this device are located in

Table 18-1

.

TABLE 18-1: COMPARATOR AVAILABILITY

PER DEVICE

Device

PIC16(L)F1946

PIC16(L)F1947

PIC16(L)F1946/47

FIGURE 18-1:

V

IN

+

V

IN

-

SINGLE COMPARATOR

+

Output

V

IN

-

V

IN

+

Output

Note:

The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.

2010-2012 Microchip Technology Inc.

DS41414D-page 179

PIC16(L)F1946/47

FIGURE 18-2:

CxNCH<1:0>

2

COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM

CxON

(1)

CxINTP

Interrupt det

C

X

IN0-

C

X

IN1-

C

X

IN2-

C

X

IN3-

0

1

2

MUX

(2)

3

C

X

POL

CxVN

-

Interrupt det

CxINTN

Cx

(3)

D Q

CxVP

+

Q1 EN

C

X

IN+

DAC Output

FVR Buffer2

V

SS

C

X

PCH<1:0>

2

2

3

0

1

MUX

(2)

CxON

CxHYS

CxSP

D Q

C

X

SYNC

0

1 to CM

X

CON0 (C

X

OUT) and CM2CON1 (MC

X

OUT) async_CxOUT

Set CxIF to PWM

C

X

OE

TRIS bit

C

X

OUT

(from Timer1)

T1CLK sync_CxOUT

To Timer1 or

SR Latch

Note 1:

2:

3:

When CxON =

0

, the Comparator will produce a ‘

0

’ at the output.

When CxON =

0

, all multiplexer inputs are disconnected.

Output of comparator can be frozen during debugging.

DS41414D-page 180

2010-2012 Microchip Technology Inc.

18.2

Comparator Control

Each comparator has 2 control registers: CMxCON0 and

CMxCON1.

The CMxCON0 registers (see Register 18-1 ) contain

Control and Status bits for the following:

• Enable

• Output selection

• Output polarity

• Speed/Power selection

• Hysteresis enable

• Output synchronization

The CMxCON1 registers (see Register 18-2 ) contain

Control bits for the following:

• Interrupt enable

• Interrupt edge polarity

• Positive input channel selection

• Negative input channel selection

18.2.1

COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption.

18.2.2

COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

Note 1:

2:

The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override.

The internal output of the comparator is latched with each instruction cycle.

Unless otherwise specified, external outputs are not latched.

PIC16(L)F1946/47

18.2.3

COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

Table 18-2

shows the output state versus input conditions, including polarity control.

TABLE 18-2: COMPARATOR OUTPUT

STATE VS. INPUT

CONDITIONS

CxPOL CxOUT Input Condition

CxV

N

> CxV

P

CxV

N

< CxV

P

CxV

N

> CxV

P

CxV

N

< CxV

P

1

1

0

0

1

0

0

1

18.2.4

COMPARATOR SPEED/POWER

SELECTION

The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is ‘

1

’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘

0

’.

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DS41414D-page 181

PIC16(L)F1946/47

18.3

Comparator Hysteresis

A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register.

See

Section 30.0 “Electrical Specifications”

for

more information.

18.4

Timer1 Gate Operation

The output resulting from a comparator operation can be used as a source for gate control of Timer1. See

Section 21.6 “Timer1 Gate”

for more information.

This feature is useful for timing the duration or interval of an analog event.

It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring.

18.4.1

COMPARATOR OUTPUT

SYNCHRONIZATION

The output from a comparator can be synchronized with Timer1 by setting the CxSYNC bit of the

CMxCON0 register.

Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator

Block Diagram (

Figure 18-2 ) and the Timer1 Block

Diagram ( Figure 21-1

) for more information.

18.5

Comparator Interrupt

An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present.

When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt

Flag bit (CxIF bit of the PIR2 register) will be set.

To enable the interrupt, you must set the following bits:

• CxON, CxPOL and CxSP bits of the CMxCON0 register

• CxIE bit of the PIE2 register

• CxINTP bit of the CMxCON1 register (for a rising edge detection)

• CxINTN bit of the CMxCON1 register (for a falling edge detection)

• PEIE and GIE bits of the INTCON register

The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.

Note:

Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register.

18.6

Comparator Positive Input

Selection

Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator:

• CxIN+ analog pin

• DAC output

• FVR (Fixed Voltage Reference)

• V

SS

(Ground)

See

Section 14.0 “Fixed Voltage Reference (FVR)”

for more information on the Fixed Voltage Reference module.

See

Section 17.0 “Digital-to-Analog Converter

(DAC) Module”

for more information on the DAC input signal.

Any time the comparator is disabled (CxON =

0

), all comparator inputs are disabled.

2010-2012 Microchip Technology Inc.

DS41414D-page 182

18.7

Comparator Negative Input

Selection

The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input.

Note:

To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.

18.8

Comparator Response Time

The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference.

Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Refer-

ence Specifications in

Section 30.0 “Electrical Specifications”

for more details.

18.9

Interaction with ECCP Logic

The comparators can be used as general purpose comparators. Their outputs can be brought out to the

CxOUT pins. When the ECCP Auto-Shutdown is active it can use one or both comparator signals. If auto-restart is also enabled, the comparators can be configured as a closed loop analog feedback to the

ECCP, thereby, creating an analog controlled PWM.

Note:

When the Comparator module is first initialized the output state is unknown.

Upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the ECCP

Auto-Shutdown mode.

PIC16(L)F1946/47

18.10 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 18-3

. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to V

DD

and V

SS

. The analog input, therefore, must be between V

SS

and V

DD

.

If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.

A maximum source impedance of 10 k

is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced.

Note 1:

When reading a PORT register, all pins configured as analog inputs will read as a

0

’. Pins configured as digital inputs will convert as an analog input, according to the input specification.

2:

Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.

2010-2012 Microchip Technology Inc.

DS41414D-page 183

PIC16(L)F1946/47

FIGURE 18-3: ANALOG INPUT MODEL

V

DD

Rs < 10K

Analog

Input pin

V

T

0.6V

R

IC

I

LEAKAGE

(1)

V

A

C

PIN

5 pF

V

T

0.6V

Vss

Legend:

C

PIN

= Input Capacitance

I

LEAKAGE

= Leakage Current at the pin due to various junctions

R

IC

R

S

= Interconnect Resistance

= Source Impedance

V

A

V

T

= Analog Voltage

= Threshold Voltage

Note 1:

See

Section 30.0 “Electrical Specifications”

To Comparator

DS41414D-page 184

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

18.11 Register Definitions: Comparator Control

REGISTER 18-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0

CxON bit 7

R-0/0

CxOUT

R/W-0/0

CxOE

R/W-0/0

CxPOL

U-0

R/W-1/1

CxSP

R/W-0/0

CxHYS

R/W-0/0

CxSYNC bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

CxON:

Comparator Enable bit

1

= Comparator is enabled and consumes no active power

0

= Comparator is disabled

CxOUT:

Comparator Output bit

If CxPOL =

1

(inverted polarity):

1

= CxVP < CxVN

0

= CxVP > CxVN

If CxPOL =

0

(non-inverted polarity):

1

= CxVP > CxVN

0

= CxVP < CxVN

CxOE:

Comparator Output Enable bit

1

= CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON.

0

= CxOUT is internal only

CxPOL:

Comparator Output Polarity Select bit

1

= Comparator output is inverted

0

= Comparator output is not inverted

Unimplemented:

Read as ‘

0

CxSP:

Comparator Speed/Power Select bit

1

= Comparator operates in normal power, higher speed mode

0

= Comparator operates in low-power, low-speed mode

CxHYS:

Comparator Hysteresis Enable bit

1

= Comparator hysteresis enabled

0

= Comparator hysteresis disabled

CxSYNC:

Comparator Output Synchronous Mode bit

1

= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.

Output updated on the falling edge of Timer1 clock source.

0

= Comparator output to Timer1 and I/O pin is asynchronous.

2010-2012 Microchip Technology Inc.

DS41414D-page 185

PIC16(L)F1946/47

REGISTER 18-2:

R/W-0/0

CxINTP bit 7

CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

R/W-0/0

CxINTN

R/W-0/0 R/W-0/0

CxPCH<1:0>

U-0

U-0

R/W-0/0 R/W-0/0

CxNCH<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6 bit 5-4 bit 3-2 bit 1-0

CxINTP:

Comparator Interrupt on Positive Going Edge Enable bits

1

= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit

0

= No interrupt flag will be set on a positive going edge of the CxOUT bit

CxINTN:

Comparator Interrupt on Negative Going Edge Enable bits

1

= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit

0

= No interrupt flag will be set on a negative going edge of the CxOUT bit

CxPCH<1:0>:

Comparator Positive Input Channel Select bits

11

= CxVP connects to V

SS

10

= CxVP connects to FVR Voltage Reference

01

= CxVP connects to DAC Voltage Reference

00

= CxVP connects to CxIN+ pin

Unimplemented:

Read as ‘

0

CxNCH<1:0>:

Comparator Negative Input Channel Select bits

11

= CxVN connects to C

X

IN3- pin

10

= CxVN connects to C

X

IN2- pin

01

= CxVN connects to C

X

IN1- pin

00

= CxVN connects to C

X

IN0- pin

REGISTER 18-3: CMOUT: COMPARATOR OUTPUT REGISTER

bit 7

U-0

U-0

U-0

U-0

U-0

R-0/0

MC3OUT

R-0/0

MC2OUT

R-0/0

MC1OUT bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

Unimplemented:

Read as ‘

0

MC3OUT:

Mirror Copy of C3OUT bit

MC2OUT:

Mirror Copy of C2OUT bit

MC1OUT:

Mirror Copy of C1OUT bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

2010-2012 Microchip Technology Inc.

DS41414D-page 186

PIC16(L)F1946/47

TABLE 18-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELF

ANSELG

CM1CON0

CM2CON0

CM1CON1

CM2CON1

CM3CON0

CM3CON1

ANSF7

C1ON

C2ON

C1NTP

C2NTP

C3ON

C3INTP

ANSF6

C1OUT

C2OUT

C1INTN

C2INTN

C3OUT

C3INTN

ANSF5

C1OE

C2OE

ANSF4

ANSG4

C1POL

C2POL

C1PCH<1:0>

C2PCH<1:0>

C3OE

C3PCH1

C3POL

C3PCH0

ANSF3

ANSG3

ANSF2

ANSG2

C1SP

C2SP

C3SP

ANSF1

ANSG1

C1HYS

C2HYS

ANSF0

C1SYNC

C2SYNC

C1NCH<1:0>

C2NCH<1:0>

C3HYS C3SYNC

C3NCH<1:0>

CMOUT

FVRCON

DACCON0

DACCON1

INTCON

PIE2

PIR2

TRISF

TRISG

Legend:

FVREN

DACEN

GIE

OSFIE

OSFIF

TRISF7

FVRRDY

DACLPS

PEIE

C2IE

C2IF

TRISF6

TSEN

DACOE

TMR0IE

C1IE

C1IF

TRISF5

TSRNG

INTE

EEIE

EEIF

TRISF4

IOCIE

BCLIE

BCLIF

TRISF3

MC3OUT

CDAFVR<1:0>

DACPSS<1:0>

DACR<4:0>

TMR0IF

LCDIE

LCDIF

TRISF2

MC2OUT

ADFVR<1:0>

INTF

C3IE

C3IF

TRISF1

— — TRISG5 TRISG4 TRISG3 TRISG2 TRISG1

— = unimplemented location, read as ‘

0

’. Shaded cells are unused by the comparator module.

MC1OUT

DACNSS

IOCIF

CCP2IE

CCP2IF

TRISF0

TRISG0

Register on Page

92

94

98

146

149

186

158

178

178

186

186

185

186

147

150

185

185

2010-2012 Microchip Technology Inc.

DS41414D-page 187

PIC16(L)F1946/47

NOTES:

DS41414D-page 188

2010-2012 Microchip Technology Inc.

19.0

SR LATCH

The module consists of a single SR Latch with multiple

Set and Reset inputs as well as separate latch outputs.

The SR Latch module includes the following features:

• Programmable input selection

• SR Latch output is available externally

• Separate Q and Q outputs

• Firmware Set and Reset

The SR Latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications.

19.1

Latch Operation

The latch is a Set-Reset Latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be set or reset by:

• Software control (SRPS and SRPR bits)

• Comparator C1 output (sync_C1OUT)

• Comparator C2 output (sync_C2OUT)

• SRI pin

• Programmable clock (SRCLK)

The SRPS and the SRPR bits of the SRCON0 register may be used to set or reset the SR Latch, respectively.

The latch is Reset-dominant. Therefore, if both Set and

Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation.

The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR Latch. The output of either comparator can be synchronized to the Timer1

clock source. See

Section 18.0 “Comparator Module”

and

Section 21.0 “Timer1 Module with Gate

Control”

for more information.

An external source on the SRI pin can be used as the

Set or Reset inputs of the SR Latch.

An internal clock source is available that can periodically set or reset the SR Latch. The SRCLK<2:0> bits in the

SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to set or reset the SR

Latch, respectively.

PIC16(L)F1946/47

19.2

Latch Output

The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR

Latch outputs may be directly output to an I/O pin at the same time.

The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver.

19.3

Effects of a Reset

Upon any device Reset, the SR Latch output is not initialized to a known state. The user’s firmware is responsible for initializing the latch output before enabling the output pins.

2010-2012 Microchip Technology Inc.

DS41414D-page 189

PIC16(L)F1946/47

FIGURE 19-1:

SRPS

SR LATCH SIMPLIFIED BLOCK DIAGRAM

Pulse

Gen

(

2

)

SRLEN

SRQEN

SRI

SRSPE

SRCLK

SRSCKE sync_C2OUT

(3)

SRSC2E sync_C1OUT

(3)

SRSC1E

SRPR

Pulse

Gen

(

2

)

S Q

SR

Latch

(1)

SRI

SRRPE

SRCLK

SRRCKE sync_C2OUT

(3)

SRRC2E sync_C1OUT

(3)

SRRC1E

R Q

SRLEN

SRNQEN

Note 1:

2:

3:

If R =

1

and S =

1

simultaneously, Q =

0

, Q =

1

.

Pulse generator causes a 1 Q-state pulse width.

Name denotes the connection point at the comparator output.

SRQ

SRNQ

DS41414D-page 190

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

TABLE 19-1:

SRCLK

111

110

101

100

011

010

001

000

SRCLK FREQUENCY TABLE

Divider F

OSC

= 32 MHz F

OSC

= 20 MHz

32

16

8

4

512

256

128

64

62.5 kHz

125 kHz

250 kHz

500 kHz

1 MHz

2 MHz

4 MHz

8 MHz

39.0 kHz

78.1 kHz

156 kHz

313 kHz

625 kHz

1.25 MHz

2.5 MHz

5 MHz

F

OSC

= 16 MHz

31.3 kHz

62.5 kHz

125 kHz

250 kHz

500 kHz

1 MHz

2 MHz

4 MHz

F

OSC

= 4 MHz

7.81 kHz

15.6 kHz

31.25 kHz

62.5 kHz

125 kHz

250 kHz

500 kHz

1 MHz

F

OSC

= 1 MHz

1.95 kHz

3.90 kHz

7.81 kHz

15.6 kHz

31.3 kHz

62.5 kHz

125 kHz

250 kHz

2010-2012 Microchip Technology Inc.

DS41414D-page 191

PIC16(L)F1946/47

19.4

Register Definitions: SR Latch Control

REGISTER 19-1: SRCON0: SR LATCH CONTROL 0 REGISTER

R/W-0/0

SRLEN bit 7

R/W-0/0 R/W-0/0

SRCLK<2:0>

R/W-0/0 R/W-0/0

SRQEN

R/W-0/0

SRNQEN

R/S-0/0

SRPS

R/S-0/0

SRPR bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

S = Bit is set only bit 7 bit 6-4 bit 3 bit 2 bit 1 bit 0

Note 1:

SRLEN:

SR Latch Enable bit

1

= SR Latch is enabled

0

= SR Latch is disabled

SRCLK<2:0>:

SR Latch Clock Divider bits

111

= Generates a 1 F

OSC

wide pulse every 512th F

OSC

cycle clock

110

= Generates a 1 F

OSC

wide pulse every 256th F

OSC

cycle clock

101

= Generates a 1 F

OSC

wide pulse every 128th F

OSC

cycle clock

100

= Generates a 1 F

OSC

wide pulse every 64th F

OSC

cycle clock

011

= Generates a 1 F

OSC

wide pulse every 32nd F

OSC

cycle clock

010

= Generates a 1 F

OSC

wide pulse every 16th F

OSC

cycle clock

001

= Generates a 1 F

OSC

wide pulse every 8th F

OSC

cycle clock

000

= Generates a 1 F

OSC

wide pulse every 4th F

OSC

cycle clock

SRQEN:

SR Latch Q Output Enable bit

If SRLEN =

1

:

1

= Q is present on the SRQ pin

0

= External Q output is disabled

If SRLEN =

0

:

SR Latch is disabled

SRNQEN:

SR Latch Q Output Enable bit

If SRLEN =

1

:

1

= Q is present on the SRnQ pin

0

= External Q output is disabled

If SRLEN =

0

:

SR Latch is disabled

SRPS:

Pulse Set Input of the SR Latch bit

(1)

1

= Pulse set input for 1 Q-clock period

0

= No effect on set input

SRPR:

Pulse Reset Input of the SR Latch bit

(1)

1

= Pulse reset input for 1 Q-clock period

0

= No effect on reset input

Set only, always reads back ‘

0

’.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

REGISTER 19-2:

R/W-0/0

SRSPE bit 7

SRCON1: SR LATCH CONTROL 1 REGISTER

R/W-0/0

SRSCKE

R/W-0/0

SRSC2E

R/W-0/0

SRSC1E

R/W-0/0

SRRPE

R/W-0/0

SRRCKE

R/W-0/0

SRRC2E

R/W-0/0

SRRC1E bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SRSPE:

SR Latch Peripheral Set Enable bit

1

= SR Latch is set when the SRI pin is high

0

= SRI pin has no effect on the set input of the SR Latch

SRSCKE:

SR Latch Set Clock Enable bit

1

= Set input of SR Latch is pulsed with SRCLK

0

= SRCLK has no effect on the set input of the SR Latch

SRSC2E:

SR Latch C2 Set Enable bit

1

= SR Latch is set when the C2 Comparator output is high

0

= C2 Comparator output has no effect on the set input of the SR Latch

SRSC1E:

SR Latch C1 Set Enable bit

1

= SR Latch is set when the C1 Comparator output is high

0

= C1 Comparator output has no effect on the set input of the SR Latch

SRRPE:

SR Latch Peripheral Reset Enable bit

1

= SR Latch is reset when the SRI pin is high

0

= SRI pin has no effect on the reset input of the SR Latch

SRRCKE:

SR Latch Reset Clock Enable bit

1

= Reset input of SR Latch is pulsed with SRCLK

0

= SRCLK has no effect on the reset input of the SR Latch

SRRC2E:

SR Latch C2 Reset Enable bit

1

= SR Latch is reset when the C2 Comparator output is high

0

= C2 Comparator output has no effect on the reset input of the SR Latch

SRRC1E:

SR Latch C1 Reset Enable bit

1

= SR Latch is reset when the C1 Comparator output is high

0

= C1 Comparator output has no effect on the reset input of the SR Latch

TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELA

SRCON0

SRCON1

TRISA

Legend:

SRLEN

SRSPE

TRISA7

SRSCKE

TRISA6

ANSA5

SRCLK<2:0>

SRSC2E

TRISA5

SRSC1E

TRISA4

ANSA3

SRQEN

SRRPE

TRISA3

ANSA2

SRNQEN

SRRCKE SRRC2E

TRISA2

ANSA1

SRPS

TRISA1

ANSA0

SRPR

SRRC1E

TRISA0

— = unimplemented location, read as ‘

0

’. Shaded cells are unused by the SR Latch module.

Register on Page

132

192

193

131

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

NOTES:

DS41414D-page 194

2010-2012 Microchip Technology Inc.

20.0

TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

• TMR0 can be used to gate Timer1

Figure 20-1

is a block diagram of the Timer0 module.

20.1

Timer0 Operation

The Timer0 module can be used as either an 8-bit timer or an 8-bit counter.

20.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the

OPTION_REG register.

FIGURE 20-1: BLOCK DIAGRAM OF THE TIMER0

F

OSC

/4

0

T0CKI

0

1

From CPSCLK

1

TMR0SE

TMR0CS

T0XCS

8-bit

Prescaler

PIC16(L)F1946/47

When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when

TMR0 is written.

20.1.2

8-BIT COUNTER MODE

In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the

Capacitive Sensing Oscillator (CPSCLK) signal.

8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to

1

’ and resetting the T0XCS bit in the CPSCON0 register to ‘

0

’.

8-Bit Counter mode using the Capacitive Sensing

Oscillator (CPSCLK) signal is selected by setting the

TMR0CS bit in the OPTION_REG register to ‘

1

’ and setting the T0XCS bit in the CPSCON0 register to ‘

1

’.

The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register.

1

0

PSA

Sync

2 T

CY

Data Bus

8

TMR0

Set Flag bit TMR0IF on Overflow

Overflow to Timer1

8

PS<2:0>

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

20.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register.

Note:

The Watchdog Timer (WDT) uses its own independent prescaler.

There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the

Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register.

The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler.

20.1.4

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register.

Note:

The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.

20.1.5

8-BIT COUNTER MODE

SYNCHRONIZATION

When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in

Section 30.0 “Electrical

Specifications”

.

20.1.6

OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.

DS41414D-page 196

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

20.2

Register Definitions: Option Register

REGISTER 20-1: OPTION_REG: OPTION REGISTER

R/W-1/1

WPUEN bit 7

R/W-1/1

INTEDG

R/W-1/1

TMR0CS

R/W-1/1

TMR0SE

R/W-1/1

PSA

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

R/W-1/1 R/W-1/1

PS<2:0>

R/W-1/1 bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0

WPUEN:

Weak Pull-Up Enable bit

1

= All weak pull-ups are disabled (except MCLR, if it is enabled)

0

= Weak pull-ups are enabled by individual WPUx latch values

INTEDG:

Interrupt Edge Select bit

1

= Interrupt on rising edge of INT pin

0

= Interrupt on falling edge of INT pin

TMR0CS:

Timer0 Clock Source Select bit

1

= Transition on T0CKI pin

0

= Internal instruction cycle clock (F

OSC

/4)

TMR0SE:

Timer0 Source Edge Select bit

1

= Increment on high-to-low transition on T0CKI pin

0

= Increment on low-to-high transition on T0CKI pin

PSA:

Prescaler Assignment bit

1

= Prescaler is not assigned to the Timer0 module

0

= Prescaler is assigned to the Timer0 module

PS<2:0>:

Prescaler Rate Select bits

Bit Value Timer0 Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CPSCON0

INTCON

OPTION_REG WPUEN

TMR0

INTEDG TMR0CS TMR0SE

Timer0 Module Register

TRISA

CPSON CPSRM

GIE PEIE

TMR0IE

INTE

Legend:

*

CPSRNG<1:0>

IOCIE

PSA

TMR0IF

CPSOUT

INTF

PS<2:0>

T0XCS

IOCIF

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used by the Timer0 module.

Page provides register information.

Register on Page

333

92

197

195 *

131

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

NOTES:

DS41414D-page 198

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

21.0

TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Dedicated 32 kHz oscillator circuit

• Optionally synchronized comparator out

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP/ECCP)

• Selectable Gate Source Polarity

FIGURE 21-1: TIMER1 BLOCK DIAGRAM

• Gate Toggle mode

• Gate Single-Pulse mode

• Gate Value Status

• Gate Event Interrupt

Figure 21-1

is a block diagram of the Timer1 module.

T1GSS<1:0>

T1G

From Timer0

Overflow sync_C1OUT sync_C2OUT

T1OSO

T1OSI

T1OSCEN

00

01

10

11

T1GPOL

Set flag bit

TMR1IF on

Overflow

T1GSPM

TMR1ON

T1GTM

OUT

T1OSC

EN t1g_in

D

R

CK

Q

Q

TMR1H

TMR1

(2)

TMR1L

(1)

0

1

Single-Pulse

Acq. Control

T1GGO/DONE

0

T1GVAL

D

1

Q1

EN

Q

Interrupt det

TMR1GE

TMR1ON

0

Data Bus

RD

T1GCON

Set

TMR1GIF

Synchronized clock input

To Comparator Module

Q

EN

D

T1CLK

1

T1SYNC

1

TMR1CS<1:0>

Cap. Sensing

Oscillator

11

10

0

F

OSC

Internal

Clock

F

OSC

/4

Internal

Clock

01

00

Prescaler

1, 2, 4, 8

2

T1CKPS<1:0>

F

OSC

/2

Internal

Clock

Synchronize

(3)

det

Sleep input

T1CKI

To LCD and Clock Switching Modules

Note 1:

2:

3:

ST Buffer is high speed type when using T1CKI.

Timer1 register increments on rising edge.

Synchronize does not operate while in Sleep.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

21.1

Timer1 Operation

The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.

When used with an internal clock source, the module is a timer and increments on every instruction cycle.

When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers, respectively.

Table 21-1 displays the Timer1 enable

selections.

TABLE 21-1:

TMR1ON

1

1

0

0

TIMER1 ENABLE

SELECTIONS

TMR1GE

0

1

0

1

Timer1

Operation

Off

Off

Always On

Count Enabled

21.2

Clock Source Selection

The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1.

Table 21-2

displays the clock source selections.

21.2.1

INTERNAL CLOCK SOURCE

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples of F

OSC

as determined by the Timer1 prescaler.

When the F

OSC

internal clock source is selected, the

Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the

Timer1 clock input.

The following asynchronous sources may be used:

• Asynchronous event on the T1G pin to Timer1 gate

• C1 or C2 comparator input to Timer1 gate

21.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1 module may work as a timer or a counter.

When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously.

When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit.

Note:

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON =

0

) when T1CKI is high then Timer1 is enabled (TMR1ON=

1

) when T1CKI is low.

TABLE 21-2:

TMR1CS1

1

1

0

0

1

CLOCK SOURCE SELECTIONS

TMR1CS0 T1OSCEN

1

0

1

0

0 x

0 x x

1

Clock Source

System Clock (F

OSC

)

Instruction Clock (F

OSC

/4)

Capacitive Sensing Oscillator

External Clocking on T1CKI Pin

Osc.Circuit On T1OSI/T1OSO Pins

2010-2012 Microchip Technology Inc.

DS41414D-page 200

21.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

21.4

Timer1 Oscillator

A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO

(amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep.

Note:

The oscillator requires a start-up and stabilization time before use. Thus,

T1OSCEN should be set and a suitable delay observed prior to using Timer1. A suitable delay, similar to the OST delay can be implemented in software by clearing the TMR1IF bit, then presetting the TMR1H:TMR1L register pair to

FC00h. The TMR1IF flag will be set when

1024 clock cycles have elapsed, thereby indicating that the oscillator is running and is reasonably stable.

21.5

Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see

Section 21.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”

).

Note:

When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.

PIC16(L)F1946/47

21.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the timer may overflow between the reads.

For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.

21.6

Timer1 Gate

Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable.

Timer1 gate can also be driven by multiple selectable sources.

21.6.1

TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the

current count. See Figure 21-3

for timing details.

TABLE 21-3:

T1CLK

TIMER1 GATE ENABLE

SELECTIONS

T1GPOL

1

1

0

0

T1G

0

1

0

1

Timer1 Operation

Counts

Holds Count

Holds Count

Counts

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DS41414D-page 201

PIC16(L)F1946/47

21.6.2

TIMER1 GATE SOURCE

SELECTION

Timer1 gate source selections are shown in

Table 21-4 .

Source selection is controlled by the T1GSS bits of the

T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the

T1GPOL bit of the T1GCON register.

TABLE 21-4:

T1GSS

00

01

10

11

TIMER1 GATE SOURCES

Timer1 Gate Source

Timer1 Gate Pin

Overflow of Timer0

(TMR0 increments from FFh to 00h)

Comparator 1 Output sync_C1OUT

(optionally Timer1 synchronized output)

Comparator 2 Output sync_C2OUT

(optionally Timer1 synchronized output)

21.6.2.1

T1G Pin Gate Operation

The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry.

21.6.2.2

Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry.

21.6.2.3

Comparator C1 Gate Operation

The output resulting from a Comparator 1 operation can be selected as a source for Timer1 gate control. The

Comparator 1 output (sync_C1OUT) can be synchronized to the Timer1 clock or left asynchronous.

For more information see

Section 18.4.1 “Comparator

Output Synchronization”

.

21.6.2.4

Comparator C2 Gate Operation

The output resulting from a Comparator 2 operation can be selected as a source for Timer1 gate control.

The Comparator 2 output (sync_C2OUT) can be synchronized to the Timer1 clock or left asynchronous.

For more information see

Section 18.4.1 “Comparator

Output Synchronization”

.

21.6.3

TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse.

The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See

Figure 21-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured.

Note:

Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation.

21.6.4

TIMER1 GATE SINGLE-PULSE

MODE

When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the

T1GGO/DONE bit in the T1GCON register must be set.

The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the

T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the

T1GGO/DONE bit is once again set in software. See

Figure 21-5

for timing details.

If the Single-Pulse Gate mode is disabled by clearing the

T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared.

Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See

Figure 21-6 for timing

details.

21.6.5

TIMER1 GATE VALUE STATUS

When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared).

21.6.6

TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized.

The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared).

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21.7

Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits:

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before enabling interrupts.

21.9

ECCP/CCP Capture/Compare Time

Base

The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event.

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

For more information, see

Section 23.0

“Capture/Compare/PWM Modules”

.

21.8

Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1CS bits of the T1CON register must be configured

• T1OSCEN bit of the T1CON register must be configured

The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service

Routine.

Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting.

FIGURE 21-2: TIMER1 INCREMENTING EDGE

21.10 ECCP/CCP Special Event Trigger

When any of the CCP’s are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1.

Timer1 should be synchronized and F

OSC

/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed.

In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence.

For more information, see

Section 16.3.1 “Special

Event Trigger”

.

T1CKI =

1 when TMR1

Enabled

T1CKI =

0 when TMR1

Enabled

Note 1:

2:

Arrows indicate counter increments.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

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PIC16(L)F1946/47

FIGURE 21-3: TIMER1 GATE ENABLE MODE

TMR1GE

T1GPOL t1g_in

T1CKI

T1GVAL

Timer1

N N + 1 N + 2

FIGURE 21-4: TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM t1g_in

T1CKI

T1GVAL

Timer1

N N + 1 N + 2 N + 3 N + 4

N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

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PIC16(L)F1946/47

FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM

T1GGO/

DONE t1g_in

Set by software

Counting enabled on rising edge of T1G

Cleared by hardware on falling edge of T1GVAL

T1CKI

T1GVAL

Timer1

TMR1GIF

N

Cleared by software

N + 1 N + 2

Set by hardware on falling edge of T1GVAL

Cleared by software

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PIC16(L)F1946/47

TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE FIGURE 21-6:

TMR1GE

T1GPOL

T1GSPM

T1GTM

T1GGO/

DONE t1g_in

Set by software

Counting enabled on rising edge of T1G

Cleared by hardware on falling edge of T1GVAL

T1CKI

T1GVAL

Timer1

TMR1GIF

N

Cleared by software

N + 1 N + 2 N + 3

N + 4

Set by hardware on falling edge of T1GVAL

Cleared by software

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PIC16(L)F1946/47

21.11 Register Definitions: Timer1 Control

REGISTER 21-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u R/W-0/u

TMR1CS<1:0> bit 7

R/W-0/u R/W-0/u

T1CKPS<1:0>

R/W-0/u

T1OSCEN

R/W-0/u

T1SYNC

U-0

R/W-0/u

TMR1ON bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

TMR1CS<1:0>:

Timer1 Clock Source Select bits

11

= Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)

10

= Timer1 clock source is pin or oscillator:

If T1OSCEN =

0

:

External clock from T1CKI pin (on the rising edge)

If T1OSCEN =

1

:

Crystal oscillator on T1OSI/T1OSO pins

01

= Timer1 clock source is system clock (F

OSC

)

00

= Timer1 clock source is instruction clock (F

OSC

/4)

T1CKPS<1:0>:

Timer1 Input Clock Prescale Select bits

11

= 1:8 Prescale value

10

= 1:4 Prescale value

01

= 1:2 Prescale value

00

= 1:1 Prescale value

T1OSCEN:

LP Oscillator Enable Control bit

1

= Dedicated Timer1 oscillator circuit enabled

0

= Dedicated Timer1 oscillator circuit disabled

T1SYNC:

Timer1 Synchronization Control bit

1

= Do not synchronize asynchronous clock input

0

= Synchronize asynchronous clock input with system clock (F

OSC

)

Unimplemented:

Read as ‘

0

TMR1ON:

Timer1 On bit

1

= Enables Timer1

0

= Stops Timer1 and clears Timer1 gate flip-flop

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PIC16(L)F1946/47

REGISTER 21-2:

R/W-0/u

TMR1GE bit 7

T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u

T1GPOL

R/W-0/u

T1GTM

R/W-0/u

T1GSPM

R/W/HC-0/u

T1GGO/

DONE

R-x/x

T1GVAL

R/W-0/u R/W-0/u

T1GSS<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

TMR1GE:

Timer1 Gate Enable bit

If TMR1ON =

0

:

This bit is ignored

If TMR1ON =

1

:

1

= Timer1 counting is controlled by the Timer1 gate function

0

= Timer1 counts regardless of Timer1 gate function

T1GPOL:

Timer1 Gate Polarity bit

1

= Timer1 gate is active-high (Timer1 counts when gate is high)

0

= Timer1 gate is active-low (Timer1 counts when gate is low)

T1GTM:

Timer1 Gate Toggle Mode bit

1

= Timer1 Gate Toggle mode is enabled

0

= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

T1GSPM:

Timer1 Gate Single-Pulse Mode bit

1

= Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate

0

= Timer1 Gate Single-Pulse mode is disabled

T1GGO/DONE:

Timer1 Gate Single-Pulse Acquisition Status bit

1

= Timer1 gate single-pulse acquisition is ready, waiting for an edge

0

= Timer1 gate single-pulse acquisition has completed or has not been started

T1GVAL:

Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

T1GSS<1:0>:

Timer1 Gate Source Select bits

11

= Comparator 2 optionally synchronized output (sync_C2OUT)

10

= Comparator 1 optionally synchronized output (sync_C1OUT)

01

= Timer0 overflow output

00

= Timer1 gate pin

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PIC16(L)F1946/47

TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCP1CON

CCP2CON

INTCON

PIE1

PIR1

TMR1H

TMR1L

TRISB

TRISC

T1CON

T1GCON

Legend:

*

GIE

P1M<1:0>

P2M<1:0>

TMR1GIE

PEIE

ADIE

DC1B<1:0>

DC2B<1:0>

TMR0IE

RCIE

INTE

TXIE

IOCIE

SSPIE

CCP1M<3:0>

CCP2M<3:0>

TMR0IF

CCP1IE

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

INTF

TMR2IE

TMR2IF

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2

TRISC7 TRISC6

TMR1CS<1:0>

TRISC5 TRISC4

T1CKPS<1:0>

TRISC3

T1OSCEN

TRISC2

T1SYNC

TRISB1

TRISC1

IOCIF

TMR1IE

TMR1IF

TRISB0

TRISC0

TMR1ON

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

T1GVAL T1GSS<1:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by the Timer1 module.

Page provides register information.

Register on Page

238

238

92

93

97

203

*

203

*

134

137

207

208

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PIC16(L)F1946/47

NOTES:

DS41414D-page 210

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PIC16(L)F1946/47

22.0

TIMER2/4/6 MODULES

There are up to three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also

Timer2/4/6).

Note:

The ‘x’ variable used in this section is used to designate Timer2, Timer4, or

Timer6. For example, TxCON references

T2CON, T4CON or T6CON. PRx references PR2, PR4 or PR6.

The Timer2/4/6 modules incorporate the following features:

• 8-bit Timer and Period registers (TMRx and PRx, respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16 and 1:64)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMRx match with PRx, respectively

• Optional use as the shift clock for the MSSPx modules (Timer2 only)

See Figure 22-1

for a block diagram of Timer2/4/6.

FIGURE 22-1: TIMER2/4/6 BLOCK DIAGRAM

F

OSC

/4

Prescaler

1:1, 1:4, 1:16, 1:64

2

TxCKPS<1:0>

TMRx

Reset

Comparator

PRx

EQ

Postscaler

1:1 to 1:16

4

TxOUTPS<3:0>

TMRx Output

Sets Flag bit TMRxIF

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22.1

Timer2/4/6 Operation

The clock input to the Timer2/4/6 modules is the system instruction clock (F

OSC

/4).

TMRx increments from 00h on each clock edge.

A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options.

These options are selected by the prescaler control bits,

TxCKPS<1:0> of the TxCON register. The value of

TMRx is compared to that of the Period register, PRx, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMRx to 00h on the next cycle and drives the output counter/postscaler (see

Section 22.2 “Timer2/4/6

Interrupt”

).

The TMRx and PRx registers are both directly readable and writable. The TMRx register is cleared on any device Reset, whereas the PRx register initializes to

FFh. Both the prescaler and postscaler counters are cleared on the following events:

• a write to the TMRx register

• a write to the TxCON register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• MCLR Reset

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

RESET

Instruction

Note:

TMRx is not cleared when TxCON is written.

22.2

Timer2/4/6 Interrupt

Timer2/4/6 can also generate an optional device interrupt. The Timer2/4/6 output signal (TMRx-to-PRx match) provides the input for the 4-bit counter/postscaler. This counter generates the TMRx match interrupt flag which is latched in TMRxIF of the

PIRx register. The interrupt is enabled by setting the

TMRx Match Interrupt Enable bit, TMRxIE of the PIEx register.

A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, TxOUTPS<3:0>, of the TxCON register.

22.3

Timer2/4/6 Output

The unscaled output of TMRx is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode.

Timer2 can be optionally used as the shift clock source for the MSSPx modules operating in SPI mode.

Additional information is provided in

Section 24.0

“Master Synchronous Serial Port (MSSP1 and

MSSP2) Module”

.

22.4

Timer2/4/6 Operation During Sleep

The Timer2/4/6 timers cannot be operated while the processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the processor is in Sleep mode.

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22.5

Register Definitions: Timer2 Control

REGISTER 22-1: TXCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER

bit 7

U-0

R/W-0/0 R/W-0/0 R/W-0/0

TxOUTPS<3:0>

R/W-0/0 R/W-0/0

TMRxON

R/W-0/0 R/W-0/0

TxCKPS<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6-3 bit 2 bit 1-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Unimplemented:

Read as ‘

0

TxOUTPS<3:0>:

Timerx Output Postscaler Select bits

1111

= 1:16 Postscaler

1110

= 1:15 Postscaler

1101

= 1:14 Postscaler

1100

= 1:13 Postscaler

1011

= 1:12 Postscaler

1010

= 1:11 Postscaler

1001

= 1:10 Postscaler

1000

= 1:9 Postscaler

0111

= 1:8 Postscaler

0110

= 1:7 Postscaler

0101

= 1:6 Postscaler

0100

= 1:5 Postscaler

0011

= 1:4 Postscaler

0010

= 1:3 Postscaler

0001

= 1:2 Postscaler

0000

= 1:1 Postscaler

TMRxON:

Timerx On bit

1

= Timerx is on

0

= Timerx is off

TxCKPS<1:0>:

Timer2-type Clock Prescale Select bits

11

= Prescaler is 64

10

= Prescaler is 16

01

= Prescaler is 4

00

= Prescaler is 1

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TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCP2CON

INTCON

PIE1

PIE3

PIR1

PIR3

PR2

PR4

PR6

T2CON

T4CON

T6CON

TMR2

TMR4

TMR6

Legend:

*

P2M<1:0>

GIE PEIE

DC2B<1:0>

TMR0IE INTE IOCIE

CCP2M<3:0>

TMR0IF INTF IOCIF

TMR1GIE

TMR1GIF

ADIE

CCP5IE

ADIF

CCP5IF

RCIE

CCP4IE

RCIF

CCP4IF

Timer2 Module Period Register

TXIE

CCP3IE

TXIF

CCP3IF

SSPIE

TMR6IE

SSPIF

TMR6IF

CCP1IE

CCP1IF

TMR2IE

TMR4IE

TMR2IF

TMR4IF

TMR1IE

TMR1IF

Timer4 Module Period Register

Timer6 Module Period Register

T2OUTPS<3:0>

T4OUTPS<3:0>

TMR2ON

TMR4ON

TMR6ON

T2CKPS<1:0>

T4CKPS<1:0>

T6CKPS<1:0> — T6OUTPS<3:0>

Holding Register for the 8-bit TMR2 Register

Holding Register for the 8-bit TMR4 Register

(1)

Holding Register for the 8-bit TMR6 Register

(1)

— = unimplemented location, read as ‘

0

’. Shaded cells are not used for Timer2 module.

Page provides register information.

Register on Page

238

92

93

95

97

99

211 *

211 *

211 *

213

213

213

211 *

211 *

211 *

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23.0

CAPTURE/COMPARE/PWM

MODULES

The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation

(PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The

PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.

This family of devices contains three Enhanced

Capture/Compare/PWM modules (ECCP1, ECCP2, and ECCP3) and two standard Capture/Compare/PWM modules (CCP4 and CCP5).

The Capture and Compare functions are identical for all five CCP modules (ECCP1, ECCP2, ECCP3, CCP4, and CCP5). The only differences between CCP modules are in the Pulse-Width Modulation (PWM) function. The standard PWM function is identical in modules, CCP4 and CCP5. In CCP modules ECCP1,

ECCP2, and ECCP3, the Enhanced PWM function has slight variations from one another. Full-Bridge ECCP modules have four available I/O pins while Half-Bridge

ECCP modules only have two available I/O pins. See

Table 23-1

for more information.

Note 1:

2:

In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules.

Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to ECCP1,

ECCP2, ECCP3, CCP4 and CCP5.

Register names, module signals, I/O pins, and bit names may use the generic designator 'x' to indicate the use of a numeral to distinguish a particular module, when required.

TABLE 23-1:

Device Name

PWM RESOURCES

PIC16(L)F1946/47

ECCP1

Enhanced PWM

Full-Bridge

ECCP2

Enhanced PWM

Full-Bridge

ECCP3

Enhanced PWM

Full-Bridge

CCP4

Standard PWM

CCP5

Standard PWM

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23.1

Capture Mode

The Capture mode function described in this section is available and identical for CCP modules ECCP1,

ECCP2, ECCP3, CCP4 and CCP5.

Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the

16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the Interrupt Request Flag bit

CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value.

Figure 23-1

shows a simplified diagram of the Capture operation.

23.1.1

CCP PIN CONFIGURATION

In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit.

Also, the CCPx pin function can be moved to alternative pins using the APFCON register. Refer to

Section 12.1 “Alternate Pin Function”

for more details.

Note:

If the CCPx pin is configured as an output, a write to the port can cause a capture condition.

FIGURE 23-1:

CCPx pin

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

Prescaler

1, 4, 16

Set Flag bit CCPxIF

(PIRx register)

CCPRxH CCPRxL and

Edge Detect

Capture

Enable

TMR1H TMR1L

CCPxM<3:0>

System Clock (F

OSC

)

23.1.2

TIMER1 MODE RESOURCE

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.

See

Section 21.0 “Timer1 Module with Gate Control”

for more information on configuring Timer1.

23.1.3

SOFTWARE INTERRUPT MODE

When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode.

Note:

Clocking Timer1 from the system clock

(F

OSC

) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (F

OSC

/4) or from an external clock source.

23.1.4

CCP PRESCALER

There are four prescaler settings specified by the

CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler.

Example 23-1

demonstrates the code to perform this function.

EXAMPLE 23-1: CHANGING BETWEEN

CAPTURE PRESCALERS

BANKSEL CCPxCON

CLRF

MOVLW

;Set Bank bits to point

;to CCPxCON

CCPxCON ;Turn CCP module off

NEW_CAPT_PS ;Load the W reg with

MOVWF CCPxCON

;the new prescaler

;move value and CCP ON

;Load CCPxCON with this

;value

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PIC16(L)F1946/47

23.1.5

CAPTURE DURING SLEEP

Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by the instruction clock (F

OSC

/4), or by an external clock source.

When Timer1 is clocked by F

OSC

/4, Timer1 will not increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

Capture mode will operate during Sleep when Timer1 is clocked by an external clock source.

23.1.6

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a

reset, see

Section 12.1 “Alternate Pin Function”

for

more information.

TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCPxCON

CCPRxL

CCPRxH

INTCON

PIE1

PIE2

PIE3

PIR1

PIR2

PIR3

T1CON

T1GCON

TMR1L

PxM<1:0>

TMR1GIE

OSFIE

TMR1GIF

OSFIF

(1)

DCxB<1:0>

Capture/Compare/PWM Register x Low Byte (LSB)

Capture/Compare/PWM Register x High Byte (MSB)

GIE PEIE

ADIE

C2IE

CCP5IE

ADIF

C2IF

CCP5IF

TMR1CS<1:0>

TMR1GE T1GPOL

TMR0IE

RCIE

C1IE

CCP4IE

RCIF

C1IF

CCP4IF

T1CKPS<1:0>

T1GTM

INTE

TXIE

EEIE

CCP3IE

TXIF

EEIF

CCP3IF

T1GSPM

IOCIE

SSPIE

BCLIE

TMR6IE

SSPIF

BCLIF

TMR6IF

T1OSCEN

T1GGO/DONE

CCPxM<3:0>

TMR0IF

CCP1IE

LCDIE

CCP1IF

LCDIF

T1SYNC

T1GVAL

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TMR1H

TRISA

TRISB

TRISC

TRISD

TRISE

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TRISA7

TRISB7

TRISC7

TRISD7

TRISA6

TRISB6

TRISC6

TRISD6

TRISA5

TRISB5

TRISC5

TRISD5

TRISA4

TRISB4

TRISC4

TRISD4

TRISA3

TRISB3

TRISC3

TRISD3

TRISE3

TRISA2

TRISB2

TRISC2

TRISD2

TRISE2

TRISA1

TRISB1

TRISC1

TRISD1

TRISE1

Legend:

Note 1:

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used by Capture mode.

Applies to ECCP modules only.

* Page provides register information.

INTF

TMR2IE

C3IE

IOCIF

TMR1IE

CCP2IE

TMR4IE

TMR2IF

C3IF

TMR4IF

TMR1IF

CCP2IF

— TMR1ON

T1GSS<1:0>

TRISA0

TRISB0

TRISC0

TRISD0

TRISE0

Register on Page

203 *

203 *

131

134

137

140

143

94

95

97

98

99

207

208

238

216 *

216 *

92

93

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PIC16(L)F1946/47

23.2

Compare Mode

The Compare mode function described in this section is available and identical for CCP modules ECCP1,

ECCP2, ECCP3, CCP4 and CCP5.

Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set.

All Compare modes can generate an interrupt.

Figure 23-2

shows a simplified diagram of the

Compare operation.

FIGURE 23-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

CCPxM<3:0>

Mode Select

CCPx

Pin

Set CCPxIF Interrupt Flag

4

(PIRx)

CCPRxH CCPRxL

Q S

R

Output

Logic Match

Comparator

TMR1H TMR1L

TRIS

Output Enable

Special Event Trigger

23.2.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by clearing the associated TRIS bit.

Also, the CCPx pin function can be moved to alternative pins using the APFCON register. Refer to

Section 12.1 “Alternate Pin Function”

for more details.

Note:

Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch.

23.2.2

TIMER1 MODE RESOURCE

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous

Counter mode.

See

Section 21.0 “Timer1 Module with Gate Control”

for more information on configuring Timer1.

Note:

Clocking Timer1 from the system clock

(F

OSC

) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (F

OSC

/4) or from an external clock source.

23.2.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> =

1010

), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register).

23.2.4

SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen

(CCPxM<3:0> = following:

1011

), the CCPx module does the

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

The CCPx module does not assert control of the CCPx pin in this mode.

The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This allows the CCPRxH,

CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1.

TABLE 23-3: SPECIAL EVENT TRIGGER

Device

PIC16(L)F1946/47

CCPx/ECCPx

CCP5

Refer to

Section 16.0 “Analog-to-Digital Converter

(ADC) Module”

for more information.

Note 1:

2:

The Special Event Trigger from the CCP module does not set interrupt flag bit

TMR1IF of the PIR1 register.

Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Special

Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.

2010-2012 Microchip Technology Inc.

DS41414D-page 218

23.2.5

COMPARE DURING SLEEP

The Compare mode is dependent upon the system clock (F

OSC

) for proper operation. Since F

OSC

is shut down during Sleep mode, the Compare mode will not function properly during Sleep.

PIC16(L)F1946/47

23.2.6

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a

reset, see

Section 12.1 “Alternate Pin Function”

for

more information.

TABLE 23-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCPxCON

CCPRxL

CCPRxH

INTCON

PIE1

PIE2

PIE3

PIR1

PIR2

PIR3

T1CON

T1GCON

TMR1L

PxM<1:0>

TMR1GIE

OSFIE

TMR1GIF

OSFIF

(1)

DCxB<1:0>

Capture/Compare/PWM Register x Low Byte (LSB)

Capture/Compare/PWM Register x High Byte (MSB)

GIE PEIE

ADIE

C2IE

CCP5IE

ADIF

C2IF

CCP5IF

TMR1CS<1:0>

TMR1GE T1GPOL

TMR0IE

RCIE

C1IE

CCP4IE

RCIF

C1IF

CCP4IF

T1CKPS<1:0>

T1GTM

INTE

TXIE

EEIE

CCP3IE

TXIF

EEIF

CCP3IF

T1GSPM

IOCIE

SSPIE

BCLIE

TMR6IE

SSPIF

BCLIF

TMR6IF

T1OSCEN

T1GGO/DONE

CCPxM<3:0>

TMR0IF

CCP1IE

LCDIE

CCP1IF

LCDIF

T1SYNC

T1GVAL

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TMR1H

TRISA

TRISB

TRISC

TRISD

TRISE

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TRISA7

TRISB7

TRISC7

TRISD7

TRISE7

TRISA6

TRISB6

TRISC6

TRISD6

TRISE6

TRISA5

TRISB5

TRISC5

TRISD5

TRISE5

TRISA4

TRISB4

TRISC4

TRISD4

TRISE4

TRISA3

TRISB3

TRISC3

TRISD3

TRISE3

TRISA2

TRISB2

TRISC2

TRISD2

TRISE2

TRISA1

TRISB1

TRISC1

TRISD1

TRISE1

Legend:

Note 1:

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used by Compare mode.

Applies to ECCP modules only.

* Page provides register information.

INTF

TMR2IE

C3IE

IOCIF

TMR1IE

CCP2IE

TMR4IE

TMR2IF

C31F

TMR4IF

TMR1IF

CCP2IF

— TMR1ON

T1GSS<1:0>

TRISA0

TRISB0

TRISC0

TRISD0

TRISE0

Register on Page

203 *

203 *

131

134

137

140

143

94

95

97

98

99

207

208

238

216 *

216 *

92

93

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PIC16(L)F1946/47

23.3

PWM Overview

Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The

PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined.

PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load.

The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied.

Figure 23-3 shows a typical waveform of the PWM

signal.

23.3.1

STANDARD PWM OPERATION

The standard PWM function described in this section is available and identical for CCP modules ECCP1,

ECCP2, ECCP3, CCP4 and CCP5.

The standard PWM mode generates a Pulse-Width modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers:

• PRx registers

• TxCON registers

• CCPRxL registers

• CCPxCON registers

Figure 23-4

shows a simplified block diagram of PWM operation.

Note 1:

2:

The corresponding TRIS bit must be cleared to enable the PWM output on the

CCPx pin.

Clearing the CCPxCON register will relinquish control of the CCPx pin.

FIGURE 23-3:

Period

CCP PWM OUTPUT SIGNAL

Pulse Width

TMRx = PRx

TMRx = CCPRxH:CCPxCON<5:4>

TMRx =

0

FIGURE 23-4:

Duty Cycle Registers

CCPRxL

SIMPLIFIED PWM BLOCK

DIAGRAM

CCPxCON<5:4>

CCPRxH

(2)

(Slave)

CCPx

Comparator

R Q

S

TMRx

(1)

TRIS

Comparator

Clear Timer, toggle CCPx pin and latch duty cycle

Note 1:

2:

PRx

The 8-bit timer TMRx register is concatenated with the 2-bit internal system clock (F

OSC

), or

2 bits of the prescaler, to create the 10-bit time base.

In PWM mode, CCPRxH is a read-only register.

2010-2012 Microchip Technology Inc.

DS41414D-page 220

23.3.2

SETUP FOR PWM OPERATION

The following steps should be taken when configuring the CCP module for standard PWM operation:

1.

2.

3.

4.

5.

6.

7.

Disable the CCPx pin output driver by setting the associated TRIS bit.

Timer2/4/6 resource selection:

• Select the Timer2/4/6 resource to be used for PWM generation by setting the

CxTSEL<1:0> bits in the CCPTMRSx register.

Load the PRx register with the PWM period value.

Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values.

Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value.

Configure and start Timer2/4/6:

• Clear the TMRxIF interrupt flag bit of the

PIRx register. See Note below.

• Configure the TxCKPS bits of the TxCON register with the Timer prescale value.

• Enable the Timer by setting the TMRxON bit of the TxCON register.

Enable PWM output pin:

• Wait until the Timer overflows and the

TMRxIF bit of the PIRx register is set. See

Note below.

• Enable the CCPx pin output driver by clearing the associated TRIS bit.

Note:

In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored.

23.3.3

TIMER2/4/6 TIMER RESOURCE

The PWM standard mode makes use of one of the 8-bit

Timer2/4/6 timer resources to specify the PWM period.

Configuring the CxTSEL<1:0> bits in the CCPTMRSx register selects which Timer2/4/6 timer is used.

23.3.4

PWM PERIOD

The PWM period is specified by the PRx register of

Timer2/4/6. The PWM period can be calculated using the formula of

Equation 23-1 .

EQUATION 23-1: PWM PERIOD

PWM Period =

 

PRx

+ 1

 

4

T

OSC

(TMRx Prescale Value)

Note 1:

T

OSC

= 1/F

OSC

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

When TMRx is equal to PRx, the following three events occur on the next increment cycle:

• TMRx is cleared

• The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.)

• The PWM duty cycle is latched from CCPRxL into

CCPRxH.

Note:

The Timer postscaler (see

Section 22.1

“Timer2/4/6 Operation”

) is not used in the

determination of the PWM frequency.

23.3.5

PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and

DCxB<1:0> bits of the CCPxCON register. The

CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs.

CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PRx and TMRx registers occurs). While using the PWM, the CCPRxH register is read-only.

Equation 23-2

is used to calculate the PWM pulse width.

Equation 23-3

is used to calculate the PWM duty cycle ratio.

EQUATION 23-2: PULSE WIDTH

Pulse Width =

CCPRxL:CCPxCON<5:4>

 

T

OSC

(TMRx Prescale Value)

EQUATION 23-3: DUTY CYCLE RATIO

Duty Cycle Ratio =

CCPRxL:CCPxCON<5:4>

-----------------------------------------------------------------------

4 PRx + 1

The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation.

The 8-bit timer TMRx register is concatenated with either the 2-bit internal system clock (F

OSC

), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2/4/6 prescaler is set to 1:1.

When the 10-bit time base matches the CCPRxH and

2-bit latch, then the CCPx pin is cleared (see

Figure 23-4

).

DS41414D-page 221

PIC16(L)F1946/47

23.3.6

PWM RESOLUTION

The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles.

The maximum PWM resolution is 10 bits when PRx is

255. The resolution is a function of the PRx register

value as shown by Equation 23-4

.

EQUATION 23-4: PWM RESOLUTION

Resolution = log

4 PRx log 2

+ 1

 

Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged.

TABLE 23-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F

OSC

= 32 MHz)

PWM Frequency

Timer Prescale

PRx Value

Maximum Resolution (bits)

1.95 kHz

16

0xFF

10

7.81 kHz

4

0xFF

10

31.25 kHz

1

0xFF

10

125 kHz

1

0x3F

8

250 kHz

1

0x1F

7

333.3 kHz

1

0x17

6.6

TABLE 23-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F

OSC

= 20 MHz)

PWM Frequency

Timer Prescale

PRx Value

Maximum Resolution (bits)

1.22 kHz

16

0xFF

10

4.88 kHz

4

0xFF

10

19.53 kHz

1

0xFF

10

78.12 kHz

1

0x3F

8

156.3 kHz

1

0x1F

7

208.3 kHz

1

0x17

6.6

TABLE 23-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F

OSC

= 8 MHz)

PWM Frequency

Timer Prescale

PRx Value

Maximum Resolution (bits)

1.22 kHz

16

0x65

8

4.90 kHz

4

0x65

8

19.61 kHz

1

0x65

8

76.92 kHz

1

0x19

6

153.85 kHz

1

0x0C

5

200.0 kHz

1

0x09

5

DS41414D-page 222

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

23.3.7

OPERATION IN SLEEP MODE

In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value.

When the device wakes up, TMRx will continue from its previous state.

23.3.8

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See

Section 5.0 “Oscillator Module (With Fail-Safe

Clock Monitor)”

for additional details.

23.3.9

EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

23.3.10

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a

reset, see

Section 12.1 “Alternate Pin Function”

for

more information.

TABLE 23-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCPxCON

CCPTMRS0

PxM<1:0>

(1)

C4TSEL<1:0>

CCPTMRS1

INTCON

PIE1

PIE2

PIE3

PIR1

PIR2

PIR3

PR2

PR4

PR6

T2CON

— —

GIE PEIE

TMR1GIE

OSFIE

TMR1GIF

OSFIF

ADIE

C2IE

CCP5IE

ADIF

C2IF

CCP5IF

Timer2 Period Register

Timer4Period Register

Timer6 Period Register

DCxB<1:0>

C3TSEL<1:0>

TMR0IE

RCIE

C1IE

CCP4IE

RCIF

C1IF

CCP4IF

INTE

TXIE

EEIE

CCP3IE

TXIF

EEIF

CCP3IF

IOCIE

SSPIE

BCLIE

TMR6IE

SSPIF

BCLIF

TMR6IF

CCPxM<3:0>

C2TSEL<1:0>

TMR0IF

CCP1IE

LCDIE

CCP1IF

LCDIF

T2OUTPS<3:0> TMR2ON

T4CON

T6CON

T4OUTPS<3:0>

T6OUTPS<3:0>

TMR4ON

TMR6ON

TMR2

TMR4

Timer2 Module Register

Timer4 Module Register

TMR6

TRISA

TRISB

TRISC

TRISD

TRISE

Timer6 Module Register

TRISA7

TRISB7

TRISC7

TRISD7

TRISE7

TRISA6

TRISB6

TRISC6

TRISD6

TRISE6

TRISA5

TRISB5

TRISC5

TRISD5

TRISE5

TRISA4

TRISB4

TRISC4

TRISD4

TRISE4

TRISA3

TRISB3

TRISC3

TRISD3

TRISE3

TRISA2

TRISB2

TRISC2

TRISD2

TRISE2

Legend:

Note 1:

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used by the PWM.

Applies to ECCP modules only.

* Page provides register information.

C1TSEL<1:0>

C5TSEL<1:0>

INTF IOCIF

TMR2IE

C3IE

TMR4IE

TMR2IF

C3IF

TMR4IF

T2CKPS<:0>1

T4CKPS<:0>1

T6CKPS<:0>1

TRISA1

TRISB1

TRISC1

TRISD1

TRISE1

TMR1IE

CCP2IE

TMR1IF

CCP2IF

TRISA0

TRISB0

TRISC0

TRISD0

TRISE0

Register on Page

99

211

*

211

*

211

*

94

95

97

98

213

238

239

239

92

93

213

131

134

137

140

143

213

211

*

211

*

211

*

2010-2012 Microchip Technology Inc.

DS41414D-page 223

PIC16(L)F1946/47

23.4

PWM (Enhanced Mode)

The enhanced PWM function described in this section is available for CCP modules ECCP1, ECCP2 and

ECCP3, with any differences between modules noted.

The enhanced PWM mode generates a Pulse-Width

Modulation (PWM) signal on up to four different output pins with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers:

• PRx registers

• TxCON registers

• CCPRxL registers

• CCPxCON registers

The ECCP modules have the following additional PWM registers which control Auto-shutdown, Auto-restart,

Dead-band Delay and PWM Steering modes:

• CCPxAS registers

• PSTRxCON registers

• PWMxCON registers

The enhanced PWM module can generate the following five PWM Output modes:

• Single PWM

• Half-Bridge PWM

• Full-Bridge PWM, Forward Mode

• Full-Bridge PWM, Reverse Mode

• Single PWM with PWM Steering Mode

To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured appropriately.

The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD. The polarity of the

PWM pins is configurable and is selected by setting the

CCPxM bits in the CCPxCON register appropriately.

Figure 23-5

shows an example of a simplified block diagram of the Enhanced PWM module.

Table 23-9

shows the pin assignments for various

Enhanced PWM modes.

Note 1:

2:

3:

4:

The corresponding TRIS bit must be cleared to enable the PWM output on the

CCPx pin.

Clearing the CCPxCON register will relinquish control of the CCPx pin.

Any pin not used in the enhanced PWM mode is available for alternate pin functions, if applicable.

To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal.

FIGURE 23-5:

Duty Cycle Registers

CCPRxL

EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

DCxB<1:0>

PxM<1:0>

2

CCPxM<3:0>

4

CCPx/PxA

CCPx/PxA

TRISx

CCPRxH (Slave)

Comparator

R Q

PxB

Output

Controller

PxC

TRISx

PxB

PxC

TMRx

(1)

S

TRISx

PxD

Comparator

PxD

Clear Timer, toggle PWM pin and latch duty cycle

PRx

PWMxCON

TRISx

Note 1:

The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base.

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PIC16(L)F1946/47

TABLE 23-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

ECCP Mode PxM<1:0> CCPx/PxA

Single

00

Yes

(1)

Half-Bridge

10

Yes

Full-Bridge, Forward

Full-Bridge, Reverse

Note 1:

01

11

Yes

Yes

PWM Steering enables outputs in Single mode.

PxB

Yes

(1)

Yes

Yes

Yes

PxC

Yes

(1)

No

Yes

Yes

PxD

Yes

(1)

No

Yes

Yes

FIGURE 23-6:

PxM<1:0>

00

(Single Output)

10

01

11

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)

PRX+1

Signal 0

Pulse

Width

Period

(Half-Bridge)

PxA Modulated

PxA Modulated

PxB Modulated

PxA Active

PxB Inactive

PxC Inactive

PxD Modulated

PxA Inactive

PxB Modulated

PxC Active

PxD Inactive

Delay

Delay

Relationships:

• Period = 4 * T

OSC

* (PRx + 1) * (TMRx Prescale Value)

• Pulse Width = T

OSC

* (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)

• Delay = 4 * T

OSC

* (PWMxCON<6:0>)

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

FIGURE 23-7:

PxM<1:0>

EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

PRx+1

Signal

0

Pulse

Width

Period

00

(Single Output)

10

01

11

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

PxA Modulated

PxA Modulated

PxB Modulated

PxA Active

PxB Inactive

PxC Inactive

PxD Modulated

PxA Inactive

PxB Modulated

PxC Active

PxD Inactive

Delay

Delay

Relationships:

• Period = 4 * T

OSC

* (PRx + 1) * (TMRx Prescale Value)

• Pulse Width = T

OSC

* (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)

• Delay = 4 * T

OSC

* (PWMxCON<6:0>)

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2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

23.4.1

HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see

Figure 23-9

). This mode can be used for Half-Bridge

applications, as shown in Figure 23-9

, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.

In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in

Half-Bridge power devices. The value of the PDC<6:0> bits of the PWMxCON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See

Section 23.4.5 “Programmable Dead-Band Delay

Mode”

for more details of the dead-band delay

operations.

FIGURE 23-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

Since the PxA and PxB outputs are multiplexed with the

PORT data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs.

FIGURE 23-8:

Period

EXAMPLE OF

HALF-BRIDGE PWM

OUTPUT

Period

Pulse Width

PxA

(2)

td td

PxB

(2)

(1) (1) (1)

td = Dead-Band Delay

Note 1:

2:

At this time, the TMRx register is equal to the

PRx register.

Output signals are shown as active-high.

PxA

+

-

Load

FET

Driver

PxB

+

-

Half-Bridge Output Driving a Full-Bridge Circuit

V+

PxA

PxB

FET

Driver

FET

Driver

Load

FET

Driver

FET

Driver

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23.4.2

FULL-BRIDGE MODE

In Full-Bridge mode, all four pins are used as outputs.

An example of Full-Bridge application is shown in

Figure 23-10

.

In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be

driven to their inactive state as shown in Figure 23-11 .

In the Reverse mode, PxC is driven to its active state, pin

PxB is modulated, while PxA and PxD will be driven to

their inactive state as shown Figure 23-11

.

PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs.

FIGURE 23-10: EXAMPLE OF FULL-BRIDGE APPLICATION

V+

QA

FET

Driver

PxA

Load

PxB

FET

Driver

PxC

QB

V-

PxD

QC

FET

Driver

QD

FET

Driver

DS41414D-page 228

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

FIGURE 23-11:

Forward Mode

EXAMPLE OF FULL-BRIDGE PWM OUTPUT

Period

PxA

(2)

Pulse Width

PxB

(2)

PxC

(2)

PxD

(2)

(1)

Reverse Mode

Period

Pulse Width

PxA

(2)

PxB

(2)

PxC

(2)

PxD

(2)

(1)

Note 1:

2:

At this time, the TMRx register is equal to the PRx register.

Output signal is shown as active-high.

(1)

(1)

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23.4.2.1

Direction Change in Full-Bridge

Mode

In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle.

A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register. The following sequence occurs four Timer cycles prior to the end of the current PWM period:

• The modulated outputs (PxB and PxD) are placed in their inactive state.

• The associated unmodulated outputs (PxA and

PxC) are switched to drive in the opposite direction.

• PWM modulation resumes at the beginning of the next period.

See Figure 23-12 for an illustration of this sequence.

FIGURE 23-12:

Signal

The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. This situation occurs when both of the following conditions are true:

1.

2.

The direction of the PWM output changes when the duty cycle of the output is at or near 100%.

The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time.

Figure 23-13

shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output PxA and

PxD become inactive, while output PxC becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see

Figure 23-10

) for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward.

If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are:

1.

2.

Reduce PWM duty cycle for one PWM period before changing directions.

Use switch drivers that can drive the switches off faster than they can drive them on.

Other options to prevent shoot-through current may exist.

EXAMPLE OF PWM DIRECTION CHANGE

Period

(1)

Period

PxA (Active-High)

PxB (Active-High)

Pulse Width

PxC (Active-High)

PxD (Active-High)

(2)

Pulse Width

Note 1:

2:

The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.

When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

FIGURE 23-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period t1

Reverse Period

PxA

PxB

PxC

PxD

External Switch C

External Switch D

Potential

Shoot-Through Current

PW

T

ON

T

OFF

PW

T = T

OFF

– T

ON

Note 1:

2:

3:

All signals are shown as active-high.

T

ON

is the turn on delay of power switch QC and its driver.

T

OFF

is the turn off delay of power switch QD and its driver.

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23.4.3

ENHANCED PWM

AUTO-SHUTDOWN MODE

The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application.

The auto-shutdown sources are selected using the

CCPxAS<2:0> bits of the CCPxAS register. A shutdown event may be generated by:

• A logic ‘

0

’ on the INT pin

• A logic ‘

0

’ on a Comparator (async_CxOUT) output

A shutdown condition is indicated by the CCPxASE

(Auto-Shutdown Event Status) bit of the CCPxAS register. If the bit is a ‘

0

’, the PWM pins are operating normally. If the bit is a ‘

1

’, the PWM outputs are in the shutdown state.

When a shutdown event occurs, two things happen:

The CCPxASE bit is set to ‘

1

’. The CCPxASE will remain set until cleared in firmware or an auto-restart

occurs (see

Section 23.4.4 “Auto-Restart Mode”

).

The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state of each pin pair is determined by the PSSxAC and

PSSxBD bits of the CCPxAS register. Each pin pair may be placed into one of three states:

• Drive logic ‘

1

• Drive logic ‘

0

• Tri-state (high-impedance)

Note 1:

2:

The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist.

Writing to the CCPxASE bit of the

CCPxAS register is disabled while an auto-shutdown condition persists.

3:

4:

Once the auto-shutdown condition has been removed and the PWM restarted

(either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period.

Prior to an auto-shutdown event caused by a comparator output or INT pin event, a software shutdown can be triggered in firmware by setting the CCPxASE bit of the CCPxAS register to ‘

1

’. The

Auto-Restart feature tracks the active status of a shutdown caused by a comparator output or INT pin event only.

If it is enabled at this time, it will immediately clear this bit and restart the

ECCP module at the beginning of the next PWM period.

DS41414D-page 232

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

FIGURE 23-14:

PWM Activity

PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN =

0

)

Timer

Overflow

Missing Pulse

(Auto-Shutdown)

Timer

Overflow

Timer

Overflow

Missing Pulse

(CCPxASE not clear)

Timer

Overflow

Timer

Overflow

PWM Period

Start of

PWM Period

Shutdown Event

CCPxASE bit

Shutdown

Event Occurs

Shutdown

Event Clears

PWM

Resumes

CCPxASE

Cleared by

Firmware

23.4.4

AUTO-RESTART MODE

The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register.

If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the

CCPxASE bit will be cleared via hardware and normal operation will resume.

FIGURE 23-15:

PWM Activity

PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN =

1

)

Timer

Overflow

Missing Pulse

(Auto-Shutdown)

Timer

Overflow

Timer

Overflow

Missing Pulse

(CCPxASE not clear)

Timer

Overflow

Timer

Overflow

PWM Period

Start of

PWM Period

Shutdown Event

CCPxASE bit

Shutdown

Event Occurs

Shutdown

Event Clears

PWM

Resumes

CCPxASE

Cleared by

Hardware

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23.4.5

PROGRAMMABLE DEAD-BAND

DELAY MODE

In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.

During this brief interval, a very high current

(

shoot-through current

) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off.

In Half-Bridge mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See

Figure 23-16

for illustration. The lower seven bits of the associated

PWMxCON register ( Register 23-5

) sets the delay period in terms of microcontroller instruction cycles

(T

CY

or 4 T

OSC

).

FIGURE 23-16:

Period

EXAMPLE OF

HALF-BRIDGE PWM

OUTPUT

Period

Pulse Width

PxA

(2)

td td

PxB

(2)

(1) (1) (1)

td = Dead-Band Delay

Note 1:

2:

At this time, the TMRx register is equal to the

PRx register.

Output signals are shown as active-high.

FIGURE 23-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

PxA

+

V

-

Load

FET

Driver

PxB

+

V

-

V-

2010-2012 Microchip Technology Inc.

DS41414D-page 234

23.4.6

PWM STEERING MODE

In Single Output mode, PWM steering allows any of the

PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins.

Once the Single Output mode is selected

(CCPxM<3:2> =

11

and PxM<1:0> =

00

of the

CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx<D:A> bits of the

PSTRxCON register, as shown in

Table 23-9 .

Note:

The associated TRIS bits must be set to output (‘

0

’) to enable the pin output driver in order to see the PWM signal on the pin.

While the PWM Steering mode is active, CCPxM<1:0> bits of the CCPxCON register select the PWM output polarity for the Px<D:A> pins.

The PWM auto-shutdown operation also applies to

PWM Steering mode as described in

Section 23.4.3

“Enhanced PWM Auto-shutdown mode”

. An

auto-shutdown event will only affect pins that have

PWM outputs enabled.

FIGURE 23-18: SIMPLIFIED STEERING

BLOCK DIAGRAM

STRxA

PxA Signal

CCPxM1

PORT Data

STRxB

1

0

TRIS

PxA pin

CCPxM0

PORT Data

STRxC

1

0

TRIS

PxB pin

CCPxM1

PORT Data

STRxD

1

0

TRIS

PxC pin

CCPxM0 1

PxD pin

PORT Data

0

TRIS

Note 1:

2:

Port outputs are configured as shown when the CCPxCON register bits PxM<1:0> =

00 and CCPxM<3:2> = 11.

Single PWM output requires setting at least one of the STRx bits.

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PIC16(L)F1946/47

23.4.6.1

Steering Synchronization

The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘

0

’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the Px<D:A> pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.

When the STRxSYNC bit is ‘

1

’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform.

Figures 23-19 and 23-20 illustrate the timing diagrams

of the PWM steering depending on the STRxSYNC setting.

23.4.7

START-UP CONSIDERATIONS

When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins.

The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output polarities must be selected before the PWM pin output

FIGURE 23-19:

drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits.

The PxA, PxB, PxC and PxD output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMRxIF bit of the PIRx register being set as the second PWM period begins.

Note:

When the microcontroller is released from

Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s).

EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC =

0)

PWM Period

PWM

STRx

P1<D:A>

PORT Data PORT Data

P1n = PWM

FIGURE 23-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(STRxSYNC =

1)

PWM

STRx

P1<D:A>

PORT Data

PORT Data

P1n = PWM

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23.4.8

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a

reset, see

Section 12.1 “Alternate Pin Function”

for

more information.

TABLE 23-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CCPxCON

CCPxAS

CCPTMRS0

CCPTMRS1

INTCON

PIE1

PIE2

PxM<1:0>

CCPxASE

(1)

C4TSEL<1:0>

— —

GIE PEIE

TMR1GIE

OSFIE

ADIE

C2IE

PIE3

PIR1

PIR2

PIR3

PR2

PR4

PR6

PSTRxCON

PWMxCON

T2CON

TMR1GIF

OSFIF

Timer2 Period Register

Timer4 Period Register

Timer6 Period Register

— —

PxRSEN

CCP5IE

ADIF

C2IF

CCP5IF

DCxB<1:0>

CCPxAS<2:0>

C3TSEL<1:0>

TMR0IE

RCIE

C1IE

INTE

TXIE

EEIE

CCP4IE

RCIF

C1IF

CCP4IF

CCP3IE

TXIF

EEIF

CCP3IF

— STRxSYNC STRxD

PxDC<6:0>

T2OUTPS<3:0>

IOCIE

SSPIE

BCLIE

TMR6IE

SSPIF

BCLIF

TMR6IF

CCPxM<3:0>

PSSxAC<1:0>

C2TSEL<1:0>

TMR0IF

CCP1IE

LCDIE

CCP1IF

LCDIF

STRxC

TMR2ON

PSSxBD<1:0>

C1TSEL<1:0>

C5TSEL<1:0>

INTF

TMR2IE

C3IE

TMR4IE

TMR2IF

C3IF

TMR4IF

STRxB

IOCIF

TMR1IE

CCP2IE

TMR1IF

CCP2IF

STRxA

T2CKPS<:0>1

T4CKPS<:0>1

T6CKPS<:0>1

T4CON

T6CON

T4OUTPS<3:0>

T6OUTPS<3:0>

TMR4ON

TMR6ON

TMR2

TMR4

Timer2 Module Register

Timer4 Module Register

TMR6 Timer6 Module Register

TRISA

TRISB

TRISC

TRISD

TRISA7

TRISB7

TRISC7

TRISD7

TRISA6

TRISB6

TRISC6

TRISD6

TRISA5

TRISB5

TRISC5

TRISD5

TRISA4

TRISB4

TRISC4

TRISD4

TRISA3

TRISB3

TRISC3

TRISD3

TRISA2

TRISB2

TRISC2

TRISD2

TRISE — — — — TRISE3 TRISE2

Legend:

Note 1:

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used by the PWM.

Applies to ECCP modules only.

* Page provides register information.

TRISA1

TRISB1

TRISC1

TRISD1

TRISE1

TRISA0

TRISB0

TRISC0

TRISD0

TRISE0

Register on Page

238

240

99

211

*

211

*

211

*

94

95

97

98

239

239

92

93

242

241

213

213

213

211

*

211

*

211

*

131

134

137

140

143

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PIC16(L)F1946/47

23.5

Register Definitions: ECCP Control

REGISTER 23-1: CCPxCON: CCPx CONTROL REGISTER

bit 7

R/W-00 R/W-0/0

PxM<1:0>

(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

DCxB<1:0> CCPxM<3:0>

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-4 bit 3-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Reset

PxM<1:0>:

Enhanced PWM Output Configuration bits

(1)

Capture mode:

Unused

Compare mode:

Unused

If CCPxM<3:2> =

00

,

01

,

10

: xx

= PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins

If CCPxM<3:2> =

11

:

11

=

10

=

01

=

00

=

Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive

Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins

Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive

Single output; PxA modulated; PxB, PxC, PxD assigned as port pins

DCxB<1:0>:

PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

CCPxM<3:0>:

ECCPx Mode Select bits

1011

= Compare mode: Special Event Trigger (ECCPx resets Timer, sets CCPxIF bit, starts A/D conversion if

A/D module is enabled)

(1)

1010

= Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state

1001

= Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)

1000

= Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)

0111

= Capture mode: every 16th rising edge

0110

= Capture mode: every 4th rising edge

0101

= Capture mode: every rising edge

0100

= Capture mode: every falling edge

0011

= Reserved

0010

= Compare mode: toggle output on match

0001

= Reserved

0000

= Capture/Compare/PWM off (resets ECCPx module)

Note 1:

CCP4/CCP5 only:

11xx

= PWM mode

ECCP1/ECCP2/ECCP3 only:

1111

= PWM mode: PxA, PxC active-low; PxB, PxD active-low

1110

= PWM mode: PxA, PxC active-low; PxB, PxD active-high

1101

= PWM mode: PxA, PxC active-high; PxB, PxD active-low

1100

= PWM mode: PxA, PxC active-high; PxB, PxD active-high

These bits are not implemented on CCP<5:4>.

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PIC16(L)F1946/47

REGISTER 23-2: CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER 0

R/W-0/0 R/W-0/0

C4TSEL<1:0> bit 7

R/W-0/0 R/W-0/0

C3TSEL<1:0>

R/W-0/0 R/W-0/0

C2TSEL<1:0>

R/W-0/0 R/W-0/0

C1TSEL<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5-4 bit 3-2 bit 1-0

C4TSEL<1:0>:

CCP4 Timer Selection

11

= Reserved

10

= CCP4 is based off Timer 6 in PWM Mode

01

= CCP4 is based off Timer 4 in PWM Mode

00

= CCP4 is based off Timer 2 in PWM Mode

C3TSEL<1:0>:

CCP3 Timer Selection

11

= Reserved

10

= CCP3 is based off Timer 6 in PWM Mode

01

= CCP3 is based off Timer 4 in PWM Mode

00

= CCP3 is based off Timer 2 in PWM Mode

C2TSEL<1:0>:

CCP2 Timer Selection

11

= Reserved

10

= CCP2 is based off Timer 6 in PWM Mode

01

= CCP2 is based off Timer 4 in PWM Mode

00

= CCP2 is based off Timer 2 in PWM Mode

C1TSEL<1:0>:

CCP1 Timer Selection

11

= Reserved

10

= CCP1 is based off Timer 6 in PWM Mode

01

= CCP1 is based off Timer 4 in PWM Mode

00

= CCP1 is based off Timer 2 in PWM Mode

REGISTER 23-3: CCPTMRS1: PWM TIMER SELECTION CONTROL REGISTER 1

bit 7

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0/0 R/W-0/0

C5TSEL<1:0> bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-2 bit 1-0

Unimplemented:

Read as ‘

0

C5TSEL<1:0>:

CCP5 Timer Selection

11

= Reserved

10

= CCP5 is based off Timer 6 in PWM Mode

01

= CCP5 is based off Timer 4 in PWM Mode

00

= CCP5 is based off Timer 2 in PWM Mode

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

REGISTER 23-4:

R/W-0/0

CCPxASE bit 7

CCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER

R/W-0/0 R/W-0/0

CCPxAS<2:0>

R/W-0/0 R/W-0/0 R/W-0/0

PSSxAC<1:0>

R/W-0/0 R/W-0/0

PSSxBD<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-4 bit 3-2 bit 1-0

CCPxASE:

CCPx Auto-Shutdown Event Status bit

1

= A shutdown event has occurred; CCPx outputs are in shutdown state

0

= CCPx outputs are operating

CCPxAS<2:0>:

CCPx Auto-Shutdown Source Select bits

111

= V

IL

on INT pin or Comparator C1 or Comparator C2 high

(1, 2)

110

= V

IL

on INT pin or Comparator C2 high

(1, 2)

101

= V

IL

on INT pin or Comparator C1 high

(1)

100

= V

IL

on INT pin

011

= Either Comparator C1 or C2 high

(1, 2)

010

= Comparator C2 output high

(1, 2)

001

= Comparator C1 output high

(1)

000

= Auto-shutdown is disabled

PSSxAC<1:0>:

Pins PxA and PxC Shutdown State Control bits

1x

= Pins PxA and PxC tri-state

01

= Drive pins PxA and PxC to ‘

1

00

= Drive pins PxA and PxC to ‘

0

PSSxBD<1:0>:

Pins PxB and PxD Shutdown State Control bits

1x

= Pins PxB and PxD tri-state

01

= Drive pins PxB and PxD to ‘

1

00

= Drive pins PxB and PxD to ‘

0

Note 1:

2:

If CxSYNC is enabled, the shutdown will be delayed by Timer1.

For PIC16F1946/47 devices in ECCP3 mode, CCPxAS uses C3 instead of C2.

DS41414D-page 240

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PIC16(L)F1946/47

REGISTER 23-5:

R/W-0/0

PxRSEN bit 7

PWMxCON: ENHANCED PWM CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

PxDC<6:0>

R/W-0/0 R/W-0/0 R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-0

PxRSEN:

PWM Restart Enable bit

1

= Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically

0

= Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM

PxDC<6:0>:

PWM Delay Count bits

PxDCx = Number of F

OSC

/4 (4 * T

OSC

) cycles between the scheduled time when a PWM signal

should

transition active and the

actual

time it transitions active

Note 1:

Bit resets to ‘

0

’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled.

2010-2012 Microchip Technology Inc.

DS41414D-page 241

PIC16(L)F1946/47

REGISTER 23-6:

bit 7

U-0

PSTRxCON: PWM STEERING CONTROL REGISTER

(1)

U-0

U-0

R/W-0/0

STRxSYNC

R/W-0/0

STRxD

R/W-0/0 R/W-0/0

STRxC STRxB

R/W-1/1

STRxA bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0

Unimplemented:

Read as ‘

0

STRxSYNC:

Steering Sync bit

1

= Output steering update occurs on next PWM period

0

= Output steering update occurs at the beginning of the instruction cycle boundary

STRxD:

Steering Enable bit D

1

= PxD pin has the PWM waveform with polarity control from CCPxM<1:0>

0

= PxD pin is assigned to port pin

STRxC:

Steering Enable bit C

1

= PxC pin has the PWM waveform with polarity control from CCPxM<1:0>

0

= PxC pin is assigned to port pin

STRxB:

Steering Enable bit B

1

= PxB pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxB pin is assigned to port pin

STRxA:

Steering Enable bit A

1

= PxA pin has the PWM waveform with polarity control from CCPxM<1:0>

0

= PxA pin is assigned to port pin

Note 1:

The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> =

PxM<1:0> =

00

.

11

and

DS41414D-page 242

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PIC16(L)F1946/47

24.0

MASTER SYNCHRONOUS

SERIAL PORT (MSSP1 AND

MSSP2) MODULE

24.1

Master SSPx (MSSPx) Module

Overview

The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSPx module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I

2

C™)

The SPI interface supports the following modes and features:

• Master mode

• Slave mode

• Clock Parity

• Slave Select Synchronization (Slave mode only)

• Daisy-chain connection of slave devices

Figure 24-1

is a block diagram of the SPI interface module.

FIGURE 24-1: MSSPX BLOCK DIAGRAM (SPI MODE)

Read

SSPxBUF Reg

Data Bus

Write

SDIx

SDOx bit 0

SSPxSR Reg

Shift

Clock

SSx

SCKx

SSx Control

Enable

Edge

Select

2 (CKP, CKE)

Clock Select

Edge

Select

SSPM<3:0>

4

( )

2

Prescaler

4, 16, 64

T

OSC

TRIS bit

Baud Rate

Generator

(SSPxADD)

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PIC16(L)F1946/47

The I

2

C interface supports the following modes and features:

• Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited Multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

• Clock stretching

• Bus collision detection

• General call address matching

• Address masking

• Address Hold and Data Hold modes

• Selectable SDAx hold times

Figure 24-2

is a block diagram of the I ule in Master mode.

Figure 24-3

2

C interface mod-

is a diagram of the I

2

C interface module in Slave mode.

The PIC16F1947 has two MSSP modules, MSSP1 and

MSSP2, each module operating independently from the other.

Note 1:

2:

In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names.

SSP1CON1 and SSP1CON2 registers control different operational aspects of the same module, while SSP1CON1 and

SSP2CON1 control the same features for two different modules.

Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or

MSSP2. Register names, module I/O signals, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module when required.

FIGURE 24-2:

SDAx

MSSPX BLOCK DIAGRAM (I

2

C™ MASTER MODE)

SDAx in

Read

Internal data bus

Write

SSPxBUF

MSb

SSPxSR

LSb

Shift

Clock

Start bit, Stop bit,

Acknowledge

Generate (SSPxCON2)

SCLx

[SSPM 3:0]

Baud Rate

Generator

(SSPxADD)

SCLx in

Bus Collision

Start bit detect,

Stop bit detect

Write collision detect

Clock arbitration

State counter for end of XMIT/RCV

Address Match detect

Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV

Reset SEN, PEN (SSPxCON2)

Set SSPxIF, BCLxIF

2010-2012 Microchip Technology Inc.

DS41414D-page 244

FIGURE 24-3:

PIC16(L)F1946/47

MSSPx BLOCK DIAGRAM (I

2

C™ SLAVE MODE)

SCLx

SDAx

Read

Internal

Data Bus

Write

SSPxBUF Reg

Shift

Clock

MSb

SSPxSR Reg

LSb

SSPxMSK Reg

Match Detect

SSPxADD Reg

Addr Match

Start and

Stop bit Detect

Set, Reset

S, P bits

(SSPxSTAT Reg)

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PIC16(L)F1946/47

24.2

SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select.

The SPI bus specifies four signal connections:

• Serial Clock (SCKx)

• Serial Data Out (SDOx)

• Serial Data In (SDIx)

• Slave Select (SSx)

Figure 24-1

shows the block diagram of the MSSPx module when operating in SPI Mode.

The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device.

Figure 24-4

shows a typical connection between a master device and multiple slave devices.

The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected.

Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least

Significant bit (LSb) is shifted into the same register.

Figure 24-5

shows a typical connection between two processors configured as master and slave devices.

Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock.

The master device transmits information out on its

SDOx output pin which is connected to, and received by, the slave’s SDIx input pin. The slave device transmits information out on its SDOx output pin, which is connected to, and received by, the master’s SDIx input pin.

To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity.

The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register.

During each SPI clock cycle, a full duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on

DS41414D-page 246 its SDOx pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDOx pin) and the master device is reading this bit and saving it as the LSb of its shift register.

After 8 bits have been shifted out, the master and slave have exchanged register values.

If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission:

• Master sends useful data and slave sends dummy data.

• Master sends useful data and slave sends useful data.

• Master sends dummy data and slave sends useful data.

Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave.

Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own.

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

FIGURE 24-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION

SCKx

SPI Master

SDOx

SDIx

General I/O

General I/O

General I/O

SCKx

SDIx

SDOx

SSx

SPI Slave

#1

SCKx

SDIx

SDOx

SSx

SPI Slave

#2

SCKx

SDIx

SDOx

SSx

SPI Slave

#3

24.2.1 SPI MODE REGISTERS

The MSSPx module has five registers for SPI mode operation. These are:

• MSSPx STATUS register (SSPxSTAT)

• MSSPx Control Register 1 (SSPxCON1)

• MSSPx Control Register 3 (SSPxCON3)

• MSSPx Data Buffer register (SSPxBUF)

• MSSPx Address register (SSPxADD)

• MSSPx Shift register (SSPxSR)

(Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and

STATUS registers in SPI mode operation. The

SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write.

In SPI master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in

Section 24.7 “Baud Rate Generator”

.

SSPxSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the

SSPxSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read.

In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and

SSPxSR.

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24.2.2 SPI MODE OPERATION

When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCKx is the clock output)

• Slave mode (SCKx is the clock input)

• Clock Polarity (Idle state of SCKx)

• Data Input Sample Phase (middle or end of data output time)

• Clock Edge (output data on rising/falling edge of

SCKx)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port, SSPx Enable bit, SSPEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the

SSPxCONx registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows:

• SDIx must have corresponding TRIS bit set

• SDOx must have corresponding TRIS bit cleared

• SCKx (Master mode) must have corresponding

TRIS bit cleared

• SCKx (Slave mode) must have corresponding

TRIS bit set

• SSx must have corresponding TRIS bit set

FIGURE 24-5:

Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.

The MSSPx consists of a transmit/receive shift register

(SSPxSR) and a buffer register (SSPxBUF). The

SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the

8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit,

BF of the SSPxSTAT register, and the interrupt flag bit,

SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPxCON1 register, will be set. User software must clear the

WCOL bit to allow the following write(s) to the

SSPxBUF register to complete successfully.

When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF.

The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the

SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSPx interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur.

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> =

00xx

=

1010

SDOx

Serial Input Buffer

(BUF)

SDIx

SPI Slave SSPM<3:0> =

010x

Serial Input Buffer

(SSPxBUF)

MSb

Shift Register

(SSPxSR)

LSb

SDIx

SCKx

Processor 1

General I/O

Serial Clock

SDOx

MSb

Shift Register

(SSPxSR)

LSb

SCKx

Slave Select

(optional)

SSx

Processor 2

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PIC16(L)F1946/47

FIGURE 24-6:

Write to

SSPxBUF

SCKx

(CKP =

0

CKE =

0

)

SCKx

(CKP =

1

CKE =

0

)

SCKx

(CKP =

0

CKE =

1

)

SCKx

(CKP =

1

CKE =

1

)

SDOx

(CKE =

0

)

SDOx

(CKE =

1

)

SDIx

(SMP =

0

)

Input

Sample

(SMP =

0

)

SDIx

(SMP =

1

)

Input

Sample

(SMP =

1

)

SSPxIF

SSPxSR to

SSPxBUF

24.2.3

SPI MASTER MODE

The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2,

Figure 24-5

) is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set).

The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as

shown in Figure 24-6

,

Figure 24-8

and

Figure 24-9 ,

where the MSb is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user programmable to be one of the following:

• F

OSC

/4 (or T

CY

)

• F

OSC

/16 (or 4 * T

CY

)

• F

OSC

/64 (or 16 * T

CY

)

• Timer2 output/2

• Fosc/(4 * (SSPxADD + 1))

Figure 24-6

shows the waveforms for Master mode.

When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown.

SPI MODE WAVEFORM (MASTER MODE)

bit 7 bit 7 bit 7 bit 7 bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 bit 0 bit 0

4 Clock

Modes

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24.2.4

SPI SLAVE MODE

In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register.

While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCKx pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep.

24.2.4.1

Daisy-Chain Configuration

The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on.

The final slave output is connected to the master input.

Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device.

Figure 24-7

shows the block diagram of a typical daisy-chain connection when operating in SPI Mode.

In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the

BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it.

24.2.5

SLAVE SELECT

SYNCHRONIZATION

The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the

Slave Select line is pulled low, the slave knows that a new transmission is starting.

If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the

Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the

Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission.

The SSx pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SSx pin control enabled (SSPxCON1<3:0> =

0100

).

When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven.

When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application.

Note 1:

2:

When the SPI is in Slave mode with SSx pin control enabled (SSPxCON1<3:0> =

0100

), the SPI module will reset if the SSx pin is set to V

DD

.

When the SPI is used in Slave mode with

CKE set; the user must enable SSx pin control.

3:

While operated in SPI Slave mode the

SMP bit of the SSPxSTAT register must remain clear.

When the SPI module resets, the bit counter is forced to ‘

0

’. This can be done by either forcing the SSx pin to a high level or clearing the SSPEN bit.

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PIC16(L)F1946/47

FIGURE 24-7: SPI DAISY-CHAIN CONNECTION

SCK

SPI Master

SDOx

SDIx

General I/O

SCK

SDIx

SDOx

SSx

SPI Slave

#1

SCK

SDIx

SDOx

SSx

SPI Slave

#2

SCK

SDIx

SDOx

SSx

SPI Slave

#3

FIGURE 24-8:

SSx

SCKx

(CKP =

0

CKE =

0

)

SCKx

(CKP =

1

CKE =

0

)

Write to

SSPxBUF

SSPxBUF to

SSPxSR

SLAVE SELECT SYNCHRONOUS WAVEFORM

Shift register SSPxSR and bit count are reset bit 7 bit 6 bit 7 bit 6

SDOx

SDIx

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF bit 7 bit 7 bit 0 bit 0

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PIC16(L)F1946/47

FIGURE 24-9:

SSx

Optional

SCKx

(CKP =

0

CKE =

0

)

SCKx

(CKP =

1

CKE =

0

)

Write to

SSPxBUF

Valid

SDOx

SDIx

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

Write Collision detection active

FIGURE 24-10:

SSx

Not Optional

SCKx

(CKP =

0

CKE =

1

)

SCKx

(CKP =

1

CKE =

1

)

Write to

SSPxBUF

Valid

SDOx

SDIx

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

Write Collision detection active

SPI MODE WAVEFORM (SLAVE MODE WITH CKE =

0

)

bit 7 bit 7 bit 7 bit 7 bit 6 bit 5 bit 6 bit 5 bit 4 bit 4 bit 3 bit 2 bit 3 bit 2 bit 1

SPI MODE WAVEFORM (SLAVE MODE WITH CKE =

1

)

bit 0 bit 1 bit 0 bit 0 bit 0

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24.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the

MSSPx clock is much faster than the system clock.

In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSPx interrupts should be disabled.

In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the

MSSPx interrupt flag bit will be set and if enabled, will wake the device.

TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELA

APFCON

INTCON

PIE1

PIE4

PIR1

ANSA7

TMR1GIE

TMR1GIF

ANSA6

P3CSEL P3BSEL

GIE PEIE

ADIE

ADIF

ANSA5

P2DSEL

TMR0IE

RCIE

RC2IE

RCIF

ANSA4

P2CSEL

INTE

TXIE

TX2IE

TXIF

ANSA3

P2BSEL

IOCIE

SSPIE

SSPIF

ANSA2

CCP2SEL

TMR0IF

CCP1IE

CCP1IF

ANSA1

P1CSEL

INTF

TMR2IE

BCL2IE

TMR2IF

ANSA0

P1BSEL

IOCIF

TMR1IE

SSP2IE

TMR1IF

PIR4 — — RC2IF TX2IF —

SSP1BUF

Synchronous Serial Port Receive Buffer/Transmit Register

SSP2BUF

SSP1CON1

Synchronous Serial Port Receive Buffer/Transmit Register

WCOL SSPOV SSPEN CKP

SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT

SSP1STAT

SSP2CON1

SSP2CON3

SMP

WCOL

ACKTIM

CKE

SSPOV

PCIE

D/A

SSPEN

SCIE

P

CKP

BOEN

S

SDAHT

SBCDE

SBCDE

BCL2IF

SSPM<3:0>

AHEN

R/W

SSPM<3:0>

UA

AHEN

SSP2IF

DHEN

BF

DHEN

SSP2STAT

TRISA

TRISB

Legend:

*

SMP

TRISA7

CKE

TRISA6

D/A

TRISA5

P

TRISA4

S

TRISA3

R/W

TRISA2

UA

TRISA1

BF

TRISA0

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used by the MSSPx in SPI mode.

Page provides register information.

TRISB0

Register on Page

96

97

100

247 *

292

295

291

131

134

247 *

292

295

291

132

129

92

93

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24.3

I

2

C

MODE OVERVIEW

The Inter-Integrated Circuit Bus (I²C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing.

The I

2

C bus specifies two signal connections:

• Serial Clock (SCLx)

• Serial Data (SDAx)

Figure 24-2

and

Figure 24-3 show the block diagrams

of the MSSPx module when operating in I

2

C mode.

Both the SCLx and SDAx connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one.

Figure 24-11 shows a typical connection between two

processors configured as master and slave devices.

The I

2

C bus can operate with one or more master devices and one or more slave devices.

There are four potential modes of operation for a given device:

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

(master is receiving data from a slave)

• Slave Transmit mode

(slave is transmitting data to a master)

• Slave Receive mode

(slave is receiving data from the master)

To begin communication, a master device starts out in

Master Transmit mode. The master device sends out a

Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device.

If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK.

The master then continues in either Transmit mode or

Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively.

A Start bit is indicated by a high-to-low transition of the

SDAx line while the SCLx line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first.

The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave.

FIGURE 24-11: I

2

C MASTER/

SLAVE CONNECTION

V

DD

SCLx

Master

SDAx

V

DD

SCLx

SDAx

Slave

The Acknowledge bit (ACK) is an active-low signal, which holds the SDAx line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more.

The transition of a data bit is always performed while the SCLx line is held low. Transitions that occur while the SCLx line is held high are used to indicate Start and

Stop bits.

If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode.

If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode.

On the last byte of data communicated, the master device may end the transmission by sending a Stop bit.

If the master device is in Receive mode, it sends the

Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDAx line while the SCLx line is held high.

In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode.

The I

2

C bus specifies three message protocols;

• Single message where a master writes data to a slave.

• Single message where a master reads data from a slave.

• Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves.

2010-2012 Microchip Technology Inc.

DS41414D-page 254

When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching.

Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time.

24.3.1

CLOCK STRETCHING

When a slave device has not completed processing data, it can delay the transfer of more data through the process of Clock Stretching. An addressed slave device may hold the SCLx clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCLx line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCLx connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating.

Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data.

24.3.2

ARBITRATION

Each master device must monitor the bus for Start and

Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an

Idle state.

However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDAx data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels don’t match, loses arbitration, and must stop transmitting on the SDAx line.

For example, if one transmitter holds the SDAx line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDAx line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating.

The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDAx line. If this transmitter is also a master device, it also must stop driving the SCLx line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDAx line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message.

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common.

If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage.

Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.

24.4

I

2

C Mode Operation

All MSSPx I

2

C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC

®

microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I

2

C devices.

24.4.1 BYTE FORMAT

All communication in I

2

C is done in 9-bit segments. A byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCLx line, the device outputting data on the SDAx changes that pin to an input and reads in an acknowledge value on the next clock pulse.

The clock signal, SCLx, is provided by the master.

Data is valid to change while the SCLx signal is low, and sampled on the rising edge of the clock. Changes on the SDAx line while the SCLx line is high define special conditions on the bus, explained below.

24.4.2 DEFINITION OF I

2

C TERMINOLOGY

I

There is language and terminology in the description of

2

C communication that have definitions specific to I

2

C.

That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I

2

C specification.

24.4.3 SDAX AND SCLX PINS

Selection of any I

2

C mode with the SSPEN bit set, forces the SCLx and SDAx pins to be open-drain.

These pins should be set by the user to inputs by setting the appropriate TRIS bits.

Note:

Data is tied to output zero when an I

2

C mode is enabled.

DS41414D-page 255

PIC16(L)F1946/47

24.4.4 SDAX HOLD TIME

The hold time of the SDAx pin is selected by the

SDAHT bit of the SSPxCON3 register. Hold time is the time SDAx is held valid after the falling edge of SCLx.

Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance.

TABLE 24-2: I

2

C BUS TERMS

TERM Description

Transmitter

Receiver

The device which shifts data out onto the bus.

The device which shifts data in from the bus.

Master

Slave

Multi-master

Arbitration

Synchronization Procedure to synchronize the clocks of two or more devices on the bus.

Idle No master is controlling the bus, and both SDAx and SCLx lines are high.

Active

Addressed

Slave

Any time one or more master devices are controlling the bus.

Slave device that has received a matching address and is actively being clocked by a master.

Matching

Address

The device that initiates a transfer, generates clock signals and terminates a transfer.

The device addressed by the master.

A bus with more than one device that can initiate data transfers.

Procedure to ensure that only one master at a time controls the bus.

Winning arbitration ensures that the message is not corrupted.

Write Request

Read Request

Address byte that is clocked into a slave that matches the value stored in SSPxADD.

Slave receives a matching address with R/W bit clear, and is ready to clock in data.

Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the

Slave. This data is the next and all following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold

SCLx low to stall communication.

Bus Collision Any time the SDAx line is sampled low by the module while it is outputting and expected high state.

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24.4.5 START CONDITION

The I

2

C specification defines a Start condition as a transition of SDAx from a high to a low state while

SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state.

Figure 24-10

shows wave forms for Start and Stop conditions.

A bus collision can occur on a Start condition if the module samples the SDAx line low before asserting it low. This does not conform to the I

2

C Specification that states no bus collision can occur on a Start.

24.4.6 STOP CONDITION has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave.

In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock and prepare to clock out data.

After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails.

A Stop condition is a transition of the SDAx line from low-to-high state while the SCLx line is high.

Note:

At least one SCLx low time must appear before a Stop is valid, therefore, if the SDAx line goes low then high again while the SCLx line stays high, only the Start condition is detected.

24.4.8 START/STOP CONDITION INTERRUPT

24.4.7

RESTART CONDITION

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart

FIGURE 24-12: I

2

C START AND STOP CONDITIONS

MASKING

The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect.

SDAx

FIGURE 24-13:

SCLx

S

Change of

Data Allowed

Start

Condition

I

2

C RESTART CONDITION

P

Change of

Data Allowed

Stop

Condition

2010-2012 Microchip Technology Inc.

Sr

Change of

Data Allowed

Restart

Condition

Change of

Data Allowed

DS41414D-page 257

PIC16(L)F1946/47

24.4.9 ACKNOWLEDGE SEQUENCE

The 9th SCLx pulse for any transferred byte in I

2

C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response.

The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.

The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register.

Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response.

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSPxCON3 register are clear.

There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received.

When the module is addressed, after the 8th falling edge of SCLx on the bus, the ACKTIM bit of the

SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN bit is enabled.

24.5

I

2

C SLAVE MODE OPERATION

The MSSPx Slave mode operates in one of four modes selected in the SSPM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit

Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses.

Modes with Start and Stop bit interrupts operated the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition.

24.5.1 SLAVE MODE ADDRESSES

The SSPxADD register ( Register 24-6

) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened.

The SSPx Mask register (

Register 24-5

) affects the address matching process. See

Section 24.5.9

“SSPx Mask Register”

for more information.

24.5.1.1 I

2

C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match.

24.5.1.2 I

2

C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register.

After the acknowledge of the high byte, the UA bit is set and SCLx is held low until the user updates

SSPxADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCLx is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated, the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication.

A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match.

2010-2012 Microchip Technology Inc.

DS41414D-page 258

24.5.2 SLAVE RECEPTION

When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the

SSPxBUF register and acknowledged.

When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see

Register 24-4

.

An MSSPx interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software.

When the SEN bit of the SSPxCON2 register is set,

SCLx will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except

sometimes in 10-bit mode. See

Section 24.2.3 “SPI

Master Mode”

for more detail.

24.5.2.1 7-bit Addressing Reception

This section describes a standard sequence of events for the MSSPx module configured as an I

2

C Slave in

7-bit Addressing mode. Figure 24-13

and Figure 24-14

are used as visual references for this description.

This is a step by step process of what typically must be done to accomplish I

2

C communication.

1.

2.

3.

4.

Start bit detected.

S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled.

Matching address with R/W bit clear is received.

The slave pulls SDAx low sending an ACK to the master, and sets SSPxIF bit.

Software clears the SSPxIF bit.

5.

6.

7.

Software reads received address from

SSPxBUF clearing the BF flag.

If SEN =

1

; Slave software sets CKP bit to release the SCLx line.

8.

9.

The master clocks out a data byte.

Slave drives SDAx low sending an ACK to the master, and sets SSPxIF bit.

10. Software clears SSPxIF.

11. Software reads the received byte from

SSPxBUF clearing BF.

12. Steps 8-12 are repeated for all received bytes from the Master.

13. Master sends Stop condition, setting P bit of

SSPxSTAT, and the bus goes idle.

PIC16(L)F1946/47

24.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCLx. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module.

This list describes the steps that need to be taken by slave software to use these options for I

2

C communication.

Figure 24-15 displays a module using both

address and data holding.

Figure 24-16

includes the operation with the SEN bit of the SSPxCON2 register set.

1.

2.

3.

4.

5.

6.

S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled.

Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the 8th falling edge of SCLx.

Slave clears the SSPxIF.

Slave can look at the ACKTIM bit of the

SSPxCON3 register to determine if the SSPxIF was after or before the ACK.

Slave reads the address value from SSPxBUF, clearing the BF flag.

Slave sets ACK value clocked out to the master by setting ACKDT.

7.

8.

Slave releases the clock by setting CKP.

SSPxIF is set after an ACK, not after a NACK.

9.

If SEN =

1

the slave hardware will stretch the clock after the ACK.

10. Slave clears SSPxIF.

Note:

SSPxIF is still set after the 9th falling edge of

SCLx even if there is no clock stretching and

BF has been cleared. Only if NACK is sent to Master is SSPxIF not set

11. SSPxIF set and CKP cleared after 8th falling edge of SCLx for a received data byte.

12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt.

13. Slave reads the received data from SSPxBUF clearing BF.

14. Steps 7-14 are the same for each received data byte.

15. Communication is ended by either the slave sending an ACK =

1

, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register.

2010-2012 Microchip Technology Inc.

DS41414D-page 259

SDAx

SCLx

S

A7 A6

Receiving Address

A5 A4 A3 A2 A1 ACK D7 D6 D5

Receiving Data

D4 D3 D2 D1 D0 ACK

From Slave to Master

D7 D6 D5

Receiving Data

D4 D3 D2 D1 D0

ACK =

1

Bus Master sends

Stop condition

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

P

SSPxIF

BF

SSPOV

Cleared by software

SSPxBUF is read

First byte

of data is

available

in SSPxBUF

Cleared by software

SSPOV set because

SSPxBUF is still full.

ACK is not sent.

SSPxIF set on 9th falling edge of

SCLx

SDAx

SCLx

S

A7 A6

Receive Address

A5 A4 A3 A2 A1

R/W=

0

ACK

Receive Data

D7 D6 D5 D4 D3 D2 D1 D0

ACK

D7 D6 D5

Receive Data

D4 D3 D2 D1 D0

ACK

Bus Master sends

Stop condition

1 2 3 4 5 6 7 8 9

SEN

1 2 3 4 5 6 7

Clock is held low until CKP is set to ‘

1

8 9

SEN

1 2 3 4 5 6 7 8 9 P

SSPxIF

Cleared by software

SSPxIF set on 9th falling edge of SCLx

BF

SSPOV

CKP

SSPxBUF is read

CKP is written to ‘ releasing SCLx

1

’ in software,

Cleared by software

First byte

of data is

available

in SSPxBUF

SSPOV set because

SSPxBUF is still full.

ACK is not sent.

CKP is written to 1 in software, releasing SCLx

SCLx is not held low because

ACK=

1

SDAx

SCLx

S

SSPxIF

BF

ACKDT

CKP

Master Releases SDAx to slave for ACK sequence

Receiving Address

A7 A6 A5 A4 A3 A2 A1

ACK

Receiving Data

D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8

If AHEN =

1

:

SSPxIF is set

Address is read from

SSBUF

Slave software clears ACKDT to

ACK the received byte

When AHEN=

1

:

CKP is cleared by hardware and SCLx is stretched

SSPxIF is set on

9th falling edge of

SCLx, after ACK

ACKTIM

ACKTIM set by hardware on 8th falling edge of SCLx

When DHEN=

1

:

CKP is cleared by hardware on 8th falling edge of SCLx

ACKTIM cleared by hardware in 9th rising edge of SCLx

S

P

ACK

Received Data

D7 D6 D5 D4 D3 D2 D1 D0

9 1 2 3 4 5 6 7 8

Cleared by software

Data is read from SSPxBUF

Slave software sets ACKDT to not ACK

CKP set by software,

SCLx is released

ACKTIM set by hardware on 8th falling edge of SCLx

ACK=

1

Master sends

Stop condition

9

P

No interrupt after not ACK from Slave

SDAx

R/W =

0

Receiving Address

A7 A6 A5 A4 A3 A2 A1

Master releases

SDAx to slave for ACK sequence

ACK

Receive Data

D7 D6 D5 D4 D3 D2 D1 D0

SCLx

S

1 2 3 4

5 6 7 8

9

1 2 3 4 5 6 7 8

SSPxIF

ACK

9

Cleared by software

BF

ACKDT

CKP

Received address is loaded into

SSPxBUF

Slave software clears

ACKDT to ACK the received byte

When AHEN =

1

; on the 8th falling edge of SCLx of an address byte, CKP is cleared

Received data is available on SSPxBUF

When DHEN =

1

; on the 8th falling edge of SCLx of a received data byte, CKP is cleared

ACKTIM

ACKTIM is set by hardware on 8th falling edge of SCLx

ACKTIM is cleared by hardware on 9th rising edge of SCLx

S

P

Receive Data

D7 D6 D5 D4 D3 D2 D1 D0

1 2

3 4 5 6 7 8

SSPxBUF can be read any time before next byte is loaded

Slave sends not ACK

Set by software, release SCLx

ACK

Master sends

Stop condition

9

P

No interrupt after if not ACK from Slave

CKP is not cleared if not ACK

PIC16(L)F1946/47

24.5.3

SLAVE TRANSMISSION

When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the

SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit.

Following the ACK, slave hardware clears the CKP bit

and the SCLx pin is held low (see

Section 24.5.6

“Clock Stretching”

for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data.

The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then the SCLx pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time.

The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCLx input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCLx pin must be released by setting bit CKP.

An MSSPx interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse.

24.5.3.1

Slave Mode Bus Collision

A slave receives a Read request and begins shifting data out on the SDAx line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLxIF bit of the PIRx register is set. Once a bus collision is detected, the slave goes Idle and waits to be addressed again. User software can use the BCLxIF bit to handle a slave bus collision.

24.5.3.2

7-bit Transmission

A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission.

Figure 24-17

can be used as a reference to this list.

1.

2.

3.

4.

5.

6.

7.

8.

9.

Master sends a Start condition on SDAx and

SCLx.

S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled.

Matching address with R/W bit set is received by the Slave setting SSPxIF bit.

Slave hardware generates an ACK and sets

SSPxIF.

SSPxIF bit is cleared by user.

Software reads the received address from

SSPxBUF, clearing BF.

R/W is set so CKP was automatically cleared after the ACK.

The slave software loads the transmit data into

SSPxBUF.

CKP bit is set releasing SCLx, allowing the master to clock the data out of the slave.

10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register.

11. SSPxIF bit is cleared.

12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data.

Note 1:

If the master ACKs the clock will be stretched.

2:

ACKSTAT is the only bit updated on the rising edge of SCLx (9th) rather than the falling.

13. Steps 9-13 are repeated for each transmitted byte.

14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

2010-2012 Microchip Technology Inc.

DS41414D-page 264

SDAx

SCLx

SSPxIF

S

Receiving Address

A7 A6 A5 A4 A3 A2 A1

R/W =

1

ACK

Automatic Transmitting Data

D7 D6 D5 D4 D3 D2 D1 D0

ACK

Automatic Transmitting Data

D7 D6 D5 D4 D3 D2 D1 D0

ACK

Master sends

Stop condition

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

P

BF

Cleared by software

Data to transmit is loaded into SSPxBUF

CKP

Received address is read from SSPxBUF

When R/W is set

SCLx is always held low after 9th SCLx falling edge

Set by software

BF is automatically cleared after 8th falling edge of SCLx

CKP is not held for not

ACK

ACKSTAT

Masters not ACK is copied to

ACKSTAT

R/W

D/A

R/W is copied from the matching address byte

Indicates an address has been received

S

P

PIC16(L)F1946/47

24.5.3.3

7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set.

Figure 24-18

displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

1.

2.

3.

Bus starts Idle.

Master sends Start condition; the S bit of

SSPxSTAT is set; SSPxIF is set if interrupt on

Start detect is enabled.

Master sends matching address with R/W bit set. After the 8th falling edge of the SCLx line the

CKP bit is cleared and SSPxIF interrupt is generated.

4.

5.

6.

Slave software clears SSPxIF.

Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt.

Slave reads the address value from the

SSPxBUF register clearing the BF bit.

7.

8.

Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPxCON2 register accordingly.

Slave sets the CKP bit releasing SCLx.

9.

Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set.

11. Slave software clears SSPxIF.

12. Slave loads value to transmit to the master into

SSPxBUF setting the BF bit.

Note:

SSPxBUF cannot be loaded until after the

ACK.

13. Slave sets CKP bit releasing the clock.

14. Master clocks out the data from the slave and sends an ACK value on the 9th SCLx pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPxCON2 register.

16. Steps 10-15 are repeated for each byte transmitted to the master from the slave.

17. If the master sends a not ACK the slave releases the bus allowing the master to send a

Stop and end the communication.

Note:

Master must send a not ACK on the last byte to ensure that the slave releases the SCLx line to receive a Stop.

DS41414D-page 266

2010-2012 Microchip Technology Inc.

SDAx

SCLx

S

SSPxIF

Receiving Address

A7 A6 A5 A4 A3 A2 A1

R/W =

1

Master releases SDAx to slave for ACK sequence

ACK

Automatic Transmitting Data

D7 D6 D5 D4 D3 D2 D1 D0

Automatic

ACK

Transmitting Data

D7 D6 D5 D4 D3 D2 D1 D0

ACK

Master sends

Stop condition

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

P

Cleared by software

BF

Received address is read from SSPxBUF

Data to transmit is loaded into SSPxBUF

BF is automatically cleared after 8th falling edge of SCLx

ACKDT

Slave clears

ACKDT to ACK address

ACKSTAT

CKP

ACKTIM

When AHEN = address.

1

;

CKP is cleared by hardware after receiving matching

ACKTIM is set on 8th falling edge of SCLx

When R/W =

1

;

CKP is always cleared after ACK

Set by software, releases SCLx

ACKTIM is cleared on 9th rising edge of SCLx

Master’s ACK response is copied to SSPxSTAT

CKP not cleared after not ACK

R/W

D/A

PIC16(L)F1946/47

24.5.4 SLAVE MODE 10-BIT ADDRESS

RECEPTION

This section describes a standard sequence of events for the MSSPx module configured as an I

2

C Slave in

10-bit Addressing mode.

Figure 24-19 is used as a visual reference for this

description.

This is a step by step process of what must be done by slave software to accomplish I

2

C communication.

1.

2.

3.

4.

5.

6.

7.

8.

Bus starts Idle.

Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled.

Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set.

Slave sends ACK and SSPxIF is set.

Software clears the SSPxIF bit.

Software reads received address from

SSPxBUF clearing the BF flag.

Slave loads low address into SSPxADD, releasing SCLx.

Master sends matching low address byte to the

Slave; UA bit is set.

Note:

Updates to the SSPxADD register are not allowed until after the ACK sequence.

9.

Slave sends ACK and SSPxIF is set.

Note:

If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected.

10. Slave clears SSPxIF.

11. Slave reads the received matching address from SSPxBUF clearing BF.

12. Slave loads high address into SSPxADD.

13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCLx pulse; SSPxIF is set.

14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched.

15. Slave clears SSPxIF.

16. Slave reads the received byte from SSPxBUF clearing BF.

17. If SEN is set the slave sets CKP to release the

SCLx.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

24.5.5 10-BIT ADDRESSING WITH ADDRESS

OR DATA HOLD

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCLx line is held low are the same.

Figure 24-20 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 24-21

shows a standard waveform for a slave transmitter in 10-bit Addressing mode.

2010-2012 Microchip Technology Inc.

DS41414D-page 268

SDAx

1

Receive First Address Byte

1 1 1

0

A9 A8

ACK

Receive Second Address Byte

A7 A6 A5 A4 A3 A2 A1 A0 ACK

Receive Data

D7 D6 D5 D4 D3 D2 D1 D0

ACK

Receive Data

D7 D6 D5 D4 D3 D2 D1 D0 ACK

SCLx

S

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8

9 1 2 3 4 5 6 7 8 9

1 2 3 4 5

SCLx is held low while CKP =

0

6 7 8 9

SSPxIF

Set by hardware on 9th falling edge

Cleared by software

Master sends

Stop condition

P

BF

If address matches

SSPxADD it is loaded into

SSPxBUF

Receive address is read from SSPxBUF

Data is read from SSPxBUF

UA

When UA =

1

;

SCLx is held low

Software updates SSPxADD and releases SCLx

CKP

When SEN =

1

;

CKP is cleared after

9th falling edge of received byte

Set by software, releasing SCLx

SDAx

1

Receive First Address Byte

1 1 1 0

A9 A8

R/W =

0

ACK A7

Receive Second Address Byte

A6 A5 A4 A3 A2 A1 A0

ACK

D7 D6 D5

Receive Data

D4 D3 D2 D1 D0 ACK

Receive Data

D7 D6 D5

SCLx

S

1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2

SSPxIF

BF

ACKDT

UA

Set by hardware on 9th falling edge

Slave software clears

ACKDT to ACK the received byte

Cleared by software

SSPxBUF can be read anytime before the next received byte

Cleared by software

Received data is read from

SSPxBUF

Update to SSPxADD is not allowed until 9th falling edge of SCLx

CKP

ACKTIM

If when AHEN =

1

; on the 8th falling edge of SCLx of an address byte, CKP is cleared

ACKTIM is set by hardware on 8th falling edge of SCLx

Update of SSPxADD, clears UA and releases

SCLx

Set CKP with software releases SCLx

SDAx

Receiving Address

1 1 1 1 0

R/W =

0

A9 A8 ACK

Receiving Second Address Byte

A7 A6 A5 A4 A3 A2 A1 A0

ACK

Master sends

Restart event

Receive First Address Byte

1 1 1 1 0 A9 A8

ACK

Master sends not ACK

Master sends

Stop condition

Transmitting Data Byte

D7 D6 D5 D4 D3 D2 D1 D0

ACK =

1

SCLx

S

1

2 3 4 5 6 7 8 9

1

2 3 4 5 6 7 8 9

1

2 3 4 5 6 7 8 9

P

Sr

1

2 3 4 5 6 7 8 9

SSPxIF

Set by hardware

BF

UA

CKP

ACKSTAT

SSPxBUF loaded with received address

UA indicates SSPxADD must be updated

Cleared by software

After SSPxADD is updated, UA is cleared and SCLx is released

Set by hardware

Received address is read from SSPxBUF

High address is loaded back into SSPxADD

When R/W =

1

;

CKP is cleared on

9th falling edge of SCLx

Data to transmit is loaded into SSPxBUF

Set by software releases SCLx

Masters not ACK is copied

R/W

D/A

R/W is copied from the matching address byte

Indicates an address has been received

PIC16(L)F1946/47

24.5.6 CLOCK STRETCHING

Clock stretching occurs when a device on the bus holds the SCLx line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCLx.

The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. Setting CKP will release SCLx and allow more communication.

24.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPxCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes.

Note 1:

The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if

SSPxBUF was read before the 9th falling edge of SCLx.

2:

Previous versions of the module did not stretch the clock for a transmission if

SSPxBUF was loaded before the 9th falling edge of SCLx. It is now always cleared for read requests.

FIGURE 24-23: CLOCK SYNCHRONIZATION TIMING

24.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the

SCLx is stretched without CKP being cleared. SCLx is released immediately after a write to SSPxADD.

Note:

Previous versions of the module did not stretch the clock if the second address byte did not match.

24.5.6.3 Byte NACKing

When AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCLx for a received matching address byte. When DHEN bit of

SSPxCON3 is set; CKP is cleared after the 8th falling edge of SCLx for received data.

Stretching after the 8th falling edge of SCLx allows the slave to look at the received address or data and decide if it wants to ACK the received data.

24.5.7 CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low.

Therefore, the CKP bit will not assert the SCLx line until an external I

2

C master device has already asserted the SCLx line. The SCLx output will remain

I low until the CKP bit is set and all other devices on the

2

C bus have released SCLx. This ensures that a write to the CKP bit will not violate the minimum high time

requirement for SCLx (see Figure 24-22 ).

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

DX ‚

1

SDAx

SCLx

DX

Master device asserts clock CKP

Master device releases clock

WR

SSPxCON1

2010-2012 Microchip Technology Inc.

DS41414D-page 272

PIC16(L)F1946/47

24.5.8 GENERAL CALL ADDRESS SUPPORT

The addressing procedure for the I

2

C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge.

The general call address is a reserved address in the

I

2

C protocol, defined as address 0x00. When the

GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD.

After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond.

Figure 24-23

shows a general call reception sequence.

FIGURE 24-24:

SDAx

In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode.

If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of

SCLx. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally.

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

General Call Address

R/W =

0

Address is compared to General Call Address after ACK, set interrupt

ACK

D7 D6

Receiving Data

D5 D4 D3 D2 D1 D0

ACK

SCLx

S

SSPxIF

BF (SSPxSTAT<0>)

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

Cleared by software

SSPxBUF is read

GCEN (SSPxCON2<7>)

1

24.5.9 SSPX MASK REGISTER

An SSPx Mask (SSPxMSK) register ( Register 24-5

) is available in I

2

C Slave mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (‘

0

’) bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a “don’t care”.

This register is reset to all ‘

1

’s upon any Reset condition and, therefore, has no effect on standard

SSPx operation until written with a mask value.

The SSPx Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0> only. The SSPx mask has no effect during the reception of the first (high) byte of the address.

2010-2012 Microchip Technology Inc.

DS41414D-page 273

PIC16(L)F1946/47

24.6

I

2

C MASTER MODE

Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDAx and SCKx pins must be configured as inputs. The

MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low.

Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I

2

C bus may be taken when the P bit is set, or the bus is Idle.

In Firmware Controlled Master mode, user code conducts all I

2

C bus operations based on Start and

Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDAx and SCLx lines.

The following events will cause the SSPx Interrupt Flag bit, SSPxIF, to be set (SSPx interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

Note 1:

I

The MSSPx module, when configured in

2

C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the

SSPxBUF will not be written to and the

WCOL bit will be set, indicating that a write to the SSPxBUF did not occur

2:

When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete.

24.6.1 I

2

C MASTER MODE OPERATION

The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I

2

C bus will not be released.

In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘

0

’. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer.

In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘

1

’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘

1

’ to indicate the receive bit.

Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received 8 bits at a time.

After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission.

A Baud Rate Generator is used to set the clock frequency output on SCLx. See

Section 24.7 “Baud

Rate Generator”

for more detail.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

24.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high).

When the SCLx pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the

SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device

(

Figure 24-25

).

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION FIGURE 24-25:

SDAx

DX

SCLx deasserted but slave holds

SCLx low (clock arbitration)

DX ‚

1

SCLx allowed to transition high

SCLx

BRG

Value

03h

BRG decrements on

Q2 and Q4 cycles

02h 01h 00h (hold off)

SCLx is sampled high, reload takes place and BRG starts its count

03h 02h

BRG

Reload

24.6.3 WCOL STATUS FLAG

If the user writes the SSPxBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the

WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle.

Note:

Because queueing of events is not allowed, writing to the lower 5 bits of

SSPxCON2 is disabled until the Start condition is complete.

2010-2012 Microchip Technology Inc.

DS41414D-page 275

PIC16(L)F1946/47

24.6.4 I

2

C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSPxCON2 register. If the

SDAx and SCLx pins are sampled high, the Baud Rate

Generator is reloaded with the contents of

SSPxADD<7:0> and starts its count. If SCLx and

SDAx are both sampled high when the Baud Rate

Generator times out (T

BRG

), the SDAx pin is driven low. The action of the SDAx being driven low while

SCLx is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the

Baud Rate Generator times out (T

BRG

), the SEN bit of the SSPxCON2 register will be automatically cleared

FIGURE 24-26: FIRST START BIT TIMING

by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete.

Note 1:

If at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low, or if during the Start condition, the SCLx line is sampled low before the

SDAx line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag,

BCLxIF, is set, the Start condition is aborted and the I

2

C module is reset into its Idle state.

2:

The Philips I

2

C Specification states that a bus collision cannot occur on a Start.

Write to SEN bit occurs here

SDAx =

1

,

SCLx =

1

Set S bit (SSPxSTAT<3>)

At completion of Start bit, hardware clears SEN bit

and sets SSPxIF bit

T

BRG

T

BRG

Write to SSPxBUF occurs here

SDAx

1st bit

T

BRG

2nd bit

SCLx

S

T

BRG

DS41414D-page 276

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

24.6.5 I

2

C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit of the SSPxCON2 register is programmed high and the

Master state machine is no longer active. When the

RSEN bit is set, the SCLx pin is asserted low. When the

SCLx pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDAx pin is released

(brought high) for one Baud Rate Generator count

(T

BRG

). When the Baud Rate Generator times out, if

SDAx is sampled high, the SCLx pin will be deasserted

(brought high). When SCLx is sampled high, the Baud

Rate Generator is reloaded and begins counting. SDAx and SCLx must be sampled high for one T

BRG

. This action is then followed by assertion of the SDAx pin

(SDAx =

0

) for one T

BRG

while SCLx is high. SCLx is asserted low. Following this, the RSEN bit of the

FIGURE 24-27:

SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the

SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.

Note 1:

2:

If RSEN is programmed while any other event is in progress, it will not take effect.

A bus collision during the Repeated Start condition occurs if:

• SDAx is sampled low when SCLx goes from low-to-high.

• SCLx goes low before SDAx is asserted low. This may indicate that another master is attempting to transmit a data ‘

1

’.

REPEAT START CONDITION WAVEFORM

SDAx

Write to SSPxCON2 occurs here

SDAx =

1

,

SCLx (no change)

T

BRG

SDAx =

1

,

SCLx =

1

T

BRG

T

BRG

S bit set by hardware

At completion of Start bit, hardware clears RSEN bit

and sets SSPxIF

1st bit

SCLx

Sr

Repeated Start

Write to SSPxBUF occurs here

T

BRG

T

BRG

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PIC16(L)F1946/47

24.6.6 I

2

C MASTER MODE TRANSMISSION

Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate

Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted. SCLx is held low for one Baud Rate Generator rollover count (T

BRG

). Data should be valid before

SCLx is released high. When the SCLx pin is released high, it is held that way for T

BRG

. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDAx.

This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and

SDAx unchanged (

Figure 24-27

).

After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDAx pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT Status bit of the

SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float.

24.6.6.1

BF Status Flag

In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out.

24.6.6.2

WCOL Status Flag

If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).

WCOL must be cleared by software before the next transmission.

24.6.6.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the slave has sent an Acknowledge (ACK =

0

) and is set when the slave does not

Acknowledge (ACK =

1

). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data.

24.6.6.4 Typical transmit sequence:

1.

2.

3.

4.

5.

The user generates a Start condition by setting the SEN bit of the SSPxCON2 register.

SSPxIF is set by hardware on completion of the

Start.

SSPxIF is cleared by software.

The MSSPx module will wait the required start time before any other operation takes place.

The user loads the SSPxBUF with the slave address to transmit.

6.

Address is shifted out the SDAx pin until all 8 bits are transmitted. Transmission begins as soon as SSPxBUF is written to.

7.

8.

The MSSPx module shifts in the ACK bit from the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the

SSPxIF bit.

9.

The user loads the SSPxBUF with eight bits of data.

10. Data is shifted out the SDAx pin until all 8 bits are transmitted.

11. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

12. Steps 8-11 are repeated for all transmitted data bytes.

13. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the

SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete.

2010-2012 Microchip Technology Inc.

DS41414D-page 278

SDAx

SCLx

SSPxIF

Write SSPxCON2<0> SEN =

1

Start condition begins

SEN =

0

Transmit Address to Slave

A7 A6 A5 A4 A3 A2 A1

R/W =

0

ACK =

0

SSPxBUF written with 7-bit address and R/W start transmit

S

1 2 3 4 5 6 7 8

From slave, clear ACKSTAT bit SSPxCON2<6>

D7

9 1

SCLx held low while CPU responds to SSPxIF

Transmitting Data or Second Half of 10-bit Address

D6

2

D5

3

D4

4

D3

5

D2

6

D1

7

D0

8

ACK

9

ACKSTAT in

SSPxCON2 =

1

P

Cleared by software

Cleared by software service routine from SSPx interrupt

Cleared by software

BF (SSPxSTAT<0>)

SSPxBUF written

SSPxBUF is written by software

SEN

After Start condition, SEN cleared by hardware

PEN

R/W

PIC16(L)F1946/47

24.6.7

I

2

C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN bit of the SSPxCON2 register.

Note:

The MSSPx module must be in an Idle state before the RCEN bit is set or the

RCEN bit will be disregarded.

The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the

BF flag bit is set, the SSPxIF flag bit is set and the Baud

Rate Generator is suspended from counting, holding

SCLx low. The MSSPx is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPxCON2 register.

24.6.7.1

BF Status Flag

In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read.

24.6.7.2

SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is already set from a previous reception.

24.6.7.3

WCOL Status Flag

If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).

24.6.7.4 Typical Receive Sequence:

1.

2.

3.

4.

5.

6.

7.

8.

9.

The user generates a Start condition by setting the SEN bit of the SSPxCON2 register.

SSPxIF is set by hardware on completion of the

Start.

SSPxIF is cleared by software.

User writes SSPxBUF with the slave address to transmit and the R/W bit set.

Address is shifted out the SDAx pin until all 8 bits are transmitted. Transmission begins as soon as SSPxBUF is written to.

The MSSPx module shifts in the ACK bit from the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the

SSPxIF bit.

User sets the RCEN bit of the SSPxCON2 register and the Master clocks in a byte from the slave.

After the 8th falling edge of SCLx, SSPxIF and

BF are set.

10. Master clears SSPxIF and reads the received byte from SSPxUF, clears BF.

11. Master sets ACK value sent to slave in ACKDT bit of the SSPxCON2 register and initiates the

ACK by setting the ACKEN bit.

12. Masters ACK is clocked out to the Slave and

SSPxIF is set.

13. User clears SSPxIF.

14. Steps 8-13 are repeated for each received byte from the slave.

15. Master sends a not ACK or Stop to end communication.

DS41414D-page 280

2010-2012 Microchip Technology Inc.

SDAx

Write to SSPxCON2<0>(SEN =

1

), begin Start condition

SEN =

0

Write to SSPxBUF occurs here, start XMIT

Master configured as a receiver by programming SSPxCON2<3> (RCEN =

ACK from Slave

1

)

RCEN cleared automatically

Write to SSPxCON2<4> to start Acknowledge sequence

SDAx = ACKDT (SSPxCON2<5>) =

0

ACK from Master

SDAx = ACKDT =

RCEN =

1

0

, start next receive

A7

Transmit Address to Slave

A6 A5 A4 A3 A2 A1

R/W

ACK D7

Receiving Data from Slave

D6

D5

D4 D3

D2

D1

D0

ACK

D7

Receiving Data from Slave

D6

D5

D4 D3

Set ACKEN, start Acknowledge sequence

SDAx = ACKDT =

1

RCEN cleared automatically

PEN bit =

1 written here

D2

D1

D0

ACK

SCLx

SSPxIF

S

1 2 3 4

5

Cleared by software

6

7

8 9

1 2 3 4

Cleared by software

5

6 7

Set SSPxIF interrupt at end of receive

8

Cleared by software

9

ACK is not sent

1 2 3 4 5 6 7

Data shifted in on falling edge of CLK

8

9

Set SSPxIF at end of receive

Set SSPxIF interrupt at end of Acknowledge sequence

P

Bus master terminates transfer

Set SSPxIF interrupt at end of Acknowledge sequence

Cleared by software

Cleared in software

Set P bit

(SSPxSTAT<4>) and SSPxIF

SDAx =

0

, SCLx =

1 while CPU responds to SSPxIF

BF

(SSPxSTAT<0>)

Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF

SSPOV

SSPOV is set because

SSPxBUF is still full

ACKEN

RCEN

Master configured as a receiver by programming SSPxCON2<3> (RCEN =

1

)

RCEN cleared automatically

ACK from Master

SDAx = ACKDT =

0

RCEN cleared automatically

PIC16(L)F1946/47

24.6.8

ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the

SSPxCON2 register. When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(T

BRG

) and the SCLx pin is deasserted (pulled high).

When the SCLx pin is sampled high (clock arbitration), the Baud Rate Generator counts for T

BRG

. The SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSPx module then goes into Idle mode

(

Figure 24-29

).

24.6.8.1

WCOL Status Flag

If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).

24.6.9

A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the

SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘

0

’. When the Baud Rate

Generator times out, the SCLx pin will be brought high and one T

BRG

(Baud Rate Generator rollover count) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the P bit of the

SSPxSTAT register is set. A T

BRG

later, the PEN bit is

cleared and the SSPxIF bit is set ( Figure 24-30 ).

24.6.9.1

STOP CONDITION TIMING

WCOL Status Flag

If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).

FIGURE 24-30: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here, write to SSPxCON2

ACKEN =

1

, ACKDT =

0

ACKEN automatically cleared

T

BRG

T

BRG

SDAx

D0

ACK

SCLx

8 9

SSPxIF

SSPxIF set at the end of receive

Note:

T

BRG

= one Baud Rate Generator period.

Cleared in software

Cleared in software

SSPxIF set at the end of Acknowledge sequence

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PIC16(L)F1946/47

FIGURE 24-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

Write to SSPxCON2, set PEN

Falling edge of

9th clock

SCLx =

1

for T

BRG

, followed by SDAx =

1

for T

BRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set.

PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set

T

BRG

SCLx

24.6.10

SDAx ACK

P

T

BRG

T

BRG

T

BRG

SCLx brought high after T

BRG

SDAx asserted low before rising edge of clock to setup Stop condition

Note:

T

BRG

= one Baud Rate Generator period.

SLEEP OPERATION

While in Sleep mode, the I

2

C Slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSPx interrupt is enabled).

24.6.11

EFFECTS OF A RESET

A Reset disables the MSSPx module and terminates the current transfer.

24.6.12

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSPx module is disabled. Control of the I

2

C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear.

When the bus is busy, enabling the SSPx interrupt will generate the interrupt when the Stop condition occurs.

In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

24.6.13

MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a ‘

1

’ on SDAx, by letting SDAx float high and another master asserts a ‘

0

’. When the SCLx pin floats high, data should be stable. If the expected data on

SDAx is a ‘

1

’ and the data sampled on the SDAx pin is

0

’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF, and reset the I

2

C port to its Idle state (

Figure 24-31

).

If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I

2

C bus is free, the user can resume communication by asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I

2

C bus is free, the user can resume communication by asserting a Start condition.

The master will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set.

A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I

2

C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

FIGURE 24-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Data changes while SCLx =

0

SDAx line pulled low by another source

SDAx released by master

Sample SDAx. While SCLx is high, data does not match what is driven by the master.

Bus collision has occurred.

SDAx

SCLx

BCLxIF

Set bus collision interrupt (BCLxIF)

DS41414D-page 284

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

24.6.13.1

Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if: a) b)

SDAx or SCLx are sampled low at the beginning of the Start condition (

Figure 24-32

).

SCLx is sampled low before SDAx is asserted low (

Figure 24-33

).

During a Start condition, both the SDAx and the SCLx pins are monitored.

If the SDAx pin is already low, or the SCLx pin is already low, then all of the following occur:

• the Start condition is aborted,

• the BCLxIF flag is set and

• the MSSPx module is reset to its Idle state

( Figure 24-32 ).

The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘

1

’ during the Start condition.

FIGURE 24-33:

If the SDAx pin is sampled low during this count, the

BRG is reset and the SDAx line is asserted early

(

Figure 24-34

). If, however, a ‘

1

’ is sampled on the

SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCLx pin is sampled as ‘

0

’ during this time, a bus collision does not occur. At the end of the BRG count, the SCLx pin is asserted low.

Note:

The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDAx before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated

Start or Stop conditions.

BUS COLLISION DURING START CONDITION (SDAX ONLY)

SDAx goes low before the SEN bit is set.

Set BCLxIF,

S bit and SSPxIF set because

SDAx =

0

, SCLx =

1

.

SDAx

SCLx

SEN

BCLxIF

Set SEN, enable Start condition if SDAx =

1

, SCLx =

1

SDAx sampled low before

Start condition. Set BCLxIF.

S bit and SSPxIF set because

SDAx =

0

, SCLx =

1

.

SEN cleared automatically because of bus collision.

SSPx module reset into Idle state.

SSPxIF and BCLxIF are cleared by software

S

SSPxIF

SSPxIF and BCLxIF are cleared by software

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

FIGURE 24-34:

SDAx

BUS COLLISION DURING START CONDITION (SCLX =

0

)

SDAx =

0

, SCLx =

1

T

BRG

T

BRG

SCLx

Set SEN, enable Start sequence if SDAx =

1

, SCLx =

1

SEN

BCLxIF

SCLx =

0

before BRG time-out, bus collision occurs. Set BCLxIF.

SCLx =

0

before SDAx =

0

, bus collision occurs. Set BCLxIF.

S

0

SSPxIF

0

Interrupt cleared by software

0

0

FIGURE 24-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDAx

SDAx =

0

, SCLx =

1

Set S

Less than T

BRG

T

BRG

SDAx pulled low by other master.

Reset BRG and assert SDAx.

Set SSPxIF

SCLx

SEN

BCLxIF

S

SCLx pulled low after BRG time-out

Set SEN, enable Start sequence if SDAx =

1

, SCLx =

1

0

S

SSPxIF

SDAx =

0

, SCLx =

1

, set SSPxIF

Interrupts cleared by software

2010-2012 Microchip Technology Inc.

DS41414D-page 286

PIC16(L)F1946/47

24.6.13.2

Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision occurs if: a) b)

A low level is sampled on SDAx when SCLx goes from low level to high level.

SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data ‘

1

’.

When the user releases SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled.

If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘

0

’, Figure 24-35 ).

If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.

If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘

1

’ during the Repeated

Start condition, see

Figure 24-36 .

If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the

SCLx pin is driven low and the Repeated Start condition is complete.

FIGURE 24-36:

SDAx

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SCLx

Sample SDAx when SCLx goes high.

If SDAx =

0

, set BCLxIF and release SDAx and SCLx.

RSEN

BCLxIF

S

SSPxIF

Cleared by software

0

0

FIGURE 24-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

T

BRG

T

BRG

SDAx

SCLx

BCLxIF

SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx.

Interrupt cleared by software

RSEN

S

SSPxIF

0

2010-2012 Microchip Technology Inc.

DS41414D-page 287

PIC16(L)F1946/47

24.6.13.3

Bus collision occurs during a Stop condition if: a) b)

Bus Collision During a Stop

Condition

After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out.

After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high.

FIGURE 24-38:

The Stop condition begins with SDAx asserted low.

When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘

0

’ ( Figure 24-37 ). If the SCLx pin is

sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘

0

’ (

Figure 24-38

).

BUS COLLISION DURING A STOP CONDITION (CASE 1)

T

BRG

T

BRG

T

BRG

SDAx sampled low after T

BRG

, set BCLxIF

SDAx

SDAx asserted low

SCLx

PEN

BCLxIF

P

SSPxIF

0

0

FIGURE 24-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)

T

BRG

T

BRG

T

BRG

SDAx

Assert SDAx

SCLx goes low before SDAx goes high, set BCLxIF

SCLx

PEN

BCLxIF

P

SSPxIF

0

0

2010-2012 Microchip Technology Inc.

DS41414D-page 288

PIC16(L)F1946/47

TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH I

2

C™ OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

PIE1

PIE2

PIE4

PIR1

PIR2

PIR4

(1)

(1)

TRISA

TRISB

SSP1ADD

SSP1BUF

SSP1CON1

SSP1CON2

SSP1CON3

SSP1MSK

SSP1STAT

TMR1GIE

OSFIE

TMR1GIF

OSFIF

TRISA7

TRISB7

ADIE

C2IE

ADIF

C2IF

TRISA6

TRISB6

RCIE

C1IE

RC2IE

RCIF

C1IF

RC2IF

TRISA5

TRISB5

MSSPx Receive Buffer/Transmit Register

WCOL

GCEN

ACKTIM

SSPOV

ACKSTAT

PCIE

SSPEN

ACKDT

SCIE

TXIE

EEIE

TX2IE

TXIF

EEIF

TX2IF

TRISA4

TRISB4

TRISA3

TRISB3

ADD<7:0>

CKP

ACKEN

BOEN

SSPIE

BCLIE

SSPIF

BCLIF

RCEN

SDAHT

MSK<7:0>

CCP1IE

LCDIE

CCP1IF

LCDIF

TRISA2

TRISB2

SSPM<3:0>

PEN

SBCDE

TMR2IE

C3IE

BCL2IE

TMR2IF

C3IF

BCL2IF

TRISA1

TRISB1

RSEN

AHEN

TMR1IE

CCP2IE

(1)

SSP2IE

TMR1IF

CCP2IF

(1)

SSP2IF

TRISA0

TRISB0

SEN

DHEN

SMP CKE D/A P S R/W UA BF

SSP2ADD

SSP2BUF

SSP2CON1

SSP2CON2

SSP2CON3

SSP2MSK

MSSP2 Receive Buffer/Transmit Register

WCOL

GCEN

ACKTIM

SSPOV

ACKSTAT

PCIE

SSPEN

ACKDT

SCIE

ADD<7:0>

CKP

ACKEN

BOEN

RCEN

SDAHT

MSK<7:0>

SSPM<3:0>

PEN

SBCDE

RSEN

AHEN

SEN

DHEN

SSP2STAT

Legend:

Note 1:

*

SMP CKE D/A P S R/W UA BF

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by the MSSP module in I

2

C™ mode.

Page provides register information.

PIC16F1947 only.

Reset

Values on

Page

97

98

291

296

247

*

292

294

295

296

100

131

134

296

247

*

292

294

295

296

291

92

93

94

96

2010-2012 Microchip Technology Inc.

DS41414D-page 289

PIC16(L)F1946/47

24.7

BAUD RATE GENERATOR

The MSSPx module has a Baud Rate Generator available for clock generation in both I

2

C and SPI Master modes. The Baud Rate Generator (BRG) reload value

is placed in the SSPxADD register ( Register 24-6

).

When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down.

Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state.

An internal signal “Reload” in Figure 24-39

triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the

FIGURE 24-40:

module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSPx is being operated in.

Table 24-4

demonstrates clock rates based on instruction cycles and the BRG value loaded into

SSPxADD.

EQUATION 24-1:

F

CLOCK

=

F

OSC

SSPxADD + 1

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0>

SSPxADD<7:0>

SSPM<3:0>

SCLx

Reload

Control

SSPxCLK

Reload

BRG Down Counter

F

OSC

/2

Note:

Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate

Generator for I

2

C. This is an implementation limitation.

TABLE 24-4: MSSPx CLOCK RATE W/BRG

Note 1:

F

OSC

32 MHz

32 MHz

32 MHz

16 MHz

F

CY

8 MHz

8 MHz

8 MHz

4 MHz

BRG Value

13h

19h

4Fh

09h

F

CLOCK

(2 Rollovers of BRG)

400 kHz

(1)

308 kHz

100 kHz

400 kHz

(1)

16 MHz

16 MHz

4 MHz

4 MHz

0Ch

27h

308 kHz

100 kHz

4 MHz 1 MHz 09h 100 kHz

The I

2

C interface does not conform to the 400 kHz I

2

C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

2010-2012 Microchip Technology Inc.

DS41414D-page 290

PIC16(L)F1946/47

24.8

Register Definitions: MSSP Control

REGISTER 24-1: SSPxSTAT: SSPx STATUS REGISTER

bit 7

R/W-0/0

SMP

R/W-0/0

CKE

R-0/0

D/A

R-0/0

P

R-0/0

S

R-0/0

R/W

R-0/0

UA

R-0/0

BF bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

SMP:

SPI Data Input Sample bit

SPI Master mode:

1

= Input data sampled at end of data output time

0

= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

In I C Master or Slave mode:

1

= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

0

= Slew rate control enabled for high speed mode (400 kHz)

CKE:

SPI Clock Edge Select bit (SPI mode only)

In SPI Master or Slave mode:

1

= Transmit occurs on transition from active to Idle clock state

0

= Transmit occurs on transition from Idle to active clock state

In I C™ mode only:

1

= Enable input logic so that thresholds are compliant with SMBus specification

0

= Disable SMBus specific inputs

D/A:

Data/Address bit (I

2

C mode only)

1

= Indicates that the last byte received or transmitted was data

0

= Indicates that the last byte received or transmitted was address

P:

Stop bit

(I

2

C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.)

1

= Indicates that a Stop bit has been detected last (this bit is ‘

0

’ on Reset)

0

= Stop bit was not detected last

S:

Start bit

(I

2

C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.)

1

= Indicates that a Start bit has been detected last (this bit is ‘

0

’ on Reset)

0

= Start bit was not detected last

R/W:

Read/Write bit information (I

2

C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit.

In I C Slave mode:

1

= Read

0

= Write

In I C Master mode:

1

= Transmit is in progress

0

= Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode.

UA:

Update Address bit (10-bit I

2

C mode only)

1

= Indicates that the user needs to update the address in the SSPxADD register

0

= Address does not need to be updated

BF:

Buffer Full Status bit

Receive (SPI and I C modes):

1

= Receive complete, SSPxBUF is full

0

= Receive not complete, SSPxBUF is empty

Transmit (I C mode only):

1

= Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full

0

= Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

REGISTER 24-2:

R/C/HS-0/0

WCOL bit 7

SSPxCON1: SSPx CONTROL REGISTER 1

R/C/HS-0/0

SSPOV

R/W-0/0

SSPEN

R/W-0/0

CKP

R/W-0/0 R/W-0/0 R/W-0/0

SSPM<3:0>

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Bit is set by hardware C = User cleared

WCOL:

Write Collision Detect bit

Master mode:

1

= A write to the SSPxBUF register was attempted while the I

2

C conditions were not valid for a transmission to be started

0

= No collision

Slave mode:

1

= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)

0

= No collision

SSPOV:

Receive Overflow Indicator bit

(1)

In SPI mode:

1

= A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software).

0

= No overflow

In I C mode:

1

= A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in

Transmit mode (must be cleared in software).

0

= No overflow

SSPEN:

Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output

In SPI mode:

1

= Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins

(2)

0

= Disables serial port and configures these pins as I/O port pins

In I C mode:

1

= Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins

(3)

0

= Disables serial port and configures these pins as I/O port pins

CKP:

Clock Polarity Select bit

In SPI mode:

1

= Idle state for clock is a high level

0

= Idle state for clock is a low level

In I C Slave mode:

SCLx release control

1

= Enable clock

0

= Holds clock low (clock stretch). (Used to ensure data setup time.)

In I C Master mode:

Unused in this mode

2010-2012 Microchip Technology Inc.

DS41414D-page 292

PIC16(L)F1946/47

REGISTER 24-2: SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED)

bit 3-0

Note 1:

2:

3:

4:

5:

SSPM<3:0>:

Synchronous Serial Port Mode Select bits

0000

= SPI Master mode, clock = F

OSC

/4

0001

= SPI Master mode, clock = F

OSC

/16

0010

= SPI Master mode, clock = F

OSC

/64

0011

= SPI Master mode, clock = TMR2 output/2

0100

= SPI Slave mode, clock = SCKx pin, SSx pin control enabled

0101

= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin

0110

0111

= I

= I

1000

= I

2

2

2

C Slave mode, 7-bit address

C Slave mode, 10-bit address

C Master mode, clock = F

OSC

/ (4 * (SSPxADD+1))

(4)

1001

= Reserved

1010

= SPI Master mode, clock = F

OSC

/(4 * (SSPxADD+1))

(5)

1011

= I

2

C firmware controlled Master mode (Slave idle)

1100

= Reserved

1101

= Reserved

1110

= I

1111

= I

2

2

C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the

SSPxBUF register.

When enabled, these pins must be properly configured as input or output.

When enabled, the SDAx and SCLx pins must be configured as inputs.

SSPxADD values of 0, 1 or 2 are not supported for I

2

C Mode.

SSPxADD value of ‘

0

’ is not supported. Use SSPM =

0000

instead.

2010-2012 Microchip Technology Inc.

DS41414D-page 293

PIC16(L)F1946/47

REGISTER 24-3:

R/W-0/0

GCEN bit 7

SSPxCON2: SSPx CONTROL REGISTER 2

R-0/0

ACKSTAT

R/W-0/0

ACKDT

R/S/HS-0/0

ACKEN

R/S/HS-0/0

RCEN

R/S/HS-0/0

PEN

R/S/HS-0/0

RSEN

R/W/HS-0/0

SEN bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HC = Cleared by hardware S = User set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Note 1:

GCEN:

General Call Enable bit (in I

2

C Slave mode only)

1

= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR

0

= General call address disabled

ACKSTAT:

Acknowledge Status bit (in I

2

C mode only)

1

= Acknowledge was not received

0

= Acknowledge was received

ACKDT:

Acknowledge Data bit (in I

2

C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1

= Not Acknowledge

0

= Acknowledge

ACKEN:

Acknowledge Sequence Enable bit (in I

2

C Master mode only)

In Master Receive mode:

1

= Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0

= Acknowledge sequence idle

RCEN:

Receive Enable bit (in I

2

C Master mode only)

1

= Enables Receive mode for I

2

C

0

= Receive idle

PEN:

Stop Condition Enable bit (in I

2

C Master mode only)

SCKx Release Control:

1

= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.

0

= Stop condition Idle

RSEN:

Repeated Start Condition Enable bit (in I

2

C Master mode only)

1

= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0

= Repeated Start condition Idle

SEN:

Start Condition Enable bit

In Master mode:

1

= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0

= Start condition Idle

In Slave mode:

1

= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0

= Clock stretching is disabled

For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I

2

C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).

2010-2012 Microchip Technology Inc.

DS41414D-page 294

PIC16(L)F1946/47

REGISTER 24-4:

R-0/0

ACKTIM bit 7

SSPxCON3: SSPx CONTROL REGISTER 3

R/W-0/0

PCIE

R/W-0/0

SCIE

R/W-0/0

BOEN

R/W-0/0

SDAHT

R/W-0/0

SBCDE

R/W-0/0

AHEN

R/W-0/0

DHEN bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

ACKTIM:

Acknowledge Time Status bit (I

2

C mode only)

(3)

1

= Indicates the I

2

C bus is in an Acknowledge sequence, set on 8

0

= Not an Acknowledge sequence, cleared on 9

TH

TH

falling edge of SCLx clock

rising edge of SCLx clock

PCIE

: Stop Condition Interrupt Enable bit (I

2

C mode only)

1

= Enable interrupt on detection of Stop condition

0

= Stop detection interrupts are disabled

(2)

SCIE

: Start Condition Interrupt Enable bit (I

2

C mode only)

1

= Enable interrupt on detection of Start or Restart conditions

0

= Start detection interrupts are disabled

(2)

BOEN:

Buffer Overwrite Enable bit

In SPI Slave mode:

(1)

1

= SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit

0

= If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the

SSPxCON1 register is set, and the buffer is not updated

In I

2

C Master mode and SPI Master mode:

This bit is ignored.

In I

2

C Slave mode:

1

= SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit =

0

.

0

= SSPxBUF is only updated when SSPOV is clear

SDAHT:

SDAx Hold Time Selection bit (I

2

C mode only)

1

= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx

0

= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx

SBCDE:

Slave Mode Bus Collision Detect Enable bit (I

2

C Slave mode only)

If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the

BCLxIF bit of the PIR2 register is set, and bus goes idle

1

= Enable slave bus collision interrupts

0

= Slave bus collision interrupts are disabled

AHEN:

Address Hold Enable bit (I

2

C Slave mode only)

1

= Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the

SSPxCON1 register will be cleared and the SCLx will be held low.

0

= Address holding is disabled

DHEN:

Data Hold Enable bit (I

2

C Slave mode only)

1

= Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low.

0

= Data holding is disabled

Note 1:

2:

3:

For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF =

1

, but hardware continues to write the most recent byte to SSPxBUF.

This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

2010-2012 Microchip Technology Inc.

DS41414D-page 295

PIC16(L)F1946/47

REGISTER 24-5:

R/W-1/1

SSPxMSK: SSPx MASK REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

MSK<7:0> bit 7

R/W-1/1 R/W-1/1 R/W-1/1 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-1 bit 0

MSK<7:1>:

Mask bits

1

= The received address bit n is compared to SSPxADD<n> to detect I

2

C address match

0

= The received address bit n is not used to detect I

2

C address match

MSK<0>:

Mask bit for I

2

C Slave mode, 10-bit Address

I

2

C Slave mode, 10-bit address (SSPM<3:0> =

0111

or

1111

):

1

= The received address bit 0 is compared to SSPxADD<0> to detect I

2

C address match

0

= The received address bit 0 is not used to detect I

2

C address match

I

2

C Slave mode, 7-bit address, the bit is ignored

REGISTER 24-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I

2

C MODE)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

ADD<7:0>

R/W-0/0 R/W-0/0 R/W-0/0 bit 7 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Master mode:

bit 7-0

ADD<7:0>:

Baud Rate Clock Divider bits

SCLx pin clock period = ((ADD<7:0> + 1) *4)/F

OSC

10-Bit Slave mode – Most Significant Address byte:

bit 7-3 bit 2-1 bit 0

Not used:

Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I

2

C specification and must be equal to ‘

11110

’. However, those bits are compared by hardware and are not affected by the value in this register.

ADD<2:1>:

Two Most Significant bits of 10-bit address

Not used:

Unused in this mode. Bit state is a “don’t care”.

10-Bit Slave mode – Least Significant Address byte:

bit 7-0

ADD<7:0>:

Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1 bit 0

ADD<7:1>:

7-bit address

Not used:

Unused in this mode. Bit state is a “don’t care”.

2010-2012 Microchip Technology Inc.

DS41414D-page 296

PIC16(L)F1946/47

25.0

ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

Note:

The PIC16(L)F1946/47 devices have two

EUSARTs. Therefore, all information in this section refers to both EUSART 1 and

EUSART 2.

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers.

FIGURE 25-1:

These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device.

The EUSART module includes the following capabilities:

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in synchronous modes

• Sleep operation

The EUSART module implements the following additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 25-1

and Figure 25-2

.

EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXxREG Register

8

MSb

(8)

• • •

Transmit Shift Register (TSR)

LSb

0

TXxIE

TXxIF

Pin Buffer and Control

Interrupt

TXx/CKx pin

TXEN

Baud Rate Generator

BRG16

SPxBRGH

+ 1

SPxBRGL

F

OSC

÷ n

Multiplier

SYNC

BRGH

BRG16 x4 n x16 x64

1 X 0 0

X 1 1 0

X 1 0 1

0

0

0

TX9D

TX9

TRMT

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PIC16(L)F1946/47

FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM

CREN OERR RCIDL

RXx/DTx pin

Pin Buffer and Control

Data

Recovery

Baud Rate Generator

F

OSC

BRG16

+ 1

SPxBRGH SPxBRGL

Multiplier

SYNC

BRGH

BRG16 x4 x16 x64

1 X 0 0

X 1 1 0

X 1 0 1

0

0

0 n

÷ n

FERR

MSb

Stop (8) 7

RSR Register

• • •

1

LSb

0

START

RX9

RX9D

RCxREG Register

8

Data Bus

RCxIF

RCxIE

FIFO

Interrupt

The operation of the EUSART module is controlled through three registers:

• Transmit Status and Control (TXxSTA)

• Receive Status and Control (RCxSTA)

• Baud Rate Control (BAUDxCON)

These registers are detailed in Register 25-1 ,

Register 25-2 and

Register 25-3

, respectively.

For all modes of EUSART operation, the TRIS control bits corresponding to the RXx/DTx and TXx/CKx pins should be set to ‘

1

’. The EUSART control will automatically reconfigure the pin from input to output, as needed.

When the receiver or transmitter section is not enabled then the corresponding RXx/DTx or TXx/CKx pin may be used for general purpose input and output.

DS41414D-page 298

2010-2012 Microchip Technology Inc.

25.1

EUSART Asynchronous Mode

The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a V

OH

mark state which represents a ‘

1

’ data bit, and a V

OL

space state which represents a ‘

0

’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud

Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See

Table 25-5

for examples of baud rate configurations.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit.

25.1.1

EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 25-1

. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register.

25.1.1.1

Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits:

• TXEN =

1

• SYNC =

0

• SPEN =

1

All other EUSART control bits are assumed to be in their default state.

Setting the TXEN bit of the TXxSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the

RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the

TXx/CKx I/O pin as an output. If the TXx/CKx pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit.

Note:

The TXxIF transmitter interrupt flag is set when the TXEN enable bit is set.

PIC16(L)F1946/47

25.1.1.2

Transmitting Data

A transmission is initiated by writing a character to the

TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one T

CY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the

TXxREG.

25.1.1.3

Transmit Data Polarity

The polarity of the transmit data can be controlled with the CKTXP bit of the BAUDxCON register. The default state of this bit is ‘

0

’ which selects high true transmit idle and data bits. Setting the CKTXP bit to ‘

1

’ will invert the transmit data resulting in low true idle and data bits.

The CKTXP bit controls transmit data polarity only in

Asynchronous mode. In Synchronous mode the

CKTXP bit has a different function. See

Section 25.5.1.2 “Clock Polarity”

.

25.1.1.4

Transmit Interrupt Flag

The TXxIF interrupt flag bit of the PIR1/PIR3 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the

TXxREG. In other words, the TXxIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the

TXxREG. The TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle following the write execution.

Polling TXxIF immediately following the TXxREG write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software.

The TXxIF interrupt can be enabled by setting the

TXxIE interrupt enable bit of the PIE1/PIE4 register.

However, the TXxIF flag bit will be set whenever the

TXxREG is empty, regardless of the state of TXxIE enable bit.

To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the

TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG.

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PIC16(L)F1946/47

25.1.1.5

TSR Status

The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status.

Note:

The TSR register is not mapped in data memory, so it is not available to the user.

25.1.1.6

Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXxSTA register is set the

EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written.

A special 9-bit Address mode is available for use with

multiple receivers. See

Section 25.1.2.8 “Address

Detection”

for more information on the Address mode.

FIGURE 25-3:

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

TXxIF bit

(Transmit Buffer

Reg. Empty Flag)

ASYNCHRONOUS TRANSMISSION

Word 1

Start bit

1 T

CY bit 0 bit 1

Word 1

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg

25.1.1.7

1.

2.

3.

4.

5.

6.

7.

8.

9.

Asynchronous Transmission Set-up:

Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see

Section 25.4 “EUSART

Baud Rate Generator (BRG)”

).

Set the RXx/DTx and TXx/CKx TRIS controls to

1

’.

Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit.

If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection.

Set the CKTXP control bit if inverted transmit data polarity is desired.

Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set.

If interrupts are desired, set the TXxIE interrupt enable bit. An interrupt will occur immediately provided that the GIE and PEIE bits of the

INTCON register are also set.

If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit.

Load 8-bit data into the TXxREG register. This will start the transmission.

bit 7/8

Stop bit

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PIC16(L)F1946/47

FIGURE 25-4:

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

TXxIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Word 1 Word 2

1 T

CY

Start bit bit 0

1 T

CY

Word 1

Transmit Shift Reg bit 1

Word 1 bit 7/8

Stop bit

Start bit

Word 2 bit 0

Word 2

Transmit Shift Reg

Note:

This timing diagram shows two consecutive transmissions.

TABLE 25-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BAUD1CON

BAUD2CON

INTCON

PIE1

PIE4

PIR1

PIR4

RC1STA

RC2STA

SP1BRGL

SP1BRGH

SP2BRGL

SP2BRGH

TX1REG

TX1STA

TX2REG

TX2STA

Legend:

*

ABDOVF

ABDOVF

GIE

SPEN

SPEN

RCIDL

RCIDL

PEIE

ADIE

ADIF

RX9

RX9

TMR0IE

RC1IE

RC2IE

RC1IF

SCKP

SCKP

INTE

TX1IE

TX2IE

TX1IF

BRG16

BRG16

IOCIE

SSP1IE

SSP1IF

TMR0IF

CCP1IE

CCP1IF

RC2IF

SREN

TX2IF

CREN

ADDEN

FERR

SREN CREN ADDEN FERR

EUSART1 Baud Rate Generator, Low Byte

EUSART1 Baud Rate Generator, High Byte

EUSART2 Baud Rate Generator, Low Byte

EUSART2 Baud Rate Generator, High Byte

EUSART1 Transmit Register

WUE

WUE

INTF

TMR2IE

BCL2IE

TMR2IF

BCL2IF

OERR

OERR

CSRC TX9 TXEN SYNC SENDB

EUSART2 Transmit Register

BRGH TRMT TX9D

CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

— = unimplemented locations, read as ‘

0

’. Shaded bits are not used for asynchronous transmission.

Page provides register information.

ABDEN

ABDEN

IOCIF

TMR1IE

SSP2IE

TMR1IF

SSP2IF

RX9D

RX9D

Register on page

100

308

308

310

*

310

*

310

*

310

*

302

*

309

309

92

93

96

97

307

302

*

307

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25.1.2

EUSART ASYNCHRONOUS

RECEIVER

The Asynchronous mode would typically be used in

RS-232 systems. The receiver block diagram is shown in

Figure 25-2

. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial

Receive Shift Register (RSR) operates at the bit rate.

When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character

First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software.

Access to the received data is via the RCxREG register.

25.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits:

• CREN =

1

• SYNC =

0

• SPEN =

1

All other EUSART control bits are assumed to be in their default state.

Setting the CREN bit of the RCxSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the

RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RXx/DTx I/O pin as an input.

Note 1:

If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function.

If the RXx/DTx pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit.

25.1.2.2

Receiving Data

The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘

0

’ or ‘

1

’ is shifted into the RSR.

This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘

1

’. If the data recovery circuit samples a ‘

0

’ in the

Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this

character. See

Section 25.1.2.5 “Receive Framing

Error”

for more information on framing errors.

Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCxIF interrupt flag bit of the PIR1/PIR3 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register.

Note:

If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See

Section 25.1.2.6

“Receive Overrun Error”

for more information on overrun errors.

25.1.2.3

Receive Data Polarity

The polarity of the receive data can be controlled with the DTRXP bit of the BAUDxCON register. The default state of this bit is ‘

0

’ which selects high true receive idle and data bits. Setting the DTRXP bit to ‘

1

’ will invert the receive data resulting in low true idle and data bits. The

DTRXP bit controls receive data polarity only in

Asynchronous mode. In synchronous mode the

DTRXP bit has a different function.

2010-2012 Microchip Technology Inc.

DS41414D-page 302

25.1.2.4

Receive Interrupts

The RCxIF interrupt flag bit of the PIR1/PIR3 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The

RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software.

RCxIF interrupts are enabled by setting the following bits:

• RCxIE interrupt enable bit of the PIE1/PIE4 register

• PEIE peripheral interrupt enable bit of the INTCON register

• GIE global interrupt enable bit of the INTCON register

The RCxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.

25.1.2.5

Receive Framing Error

Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the

FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG.

The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error

(FERR =

1

) does not preclude reception of additional characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART.

Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit.

25.1.2.6

Receive Overrun Error

The receive FIFO buffer can hold two characters. An overrun error will be generated If a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the

RCxSTA register.

PIC16(L)F1946/47

25.1.2.7

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set, the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCxREG.

25.1.2.8

Address Detection

A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register.

Address detection requires 9-bit character reception.

When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt bit. All other characters will be ignored.

Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

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25.1.2.9

Asynchronous Reception Set-up:

1.

2.

3.

4.

5.

6.

Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the

desired baud rate (see

Section 25.4 “EUSART

Baud Rate Generator (BRG)”

).

Set the RXx/DTx and TXx/CKx TRIS controls to

1

’.

Enable the serial port by setting the SPEN bit and the RXx/DTx pin TRIS bit. The SYNC bit must be clear for asynchronous operation.

If interrupts are desired, set the RCxIE interrupt enable bit and set the GIE and PEIE bits of the

INTCON register.

If 9-bit reception is desired, set the RX9 bit.

Set the DTRXP if inverted receive polarity is desired.

Enable reception by setting the CREN bit.

7.

8.

9.

The RCxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set.

Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit.

10. Get the received 8 Least Significant data bits from the receive buffer by reading the RCxREG register.

11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.

25.1.2.10

9-bit Address Detection Mode Set-up

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1.

2.

3.

4.

Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the

desired baud rate (see

Section 25.4 “EUSART

Baud Rate Generator (BRG)”

).

Set the RXx/DTx and TXx/CKx TRIS controls to

1

’.

Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous operation.

If interrupts are desired, set the RCxIE interrupt enable bit and set the GIE and PEIE bits of the

INTCON register.

Enable 9-bit reception by setting the RX9 bit.

5.

6.

7.

Enable address detection by setting the ADDEN bit.

Set the DTRXP if inverted receive polarity is desired.

8.

9.

Enable reception by setting the CREN bit.

The RCxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set.

10. Read the RCxSTA register to get the error flags.

The ninth data bit will always be set.

11. Get the received 8 Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device’s address.

12. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.

13. If the device has been addressed, clear the

ADDEN bit to allow all received data into the receive buffer and generate interrupts.

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FIGURE 25-5:

RXx/DTx pin

Rcv Shift

Reg

Rcv Buffer Reg

RCIDL

Read Rcv

Buffer Reg

RCxREG

RCxIF

(Interrupt Flag)

OERR bit

CREN

Note:

ASYNCHRONOUS RECEPTION

Start bit bit 0 bit 1 bit 7/8

Stop bit

Start bit bit 0

Word 1

RCxREG bit 7/8 Stop

Word 2

RCxREG bit

Start bit bit 7/8

Stop bit

This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.

TABLE 25-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BAUD1CON

BAUD2CON

INTCON

PIE1

PIE4

PIR1

PIR4

RC1REG

RC1STA

RC2REG

RC2STA

SP1BRGL

SP1BRGH

SP2BRGL

ABDOVF

ABDOVF

GIE

SPEN

SPEN

RCIDL

RCIDL

PEIE

ADIE

ADIF

RX9

RX9

TMR0IE

RC1IE

RC2IE

RC1IF

RC2IF

SCKP

SCKP

INTE

TX1IE

TX2IE

TX1IF

TX2IF

BRG16

BRG16

IOCIE

SSP1IE

SSP1IF

EUSART1 Receive Register

TMR0IF

CCP1IE

CCP1IF

SREN CREN ADDEN

EUSART2 Receive Register

FERR

SREN CREN ADDEN FERR

EUSART1 Baud Rate Generator, Low Byte

EUSART1 Baud Rate Generator, High Byte

EUSART2 Baud Rate Generator, Low Byte

WUE

WUE

INTF

TMR2IE

BCL2IE

TMR2IF

BCL2IF

OERR

OERR

ABDEN

ABDEN

IOCIF

TMR1IE

SSP2IE

TMR1IF

SSP2IF

RX9D

RX9D

SP2BRGH

TRISC

TX1STA

TX2STA

Legend:

*

TRISC7

CSRC

CSRC

TRISC6

TX9

TX9

EUSART2 Baud Rate Generator, High Byte

TRISC5

TXEN

TXEN

TRISC4

SYNC

SYNC

TRISC3

SENDB

SENDB

TRISC2

BRGH

BRGH

TRISC1

TRMT

TRMT

TRISC0

TX9D

TX9D

— = unimplemented locations, read as ‘

0

’. Shaded bits are not used for asynchronous reception.

Page provides register information.

Register on Page

100

302 *

308

302 *

308

310 *

310 *

310 *

309

309

92

93

96

97

310 *

137

302

307

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PIC16(L)F1946/47

25.2

Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as V

DD

or temperature changes, and this directly affects the asynchronous baud rate.

Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See

Section 5.2

“Clock Source Types”

for more information.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see

Section 25.4.1

“Auto-Baud Detect”

). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.

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2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

25.3

Register Definitions: EUSART Control

REGISTER 25-1:

bit 7

R/W-0

CSRC

TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

TX9

R/W-0

TXEN

(1)

R/W-0

SYNC

R/W-0

SENDB

R/W-0

BRGH

R-1

TRMT

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R/W-0

TX9D bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Note 1:

CSRC:

Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1

= Master mode (clock generated internally from BRG)

0

= Slave mode (clock from external source)

TX9:

9-bit Transmit Enable bit

1

= Selects 9-bit transmission

0

= Selects 8-bit transmission

TXEN:

Transmit Enable bit

(1)

1

= Transmit enabled

0

= Transmit disabled

SYNC:

EUSART Mode Select bit

1

= Synchronous mode

0

= Asynchronous mode

SENDB:

Send Break Character bit

Asynchronous mode:

1

= Send Sync Break on next transmission (cleared by hardware upon completion)

0

= Sync Break transmission completed

Synchronous mode:

Don’t care

BRGH:

High Baud Rate Select bit

Asynchronous mode:

1

= High speed

0

= Low speed

Synchronous mode:

Unused in this mode

TRMT:

Transmit Shift Register Status bit

1

= TSR empty

0

= TSR full

TX9D:

Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

SREN/CREN overrides TXEN in Sync mode.

2010-2012 Microchip Technology Inc.

DS41414D-page 307

PIC16(L)F1946/47

REGISTER 25-2:

bit 7

R/W-0

SPEN

RCxSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

ADDEN

R-0

FERR

R-0

OERR

R-x

RX9D bit 0

Legend:

R = Readable bit

-n = Value at POR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

SPEN:

Serial Port Enable bit

1

= Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)

0

= Serial port disabled (held in Reset)

RX9:

9-bit Receive Enable bit

1

= Selects 9-bit reception

0

= Selects 8-bit reception

SREN:

Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1

= Enables single receive

0

= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

CREN:

Continuous Receive Enable bit

Asynchronous mode:

1

= Enables receiver

0

= Disables receiver

Synchronous mode:

1

= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0

= Disables continuous receive

ADDEN:

Address Detect Enable bit

Asynchronous mode 9-bit (RX9 =

1

):

1

= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0

= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 =

0

):

Don’t care

FERR:

Framing Error bit

1

= Framing error (can be updated by reading RCxREG register and receive next valid byte)

0

= No framing error

OERR:

Overrun Error bit

1

= Overrun error (can be cleared by clearing bit CREN)

0

= No overrun error

RX9D:

Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

2010-2012 Microchip Technology Inc.

DS41414D-page 308

PIC16(L)F1946/47

REGISTER 25-3:

R-0/0

ABDOVF bit 7

BAUDxCON: BAUD RATE CONTROL REGISTER

R-1/1

RCIDL

U-0

R/W-0/0

SCKP

R/W-0/0

BRG16

U-0

R/W-0/0

WUE

R/W-0/0

ABDEN bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

ABDOVF:

Auto-Baud Detect Overflow bit

Asynchronous mode:

1

= Auto-baud timer overflowed

0

= Auto-baud timer did not overflow

Synchronous mode:

Don’t care

RCIDL

: Receive Idle Flag bit

Asynchronous mode:

1

= Receiver is Idle

0

= Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

Unimplemented:

Read as ‘

0

SCKP

: Synchronous Clock Polarity Select bit

Asynchronous mode:

1

= Transmit inverted data to the TXx/CKx pin

0

= Transmit non-inverted data to the TXx/CKx pin

Synchronous mode:

1

= Data is clocked on rising edge of the clock

0

= Data is clocked on falling edge of the clock

BRG16:

16-bit Baud Rate Generator bit

1

= 16-bit Baud Rate Generator is used

0

= 8-bit Baud Rate Generator is used

Unimplemented:

Read as ‘

0

WUE:

Wake-up Enable bit

Asynchronous mode:

1

= Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set.

0

= Receiver is operating normally

Synchronous mode:

Don’t care

ABDEN

: Auto-Baud Detect Enable bit

Asynchronous mode:

1

= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0

= Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

2010-2012 Microchip Technology Inc.

DS41414D-page 309

PIC16(L)F1946/47

25.4

EUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDxCON register selects 16-bit mode.

The SPxBRGH:SPxBRGL register pair determines the period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the

TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored.

Example 25-1 provides a sample calculation for deter-

mining the desired baud rate, actual baud rate, and baud rate % error.

Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in

Table 25-5

. It may be advantageous to use the high baud rate (BRGH =

1

), or the 16-bit BRG (BRG16 =

1

) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies.

Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate.

TABLE 25-3: BAUD RATE FORMULAS

Configuration Bits

SYNC BRG16 BRGH

1

1

Legend:

0

0

0

0

BRG/EUSART Mode

0 0

8-bit/Asynchronous

0 1

8-bit/Asynchronous

16-bit/Asynchronous

1 0

1 1

16-bit/Asynchronous

8-bit/Synchronous

0 x

1 x

16-bit/Synchronous x

= Don’t care, n = value of SPxBRGH, SPxBRGL register pair

If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock.

EXAMPLE 25-1: CALCULATING BAUD

RATE ERROR

For a device with F

OSC

of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

F

OS C

Desired Baud Rate =

+ 1

Solving for SPxBRGH:SPxBRGL:

SPxBRGH: SPxBRGL =

F

OS C

---------------------------------------------

64

1

=

1

64

=

25.042

= 25

ActualBaudRate

= ---------------------------

64 25 + 1

= 9615

Baud Rate % Error

=

=

Desired Baud Rate

Desired Baud Rate

9600

9600

= 0.16%

Baud Rate Formula

F

OSC

/[64 (n+1)]

F

OSC

/[16 (n+1)]

F

OSC

/[4 (n+1)]

2010-2012 Microchip Technology Inc.

DS41414D-page 310

PIC16(L)F1946/47

TABLE 25-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

BAUD1CON

BAUD2CON

RC1STA

RC2STA

SP1BRGL

SP1BRGH

SP2BRGL

ABDOVF

ABDOVF

SPEN

SPEN

RCIDL

RCIDL

RX9

RX9

SREN

SCKP

SCKP

CREN

BRG16

BRG16

ADDEN

FERR

SREN CREN ADDEN FERR

EUSART1 Baud Rate Generator, Low Byte

EUSART1 Baud Rate Generator, High Byte

EUSART2 Baud Rate Generator, Low Byte

SP2BRGH

TX1STA

TX2STA

Legend:

*

CSRC TX9

EUSART2 Baud Rate Generator, High Byte

TXEN SYNC SENDB BRGH

BRGH CSRC TX9 TXEN SYNC SENDB

— = unimplemented, read as ‘

0

’. Shaded bits are not used by the BRG.

Page provides register information.

Bit 1

WUE

WUE

OERR

OERR

TRMT

TRMT

Bit 0

ABDEN

ABDEN

RX9D

RX9D

TX9D

TX9D

Reset

Values on page

309

309

308

308

310 *

310 *

310 *

310 *

302

307

TABLE 25-5:

BAUD

RATE

300

1200

2400

9600

10417

19.2k

57.6k

115.2k

BAUD RATES FOR ASYNCHRONOUS MODES

F

OSC

= 32.000 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

2404

9615

10417

19.23k

55.55k

0.16

0.16

0.00

0.16

-3.55

207

51

47

25

3

SYNC =

0

, BRGH =

0

, BRG16 =

0

F

OSC

= 18.432 MHz F

OSC

= 16.000 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

Actual

Rate

%

Error

SPxBRGL value

(decimal)

1200

2400

0.00

0.00

239

119

1202

2404

0.16

0.16

207

103

9600

10286

19.20k

57.60k

0.00

-1.26

0.00

0.00

29

27

14

7

9615

10417

19.23k

0.16

0.00

0.16

25

23

12

F

OSC

= 11.0592 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

1200

2400

0.00

0.00

143

71

9600

10165

19.20k

57.60k

0.00

-2.42

0.00

0.00

17

16

8

2

BAUD

RATE

300

1200

2400

9600

10417

19.2k

57.6k

115.2k

F

OSC

= 8.000 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

1202

2404

9615

10417

0.16

0.16

0.16

0.00

103

51

12

11

Actual

Rate

300

1202

2404

10417

SYNC =

0

, BRGH =

0

, BRG16 =

0

F

OSC

= 4.000 MHz

%

Error

0.16

0.16

0.16

0.00

SPxBRGL value

(decimal)

207

51

25

5

F

OSC

= 3.6864 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

0.00

300

1200

2400

9600

19.20k

57.60k

0.00

0.00

0.00

0.00

0.00

191

47

23

5

2

0

F

OSC

= 1.000 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

300

1202

0.16

0.16

— —

51

12

2010-2012 Microchip Technology Inc.

DS41414D-page 311

PIC16(L)F1946/47

TABLE 25-5:

BAUD

RATE

300

1200

2400

9600

10417

19.2k

57.6k

115.2k

BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

F

OSC

= 32.000 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

9615

10417

19.23k

57.14k

117.64k

0.16

0.00

0.16

-0.79

2.12

207

191

103

34

16

SYNC =

0

, BRGH =

1

, BRG16 =

0

Actual

Rate

F

OSC

= 18.432 MHz

%

Error

SPxBRGL value

(decimal)

F

Actual

Rate

OSC

= 16.000 MHz

%

Error

SPxBRGL value

(decimal)

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

0.00

0.00

119

110

59

19

9

9615

10417

19.23k

58.82k

111.1k

0.16

0.00

0.16

2.12

-3.55

103

95

51

16

8

F

OSC

= 11.0592 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

— — —

9600

10473

19.20k

57.60k

115.2k

0.00

0.53

0.00

0.00

0.00

71

65

35

11

5

BAUD

RATE

300

1200

2400

9600

10417

19.2k

57.6k

115.2k

F

OSC

= 8.000 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

2404

9615

10417

19231

55556

0.16

0.16

0.00

0.16

-3.55

207

51

47

25

8

SYNC =

0

, BRGH =

1

, BRG16 =

0

F

OSC

= 4.000 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

Actual

Rate

F

OSC

= 3.6864 MHz

%

Error

SPxBRGL value

(decimal)

1202

2404

9615

10417

19.23k

0.16

0.16

0.16

0.00

0.16

23

12

207

103

25

1200

2400

9600

10473

19.2k

57.60k

115.2k

0.00

0.00

0.00

0.53

0.00

0.00

0.00

21

11

3

1

191

95

23

F

OSC

= 1.000 MHz

Actual

Rate

%

Error

SPxBRGL value

(decimal)

300

1202

2404

10417

0.16

0.16

0.16

0.00

5

207

51

25

BAUD

RATE

300

1200

2400

9600

10417

19.2k

57.6k

115.2k

F

OSC

= 32.000 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.0

1200.1

2401

9615

0.00

0.02

-0.04

0.16

6666

3332

832

207

10417

19.23k

57.14k

117.6k

0.00

0.16

-0.79

2.12

191

103

34

16

SYNC =

0

, BRGH =

0

, BRG16 =

1

F

OSC

= 18.432 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.0

1200

2400

9600

0.00

0.00

0.00

0.00

3839

959

479

119

10378

19.20k

57.60k

115.2k

-0.37

0.00

0.00

0.00

110

59

19

9

Rate

2398

9615

F

OSC

= 16.000 MHz

Actual

300.03

1200.5

10417

19.23k

58.82k

111.11k

%

Error

0.01

0.04

-0.08

0.16

0.00

0.16

2.12

-3.55

SPxBRGH:

SPxBRGL

(decimal)

3332

832

416

103

95

51

16

8

F

OSC

= 11.0592 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.0

1200

2400

9600

0.00

0.00

0.00

0.00

2303

575

287

71

10473

19.20k

57.60k

115.2k

0.53

0.00

0.00

0.00

65

35

11

5

2010-2012 Microchip Technology Inc.

DS41414D-page 312

PIC16(L)F1946/47

TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

BAUD

RATE

300

1200

2400

9600

10417

19.2k

57.6k

115.2k

Actual

Rate

F

OSC

= 8.000 MHz

%

Error

SPxBRGH:

SPxBRGL

(decimal)

299.9

1199

2404

9615

10417

19.23k

55556

-0.02

-0.08

0.16

0.16

0.00

0.16

-3.55

47

25

8

1666

416

207

51

SYNC =

0

, BRGH =

0

, BRG16 =

1

Actual

Rate

F

OSC

= 4.000 MHz

%

Error

SPxBRGH:

SPxBRGL

(decimal)

Rate

F

Actual

OSC

= 3.6864 MHz

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.1

1202

2404

9615

10417

19.23k

0.04

0.16

0.16

0.16

0.00

0.16

23

12

832

207

103

25

300.0

1200

2400

9600

10473

19.20k

57.60k

115.2k

0.00

0.00

0.00

0.00

0.53

0.00

0.00

0.00

21

11

3

1

767

191

95

23

Actual

Rate

F

OSC

= 1.000 MHz

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.5

1202

2404

10417

0.16

0.16

0.16

0.00

5

207

51

25

BAUD

RATE

300

1200

2400

9600

10417

19.2k

57.6k

115.2k

F

OSC

= 32.000 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300

1200

2400

9604

10417

19.18k

57.55k

115.9

0.00

0.00

0.01

0.04

0.00

-0.08

-0.08

0.64

26666

6666

3332

832

767

416

138

68

SYNC =

0

, BRGH =

1

, BRG16 =

1

or SYNC =

1

, BRG16 =

1

F

OSC

= 18.432 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

Actual

Rate

F

OSC

= 16.000 MHz

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.0

1200

2400

9600

10425

19.20k

57.60k

115.2k

0.00

0.00

0.00

0.00

0.08

0.00

0.00

0.00

15359

3839

1919

479

441

239

79

39

300.0

1200.1

2399.5

9592

10417

19.23k

57.97k

114.29k

0.00

0.01

-0.02

-0.08

0.00

0.16

0.64

-0.79

13332

3332

1666

416

383

207

68

34

F

OSC

= 11.0592 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.0

1200

2400

9600

10433

19.20k

57.60k

115.2k

0.00

0.00

0.00

0.00

0.16

0.00

0.00

0.00

9215

2303

1151

287

264

143

47

23

BAUD

RATE

300

1200

2400

9600

10417

19.2k

57.6k

115.2k

F

OSC

= 8.000 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.0

1200

2401

9615

10417

19.23k

0.00

-0.02

0.04

0.16

0.00

0.16

6666

1666

832

207

191

103

57.14k

117.6k

-0.79

2.12

34

16

SYNC =

0

, BRGH =

1

, BRG16 =

1

or SYNC =

1

, BRG16 =

1

F

OSC

= 4.000 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.0

1200

2398

9615

10417

19.23k

0.01

0.04

0.08

0.16

0.00

0.16

3332

832

416

103

95

51

58.82k

111.1k

2.12

-3.55

16

8

Rate

2400

9600

F

OSC

= 3.6864 MHz

Actual

300.0

1200

10473

19.20k

57.60k

115.2k

%

Error

0.00

0.00

0.00

0.00

0.53

0.00

0.00

0.00

SPxBRGH:

SPxBRGL

(decimal)

3071

767

383

95

87

47

15

7

F

OSC

= 1.000 MHz

Actual

Rate

%

Error

SPxBRGH:

SPxBRGL

(decimal)

300.1

1202

2404

9615

10417

19.23k

0.04

0.16

0.16

0.16

0.00

0.16

832

207

103

25

23

12

2010-2012 Microchip Technology Inc.

DS41414D-page 313

PIC16(L)F1946/47

25.4.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection and calibration of the baud rate.

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG.

The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.

Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence

(

Figure 25.4.2

). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the

SPxBRGL begins counting up using the BRG counter

clock as shown in Table 25-6

. The fifth rising edge will occur on the RXx/DTx pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH:SPxBRGL register pair, the ABDEN bit is automatically cleared, and the RCxIF interrupt flag is set. A read operation on the RCxREG needs to be performed to clear the RCxIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register.

The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in

Table 25-6 . During ABD,

both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the

SPxBRGH and SPxBRGL registers are clocked at

1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed.

Note 1:

2:

If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see

Section 25.4.3 “Auto-Wake-up on

Break”

).

It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.

Some combinations of oscillator frequency and EUSART baud rates are not possible.

3:

During the auto-baud process, the auto-baud counter starts counting at 1.

Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPx-

BRGL register pair.

TABLE 25-6:

BRG16 BRGH

BRG COUNTER CLOCK

RATES

BRG Base

Clock

BRG ABD

Clock

0

0

1

1

Note:

0

F

OSC

/64 F

OSC

/512

1

F

OSC

/16 F

OSC

/128

0

F

OSC

/16 F

OSC

/128

1

F

OSC

/4 F

OSC

/32

During the ABD sequence, SPxBRGL and

SPxBRGH registers are both used as a

16-bit counter, independent of BRG16 setting.

FIGURE 25-6:

BRG Value

XXXXh

AUTOMATIC BAUD RATE CALIBRATION

0000h

RXx/DTx pin

Start

Edge #1 bit 0 bit 1

Edge #2 bit 2 bit 3

Edge #3 bit 4 bit 5

Edge #4 bit 6 bit 7

001Ch

Edge #5

Stop bit

BRG Clock

ABDEN bit

Set by User

RCIDL

RCxIF bit

(Interrupt)

Read

RCxREG

SPxBRGL

SPxBRGH

XXh

XXh

Note 1:

The ABD sequence requires the

EUSART

module to be configured in Asynchronous mode.

Auto Cleared

1Ch

00h

2010-2012 Microchip Technology Inc.

DS41414D-page 314

25.4.2

AUTO-BAUD OVERFLOW

During the course of automatic baud detection, the

ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RXx/DTx pin. Upon detecting the fifth

RXx/DTx edge, the hardware will set the RCxIF interrupt flag and clear the ABDEN bit of the BAUDxCON register. The RCxIF flag can be subsequently cleared by reading the RCxREG. The ABDOVF flag can be cleared by software directly.

To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the ABDOVF bit. The ABDOVF bit will remain set if the ABDEN bit is not cleared first.

25.4.3

AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line. This feature is available only in Asynchronous mode.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RXx/DTx is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the

RXx/DTx line. (This coincides with the start of a Sync

Break or a wake-up signal character for the LIN protocol.)

The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU

operating modes ( Figure 25-7 ), and asynchronously if

the device is in Sleep mode (

Figure 25-8 ). The interrupt

condition is cleared by reading the RCxREG register.

The WUE bit is automatically cleared by the low-to-high transition on the RXx line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.

PIC16(L)F1946/47

25.4.3.1

Special Considerations

Break Character

To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros.

When the wake-up is enabled the function works independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors.

Therefore, the initial character in the transmission must be all ‘

0

’s. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices.

Oscillator Startup Time

Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART.

WUE Bit

The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared by hardware by a rising edge on RXx/DTx. The interrupt condition is then cleared by software by reading the

RCxREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode.

2010-2012 Microchip Technology Inc.

DS41414D-page 315

PIC16(L)F1946/47

FIGURE 25-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

OSC1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Bit set by user

Auto Cleared

WUE bit

RXx/DTx Line

RCxIF

Cleared due to User Read of RCxREG

Note 1:

The

EUSART

remains in Idle while the WUE bit is set.

FIGURE 25-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

OSC1

Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4

Bit Set by User

WUE bit

RXx/DTx Line

RCxIF

Sleep Command Executed

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

Auto Cleared

Note 1

Cleared due to User Read of RCxREG

Sleep Ends

Note 1:

2:

If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc

signal is still active. This sequence should not depend on the presence of Q clocks.

The

EUSART

remains in Idle while the WUE bit is set.

DS41414D-page 316

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

25.4.4

BREAK CHARACTER SEQUENCE

The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘

0

’ bits and a Stop bit.

To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all

0

’s will be transmitted.

The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification).

The TRMT bit of the TXxSTA register indicates when the transmit operation is active or Idle, just as it does during

normal transmission. See Figure 25-9 for the timing of

the Break character sequence.

25.4.4.1

Break and Sync Transmit Sequence

The following sequence will start a message frame header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus master.

1.

2.

3.

4.

5.

Configure the EUSART for the desired mode.

Set the TXEN and SENDB bits to enable the

Break sequence.

Load the TXxREG with a dummy character to initiate transmission (the value is ignored).

Write ‘55h’ to TXxREG to load the Sync character into the transmit FIFO buffer.

After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted.

SEND BREAK CHARACTER SEQUENCE FIGURE 25-9:

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx (pin)

Dummy Write

Start bit bit 0

When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG.

25.4.5

RECEIVING A BREAK CHARACTER

The Enhanced EUSART module can receive a Break character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCxSTA register and the Received data as indicated by RCxREG. The Baud Rate

Generator is assumed to have been initialized to the expected baud rate.

A Break character has been received when;

• RCxIF bit is set

• FERR bit is set

• RCxREG = 00h

The second method uses the Auto-Wake-up feature described in

Section 25.4.3 “Auto-Wake-up on

Break”

. By enabling this feature, the EUSART will

sample the next two transitions on RXx/DTx, cause an

RCxIF interrupt, and receive the next data byte followed by another interrupt.

Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in

Sleep mode.

bit 1

Break bit 11

Stop bit

TXxIF bit

(Transmit interrupt Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB

(send Break control bit)

SENDB Sampled Here

Auto Cleared

2010-2012 Microchip Technology Inc.

DS41414D-page 317

PIC16(L)F1946/47

25.5

EUSART Synchronous Mode

Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry.

There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device.

Start and Stop bits are not used in synchronous transmissions.

25.5.1

SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART for Synchronous Master operation:

• SYNC =

1

• CSRC =

1

• SREN =

0

(for transmit); SREN =

1

(for receive)

• CREN =

0

(for transmit); CREN =

1

(for receive)

• SPEN =

1

Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXxSTA register configures the device as a master. Clearing the SREN and CREN bits of the

RCxSTA register ensures that the device is in the

Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. If the RXx/DTx or TXx/CKx pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding

ANSEL bits.

The TRIS bits corresponding to the RXx/DTx and

TXx/CKx pins should be set.

25.5.1.1

Master Clock

Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TXx/CKx line. The

TXx/CKx pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit.

Only as many clock cycles are generated as there are data bits.

25.5.1.2

Clock Polarity

A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the CKTXP bit of the BAUDxCON register. Setting the CKTXP bit sets the clock Idle state as high. When the CKTXP bit is set, the data changes on the falling edge of each clock and is sampled on the rising edge of each clock.

Clearing the CKTXP bit sets the Idle state as low. When the CKTXP bit is cleared, the data changes on the rising edge of each clock and is sampled on the falling edge of each clock.

25.5.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation.

A transmission is initiated by writing a character to the

TXxREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG.

Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge.

Note:

The TSR register is not mapped in data memory, so it is not available to the user.

25.5.1.4

Data Polarity

The polarity of the transmit and receive data can be controlled with the DTRXP bit of the BAUDxCON register. The default state of this bit is ‘

0

’ which selects high true transmit and receive data. Setting the DTRXP bit to ‘

1

’ will invert the data resulting in low true transmit and receive data.

2010-2012 Microchip Technology Inc.

DS41414D-page 318

PIC16(L)F1946/47

25.5.1.5

1.

2.

3.

Synchronous Master Transmission

Set-up:

Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the

desired baud rate (see

Section 25.4 “EUSART

Baud Rate Generator (BRG)”

).

Set the RXx/DTx and TXx/CKx TRIS controls to

1

’.

Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the

TRIS bits corresponding to the RXx/DTx and

TXx/CKx I/O pins.

FIGURE 25-10:

RXx/DTx pin

SYNCHRONOUS TRANSMISSION

TXx/CKx pin

(SCKP =

0

)

TXx/CKx pin

(SCKP =

1

)

Write to

TXxREG Reg

TXxIF bit

(Interrupt Flag)

TRMT bit

Write Word 1

bit 0 bit 1

Word 1

bit 2

Write Word 2

bit 7

4.

5.

6.

7.

8.

9.

Disable Receive mode by clearing bits SREN and CREN.

Enable Transmit mode by setting the TXEN bit.

If 9-bit transmission is desired, set the TX9 bit.

If interrupts are desired, set the TXxIE, GIE and

PEIE interrupt enable bits.

If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit.

Start transmission by loading data to the

TXxREG register.

bit 0 bit 1

Word 2

bit 7

TXEN bit

1

Note:

Sync Master mode, SPxBRGL =

0

, continuous transmission of two 8-bit words.

1

FIGURE 25-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RXx/DTx pin bit 0 bit 1 bit 2 bit 6 bit 7

TXx/CKx pin

Write to

TXxREG reg

TXxIF bit

TRMT bit

TXEN bit

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

TABLE 25-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

BAUD1CON

BAUD2CON

INTCON

PIE1

PIE4

PIR1

PIR4

RC1STA

ABDOVF

ABDOVF

GIE

SPEN

SPEN

RCIDL

RCIDL

PEIE

ADIE

ADIF

RX9

RX9

TMR0IE

RC1IE

RC2IE

RC1IF

RC2IF

SREN

SCKP

SCKP

INTE

TX1IE

TX2IE

TX1IF

TX2IF

CREN

BRG16

BRG16

IOCIE

SSP1IE

SSP1IF

ADDEN

TMR0IF

CCP1IE

CCP1IF

FERR

WUE

WUE

INTF

TMR2IE

BCL2IE

TMR2IF

BCL2IF

OERR

OERR

ABDEN

ABDEN

IOCIF

TMR1IE

SSP2IE

TMR1IF

SSP2IF

RX9D

RX9D RC2STA

SP1BRGL

SP1BRGH

SP2BRGL

SREN CREN ADDEN FERR

EUSART1 Baud Rate Generator, Low Byte

EUSART1 Baud Rate Generator, High Byte

EUSART2 Baud Rate Generator, Low Byte

308

310 *

310 *

310 *

SP2BRGH

TRISC

TX1REG

TX1STA

TX2REG

TX2STA

Legend:

*

TRISC7 TRISC6

EUSART2 Baud Rate Generator, High Byte

TRISC5 TRISC4 TRISC3 TRISC2

EUSART1 Transmit Register

TXEN SYNC SENDB BRGH

TRISC1 TRISC0

310 *

137

302 *

307

CSRC TX9 TRMT TX9D

CSRC TX9

EUSART2 Transmit Register

TXEN SYNC SENDB BRGH TRMT TX9D

302

307

— = unimplemented locations, read as ‘

0

’. Shaded bits are not used for synchronous master transmission.

Page provides register information.

*

96

97

100

308

309

309

92

93

DS41414D-page 320

2010-2012 Microchip Technology Inc.

25.5.1.6

Synchronous Master Reception

Data is received at the RXx/DTx pin. The RXx/DTx pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous master receive operation.

In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the

RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register).

When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge of the

TXx/CKx clock pin and is shifted into the Receive Shift

Register (RSR). When a complete character is received into the RSR, the RCxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in

RCxREG. The RCxIF bit remains set as long as there are un-read characters in the receive FIFO.

25.5.1.7

Slave Clock

Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TXx/CKx line. The

TXx/CKx pin output driver must be disabled by setting the associated TRIS bit when the device is configured for synchronous slave transmit or receive operation.

Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits.

25.5.1.8

Receive Overrun Error

The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the

RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading

RCxREG.

PIC16(L)F1946/47

If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the

CREN bit of the RCxSTA register or by clearing the

SPEN bit which resets the EUSART.

25.5.1.9

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCxREG.

25.5.1.10

Synchronous Master Reception

Set-up:

1.

2.

3.

4.

5.

6.

7.

Initialize the SPxBRGH, SPxBRGL register pair for the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve the desired baud rate.

Set the RXx/DTx and TXx/CKx TRIS controls to

1

’.

Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable

RXx/DTx and TXx/CKx output drivers by setting the corresponding TRIS bits.

Ensure bits CREN and SREN are clear.

If using interrupts, set the GIE and PEIE bits of the INTCON register and set RCxIE.

If 9-bit reception is desired, set bit RX9.

Start reception by setting the SREN bit or for continuous reception, set the CREN bit.

8.

9.

Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCxIE was set.

Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.

10. Read the 8-bit received data by reading the

RCxREG register.

11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART.

2010-2012 Microchip Technology Inc.

DS41414D-page 321

PIC16(L)F1946/47

FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RXx/DTx pin

TXx/CKx pin

(SCKP =

0

) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5

TXx/CKx pin

(SCKP =

1

)

Write to bit SREN

SREN bit

CREN bit

0

RCxIF bit

(Interrupt)

Read

RCxREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN =

1

and bit BRGH =

0

.

bit 6 bit 7

0

TABLE 25-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

BAUD1CON

BAUD2CON

INTCON

PIE1

PIE4

PIR1

ABDOVF

ABDOVF

GIE

RCIDL

RCIDL

PEIE

ADIE

ADIF

TMR0IE

RC1IE

RC2IE

RC1IF

SCKP

SCKP

INTE

TX1IE

TX2IE

TX1IF

BRG16

BRG16

IOCIE

SSP1IE

SSP1IF

TMR0IF

CCP1IE

CCP1IF

WUE

WUE

INTF

TMR2IE

BCL2IE

TMR2IF

BCL2IF

ABDEN

ABDEN

IOCIF

TMR1IE

SSP2IE

TMR1IF

SSP2IF PIR4

RC1REG

RC1STA

RC2REG

RC2STA

SP1BRGL

SP1BRGH

SP2BRGL

SPEN

SPEN

RX9

RX9

RC2IF TX2IF —

EUSART1 Receive Register

SREN CREN ADDEN

EUSART2 Receive Register

FERR

SREN CREN ADDEN FERR

EUSART1 Baud Rate Generator, Low Byte

EUSART1 Baud Rate Generator, High Byte

EUSART2 Baud Rate Generator, Low Byte

OERR

OERR

RX9D

RX9D

100

302

308

302

308

310

310

310

*

*

*

*

*

SP2BRGH

TX1STA

TX2STA

Legend:

*

CSRC

CSRC

TX9

TX9

EUSART2 Baud Rate Generator, High Byte

TXEN

TXEN

SYNC

SYNC

SENDB

SENDB

BRGH

BRGH

TRMT

TRMT

TX9D

TX9D

— = unimplemented locations, read as ‘

0

’. Shaded bits are not used for synchronous master reception.

Page provides register information.

310

*

302

307

309

309

92

93

96

97

2010-2012 Microchip Technology Inc.

DS41414D-page 322

25.5.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART for Synchronous slave operation:

• SYNC =

1

• CSRC =

0

• SREN =

0

(for transmit); SREN =

1

(for receive)

• CREN =

0

(for transmit); CREN =

1

(for receive)

• SPEN =

1

Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the

CSRC bit of the TXxSTA register configures the device as a slave. Clearing the SREN and CREN bits of the

RCxSTA register ensures that the device is in the

Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. If the RXx/DTx or TXx/CKx pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding

ANSEL bits.

RXx/DTx and TXx/CKx pin output drivers must be disabled by setting the corresponding TRIS bits.

25.5.2.1

EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave modes are identical (see

Section 25.5.1.3

“Synchronous Master Transmission” )

, except in the case of the Sleep mode.

PIC16(L)F1946/47

If two words are written to the TXxREG and then the

SLEEP

instruction is executed, the following will occur:

1.

2.

3.

4.

5.

The first character will immediately transfer to the TSR register and transmit.

The second word will remain in TXxREG register.

The TXxIF bit will not be set.

After the first character has been shifted out of

TSR, the TXxREG register will transfer the second character to the TSR and the TXxIF bit will now be set.

If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.

5.

6.

7.

25.5.2.2

1.

2.

3.

4.

8.

Synchronous Slave Transmission

Set-up:

Set the SYNC and SPEN bits and clear the

CSRC bit.

Set the RXx/DTx and TXx/CKx TRIS controls to

1

’.

Clear the CREN and SREN bits.

If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the

TXxIE bit.

If 9-bit transmission is desired, set the TX9 bit.

Enable transmission by setting the TXEN bit.

If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

Start transmission by writing the Least

Significant 8 bits to the TXxREG register.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

TABLE 25-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

BAUD1CON

BAUD2CON

INTCON

PIE1

PIE4

PIR1

PIR4

RC1STA

ABDOVF

ABDOVF

GIE

SPEN

SPEN

RCIDL

RCIDL

PEIE

ADIE

ADIF

RX9

RX9

TMR0IE

RC1IE

RC2IE

RC1IF

RC2IF

SREN

SCKP

SCKP

INTE

TX1IE

TX2IE

TX1IF

TX2IF

CREN

BRG16

BRG16

IOCIE

SSP1IE

SSP1IF

ADDEN

TMR0IF

CCP1IE

CCP1IF

FERR

WUE

WUE

INTF

TMR2IE

BCL2IE

TMR2IF

BCL2IF

OERR

OERR

ABDEN

ABDEN

IOCIF

TMR1IE

SSP2IE

TMR1IF

SSP2IF

RX9D

RX9D RC2STA

SP1BRGL

SP1BRGH

SP2BRGL

SREN CREN ADDEN FERR

EUSART1 Baud Rate Generator, Low Byte

EUSART1 Baud Rate Generator, High Byte

EUSART2 Baud Rate Generator, Low Byte

308

310 *

310 *

310 *

SP2BRGH

TRISC

TX1REG

TX1STA

TX2REG

TX2STA

Legend:

*

TRISC7 TRISC6

EUSART2 Baud Rate Generator, High Byte

TRISC5 TRISC4 TRISC3 TRISC2

TXEN

EUSART1 Transmit Register

SYNC SENDB BRGH

TRISC1 TRISC0

310 *

137

302 *

307

CSRC TX9 TRMT TX9D

CSRC TX9 TXEN

EUSART2 Transmit Register

SYNC SENDB BRGH TRMT TX9D

— = unimplemented locations, read as ‘

0

’. Shaded bits are not used for synchronous slave transmission.

Page provides register information.

302 *

307

96

97

100

308

309

309

92

93

DS41414D-page 324

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

25.5.2.3

EUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave modes is identical (

Section 25.5.1.6 “Synchronous

Master Reception”

), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is never Idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RCxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector.

4.

5.

6.

25.5.2.4

1.

2.

3.

7.

8.

9.

Synchronous Slave Reception

Set-up:

Set the SYNC and SPEN bits and clear the

CSRC bit.

Set the RXx/DTx and TXx/CKx TRIS controls to

1

’.

If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the

RCxIE bit.

If 9-bit reception is desired, set the RX9 bit.

Set the CREN bit to enable reception.

The RCxIF bit will be set when reception is complete. An interrupt will be generated if the

RCxIE bit was set.

If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCxSTA register.

Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCxREG register.

If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART.

TABLE 25-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BAUD1CON

BAUD2CON

INTCON

PIE1

PIE4

PIR1

ABDOVF

ABDOVF

GIE

RCIDL

RCIDL

PEIE

ADIE

ADIF

TMR0IE

RC1IE

RC2IE

RC1IF

SCKP

SCKP

INTE

TX1IE

TX2IE

TX1IF

BRG16

BRG16

IOCIE

SSP1IE

SSP1IF

TMR0IF

CCP1IE

CCP1IF

WUE

WUE

INTF

TMR2IE

BCL2IE

TMR2IF

BCL2IF

ABDEN

ABDEN

IOCIF

TMR1IE

SSP2IE

TMR1IF

SSP2IF PIR4

RC1REG

RC1STA

RC2REG

RC2STA

SP1BRGL

SP1BRGH

SP2BRGL

SPEN

SPEN

RX9

RX9

RC2IF

SREN

SREN

TX2IF

EUSART1 Receive Register

CREN ADDEN

EUSART2 Receive Register

CREN

ADDEN

FERR

FERR

EUSART1 Baud Rate Generator, Low Byte

EUSART1 Baud Rate Generator, High Byte

EUSART2 Baud Rate Generator, Low Byte

OERR

OERR

RX9D

RX9D

SP2BRGH

TX1STA

TX2STA

Legend:

*

CSRC

CSRC

TX9

TX9

EUSART2 Baud Rate Generator, High Byte

TXEN

TXEN

SYNC

SYNC

SENDB

SENDB

BRGH

BRGH

TRMT

TRMT

TX9D

TX9D

— = unimplemented locations, read as ‘

0

’. Shaded bits are not used for synchronous slave reception.

Page provides register information.

Register on Page

100

302 *

308

302 *

308

310 *

310 *

310 *

309

309

92

93

96

97

310 *

302

307

2010-2012 Microchip Technology Inc.

DS41414D-page 325

PIC16(L)F1946/47

NOTES:

DS41414D-page 326

2010-2012 Microchip Technology Inc.

CPS0

CPS1

CPS2

CPS3

CPS4

CPS5

CPS6

CPS7

CPS8

CPS9

CPS10

CPS11

CPS12

CPS13

CPS14

CPS15

CPS16

26.0

CAPACITIVE SENSING (CPS)

MODULE

The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the

CPS module. The CPS module requires software and at least one timer resource to determine the change in frequency. Key features of this module include:

• Analog MUX for monitoring multiple inputs

• Capacitive sensing oscillator

• Multiple power modes

• Multiple current ranges

• Multiple voltage reference modes

• Software control

• Operation during Sleep

FIGURE 26-1: CAPACITIVE SENSING BLOCK DIAGRAM

PIC16(L)F1946/47

CPSCH<3:0>

CPSON

(1)

CPSRNG<1:0>

CPSON

T0CKI

T0XCS

0

1

Capacitive

Sensing

Oscillator

CPSOSC

CPSCLK

Ref-

0

1

Int.

Ref.

DAC

Output

0

Ref+

1 FVR

CPSOUT

F

OSC

/4

0

1

Timer0 Module

TMR0CS

TMR0

Overflow

Set

TMR0IF

TMR1CS<1:0>

F

OSC

F

OSC

/4

T1OSC/

T1CKI

T1GSEL<1:0>

T1G sync_C1OUT sync_C2OUT

Timer1 Module

EN

TMR1H:TMR1L

Timer1 Gate

Control Logic

CPSRM

Note 1:

If CPSON =

0

, disabling capacitive sensing, no channel is selected.

2010-2012 Microchip Technology Inc.

DS41414D-page 327

PIC16(L)F1946/47

FIGURE 26-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM

Oscillator Module

CPSx

Analog Pin

V

DD

(1)

+

-

(2)

(1)

-

+

(2)

S

R

Q

Ref-

0

1 DAC

Ref+

0

1 FVR

Internal

References

CPSRM

Note 1:

2:

Module Enable and Power mode selections are not shown.

Comparators remain active in Noise Detection mode.

CPSCLK

2010-2012 Microchip Technology Inc.

DS41414D-page 328

26.1

Analog MUX

The CPS module can monitor up to 16 inputs. The capacitive sensing inputs are defined as CPS<15:0>.

To determine if a frequency change has occurred the user must:

• Select the appropriate CPS pin by setting the appropriate CPSCH bits of the CPSCON1 register.

• Set the corresponding ANSEL bit.

• Set the corresponding TRIS bit.

• Run the software algorithm.

Selection of the CPSx pin while the module is enabled will cause the capacitive sensing oscillator to be on the

CPSx pin. Failure to set the corresponding ANSEL and

TRIS bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings.

26.2

Capacitive Sensing Oscillator

The capacitive sensing oscillator consists of a constant current source and a constant current sink, to produce a triangle waveform. The CPSOUT bit of the

CPSCON0 register shows the status of the capacitive sensing oscillator, whether it is a sinking or sourcing current. The oscillator is designed to drive a capacitive load (single PCB pad) and at the same time, be a clock source to either Timer0 or Timer1. The oscillator has three different current settings as defined by

CPSRNG<1:0> of the CPSCON0 register. The different current settings for the oscillator serve two purposes:

• Maximize the number of counts in a timer for a fixed time base.

• Maximize the count differential in the timer during a change in frequency.

PIC16(L)F1946/47

26.2.1

VOLTAGE REFERENCE MODES

The capacitive sensing oscillator uses voltage references to provide two voltage thresholds for oscillation.

The upper voltage threshold is referred to as Ref+ and the lower voltage threshold is referred to as Ref-.

The user can elect to use fixed voltage references, which are internal to the capacitive sensing oscillator, or variable voltage references, which are supplied by the Fixed Voltage Reference (FVR) module and the

Digital-to-Analog Converter (DAC) module.

When the fixed voltage references are used, the V

SS voltage determines the lower threshold level (Ref-) and the V

DD

voltage determines the upper threshold level

(Ref+).

When the variable voltage references are used, the

DAC voltage determines the lower threshold level

(Ref-) and the FVR voltage determines the upper threshold level (Ref+). An advantage of using these reference sources is that oscillation frequency remains constant with changes in V

DD

.

Different oscillation frequencies can be obtained through the use of these variable voltage references.

The more the upper voltage reference level is lowered and the more the lower voltage reference level is raised, the higher the capacitive sensing oscillator frequency becomes.

Selection between the voltage references is controlled by the CPSRM bit of the CPSCON0 register. Setting this bit selects the variable voltage references and clearing this bit selects the fixed voltage references.

Please see

Section 14.0 “Fixed Voltage Reference

(FVR)”

and

Section 17.0 “Digital-to-Analog Converter

(DAC) Module”

for more information on configuring the

variable voltage levels.

2010-2012 Microchip Technology Inc.

DS41414D-page 329

PIC16(L)F1946/47

26.2.2

CURRENT RANGES

The capacitive sensing oscillator can operate in one of seven different power modes. The power modes are separated into two ranges; the low range and the high range.

When the oscillator’s low range is selected, the fixed internal voltage references of the capacitive sensing oscillator are being used. When the oscillator’s high range is selected, the variable voltage references supplied by the FVR and DAC modules are being used.

Selection between the voltage references is controlled by the CPSRM bit of the CPSCON0 register. See

Section 26.2.1 “Voltage Reference Modes”

for more information.

Within each range there are three distinct Power modes; low, medium and high. Current consumption is dependent upon the range and mode selected. Selecting Power modes within each range is accomplished by configuring the CPSRNG <1:0> bits in the CPSCON0 register. See

Table 26-1 for proper Power mode selection.

The remaining mode is a Noise Detection mode that resides within the high range. The Noise Detection mode is unique in that it disables the sinking and sourcing of current on the analog pin but leaves the rest of the oscillator circuitry active. This reduces the oscillation frequency on the analog pin to zero and also greatly reduces the current consumed by the oscillator module.

When noise is introduced onto the pin, the oscillator is driven at the frequency determined by the noise. This produces a detectable signal at the comparator output, indicating the presence of activity on the pin.

Figure 26-2 shows a more detailed drawing of the

current sources and comparators associated with the oscillator.

TABLE 26-1: POWER MODE SELECTION

CPSRM

Note 1:

Range CPSRNG<1:0> Current Range

00

01

Noise Detection

Low

1

High

10

Medium

11

00

High

Off

01

Low

0

Low

10

11

See

Section 30.0 “Electrical Specifications”

for more information.

Medium

High

26.2.3

TIMER RESOURCES

To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base.

26.2.4

FIXED TIME BASE

To measure the frequency of the capacitive sensing oscillator, a fixed time base is required. Any timer resource or software loop can be used to establish the fixed time base. It is up to the end user to determine the method in which the fixed time base is generated.

Note:

The fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking.

Nominal Current

(1)

0.0

A

9

A

30

A

100

A

0.0

A

0.25

A

1.5

A

7.5

A

26.2.4.1

Timer0

To select Timer0 as the timer resource for the CPS module:

• Set the T0XCS bit of the CPSCON0 register.

• Clear the TMR0CS bit of the OPTION_REG register.

When Timer0 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for

Timer0. Refer to

Section 20.0 “Timer0 Module”

for

additional information.

2010-2012 Microchip Technology Inc.

DS41414D-page 330

26.2.4.2

Timer1

To select Timer1 as the timer resource for the CPS module, set the TMR1CS<1:0> of the T1CON register to ‘

11

’. When Timer1 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for the frequency measurement can be simplified by using the Timer0 overflow flag.

It is recommend that the Timer0 overflow flag, in conjunction with the Toggle mode of the Timer1 Gate, be used to develop the fixed time base required by the soft-

ware portion of the CPS module. Refer to

Section 21.11

“Register Definitions: Timer1 Control”

for additional information.

TABLE 26-2:

TMR1ON

0

0

1

1

TIMER1 ENABLE FUNCTION

TMR1GE Timer1 Operation

0

1

0

1

Off

Off

On

Count Enabled by input

26.2.5

SOFTWARE CONTROL

The software portion of the CPS module is required to determine the change in frequency of the capacitive sensing oscillator. This is accomplished by the following:

• Setting a fixed time base to acquire counts on

Timer0 or Timer1.

• Establishing the nominal frequency for the capacitive sensing oscillator.

• Establishing the reduced frequency for the capacitive sensing oscillator due to an additional capacitive load.

• Set the frequency threshold.

26.2.5.1

Nominal Frequency

(No Capacitive Load)

To determine the nominal frequency of the capacitive sensing oscillator:

• Remove any extra capacitive load on the selected

CPSx pin.

• At the start of the fixed time base, clear the timer resource.

• At the end of the fixed time base save the value in the timer resource.

The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base.

PIC16(L)F1946/47

26.2.5.2

Reduced Frequency (additional capacitive load)

The extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. To determine the reduced frequency of the capacitive sensing oscillator:

• Add a typical capacitive load on the selected

CPSx pin.

• Use the same fixed time base as the nominal frequency measurement.

• At the start of the fixed time base, clear the timer resource.

• At the end of the fixed time base save the value in the timer resource.

The value of the timer resource is the number of oscillations of the capacitive sensing oscillator with an additional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base.

This frequency should be less than the value obtained during the nominal frequency measurement.

26.2.5.3

Frequency Threshold

The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator.

Refer to Application Note AN1103, “

Software Handling for Capacitive Sensing

” (DS01103) for more detailed information on the software required for CPS module.

Note:

For more information on general capacitive sensing refer to Application Notes:

• AN1101, “

Introduction to Capacitive

Sensing

” (DS01101)

• AN1102, “

Layout and Physical

Design Guidelines for Capacitive

Sensing

” (DS01102)

2010-2012 Microchip Technology Inc.

DS41414D-page 331

PIC16(L)F1946/47

26.3

Operation during Sleep

The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts.

Note:

Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep.

DS41414D-page 332

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

26.4

Register Definitions: Capacitive Sensing Control

REGISTER 26-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0

R/W-0/0

CPSON bit 7

R/W-0/0

CPSRM

U-0

U-0

R/W-0/0 R/W-0/0

CPSRNG<1:0>

R-0/0

CPSOUT

R/W-0/0

T0XCS bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5-4 bit 3-2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

CPSON:

CPS Module Enable bit

1

= CPS module is enabled

0

= CPS module is disabled

CPSRM:

Capacitive Sensing Reference Mode bit

1

= CPS module is in high range. DAC and FVR provide oscillator voltage references.

0

= CPS module is in the low range. Internal oscillator voltage references are used.

Unimplemented:

Read as ‘

0

CPSRNG<1:0>:

Capacitive Sensing Current Range bits

If CPSRM =

0

(low range):

11

= Oscillator is in High Range. Charge/Discharge Current is nominally 18 µA

10

= Oscillator is in Medium Range. Charge/Discharge Current is nominally 1.2 µA

01

= Oscillator is in Low Range. Charge/Discharge Current is nominally 0.1 µA

00

= Oscillator is off

If CPSRM =

1

(high range):

11

= Oscillator is in High Range. Charge/Discharge Current is nominally 100 µA

10

= Oscillator is in Medium Range. Charge/Discharge Current is nominally 30 µA

01

= Oscillator is in Low Range. Charge/Discharge Current is nominally 9 µA

00

= Oscillator is on. Noise Detection mode. No Charge/Discharge current is supplied.

CPSOUT:

Capacitive Sensing Oscillator Status bit

1

= Oscillator is sourcing current (Current flowing out of the pin)

0

= Oscillator is sinking current (Current flowing into the pin)

T0XCS:

Timer0 External Clock Source Select bit

If TMR0CS =

1

:

The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0:

1

= Timer0 clock source is the capacitive sensing oscillator

0

= Timer0 clock source is the T0CKI pin

If TMR0CS =

0

:

Timer0 clock source is controlled by the core/Timer0 module and is F

OSC

/4

2010-2012 Microchip Technology Inc.

DS41414D-page 333

PIC16(L)F1946/47

REGISTER 26-2:

U-0

CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1

U-0

U-0

R/W-0/0 R/W-0/0 R/W-0/0

CPSCH<4:0>

R/W-0/0 bit 7

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-5 bit 4-0

Unimplemented:

Read as ‘

0

CPSCH<4:0>:

Capacitive Sensing Channel Select bits

If CPSON =

0

:

These bits are ignored. No channel is selected.

If CPSON =

1

:

00000

= channel 0, (CPS0)

00001

= channel 1, (CPS1)

00010

= channel 2, (CPS2)

00011

= channel 3, (CPS3)

00100

= channel 4, (CPS4)

00101

= channel 5, (CPS5)

00110

= channel 6, (CPS6)

00111

= channel 7, (CPS7)

01000

= channel 8, (CPS8)

01001

= channel 9, (CPS9)

01010

= channel 10, (CPS10)

01011

= channel 11, (CPS11)

01100

= channel 12, (CPS12)

01101

= channel 13, (CPS13)

01110

= channel 14, (CPS14)

01111

= channel 15, (CPS15)

.

10000

= channel 16, (CPS16)

10001

= Reserved. Do not use.

.

.

11111

= Reserved. Do not use.

TABLE 26-3:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELA

CPSCON0

CPSON

CPSRM

ANSA5

ANSA4

ANSA3 ANSA2

CPSRNG<1:0>

ANSA1

CPSOUT

CPSCON1

OPTION_REG

T1CON

TRISA

TRISB

TRISD

WPUEN

INTEDG

TMR1CS<1:0>

TRISA7

TRISB7

TRISA6

TRISB6

TMR0CS

T1CKPS<1:0>

TRISA5

TRISB5

TMR0SE

TRISA4

TRISB4

PSA

T1OSCEN

TRISA3

TRISB3

TRISD<7:0>

CPSCH<4:0>

PS2

T1SYNC

TRISA2

TRISB2

PS1

TRISA1

TRISB1

Legend:

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used by the CPS module.

ANSA0

T0XCS

PS0

TMR1ON

TRISA0

TRISB0

Register on Page

207

131

134

140

132

333

334

197

2010-2012 Microchip Technology Inc.

DS41414D-page 334

PIC16(L)F1946/47

27.0

LIQUID CRYSTAL DISPLAY

(LCD) DRIVER MODULE

The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16(L)F1946/47 device, the module drives the panels of up to four commons and up to 46 segments. The LCD module also provides control of the LCD pixel data.

The LCD driver module supports:

• Direct driving of LCD panel

• Three LCD clock sources with selectable prescaler

• Up to four common pins:

- Static (1 common)

- 1/2 multiplex (2 commons)

- 1/3 multiplex (3 commons)

- 1/4 multiplex (4 commons)

• Segment pins up to:

- 64 (PIC16(L)F1946/47)

• Static, 1/2 or 1/3 LCD Bias

FIGURE 27-1: LCD DRIVER MODULE BLOCK DIAGRAM

27.1

LCD Registers

The module contains the following registers:

• LCD Control register (LCDCON)

• LCD Phase register (LCDPS)

• LCD Reference Ladder register (LCDRL)

• LCD Contrast Control register (LCDCST)

• LCD Reference Voltage Control register

(LCDREF)

• Up to 6 LCD Segment Enable registers (LCDSEn)

• Up to 24 LCD data registers (LCDDATAn)

Data Bus

LCDDATAx

Registers

MUX

SEG<23:0>

To I/O Pads

(1)

Timing Control

LCDCON

LCDPS

LCDSEn

COM<3:0>

F

OSC

/256

T1OSC

LFINTOSC

Clock Source

Select and

Prescaler

To I/O Pads

(1)

Note 1:

These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module.

2010-2012 Microchip Technology Inc.

DS41414D-page 335

PIC16(L)F1946/47

TABLE 27-1: LCD SEGMENT AND DATA

REGISTERS

Device

# of LCD Registers

Segment

Enable

6

Data

24 PIC16(L)F1946/47

The LCDCON register (

Register 27-1 ) controls the

operation of the LCD driver module. The LCDPS regis-

ter ( Register 27-2

) configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B.

The LCDSEn registers (

Register 27-5 ) configure the

functions of the port pins.

The following LCDSEn registers are available:

• LCDSE0 SE<7:0>

• LCDSE1 SE<15:8>

LCDSE2 SE<23:16>

(1)

• LCDSE3 SE<31:24>

• LCDSE4 SE<39:32>

• LCDSE5 SE<45:40>

Once the module is initialized for the LCD panel, the individual bits of the LCDDATAn registers are cleared/set to represent a clear/dark pixel, respectively:

• LCDDATA0

• LCDDATA1

• LCDDATA2

• LCDDATA3

• LCDDATA4

SEG<7:0>COM0

SEG<15:8>COM0

SEG<23:16>COM0

SEG<7:0>COM1

SEG<15:8>COM1

• LCDDATA5

• LCDDATA6

• LCDDATA7

SEG<23:16>COM1

SEG<7:0>COM2

SEG<15:8>COM2

• LCDDATA8

• LCDDATA9

SEG<23:16>COM2

SEG<7:0>COM3

• LCDDATA10 SEG<15:8>COM3

• LCDDATA11 SEG<23:16>COM3

• LCDDATA12 SEG<31:24>COM0

• LCDDATA13 SEG<39:32>COM0

• LCDDATA14 SEG<45:40>COM0

• LCDDATA15 SEG<31:24>COM1

• LCDDATA16 SEG<39:32>COM1

• LCDDATA17 SEG<45:40>COM1

• LCDDATA18 SEG<31:24>COM2

• LCDDATA19 SEG<39:32>COM2

• LCDDATA20 SEG<45:40>COM2

• LCDDATA21 SEG<31:24>COM3

• LCDDATA22 SEG<39:32>COM3

• LCDDATA23 SEG<45:40>COM3

As an example, LCDDATAn is detailed in

Register 27-6

.

Once the module is configured, the LCDEN bit of the

LCDCON register is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN bit of the LCDCON register.

DS41414D-page 336

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

27.2

Register Definitions: Liquid Crystal Display (LCD) Control

REGISTER 27-1: LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER

R/W-0/0

LCDEN bit 7

R/W-0/0

SLPEN

R/C-0/0

WERR

U-0

R/W-0/0 R/W-0/0

CS<1:0>

R/W-1/1 R/W-1/1

LMUX<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3-2 bit 1-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

LCDEN:

LCD Driver Enable bit

1

= LCD driver module is enabled

0

= LCD driver module is disabled

SLPEN:

LCD Driver Enable in Sleep Mode bit

1

= LCD driver module is disabled in Sleep mode

0

= LCD driver module is enabled in Sleep mode

WERR:

LCD Write Failed Error bit

1

= LCDDATAn register written while the WA bit of the LCDPS register =

0

(must be cleared in software)

0

= No LCD write error

Unimplemented:

Read as ‘

0

CS<1:0>:

Clock Source Select bits

00

= F

OSC

/256

01

= T1OSC (Timer1)

1x

= LFINTOSC (31 kHz)

LMUX<1:0>:

Commons Select bits

Maximum Number of Pixels

LMUX<1:0> Multiplex Bias

00

01

10

11

Static (COM0)

1/2 (COM<1:0>)

1/3 (COM<2:0>)

1/4 (COM<3:0>)

PIC16F1946/47/

PIC16LF1946/47

46

92

138

184

Static

1/2 or 1/3

1/2 or 1/3

1/3

2010-2012 Microchip Technology Inc.

DS41414D-page 337

PIC16(L)F1946/47

REGISTER 27-2:

R/W-0/0

WFT bit 7

LCDPS: LCD PHASE REGISTER

R/W-0/0

BIASMD

R-0/0

LCDA

R-0/0

WA

R/W-0/0 R/W-0/0 R/W-1/1

LP<3:0>

R/W-1/1 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

WFT:

Waveform Type bit

1

= Type-B phase changes on each frame boundary

0

= Type-A phase changes within each common type

BIASMD:

Bias Mode Select bit

When LMUX<1:0> =

00

:

0

= Static Bias mode (do not set this bit to ‘

1

’)

When LMUX<1:0> =

01

:

1

= 1/2 Bias mode

0

= 1/3 Bias mode

When LMUX<1:0> =

10

:

1

= 1/2 Bias mode

0

= 1/3 Bias mode

When LMUX<1:0> =

11

:

0

= 1/3 Bias mode (do not set this bit to ‘

1

’)

LCDA:

LCD Active Status bit

1

= LCD driver module is active

0

= LCD driver module is inactive

WA:

LCD Write Allow Status bit

1

= Writing to the LCDDATAn registers is allowed

0

= Writing to the LCDDATAn registers is not allowed

LP<3:0>:

LCD Prescaler Selection bits

1111

= 1:16

1110

= 1:15

1101

= 1:14

1100

= 1:13

1011

= 1:12

1010

= 1:11

1001

= 1:10

1000

= 1:9

0111

= 1:8

0110

= 1:7

0101

= 1:6

0100

= 1:5

0011

= 1:4

0010

= 1:3

0001

= 1:2

0000

= 1:1

2010-2012 Microchip Technology Inc.

DS41414D-page 338

PIC16(L)F1946/47

REGISTER 27-3:

R/W-0/0

LCDIRE bit 7

LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER

R/W-0/0

LCDIRS

R/W-0/0

LCDIRI

U-0

R/W-0/0

VLCD3PE

R/W-0/0

VLCD2PE

R/W-0/0

VLCD1PE

U-0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

LCDIRE:

LCD Internal Reference Enable bit

1

= Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit

0

= Internal LCD Reference is disabled

LCDIRS:

LCD Internal Reference Source bit

If LCDIRE =

1:

0

= Internal LCD Contrast Control is powered by V

DD

1

= Internal LCD Contrast Control is powered by a 3.072V output of the FVR.

If LCDIRE =

0

:

Internal LCD Contrast Control is unconnected. LCD bandgap buffer is disabled.

LCDIRI:

LCD Internal Reference Ladder Idle Enable bit

Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’

1

= When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled.

0

= The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode.

Unimplemented:

Read as ‘

0

VLCD3PE:

VLCD3 Pin Enable bit

1

= The VLCD3 pin is connected to the internal bias voltage LCDBIAS3

(1)

0

= The VLCD3 pin is not connected

VLCD2PE:

VLCD2 Pin Enable bit

1

= The VLCD2 pin is connected to the internal bias voltage LCDBIAS2

(1)

0

= The VLCD2 pin is not connected

VLCD1PE:

VLCD1 Pin Enable bit

1

= The VLCD1 pin is connected to the internal bias voltage LCDBIAS1

(1)

0

= The VLCD1 pin is not connected

Unimplemented:

Read as ‘

0

Note 1:

Normal pin controls of TRISx and ANSELx are unaffected.

2010-2012 Microchip Technology Inc.

DS41414D-page 339

PIC16(L)F1946/47

REGISTER 27-4:

bit 7

U-0

LCDCST: LCD CONTRAST CONTROL REGISTER

U-0

U-0

U-0

U-0

R/W-0/0 R/W-0/0

LCDCST<2:0>

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-3 bit 2-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

Unimplemented:

Read as ‘

0

LCDCST<2:0>:

LCD Contrast Control bits

Selects the resistance of the LCD contrast control resistor ladder

Bit Value = Resistor ladder

000

= Minimum resistance (maximum contrast). Resistor ladder is shorted.

001

= Resistor ladder is at 1/7th of maximum resistance

010

= Resistor ladder is at 2/7th of maximum resistance

011

= Resistor ladder is at 3/7th of maximum resistance

100

= Resistor ladder is at 4/7th of maximum resistance

101

= Resistor ladder is at 5/7th of maximum resistance

110

= Resistor ladder is at 6/7th of maximum resistance

111

= Resistor ladder is at maximum resistance (minimum contrast).

DS41414D-page 340

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PIC16(L)F1946/47

REGISTER 27-5:

R/W-0/0

SEn bit 7

LCDSEn: LCD SEGMENT ENABLE REGISTERS

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

SEn:

Segment Enable bits

1

= Segment function of the pin is enabled

0

= I/O function of the pin is enabled

REGISTER 27-6: LCDDATAn: LCD DATA REGISTERS

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy bit 7 bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

SEGx-COMy:

Pixel On bits

1

= Pixel on (dark)

0

= Pixel off (clear)

R/W-0/0

SEn bit 0

2010-2012 Microchip Technology Inc.

DS41414D-page 341

PIC16(L)F1946/47

27.3

LCD Clock Source Selection

The LCD module has 3 possible clock sources:

• F

OSC

/256

• T1OSC

• LFINTOSC

The first clock source is the system clock divided by

256 (F

OSC

/256). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz.

The divider is not programmable. Instead, the LCD prescaler bits LP<3:0> of the LCDPS register are used to set the LCD frame clock rate.

The second clock source is the T1OSC. This also gives about 1 kHz when a 32.768 kHz crystal is used with the

Timer1 oscillator. To use the Timer1 oscillator as a clock source, the T1OSCEN bit of the T1CON register should be set.

The third clock source is the 31 kHz LFINTOSC, which provides approximately 1 kHz output.

The second and third clock sources may be used to continue running the LCD while the processor is in

Sleep.

FIGURE 27-2: LCD CLOCK GENERATION

Using bits CS<1:0> of the LCDCON register can select any of these clock sources.

27.3.1

LCD PRESCALER

A 4-bit counter is available as a prescaler for the LCD clock. The prescaler is not directly readable or writable; its value is set by the LP<3:0> bits of the LCDPS register, which determine the prescaler assignment and prescale ratio.

The prescale values are selectable from 1:1 through

1:16.

F

OSC

÷256

T1OSC 32 kHz

Crystal Osc.

LFINTOSC

Nominal = 31 kHz

CS<1:0>

To Ladder

Power Control

÷4

÷2

Static

1/2

1/3,

1/4

4-bit Prog

Prescaler

÷ 32

Counter

Segment

Clock

÷1, 2, 3, 4

Ring Counter

LP<3:0>

LMUX<1:0>

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

27.4

LCD Bias Voltage Generation

The LCD module can be configured for one of three bias types:

• Static Bias (2 voltage levels: V

SS

and V

LCD

)

• 1/2 Bias (3 voltage levels: V

SS

, 1/2 V

LCD

and

V

LCD

)

• 1/3 Bias (4 voltage levels: V

SS

, 1/3 V

LCD

,

2/3 V

LCD

and V

LCD

)

FIGURE 27-3:

TABLE 27-2: LCD BIAS VOLTAGES

LCD Bias 0

LCD Bias 1

LCD Bias 2

LCD Bias 3

Static Bias

V

SS

V

LCD

3

1/2 Bias

V

SS

1/2 V

DD

1/2 V

DD

V

LCD

3

1/3 Bias

V

SS

1/3 V

DD

2/3 V

DD

V

LCD

3

So that the user is not forced to place external components and use up to three pins for bias voltage generation, internal contrast control and an internal reference ladder are provided internally to the PIC16(L)F1946/47. Both of these features may be used in conjunction with the external VLCD<3:1> pins, to provide maximum flexibility. Refer to

Figure 27-3 .

LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM

V

DD

LCDIRE

LCDIRS

LCDA

1.024V from

FVR x 3

3.072V

LCDIRE

LCDIRS

LCDA

LCDCST<2:0>

Power Mode Switching

(LRLAP or LRLBP)

2

A

B

2

2

VLCD3PE

LCDA

VLCD3 lcdbias3

VLCD2

VLCD2PE lcdbias2

BIASMD

VLCD1

VLCD1PE lcdbias1 lcdbias0

2010-2012 Microchip Technology Inc.

DS41414D-page 343

PIC16(L)F1946/47

27.5

LCD Bias Internal Reference

Ladder

The internal reference ladder can be used to divide the

LCD bias voltage two or three equally spaced voltages that will be supplied to the LCD segment pins. To create this, the reference ladder consists of three matched resistors. Refer to

Figure 27-3 .

27.5.1

BIAS MODE INTERACTION

When in 1/2 Bias mode (BIASMD =

1

), then the middle resistor of the ladder is shorted out so that only two voltages are generated. The current consumption of the ladder is higher in this mode, with the one resistor removed.

TABLE 27-3:

Power

Mode

Low

Medium

High

LCD INTERNAL LADDER

POWER MODES (1/3 BIAS)

Nominal Resistance of

Entire Ladder

3 Mohm

300 kohm

30 kohm

Nominal

I

DD

1 µA

10 µA

100 µA

27.5.2

POWER MODES

The internal reference ladder may be operated in one of three power modes. This allows the user to trade off LCD contrast for power in the specific application. The larger the LCD glass, the more capacitance is present on a physical LCD segment, requiring more current to maintain the same contrast level.

Three different power modes are available, LP, MP and

HP. The internal reference ladder can also be turned off for applications that wish to provide an external ladder or to minimize power consumption. Disabling the internal reference ladder results in all of the ladders being disconnected, allowing external voltages to be supplied.

Whenever the LCD module is inactive (LCDA = internal reference ladder will be turned off.

0

), the

DS41414D-page 344

2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47

27.5.3

AUTOMATIC POWER MODE

SWITCHING

As an LCD segment is electrically only a capacitor, current is drawn only during the interval where the voltage is switching. To minimize total device current, the LCD internal reference ladder can be operated in a different power mode for the transition portion of the duration.

This is controlled by the LCDRL Register

(

Register 27-7 ).

FIGURE 27-4:

The LCDRL register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time when the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT<2:0> bits select how long, if any, that the ‘A’ Power mode is active.

Refer to Figure 27-4

.

To implement this, the 5-bit prescaler used to divide the 32 kHz clock down to the LCD controller’s 1 kHz base rate is used to select the power mode.

LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –

TYPE A

Single Segment Time

32 kHz Clock

Ladder Power

Control

Segment Clock

LRLAT<2:0>

Segment Data

‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07

‘H3

‘H0E ‘H0F ‘H00 ‘H01

LRLAT<2:0>

Power Mode A Power Mode B Power Mode

COM0

SEG0

COM0-SEG0

V

1

V

0

V

1

V

0

V

1

V

0

-V

1

Mode A

2010-2012 Microchip Technology Inc.

DS41414D-page 345

FIGURE 27-5: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS

DRIVE)

Single Segment Time Single Segment Time

32 kHz Clock

Ladder Power

Control

Segment Clock

Segment Data

‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F

Power Mode Power Mode A

LRLAT<2:0> =

011

Power Mode B Power Mode A

LRLAT<2:0> =

011

Power Mode B

COM0-SEG0

V

2

V

1

V

0

-V

1

-V

2

FIGURE 27-6: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS

DRIVE)

Single Segment Time

32 kHz Clock

Ladder Power

Control

Segment Clock

‘H00 ‘H01 ‘H02 ‘H03

Single Segment Time

‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F

Single Segment Time

‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F

Single Segment Time

‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F

Segment Data

Power Mode Power Mode A

LRLAT<2:0> =

011

Power Mode B

Power Mode A

LRLAT<2:0> =

011

Power Mode B Power Mode A

LRLAT<2:0> =

011

Power Mode B

Power Mode A

LRLAT<2:0> =

011

Power Mode B

COM0-SEG0

V

2

V

1

V

0

-V

1

-V

2

PIC16(L)F1946/47

27.6

Register Definitions: LCD Ladder Control

REGISTER 27-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS

R/W-0/0 R/W-0/0

LRLAP<1:0> bit 7

R/W-0/0 R/W-0/0

LRLBP<1:0>

U-0

R/W-0/0 R/W-0/0

LRLAT<2:0>

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-4 bit 3 bit 2-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

LRLAP<1:0>:

LCD Reference Ladder A Time Power Control bits

During Time interval A (Refer to

Figure 27-4 ):

00

= Internal LCD Reference Ladder is powered down and unconnected

01

= Internal LCD Reference Ladder is powered in Low-Power mode

10

= Internal LCD Reference Ladder is powered in Medium-Power mode

11

= Internal LCD Reference Ladder is powered in High-Power mode

LRLBP<1:0>:

LCD Reference Ladder B Time Power Control bits

During Time interval B (Refer to

Figure 27-4 ):

00

= Internal LCD Reference Ladder is powered down and unconnected

01

= Internal LCD Reference Ladder is powered in Low-Power mode

10

= Internal LCD Reference Ladder is powered in Medium-Power mode

11

= Internal LCD Reference Ladder is powered in High-Power mode

Unimplemented:

Read as ‘

0

LRLAT<2:0>:

LCD Reference Ladder A Time interval control bits

Sets the number of 32 kHz clocks that the A Time interval power mode is active

For type A waveforms (WFT =

0

):

000

= Internal LCD Reference Ladder is always in ‘B’ Power mode

001

= Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 15 clocks

010

= Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 14 clocks

011

= Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 13 clocks

100

= Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 12 clocks

101

= Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 11 clocks

110

= Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 10 clocks

111

= Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 9 clocks

For type B waveforms (WFT =

1

):

000

= Internal LCD Reference Ladder is always in ‘B’ Power mode.

001

= Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 31 clocks

010

= Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 30 clocks

011

= Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 29 clocks

100

= Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 28 clocks

101

= Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 27 clocks

110

= Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 26 clocks

111

= Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 25 clocks

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

27.6.1

CONTRAST CONTROL

The LCD contrast control circuit consists of a seven-tap resistor ladder, controlled by the LCDCST

bits. Refer to Figure 27-7

.

The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST =

111

.

Whenever the LCD module is inactive (LCDA = contrast control ladder will be turned off (open).

0

), the

FIGURE 27-7:

V

DDIO

INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM

7 Stages

R R R R

3.072V

From FVR

Buffer

LCDCST<2:0>

3

Analog

MUX

7

To top of

Reference Ladder

0

Internal Reference

27.6.2

INTERNAL REFERENCE

Under firmware control, an internal reference for the

LCD bias voltages can be enabled. When enabled, the source of this voltage can be either V

DDIO

or a voltage

3 times the main fixed voltage reference (3.072V).

When no internal reference is selected, the LCD contrast control circuit is disabled and LCD bias must be provided externally.

Whenever the LCD module is inactive (LCDA = internal reference will be turned off.

0

), the

.

When the internal reference is enabled and the Fixed

Voltage Reference is selected, the LCDIRI bit can be used to minimize power consumption by tieing into the

LCD reference ladder automatic power mode switching.

When LCDIRI =

1

and the LCD reference ladder is in

Power mode ‘B’, the LCD internal FVR buffer is disabled.

Note:

The LCD module automatically turns on the

Fixed Voltage Reference when needed.

Contrast control

27.6.3

VLCD<3:1> PINS

The VLCD<3:1> pins provide the ability for an external

LCD bias network to be used instead of the internal ladder. Use of the VLCD<3:1> pins does not prevent use of the internal ladder. Each VLCD pin has an indepen-

dent control in the LCDREF register ( Register 27-3

), allowing access to any or all of the LCD Bias signals.

This architecture allows for maximum flexibility in different applications

For example, the VLCD<3:1> pins may be used to add capacitors to the internal reference ladder, increasing the drive capacity.

For applications where the internal contrast control is insufficient, the firmware can choose to only enable the

VLCD3 pin, allowing an external contrast control circuit to use the internal reference divider.

2010-2012 Microchip Technology Inc.

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PIC16(L)F1946/47

27.7

LCD Multiplex Types

The LCD driver module can be configured into one of four multiplex types:

• Static (only COM0 is used)

• 1/2 multiplex (COM<1:0> are used)

• 1/3 multiplex (COM<2:0> are used)

• 1/4 multiplex (COM<3:0> are used)

The LMUX<1:0> bit setting of the LCDCON register decides which of the LCD common pins are used (see

Table 27-4

for details).

If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. If the pin is a COM drive, then the TRIS setting of that pin is overridden.

TABLE 27-4:

Multiplex

LMUX

<1:0>

COMMON PIN USAGE

COM3 COM2 COM1

Static

1/2

1/3

1/4

00

01

10

11

Unused

Unused

Unused

Active

Unused

Unused

Active

Active

Unused

Active

Active

Active

COM0

Active

Active

Active

Active

27.8

Segment Enables

The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin’s alternate functions. To configure the pin as a segment pin, the corresponding bits in the

LCDSEn registers must be set to ‘

1

’.

If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSEn registers overrides any bit settings in the corresponding

TRIS register.

Note:

On a Power-on Reset, these pins are configured as normal I/O, not LCD pins.

27.9

Pixel Control

The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel.

Register 27-6

shows the correlation of each bit in the

LCDDATAx registers to the respective common and segment signals.

Any LCD pixel location not being used for display can be used as general purpose RAM.

27.10 LCD Frame Frequency

The rate at which the COM and SEG outputs change is called the LCD frame frequency.

TABLE 27-5: FRAME FREQUENCY

FORMULAS

Frame Frequency

(2)

= Multiplex

Static

1/2

1/3

1/4

Note 1:

2:

Clock source/(4 x (LCD Prescaler) x 32 x 1))

Clock source/(2 x (LCD Prescaler) x 32 x 2))

Clock source/(1 x (LCD Prescaler) x 32 x 3))

Clock source/(1 x (LCD Prescaler) x 32 x 4))

Clock source is F

OSC

/256, T1OSC or

LFINTOSC.

See Figure 27-2

.

TABLE 27-6:

LP<3:0>

4

5

6

2

3

7

APPROXIMATE FRAME

FREQUENCY (IN Hz) USING

F

OSC

@ 8 MHz, TIMER1 @

32.768 kHz OR LFINTOSC

Static 1/2 1/3 1/4

122

81

61

49

41

35

122

81

61

49

41

35

162

108

81

65

54

47

122

81

61

49

41

35

2010-2012 Microchip Technology Inc.

DS41414D-page 350

PIC16(L)F1946/47

TABLE 27-7:

LCD

Function

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

LCD SEGMENT MAPPING WORKSHEET

COM0

LCDDATA1, 6

LCDDATA1, 7

LCDDATA2, 0

LCDDATA2, 1

LCDDATA2, 2

LCDDATA2, 3

LCDDATA2, 4

LCDDATA2, 5

LCDDATA2, 6

LCDDATA2, 7

LCDDATA12, 0

LCDDATA12, 1

LCDDATA12, 2

LCDDATA12, 3

LCDDATA12, 4

LCDDATA12, 5

LCDDATAx

Address

LCDDATA0, 0

LCDDATA0, 1

LCDDATA0, 2

LCDDATA0, 3

LCDDATA0, 4

LCDDATA0, 5

LCDDATA0, 6

LCDDATA0, 7

LCDDATA1, 0

LCDDATA1, 1

LCDDATA1, 2

LCDDATA1, 3

LCDDATA1, 4

LCDDATA1, 5

LCDDATA12, 6

LCDDATA12, 7

LCDDATA13, 0

LCDDATA13, 1

LCDDATA13, 2

LCDDATA13, 3

LCDDATA13, 4

LCDDATA13, 5

LCDDATA13, 6

LCDDATA13, 7

LCDDATA14, 0

LCDDATA14, 1

LCDDATA14, 2

LCDDATA14, 3

LCDDATA14, 4

LCDDATA14, 5

LCD

Segment

COM1

LCD

Segment

LCDDATA4, 6

LCDDATA4, 7

LCDDATA5, 0

LCDDATA5, 1

LCDDATA5, 2

LCDDATA5, 3

LCDDATA5, 4

LCDDATA5, 5

LCDDATA5, 6

LCDDATA5, 7

LCDDATA15, 0

LCDDATA15, 1

LCDDATA15, 2

LCDDATA15, 3

LCDDATA15, 4

LCDDATA15, 5

LCDDATAx

Address

LCDDATA3, 0

LCDDATA3, 1

LCDDATA3, 2

LCDDATA3, 3

LCDDATA3, 4

LCDDATA3, 5

LCDDATA3, 6

LCDDATA3, 7

LCDDATA4, 0

LCDDATA4, 1

LCDDATA4, 2

LCDDATA4, 3

LCDDATA4, 4

LCDDATA4, 5

LCDDATA15, 6

LCDDATA15, 7

LCDDATA16, 0

LCDDATA16, 1

LCDDATA16, 2

LCDDATA16, 3

LCDDATA16, 4

LCDDATA16, 5

LCDDATA16, 6

LCDDATA16, 7

LCDDATA17, 0

LCDDATA17, 1

LCDDATA17, 2

LCDDATA17, 3

LCDDATA17, 4

LCDDATA17, 5

COM2

LCDDATA7, 6

LCDDATA7, 7

LCDDATA8, 0

LCDDATA8, 1

LCDDATA8, 2

LCDDATA8, 3

LCDDATA8, 4

LCDDATA8, 5

LCDDATA8, 6

LCDDATA8, 7

LCDDATA18, 0

LCDDATA18, 1

LCDDATA18, 2

LCDDATA18, 3

LCDDATA18, 4

LCDDATA18, 5

LCDDATAx

Address

LCDDATA6, 0

LCDDATA6, 1

LCDDATA6, 2

LCDDATA6, 3

LCDDATA6, 4

LCDDATA6, 5

LCDDATA6, 6

LCDDATA6, 7

LCDDATA7, 0

LCDDATA7, 1

LCDDATA7, 2

LCDDATA7, 3

LCDDATA7, 4

LCDDATA7, 5

LCDDATA18, 6

LCDDATA18, 7

LCDDATA19, 0

LCDDATA19, 1

LCDDATA19, 2

LCDDATA19, 3

LCDDATA19, 4

LCDDATA19, 5

LCDDATA19, 6

LCDDATA19, 7

LCDDATA20, 0

LCDDATA20, 1

LCDDATA20, 2

LCDDATA20, 3

LCDDATA20, 4

LCDDATA20, 5

LCD

Segment

COM3

LCDDATA10, 6

LCDDATA10, 7

LCDDATA11, 0

LCDDATA11, 1

LCDDATA11, 2

LCDDATA11, 3

LCDDATA11, 4

LCDDATA11, 5

LCDDATA11, 6

LCDDATA11, 7

LCDDATA21, 0

LCDDATA21, 1

LCDDATA21, 2

LCDDATA21, 3

LCDDATA21, 4

LCDDATA21, 5

LCDDATAx

Address

LCDDATA9, 0

LCDDATA9, 1

LCDDATA9, 2

LCDDATA9, 3

LCDDATA9, 4

LCDDATA9, 5

LCDDATA9, 6

LCDDATA9, 7

LCDDATA10, 0

LCDDATA10, 1

LCDDATA10, 2

LCDDATA10, 3

LCDDATA10, 4

LCDDATA10, 5

LCDDATA21, 6

LCDDATA21, 7

LCDDATA22, 0

LCDDATA22, 1

LCDDATA22, 2

LCDDATA22, 3

LCDDATA22, 4

LCDDATA22, 5

LCDDATA22, 6

LCDDATA22, 7

LCDDATA23, 0

LCDDATA23, 1

LCDDATA23, 2

LCDDATA23, 3

LCDDATA23, 4

LCDDATA23, 5

LCD

Segment

2010-2012 Microchip Technology Inc.

DS41414D-page 351

PIC16(L)F1946/47

27.11 LCD Waveform Generation

LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero.

The COM signal represents the time slice for each common, while the SEG contains the pixel data.

The pixel signal (COM-SEG) will have no DC component and it can take only one of the two RMS values. The higher RMS value will create a dark pixel and a lower RMS value will create a clear pixel.

As the number of commons increases, the delta between the two RMS values decreases. The delta represents the maximum contrast that the display can have.

FIGURE 27-8:

The LCDs can be driven by two types of waveform:

Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary. Thus, Type-A waveform maintains 0 V

DC over a single frame, whereas Type-B waveform takes two frames.

Note 1:

2:

If Sleep has to be executed with LCD

Sleep disabled (LCDCON<SLPEN> is

1

’), then care must be taken to execute

Sleep only when V

DC

on all the pixels is

0

’.

When the LCD clock source is F

OSC

/256, if Sleep is executed, irrespective of the

LCDCON<SLPEN> setting, the LCD immediately goes into Sleep. Thus, take care to see that V

DC

on all pixels is ‘

0

’ when Sleep is executed.

Figure 27-8

through

Figure 27-18

provide waveforms for static, half-multiplex, 1/3-multiplex and 1/4-multiplex drives for Type-A and Type-B waveforms.

TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE

COM0

COM0 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

1 Frame

V

1

V

0

V

1

V

0

V

1

V

0

V

1

V

0

-V

1

V

0

2010-2012 Microchip Technology Inc.

DS41414D-page 352

FIGURE 27-9:

COM1

COM0

PIC16(L)F1946/47

TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

COM0 pin

COM1 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

1 Frame

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

1 Segment Time

Note:

1 Frame = 2 single segment times.

2010-2012 Microchip Technology Inc.

DS41414D-page 353

PIC16(L)F1946/47

FIGURE 27-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

COM1

COM0 pin

COM0

COM1 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

Note:

1 Frame = 2 single segment times.

2 Frames

1 Segment Time

DS41414D-page 354

2010-2012 Microchip Technology Inc.

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

PIC16(L)F1946/47

FIGURE 27-11: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

COM1

COM0

COM0 pin

COM1 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

1 Frame

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

1 Segment Time

Note:

1 Frame = 2 single segment times.

2010-2012 Microchip Technology Inc.

DS41414D-page 355

PIC16(L)F1946/47

FIGURE 27-12: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

COM1

COM0

COM0 pin

COM1 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

Note:

1 Frame = 2 single segment times.

DS41414D-page 356

2 Frames

1 Segment Time

2010-2012 Microchip Technology Inc.

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

PIC16(L)F1946/47

FIGURE 27-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

COM2

COM1

COM0

COM0 pin

COM1 pin

COM2 pin

SEG0 and

SEG2 pins

SEG1 pin

COM0-SEG0 segment voltage

(inactive)

COM0-SEG1 segment voltage

(active)

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

2010-2012 Microchip Technology Inc.

DS41414D-page 357

PIC16(L)F1946/47

FIGURE 27-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

COM0 pin

COM2

COM1

COM0

COM1 pin

COM2 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(inactive)

COM0-SEG1 segment voltage

(active)

Note:

1 Frame = 2 single segment times.

2 Frames

1 Segment Time

2010-2012 Microchip Technology Inc.

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

-V

1

-V

2

DS41414D-page 358

PIC16(L)F1946/47

FIGURE 27-15: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

COM2

COM1

COM0

COM0 pin

COM1 pin

COM2 pin

SEG0 and

SEG2 pins

SEG1 pin

COM0-SEG0 segment voltage

(inactive)

COM0-SEG1 segment voltage

(active)

V

0

V

3

V

2

V

1

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

2010-2012 Microchip Technology Inc.

DS41414D-page 359

PIC16(L)F1946/47

FIGURE 27-16: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

COM2

COM1

COM0

COM0 pin

COM1 pin

COM2 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(inactive)

COM0-SEG1 segment voltage

(active)

Note:

1 Frame = 2 single segment times.

2 Frames

1 Segment Time

2010-2012 Microchip Technology Inc.

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

DS41414D-page 360

PIC16(L)F1946/47

FIGURE 27-17:

COM3

COM2

TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

COM0 pin

COM1

COM0

COM1 pin

COM2 pin

COM3 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

1 Frame

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

1 Segment Time

Note:

1 Frame = 2 single segment times.

2010-2012 Microchip Technology Inc.

DS41414D-page 361

PIC16(L)F1946/47

FIGURE 27-18:

COM3

COM2

TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

COM0 pin

COM1 pin

COM1

COM0

COM2 pin

COM3 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

2 Frames

1 Segment Time

Note:

1 Frame = 2 single segment times.

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

2010-2012 Microchip Technology Inc.

DS41414D-page 362

27.12 LCD Interrupts

The LCD module provides an interrupt in two cases. An interrupt when the LCD controller goes from active to inactive controller. An interrupt also provides unframe boundaries for Type B waveform. The LCD timing generation provides an interrupt that defines the LCD frame timing.

27.12.1

LCD INTERRUPT ON MODULE

SHUTDOWN

An LCD interrupt is generated when the module completes shutting down (LCDA goes from ‘

1

’ to ‘

0

’).

27.12.2

LCD FRAME INTERRUPTS

A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (T

FINT

), as

shown in Figure 27-19 . The LCD controller will begin to

access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (T

FWR

). New data must be written within T

FWR

, as this is when the LCD controller will begin to access the data for the next frame.

When the LCD driver is running with Type-B waveforms and the LMUX<1:0> bits are not equal to ‘

00

’ (static drive), there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. If the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a DC component would be introduced into the panel.

Therefore, when using Type-B waveforms, the user must synchronize the LCD pixel updates to occur within a subframe after the frame interrupt.

To correctly sequence writing while in Type-B, the interrupt will only occur on complete phase intervals. If the user attempts to write when the write is disabled, the WERR bit of the LCDCON register is set and the write does not occur.

Note:

The LCD frame interrupt is not generated when the Type-A waveform is selected and when the Type-B with no multiplex

(static) is selected.

PIC16(L)F1946/47

2010-2012 Microchip Technology Inc.

DS41414D-page 363

PIC16(L)F1946/47

FIGURE 27-19:

COM0

COM1

COM2

COM3

WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE

(EXAMPLE – TYPE-B, NON-STATIC)

LCD

Interrupt

Occurs

Controller Accesses

Next Frame Data

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

2 Frames

T

FWR

T

FINT

Frame

Boundary

Frame

Boundary

T

FWR

= T

FRAME

/2*(LMUX<1:0> + 1) + T

CY

/2

T

FINT

= (T

FWR

/2 – (2 T

CY

+ 40 ns))

 minimum = 1.5(T

FRAME

/4) – (2 T

CY

+ 40 ns)

(T

FWR

/2 – (1 T

CY

+ 40 ns))

 maximum = 1.5(T

FRAME

/4) – (1 T

CY

+ 40 ns)

Frame

Boundary

DS41414D-page 364

2010-2012 Microchip Technology Inc.

27.13 Operation During Sleep

The LCD module can operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep.

If a

SLEEP

instruction is executed and SLPEN =

1

, the

LCD module will cease all functions and go into a very low-current Consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines.

Figure 27-20 shows this operation.

The LCD module can be configured to operate during

Sleep. The selection is controlled by bit SLPEN of the

LCDCON register. Clearing SLPEN and correctly configuring the LCD module clock will allow the LCD module to operate during Sleep. Setting SLPEN and correctly executing the LCD module shutdown will disable the LCD module during Sleep and save power.

If a

SLEEP

instruction is executed and SLPEN =

1

, the

LCD module will immediately cease all functions, drive the outputs to Vss and go into a very low-current mode.

The

SLEEP

instruction should only be executed after the LCD module has been disabled and the current cycle completed, thus ensuring that there are no DC voltages on the glass. To disable the LCD module, clear the LCDEN bit. The LCD module will complete the disabling process after the current frame, clear the

LCDA bit and optionally cause an interrupt.

The steps required to properly enter Sleep with the

LCD disabled are:

• Clear LCDEN

• Wait for LCDA =

0

either by polling or by interrupt

• Execute

SLEEP

If SLPEN =

0

and

SLEEP

is executed while the LCD module clock source is F

OSC

/4, then the LCD module will halt with the pin driving the last LCD voltage pattern. Prolonged exposure to a fixed LCD voltage pattern will cause damage to the LCD glass. To prevent

LCD glass damage, either perform the proper LCD module shutdown prior to Sleep, or change the LCD module clock to allow the LCD module to continue operation during Sleep.

If a

SLEEP

instruction is executed and SLPEN =

0

and the LCD module clock is either T1OSC or LFINTOSC, the module will continue to display the current contents of the LCDDATA registers. While in Sleep, the LCD data cannot be changed. If the LCDIE bit is set, the device will wake from Sleep on the next LCD frame boundary. The LCD module current consumption will not decrease in this mode; however, the overall device power consumption will be lower due to the shutdown of the CPU and other peripherals.

PI