3 STM32L0 ULP peripherals
STM32L0 ULP Peripherals
OBJECTIVES
• Introduce STM32L0 Ultra-Low-Power peripherals
• Highlight key features and discuss possible applications
• With focus on energy consumption optimizing enhancements
• Test some of the peripherals in operation (exercises)
After this presentation you will understand
the benefits of Ultra-Low-Power peripherals
included in STM32L0.
2
Flash I/F
ULP Peripherals Overview
CORTEXTM-M0+
M0+
CPU
32 MHz
With MPU
37/51 I/Os
NVIC
SysTick
ARM ® Lite Hi-Speed Bus
Matrix / Arbiter (max 32MHz)
SW Debug
64KB
Flash Memory
Power Supply
Reg 1.8V/1.5V/1.2V
POR/PDR/BOR/PVD
2KB
Data EEPROM
Int. RC 16 MHz
8KB SRAM
20B
Backup Reg.
TSC
RNG
RCC
DMA
7 Channels
Xtal 1-24MHz
Int. RC 37 kHz
Xtal 32,768 kHz
Int. RC 65K..4.2MHz
PLL
RTC / WUT
AES Tiny
4 x 16-bit Timer
EXTI
2 x Watchdog
2 x SPI
2 x COMP
(ind. & window)
1x LPTIM
Glass LCD Control.
(up to 8x24)
USB 2.0 FS
1 x 12-bit DAC
2 x USART
1 x 12-bit ADC
19 channels / 1Msps
1 x LPUART
Temp Sensor
2 x I2C
3
Digital peripherals
Real-Time Clock (RTC)
Block Diagram (RTC)
RTC_TAMP1
Backup Registers and
RTC Tamper
Control registers
RTC_TAMP2
Tamper Event
TimeStamp Event
TimeStamp Registers
RTC_TS
Alarm B
RTC_REFIN
Alarm B Event
=
RTCSEL [1:0]
Alarm A
HSE / 32
hh:mm:ss:ssr
dd/mm/year
Smooth
Calibration
LSE
LSI
hh:mm:ss:ssr
dd/mm/year
RTCCLK
Calendar
Alarm A Event
=
Calendar
ssr
(binary format)
Synchronous
15-bit Prescaler
PREDIV_A [6:0]
PREDIV_S [14:0]
ck_spre
Day/date/month/year
OSEL
HH:mm:ss
(12/24 format)
1 Hz
RTC_CALIB
512 Hz
Output
Control
Asynchronous
7-bit Prescaler
Wake-Up
COSEL
RTC_OUT
Prescaler
/2, /4, /8, /16
Wake-Up Event
16-bit autoreload
Timer
5
RTC Calendar
• The initialization or the reading of the calendar value is done
through 3 shadow registers, SSR, TR and DR. The RTC TR and
DR registers are in BCD format.
• SSR register represents the RTC Sub seconds register
Calendar
12h/24h
Actual
registers
Shadow
registers
Time
Date
Day : Month : Date : Year
DR
hh
: mm : ss
TR
: ssr
SSR
6
Wake-Up Timer (WUT)
7
RTCCLK (LSE, 32.768 kHz)
Asynchronous
7-bit Prescaler
To Calendar
Synchronous
15-bit Prescaler
VALUE <0x00, 0x7F>
VALUE <0x0000, 0x7FFF>
DEFAULT = 0x7F
DEFAULT = 0xFF
ck_spre
2
3
VALUE <0x(1)0000, 0x(1)FFFF>
Wake-Up
WakeUpCLK
Prescaler
/2, /4, /8, /16
Wake-Up Event
16-bit autoreload
Timer
1
WakeUpCLK
MIN_TIME
MAX_TIME
Resolution
RTCCLK /2
121 µs
4s
61 µs resolution
RTCCLK /16
976 µs
32 s
488 µs resolution
1s
18.2 h
1s resolution
18.2 s
36.4 h
1s resolution
1
2
ck_spre = 1Hz
3
BACKUP domain
RCC CSR
LSE (32 kHz)
IWDG
LSI (37 kHz)
Wakeup Logic
8
Wakeup Pin 1 /
Tamper 2
RTC + 20 Bytes Data
Reference clock
input
RTC output / Wakeup
Pin 2 / Tamper 1 /
Timestamp
RTC pins alternate functions
Tamper detection (resets all RTC user backup registers)
Time Stamp detection: the calendar is saved in the time-stamp registers
Configurable level: low/high, interrupt request generation
Wake-Up:
Reference clock input: 50 / 60Hz precise signal resynchronization
Alarm Ouput: Alarm A, Alarm B and RTC Wakeup event signals
Clock calibration Output: 1 Hz / 512 Hz when using 32.768 kHz crystal
Smooth Digital Calibration
• Consists in masking/adding N (configurable) 32kHz
clock pulses, fairly well distributed in a configurable
window.
• A 1Hz output is provided to measure the quartz
frequency and the calibration result.
• Calibration value can be changed on the fly.
Calibration window
Accuracy
Total range
8s
±1.91 ppm
[0 ±480ppm]
16s
±0.95 ppm
[0 ±480ppm]
32s
±0.48 ppm
[0 ±480ppm]
9
RTC registers write protection
• By default and after reset, the RTC registers are write protected to
avoid possible parasitic write accesses.
• DBP bit must be set in PWR_CR to enable RTC write access
• A Key must be written in RTC_WPR register.
• To unlock write protection on all RTC registers
• 1. Write ‘0xCA’ into the RTC_WPR register
• 2. Write ‘0x53’ into the RTC_WPR register
* Except for the clear of Alarm and Wakeup timer interrupt flags
Writing a wrong key reactivates the write protection.
10
10
Tamper detection
• 2 tamper pins and events
RTC_TAMPx
Tamper
switch
STM32
Capacitor is optional (filtering can be
done by software)
Biasing is done using the I/O’s Pullup resistor
• Configurable active level for each event
• Configurable use of I/Os pull-up resistors
• Configurable pre-charging pulse to support different
capacitance values
• 1, 2, 4 or 8 cycles
• Configurable filter:
• Sampling rate
(128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz, 1Hz)
• Number of consecutive identical events before
issuing an interrupt to wake-up the MCU
(1, 2, 4, 8)
• Reset of backup registers when tamper event detected
• Tamper event can generate a timestamp event
11
12
Digital peripherals
LPTIM
Low-Power Timer Block diagram
APB bus
Registers
1
Up/Down
2
3
Encoder
1
2
3
Glitch
Filter
Input 2
Glitch
Filter
Input 1
up to 8 ext
trigger
Glitch
Filter
s/w
trigger
16-bit ARR
MUX trigger
+ 16-bit Counter
APB clock
LSE
LSI
HSI16
3-bit Prescaler
CLKMUX
16-bit Compare
Output
13
LPTIM Glitch Filters
Glitch
Filter
2 consecutive
samples
2 consecutive
samples
2 consecutive
samples
CLK
INPUT
Filtered
OUTPUT
Filtered glitches
2, 4 or 8 consecutive samples configuration
14
LPTIM as Waveform Generator
• 3 configurable waveforms
• PWM waveform
• One Pulse waveform
• Set Once waveform
LPTIMx_ARR
LPTIMx_CMP
LPTIMx_CNT
PWM
One Pulse
Set Once
POL = 0
15
LPTIM as Encoder Interface
1
• Encoder mode
• Same operation as Encoder mode on General Purpose Timers
• Only available when LPTIM runs in Continuous mode
CLK
INPUT1
INPUT2
COUNTER
2
3
16
LPTIM as External Pulse Counter
Sampling
1
2
3
Glitch
Filter
Input 1
16-bit ARR
APB clock
LSE
LSI
HSI16
+ 16-bit Counter
3-bit Prescaler
CLKMUX
Output
must be ‘000’
16-bit Compare
Fully asynchronous operation
1
2
Glitch
Filter
Input 1
16-bit ARR
APB clock
LSE
LSI
HSI16
+ 16-bit Counter
3-bit Prescaler
CLKMUX
16-bit Compare
Output
17
18
Digital peripherals
USART
USART – Block Diagram
Transmit Data
Register
Tx
Transmit.
Receiver
Rx
IrDA SIR
Encoder /
Decoder
Receive Data
Register
Receive
Control
DMA
Control
Transmit
Control
Interrupt
Control /
Status
DMA Requests
IRQ Requests
Wakeup
from STOP
nRTS
/DE
Node
Address
HW Flow
Control
nCTS
Wakeup
Unit
Baud
Rate
Generator
Clocks
SCLK Control
SCLK
USART peripheral
PCLK
SYSCLK
HSI
LSE
19
USART Features List
Frame
•
•
•
•
7, 8, 9 DATA bits
0.5, 1, 1.5, 2 STOP bits
Even, odd, none PARITY
Oversampling /8 and /16 (default)
Modes
• Asynchronous
LIN
SmartCard (T=0, T=1)
IrDA
Basic MODBUS
Multiprocessor communication
Half duplex
• Synchronous (CLK line)
Other
•
•
•
•
•
•
DMA support
HW flow control (RTS, CTS lines)
Auto baudrate detection
Programmable data order (MSB/LSB)
Swappable Tx/RX pins
Wakeup from STOP (!!! no data loss !!!)
4Mbps
NO data loss
on wakeup
20
Wakeup from STOP (USART)
Typical Wakeup from STOP flowchart:
Select the USART clock source
HSI
LSE
Set the UESM bit
There is a deviation add-on, due
to wakeup time:
tWUSTOP
DWU =
(10 + M )⋅ Tbit
M is 0 for 8 bit, 1 for 9 bit frame
Select the Wakeup event
RXNE
Start bit
Address
Match
tWUSTOP is the time for wakeup
from STOP mode (typ. 4.2 usec)
The first byte is received correctly
Go to STOP mode
After wakeup, the WUF bit is set
if this timing is included in the
allowed overall deviation
21
USART – Automatic Baudrate Detection
2 patterns for auto-baudrate detection:
T measured
T measured
The auto-baudrate completed
Baud rate register updated
Conditions:
ABRF flag set
Detection range: bit time from 16 to 65535 USART clock periods.
BRR must be a value different from 0.
Only oversampling by 16 allowed
22
USART – Synchronous Mode
USART supports Full duplex synchronous communication mode
Another SPI like interface
Full-duplex, three-wire synchronous transfer
USART Master mode only
Synchronous clock generated on (SCLK)
Programmable clock polarity (CPOL) and phase (CPHA)
Programmable Last Bit Clock Pulse generation (LBCL)
Slave
Master
SCK
SCLK
MISO
RX
SPI
USART
MOSI
TX
Full Duplex
NSS
23
USART – Single Wire Half Duplex mode
USART supports Half duplex synchronous communication mode
Only TX pin is used (RX is no longer used)
Used to follow a single wire Half duplex protocol.
USART1
TX
R = 10 KΩ
VDD
Half Duplex
USART2
TX
24
USART – Smart Card Mode
USART supports Smart Card Emulation ISO 7816-3
Half-Duplex, Clock Output (SCLK)
9Bits data, 1.5 Stop Bits in transmit and receive.
T = 0, T = 1 support
Programmable Clock Prescaler to guarantee a wide range clock input
ISO 7816-2 Electrical contact layout
USART
TX
SCLK
C1
C5
C2
C6
C3
C7
C4
C8
25
USART – IrDA SIR Encoder Decoder
USART supports the IrDA SIR Specification
• Half-duplex, NRZ modulation,
• Max bit rate 115200 bps
• The pulse width is 3/16 bit duration in normal mode
• Low power mode: 1.42MHz <PSC < 2.12MHz
USART
IrDA
SIR
Encoder
TX
USART
SIR
Decoder
RX
IrDA
transceiver
26
USART – RS485, RS422 Transceiver Control
TX signal
DEAT
DE signal
DEDT
time
time
TX
USART
DE
RX
+
RS485
transceiver
-
The times are expressed in oversampling time units (1/8 or 1/16 of bit time)
The polarity can be selected by DEP bit
DE pin shared with RTS pin
27
28
Digital peripherals
Low-Power UART (LPUART)
LPUART
• LPUART includes all necessary hardware support to make
asynchronous serial communications possible with minimum power
consumption
• With just the LSE 32.768 kHz it is possible to run at up to 9600 baud
•
For this purpose, the baudrate generation has been changed
comparing to the USART peripheral
SYSCLK
HSI16
to LPUART
LSE
APB (PCLK)
• Can be kept enabled and clocked even during STOP mode
29
LPUART baudrate generation
Tx/Rx Baud =
256 × fCK
LPUARTDIV
Where:
Tx/Rx_baud... desired baudrate
fck... LPUART clock source frequency
LPUARTDIV... coded on the the BRR register
(LPUARTx_BRR value can’t be lower than 0x300)
Desired Baud rate
Actual Baud rate
LPUARTx_BRR
% Error
2400 Bps
2400.17 Bps
0xDA7
0.007
9600 Bps
9608.94 Bps
0x369
0.093
Assuming LSE (32.768 kHz) used as clock source
30
USART/LPUART feature list
Features
USART1/2
LPUART1
Programmable data word length (7,8 or 9 bits)
•
•
Configurable stop bits (1 or 2)
•
•
Hardware Flow Control (Modem, RS-485 transceiver)
•
•
Continuous communication using DMA
•
•
Multi-processor communication
•
•
Single wire half duplex mode
•
•
Dual clock domain and Wake-Up from STOP mode
•
•
Swappable Rx/Tx pin configuration
•
•
Synchronous mode
•
Smartcard mode
•
IrDA
•
LIN
•
Receiver timeout
•
Modbus Communication
•
Autobaudrate detection
•
31
32
Digital peripherals
2
IC
I2C Block Diagram
PCLK
HSI16
SYSCLK
SYSCFG_CFGR1 /
I2C_PBx_FM+
Data control
I2C_CLK
WUPEN
SMBus PEC
gen./check
RCC_CFGR_I2CxSEL
Wake-Up on
address match
Clock control
MASTER clk
control
Digital
Noise
Filter
Analog
Noise
Filter
Digital
Noise
Filter
Analog
Noise
Filter
GPIO
logic
SDA
GPIO
logic
SCL
SLAVE clk.
stretching
SMBus
Timeout chck
SMBus Alert ctrl.
& status
PCLK
Registers
APB bus
SYSCFG_CFGR1 /
I2C_PBx_FM+
SMBA
33
Wakeup from STOP on address match
•
•
When I2C_CLK clock is HSI, the I2C is able to wakeup MCU from
STOP when it receives its slave address. All addressing mode are
supported:
•
During STOP mode and no address reception: HSI is switched off
•
On START detection, I2C enables HSI, used for address reception
Wakeup from STOP is enabled by setting WUPEN in I2C1_CR1
•
The HSI oscillator must be selected as the clock source for I2CCLK in
order to allow wakeup from STOP.
•
Clock stretching must be enabled to ensure proper operation
(NOSTRETCH=0)
2 configurable addresses
34
Easy Master mode management
• For payload <= 255 bytes : only 1 write action needed !! (apart data rd/wr)
I2Cx_CR2 is written with : START enable (START=1)
Slave address configuration (SADD)
Transfer direction (RD_WRN)
Number of bytes to be transferred (NBYTES = N)
Autoend enable (AUTOEND=1) => peripheral will
generate STOP automatically after N bytes are sent
AUTOEND
0 : Software end mode
End of transfer SW control after NBYTES data transfer :
• TC flag is set. Interrupt if TCIE=1.
• TC is cleared when START or STOP is set by SW
If START=1 : RESTART condition is sent
1 : Automatic end mode
STOP condition sent after NBYTES data transfer
• Data transfer managed by Interrupts (TXIS / RXNE) or DMA
35
36
Analog peripherals
Power Supply Supervisors
Power Supply monitoring
/ Reset circuitry
VDD / VDDA
37
2.0V
(PVD)
100mV hysteresis
1.9V
(1.9V min)
(BOR)
1.8V
1.8V (min)
100mV hysteresis
1.7V
PDR / POR
1.5V
(1.5V)
Reset Temporization (tRSTTEMPO)
PVD output
BOR reset
(NRST)
PVD enabled
by Software
Option Bytes
Reload
BOR/PDR reset
(NRST)
POR/PDR
(NRST)
PVD interrupt
(if enabled)
38
Analog peripherals
COMPx
COMPx Block diagram
COMP1 window
mode selection
PA1
+
COMP1 polarity
selection
COMP1
-
PA0
PA4 (DAC)
PA5
VREFINT
TIM2_ETR
TIM2_CH4
TIM21_ETR
TIM21_CH2
TIM22_ETR
TIM22_CH1
LPTIM_ETR
LPTIM_CH2
COMP2 non-inverting
input selection
PA3
PB4
PB5
PB6
PB7
COMP1 inverting
input selection
+
COMP2
PA2
PA4 (DAC)
PA5
PB3
VREFINT
¾ VREFINT
½ VREFINT
¼ VREFINT
WAKEUP
EXTI_LINE_21
GPIOx
COMP1_VALUE
COMP2 polarity
selection
WAKEUP
EXTI_LINE_22
GPIOx
COMP2_VALUE
TIM2_ETR
TIM2_CH4
TIM21_ETR
TIM21_CH2
TIM22_ETR
TIM22_CH1
LPTIM_ETR
LPTIM_CH2
COMP2 inverting
input selection
39
COMP features
• Parameters at a glance
• Full voltage range 2V < Vdda < 3.6V
• Propagation time vs consumption (typ. 2.7 < Vdd < 3.6V, for 200 mV step with 100
mV overdrive)
• High speed mode:
• Low power mode:
120ns / 100µA
1µs / 3µA
• Input offset: +/-5mV typ, +/- 20mV max
• Programmable hysteresis: 0, 8, 15, 31 mV
• Fully asynchronous operation
• Comparators are still operational even in STOP mode
• No clock related propagation delay (analog peripheral)
• Functional safety (Class B)
• The comparator configuration can be locked with a write-once bit
40
41
Analog peripherals
ADC
ADC Block Diagram
1.8V ~ 3.6V
42
Vref+
VDDA
VSSA
AUTOFF
ADC_IN0
ADEN/ADDIS
GPIO
Ports
Bias & Ref
VIN
Sampling
time control
S&H
Temp Sensor
CONVERTED DATA
Oversampler
SAR ADC
16-bit DATA
VREFINT
VLCD
Analog Watchdog
Start
Higher Threshold
Input Sel. &
Scan Control
Lower Threshold
AUTDLY
ADSTP
Start & Stop
Control
s/w trigger
h/w trigger
ADRDY
ADSTART
EOSEQ EOC
OVR
AWD
Flags
EXTRIG bit
TRG0
TRG1
EOSMP
ADDRESS/DATA BUS
ADC_IN15
ANALOG MUX
.
.
.
.
.
.
.
.
.
1
2
ADRDYIE
3
EOSMPIE EOSEQIE EOCIE OVRIE AWDIE
Interrupt
enable bits
TRG2
…
Trigger enable and
edge selection
TRG7
DMA
request
EXTSEL[2:0] bits
Interrupt
request
Clock sources (ADC)
• The ADC has a dual clock-domain architecture:
• Dedicated 16MHz clock
• PCLK clock divided by 2 or divided by 4, in case of /1 the duty cycle must be 50%
ADC PERIPHERAL
PCLK
ADC Prescalers:
/1 or /2 or /4
Digital Interface
Analog Interface
16MHz
16MHz internal
oscillator
max
/1, /2, /4 .. /256
Guaranteed maximum speed whatever the MCU operating frequency.
Capability to use the low-power auto-off mode.
(automatic ON/OFF switch of 16 MHz internal oscillator)
43
Total Conversion Time
• Total conversion Time = TSampling + TConversion
Resolution
TConversion
TSampling
Total conversion time
tADC at fADC =
16MHz
12 bit
12.5 Cycles
1.5 Cycles
14 Cycles
875ns
10 bit
11.5 Cycles
1.5 Cycles
13 Cycles
813ns
8 bit
9.5 Cycles
1.5 Cycles
11 Cycles
688ns
6 bit
7.5 Cycles
1.5 Cycles
9 Cycles
562ns
Lower resolution allows faster conversion times for applications where high
data precision is not required.
44
Auto delayed conversion
• Auto Delay Mode
• When AUTDLY = 1, a new conversion can start only if the previous
data has been treated, once the ADC_DR register has been read or
if the EOC bit has been cleared.
HW/SW Trigger
ADC State
1
Delay
2
Delay
3
Delay
EOC Flag
i
Channel conversion #i
Note : A trigger event (for the same group of conversions) occurring during this delay is ignored.
This is a way to automatically adapt the speed of the ADC to the
speed of the system that reads the data.
Auto-delayed mode avoids any possible overrun issue
45
Auto-OFF mode (Power Saving)
46
• ADC power-on and power-off can be managed by hardware and turn
OFF the 16 MHz internal oscillator in order to save power. The ADC
can be powered down:
• During the ADC is waiting for a trigger event (AUTOFF= 1)
The ADC is powered
up at the next trigger event.
• During the delay and waiting for a trigger event (AUTDLY= 1 and AUTOFF= 1)
The ADC is powered up again at the end of the delay and at the next trigger event.
HW/SW Trigger
AUTOFF =1
AUTDLY =1
1
OFF
AUTOFF =1
AUTDLY =0
AUTOFF =0
AUTDLY =0
OFF
ON
1
AUTOFF =0
AUTDLY =1
2
Delay
Delay
OFF
ON
2
1
Delay
OFF
ON
1
Delay
ON
ON
1
ON
OFF
1 2
1
ON
ADC Waiting for Trigger
OFF
Delay
1 2
OFF
Delay
Startup Time
i
Channel conversion #i
OFF
Oversampling
• Principle
• The ADC hardware can do averaging according to the formula:
1
• M and N are programmable
• N – 2 to 256
• M – division is made by logical shift up to 8 bits (division by 256)
• Benefits
• Data rate reduction
• SNR improvement
• Basic filtering
47
STM32L0 implementation
48
• ADC does oversampling and averaging by HW
• N is setup by OVFS[2:0], 2x to 256x
• M by OVSS[3:0], 0 to 8 bit
19
Raw 20-bit
accumulator
0
0xDEDA1
Programmable
shift
Up to 8 bits
15
16-bit result, the
MSB is truncated
0
0xDEDA
Shift by 4 bits in this example
• EOC = 1 when new averaged value is ready
• ADC can be put to AUTOFF mode between conversions
49
Analog peripherals
Glass LCD Controller (LCD)
LCD Controller Block diagram
50
Frequency generator
LCDCLK
16-bit prescaler
COM0
Registers
Clock MUX
COM3
Interrupt
ck_div
LCD RAM
(32x16 bits)
8-to-1 MUX
ADDRESS/DATA BUS
Divide by 16 to 31
SEG
Driver
COM
Driver
SEG0
Analog
switch
array
SEG27
SEG COM
MUX
Registers
Voltage
Generator
VSS
1/3 – 1/4 VLCD
SEG28/COM4
SEG29/COM5
SEG30/COM6
2/3 – 3/4 VLCD
Pulse
Generator
1/2 VLCD
Contrast
Controller
Analog STEP-UP converter
VLCD
SEG31/COM7
Frequency generator
51
• The LCD Controller (LCDCLK) uses the same
clock as RTCCLK. It can be: LSE, LSI,
HSE_DIV divided by 1, 2, 4 or 8.
• The LCDCLK input clock must be in the range
of 32 kHz to 1MHz.
LSE/LSI/
HSE_Div1/2/4/8
16-bits Prescaler
LCDCLK
• The LCDCLK divided by 2PS[3:0] : ck_ps PCLK1
• The ck_ps to be also divided by 16 to 31 to
adjust the resolution rate: ck_div
fck_div = f LCD =
f LCDCLK
2PS (16+ DIV)
LCD_FCR
PS[3:0]
LCDCLK / 32768
Clock MUX
ck_ps
DIV[3:0]
Divide by 16 to 31
ck_div
• The frame frequency is obtained from the LCD
frequency by dividing it by the number of active
common terminals
f Frame = f LCD * duty
The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz
Memory/Segment mapping
X
Digit 16 Segment
31
……
3
2
A
F
J
G
E
Example of Writing the
character “A” on the
B Liquid crystal display
first digit
COM1
K
L
M
N
COM2
C
COM3
DP
D
.
.
.
COM0 COM1 COM2 COM3
SEG0
X
F
E
D
SEG1
I
J
K
N
SEG2
A
B
C
DP
SEG3
H
G
L
M
0x
4
0
COM0
I
H
1
52
D
7
0
COM7
LCD RAM
Common/Segment driver(1/2)
• Every common signal has identical waveforms but different phases
• The common has the maximum amplitude VLCD or VSS only in the
corresponding phase of a frame cycle.
• During the other phases, the signal amplitude is 1/4 VLCD or 3/4 VLCD in
case of 1/4 bias or 1/3 VLCD or 2/3 VLCD in case of 1/3 Bias and 1/2 VLCD
in case of 1/2 Bias.
• The first frame generated is the odd one followed by an even one
• Five Duty ratios can be selected: Static Duty, 1/2 Duty, 1/3 Duty, 1/4 Duty or
1/8 Duty
• Three modes can be selected: 1/2 Bias, 1/3 Bias or ¼ Bias
53
Common/Segment driver(2/2)
Odd Frame
To activate segments[n] connected to COM0,
SEGn needs to be inactive (VSS) during phase 0
of an odd frame and active (VLCD) during phase
0 of an even frame when COM0 is active
To deactivate segments[n+44] connected to
COM1, SEGn needs to be active during the
phase 1 of an odd frame and inactive during the
phase 1 of an even frame when COM1 is active
COM0
COM1
COM2
Common signals are phase inverted in order
to reduce EMI
COM3
A segment is active if the corresponding
segment line gets a maximum voltage opposite
to the common
Even Frame
VLCD
SEGn
The segment terminals are multiplexed and
each of them controls four segments
54
2/3 VLCD
1/3 VLCD
VSS
VLCD
2/3 VLCD
1/3 VLCD
VSS
VLCD
2/3 VLCD
1/3 VLCD
VSS
VLCD
2/3 VLCD
1/3 VLCD
VSS
VLCD
2/3 VLCD
1/3 VLCD
VSS
Pixels[n]
Pixels[n+44] Pixels[n+88] Pixels[n+132]Pixels[n]
RAM refresh
LCD RAM
Pixels[n+44]Pixels[n+88] Pixels[n+132]
RAM refresh
LCD RAM
Double Buffer Memory: LCD RAM AREA ALWAYS ACCESSIBLE
LCD Contrast Control
The contrast can be adjusted using two different methods:
Method 1 (external VLCD voltage)
Contrast can be controlled by programming a dead time (up to 8 phase periods)
between each couple of frames where the COM and SEG value is tied to Vss in
the same time.
Even Frame
Odd Frame
COM0
VLCD
2/3 VLCD
1/3 VLCD
VSS
phase0 phase1 phase2 phase3
3 phase dead time
phase0 phase1 phase2 phase3
Method 2 (internal STEP-UP converted used)
The software can adjust VLCD between 2.6 V to 3.3 V in 8 steps
55
LCD Signals Generation
The LCD voltage levels can be generated :
Internally using an internal step-up converter or externally using VLCD voltage
An internal resistor divider network generates all VLCD intermediate voltages
External capacitor can be used to stabilize intermediate VLCD voltage
Signal shape and thus VRMS are improved without the use of High Drive (suitable
especially for large displays with higher segment capacity)
The RL and RH resistive
networks are used to
increase the current during
transitions and to reduce
consumption in static state.
The nodes provide several
intermediate voltage:
• One (Bias ½),
• two (Bias 1/3)
• three (Bias ¼)
remains active in STOP modes
not active in STANDBY mode
56
Thank you
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