CD00217825
SCLT3-8BT8
Protected digital input termination with serialized state transfer
Datasheet - production data
• Power supply and input protection, RI = 2.2 kW:
– IEC 61000-4-4 transient burst: ±4 kV
minimum
– IEC 61000-4-5 voltage surge: ±1 kV
minimum
– IEC 61000-4-2 ESD: ±8 kV in contact:
± 15 kV in air minimum
• Wide range power supply voltage VC:
– +9 V to +35 V with 10 mA output current
– Protected against -30 V reverse polarity
HTSSOP-38 package
Applications
• Digital inputs for programmable logic controller
and decentralized I/O modules
• Digital input with serialized state transfer
Features
• 8-input circuit in common ground low side
topology
• Wide range input DC voltage VI: -30 V to 35 V
– On state threshold: < 11 V with RI = 2.2 kW
– Off state threshold: IIN > 1.5 mA or VI > 5 V
– Protected against -30 V reverse polarity
• 2.35 mA active current limiter with 10%
tolerance
– Drastic dissipation reduction:
78 mW max. per input
• Input digital filter with adjustable delay:
20 µs to 3 ms
• Energy-less LED visual status driver
• Input logic state transfer through a 2 MHz SPI
– Programmable 8 / 16-bit register length
– Multi SCLT connection in daisy chain
– Chip temperature OTA and under voltage
UVA alarms
– Multi parity bits and power loss detection
with stop bits
– Drastic reduction of isolated coupler count
and I/O of the field bus ASIC
November 2015
This is information on a product in full production.
• Enabling digital inputs to meet type 1 and 3
characteristics of IEC 61131-2
• EN60947-5-2 2-wire proximity sensor
compatibility
Description
The SCLT3-8BT8 provides an 8-line protected
digital input termination with serialized state
transfer. This device enhances the I/O module
density by cutting the dissipation (78 mW per
input) and reducing the count of opto-transistors.
An adjustable digital filter and an LED driver are
embedded in each type 3 input section. Its 2 MHz
SPI peripheral output serializes the input state
transfer to the I/O module controller.
TM Transil is a trademark of STMicroelectronics
Doc ID15191 Rev 6
1/31
www.st.com
Contents
SCLT3-8BT8
Contents
1
Circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Input power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Visual input LED driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
The input digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Operation of the SCLT with the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
SPI bus signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
2.7
3
I/O pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5.1
Chip select /CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.2
Serial clock SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.3
Serial data input MOSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.4
Serial data output MISO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.5
SPI shift register operation selector SPM . . . . . . . . . . . . . . . . . . . . . . . 11
SPI data transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.6.1
SPI data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6.2
SPI data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6.3
SPI transfer speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Control bit signals of the SPI transferred data frame . . . . . . . . . . . . . . . . 13
2.7.1
Power bus voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7.2
Over temperature alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7.3
Parity checksum bits calculation and transfer . . . . . . . . . . . . . . . . . . . . 14
2.7.4
SPI hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7.5
Loss of VCC power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1
SCLT serial link configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.1
3.2
High speed operation with magnetic isolators . . . . . . . . . . . . . . . . . . . . . 24
3.3
Reverse polarity robustness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4
Surge voltage immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5
Fast transient burst immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1
2/31
Interfacing SPI section to I/O controller through opto-transistors . . . . . 24
Considerations on the power section . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID15191 Rev 6
SCLT3-8BT8
Contents
3.5.2
Considerations on the logic section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.6
Under voltage alarm setting for IEC and device-net applications . . . . . . . 26
3.7
Input operation for the device-net applications . . . . . . . . . . . . . . . . . . . . . 27
3.8
Dissipation calculation in the SCLT3-8 circuit . . . . . . . . . . . . . . . . . . . . . 27
4
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Circuit block diagram
1
SCLT3-8BT8
Circuit block diagram
Figure 1. Circuit block diagram
VDD
Protected input
LD1
VIN < V R
16 µs / 3 ms digital filters
4/31
COMS
MOSI
SHIFT
MOSI
8 / 64
Clock divider
Transfer
logic
8 lines
7 lines
/CS
SHIFT
4 lines
Current
reference
Oscillator
VDD
WRITE
SCK
DVR
OSC
/MISO
CAPTURE
Parity
bits gen.
I = 2 to 8
8 lines
Over temperature
alarm
Doc ID15191 Rev 6
Control state register
REF
Protected input
COMP
LDI
8 lines
Data state register
VR
INI
VDD
MISO
Input state register
IN1
SPM
16-bit
VC
Power
reset
Power
supply
VDD
Under voltage
alarm
VCS
SCLT3-8BT8
1.1
Circuit block diagram
I/O pin descriptions
Table 1. I/O pin descriptions
Name
Type
Description
Pin #
8 to 11, 13 to
16
INI
Power input
Logic input with a current regulation behavior, I = 1 to 8
LDI
Power output
LED output driver with a current regulation behavior,
I = 1 to 8
VC
Power input
24 V sensor power supply
5
VCS
Signal input
24 V sensor power supply sensing input
6
Ground
Power ground of power sensor supply
COMP
VDD
20 to 27
4, 7, 12, 17
Power output 5 V logic power supply
38
Ground
Signal ground of logic / output section
30
REF
Signal input
Input current limiter reference setting
29
DVR
Logic input
Divider ratio selector of the digital input filters (8 or 64 steps)
1
OSC
Signal input
Delay setting of the digital input filters
2
SPM
Signal input
SPI shift register length selector (8 or 16 bits)
3
/CS
Logic input
SPI chip Select signal
35
SCK
Logic input
SPI serial clock signal
34
MOSI
Logic output
SPI serial data input signal
33
/MISO
Logic output
Inverting SPI serial data output signal
32
MISO
Logic input
SPI serial data input signal
31
SUB
Substrate
Exposed pad: connected to die substrate, to connect to
COMPP
COMS
NC
Not connected (or to be connected to COMP)
Doc ID15191 Rev 6
Exposed
pad
18, 19, 28,
36, 37
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Circuit block diagram
SCLT3-8BT8
Figure 2. Pinout description of the HTSSOP-38 version (top view)
1
2
3
DVR
VDD
OSC
NC
SPM
SUB
COMP
5
VC
SCK
6
VCS
MOSI
7
COMP
9
10
11
12
13
14
15
16
17
18
19
36
35
/CS
34
33
32
/MISO
IN1
MISO
IN2
COMS
IN3
REF
IN4
NC
COMP
LD1
IN5
LD2
IN6
LD3
IN7
LD4
IN8
LD5
COMP
37
NC
4
8
38
31
30
29
28
27
26
25
24
23
22
LD6
SUB
NC
LD7
NC
LD8
21
20
SCLT3 -8BT8
Figure 3. Basic application diagram
VCS
UVA
SPI
SCLT3 -8
RPD
VDD
VC
RC
COMP
8-input
type 1/3
CLT
8 / 16-bit
O-T
/CS
O-T
State transfer
IN8
RREF
COMS
SCK
IN1
Digital filters
RI
Voltage
regulator
SPI
MISO
CPHA = 0
CPOL = 0
/MISO
O-T
MOSI
REF
SPM
DVR
OSC
O-T = opto-transistor
or isolator
LD8
LD1
Figure 4. Basic module input characteristics in type 3
30
2.1mA
VI (V)
RI = 2.2 kΩ
VI = V IN + RI x IIN
25
2.6mA
ON
RI
20
SCLT
15
11V
10
OFF
5
0
0
6/31
0.5
1
1.5
IIN (mA)
Doc ID15191 Rev 6
2
2.5
3
Field bus
controller
RS
SCLT3-8BT8
Functional description
2
Functional description
2.1
Input power section
The SCLT3-8 is an 8-line input termination device designed for 24 V DC automation
applications. It provides the front-end circuitry of a digital input module (I/O) in industrial
automation.
Available in an eight-channel configuration, it offers a high-density termination by minimizing
the conducting dissipation and the external component count.
Made of an input voltage protection, a serial current limiting circuit and an output interface,
each channel circuit terminates the connection between the logic input and its associated
high side sensor or switch.
The SCLT3-8 is an 8-line current limiting input array compatible with type 1 and 3 (>2 mA)
characteristics of the IEC 61131-2 standard.
Each input voltage clamping block protects the module input against electromagnetic
interferences such as those described in the IEC 61131-2 standard and IEC 61000-4-2
(ESD), 4-4 (transient burst), 4-5 (voltage surge) and 4-6 (conducted radio frequency
interferences) standards. The supply input is also designed with such a protection structure.
The current limiting circuit connected between the INI and LDI pins is set externally by a
resistor RREF and is compensated over the full temperature range. Thanks to its 10%
tolerance, the current limitation allows drastic reduction of the input dissipation, 78 mW per
channel in type 3, compared with a resistive input.
Furthermore, the SCLT3-8 is housed in a very low RTH exposed pad HTSSOP surface
mount package that allows the PCB cooling pad to be reduced. The overall module and
printed board size become smaller and the hot spot effect is reduced.
In accordance with IEC 61131-2 standard when the input current is less than 1.5 mA, the
output circuit maintains the associated output data and the visual LED in the OFF state.
When the module input voltage VI, including the 2.2 kΩ input resistor, is higher than 11 V
corresponding to a SCLT input voltage VIN higher than 5 V, the output circuit puts its
associated output data in ON state.
2.2
Visual input LED driver
Since the inputs are indicated with an LED, as described in the IEC 61131-2 standard, an
LED driver is implemented on each input power section.
This driver has two major benefits for the application. First, it takes its electrical energy
directly from the input current. This energy is free being, in any case, dissipated in the SCLT.
Second, it eliminates the need for extra pins on the I/O controller to manage the LED drive.
The LED will be powered when the input voltage VI is higher than 11 V, and it is turned off
when the input current is less than 1.5 mA.
The LED diodes will be driven in a low side configuration, all cathodes connected to ground.
This topology naturally protects the LEDs and simplifies their wiring (8 wires plus the ground
wire). When the LEDs are not used, the pins LDI are grounded to COMP to maintain the
path of the input current.
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Functional description
SCLT3-8BT8
Figure 5. Low side front-end input topology including the ESD surge protection and
the LED driver
IN
VR
Filter
LD
COMP
2.3
The input digital filter
A digital filter is implemented between the input state comparator and the input state
register. It consists of a 2-step sampling circuit that is controlled by an oscillator as shown on
Figure 6.
The filtering time tFT is set by the external oscillator resistor and is a function of the oscillator
period tCKF:
2 x tCKF < tFT < 3 x tCKF
tCKF = Divider ratio x tOSC (ROSC)
This period can be adjusted between 20 µs and 3000 µs and is compatible with the
IEC 61131-2 standard as shown on Table 2.
Table 2. Typical setting of the digital filter timings
Input speed
Input frequency
Fast
Medium
Slow
60 kHz
20 kHz
5 kHz
300 Hz
Min. filter time tFT
20 µs
50 µs
230 µs
3.0 ms
OSC resistance
51 kΩ
150 kΩ
82 kΩ
1.3 MΩ
CKF period tCKF
10 µs
25 µs
115 µs
1500 µs
DVR connection
COMS
COMS
VDD
VDD
8
8
64
64
Divider ratio
Being placed in the front end of the module, this filter increases the transient immunity of the
SCLT and its SPI logic circuitry. It also simplifies the input management software task of the
ASIC controller.
8/31
Doc ID15191 Rev 6
SCLT3-8BT8
Functional description
Figure 6. Two-step digital filter placed after the analog section of the logic input
IN
D
Q
D
Q
D
Q
S
CK
/Q
CK
/Q
CK
/Q
R
Q
OUT
CKF
CKF
IN
OUT
2.4
Operation of the SCLT with the SPI bus
The SPI bus master controller manages the data transfer with the chip select signal /CS and
controls the data shift in the register with the clock SCK signal. This data transfer operation
is defined by the phase CPHA and the polarity CPOL of the clock. The SCLT runs with an SPI
master protocol mode: CPHA = 0 and CPOL = 0.
Figure 7. Serial data format frame with a master running in CPHA = 0 and CPOL = 0
mode
CS
SCK
MOSI
MISO
DATA CAPTURE
1
MSBM
MSBS
1
2
3
4
13
14
15
16
14
13
12
3
2
1
LSBM
MSBS
14
13
12
3
2
1
LSBS
MSBM
2
3
4
13
14
15
16
The transfer of the SCLT input state in the SPI register starts when the chip select signal
/CS falls and ends when this chip select signal rises back.
The transfer of data out of the SCLT slave MISO output starts immediately when the chip
select signal /CS goes low. The input MOSI is captured and presented to the shift register
on each rising edge of the clock SCK. The data are shifted in this register on each falling
edge of the serial clock SCK, the data bits are written on the output MISO with the most
significant bit first.
During all operations, VDD is held stable within the specified operating range.
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Functional description
SCLT3-8BT8
2.5
SPI bus signal description
2.5.1
Chip select /CS
When the chip select signal /CS is high, the data transfer is disabled (SCK and MOSI
signals are ignored) and the data output MISO is in high impedance tri-state Z.
Driving this input low enables the communication process. At each falling edge of the /CS,
the 8 input logic states, and the 8 control bits are loaded into the SPI shift register.
The chip select /CS must toggle only when the serial clock signal SCK is in low state.
2.5.2
Serial clock SCK
This clock signal defines the speed and sequence of the SPI communication and is
controlled by the master unit. Its transient edges define the serial protocol operation:
•
The falling edge generates the shift of the data in the register and the last bit writing on
the output MISO.
•
The rising edge generates the capture of the data on the input MOSI.
The SCLT internal circuitry secures the SPI operation in mode CPOL = 0, CPHA = 0. When
the chip select /CS falls low, the first edge of the clock SCK to be active is always the rising
edge.
Figure 8. Functional diagram of the SPI logic inputs SCK, MOSI, /CS
VDD
250kΩ
2pF
2kΩ
SCK
ESD HBM
SCLT3-8
2.5.3
Serial data input MOSI
This input signal MOSI is used to shift external data bits into the SCLT register from the
most significant (MSB) bit to the least significant one (LSB). The data bits are captured by
the SCLT on the rising edge of the serial clock signal SCK.
Like the clock SCK, and the chip select /CS, the MOSI input circuit is filtered as shown in
Figure 8, in order to match maximum speed operation and improve the EFT burst immunity
of the SPI circuit.
2.5.4
Serial data output MISO
This output signal is used to transfer data out of the SCLT slave circuit from the most
significant bit (MSB) to the least significant bit (LSB). The first data bit is written out when
the chip select /CS goes low. Then the other data bits are written out on the falling edge of
the clock signal SCK.
The output MISO goes to high impedance tri-state shown on Table 5 when the /CS signal
goes in high state.
10/31
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SCLT3-8BT8
2.5.5
Functional description
SPI shift register operation selector SPM
The input SPM allows the operation of the SPI shift register to be configured for an 8-bit or
16-bit operation.
When SPM is set low (COMP) the shift register runs in a 16-bit mode and transfers both the
input state bits and the control bits. When SPM is set high (VDD) the shift register runs in an
8-bit mode and transfers the eight input state bits in a faster transfer process.
This SPM input can be changed, and the SPI operation modified, only when the chip select
/CS is high (no communication).
2.6
SPI data transfer operation
2.6.1
SPI data frame
The selected structure of the SPI is a 16-bit word in order to be able to implement the input
state data and some control bits, such as the UVA alarm, the 4 parity bits and the two low
and high state stop bits.
2.6.2
SPI data transfer
The SCLT transfers its 16 data bits through the SPI within one chip select Hi-Lo-Hi
sequence. So, this length defines the minimum length that the shift register of the SPI
master controller is able to capture 16 bits.
Table 3 shows the 16-bit mode in which the data are transferred starting from the data bits,
the control bits and ending with a stop bit.
Table 3. SPI data transfer organization versus SCLT input states with SPM = 0
Bit #
LSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Control
High
Low
PC4
PC3
PC2
PC1
/OTA
/UVA
Last out
Bit #
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
MSB
Data
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
First out
Table 4. SPI data transfer organization versus CLT input states with SPM = 1
Bit #
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
MSB
Data
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
Last out
First out
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Functional description
2.6.3
SCLT3-8BT8
SPI transfer speed
The speed of the SPI is defined by the clock frequency and the data frame transfer time. In
the SCLT application the transfer time correspond to the input scanning time programmed
by the I/O controller.
In a 16-bit mode this scanning time should be less than 500 µs for a 64-input module (128
bits to transfer) where it should be about 160 µs for a 16-input module (32 bits to transfer).
To obtain such scanning with the data frame structure, the clock frequency is set
respectively at 256 kHz and 200 kHz.
Figure 9. SCLT slave unit operation, input MOSI and output MISO timing diagrams
/CS
TCH
TLD
SCK
TCL
1
2
TS
MSBM
MOSI
15
14
MSBS
TR
THC
TDT
16
TH
1
TD
TA
MISO
TF
TFO
14
1
LSBM
MSBS
LSBS
MSBM
TRO
The clock frequency is limited by the application requirements to secure the immunity of the
SPI section against fast transient disturbances and keep the isolator consumption low
enough.
The SCLT maximum SPI clock frequency is 2 MHz.
•
•
The minimum SPI clock period is also defined by the capability of the SCLT to capture
data on MOSI and to write out data on MISO as shown in Table 9.
–
Capture rule: tCH > tH
–
Write out rule: tD + tS < tCL = tC - tCH
At the start of the transfer sequence the first rising edge of the clock SCK should occur
after the data writing on the SPI output MISO corresponding with the propagation time
tA, avoiding missing the first data: tLD > tA + tS
In between two transfer sequences the output driver of the SPI circuit should go in high
impedance before any new transfer operation so falling edge of the chip select /CS:
tDIS < tDT.
12/31
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SCLT3-8BT8
Functional description
Figure 10. SPI shift register data transfer sequence versus SCLT input states
PC1
OTA
U VA
IN1
IN2
PC1
OTA
U VA
IN1
IN2
B14
IN7
B10
B11
B12
B13
B14
IN8
IN7
MSB
B13
IN6
MSB
IN6
B4
B12
IN5
B3
IN5
B2
B11
IN3
B1
B10
IN4
LSB
IN3
0
IN4
B4
PC2
B9
B3
PC3
B8
PC2
B7
PC3
B6
B2
LO
B5
B1
PC4
B9
LO
B8
PC4
B7
LSB
HI
B6
0
MOSI
MSB
MISO
MOSI
MSB
Z
MSB
IN8
/CS
B5
HI
/CS=”1”
MISO
SCK1
MSB
MSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
MSB
SCK1
B14
MSB
MSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B14
SCK2
B13
B14
B14
MSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B13
SCK15
LSB
B1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
LSB
LSB
SCK16
LSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
LSB
LSB
SCK16
MSB
LSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
MSB
/CS
MSB
SCK1
MSB
0
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
Z
0
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
Z
2.7
Control bit signals of the SPI transferred data frame
2.7.1
Power bus voltage monitoring
The UVA circuit generates the alarm /UVA that is active low when the power bus voltage is
lower than the activation threshold VCON, 17 V typical, and it is disabled high when the
power bus voltage rises above the threshold VCOFF, 18 V typical as shown in Figure 12.
The UVA circuit is robust enough to resist ESD and EFT effects, and a filter is added to
avoid drop out effects. The analog level can be adjusted externally with a pull down resistor.
The power bus voltage is sensed from a separate sensing pin VCS. The overall accuracy is
about 15% and the alarm circuit should be insensitive to drop out of less than 1 ms.
The under voltage detection does not lead to the SCLT internal shutdown but generates an
alarm /UVA that is transmitted through the SPI on control bit #7.
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Figure 11. UVA circuit block diagram
VCC
RS
VCS
1ms delay filter
/UVA
VBG
RPD
COMP
ESD
SCLT3-8
The power supply diagnostics help to determine if the input state is really low or if some
power bus failure is damaging the quality of this state signal.
2.7.2
Over temperature alarm
A temperature sensor, equivalent to a diode drop voltage, is placed on the power section of
the SCLT in order to sense its operating junction temperature.
This protection allows abnormal temperature cases to be detected. The input reverse
polarity generates higher current in the inputs, more than twice that shown in the application
section, and a maintenance action allows the overall system and functional reliability to be
improved.
The alarm signal /OTA is enabled, low state active, when the junction temperature is higher
than the activation threshold TON, 150 °C typical, and it is disabled when the junction
temperature falls below the threshold TOFF, 135 °C typical as shown in Figure 12.
The over temperature detection does not lead to the SCLT internal shutdown but generates
an alarm OTA that is transmitted through the SPI on control bit #6. So, it is up to the I/O
controller to launch the appropriate action on the system to reduce the constraint in the I/O
module.
Figure 12. Logic behavior of the OTA and UVA alarm control bits
TOFF
2.7.3
TON
VCCON
VCCOFF
Parity checksum bits calculation and transfer
The aim of the parity checksum bit is to detect one error in the transferred SPI word. Several
parity checksum bits are generated and transmitted through the SPI on the control bit #2 to
#5.
Transmission errors can occur because of the ESD / surge effects or the indirect effects of
EFT burst tests beyond the required levels.
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Functional description
It is supposed such disturbances affect one bit at a time during the SPI frame transfer. EFT
burst repetition rate is about 200 µs (5 kHz) and the SPI 16-bit frame should last less than
160 µs.
A parity bit on the full byte should be obtained by applying an “exclusive NOR” Boolean
operation to the eight logic input states (PC1): it goes high when the parity of the 8 inputs is
even.
The other parity bits PC2 and PC3 are obtained with an “exclusive NOR” Boolean operation
respectively on the MSB half data byte (IN5 to IN8) and the LSB half data byte (IN1 to IN4),
and PC4 on the middle half data byte (IN3 to IN6): they go high when the parity of the 4
considered inputs is even.
These parity bits allow one error to be detected at a time in the SPI data transfer, and this
error can be corrected thanks to a second SPI data scan because the corrupted data bit
should be statistically different between the two scan sequences.
A method is proposed to correct one corrupted input data bit. If full data byte parity bit PC1 is
wrong, the first scanned word is stored, and the SCLT input data are scanned immediately
twice. Then the first full byte parity bit is checked with its half byte parity bits to confirm the
error. The second scanned SPI word is stored and its full byte parity bit is also checked.
By using the parity bits on half data byte (the 4 MSB, the 4 LSB, the 4 medium bits), the
corrupted input data bit couple of the two scanned SPI words can be detected and the input
data byte can be re-synthesized by isolating and replacing these failing bit couples.
2.7.4
SPI hardware interface
All the logic level output signals deliver 80% of VDD for high state and 20% VDD for low state.
This SPI circuit is designed to drive CMOS circuit or isolated opto-transistors. Since the
clock frequency is always higher than 100 kHz, high speed opto-transistors are selected
requiring higher driving input and output currents.
The biasing resistors of their output transistors are kept external to allow the speed and the
device sourcing to be set for each application, providing thus more flexibility in the choice of
these isolators.
In Section 3: Application considerations, several cases are proposed for the major
applications.
2.7.5
Loss of VCC power supply
The operation of the SCLT is extended beyond the levels required in the IEC 61131-2
standard to allow the implementation of the under voltage alarm UVA as described in
Section 2.7.1.
If there is no more power feeding on the VCC input, the SCLT chip goes to sleep mode, and
the MISO output is forced in low state during SPI transfer attempt. The last SPI control data
bit is a stop bit placed normally in high state. The loss of power supply is detected by
checking its state. If low, the output is disabled by the internal power reset POR.
This POR signal is active in low state when VC is less than 9 V or the internal power supply
VDD is less than 3.25 V.
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SCLT3-8BT8
Table 5. Logic state of the SPI output versus the power loss signal POR and the SPI
chip select /CS
POR
/CS
MISO
/MISO
SPI status
1
1
Z
Z
Normal with no communication
1
0
1
0
Normal with communication
1
0
0
1
Normal with communication
0
1
Z
Z
Power loss with no communication
0
0
0
1
Power loss with communication attempt
Figure 13. Logic status of the SCLT power supply
Power supply status
Loss of power
UV Alarm
15V
Power good
17V
19V
VC = V CC - RC x (IC + IDD)
~5V
16/31
9V
11V
VCC
IEC61131-2 level
13V
UVA
/CS = Lo
POR
/CS = Lo
MISO
/CS = Lo ; IN ASIC = MISO (non inverting isolator)
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VC
SCLT3-8BT8
Functional description
Table 6. Absolute ratings
Symbol
Pin
Parameter name and conditions
Value
Unit
VCC
VC
Bus power supply DC voltage, 500 Ω < RC < 2.2 kΩ
- 0.3 to 35
V
VC
VC
SCLT power supply voltage, R C = 0 kΩ
- 0.3 to 30
V
ICC
VC
Maximum bus power supply current
15
mA
VCS
VCS
Sensing bus power supply voltage
- 0.3 to 6
V
VDD
VDD
Internal logic power supply voltage
-0.3 to 6
V
IDD
VDD
Maximum logic power supply current
12
mA
VIN
IN I
Input steady state voltage, RI = 0 Ω, I = 1 to 8
- 0.3 to 30
V
IIN
IN I
Input forward and reverse current range, RI = 2.2 kΩ
-20 to +10
mA
LVO
MISO
/MISO
Logic output voltage
-0.3 to 6
V
LVI
SCK
/CS MOSI
Logic input voltage
-0.3 to 6
V
VLD
LDI
Maximum LED output voltage, I = 1 to 8
3
V
IREF
REF
Maximum sourced reference current
300
µA
IOSC
OSC
Maximum sourced oscillator current
120
µA
PDIS
All
Maximum dissipation at TAMB= 85 °C
850
mW
TJ
All
Storage junction temperature
- 40 to 150
°C
Table 7. Thermal resistance
Symbol
Parameter name and conditions
Value
Unit
RTH(j-a)
Thermal resistance junction to ambient
Copper thickness= 35 µm, printed board copper surface S = 1 cm²
80
°C/W
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Functional description
SCLT3-8BT8
Table 8. Operating conditions
Symbol
Pin
Parameter name and conditions
Value
Unit
VCC
VC
Bus power supply steady state voltage, RC > 500 Ω
15 to 35
V
VC
VC
SCLT power supply voltage range
9 to 30
V
VCS
VCS
Sensing bus power supply voltage, RS = 1.5 MΩ
0 to 5
V
VDD
VDD
Internal logic power supply voltage
5
V
IDD
VDD
Maximum logic power supply current, RC = 500 Ω
10
mA
- 30 to 35
V
4.7 to 18
kΩ
VI
INI
RREF
REF
Current limiter reference resistance range
Rosc
OSC
Filter oscillator resistance range
15 k to 1.5 M
Ω
Maximum single input frequency
20
kHz
FIN MAX
Input repetitive steady state voltage, RI > 1.8 kΩ
FSCK
SCK
SPI clock frequency range
0.1 to 2
MHz
tC
SCK
Clock period range
0.5 to 10
µs
tCH
SCK
Minimum clock active width
0.25
ns
DCCH
SCK
Clock duty cycle
50
%
tR, tF
Minimum logic inputs rise and fall times
50
ns
LVI
SCK,
/CS,
MOSI
0 to 5.5
V
VLD
LDI
2.7
V
Operating ambient temperature range
- 40 to 85
°C
Operating junction temperature range
- 40 to 150
°C
TAMB
Tj
Logic input voltage
Maximum LED output voltage, I = 1 to 8
ALL
1. VI = VIN + RI x IIN , I = 1 to 8
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Functional description
Table 9. DC electrical characteristics(1)
Symbol
Pin
Name
Conditions
Min.
Typ.
Max.
Unit
Input current limitation
ILIM
IN
Input limiting current
VIN = 5.5 to 26 V
VCC = 19 V to 30 V
TAMB = -40 to + 85 °C
2.1
2.35
2.6
mA
VLOW
IN
Low current input voltage
IIN = 100 µA, RI = 0 Ω
-
2.6
3
V
VLIM TH
IN
Current limiter activation
voltage
IIN = 95% x ILIM_TYP(2)
-
8.5
-
V
32.0
38.8
46.0
V
Input and supply protection
VCL
IN, VC
Clamping voltage
IIN= 7 mA, tP=1 ms,
RREF open
Input state operation
VON
IN
On state input voltage
TAMB = -40 to + 85 °C(3)
Iin = Ioff = 1.5 A
5
-
-
V
VTH_ON
IN
Input on state threshold
RI = 2.2 kΩ, OFF to ON
4.5
4.75
5
V
VTH_OFF
IN
Input off state threshold
RI = 2.2 kΩ, ON to OFF
3.5
3.75
4
V
°C(4)
2.9
3
3.4
V
2.0
2.25
2.6
mA
1.13
1.37
µs
20
28
µs
51
1200
kΩ
VOFF
IN
Maximum Off state voltage TAMB = -40 to + 85
ION
LDI
On state LED current
VI = 11 V
Input digital filter
tOSC
OSC
ROSC
OSC
tCKF
-
tFT
IN
Oscillator period
ROSC = 51 kΩ
ROSC = 1200 kΩ
Oscillator resistance
CKF period
DVR = VDD
64 x tOSC
DVR = COMS
8 x tOSC
Filtering time
2xtCKF
3xtCKF
Power supply circuit
VRSON
VC
Power on supply voltage
TAMB = - 40 to + 85 °C
8
8.5
9
V
VRSOFF
VC
Power off supply voltage
TAMB = - 40 to + 85 °C
7.5
8.1
8.5
V
IC
VC
Supply current
VCC = 30 V,
VDD, MISO, /MISO open
1.2
1.6
2.3
mA
Internal supply voltage
IDD= 10 mA, CDD = 33 nF,
RC = 500 Ω,
TAMB = - 40 to + 85 °C
4.5
5
5.5
V
Internal supply voltage
IDD= 4 mA, CDD = 33 nF
TAMB = - 40 to + 85 °C
4.75
5
5.25
V
VDD
VDD
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SCLT3-8BT8
Table 9. DC electrical characteristics(1) (continued)
Symbol
Pin
Name
Conditions
Min.
Typ.
Max.
Unit
Over temperature alarm
TON
IN
Thermal alarm activation
-
148
-
°C
TOFF
IN
Thermal alarm release
-
135
-
°C
16
17
18
-
1
-
Under voltage alarm
VCON
VCC
Power voltage alarm
VCC
Voltage release hysteresis
VBG
VCS
Input activation voltage
1.25
1.27
1.30
VHY
VCS
Input hysteresis voltage
-
0.1
-
tD_ON
VCS
Drop out filtering time
1
1.7
-
ΔVOFF ON
RS =1.5 MΩ, RPD =120 kΩ
V
ms
1. TJ = 25 °C, VCC = 24 V, RREF = 15 kΩ, RI = 2.2 kΩ, RC = 2.2 kΩ with reference to COMP = COMS voltage, unless otherwise
specified.
2. VLIM = VIN + 95% x ILIM x R I
3. Corresponding to VI = 11 V with RI = 2.2 kΩ.
4. Corresponding to VI = 5 V or IIN = 1.5 mA.
Table 10. SPI serial bus link electrical characteristics(1)
Symbol
Pin
Name
tLD
SCK
Enable lead time
tHC
SCK
tDT
/CS
CIN
SCK,
/CS,
MOSI
Input filter time constant
Referred to VDD
Input pull up current
LVI = 0 V
tS
MOSI
Data setup time
tH
MOSI
LVIH
MOSI
SCK,
/CS
tRC
IIN
LVIL
LVOH
LVOL
1.
/MISO
MISO
Conditions
Min.
Typ.
Max.
Unit
/CS falling to SCK rising
-
-
50
ns
Clock hold time
SCK falling to /CS rising
-
-
250
ns
Transfer delay time
/CS rising to /CS falling
-
500
-
ns
-
10
-
pF
-
4
-
ns
15
22
30
µA
MOSI toggling to SCK rising
-
-
25
ns
Data hold time
SCK rising to MOSI toggling
-
-
25
ns
Logic input high voltage
Share of VDD
-
-
70
%
Logic input low voltage
Share of VDD
30
-
-
%
Logic output high voltage
IOH = 3 mA
4
4.5
-
V
Logic output low voltage
IOH = 3 mA
-
0.45
1
V
SCK falling to MISO
toggling, CO = 15 pF
-
35
50
ns
IMISO = 3 mA
-
20
50
ns
CO = 15 pF
-
20
50
ns
/CS falling to MISO toggling
-
55
80
ns
Input capacitance
tD
/MISO
MISO
Write out propagation time
tRO,
tFO
/MISO
MISO
MISO signal fall/rise time
tA
MISO
Output access time
TJ = 25 °C, VCC = 24 V, VDD = 5 V with respect to COMS ground pin, unless otherwise specified.
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Functional description
Table 11. Electromagnetic compatibility ratings(1)
Symbol
VPPB
VPP
VPP
VESD
VESD
Node
VI
VI
VCC
Parameter name and conditions
Value
Burst Peak Pulse Voltage: IEC 61000-4-4 class 3
CC = 33 nF, C I = 22 nF, F= 5 kHz, test criteria A
((2) and (3))
± 2.5
Burst Peak Pulse Voltage: IEC 61000-4-4 class 4
CC = 33 nF, C I = 22 nF, F= 5 kHz, test criteria A(2)
±4
Surge Peak Pulse Voltage: IEC 61000-4-5 class 3
R = 42 Ω, test criteria B(2)
±1
Surge Peak Pulse Voltage: IEC 61000-4-5 class 3,
R = 2 Ω, RC = 2.2 kΩ(2)
± 2.5
Surge Peak Pulse Voltage: IEC 61000-4-5 class 3,
R = 2 Ω, RC = 500 Ω(2)
±1
ESD protection, IEC 61000-4-2 class 4, in air
Per input to ground, test criteria B
±15
kV
kV
kV
IN
VCC
Unit
kV
ESD protection, IEC 61000-4-2 class 4, in contact
Per input to ground COMP, test criteria B
±8
ESD protection, IEC 61000-4-2 class 4, in air
Test criteria B, CC = 33 nF, RC = 500 Ω
±15
ESD protection, IEC 61000-4-2 class 4, in contact
Test criteria B, CC = 33 nF, RC = 500 Ω
±8
kV
1. TJ = 25 °C, RI = 2.2 kΩ unless otherwise specified.
2. Respect to ground COMP. Test according to standard with schematic described in application section.
3. Fully functional without any SPI data correction.
Figure 14. Typical limiting current ILIM versus reference resistance RREF
ILIM (mA)
6
5.5
VCC = 24 V
VI = 24 V
TJ = 25 °C
5
4.5
4
3.5
3
2.5
2
RREF (kΩ)
1.5
1
0
2
4
6
8
10
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SCLT3-8BT8
Figure 15. Typical limiting current ILIM versus junction temperature TJ
ILIM (mA)
2.8
Rref = 15 kΩ with RIN = 2.2 kΩ, VI = 11 to 30 V, VCC = 11 to 30 V
2.7
2.6
2.5
2.4
2.3
2.2
TJ (°C)
2.1
2
-25
0
25
50
75
100
125
150
Figure 16. Relative variation of minimum filter time TFT MIN versus junction
temperature TJ
TFT MIN / T FT MIN (25°C)
1.15
1.1
1.05
ROSC < 150kΩ
1
ROSC = 1.2MΩ
0.95
0.9
TJ (°C)
0.85
25
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75
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150
SCLT3-8BT8
Application considerations
3
Application considerations
3.1
SCLT serial link configurations
As long as /CS is low, a slave is able to transmit data bits whatever the length of the data
frames. This feature allows several SCLT circuits to be connected in a daisy chain
configuration.
In the daisy chain configuration with several SCLT circuits (N) all the circuits are addressed
by the same chip select and receive the clock signals from the same clock. They all work
synchronously.
The SPI output MISO of the previous SCLTP-1 device is connected to the SPI input MOSI of
the next SCLTP device and the output MISO of the last SCLTN is connected to the MISO
input of the master. The MOSI of the first SCLT1 can be kept open or grounded.
So, the SPI master reads the whole chain of N 16-bit words starting with the word of the last
SCLTN and ending with the word of the first SCLT1.
Detailed considerations on SPI operation and daisy chain configurations are also described
in ST application notes AN2846 and AN3031.
Figure 17. SCLT connection to opto-couplers, bus controller SPI master, and output
driver
Case 1: 16-DI
Case 2: 8-DI and 8-DO
SCK
SCK
MISO
MISO
SCLT 2
MOSI
/CS
SCK
SCK
MISO
MISO
/CS1
/CS
/CS2
SCK
SCLT 1
MOSI
SCLT
/CS
SCK
VNI8200XP
SDI
MOSI
SDO
MISO
SPI master
SPI master
/CS
MOSI
/CS
= 1Mbps coupler
The configuration of the SCLT slave bus circuit allows the master bus controller to operate
with other slave circuits in a different phase and polarity mode as long as it runs
communication with SCLT in CPHA = 0 and C POL = 0.
The requirement to transfer data in a daisy chain configuration is to use an SPI control
master circuit that is able to send and receive a bit stream from 8 minimum up to 128 within
one chip select sequence depending on the number of SCLTs and SPI mode (8- or 16-bit).
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Application considerations
3.1.1
SCLT3-8BT8
Interfacing SPI section to I/O controller through opto-transistors
Figure 18. Opto-couplers connection between dual SCLT circuit and their master bus
controller
VDD1
5V.REG
SCK
100nF
VDD1
330W
CCK
SCK
/CS
To LED
330W
RCK
SPI master
Controller
ACPL-K73L
SCLT3 - 8
330W
MISO
330W
VDD2
VDD2
100nF
RMI
COMS
VOUT
330W
SPI data output
3.2
LED
VOUT
ON
HIGH
OFF
LOW
MISO
CMI
ACPL-W70L
FCK
RCK, RCS , RMI
CCK, CCS, CMI
220
220Ω
470pF
< 1MHz
High speed operation with magnetic isolators
Figure 19. Connection of SCLT with a magnetic or capacitive coupler for alarm active
in low level
VDD1
MISO
Alarm = low
SPI
VDD1
VDD1
VDD2
/MISO
SCLT
VDD2
VDD2
MISO
Isolator
SPI master
Magnetic isolators are suitable for higher frequency operation, above 1 MHz, because of
their lower current consumption.
But their primary power supply loss leads to a high state output that is not compatible with
an alarm strategy active in low state as with SCLT. To overcome this issue, two inverting
logic buffers can be implemented in the SPI hardware chain. The ASIC will also detect a
primary supply loss with a low state. The SCLT is designed providing both MISO and /MISO
in order to simplify this hardware environment as shown on Figure 19.
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3.3
Application considerations
Reverse polarity robustness
Any reverse polarity of an input INI generates some negative current in the circuit that does
not disturb the operation of the other input channels as long as the power supply is working
properly (VCC >19 V).
Such a case is not dissipative for the SCLT, < 15 mW per input, but consideration should be
given to the input resistors. A resistance of RIN = 2.2 kΩ should produce a dissipation of
0.38 W at VI = 30 V. The dissipation rating of the input resistor is set according to the
duration of this situation.
The power supply VC withstands also this kind of stress, the whole circuit being disabled.
3.4
Surge voltage immunity
Figure 20. Surge voltage test diagram of the SCLT circuit
VPPS = +/- 1kV with 2 Ω
VCC
RC
VC
RI
VPPI
IN1
VPP
I
VPPS
RI
VPPI = +/- 1kV with 42 Ω
IN2
RI
SCLT3-8
VPPI
GND
COMP
5 nF
PE/FE
The input and supply pins are designed to withstand electromagnetic interferences. They
are protected by a clamping function that is connected to the ground pin COMP. Combined
with the serial input resistance RI, this clamping protection is effective against the fast
transient bursts (±4 kV, IEC 61000-4-4) and the voltage surges (±1 kV, IEC 61000-4-5).
This topology allows the surge voltage to be applied from each input to other inputs, the
ground and the supply contacts in differential or common modes as shown in Figure 20.
Thanks to its high resistance RC = 500 Ω, the supply pin VC withstands ±1 kV surge voltage
according to IEC 61000-4-5 using same diagram as Figure 20. With RC = 2.2 kΩ, this power
supply pin withstands more than ±2.5 kV.
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SCLT3-8BT8
3.5
Fast transient burst immunity
3.5.1
Considerations on the power section
The EFT protection is achieved with the same strategy as ESD and surge protection. An
input capacitor CI can be added to meet mainly the IEC 61000-4-6 conducted RFI immunity.
These capacitors play a key role in suppressing front-end electrical stresses. Their
capacitance can be about 22 nF (to validate by test for both EFT and RFI tests).
Detailed considerations for EMC performances, board design precautions and component
selections are also described in ST application notes AN2846 and AN3031.
3.5.2
Considerations on the logic section
The SPI section is not submitted directly to the transient burst disturbance because this
disturbance is applied to the logic input wires and the power supply wires.
Since the power section is protected with the clamping diodes, their serial impedance and
the digital filters, the logic section and the serial interface is protected against the effects of
transients.
Nevertheless, the SPI section may be submitted to indirect effects of the EFT transients. So,
the design of the power supplies (VCC and VDD), the opto-transistors, and the printed circuit
board are done with care to minimize the layout influences.
As shown on the suggested opto-transistor schematic on Figure 13, some RC network and
power supply decoupling capacitors should be added to meet the reinforced immunity level
up to 2 MHz operation.
3.6
Under voltage alarm setting for IEC and device-net
applications
The power supply voltage VCC is monitored by the UVA block through the input resistances
RS and R PD.
VCON = VBG x (1 + RS/RPD)
VCOFF = (VBG + VHY) x (1 + RS/RPD)
With VBG = 1.26 V and VHY = 0.1 V
For IEC 6131 PLC applications, the alarm /UVA is activated when the power bus voltage is
lower than the activation threshold VCON, 17 V typical, and is released when the power bus
voltage rises above the threshold VCOFF, 18 V typical.
In this application, the resistances are set to RS = 1.5 MΩ and RPD = 120 kΩ.
For device-net applications, the sensor power supply voltage can vary from 11 V to 25 V.
The UVA alarm is set between the lower value and the SCLT minimum operation that is set
at 9 V.
The power supply resistor RC is reduced to match the minimum voltage VCC with the device
current consumption. The VC pin robustness could be increased with an additional clamping
diode DZ to fit the 1 kV surge requirement. In this case an RC resistance of 150 Ω and an
SMAJ30A Transil™ diode are indicated.
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Application considerations
Figure 21. Power supply connection versus IEC 61131-2 norm levels (left) and devicenet norm levels (right)
VCC
RC
SCLT3 -8
VC
SCLT3 -8
DZ = SMAJ30A
VCC
RC
VC
5V.REG
5V.REG
DZ
RS
RS
VCS
VCS
UVA
UVA
RPD
3.7
RPD
Input operation for the device-net applications
If the sensor connected to the SCLT input has a drop voltage less than 1 V, this input runs
with an on-state threshold equal to 10 V. Reducing the input resistance RIN = 1.8 kΩ, the
SCLT input meets such an operation.
3.8
Dissipation calculation in the SCLT3-8 circuit
Table 12. Evaluation of dissipation in the SCLT3-8(1) with RC = 500 Ω and IDD = 7 mA
Circuit
Count
Drop voltage (V)
Current
(mA)
Losses
(mW)
V Regulator
1
30 - 500 x 0.007 - 5 = 21.5
7
150
Current limiter
8
30 - 2200 x 0.0026 = 24.3
< 2.6
505
Quiescent current
1
30 - 500 x 0.0018 = 29.1
1.8
53
Total
708
1. Thermal resistance is less than: 90 °C/W corresponding to ΔT = 150 - 85 = 65 °C, PD = 708 mW.
Figure 22. Relative variation of junction-to-ambient thermal resistance RTH_JA versus
printed circuit board copper surface SCU
Rth(j-a) (°C/W)
Printed circuit board, FR4 epoxy
single layer, copper thickness = 35 µm
120
100
80
60
40
20
SCU (mm²)
0
0
20
40
60
80
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100
120
140
160
180
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Package information
4
SCLT3-8BT8
Package information
•
Epoxy meets UL94, V0
•
Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1
HTSSOP-38 package information
The exposed pad of the HTSSOP-38 improves heat transfer from the input dissipation to the
printed circuit board. Increasing the copper surface helps to reduce any hot point on the
board.
Figure 23. HTSSOP-38 package outline
38
20
E E1
1
c
e 19
D
14°
0.25 mm
A2
A
P
b
A1
L
P1
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Ø
SCLT3-8BT8
Package information
Table 13. HTSSOP-38 package mechanical data
Dimensions
Ref.
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.1
-
-
0.043
A1
0.05
-
0.15
0.002
-
0.006
A2
0.85
0.9
0.95
0.033
0.035
0.037
b
0.17
-
0.27
0.007
-
0.011
c
0.09
-
0.20
0.003
-
0.008
D
9.60
9.70
9.80
0.378
0.382
0.386
E1
4.30
4.40
4.50
0.169
0.173
0.177
e
-
0.50
-
-
0.020
-
E
-
6.40
-
-
0.252
-
L
0.50
0.60
0.70
0.020
0.024
0.027
P
6.40
6.50
6.60
0.252
0.256
0.260
P1
3.10
3.20
3.30
0.122
0.126
0.130
Ø
0°
-
8°
0°
-
8°
Figure 24. Footprint (dimensions in mm)
0.5
1.30
0.60
7.10
3.30
4.50
0.3
6.60
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Ordering Information
5
SCLT3-8BT8
Ordering Information
Figure 25. Ordering information scheme
SCLT
3 -
8
B
T8
SCLT = Serial output current limiting termination
3 = 3 mA current setting
8 = Eight channels
B = EMC Level
±1 kV according to IEC 61000-4-5
T8 = HTSSOP-38 package
Table 14. Ordering information
6
Order code
Marking
Package
Weight
Base qty
Delivery mode
SCLT3-8BT8-TR
SCLT3-8BT8
HTSSOP-38
114 mg
2500
Tape and reel
SCLT3-8BT8
SCLT3-8BT8
HTSSOP-38
114 mg
50
Tube
Revision history
Table 15. Document revision history
30/31
Date
Revision
Changes
17-Nov-2008
1
Initial release.
04-May-2009
2
Updated mechanical data for package HTSSOP-38.
02-Nov-2009
3
Updated parameters in Table 9 and Table 10. Added Figure 14,
Figure 15, Figure 16, and Figure 22.
08-Sep-2011
4
Updated application note from AN2853 to AN3031.
04-Jul-2013
5
Updated Figure 8 and Figure 9.
12-Nov-2015
6
Updated Table 9.
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SCLT3-8BT8
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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