Wolfson WM8776 EV2M Audio CODEC User Handbook
The WM8776 EV2M is a high performance stereo audio CODEC for surround sound processing applications for home hi-fi, DVD-RW and other audio visual equipment. This evaluation platform and documentation should be used in conjunction with the latest version of the WM8776 datasheet. The datasheet gives device functionality information as well as timing and data format requirements. This evaluation platform has been designed to allow the user ease of use and give optimum performance in device measurement as well as providing the user with the ability to listen to the excellent audio quality offered by the WM8776.
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WM8776-EV2M
Evaluation Board User Handbook
Rev 1.3
WM8776-EV2M
TABLE OF CONTENTS
TABLE OF CONTENTS .................................................................................. 2
INTRODUCTION ............................................................................................. 3
GETTING STARTED ....................................................................................... 3
EVALUATION KIT CHECKLIST ............................................................................. 3
CUSTOMER REQUIREMENTS.............................................................................. 3
EVALUATION BOARD OPERATION.............................................................. 4
POWER SUPPLIES ............................................................................................... 4
BOARD FUNCTIONALITY ..................................................................................... 4
BOARD INPUT ....................................................................................................... 5
BOARD OUTPUT ................................................................................................... 5
INTERFACES......................................................................................................... 6
HEADERS .............................................................................................................. 6
LINKS, JUMPERS AND SWITCHES ...................................................................... 7
WM8776 OPERATION .................................................................................... 9
SOFTWARE CONTROL......................................................................................... 9
SERIAL INTERFACE SOFTWARE DESCRIPTION...................................... 11
SOFTWARE DOWNLOAD ................................................................................... 11
SOFTWARE INSTALLATION............................................................................... 11
SOFTWARE OPERATION ................................................................................... 11
POWER DOWN AND INTERFACE CONTROL.................................................... 17
ADC, DAC AND OUTPUT CONTROL .................................................................. 18
VOLUME CONTROL ............................................................................................ 19
LIMITER/ALC CONTROL ..................................................................................... 20
SCHEMATIC LAYOUT ......................................................................................... 21
WM8776-EV2B PCB LAYOUT ............................................................................. 29
WM8776-EV2B BILL OF MATERIAL............................................................ 33
APPENDIX .................................................................................................... 35
DAC AND ADC ALTERNATIVE AUDIO INTERFACE CONFIGURATION ... 35
MASTER/SLAVE MODE....................................................................................... 35
EXTERNAL DSP CONNECTION TO THE WM8776-EV1B .......................... 37
AUDIO INTERFACE CONNECTIONS.................................................................. 37
SOFTWARE INTERFACE .................................................................................... 39
CONNECTION DIAGRAMS.................................................................................. 40
ADDITIONAL WM8776-EV1B SETUP RECOMMENDATIONS .................... 42
ADC TO DAC LOOPBACK ........................................................................... 42
EVALUATION SUPPORT ............................................................................. 44
IMPORTANT NOTICE ................................................................................... 45
ADDRESS: ........................................................................................................... 45 w Rev 1.3, March 2005
2
INTRODUCTION
WM8776-EV2M
The WM8776 is a high performance stereo audio CODEC for surround sound processing applications for home hi-fi, DVD-RW and other audio visual equipment.
This evaluation platform and documentation should be used in conjunction with the latest version of the WM8776 datasheet. The datasheet gives device functionality information as well as timing and data format requirements.
This evaluation platform has been designed to allow the user ease of use and give optimum performance in device measurement as well as providing the user with the ability to listen to the excellent audio quality offered by the WM8776.
GETTING STARTED
EVALUATION KIT CHECKLIST
The following items are available from Wolfson:
• WM8776-EV1B Evaluation Board (order from Wolfson)
•
WM8776-EV1S .exe file for control software (download from http://www.wolfsonmicro.com/ )
• WM8776-EV1M User Handbook (download from http://www.wolfsonmicro.com/ )
CUSTOMER REQUIREMENTS
Minimum customer requirements are:
•
D.C. Power supply of +5V
•
D.C. Power supply of +2.7V to +5.5V
• D.C. Power supply of +/-12.0V
• PC and printer cable (for software control)
Minimum PC spec requirements are:
•
Win95/98/NT/2000/XP
•
486 Processor
DAC Signal Path Requires:
•
Digital coaxial or optical data source
• 1 set of active stereo speakers and/or 1 set of headphones
ADC Signal Path Requires:
•
Analogue coaxial signal source
• Digital coaxial or optical data receiving unit
Analogue Signal Path Requires:
•
Analogue coaxial signal source
• 1 set of active stereo speakers and/or 1 set of headphones w Rev 1.3, March 2005
3
WM8776-EV2M
EVALUATION BOARD OPERATION
POWER SUPPLIES
Using appropriate power leads with 4mm connectors, power supplies should be connected as described in Table 1.
REF-DES
J1
J2
J54
J10
J8
J7
J2
J70
SOCKET NAME
+5V
DVDD
AVDD
HPVDD
+12V
-12V
GND
GND
Table 1 Power Supply Connections
SUPPLY
+5V
+2.7V to +3.6V
+2.7V to +5.5V
+2.7V to +5.5V
+12V
-12V
0V
0V
The GND and GND connections may be connected to a common GND on the supply with no reduction in performance.
To reduce the supply connections that need to be attached to the EVB, site L10 is populated with a 0R resistor shorting AVDD and HPVDD. In this configuration it is recommended that the supply only be attached to AVDD. If separate supplies are required the 0R resistor should be removed from site L10.
Note: Refer to WM8776 datasheet for limitations on individual supply voltages.
Important: Exceeding the recommended maximum voltage can damage EVB components.
Under voltage may cause improper operation of some or all of the EVB components.
BOARD FUNCTIONALITY
There are three options for inputting digital data into the WM8776 evaluation board. There is a coaxial input (J5) via a standard phono connector or an optical input (U1) via a standard optical receiver module. A direct digital input is also available via one side of a 2x8 pin header (H1).
The analogue input signals are applied to the evaluation board via double phono connectors
J4 (AIN_LEFT/RIGHT1), J13 (AIN_LEFT/RIGHT2), J14 (AIN_LEFT/RIGHT3), J20
(AIN_LEFT/RIGHT4), J21 (AIN_LEFT/RIGHT5). A analogue AUX signal input can also be applied to the evaluation board via a double phono connector J24 (AUX_LEFT/RIGHT).
There are two options for outputting digital data from the WM8776 evaluation board. There is a coaxial output (J18) via a standard phono connector. The digital signals may also be accessed via one side of a 2x8 pin header (H2).
The line analogue outputs of the board are via phono connectors J19 (VOUTL) and J23
(VOUTR). The headphone analogue outputs of the board are via a 3.5mm jack socket J46
(HEADPHONE_OUT).
All WM8776 device pins are accessible for easy measurement via the 2x6 pin headers (H3,
H4, H5 and H6) running up each side of the device.
Level-shift IC’s (U5 and U8) are used to shift the fixed +5V digital input from the CS8427 (U4) down to the same level as DVDD and vice-versa. w Rev 1.3, March 2005
4
BOARD INPUT
WM8776-EV2M
BOARD OUTPUT
REF-DES
J5
U1
SOCKET NAME
SPDIF_IN
DIGITAL_OPTICAL
INPUT
SIGNAL
Digital (AES/EBU, UEC958,
S/PDIF, EIAJ CP340/1201) signal.
Digital (AES/EBU, UEC958,
S/PDIF, EIAJ CP340/1201) optical signal.
Table 2 Digital Inputs
REF-DES
J4
J13
J14
J20
J21
J24
SOCKET NAME
AIN_L/R_1
AIN_L/R_2
AIN_L/R_3
AIN_L/R_4
AIN_L/R_5
AUX_L/R
SIGNAL
Analogue Input signal
Analogue Input signal
Analogue Input signal
Analogue Input signal
Analogue Input signal
Analogue Input signal
Analogue signals applied to these connectors are AC coupled before being input to the WM8776.
Table 3 Analogue Inputs
Note: When used in Slave Mode, an SPDIF signal must still be applied to phono connector
J5. This input signal is used to allow correct operation of the CS8427 as well as being used to generate the MCLK for the WM8776.
REF-DES
J18
SOCKET NAME
SPDIF_OUT
SIGNAL
Digital (AES/EBU, UEC958,
S/PDIF, EIAJ CP340/1201) signal.
Table 4 Digital Output
REF-DES
J46
J23
J19
SOCKET NAME
HEADPHONE OUT
VOUT_R
VOUT_L
Table 5 Analogue Outputs
SIGNAL
Headphone Output
Line Output
Line Output w Rev 1.3, March 2005
5
WM8776-EV2M
INTERFACES
HEADERS
Figure 1 Interfaces
H1
1/2
3/4
5/6
7/8
9/10
11/12
13/14
15/16
LNK1
1
2
SIGNAL
DIN
GND
DACLRC
GND
DACBCLK
GND
DACMCLK
GND
SIGNAL
ZFLAGL
AGND
J1 J2 J3
SW6
H2
SW2
H1
O PEN
0
1
J15
J16
J12
J25
J9
J54
H3
LNK6
J11
J32
J33
LNK4 LNK1
J22
1 J17
1
J70
J30 J29
H6
H4
J10
H5
J8 J7
H2
16/15
14/13
12/11
10/9
8/7
6/5
4/3
2/1
LNK4
1
2
SIGNAL
GND
ADCMCLK
GND
DIN
GND
ADCBCLK
GND
ADCLRC
SIGNAL
ZFLAGR
AGND
KEY
1
3
5
7
9
11
13
15
12
10
8
6
4
2
1
2
1
2
3
11
9
7
5
3
1
2
4
6
8
10
12
14
16
5
7
1
3
1
2
6
8
2
4 w Rev 1.3, March 2005
6
1
2
7
8
9
10
3
4
5
6
11
12
Table 6 Headers
9
10
11
12
H4
5
6
7
8
H3
1
2
3
4
13
14
19
20
21
22
15
16
17
18
23
24
WM8776
1
2
3
4
5
6
7
8
9
10
11
12
WM8776
LINKS, JUMPERS AND SWITCHES
J12
LINKS AND
JUMPERS
J15 (BCLK)
J16 (LRC)
J25
J9 (MCLK)
J32, J33, J22, J17
J29
J30
LINK/JUMPER
STATUS
OPEN
SHORT
OPEN
SHORT
OPEN
SHORT
OPEN
SHORT
OPEN
SHORT
OPEN
SHORT
OPEN
SHORT
OPEN
SHORT
Table 7 Links
ADCLRC
DGND
DVDD
MODE
CE
DI
CL
HPOUTL
HPGND
HPVDD
HPOUTR
NC
PIN NAME
AIN2L
AIN1R
AIN1L
DACBCLK
DACMCLK
DIN
DACLRC
ZFLAGR
ZFLAGL
ADCBCLK
ADCMCLK
DOUT
PIN NAME
37
38
43
44
45
46
39
40
41
42
47
48
WM8776
25
26
27
28
29
30
31
32
33
34
35
36
WM8776
1
2
7
8
9
10
3
4
5
6
11
12
9
10
11
12
H6
5
6
7
8
H5
1
2
3
4
WM8776-EV2M
DESCRIPTION
DAC Slave Mode (Level shift direction) [default setting]
DAC Master Mode
Master mode
Slave mode (Ties ADCBCLK to DACBCLK) [default setting]
Master mode
Slave mode (Ties ADCLRC to DACLRC) [default setting]
ADC Slave Mode (Level shift direction) [default setting]
ADC Master Mode
Master mode
Slave mode (Ties DACMCLK to ADCMCLK) [default setting]
OUT Signals are AC coupled [default setting]
OUT Signals are not AC coupled
AINR input gain set to 1
AINR input gain set to 0.5 [default setting]
AINL input gain set to 1
AINL input gain set to 0.5 [default setting]
AGND
AINVGR
AINOPR
AINVGL
AINOPL
AIN5R
AIN5L
AIN4R
AIN4L
AIN3R
AIN3L
AIN2R
PIN NAME
NC
VOUTL
VOUTR
VMIDDAC
DACREFN
DACREFP
AUXR
AUXL
VMIDADC
ADCREFGND
ADCREFP
AVDD
PIN NAME w Rev 1.3, March 2005
7
WM8776-EV2M
SW1
SWITCHES
SW2
(DATA FORMAT)
J11
(Software Control)
LNK6
(5V tolerant supply control)
SWITCH STATUS
ON
OFF
Pins 1 and 2
SHORT
Pins 2 and 3
SHORT
Centre Position
DESCRIPTION
After an input data format change has been made using
SW2, the CS8427 will only latch the new settings after SW1 has been pressed and released.
1 2 3 4 5 6 DATA FORMAT
1 0 0 1 0 0 I2S Compatible [default setting]
1 0 0 0 0 1 24-bit Right Justified
1 0 0 0 0 0 Left Justified
2-wire Control Mode
3-wire (SPI) Control Mode [default setting]
DVDD Supply for S/W and mode control [default setting]
+5v Supply for S/W and mode control
No Supply for S/W and mode control
Table 8 Switches w Rev 1.3, March 2005
8
WM8776-EV2M
WM8776 OPERATION
SOFTWARE CONTROL
There are two possible serial software control modes that may be selected to operate the
WM8776. The standard SPI user interface is a 3-wire solution with the second option being a 2-wire solution.
3-WIRE MODE
To operate the WM8776 in SPI (3-wire) mode, jumper switch J11 must be set to the OFF position, selection of 3 wire mode will be indicated by D1 being OFF. The 3-wire serial interface then becomes active on pins 17(CE), 18(DI) and 19(CL). The serial interface on the board can be connected to a PC via the printer port or any other standard parallel port. The port used can be selected through the software provided. The software supplied with this kit gives the user access to all the possible features provided by the WM8776. The 3-wire latch, data and clock lines may also be connected to the board via the test points TP6 (CE), TP18
(DI) and TP4 (CL).
Please refer to the WM8776 datasheet for full details of the serial interface timing and all register features. latch
CE
CL
DI B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 control register address control register data bits
Figure 2 3-Wire Serial Interface
2-WIRE MODE
To operate the WM8776 in 2-wire mode, jumper switch J11 must be set to the ON position, selection of 2 wire mode will be indicated by D1 being ON. The 2-wire serial interface becomes active on pins 18(DI) and 19(CL). The serial interface on the board can be connected to a PC via the printer port or any other standard parallel port. Note: a bi- directional parallel port is required for 2-wire operation
1
. The 2-wire data and clock lines may also be connected to the board via the test points TP18 (DI) and TP4 (CL).
When used in 2-wire mode, the WM8776 has two possible addresses (0011010 [0x34h] or
0011011 [0x36h]) that are selectable by pulling CSB low or high. If connecting a probe to the
Test Points it must be noted that the CSB line is pulled high on the WM8776 evaluation board selecting address 0011011. CSB must be pulled low or driven low through the software writes if address 0011010 is used (as is done in the WM8776-EV1S software provided).
Figure 3 2-Wire Serial Interface w
Note:
1
If the 2-wire mode is not reporting as expected then the most likely cause is that the parallel port being used is not bi-directional. In most PC’s, the parallel port can be configured in the BIOS settings during initial power up.
Rev 1.3, March 2005
9
WM8776-EV2M
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R14 (0Eh)
R15 (0Fh)
R16 (10h)
R17 (11h)
R18 (12h)
R19 (13h)
R20 (14h)
R21 (15h)
REGISTER
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
R9 (09h)
R10 (0Ah)
1011
1100
1101
1110
1111
10000
10001
10010
10011
10100
10101
ADDRESS
(Bit 15 – 9)
0
1
10
111
1000
1001
1010
11
100
101
110
Bit[8]
UPDATE
UPDATE
UPDATEA
Bit[7]
LINMUTE
RINMUTE
LO1ZC
UPDATED
UPDATED
UPDATED
0
0
0
0
0
0
ADCHPD
ADCMS
0
0
0
0
0
DACMS
0
ZCLA
ZCRA
LCSEL[1:0]
LCEN ALCZC
FDECAY
0 0
CHGPERZC[1:0]
LRBOTH MUTELA
R22 (16h) 10110 0 0
R23 (17h) 10111
Table 9 Mapping of Program Registers
Bit[6] Bit[5] Bit[4] Bit[3]
HPLA[6:0]
HPRA[6:0]
HPMASTA[6:0]
Bit[2] Bit[1] Bit[0]
0
0
0
0
0
AINPD
0
PL[3:0]
0
0
0
DACWL[1:0]
0
0
LDA[7:0]
RDA[7:0]
0
MASTDA[7:0]
0
TOD
0
0
DACBCP
ADCWL[1:0]
DACRATE[2:0]
0 0
LAG[7:0]
RAG[7:0]
ADCBCP
ADCOSR
HPPD
MAXGAIN[2:0]
0 0
0
DCY[3:0]
MUTERA
0
TRANWIN[2:0]
0
NGTH[2:0]
0 PHASE[1:0]
IZD
0
DZFM[1:0]
DACLRP
ATC
0
DZCEN
DMUTE
DEEMPH
DACFMT[1:0]
ADCLRP
DACPD
ATK[3:0]
MAXATTEN[3:0]
AMX[4:0]
0 writing 000000000 to this register resets all registers to their default state
ADCFMT[1:0]
ADCRATE[2:0]
ADCPD PDWN
LCT[3:0]
HLD[3:0]
NGG
MX[2:0]
NGAT
Please refer to the WM8776 datasheet for full details of the serial interface timing and all register features. w Rev 1.3, March 2005
10
SERIAL INTERFACE SOFTWARE DESCRIPTION
WM8776-EV2M
The following section will detail the downloading and installation of evaluation software and also the operation of the software and the functionality of each control button. Details the main panel, hidden panels and details on the hardware setup required to use the main functional buttons “DAC Setup”, “ADC Setup” AND “Line Setup” will be provided.
SOFTWARE DOWNLOAD
The current evaluation board software should be downloaded from the Wolfson website
[ www.wolfsonmicro.com
].
From the homepage it is recommended that you do a search for ‘WM8776’ and select the
‘more’ button located under the ‘EVALUATION BOARDS’ heading. Select ‘DOWNLOAD’ from the right hand side of the screen under the ‘SOFTWARE’ heading. Once you have accepted the licence agreement you can select the WM8776_EV1S_REVx.x.ZIP link and download to your hard drive.
SOFTWARE INSTALLATION
Once the .zip file has been downloaded, to install the software:
•
Open the .zip file
• Double click on the setup.exe file.
•
Follow the on-screen installation instructions and save to the desired location.
The software can then be opened by either running the extracted WM8776_EV1_REV1.exe file from the saved location. Alternatively select: Start > Programs > WM8776-EV1S Revx.x >
WM8776-EV1S.
SOFTWARE OPERATION
Due to the many features offered by the WM8776 the software has been split into 4 different panels. This eases the complexity of the software making each panel less busy, the panels have also been grouped so that it makes it simple to control each section of the device.
The main menu panel shown in Figure 4 is used to call up the other panels as well as offering a number of pull-down menus. w Rev 1.3, March 2005
11
WM8776-EV2M w
Figure 4 Software Menu Panel
SUBMIT ALL
The ‘Submit All’ button will submit the current panel settings, within each of the four main panels to every register of the WM8776. This means changes within a number of different panels can be made and then submitted together.
WM8776 RESET
The ‘Reset’ button writes to the reset register (R23) but does not reset the control panel values. If the previous values are to be resubmitted then the ‘Submit All’ button should be pressed.
RESET SOFTWARE PANEL SETTINGS
If the user would like to start afresh then the ‘Reset Software Panel Settings’ button should also be pressed. Pressing this button does not write to the device, it only resets the panel settings to their default state.
WOLFSON LOGO
Left clicking on the Wolfson logo will open the PCs default web browser and go top the
Wolfson Microelectronics website (‘ www.wolfsonmicro.com
’).
On the main panel there are three buttons, “DAC Setup”, “ADC Setup” and “Line Setup” which have been provided as a quick start approach. Pressing either of these buttons will power up the DAC, ADC or Line signal paths in a known state as described in the following pages.
Rev 1.3, March 2005
12
WM8776-EV2M
Important: It must be noted that the CS8427 SPDIF decoder IC will only work at a rate of
256fs. This will limit the sample rates that may be set using the WM8776 unless an external source is used supplying signals directly to the relevant pins of header H1 or taking the signals from the relevant pins of header H2.
DAC SUBMIT SETUP
By pressing the ‘DAC Setup’ button, the software writes to the device setting the SPDIF_In through DAC to the VOUTL/R and Headphone outputs; active in 24-bit, I
2
S input data format.
Table 6 lists the required board settings to allow this signal path to become active. This is to ease the initial use of the WM8776 hardware and software until the user becomes familiar with both device and software operation.
+5v DGND
DVDD
+2.7V
to
+3.6V
AVDD
+2.7V
to
+5.5V
AGND
J1 J2 J3
SPDIF_
OUT
OPT
_IN
SPDIF_
IN
SW6
H2
0
1
E N O P
6 5 4 3
2 1
SW2
H1
J15
J16
J12
J25
J9
LNK4
LNK6
J11
J32
J33
J22
1
J54
H3
LNK1
J70
J30 J29
H6
J17
1
H4
J10
H5
J8 J7
Headphone Out
AIN_L/R_1
AIN_L/R_2
AIN_L/R_3
AIN_L/R_4
AIN_L/R_5
AUX_L/R
+12v -12v
Figure 5 Recommended DAC Setup w Rev 1.3, March 2005
13
WM8776-EV2M
H1
H2
J12
LINKS AND
J15 (BCLK)
J16 (LRC)
J25
J9 (MCLK)
SW2
JUMPERS
LNK6
J11
J32, J33, J22, J17
J29
J30
LINK/JUMPER
STATUS
DESCRIPTION
Fit jumpers (1,2)
(5,6) (9,10) (13,14)
DAC clocks and data input
No jumpers in place ADC clocks and data output
OPEN
OPEN
DAC Slave mode
Separate BCLK (To DAC only)
OPEN
OPEN
OPEN
Pins 1 and 2
SHORT
OFF
OPEN
OPEN
OPEN
Separate LRC (To DAC only)
ADC Slave mode
Separate MCLK (To DAC only)
1 2 3 4 5 6 DATA FORMAT
1 0 0 1 0 0 I2S Compatible
DVDD Supply for S/W and mode control
3-wire (SPI) Control Mode
OUT Signals are AC coupled
AINR input gain set to 1
AINL input gain set to 1
Table 10 DAC Setup Jumper Settings (Slave Mode)
ADC SUBMIT SETUP
By pressing the ‘ADC Setup’ button, the software writes to the device setting the AIN_L/R_1 through ADC to SPDIF_Out path active. As with the DAC setup described previously, this is to ease the initial use of the WM8776 until the user becomes familiar with both device and software operation. It should be noted that the SPDIF_In connection is still required to provide the necessary clocks to the WM8776 in this mode.
+5v DGND
DVDD
+2.7V
to
+3.6V
AVDD
+2.7V
to
+5.5V
AGND
The SPDIF input is required to provide clocks for the
WM8750 audio interface.
Figure 6 Recommended ADC Setup w
J1 J2 J3
SPDIF_
OUT
OPT
_IN
SPDIF_
IN
SW6
H2
0
1
N O PE
SW2
H1
J15
J16
J12
J25
J9
LNK4
LNK6
J11
J32
J33
J22
1
J54
LNK1
J70
H3
J30 J29
H6
J17
1
H4
J10
H5
J8 J7
Headphone Out
AIN_L/R_1
AIN_L/R_2
AIN_L/R_3
AIN_L/R_4
AIN_L/R_5
AUX_L/R
Rev 1.3, March 2005
14
WM8776-EV2M
H1
H2
J12
LINKS AND
JUMPERS
J15 (BCLK)
J16 (LRC)
J25
J9 (MCLK)
SW2
LINK/JUMPER
STATUS
Fit jumpers (5,6)
(9,10) (13,14)
Fit jumpers (1,2)
(5,6) (9,10) (13,14)
OPEN
SHORT
SHORT
OPEN
SHORT
DAC clocks
ADC clocks and data output from WM8776
LNK6
J11
J32, J33, J22, J17
J29
J30
Pins 1 and 2
SHORT
OFF
OPEN
SHORT
SHORT
Table 11 ADC Setup Jumper Setup (Slave Mode)
DESCRIPTION
DAC Slave mode
Link BCLK (DAC BCLK to ADC)
Link LRC (DAC LRC to ADC)
ADC Slave mode
Link MCLK ((DAC MCLK to ADC)
1 2 3 4 5 6 DATA FORMAT
1 0 0 1 0 0 I2S Compatible
DVDD Supply for S/W and mode control
3-wire (SPI) Control Mode
OUT Signals are AC coupled
AINR input gain set to 0.5
AINL input gain set to 0.5 w Rev 1.3, March 2005
15
WM8776-EV2M
LINE SUBMIT SETUP
By pressing the ‘Line Setup’ button, the software writes to the device setting the AIN_L/R_1 through the analogue path to the VOUTL/R and Headphone outputs. As with the previous configurations, this is to ease the initial use of the WM8776 until the user becomes familiar with both device and software operation.
Note: The WM8776 does not require an MCLK to operate in this mode. If the ADC or DAC are used then the MCLK would be required.
+5v DGND
DVDD
+2.7V
to
+3.6V
AVDD
+2.7V
to
+5.5V
AGND
J1 J2 J3
SPDIF_
OUT
OPT
_IN
SPDIF_
IN
SW6
H2
0
1
N OPE
SW2
H1
J15
J16
J12
J25
J9
LNK6
J11
J32
J54 J70 J10
AIN_L/R_1
J33
LNK4
J22
1
AIN_L/R_2
H3
J30 J29
H6
H5
AIN_L/R_3
AIN_L/R_4
LNK1
H4
AIN_L/R_5
J17
1
AUX_L/R
J8 J7
Headphone Out
+12v -12v
Figure 7 Recommended Line Setup w Rev 1.3, March 2005
16
WM8776-EV2M
H1
H2
J12
LINKS AND
JUMPERS
J15 (BCLK)
J16 (LRC)
J25
J9 (MCLK)
SW2
LNK6
J11
J32, J33, J22, J17
J29
J30
LINK/JUMPER
STATUS
No jumpers in place DAC clocks
No jumpers in place ADC clocks
OPEN
OPEN
DAC Slave mode
Separate BCLK
OPEN
OPEN
OPEN
Separate LRC
ADC Slave mode
Separate MCLK
DESCRIPTION
1 2 3 4 5 6 DATA FORMAT
1 0 0 1 0 0 I2S Compatible
DVDD Supply for S/W and mode control Pins 1 and 2
SHORT
OFF
OPEN
SHORT
SHORT
3-wire (SPI) Control Mode
OUT Signals are AC coupled
AINR input gain set to 0.5
AINL input gain set to 0.5
Table 12 Line Setup Jumper Setup (Slave Mode)
POWER DOWN AND INTERFACE CONTROL
w
Figure 8 Power and Interface Control
Rev 1.3, March 2005
17
WM8776-EV2M
The Power Down and Interface Control panel is used to enable/disable the various sections of the WM8776. It is also used to individually set the audio interface to the required data format for both the ADC and DAC. Pressing the ‘Power Submit’ button will cause the settings shown on this panel to be written to the WM8776. A full device register write is not sent using the ‘Power Submit’ button.
ADC, DAC AND OUTPUT CONTROL
Figure 9 DAC and ADC Control
The ADC, DAC and Output Control panel is used to control the ADC, DAC and Output Mixer related features of the WM8776. Pressing the ‘ADC, DAC and Output Submit’ button will cause the settings shown on this panel to be written to the WM8776. A full device register write is not sent using the ‘ADC, DAC and Output Submit’ button. w Rev 1.3, March 2005
18
VOLUME CONTROL
WM8776-EV2M
Figure 10 Volume Control
The Volume Control panel is used to control both analogue (input and Headphone output) and digital volume settings of the WM8776. The volume sliders update in ‘real’ time (i.e. the
‘Volume Submit’ button does not have to be pressed to update the output volume level) but will only have an effect on the output if the Volume Update bits are set. Once changes are made to the Volume Update bits or any other settings excluding the volume sliders, the
‘Volume Submit’ button must be left clicked for the change to take effect. Pressing the
‘Volume Submit’ button will cause the settings shown on this panel to be written to the
WM8776. A full device register write is not sent using the ‘Volume Submit’ button. w Rev 1.3, March 2005
19
WM8776-EV2M
LIMITER/ALC CONTROL
Figure 11 Mixer Control
The Limiter/ALC Control panel is used to control the many options offered by the WM8776 for either ALC (Automatic Level Control) or Limiter operation. The default of the WM8776 is for the operation to be disabled, this must firstly be enabled and then the correct limiter or
ALC function selected. Controls specific to ALC or limiter are dimmed and not controllable depending on the operation selected. The following control sliders update in ‘real’ time’:
Maximum Gain of PGA, Noise Gate Threshold and Limiter Threshold/ALC Target Level (i.e. the ‘Limiter/ALC Submit’ button does not have to be pressed to update these settings).
Pressing the ‘Limiter/ALC Submit’ button will cause the settings shown on this panel to be written to the WM8776. A full device register write is not sent using the ‘Limiter/ALC Submit’ button. w Rev 1.3, March 2005
20
SCHEMATIC LAYOUT
Figure 12 Functional Diagram
WM8776-EV2M w Rev 1.3, March 2005
21
WM8776-EV2M
Figure 13 Digital Input w Rev 1.3, March 2005
22
Figure 14 Software Control
WM8776-EV2M w Rev 1.3, March 2005
23
WM8776-EV2M
Figure 15 Level Shift w Rev 1.3, March 2005
24
WM8776-EV2M
Figure 16 Analogue Input and Output Mute w Rev 1.3, March 2005
25
WM8776-EV2M
Figure 17 WM8776 w Rev 1.3, March 2005
26
Figure 18 Analogue Output
WM8776-EV2M w Rev 1.3, March 2005
27
WM8776-EV2M
Figure 19 Power w Rev 1.3, March 2005
28
WM8776-EV2B PCB LAYOUT
WM8776-EV2M
Figure 20 Top Layer Silkscreen w Rev 1.3, March 2005
29
WM8776-EV2M
Figure 21 Top Layer w Rev 1.3, March 2005
30
WM8776-EV2M
Figure 22 Bottom Layer w Rev 1.3, March 2005
31
WM8776-EV2M
Figure 23 Bottom Layer Silkscreen w Rev 1.3, March 2005
32
WM8776-EV2B BILL OF MATERIAL
Description
0.1uF 0805 SMD Ceramic Capacitor 50V X7R
WM8776-EV2M
220pF 0805 SMD Ceramic Capacitor 50V X7R
0.01uF 0805 SMD Ceramic Capacitor 50V X7R
10uF 6.3 Dia 2.5 pitch Oscon Through Hole Cap. 16V 20%
680pF 0805 SMD Ceramic Capacitor 50V NPO
1nF 0805 SMD Ceramic Capacitor 50V NPO
220pF 0805 SMD Ceramic Capacitor 50V NPO
Unpop 0805 SMD Ceramic Capacitor site
330uF M Series 10 Dia 5 pitch Through Hole Cap. 35V 20%
10uF 6.3 Dia 2.5 pitch Oscon Through Hole Cap. 25V 20%
4.7nF 1206 SMD Ceramic Capacitor 50V X7R
100uF 8 Dia 3.5 pitch Oscon Through Hole Cap. 10V 20%
220uF 10 Dia 5 pitch Oscon Through Hole Cap. 10V 20%
10uF 10V SMD Tantalum Capacitor case A
HSMY-C670 0805 SMD Chip LED YELLOW
2x8 2.54mm pitch PCB Pin Header VERTICAL
2x6 2.54mm pitch PCB Pin Header VERTICAL
4mm Non-Insulated Panel Socket 16A
1x2 Jumper Switch 0.1" on-off VERTICAL
Phono Socket PCB mount BLACK
Phono Socket PCB mount WHITE
Phono Socket PCB mount RED
Phono Socket PCB mount Pair Red/White
3.5mm Jack Socket 6.5mm Centre Height
Phono Socket PCB mount YELLOW
36-way Centronics/IEE488 PCB mountable Connector
1x2 PCB Pin Header 0.1" VERTICAL
47uH 1210 Surface Mount Inductor 'PA series'
0R 1206 Resistor on 1210 Inductor site
Unpop 1210 Surface Mount Inductor site
3.3uH 1210 Surface Mount Inductor '1210A series'
JSK9-16-G0 PCB 1x3 Jumper Switch 0.1" Center-off
VERTICAL
PCB Mounting Hole 3.2mm Dia.
TN0200T N- Channel MOSFET SOT23
MMBT3906 PNP Bipolar Transistor SOT23
FMMT617 NPN Switching Transistor SOT23
0R 0805 SMD chip resistor 1% 0.1W
33R 0805 SMD chip resistor 1% 0.1W
10K 0805 SMD chip resistor 1% 0.1W
Reference Designator
C1, C3, C4, C5, C10, C11, C14, C15, C16,
C18, C20, C21, C22, C25, C26, C31, C34, C35,
C37, C42, C44, C45, C46, C53, C60, C64, C69,
C73, C74, C75, C79, C109
C12, C13, C17, C51, C67, C68, C71, C72, C76,
C80, C81, C82, C83, C84
C2
C24, C30, C32, C33, C36, C38, C55, C56, C57,
C58, C59, C62,C63, C70
C27, C39
C28, C40
C29, C41
C47, C48, C50, C124, C125, C126, C127,
C128
C49
C6, C9, C19, C23, C43, C52, C54, C77, C78,
C86, C87, C115
C61
C65
C7, C66
C8
D1
H1, H2
H3, H4, H5, H6
J1, J2, J3, J7, J8, J10, J54, J70
J11
J18
J19
J23
J4, J13, J14, J20, J21, J24
J46
J5
J6
J9, J12, J15, J16, J17, J22, J25, J29, J30, J32,
J33, LNK1, LNK4
L1
L2, L4, L6, L7, L8, L9, L10
L3
L5
LNK6
MTH1, MTH2, MTH3, MTH4, MTH5
Q1, Q2, Q3
Q10, Q11
Q4, Q5
R1, R27, R34, R38, R54, R60, R67, R73, R74,
R76, R77, R125, R126, R127
R10, R11, R12, R13, R14, R15, R16, R17, R37,
R48
R18, R28, R29, R39, R41, R49, R50, R51, R52,
R56, R57, R58, R59, R61, R62, R63, R64, R65,
R68, R70, R72, R86, R87, R88,
Qty
32
14
1
12
1
6
1
1
8
1
1
1
1
13
1
1
2
4
1
1
2
1
14
2
2
2
8
5
3
2
2
14
1
7
1
1
1
10
24 w Rev 1.3, March 2005
33
WM8776-EV2M
100K 0805 SMD chip resistor 1% 0.1W
75R 0805 SMD chip resistor 1% 0.125W
560R 0805 SMD chip resistor 1% 0.1W
4K7 0805 SMD chip resistor 1% 0.1W
1K2 0805 SMD chip resistor 1% 0.1W
Unpopulated 0805 resistor site
1K8 0805 SMD chip resistor 1% 0.1W
7K5 0805 SMD chip resistor 1% 0.125W
49R9 0805 SMD chip resistor 1% 0.125W
5k1 0805 SMD chip resistor 1% 0.125W
620R 0805 SMD chip resistor 1% 0.1W
3K 0805 SMD chip resistor 1% 0.1W
1K 0805 SMD chip resistor 1% 0.1W
47k 1206 SMD chip 4 resistor array 5% 0.063W
Slotted Panhead Screw - M3 thread; 12mm long
Hexagonal brass M3 size spacer 20mm length
B3F1000 SPNO PCB mount switch
DIL Switch 6-Way Rocker
1.32mm PCB Test Terminal BLACK
1.32mm PCB Test Terminal RED
TORX176 Digital Audio Optical Receiver
2:1 Ratio 96KHz SPDIF Digital Audio transformer SOIC (1)
DS1813 5V active Low Power-On-Reset chip SOT
CS8427 96KHz Audio Transceiver
74ALVC164245 16 Bit Dual Supply Bus Transceiver SSO
WM8776 24-bit; Stereo CODEC with 5 Channel I/P Mux
Plain M3 size washer
Table 13 WM8776-EV1M Bill of Materials
R19
R2
R20
R21, R22, R23, R32, R36, R40, R44
R24, R25, R26, R47
R3, R6, R35, R46, R66, R123, R124, R128,
R129, R130, R131, R132
R30, R42
R31, R43
R33, R45
R4,R75, R78, R85
R5
R53
R55
R7, R8, R9
SC1, SC2, SC3, SC4, SC6
SPR1, SPR2, SPR3, SPR4, SPR6
SW1
SW2
TP1, TP2, TP3, TP5, TP7, TP10, TP14, TP15,
TP22, TP27, TP28
TP4, TP6, TP8, TP9, TP12, TP13, TP16, TP18,
TP19, TP20, TP21, TP23, TP24, TP25, TP26
U1
U2
U3
U4
U5, U8
U9
WSH1, WSH2, WSH3, WSH4, WSH6
5
1
1
11
1
1
3
5
2
2
2
4
1
1
1
1
7
4
12
15
1
2
1
5
1
1
1
Note:
1
The audio transformer used on this board is manufactured by Scientific Conversion
Inc. ( www.scientificonversion.com) . w Rev 1.3, March 2005
34
APPENDIX
WM8776-EV2M
DAC AND ADC ALTERNATIVE AUDIO INTERFACE CONFIGURATION
The DAC and ADC have separate left/right clocks, bit clocks, master clocks and data I/O’s.
The audio interface for each may be configured independently to operate as master or slave.
In slave mode ADCLRC, DACLRC, ADCBCLK and DACBCLK are all inputs. In master mode
ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs.
Previous configuration details (ADC, DAC and Line setup) have configured the WM8776 for slave mode. Also the clocks for the audio interface have been generated from the SPDIF crystal and for operation of the ADC common MCLK (fit J9), LRC (fit J16) and BCLK (fit J15) clocks were used. The following information details the configuration of the DAC and ADC for master mode and also the configuration for independent DAC and ADC audio interface.
MASTER/SLAVE MODE
The WM8776-EV1B has the ability to configure the WM8776 for independent DAC and ADC in either master or slave mode. This means that there are four configurable options, the following details the recommended jumper settings for these options.
1. DAC and ADC = Slave. This configuration has been detailed during the software operation explanation.
2. DAC and ADC = Master. The following switch and jumper settings should be made.
LINKS AND
JUMPERS
H1
LIINK/JUMPER
STATUS
Fit all jumpers
DESCRIPTION
DAC clocks to SPDIF crystal
Fit all jumpers ADC clocks to SPDIF crystal H2
J12
J15 (BCLK)
J16 (LRC)
J25
J9 (MCLK)
SW2
LNK6
J11
J32, J33, J22, J17
J29
J30
SHORT
OPEN
OPEN
SHORT
SHORT
Pins 1 and 2 SHORT
OFF
OPEN
SHORT
SHORT
DAC Master mode (Level shift direction)
BCLK not linked (DAC BCLK to ADC)
LRC not linked (DAC LRC to ADC)
ADC Master mode (Level shift direction)
Link MCLK (DAC MCLK to ADC)
Note 1
1 2 3 4 5 6 DATA FORMAT
0 0 0 1 0 0 I2S Compatible
DVDD Supply for S/W and mode control
3-wire (SPI) Control Mode
OUT Signals are AC coupled
AINR input gain set to 0.5
AINL input gain set to 0.5 w Rev 1.3, March 2005
35
WM8776-EV2M
3. DAC = Master ADC = Slave. The following switch and jumper settings should be made.
LINKS AND
JUMPERS
H1
LIINK/JUMPER
STATUS
Fit all jumpers
DESCRIPTION
DAC clocks to SPDIF crystal
Fit all jumpers ADC clocks to SPDIF crystal H2
J12
J15 (BCLK)
J16 (LRC)
J25
J9 (MCLK)
SW2
LNK6
J11
J29
J30
SHORT
SHORT
SHORT
OPEN
SHORT
Pins 1 and 2 SHORT
OFF
J32, J33, J22, J17 OPEN
SHORT
SHORT
DAC Master mode (Level shift direction)
BCLK linked (DAC BCLK to ADC)
LRC linked (DAC LRC to ADC)
ADC Slave mode (Level shift direction)
Link MCLK (DAC MCLK to ADC)
DVDD Supply for S/W and mode control
3-wire (SPI) Control Mode
OUT Signals are AC coupled
AINR input gain set to 0.5
AINL input gain set to 0.5
Note 1
1 2 3 4 5 6 DATA FORMAT
0 0 0 1 0 0 I2S Compatible
4. DAC = Slave ADC = Master. The following switch and jumper settings should be made.
LINKS AND
JUMPERS
H1
H2
J12
J15 (BCLK)
J16 (LRC)
J25
J9 (MCLK)
SW2
LNK6
J29
J30
LIINK/JUMPER
STATUS
Fit all jumpers
Fit all jumpers
OPEN
OPEN
OPEN
SHORT
SHORT
Pins 1 and 2 SHORT
J11 OFF
J32, J33, J22, J17 OPEN
SHORT
SHORT
DESCRIPTION
DAC clocks to SPDIF crystal
ADC clocks to SPDIF crystal
DAC Slave mode (Level shift direction)
BCLK not linked (DAC BCLK to ADC)
LRC not linked (DAC LRC to ADC)
ADC Master mode (Level shift direction)
Link MCLK (DAC MCLK to ADC)
Note 1
1 2 3 4 5 6 DATA FORMAT
1 0 0 1 0 0 I2S Compatible
DVDD Supply for S/W and mode control
3-wire (SPI) Control Mode
OUT Signals are AC coupled
AINR input gain set to 0.5
AINL input gain set to 0.5
Notes:
1. The WM8776-EV1B does not have the functionality to create a separate ADCMCLK.
There are two options for the ADCMCLK. One is to use the common DACMCLK by fitting J9, as suggested in table above. The other is to apply an external MCLK to H2/13 and the ground to pin H2/15.
Software configuration of the WM8776 for master and slave mode can be found within the
“Power Down and General Audio” panel. It should be noted that the SPDIF crystal (U4) has an MCLK output which is fixed at 256x the sample rate (Fs). w Rev 1.3, March 2005
36
EXTERNAL DSP CONNECTION TO THE WM8776-EV1B
WM8776-EV2M
The WM8776-EV2B evaluation board has been designed to allow it to be easily connected to an external DSP platform with error free operation.
The following information is provided to ease the connection process and ensure that all signals sent and received by the WM8776-EV2B are reliable and at the correct voltage levels.
AUDIO INTERFACE CONNECTIONS
It is recommended that twisted pair (signal twisted with GND) or shielded wires are used to make the audio interface connections between the DSP and WM8776-EV1B platforms. This is to ensure that no interference or noise is picked up by the clocks or data lines, thus reducing performance and reliability.
When the WM8776 is set in Slave Mode (both DAC and ADC), the jumpers on header H1 should be removed, disconnecting the digital input section of the evaluation board. The audio interface timing and data signals from the DSP platform should then be connected as shown in Figure 24. The signals should be connected to H1 and not on the header strip H3 running up each side of the device. Connecting the signals on the output side of the levelshift IC (U5) will cause drive contention between U5 and the DSP and could result in damage to either or both devices. In most cases, the DSP supplies will be set around 3V for low power portable applications. The inputs to the level-shift IC (74ALVC164245) have a TTL threshold (i.e. Logic High = +2V(min); Logic Low = +0.8V(max)) and low input current requirements (i.e. 15uA max) allowing most DSP's to connect directly.
Figure 24 Connections from DSP Platform
The digital inputs to the WM8776 have a CMOS threshold (i.e. Logic High (min) =
DBVDDx0.7; Logic Low (max) = DBVDDx0.3). These are met directly by the level shift IC outputs.
The jumpers on H2 should also be removed, disconnecting the digital output section of the
WM8776 evaluation board. The DOUT data from the WM8776 should then be connected to the DSP via pin 12 of header strip H3 and the GND connection should be taken from pin 2 of header strip H4.
The ADCDAT signal should be taken direct from the WM8776 digital output (H3) as the output side of the level-shift IC (U5) from the WM8776 is pulled up to +5V which may overdrive and cause damage to the DSP inputs. The digital output levels of the WM8776 are
Logic High (min) = DBVDDx0.9; Logic Low (max) = DBVDDx0.1 which should meet the input level requirements of most DSPs running at +3V supplies. If the DSP is running with +5V supplies then the connections to it should be made from the output side of the level-shift IC
(U5), connecting the signals as shown in Figure 25. w Rev 1.3, March 2005
37
WM8776-EV2M
Figure 25 Data Connection to the DSP Platform (+5V tolerant input levels)
The connection in Figure 25 is applicable when links J9, J15 and J16 are fitted for common
DAC and ADC MCLK, BCLK and LRC clocks. If separate ADC clocks are required then remove links J9, J15 and J16 and connect the separate clocks as shown in Figure 26. The
ADC data can then be connected to the point relevant for the DSP power supply, either H2
(5v tolerant) or H3 (direct to device).
GND
ADCMCLK
GND
ADCBCLK
GND
ADCLRC
H2
Figure 26 Connections to DSP Platform
When the WM8776 is set to Master mode (DAC and ADC), the jumpers on header H1 should be removed, disconnecting the digital input section of the evaluation board. If an external MCLK signal is being used (i.e. supplied by the DSP) then the DSP platform should be connected as shown in Figure 27 for MCLK and DOUT. The signals should be connected to H1 and not on the header strip H3 running up the side of the device. Connecting the signals on the output side of the level-shift IC (U5) will cause drive contention between U5 and the DSP and could result in damage to either or both devices. In most cases, the DSP supplies will be set around +3V for low power portable applications. The inputs to the levelshift IC (74ALVC164245) have a TTL threshold (i.e. Logic High = +2V(min); Logic Low =
+0.8V(max)) and low input current requirements (i.e. 15uA max) allowing most DSPs to connect directly. w
Figure 27 Timing Connections from DSP Platform
The digital inputs to the WM8776 have a CMOS threshold (i.e. Logic High (min) =
DBVDDx0.7; Logic Low (max) = DBVDDx0.3). These are met directly by the level shift IC outputs.
The DACBCLK AND DACLRC signals can then be connected directly to the device on header H3 pin 4 and pin 7 respectively.
The jumpers on H2 should also be removed, disconnecting the digital output section of the
WM8776 evaluation board.
Rev 1.3, March 2005
38
WM8776-EV2M
The DOUT, ADCBCLK and ADCLRC signals should be taken direct from the WM8776 digital output as the output side of the level-shift IC (U4) from the WM8776 is pulled up to +5V which may overdrive and cause damage to the DSP inputs. The digital output levels of the
WM8776 are Logic High (min) = DBVDDx0.9; Logic Low (max) = DBVDDx0.1 which should meet the input level requirements of most DSPs running at +3V supplies. If the DSP is running with +5V supplies (and +5V tolerant inputs) then the connections from the WM8776 evaluation board to the DSP should be made from H2 on the output side of the level-shift IC from the WM8776 as shown in Figure 26. The ADCMCLK is only required as an input if a separate MCLK is required. For a common MCLK then by fitting link J9 the DACMCLK will be used.
If the DAC and ADC wish to be configured as separate master and slave then the details for separate operation for either master or slave previous should be followed. Care should be taken when connecting an external DSP to ensure that signal levels and device drive direction (DSP, WM8776 or level shift) are configured correctly to save component damage.
This will ensure that the DSP input level specifications are met.
SOFTWARE INTERFACE
When using the WM8776-EV1B evaluation board with a DSP platform, the registers may be set using the supplied software with a PC and parallel port cable as shown in Figure 28. The example shown is for ADC and DAC in slave mode, interface connections to the board depends on independent configuration for master or slave.
If the DSP is being used to write to the WM8776 registers as well as supplying/receiving the audio interface timing and data signals, then it is recommended that twisted pair or shielded wires are used to connect the DSP platform to the WM8776-EV1B. A direct connection can be made to pin 5 (CE), pin 6 (DI) and pin 7 (CL) of header strip H4 for 3-wire software mode as shown in Figure 29. This is applicable to a DSP with either 3v or 5v tolerant thresholds as the software pins have 5v thresholds.
The same connections apply for controlling the WM8776 via 2-wire software mode (i.e. only pin 6 (DI) and pin 7 (CL) of header strip H4 are used). Pin 5 (CE) can be pulled low on the board if device address 0011010 [0x34h] is required or pulled high address 0011011 [0x36h] is required. w Rev 1.3, March 2005
39
WM8776-EV2M
CONNECTION DIAGRAMS
m
Software
Control
DSP
Platform
Audio
Interface
H1
WM8776-EV1B
H6
H3 H5
H4
Figure 28 DSP Connection with PC Control using Wolfson Software w Rev 1.3, March 2005
40
Figure 29 Full DSP Control
DSP
Platform
WM8776-EV2M
Audio
Interface
H1
WM8776-EV1B
H6
H3 H5
H4
DSP
Software
Control
w Rev 1.3, March 2005
41
WM8776-EV2M
ADDITIONAL WM8776-EV1B SETUP RECOMMENDATIONS
ADC TO DAC LOOPBACK
Setting the WM8776-EV1 into loopback mode allows an analogue signal to be applied to
L/RLINE_IN1, passed through the ADC, looped into the DAC and output on the L/ROUT outputs.
+5v DGND
DVDD
+2.7V
to
+3.6V
AVDD
+2.7V
to
+5.5V
AGND
The SPDIF input is required to provide clocks for the
WM8750 audio interface.
J1 J2 J3
SPDIF_
OUT
OPT
_IN
SPDIF_
IN
SW6
H2
0
1
N OP E
SW2
H1
J15
J16
J12
J9
J25
ADCDAT &
DACDAT need to be linked
LNK4
LNK6
J11
J32
J33
J22
1
J54
H3
LNK1
J70
J30 J29
H6
J17
1
H4
J10
H5
J8 J7
Headphone Out
AIN_L/R_1
AIN_L/R_2
AIN_L/R_3
AIN_L/R_4
AIN_L/R_5
AUX_L/R
+12v -12v
Figure 30 Recommended ADC to DAC Loopback Setup
Note: Pin 2 of H1 (DIN) MUST be linked to pin 9 of H2 (DOUT). A digital input must also be applied to U1 or J5 so that the correct clocks are supplied to the WM8776. w Rev 1.3, March 2005
42
WM8776-EV2M
H1
H2
J12
LINKS AND
JUMPERS
J15 (BCLK)
J16 (LRC)
J25
J9 (MCLK)
SW2
LINK/JUMPER
STATUS
Fit jumpers (5,6)
(9,10) (13,14)
Fit jumpers (1,2)
(5,6) (13,14)
OPEN
SHORT
SHORT
OPEN
SHORT
DAC clocks
ADC clocks
DESCRIPTION
DAC Slave mode
Link BCLK (DAC BCLK to ADC)
Link LRC (DAC LRC to ADC)
ADC Slave mode
Link MCLK ((DAC MCLK to ADC)
1 2 3 4 5 6 DATA FORMAT
1 0 0 1 0 0 I2S Compatible
DVDD Supply for S/W and mode control LNK6
J11
J32, J33, J22, J17
J29
J30
H1 and H2
Pins 1 and 2
SHORT
OFF
OPEN
SHORT
SHORT
Short H1/2 to H2/9
3-wire (SPI) Control Mode
OUT Signals are AC coupled
AINR input gain set to 0.5
AINL input gain set to 0.5
Link DOUT to DIN
Table 14 Loopback Setup Jumper Settings (Slave Mode)
SOFTWARE SETUP
Press the ‘WM8776 Reset’ button. This ensures device is default.
Press the ‘Reset Software Panel Settings’ button. This ensures panel buttons are set to default.
Open the Power Down and General Audio Interface Control panel and set the HPPD bit
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WM8776-EV2M
EVALUATION SUPPORT
The aim of this evaluation kit is to help you to become familiar with the functionality and performance of the WM8776 CODEC.
If you require more information or require technical support please contact Wolfson
Microelectronics Applications group through the following channels:
Email: [email protected]
Telephone Apps: (+44) 131 272 7070
Fax:
Mail:
(+44) 131 272 7001
Applications Department at address on last page. or contact your local Wolfson representative.
Additional information may be made available from time to time on our web site at http://www.wolfsonmicro.com
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WM8776-EV2M
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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Key Features
- High performance stereo audio CODEC
- Surround sound processing applications
- Easy to use evaluation platform
- Optimum performance in device measurement
- Excellent audio quality
