a Microprocessor Supervisory Circuits ADM691A/ADM693A/ADM800L/M

a Microprocessor Supervisory Circuits ADM691A/ADM693A/ADM800L/M

a

FEATURES

Low Power Consumption:

Precision Voltage Monitor

62% Tolerance on ADM800L/M

Reset Time Delay—200 ms, or Adjustable

1

mA Standby Current

Automatic Battery Backup Power Switching

Fast Onboard Gating of Chip Enable Signals

Also Available in TSSOP Package (ADM691A)

APPLICATIONS

Microprocessor Systems

Computers

Controllers

Intelligent Instruments

Automotive Systems

Critical

mP Power Monitoring

GENERAL DESCRIPTION

The ADM691A/ADM693A/ADM800L/ADM800M family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include

µ

P reset, backup-battery switchover, watchdog timer, CMOS RAM write protection, and power-failure warning. The family of products provides an upgrade for the MAX691A/93A/800M family of products.

All parts are available in 16-pin DIP and SO packages. The

ADM691A is also available in a space-saving TSSOP package.

The following functionality is provided:

1. Power-on reset output during power-up, power-down and brownout conditions. The circuitry remains operational with

V

CC

as low as 1 V.

2. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic.

3. A reset pulse if the optional watchdog timer has not been toggled within a specified time.

4. A 1.25 V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V.

Microprocessor

Supervisory Circuits

ADM691A/ADM693A/ADM800L/M

FUNCTIONAL BLOCK DIAGRAM

BATT ON

4.65V

1

LOW LINE

V

CC

V

OUT

V

BATT

CHIP ENABLE

OUTPUT

CONTROL

CE

IN

CE

OUT

OSC IN

OSC SEL

RESET &

WATCHDOG

TIMEBASE

RESET &

GENERATOR

RESET

RESET

WATCHDOG

OUTPUT ( WDO )

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

WATCHDOG

TRANSITION DETECTOR

WATCHDOG

TIMER

1.25V

ADM691A/ADM693A

ADM800L/ADM800M

1

VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)

POWER FAIL

OUTPUT ( PFO )

INPUT

POWER

7805

+5V

R1

R2

BATTERY

NC

V

CC

V

BATT

PFI

GND

BAT

ON

ADM691A

ADM693A

ADM800L

ADM800M

V

OUT

CE

OUT

CE

IN

WDI

OSC IN

PFO

OSC SEL

RESET

LOW LINE

WDO

0.1µF

V

CC

CMOS

RAM

ADDRESS

DECODE

A0–A15

µP

POWER

I/O LINE

NMI

µP

RESET

SYSTEM

STATUS

INDICATORS

Figure 1. Typical Application

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

World Wide Web Site: http://www.analog.com

© Analog Devices, Inc., 1996

ADM691A/ADM693A/ADM800L/M–SPECIFICATIONS

(V

CC

= 4.75 V to 5.5 V (ADM691A, ADM800L) 4.5 V to 5.5 V (ADM693A, ADM800M) V

BATT

= +2.8 V, T

A

= T

MIN

to T

MAX

unless otherwise noted)

Min Typ Max Unit Test Conditions/Comments Parameter

BATTERY BACKUP SWITCHING

V

CC

, V

BATT

Operating Voltage Range

V

OUT

Output Voltage

V

CC

to V

OUT

Output Resistance

V

OUT

in Battery Backup Mode

V

BATT

to V

OUT

Output Resistance

Supply Current (Excludes I

OUT

)

Supply Current in B. Backup (Excludes I

OUT

)

Battery Standby Current

(+ = Discharge, – = Charge)

Battery Switchover Threshold

V

CC

–V

BATT

Battery Switchover Hysteresis

BATT ON Output Voltage Low

BATT ON Output Short Circuit Current

0

V

CC

– 0.05

V

CC

– 0.3

V

BATT

– 0.3

V

BATT

– 0.25

V

BATT

– 0.15

–0.1

–1.0

1

5.5

V

CC

– 0.02

V

CC

– 0.2

0.8

1.2

70

0.04

12

20

25

100

1

60

15

+0.02

+0.02

V

BATT

+ 0.03

V

BATT

– 0.03

60

0.1

0.7

0.4

1.5

100

µ

A

µ

A

V

V mV

V

V mA

µ

A

V

V

V

V

V

V

µ

A

µ

A

I

OUT

= 25 mA

I

OUT

= 250 mA

V

CC

= 4.5 V

V

BATT

= 4.5 V, I

OUT

= 20 mA

V

BATT

= 2.8 V, I

OUT

= 10 mA

V

BATT

= 2.0 V, I

OUT

= 5 mA

V

BATT

= 4.5 V

V

BATT

= 2.8 V

V

BATT

= 2.0 V

V

CC

> (V

BATT

– 1 V)

V

CC

< (V

BATT

– 1.2 V), V

BATT

= 2.8 V

5.5 V > V

CC

(V

BATT

> V

BATT

+0.2 V) < V

+ 0.2 V

CC

, T

A

= +25

°

C

(V

BATT

+0.2 V) < V

CC

Power Up

Power Down

I

SINK

= 3.2 mA

I

SINK

= 25 mA

Sink Current

Source Current

RESET AND WATCHDOG TIMER

Reset Voltage Threshold

ADM691A, ADM800L

ADM693A, ADM800M

ADM800L, V

CC

Falling

ADM800M, V

CC

Falling

Reset Threshold Hysteresis

V

CC

to RESET Delay

LOW LINE to RESET Delay

Reset Timeout Period Internal Oscillator

Reset Timeout Period External Clock

Watchdog Timeout Period, Internal Oscillator

Watchdog Timeout Period, External Clock

Minimum WDI Input Pulse Width

RESET Output Voltage

RESET Output Short Circuit Current

RESET Output Voltage Low

LOW LINE Output Voltage

LOW LINE Short Circuit Source Current

WDO Output Voltage

4.5

4.25

4.55

4.3

140

1.0

70

100

3.5

0.1

3.5

1

3.5

4.65

4.40

15

80

800

200

2048

1.6

100

4096

1024

0.004

0.1

7

0.4

15

3

4.75

4.50

4.70

4.45

280

2.25

140

0.3

0.4

20

0.4

100

0.4

10

V

V

V

V mV

µ s ns ms

T

A

T

A

= +25

°

C

= +25

°

C

Power Down

Power Up

Cycles Power Up s ms

Long Period

Short Period

Cycles Long Period

V

V

V

µ

A

V

V

Cycles Short Period ns

V

V

IL

= 0.4, V

IH

= 0.75

×

V

I

SINK

= 50

µ

A, V

CC

CC

= 1 V, V

BATT

= 0 V

V

V

I

SINK

= 3.2 mA, V

I

SOURCE

CC

= 1.6 mA, V

= 4.25 V

CC

= 5 V mA

I

SINK

= 3.2 mA

I

I

SINK

= 3.2 mA, V

CC

SOURCE

= 1

µ

A, V

CC

= 4.25 V

= 5 V

I

I

SINK

= 3.2 mA, V

SOURCE

CC

= 500

µ

A, V

= 4.25 V

CC

= 5 V mA WDO Short Circuit Source Current

WDI Input Threshold

Logic Low

Logic High

WDI Input Current

0.75

×

V

CC

–50 –10

20

0.8

50

V

V

µ

A

µ

A

WDI = 0 V

WDI = V

OUT

POWER FAIL DETECTOR

PFI Input Threshold ADM69xA

PFI Input Threshold ADM800L/M

PFI Input Current

PFO Output Voltage

PFO Short Circuit Source Current

PFI to PFO Delay

1.2

1.225

3.5

1

1.25

1.25

±

0.01

15

25

60

1.3

1.275

±

25

0.4

100

V

V nA

V

µ

A

µ s

µ s

V

CC

= 5 V

V

CC

= 5 V

I

I

SINK

= 3.2 mA

SOURCE

= 1

µ

A

V

IN

= –20 mV

V

IN

= 20 mV

REV. 0

–2–

Parameter

CHIP ENABLE GATING

CE

IN

Leakage Current

CE

IN

to CE

OUT

Resistance

CE

I N

to CE

OUT

Propagation Delay

CE

OUT

Short-Circuit Current

CE

OUT

Output Voltage

RESET to CE

OUT

Propagation Delay

OSCILLATOR

OSC IN Input Current

OSC In Input Pullup Current

OSC SEL Input Pullup Current

OSC IN Frequency Range

OSC IN Threshold Voltage

OSC IN Frequency with Ext Capacitor

NOTES

1

Either V

CC

or V

BATT

can be 0 V if the other > +2.0 V.

Specifications subject to change without notice.

Min

0.1

3.5

2.7

V

OUT

– 0.4

Typ

±

0.005

40

6

0.75

12

0.1

10

10

500

V

OUT

– 0.6

3.65

100

±

5

100

100

2.00

Max

±

1

150

10

2.0

ADM691A/ADM693A/ADM800L/M

Units Test Conditions/Comments

µ

A

µ

A

µ

A kHz

V

V kHz

µ

A

Ω ns mA

V

V

µ s

Disable Mode

Enable Mode

R

IN

= 50

, C

LOAD

= 50 pF

Disable Mode, CE

V

CC

= 5 V, I

OUT

OUT

= 0 V

= –100

µ

A

V

CC

= 0 V, V

BATT

= 2.8 V, I

OUT

= 1

µ

A

Power Down

OSC SEL = 0 V

OSC SEL = V

OUT

or Floating

OSC SEL = 0 V

OSC SEL = 0 V

V

IH

V

IL

OSC SEL = 0 V, C

OSC

= 47 pF

ABSOLUTE MAXIMUM RATINGS*

(T

A

= 25

°

C unless otherwise noted)

V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

V

BATT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to V

OUT

+ 0.5 V

Input Current

V

CC

(Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mA

V

CC

(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA

V

BATT

(Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA

V

BATT

(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

GND, BATT ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . 842 mW

θ

ϑ

A

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135

°

C/W

Power Dissipation, R-16 Narrow SOIC . . . . . . . . . . . 700 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 110

°

W

Power Dissipation, R-16 Wide SOIC . . . . . . . . . . . . . 762 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110

°

C/W

Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . 500 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158

°

C/W

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40

°

C to +85

°

C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300

°

C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215

°

C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220

°

C

Storage Temperature Range . . . . . . . . . . . . –65

°

C to +150

°

C

*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability.

Model

ADM691AAN

ADM691AARN

ADM691AARW

ADM691AARU

ADM693AAN

ADM693AARN

ADM693AARW

ADM800LAN

ADM800LARN

ADM800LARW

ADM800MAN

ADM800MARN

ADM800MARW

Part No.

Power On

Reset Time

Low V

CC

Threshold

ADM691A

ADM693A

ADM800L

200 ms or Adj.

4.65 V

±

3%

200 ms or Adj.

4.4 V

±

3%

ADM800M 200 ms or Adj.

4.4 V

±

2%

200 ms or Adj.

4.65 V

±

2%

Table I. Product Selection Table

Watchdog

Timeout

Battery Backup

Switching

100 ms, 1.6 s, Adj.

Yes

100 ms, 1.6 s, Adj.

Yes

100 ms, 1.6 s, Adj.

Yes

100 ms, 1.6 s, Adj.

Yes

ORDERING GUIDE

Temperature

Range

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

Base Drive

Ext PNP

Yes

Yes

Yes

Yes

Chip Enable

Signals

Yes

Yes

Yes

Yes

Package

Option

N-16

R-16N

R-16W

RU-16

N-16

R-16N

R-16W

N-16

R-16N

R-16W

N-16

R-16N

R-16W

REV. 0

–3–

3

4

5

Pin Mnemonic

1 V

BATT

2

6

7

8

9

ADM691A/ADM693A/ADM800L/M

10

11

12

13

14

15

16

V

OUT

V

CC

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

PFI

PFO

WDI

CE

OUT

CE

IN

WDO

RESET

RESET

PIN DESCRIPTIONS

Function

Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is not used.

Output Voltage, V

CC

or V

BATT

is internally switched to V

OUT

depending on which is at the highest potential. When V

CC

is higher than V

BATT

and is also higher than the reset threshold, V

CC

is switched to V

OUT

.

When V

CC

is lower than V

BATT

and below the reset threshold, V

BATT

is switched to V

OUT

. Connect V

OUT

to

V

CC

if a backup battery is not being used.

Power Supply Input; +5 V.

0 V. Ground reference for all signals.

Logic Output. BATT ON goes high when V

OUT

is internally switched to the V

BATT

input. It goes low when

V

OUT

is internally switched to V

CC

. The output may also be used to drive the base (via a resistor) of an external PNP transistor to increase the output current above the 250 mA rating of V

OUT

.

Logic Output. LOW LINE goes low when V

CC

falls below the reset threshold. It returns high as soon as

V

CC

rises above the reset threshold.

Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period. (See Table II and Figure 4.)

Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 10

µ

A internal pullup.

Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than

1.25 V, PFO goes low. Connect PFI to GND or V

OUT

when not used.

Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than

1.25 V.

Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the

WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.

Output. CE

OUT

goes low only when CE

IN

is low and V

CC

is above the reset threshold. If CE

IN

is low when reset is asserted, CE

OUT

will remain low for 15

µ s or until CE

IN

goes high, whichever occurs first.

Chip Enable Input. The input to the CE gating circuit. Connect to GND or V

OUT

if not used.

Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI is unconnected.

Logic Output. RESET goes low if V

CC

falls below the Reset Threshold. It remains low for 200 ms typ after

V

CC

goes above the reset threshold.

Logic Output. RESET is an open-drain output. It is the inverse of RESET.

PIN CONFIGURATIONS

V

BATT

V

OUT

V

CC

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

1

2

16 RESET

15

RESET

3

4

5

6

7

ADM691A

ADM693A

ADM800L

ADM800M

14

13

12

TOP VIEW

(Not to Scale)

11

10

WDO

CE

IN

CE

OUT

WDI

PFO

8

9 PFI

–4–

REV. 0

Typical Performance Curves– ADM691A/ADM693A/ADM800L/M

1.2

70

60

50

40

100

90

80

30

20

–50 –25 0 25 50

TEMPERATURE –

°

C

75 100 125

Figure 2. I

CC

vs. Temperature: Normal Operation

1.1

1.0

0.9

0.8

0.7

0.6

–50 –30 –10 10 30

TEMPERATURE –

°

C

50 70 90

Figure 5. V

CC

to V

OUT

ON-Resistance vs. Temperature

60

55

50

45

40

35

30

–50 –30 –10 10 30

TEMPERATURE –

°

C

50 70 90

Figure 3. I

BATT

vs. Temperature: Battery Backup Mode

80

70

60

50

40

30

20

–50 –25 0 25 50

TEMPERATURE –

°

C

75 100 125

Figure 4. Chip Enable ON-Resistance vs. Temperature

60

50

80

70

40

30

20

10

0

40

R

OUT

= 0.67

60 80

I

OUT

– mA

100 120

Figure 6. V

CC

to V

OUT

Voltage Drop vs. Current

40

30

70

60

50

20

10

0

4 6

R

OUT

= 7

8 10

I

OUT

– mA

Figure 7. V

BATT

to V

OUT

Voltage Drop vs. Current

REV. 0

–5–

ADM691A/ADM693A/ADM800L/M

4

3

6

5

10

9

8

7

2

1

0

0

V

BATT

= 2.8V

0.5

1.0

1.5

2.0

2.5

V

CC

– V

3.0

3.5

4.0

4.5

5.0

Figure 8. Battery Current vs. Input Supply Voltage

100

LONG WATCHDOG TIMEOUT PERIOD

10

1

RESET ACTIVE

TIMEOUT PERIOD = >

SHORT WATCHDOG

TIMEOUT PERIOD

0.1

10 100

C

OSC

– pF

1k

Figure 9. Watchdog and Reset Timeout Period vs.

OSC IN Capacitor

6.0

5.5

5.0

4.5

7.0

6.5

4.0

–50 –25 0 25 50

TEMPERATURE –

°

C

75 100 125

Figure 10. Chip Enable Propagation Delay vs.

Temperature

10

8

6

4

16

14

12

2

0

0 50 100 150 200

LOAD CAPACITANCE – pF

250 300

Figure 11. Chip Enable Propagation Delay vs.

Load Capacitance

230

220

210

200

190

180

170

–50 –30 –10 10 30

TEMPERATURE –

°

C

50 70 90

Figure 12. Reset Timeout Relay vs. Temperature

1200

1000

800

600

400

200

0

–50

V

CC

= 5V, V

BATT

= 2.8V

SOURCING CURRENT

V

CC

= 0V, V

BATT

= 2.8V

SINKING CURRENT

–20 10 40 70

TEMPERATURE –

°

C

100 130

Figure 13. RESET Output Resistance vs. Temperature

–6–

REV. 0

100

90

ADM691A/ADM693A/ADM800L/M

100

90

10

0%

1V 400ms

Figure 14. RESET Output Voltage vs. Supply

10

0%

1V 10µs

Figure 15. RESET Response Time

POWER FAIL RESET OUTPUT

RESET is an active low output that provides a reset signal to the

Microprocessor whenever V

CC

is at an invalid level. When V

CC falls below the reset threshold, the RESET output is forced low. The reset voltage threshold is 4.65 V (ADM691A/

ADM800L) or 4.4 V (ADM693A/ADM800M).

On power-up RESET will remain low for 200 milliseconds after

V

CC

rises above the appropriate reset threshold. This allows time for the power supply and microprocessor to stabilize. On powerdown, the RESET output remains low with V

CC

as low as 1 V.

This ensures that the microprocessor is held in a stable shutdown condition. If RESET is required to be low for voltages below 1 V, this may be achieved by connecting a pull-down resistor on the RESET line. The resistor will help maintain RESET low down to V

CC

= 0 V. Note that this is only necessary if V

BATT

is below 2 V. With battery voltages

2 V RESET will function correctly with V

CC

from 0 V to +5.5 V.

This reset active time is adjustable by using an external oscillator or by connecting an external capacitor to the OSC IN pin. Refer to Table II.

The guaranteed minimum and maximum thresholds of the

ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaranteed thresholds of the ADM693A/ADM800M are 4.25 V and

4.5 V. The ADM691A/ADM800L is therefore compatible with

5 V supplies with a +10%, –5% tolerance while the ADM693A/

ADM800M is compatible with 5 V

±

10% supplies.

In addition to RESET an active high RESET output is provided.

This is the complement of RESET and is useful for processors requiring an active high RESET signal.

Watchdog Timer Reset

The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the

Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, a reset pulse is generated. The watchdog timeout period may be configured for either a fixed “short”

100 ms or a “long” 1.6 second timeout period or for an adjustable timeout period. Note that even if the short timeout period is selected, the first time out immediately following a reset is

1.6 sec. This is to allow additional time for the microprocessor to regain control following a reset.

The watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activity on WDI or by V

CC

falling below the reset threshold.

REV. 0

–7–

The normal (short) timeout period becomes effective following the first transition of WDI after reset has gone inactive. The watchdog timeout period restarts with each transition on the

WDI pin. To ensure that the watchdog timer does not time out, either a high-to-low or low-to high transition on the WDI pin must occur at or less than the minimum timeout period. If WDI remains permanently either high or low, reset pulses will be issued after each timeout period (1.6 seconds). The watchdog monitor can be deactivated by floating the Watchdog Input

(WDI). If floating, an internal resistor network biases WDI to around 1.6 V.

BATT ON

4.65V

1

LOW LINE

V

CC

V

OUT

V

BATT

CE

IN

CHIP ENABLE

OUTPUT

CONTROL

CE

OUT

OSC IN

OSC SEL

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

RESET &

WATCHDOG

TIMEBASE

RESET &

GENERATOR

WATCHDOG

TRANSITION DETECTOR

WATCHDOG

TIMER

1.25V

ADM691A/ADM693A

ADM800L/ADM800M

1

VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)

RESET

RESET

WATCHDOG

OUTPUT ( WDO )

POWER FAIL

OUTPUT ( PFO )

Figure 16. Functional Block Diagram

Watchdog Output (WDO)

The Watchdog Output WDO provides a status output that goes low if the watchdog timer “times out” and remains low until set high by the next transition on the watchdog input. WDO is also set high when V

CC

goes below the reset threshold. If WDI remains high or low indefinitely, RESET and RESET will generate 200 ms pulses every 1.6 sec.

ADM691A/ADM693A/ADM800L/M

Changing the Watchdog and Reset Timeout

The watchdog and reset timeout periods may be controlled using OSC SEL and OSC IN. Please refer to Table II. With both these inputs floating (or connected to V

OUT

) as in Figure 16, the reset timeout is fixed at 200 ms and the watchdog timeout is fixed at 1.6 sec.. If OSC IN is connected to GND as in Figure

16, the reset timeout period remains at 200 ms but a short

(100 ms) watchdog timeout period is selected (except immediately following a reset where it reverts to 1.6 sec). By connecting

OSC SEL to GND it is possible to select alternative timeout periods by either connecting a capacitor from OSC IN to GND or by overdriving OSC IN with an external clock. With an external capacitor, the watchdog timeout period is

Twd (ms) = 600 (C/47 pF) and the reset active period is

Treset (ms) = 1200 (C/47 pF)

With an external clock connected to OSC IN, the timeout periods become

Twd = 1024 (1/f

CLK

)

Treset = 2048 (1/f

CLK

)

Battery-Switchover Section

During normal operation with V

CC

higher than the reset threshold and higher than V

BATT

, V

CC

is internally switched to V

OUT via an internal PMOS transistor switch. This switch has a typical on-resistance of 0.75

and can supply up to 250 mA at the

V

OUT

terminal. V

OUT

is normally used to drive a RAM memory bank which may require instantaneous currents of greater than

250 mA. If this is the case then a bypass capacitor should be connected to V

OUT

. The capacitor will provide the peak current transients to the RAM. A capacitance value of 0.1

µ

F or greater may be used.

If the continuous output current requirement at V

OUT

exceeds

250 mA or if a lower V

CC

–V

OUT

voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can drive the base of the external transistor.

If V

CC

drops below V

BATT

and below the reset threshold, battery backup is selected. A 7

MOSFET switch connects the V

BATT input to V

OUT

. This MOSFET has very low input-to-output differential (dropout voltage) at the low current levels required for battery backup of CMOS RAM or other low power CMOS circuitry. The supply current in battery backup is typically 0.04

µ

A.

High value capacitors, either standard electrolytic or the faradsize double layer capacitors, can also be used for short-term memory backup.

If the battery-switchover section is not used, V

BATT

should be connected to GND and V

OUT should be connected to V

CC

.

OSC SEL

Low

Low

Floating

Floating

When V

CC

is below the reset threshold, the watchdog function is disabled and WDI goes high impedance as it is disconnected from its internal resistor network.

The internal oscillator is enabled when OSC SEL is high or floating. In this mode, OSC IN selects between the 1.6 second and 100 ms watchdog timeout periods.

V

CC

RESET

THRESHOLD

80µs

RESET t

RS

80µs t

RS

OSC SEL

RESET

CE

IN

CE

OUT

12µs

Figure 17. RESET and Chip Enable Timing

CLOCK

0 TO 250kHz

8

OSC SEL

7

OSC IN

ADM69_A

ADM800_

Figure 18a. External Clock Source

NC

NC

8

OSC SEL

7

OSC IN

ADM69_A

ADM800_

Figure 18b. Internal Oscillator (1.6 s Watchdog)

8

OSC SEL

7

OSC IN

ADM69_A

ADM800_

C

OSC

Figure 18c. External Capacitor

OSC IN

Table II. Reset Pulse Width and Watchdog Timeout Selections

External Clock Input

External Capacitor

Low

Floating or V

OUT

Watchdog Timeout Period

Normal Immediately After Reset

1024 clks

600 ms

×

C/47 pF

100 ms

1.6 s

4096 clks

2.4 s

×

C/47 pF

1.6 s

1.6 s

Reset Active Period

2048 clks

1200 ms

×

C/47 pF

200 ms

200 ms

–8–

REV. 0

8

OSC SEL

7

OSC IN

ADM69_A

ADM800_

ADM691A/ADM693A/ADM800L/M

INPUT

POWER

R1

POWER

FAIL

INPUT

R2

1.25V

PFO

POWER

FAIL

OUTPUT

C

OSC

Figure 18d. Internal Oscillator (100 ms Watchdog)

WDI

WDO t

2 t

3

RESET t

1 t

1 t

1 t

1

= RESET TIME.

t

2

= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.

t

3

= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.

Figure 19. Watchdog Timing

CE Gating and RAM Write Protection

All products include memory protection circuitry which ensures the integrity of data in memory by preventing write operations when V

CC

is at an invalid level. There are two additional pins,

CE

IN

and CE

OUT

, that control the Chip Enable or Write inputs of CMOS RAM. When V

CC

is present, CE

OUT

is a buffered replica of CE

IN

, with a 5 ns propagation delay. When V

CC

falls below the reset voltage threshold, an internal gate forces CE

OUT high, independent of CE

IN

.

CE

OUT

typically drives the CE, CS, or Write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write operations when V

CC

is at an invalid level. Similar protection of EEPROMs can be achieved by using the CE

OUT

to drive the Store or Write inputs of an

EEPROM, EAROM, or NOVRAM.

Power Fail Warning Comparator

An additional comparator is provided for early warning of failure in the microprocessor’s power supply. The Power Fail Input

(PFI) is compared to an internal +1.25 V reference. The Power

Fail Output (PFO) goes low when the voltage at PFI is less than

1.3 V. Typically PFI is driven by an external voltage divider that senses either the unregulated dc input to the system’s 5 V regulator or the regulated 5 V output. The voltage divider ratio can be chosen such that the voltage at PFI falls below 1.25 V several milliseconds before the +5 V power supply falls below the reset threshold. PFO is normally used to interrupt the microprocessor so that data can be stored in RAM and the shut- down procedure executed before power is lost.

Figure 20. Power Fail Comparator

Signal

V

BATT

V

OUT

V

Table III. Input and Output Status in Battery Backup Mode

CC

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

PFI

PFO

WDI

CE

CE

OUT

IN

WDO

RESET

RESET

Status

Supply Current is <1

µ

A.

V

OUT

is connected to V

BATT

via an internal

PMOS switch.

Switchover comparator monitors V

CC

for active switchover.

0 V.

Logic High. The open circuit voltage is equal to V

OUT

.

Logic Low.

OSC IN is ignored.

OSC SEL is ignored.

The Power Fail Comparator remains active in the battery-backup mode for V

CC

V

BATT

–1.2 V. With V

CC

lower than this, PFO is forced low.

The Power Fail Comparator remains active in the battery-backup mode for V

CC

V

BATT

–1.2 V. With V

CC

lower than this, PFO is forced low.

WDI is ignored.

Logic High. The open circuit voltage is equal to V

OUT

.

High Impedance.

Logic High. The open circuit voltage is equal to V

OUT

.

Logic Low.

High Impedance.

REV. 0

–9–

ADM691A/ADM693A/ADM800L/M

APPLICATIONS INFORMATION

INCREASING THE DRIVE CURRENT

If the continuous output current requirements at V

OUT

exceeds

250 mA or if a lower V

CC

–V

OUT

voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can drive the base of the external transistor via a current limiting transistor.

+5V

INPUT

POWER

PNP

TRANSISTOR

0.1µF 0.1µF

INPUT

POWER

R1

R2

1.25V

PFI

R3

(PFO)

TO

µP NMI

5V

PFO

V

H

R2+R3

= 1.25 1+ R1

R2

×

R3

V

L

= 1.25+R1

1.25

V

CC

–1.25

R2 R3

V

MID

= 1.25

R1+R2

R2

V

CC

V

BATT

BATT

ON

V

OUT

BATTERY

Figure 21. Increasing the Drive Current

Using a Rechargeable Battery for Backup

If a capacitor or a rechargeable battery is used for backup, then the charging resistor should be connected to V

OUT

since this eliminates the discharge path that would exist during power down if the resistor were connected to V

CC.

+5V

INPUT

POWER

0.1µF

I =

V

OUT

– V

BATT

R

R

RECHARGEABLE

BATTERY

V

CC

V

BATT

ADM69_A

ADM800_

V

OUT

0.1µF

Figure 22. Rechargeable Battery

Adding Hysteresis to the Power Fail Comparator

For increased noise immunity, hysteresis may be added to the power fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 23. When

PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, R3 sources current into the

PFI summing junction. This results in differing trip levels for the comparator. Resistors R1 and R2 therefore set the trip point while R3 adds hysteresis. R3 should be larger than 10 k

so that it does not cause excessive loading on the PFO output. Additional noise rejection and filtering may be achieved by adding a capacitor from PFI to GND.

0V

0V V

L

V

IN

V

M

Figure 23. Adding Hysteresis to the Power Fail Comparator

Typical Operating Circuit

A typical operating circuit is shown in Figure 24. The circuit features power supply monitoring, battery backup switching and watchdog timing.

CMOS RAM is powered from V

OUT

. When 5 V power is present, this is routed to V

OUT

. If V

CC

fails, then V

BATT

is routed to V

OUT

. V

OUT

can supply up to 250 mA from V

CC

, but if more current is required, an external PNP transistor can be added. When V

CC

is higher than V

BATT and the reset threshold,

BATT ON goes low, providing base drive for the external transistor. When V

CC

is lower than V

BATT

and the reset threshold, an internal 7

. MOSFET connects the backup battery to

V

OUT

.

Reset Output

The internal voltage detector monitors V

CC

and generates a

RESET output to hold the microprocessor’s RESET line low when V

CC

is below the reset threshold. An internal timer holds

RESET low for 200 ms after V

CC

rises above the threshold.

This prevents repeated toggling of RESET even if the 5 V power drops out and recovers with each power line cycle.

Early Power Fail Detector

The input power line is monitored via a resistive potential divider connected to the Power Fail Input (PFI). When the voltage at PFI falls below 1.25 V, the Power Fail Output (PFO) drives the processor’s NMI input low. If a Power Fail threshold of 7 V is set with resistors R1 and R2, the microprocessor will have the time when V

CC

drops below 7 V to save data into

RAM. Power supply capacitance will extend the time available.

This will allow more time for microprocessor housekeeping tasks to be completed before power is lost.

–10–

REV. 0

RAM Write Protection

The CE

OUT

line drives the Chip Select inputs of the CMOS

RAM. CE

OUT

follows CE

IN

as long as V

CC

is above the reset threshold. If V

CC

falls below the reset threshold, CE

OUT

goes high, independent of the logic level at CE

IN

. This prevents the microprocessor from writing erroneous data into RAM during power-up, power-down, brownouts and momentary power interruptions. The LOW LINE output goes low when V

CC

falls below the reset threshold.

Watchdog Timer

The microprocessor drives the WATCHDOG INPUT (WDI) with an I/O line. When OSC IN and OSC SEL are unconnected, the microprocessor must toggle the WDI pin once every

1.6 seconds to verify proper software execution. If a hardware or software failure occurs such that WDI not toggled a 200 ms

RESET pulse will be generated after 1.6 seconds. This typically restarts the microprocessor’s power-up routine. A new

RESET pulse is issued every 1.6 seconds until WDI is again strobed.

The WATCHDOG OUTPUT (WDO) goes low if the watchdog timer is not serviced within its timeout period. Once WDO goes low it remains low until a transition occurs at WDI. The watchdog timer feature can be disabled by leaving WDI unconnected. OSC IN and OSC SEL also allow other watchdog timing options.

ADM691A/ADM693A/ADM800L/M

RESET also goes low if the Watchdog Timer is enabled and

WDI remains either high or low for longer than the watchdog timeout period.

The RESET output has an internal 1.6 mA pullup, and can either connect to an open collector RESET bus or directly drive a

CMOS gate without an external pullup resistor.

INPUT POWER

+5V

R1

R2

3V

BATTERY

NC

0.1µF

V

CC

V

BATT

BATT

ON

V

OUT

CE

OUT

PFI

GND

ADM691A

ADM693A

ADM800L

ADM800M

CE

IN

WDI

OSC IN

PFO

OSC SEL

LOW LINE

RESET

WDO

0.1µF

RESET

CMOS

RAM

ADDRESS

DECODE

0.1µF

A0–A15

I/O LINE

NMI

µP

RESET

SYSTEM STATUS

INDICATORS

Figure 24. Typical Application Circuit

REV. 0

–11–

ADM691A/ADM693A/ADM800L/M

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Plastic DIP

(N-16)

0.840 (21.33)

0.745 (18.93)

16

1

PIN 1

0.210 (5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

0.100

(2.54)

BSC

9

8

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130

(3.30)

MIN

0.070 (1.77)

0.045 (1.15)

SEATING

PLANE

0.325 (8.25)

0.300 (7.62)

0.195 (4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

1

16

16-Lead TSSOP

(RU-16)

0.201 (5.10)

0.193 (4.90)

9

8

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.0256

(0.65)

BSC

0.0118 (0.30)

0.0075 (0.19)

0.0433

(1.10)

MAX

0.0079 (0.20)

0.0035 (0.090)

8

°

0

°

0.028 (0.70)

0.020 (0.50)

16

16-Lead Wide SOIC

(R-16W)

0.4133 (10.50)

0.3977 (10.00)

9

1 8

0.0118 (0.30)

0.0040 (0.10)

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

0.0098 (0.25) x 45

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

8

°

0

°

0.0500 (1.27)

0.0157 (0.40)

°

0.1574 (4.00)

0.1497 (5.80)

16

1

16-Lead Narrow SOIC

(R-16N)

0.3937 (10.00)

0.3859 (9.80)

9

8

0.2550 (6.20)

0.2284 (5.80)

0.0098 (0.25)

0.0040 (0.10)

PIN 1

0.0688 (1.75)

0.0532 (1.35)

0.0196 (0.50)

0.0099 (0.25) x 45

SEATING

PLANE

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0099 (0.25)

0.0075 (0.19)

8

°

0

°

0.0500 (1.27)

0.0160 (0.41)

°

–12–

REV. 0

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