Quectel L30 HD GPS Engine Hardware Design
Below you will find brief information for GPS Engine L30 HD. The L30 HD GPS Engine module is designed for fast acquisition and tracking, offering outstanding performance in a compact form factor. It supports Standalone and A-GPS (CGEE function) with external EEPROM for ephemeris and patch code storage.
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L30 Hardware Design
L30
Quectel GPS Engine
Hardware Design
L30_HD_V1.0
L30 Hardware Design
Document Title
Revision
Date
Status
Document Control ID
L30 Hardware Design
1.0
2011-4-7
Release
L30_HD_V1.0
General Notes
Quectel offers this information as a service to its customers, to support application and engineering efforts that use the products designed by Quectel. The information provided is based upon requirements specifically provided for customers of Quectel. Quectel has not undertaken any independent search for additional information, relevant to any information that may be in the customer’s possession. Furthermore, system validation of this product designed by Quectel within a larger electronic system remains the responsibility of the customer or the customer’s system integrator. All specifications supplied herein are subject to change.
Copyright
This document contains proprietary technical information of Quectel Co., Ltd. Copying of this document, distribution to others and communication of the contents thereof, are forbidden without permission. Offenders are liable to the payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. All specification
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Content
0 Revision History
Introduction
Product Concept
Application
Radio Frequency
Electrical, Reliability and Radio Characteristics
................................................32
Mechanics
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Manufacture
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Table Index
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Figure Index
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L30 Hardware Design
0 Revision History
Revision Date Author Description of change
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L30 Hardware Design
1
Introduction
This document defines and specifies L30 GPS module. It describes L30 hardware interface and its external application reference circuits, mechanical size and air interface.
This document can help customer quickly understand module interface specifications, electrical and mechanical characteristics. With the help of this document and other application notes, customer can use L30 module to design and set up application quickly.
1.1 Related Documents
Table 1: Related documents
SN Document name
[1] L30_EVB _UGD
[2] L30_GPS_Protocol
[3] SIRF_AGPS_AN
Remark
L30 EVB User Guide
L30 GPS Protocol Specification
1.2 Terms and Abbreviations
IC
I/O
Kbps
LNA
MSAS
CGEE
HDOP
Client Generated Extended Ephemeris
EMC Electromagnetic Compatibility
GPS Global System
GSA
GSV
ESD
GGA
GLL
Electrostatic Discharge
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GNSS DOP and Active Satellites
GNSS Satellites in View
Horizontal Dilution of Precision
Integrated Circuit
Input/Output
Kilo Bits Per Second
Low Noise Amplifier
Multi-Functional Satellite Augmentation System
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NMEA
OSP
PDOP
RMC
SBAS
SUPL
SAW
TBD
National Marine Electronics Association
One Socket Protocol
Position Dilution of Precision
Recommended Minimum Specific GNSS Data
Satellite-based Augmentation System
Secure User Plane Location
Surface Acoustic Wave
To Be Determined
TTFF Time-To-First-Fix
UART Universal Asynchronous Receiver & Transmitter
VDOP
VTG
WAAS
ZDA
Vertical Dilution of Precision
Course over Ground and Ground Speed, Horizontal Course and Horizontal
Velocity
Wide Area Augmentation System
Time & Date
Imax
Vmax
Vnorm
Maximum Load Current
Maximum Voltage Value
Normal Voltage Value
Vmin
VIHmax
Minimum Voltage Value
Maximum Input High Level Voltage Value
VIHmin Minimum Input High Level Voltage Value
VILmax
VILmin
VImax
VImin
Maximum Input Low Level Voltage Value
Minimum Input Low Level Voltage Value
Absolute Minimum Input Voltage Value
VOHmax Maximum Output High Level Voltage Value
VOHmin
VOLmax
VOLmin
Minimum Output High Level Voltage Value
Maximum Output Low Level Voltage Value
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2
Product Concept
The GPS ROM-based module L30 features fast acquisition and tracking with the latest SiRF Star IV technology. This module provides outstanding GPS performance in a compact form factor. Based on an external optional EEPROM which provides capability of storing ephemeris and downloading patch codes through UART, L30 can support Standalone and A-GPS (CGEE function). Advanced jamming suppression mechanism and innovative RF architecture, L30 provides a higher level of anti-jamming, ensuring maximum GPS performance. The module supports location, navigation and industrial applications including autonomous GPS C/A, SBAS (WAAS or EGNOS) and A-GPS.
L30, in SMD type, can be embedded in customer applications via the 21-pin pads with the compact
9mm * 9 mm * 1.6mm form factor. It provides all hardware interfaces between the module and host board. z The multiplexed communication interface: UART/SPI/I2C interface. z The Dead Reckoning I2C interface up to 400Kbps can be used to connect with an external
EEPROM to save Ephemeris data for CGEE function and to store patch codes. z The antenna interface supports passive or active antenna.
The module is RoHS compliant to EU regulation.
2.1 Key Features
Table 3: Module key features
Quectel
(passive antenna)
Receiver Type
Sensitivity z Tracking 36 mA @ -130dBm z Hot Start -159 dBm z
Tracking -160 dBm z Navigation -159 dBm
Sensitivity
（ with external
LNA ） z Cold Start (Autonomous) -148 dBm z Reacquisition -160 dBm z Hot Start -160 dBm z Tracking -163 dBm z Navigation -160 dBm
Time-To-First-Fix z Cold Start (Autonomous) <35s
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z Warm Start (Autonomous) <35s z Warm Start (With CGEE) 10s typ. z Hot Start (Autonomous) <1s
Horizontal Position Accuracy z <2.5 m CEP
Max Update Rate z
1Hz
Accuracy of 1PPS Signal z Typical accuracy 61 ns z Time pulse 200ms
Velocity Accuracy
Acceleration Accuracy
Dynamic Performance
Dead Reckoning I2C
Interface
Communication interface z Without aid 0.01 m/s z Without aid 0.1 m/s² z Maximum altitude <18288m z Maximum velocity 514m/s Maximum z Acceleration 4 G z Open drain output z MEMS support (TBD devices) z Standard I2C bus maximum data rate 400kbps z Minimum data rate 100kbps z Support multiplexed SPI/I2C/UART interface z the output is CMOS 1.8V compatible and the input is 3.6V tolerant
Temperature range
Physical Characteristics z Normal operation: -40°C ~ +85°C z Storage temperature: -45°C ~ +125°C
Size:
9±0.15 mm * 9±0.15 mm * 1.6±0.1mm
Weight: Approx. 0.6 g
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2.2 Functional Diagram
The block diagram of L30 is shown in the Figure 1.
RF_IN
Saw filter
Match
Network
RTC
RF Front-
End w ith
Integrated LNA
Fractional-N
Syntheszer
ROM
RAM
GPS
Engine
ARM7
Processor
Power
Management
Perpheral controller
VCC
VIO/RTC
UART/SPI/I2C
EINT0
1PPS
DR_I2C
Optional
EEPROM for CGEE
ON/OFF
RESET
WAKEUP
Figure 1: Module functional diagram
2.3 Evaluation Board
In order to help customer to develop applications with L30, Quectel offers an Evaluation Board (EVB) with appropriate power supply, RS-232 serial port, EEPROM and active antenna.
Note: For more details, please refer to the document [1]
.
Quectel protocol interface that enables customer host device to access all SiRF GPS chip products of the SiRF
Protocol Type
NMEA Input/output, ASCII, 0183, 3.01
OSP Input/output, OSP protocol
Note: Please refer to document [2] about NMEA standard protocol and SiRF private protocol.
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3
Application
L30 is equipped with a 21-pin SMT pad that connects to customer serial port. Sub-interfaces included in these pads are described in details in the following chapters: z
z Power supply
z
z
z
Electrical and mechanical characteristics of the SMT pad are specified in
Chapter 5 & Chapter 6.
3.1 Pin Assignment of the Module
GND
RESET
CFG0/SCK
CFG1/SCS
1
2
Quectel
16
15
14
13
12
11
TXD/MISO/SCL
RXD/MOSI/SDA
EINT0
WAKEUP
ON/OFF
DR_I2C_DIO
DR_I2C_CLK
GND
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3.2 Pin Description
Table 5: Pin description
Power Supply
PIN
NAME
VCC
PIN
NO.
9
VIO/RTC 8
I/O DESCRIPTION DC
I
I
Supply voltage
RTC and CMOS
I/O voltage supply
CHARACTERISTICS
Vmax= 1.89V
Vmin=1.71V
Vnorm=1.8V
Vmax=1.89V
Vmin=1.71V
Vnorm=1.8V
I
VIO/RTC
=15uA@ hibernate mode
COMMENT
Supply current will be no less than 100mA.
Power supply for RTC and
CMOS I/O.
In the full on mode make sure both VIO/RTC and
VCC simultaneously power-on.
In the hibernate mode make sure VIO/RTC power-on to keep the data lossless.
General purpose input/output
PIN PIN I/O DESCRIPTION DC
NAME NO.
WAKEUP 15 O When module
CHARACTERISTICS
VOLmin=-0.3V
VOLmax=0.4V
VOHmin=0.75*
VIO/RTC
COMMENT
The wakeup pin is used as a flag of power mode. The low level indicates hibernate mode and the high level indicates the full on module.
If unused, keep this pin open.
VILmin=-0.4V
VILmax=0.45V
VIHmin=0.7* VIO/RTC
VIHmax=3.6V
The system reset is provided by the RTC monitor circuit and it is active low and must have an external pull up resistor to keep the signal stable when it works.
Pressing reset pin will result in clearing of all BBRAM ,
SRAM and RTC block. If unused, keep this pin open.
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EINT0 16 input pin Provides an interrupt on either high or low logic level or edge sensitive interrupt.
VILmax=0.45V
VIHmin=0.7*VCC
VIHmax=3.6V
If unused, pull this pin down to ground directly. It is not supported by SIRF at present.
ON_OFF 14
1PPS 7
I
O
Power control pin VILmin=-0.4V
VILmax=0.45V
VIHmin=0.7* VIO/RTC
VIHmax=3.6V
One pulse per second
VOLmin=-0.3V
VOLmax=0.4V
VOHmin=0.75*VCC
A pulse generated on the
ON_OFF pin which lasts for at least 1ms and consists of a rising edge and low level, can switch operating mode between hibernate and full-on.
1PPS output provides a pulse signal for time purpose. If unused, keep this pin open.
COMMENT
Serial Interface
PIN PIN
NAME NO.
I/O DESCRIPTION DC
CHARACTERISTICS
DR_I2C 13 Reckoning VOLmax=0.4V If unused, keep this pin open.
DIO
CLK
I2C data (SDA)
VOHmin=0.75*VCC
VILmin=-0.4V
VILmax=0.45V
Quectel
CFG0/
SCK
DR_I2C_
I2C clock(SCL) z SPI_CLK slave SPI clock input
VOHmin=0.75*VCC
If unused, keep this pin open.
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(SCK) z Configure
VILmax=0.45V
VIHmin=0.7*VCC
VIHmax=3.6V
When serial port is configured as UART, pull up to VCC via a 10k resistor.
Pin 0
CFG1/
SCS z SPI_CS_N slave SPI chip select
(SCS) active low
VILmax=0.45V
VIHmin=0.7*VCC
VIHmax=3.6V
When serial port is configured as I2C, pull down to GND via a 10k resistor.
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z Configure
Pin 1
RXD/
MOSI/
SDA
TXD/
MISO/
SCL z SSPI_DI slave SPI data input
(MOSI) z
UART_RX
UART data receive
(RXD) z I2C_DIO I2C data (SDA)
VOHmin=0.75*VCC
VILmin=-0.4V
VILmax=0.45V
VIHmin=0.7*VCC
VIHmax=3.6V z SSPI_DO slave SPI data output
(MISO) z
UART_TX
UART data
VOHmin=0.75*VCC
VILmin=-0.4V
VILmax=0.45V
VIHmin=0.7*VCC
VIHmax=3.6V
I2C clock
(SCL)
RF interface
PIN
NAME
PIN
NO. CHARACTERISTICS
COMMENT
RFIN 19 I GPS signal input Impedance of 50 Ω Refer to Chapter 4.
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3.3 Operating Modes
The table below briefly summarizes the various operating modes in the following chapters.
Table 6: Overview of operating modes
Mode
Acquisition mode
Tracking mode
Hibernate mode
Function
The module starts to search satellite, determine visible satellites and coarse carrier frequency and code phase of satellite signals. When the acquisition is done, it switches to tracking mode automatically.
The module refines acquisition’s message, as well as keeps tracking and demodulating the navigation data from the specific satellites.
The module can be switched to hibernate mode by applying a pulse which consists of a rising edge and high level that persists for at least 1ms on the
ON_OFF pin.
3.4 Power Management
There are two power supply pins in L30, VCC and VIO/RTC.
3.4.1 VCC Power
VCC pin supplies power for GPS BB domain and GPS RF domain. The power supply VCC’s current
Quectel
Table 7: Pin definition of the VCC pin
Name
VCC
3.4.2 VIO/RTC Power
The VIO/RTC pin supplies power for all RTC domain and CMOS I/O domain. So VIO/RTC should be powered all the time when the module is running. It ranges from 1.71V to 1.89V, In order to achieve a better Time To First Fix (TTFF) after VCC power down, VIO/RTC should be valid all the time. It can supply power for SRAM memory which contains all the necessary GPS information for quick start-up and a small amount of user configuration variables.
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Table 8: Pin definition of the VIO/RTC pin
Name
VIO/RTC
Pin
8
Function
Power for RTC and CMOS /IO
3.4.3 Energy Saving Mode
3.4.3.1 ATP Mode
Adaptive trickle power (ATP)
: In this mode, L30 cycles three modes internally to optimize power consumption. This three modes consist of full on mode, CPU only mode and standby mode. The full on mode lasts about 200~900ms to require new ephemeris to get a valid position, and the other two modes are partially power off or completely power off to decrease consumption. The timing sequence is shown in following figure. This mode is configurable with SiRF binary protocol message ID151.
The following diagram is a default configuration and it is tested in the strong signal environment.
When the signal becomes weak, it will not comply with the following rule. The weaker the signal is, the longer time the module lasts in full on mode. In the extreme condition, when there is no signal input, the mode cycles only two modes including full on and standby mode.
Power consumption
Power on
Or reset
Full power state(
3.4.3.2 PTF Mode
Full power state
(tracking)
Cpu only state
Full power
Quectel
Figure 2: ATP timing sequence
Cpu only state
Standby state time
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Push to fix (PTF)
: In this mode, L30 is configured to be waked up periodically, typically every 1800 sec (configurable range 10… 7200 sec) for updating position and collecting new ephemeris data from valid satellites. For the rest of the time, the module stays in Hibernate mode. A position request acts as a wakeup of the module, which is then able to supply a position within the hot-start time specification.This mode is configurable with SiRF binary protocol message ID167 and the following figure is the default configuration. Additionally, when the signal becomes weak, push to fix function is not valid.
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Power consumption
Power on
Or reset
Position request
Full power state( acqui ng)
Full power state (tracking)
Full power state
(tracking)
Full power state
(tracking)
30min
Hibernate state Hibernate state Hibernate state
30min
30min
Figure 3: PTF timing sequence
time
3.4.3.3 Hibernate Mode
Hibernate mode means low consumption in this mode. Some power domains are powered off such as
ARM, DSP and RF part, but the RTC domain includes all non-volatile logic, the RAM, and GPS BB logic I/O are still active. The module is waked up from Hibernate mode on the next ON_OFF (at rising edge) using all internal aided information like GPS time, Ephemeris, Last Position and so on, to carry out a fast TTFF in either Cold or Warm start mode.
3.5 Power Supply
3.5.1 Power Reference Design
Quectel same time, VCC_3.3 will charge the battery when it is active.
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Figure 4: Reference power design for L30 module
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3.5.2 Battery
In this part, the charging circuit of battery is introduced and XH414 is chosen as an example, the following circuit is the reference design.
Figure
5
: Reference charging circuit for chargeable battery
Quectel
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Figure 6: Seiko XH414 charging and discharging characteristics
3.6 Timing Sequence
The ON_OFF pin is used to wake up the module. Pull this pin up to VCC via a 10K resistor to avoid being triggered unexpectedly.
Quectel removed abruptly, an externally RESET is suggested. Additional, make sure external RESET pin pull full on mode and the WAKEUP will turn to high level. Next toggling of the ON/OFF can return to the hibernate mode. The state conversion is shown in the following figure.
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VCC
VIO/RTC
ON/OFF
400us
400ms
WAKEUP
T>0
(Hibernate)
>1s
>1ms
(FULL ON)
>1ms
35ms
400us
(Hibernate)
UART
Invalid
Valid
Invalid
Figure 7: Turn on timing sequence of module
NOTE:
If the “ON_OFF” pin is controlled by host controller, a 1K
Ω
resistor should be inserted between
the GPIO of the controller and “ON_OFF” pin.
Figure 8: State conversion of module
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3.7 Communication Interface
Communicate interface which includes UART interface/ I2C interface/ SPI interface is used to output
NMEA messages or to communicate with the customer device via the OSP protocol. All these interfaces are multiplexed on a share set of pins. The interface selection is not intended o be changed dynamically but only at boot time.
Table 9: Communicate interface multiplexed function pin
Pin name
CFG0/SCK
Pin NO.
3
UART
Pull up
Communicate interface
Slave SPI
slave SPI clock input (SCK)
I2C
Open select (SCS) active low
RXD/MOSI/SDA 6 Data receive slave SPI data input
(MOSI)
I2C data (SDA)
Data slave SPI data I2C clock (SCL) TXD/MISO/SCL 5
3.7.1 UART Interface
message ID 134. transmit output (MISO)
Quectel
L30 offers multiplexed pins which can be configured as one UART interface and CFG0/SCK should be pulled up to VCC via a 10K resistor. The module is designed as a DCE (Data Communication
Equipment).
Serial port TXD/MISO/SCL is connected to UART RX of customer device. Serial port
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z The UART interface can be used to output NMEA and input & output OSP messages. z z
The default output NMEA types are
RMC, GGA, GSA, and GSV (after successful positioning).
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Note: It is strongly recommended that the UART interface is used to output NMEA message to serial port of host processor.
The UART interface does not support the RS-232 level. It supports only the TTL/CMOS level. If the module UART interface is connected to the UART interface of a computer, it is necessary to insert a level shift circuit between the module and the computer. Please refer to the following figure.
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Figure 10: RS-232 level shift circuit
3.7.2 I2C Interface
resistor R1. The default mode is master mode. It is important that the customer must pull up these two z z
Quectel pins via 2K resistor for the OC/OD interface. Otherwise, there is no signal output. The reference design is described in Figure 12. z The default I2C master address: 0x60. z The default I2C slave address: 0x62.
The following figure is the I2C timing sequence.
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Figure 11: I2C timing sequence
The following circuit is an example of connection.
Quectel
Figure 12:
I2C design for L30 module
Note: The reference code of I2C will be released in the future, L30 does not support I2C at present.
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3.7.3 SPI Interface
L30 provides SPI interface and is designed as a slave mode. The reference design is shown in Figure
14.
This SPI interface has the following features:
z
An interrupt is provided when the transmit FIFO and output serial register (SR) are both empty. z The transmitter and receiver have individual software-defined 2-byte idle patterns of 0xa7 0xb4. z SPI detects synchronization errors and is reset by software. z Supports both SPI and Microwire formats. z Supports a maximum clock of 6.8MHz. z
Clock polarity: default SPI mode 1 (CPOL=0; CPHA=1). z The output is CMOS 1.8V compatible and the input is 3.6V tolerant.
The following diagram is the timing sequence of SPI.
Quectel
Figure 13: Timing sequence of SPI
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Note: The reference code of SPI will be released in the future, L30 does not support SPI at present.
mode.
3.8
Assisted GPS
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L30 supports one kind of A-GPS called Client Generated Extended Ephemeris (CGEE) which ensures fast TTFF for 3 days .The CGEE data is generated internally from satellite ephemeris as a background task, and then L30 collects ephemeris from as many satellites as possible before entering Hibernate
The CGEE feature requires that VIO/RTC power supply is kept active all the time and an external
1Mbit EEPROM connected to DR_I2C bus for CGEE data storage. The recommended EEPROM is in the following table and it is verified.
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Table 10: Recommended EEPROM
Manufacturer Part Number
ST M24M01
Seiko Instruments Inc. S-24CM01C
Atmel AT24C1024B
Note: The part number which we recommend is a series part number, please get more details from the datasheet such as operation voltage and package.
Table 11: Pin definition of the DR_I2C interfaces
Interface
I2C Interface
Name
DR_I2C_
Dead Reckoning DIO
DR_I2C_
CLK
Pin
13
12
Function
I2C data (SDA)
I2C clock (SCL)
The DR_I2C_DIO and DR_I2C_CLK pins are open-drain output and pulled up to VDD which depends on the EEPROM’s operation voltage externally by 2K resistors to meet requirement of maximum data rate up to 400Kbs. The following circuit is the reference design between L30 and
EEPROM.
Quectel
Figure 15: Reference design for CGEE function
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4
Radio Frequency
L30 receives L1 band signal from GPS satellites at a nominal frequency of 1575.42MHz. The RF signal is connected to the RFIN pin. The input impedance of RFIN is 50 Ω .
4.1 Antenna
L30 can be connected to passive or active antenna.
Table 12: Antenna specification for L30 module
Antenna type
Passive antenna
Active antenna
Specification
Center frequency: 1575.42 MHz
Band Width: >20 MHz
Gain: >0 dB
Polarization: RHCP or Linear
Center frequency: 1575.42 MHz
Band Width: >5 MHz
Minimum gain: 15-20dB (compensate signal loss in RF cable)
Maximum noise figure: 1.5dB
Maximum gain: 50dB
4.2.1 Passive Antenna
Polarization: RHCP or Linear
Quectel
Connecting a passive antenna does not require a DC bias voltage and the antenna can be connected to
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Figure 16: Reference design for passive antenna
4.2.2 Active Antenna
Active antenna could be connected to RFIN directly. If an active antenna is connected to RFIN, the integrated low-noise amplifier of the antenna must be powered by a external correct supply voltage.
Generally, the supply voltage is fed to the antenna through the coaxial RF cable. An active antenna’s loading current is between 5mA to 20mA. The inductor outside of the module prevents the RF signal from leaking into the VCC_ANT pin and routes the bias supply to the active antenna. Please refer to the reference circuit shown in Figure 17.
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Figure 17: Reference design for active antenna with external power
Note: The rated power of resistor R3 should be chosen no less than 1 watt in case active antenna is shorted unexpectedly.
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4.3 External LNA
If a passive antenna is adopted in customer’s application, an LNA could be inserted between the antenna and pin RFIN of L30 to improve the general sensitivity by 2~3dB. A reference schematic diagram based on the LNA BGA715L7 manufactured by INFINEON is given as Figure 18. Here, the gain of LNA is 20 dB, noise figure is 0.75 dB, current consumption is 3.3 mA, and range of power supply is 1.5 V to 3.3 V. Generally, the customer can get a good effective performance by using the default value marked in the reference design. Note that the interelectrode capacitance of TVS1 should be less than 0.5pF.
Quectel
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5
Electrical, Reliability and Radio Characteristics
5.1 Absolute Maximum Ratings
Absolute maximum rating for power supply and voltage on digital pins of the module are listed in the following table.
Table 13: Absolute maximum ratings
Parameter
Input voltage at digital pins
Min Max Unit
Power supply voltage （ VCC ） V
Backup battery voltage (VIO/RTC) -0.3 2 V
-0.5 3.6 V
Input power at RFIN (Prfin)
Storage temperature
－
10 dBm
-45 125 °C
Note: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. The product is not protected against over voltage or reversed voltage.
If necessary, voltage spikes exceeding the power supply voltage specification, given in table above, must be limited to values within the specified boundaries by using appropriate protection diodes.
T
OPR
VCC
I
VCC
I
VIO/RTC
Parameter Description
VIO/RTC
Supply voltage
Backup voltage supply
Backup battery current
Conditions
Voltage must stay within the min/max values, including voltage drop, ripple, and spikes.
VIO/RTC=1.8V
Min Typ Max Unit
1.71 1.8 1.89
V
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Peak supply current VCC=1.8V@-140dBm
－ －
54 mA
1.71 1.8 1.89
V
－ 15 － uA
In hibernate mode
Normal Operating temperature
Note: Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
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5.3 Current Consumption
Table 15: The module current consumption (passive antenna)
Parameter Condition
I total
Acquisition Open sky @-130dBm
Min Typ
- 40
Max
-
Unit
mA
I total
Tracking Open sky@-130dBm - 36 - mA
Hibernate Open uA
Note: Itotal=Ivcc+Ivio/rtc
5.4 Electro-Static Discharge
L30 module is ESD sensitive device, ESD protection precautions should be emphasized. Proper ESD handing and packaging procedures must be applied throughout the processing, handing and operation of any application.
The ESD bearing capability of the module is listed in the following table. Note that the customer should add ESD components to module pins in detail application except RFIN, VCC and GND pins.
Table 16: The ESD endurance table (Temperature: 25
°C
, Humidity: 45 %)
VCC, GND
±
4KV
Air discharge
±
8K
±
8K
Confidential
L30_HD_V1.0 -33-
L30 Hardware Design
5.5 Reliability Test
Table 17: Reliability test
Test term
Thermal shock
Damp heat, cyclic
Vibration shock
Heat test
Cold test
Heat soak
Cold soak
Condition
-30°C...+80°C, 144 cycles
+55°C; >90% Rh 6 cycles for 144 hours
5~20Hz,0.96m
2
/s
3
;20~500Hz,0.96m
2
/s
3
-3dB/o ct, 1hour/axis; no function
85°C, 2 hours, Operational
-40°C, 2 hours, Operational
90°C, 72 hours, Non-Operational
-45°C, 72 hours, Non-Operational
Standard
GB/T 2423.22-2002 Test
Na
IEC 68-2-14 Na
IEC 68-2-30 Db Test
2423.13-1997 Test Fdb
IEC 68-2-36 Fdb Test
GB/T 2423.1-2001 Ab
IEC 68-2-1 Test
GB/T 2423.1-2001 Ab
IEC 68-2-1 Test
GB/T 2423.2-2001 Bb
IEC 68-2-2 Test B
GB/T 2423.1-2001 A
IEC 68-2-1 Test
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L30 Hardware Design
6
Mechanics
This chapter describes the mechanical dimensions of the module.
6.1 Mechanical Dimensions of the Module
Figure 19: L30 Top view and Side view
（
Unit:mm
）
Confidential
Figure 20: L30 Bottom view
（
Unit:mm
）
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L30 Hardware Design
6.2 Footprint of Recommendation
Figure 21: Footprint of recommendation
（
Unit:mm
）
Note
：
Keep out on the host board below the module and the keep-out area should be covered by solder mask and top silk layer for isolation between the top layer of host board and the bottom layer
Confidential
Figure 22: Top view of module
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L30 Hardware Design
6.4 Bottom View of the Module
Figure 23: Bottom view of module
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L30 Hardware Design
7
Manufacture
7.1 Assembly and Soldering
L30 is intended for SMT assembly and soldering in a Pb-free reflow process on the top side of the
PCB. It is suggested that solder paste stencil height is 130um minimum to ensure sufficient solder volume. Paste mask pad openings can be increased to ensure proper soldering and solder wetting over pads. Suggest peak reflow temperature is 235…245ºC (for SnAg3.0Cu0.5 alloy). Absolute max reflow temperature is 260ºC. To avoid damage to the module when it was repeatedly heated, it is suggested that the module should be mounted after the first panel has been reflowed. The following picture is the actual diagram which we have operated.
℃
250
217
200
Preheat
Liquids Temperature
200 ℃
Heating
40s~60s
Cooling
160
℃
150
70s~120s
100
Between 1
~
3℃/S
0
Figure 24: Ramp-soak-spike-reflow of furnace temperature
s
Confidential
7.2 Moisture Sensitivity
L30 is sensitivity to moisture absorption. To prevent L30 from permanent damage during reflow soldering, baking before reflow is required in following cases: z Humidity indicator card: At least one circular indicator is no longer blue z The seal is opened and the module is exposed to excessive humidity.
L30 should be baked for 192 hours at temperature 40
℃
+5
℃
/-0
℃
and <5% RH in low-temperature containers, or 24 hours at temperature 125
℃
±5
℃
in high-temperature containers. Care should be
L30_HD_V1.0 -38-
L30 Hardware Design
taken that plastic tray is not heat resistant. L30 should be taken out before preheating, otherwise, the tray maybe damaged by high-temperature heating.
7.3 ESD Safe
L30 module is an ESD sensitive device and should be careful to handle.
7.4 Tape and Reel
Direction of SMT
16±0.1
2±0.1(A0中线)
4±0.1
+0
.1
?1
.5
0
0.50±0.05
positon of pin 1
9.25±0.1
7±0.1
2.1±0.1
A(4:1)
Figure 25: Tape and reel specification
L30_HD_V1.0 -39-
L30 Hardware Design
Shanghai Quectel Wireless Solutions Co., Ltd.
Room 501, Building 13, No.99 TianZhou Road, Shanghai, China 200233
Tel: +86 21 54453668
Mail: [email protected]
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Key Features
- Fast acquisition and tracking
- Standalone and A-GPS support
- Compact form factor
- External EEPROM for ephemeris and patch code storage
- Multiple communication interfaces (UART, SPI, I2C)
- Dead Reckoning I2C interface for external EEPROM
- Passive or active antenna support
- RoHS compliant
Frequently Answers and Questions
What is the power consumption of the L30 HD module?
What is the sensitivity of the L30 HD module?
What are the communication interfaces supported by the L30 HD module?
What are the operating modes of the L30 HD module?
What is the size of the L30 HD module?
What is the difference between Standalone and A-GPS (CGEE function)?
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