Altera Stratix V GT Edition Transceiver Signal Integrity Development Kit Reference Manual

Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

101 Innovation Drive

San Jose, CA 95134 www.altera.com

MNL-01068-1.2

Feedback Subscribe

© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

Contents

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Stratix V GT FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

MAX II CPLD System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

FPP Configuration/MAX II Bypass DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Program Select Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Dedicated Transceiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

General-Purpose Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Embedded USB-Blaster Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Transceiver Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

Transceiver Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

XFP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

SFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–40

Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Additional Information



iv ContentsContents

Board Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Transceiver Signal Integrity Development Kit


May 2014 Altera Corporation

1. Overview

This document describes the hardware features of the Stratix

®

V GT transceiver signal integrity development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Transceiver Signal Integrity Development Kit, Stratix V GT Edition, allows you to evaluate the performance of the Stratix V GT FPGA which is optimized for high-performance and high-bandwidth applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation. f

For more information on the following topics, refer to the respective documents:

■

■

Setting up the development board and using the included software, refer to the

Transceiver Signal Integrity Development Kit, Stratix V GT Edition User Guide

.

Stratix V device family, refer to the

Stratix V Device Handbook

.

Board Component Blocks

The Stratix V GT transceiver signal integrity development board provides a hardware platform for evaluating the performance and signal integrity features of the Altera

®

Stratix V GT device. The development board features the following major component blocks:

■ Altera Stratix V GT FPGA (5SGTMC7K2F40C2) in a 1517-pin FineLine BGA package

■

■

■

■

■

■

622,000 LEs

234,720 adaptive logic modules (ALMs)

50-Mbits (Mb) embedded memory

512 18x18-bit multipliers

36 transceivers (32 channels with 12.5 Gbps and four channels with 28 Gbps)

174 LVDS transmit channels

■

■

■

28 phase locked loops (PLLs)

696 user I/Os

850-mV core voltage



1–2 Chapter 1: Overview

Board Component Blocks

■

■

■

■

■

■

FPGA configuration circuitry

■

■

MAX

®

II CPLD (EPM2210F256C3N) and flash Fast Passive Parallel (FPP) configuration

MAX II CPLD (EPM570M100C4N) for on-board USB-Blaster

TM

to use with the

Quartus

®

II Programmer

■

■

JTAG header for external USB-Blaster

■

Flash storage for two configuration images (factory and user)

On-Board clocking circuitry

625-MHz, 644.53125-MHz, 706.25-MHz, and 875-MHz programmable oscillators for the high-speed transceiver reference clocks

■

■

■

■

25/100/125/200 MHz jumper-selectable oscillator to the FPGA

50-MHz general-purpose oscillator to the FPGA

One differential SMA clock input to the FPGA

Four differential SMA clock input to the transceivers

■

■

Spread spectrum clock input

Four clock trigger outputs

Transceiver interfaces

■

■

Four 28-Gbps TX/RX channels to MMPX connectors (for Stratix V GT FPGA only)

Seven 12.5-Gbps TX/RX channels to SMA connectors

■

■

■

One 12.5-Gbps TX/RX channel to SFP+ cage

One 12.5-Gbps TX/RX channel to XFP cage

Seven 12.5-Gbps TX/RX channels to Molex backplane connectors

Seven 12.5-Gbps TX/RX channels to Amphenol backplane connectors

■

■

Seven 12.5-Gbps TX/RX channels to Tyco backplane connectors

Memory devices

■

One 1-Gbit (Gb) synchronous flash with a 16-bit data bus

Communication ports

■

■

USB type-B connector

Gigabit Ethernet port and RJ-45 jack

■

LCD header

General user I/O

■

■

■

■

Eight user LEDs

Three configuration status LEDs (factory, user, error)

Six Ethernet LEDs

One 16-character × 2-line character LCD display




Chapter 1: Overview

Board Component Blocks

■

■

■

■

■

Push button and DIP switches

■

One CPU reset push button

■

■

One configuration reset push button

Four general user push buttons

■

■

■

One 8-position user DIP switch

One 6-position MSEL control DIP switch

One 4-position frequency select and spread spectrum select DIP switch

One 4-position transceiver clock input select DIP switch

■

■

■

Two 4-position power sequence enable select DIP switches

One 4-position VCCRT_GXB/VCCA_GXB voltage select DIP switch

Heat sink and fan

■

40-mm heat sink and fan combo

■

One over-temperature warning indicator LED

Power

■

■

14-V – 20-V (laptop) DC input

One power-on LED

■

■

One on/off power slide switch

Power monitor and trim capability

■

Power sequence capability

System Monitoring

■

Temperature—FPGA die

Mechanical

■

7.5" x 10.5" board dimension

1–3



1–4 Chapter 1: Overview

Development Board Block Diagram

Development Board Block Diagram

Figure 1–1

shows the block diagram of the Stratix V GT transceiver signal integrity development board.

Figure 1–1. Stratix V GT Transceiver Signal Integrity Development Board Block Diagram

Buttons, Switches, Displays

16 Char × 2 Line LCD

LCD

8 User

LEDs

4 User

Push Buttons

8 User DIP Switch

USB

Type-B

Connector

10/100/1000 Ethernet

RJ45+

Magnetics

Marvell

88E1111

Ethernet PHY

USB-Blaster

FTDI

745BL

USB PHY

MAX II

EPM570M

CPLD

Temperature Measure

5-V Fan

Dual Temp

Sensor

TDIODES

Temperature

Power Monitor

15-bit ADCs

10-bit IDACs

ADC

12.5-Gbps Channels

7 TX/RX

Tyco

Connector

1 TX/RX

1 SFP+

7 TX/RX

7 TX/RX

1 TX/RX

Amphl/FCI

Connector

28 SMA

Connectors

XFP

7 TX/RX

Molex

Connector

28-Gbps Channels

4-ATT TX/RX

16 MMPX

Connectors

1 Gb

Flash

PGMSEL

Power

Circuitry

Pwrgood

Clock

Circuitry

MAX II

EPM2210

CPLD

3 Configuration

Status LEDs

FPP Configuration

Handling the Board

When handling the board, it is important to observe the following static discharge precaution: c

Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board.

The Stratix V GT transceiver signal integrity development board must be stored between –40º C and 100º C. The recommended operating temperature is between 0º C and 55º C.




2. Board Components

This chapter introduces all the important components on the Stratix V GT transceiver signal integrity development board.

Figure 2–1 illustrates major component locations and Table 2–1 provides a brief description of all features of the board.

1

A complete set of schematics, a physical layout database, and GERBER files for the development board reside in the Stratix V GT development kit documents directory. f

For information about powering up the board and installing the demo software, refer to the

Transceiver Signal Integrity Development Kit, Stratix V GT Edition User Guide

.

■

■

■

■

■

■

■

■

■

■

This chapter consists of the following sections:

“Board Overview”

“Featured Device: Stratix V GT FPGA” on page 2–6

“MAX II CPLD System Controller” on page 2–9

“Configuration, Status, and Setup Elements” on page 2–14

“Clock Circuitry” on page 2–21

“General User Input/Output” on page 2–28

“Components and Interfaces” on page 2–32

“Flash Memory” on page 2–36

“Power Supply” on page 2–37

“Statement of China-RoHS Compliance” on page 2–42



2–2 Chapter 2: Board Components

Board Overview

Board Overview

This section provides an overview of the Stratix V GT transceiver signal integrity development board, including an annotated board image and component descriptions.

Figure 2–1 provides an overview of the development board features.

Figure 2–1. Overview of the Stratix V GT Transceiver Signal Integrity Development Board Features

DC Power

Jack (J1)

Power

Switch

(SW1)

Reset Push Buttons (S5, S6)

Fan Connector (J12)

Fan Jumper (J26)

Fan LED (D6)

Character LCD (J30)

Amphenol Backplane Connector (J32)

Transceiver Clock Input Select DIP switch (SW6)

MSEL Selection/MAX II Bypass (S7)

User DIP Switch (SW4)

User Push

Buttons

(SW1-SW4)

User LEDs

(D8-D15)

SFP+

Module

(J51)

Clock Trigger

Outputs

(U32, U33)

External Power

Input Banana Jacks

(J6, J15, J18, J21)

Molex

Backplane

Connector

(J34)

Power Sequence

Enable/Disable

(SW7, SW3)

JTAG Header

(J93)

10/100 /1000

Ethernet

Port (J29)

Embedded

USB-Blaster

(CN1)

Clock Trigger

Outputs

(U34, U35)

XFP Module

(U25)

VCCRT_GXB/ VCCA_GXB

Voltage Select (SW2)

FPGA Clock Input Select/

Spread Spectrum Clock Select

(SW5)

MMPX

Connectors

MAX II

CPLD (U19)

Stratix V GT

FPGA (U29)

Tyco

Connector

(J33)

Transceiver Input

Reference Clocks

GXB Receive SMA

GXB Transmit SMA

Table 2–1

describes the components and lists their corresponding board references.

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 1 of 4)

Board Reference Type Description

Featured Devices

U29 FPGA

U19 CPLD

Configuration, Status, and Setup Elements

Stratix V GT FPGA (5SGTMC7K2F40C2), 1517-pin BGA.

MAX II CPLD (EPM2210F256C3N), 256-pin BGA.

S7 (pin 6-7) MAX II bypass switch

Enables or disables the MAX II CPLD in the JTAG chain. The MAX II

CPLD is disabled by default.




Chapter 2: Board Components

Board Overview

2–3


Board Reference

J28

Type

Program select jumper

Description

Toggles the program LEDs to select which FPGA image to load on power-up; 0 selects factory image and 1 selects user-defined image.

S7

SW5

SW2 (pin2-7)

SW2 (pin 1-8)

J26

D7

D8

D9

D3

D12-D17

FPP configuration/MAX II bypass DIP switch

Spread spectrum clock settings DIP switch

VCCA_GXB voltage selection jumper

VCCRT voltage selection jumper

Fan control jumper

Fan LED

Load LED

Error LED

Power LED

Ethernet LEDs

Select the configuration mode from the MAX II CPLD.

Sets the spread spectrum output clock frequency and down-spread percentages.

Selects V

CCA

voltage to the FPGA. When the jumper is set to close position, the V

CCA

voltage is 3.0 V (default). When set to open position, the V

CCA

voltage is 2.5 V.

Selects V

CCRT

voltage to the FPGA. When the jumper is set to close position, the V

CCRT

voltage is 1.0 V (default). When set to open position, the V

CCRT

voltage is 0.85 V.

Selects whether the fan is always on or the FPGA automatically controls the fan. To set it to its default setting of always on, connect jumper pin 2-3. Connect jumper pin 1-2 to set the fan in auto mode.

Indicates an over-temperature condition in the FPGA and a fan should be attached to the FPGA and running.

Illuminates during embedded USB-Blaster data transfers.

Illuminates when the FPGA configuration from flash fails.

Illuminates when 14-V power is present.

Indicates the connection speed as well as transmit or receive activity.

Clock Circuitry

Y3

Y4

Y5

Y6

SW6

Y2

X3

SW5

J70 and J71

Programmable oscillator




Feeds even-numbered REFCLKs on left side of the Stratix V GT device and trigger an output at board reference J81. The external input is available at board reference J79 and J80. The default frequency is

644.53125 MHz.

Feeds odd-numbered REFCLKs on left side of the Stratix V GT device and trigger an output at board reference J85. The external input is available at board reference J83 and J84. The default frequency is

706.25 MHz.

Feeds even-numbered REFCLKs on right side of the Stratix V GT device and trigger an output at board reference J88. The external input is available at board reference J86 and J87. The default frequency is

625 MHz.

Feeds odd-numbered REFCLKs on right side of the Stratix V GT device and trigger an output at board reference J91. The external input is available at board reference J89 and J90. The default frequency is

875 MHz.

Transceiver clock input select

DIP switch

50-MHz oscillator

25/100/125/200-MHz core clock selectable oscillator

Spread spectrum selection switch

External core clock input

Selects the SMA or oscillator as the clock input.

50.000-MHz crystal oscillator for general purpose logic.

Selects the core clock frequency. The default frequency is 100 MHz.

Select either the core or spread spectrum clock. Pin 1-2 selects S0 and

S1 while pin 3-4 selects SS0 and SS1.

SMA external input at CLK10 p/n.




Board Overview


Board Reference

J72 and J73

Type

External core clock output

Description

SMA external output at FPLL/IO4D.

Transceiver Interfaces

J36, J39, J41,

J46, J48, J53,

J55, J57, J59,

J61, J63, J65,

J67, J69

J35, J37, J38,

J40, J42, J45,

J47, J52, J54,

J56, J58, J60,

J62, J64, J66,

J68

J51

GXB transmit channel

GXB receive channel

U25

Transceiver GXB transmit channels connected to SMA.

Transceiver GXB receive channels connected to SMA.

Transceiver optical interface Transceiver receive and transmit channel connected to the SFP+ module.

Transceiver optical interface Transceiver receive and transmit channel connected to the XFP module.

Transceiver Interfaces – Backplane Connectors

J33

J34

J32

10Gbase-KR reference backplane



7 transceiver-channel pairs, right angle receptacle for Tyco backplane connector.

7 transceiver-channel pairs, right angle receptacle for Molex Impact backplane connector.

7 transceiver-channel pairs, right angle receptacle for Amphenol backplane connector.

Transceiver Interfaces – Stratix V GT

J94, J96, J98,

J100, J102, J104,

J106, J108

J95, J97, J99,

J101, J103, J105,

J107, J109

J110, J111, J112,

J113

Advanced transceiver interface Transceiver GTB receive channels connected to the MMPX connectors.

Advanced transceiver interface Transceiver GTB transmit channels connected to the MMPX

Transceiver test trace connectors.

Transceiver GTB receive and transmit channels connected to the

MMPX connectors with an eight inch test trace.

General User Input and Output

D18-D25 User LEDs

SW4 User DIP switch

8 user LEDs. Illuminates when driven low.

Octal user DIP switch. When the switch is in the open position, a logic

0 is selected.

S5

S6

S1-S4

J30

Configuration reset push button

CPU reset push button

General user push buttons

Character LCD header

The default reset for the MAX II CPLD System Controller.

The default reset for the FPGA logic.

Four user push buttons. Driven low when pressed.

A single 14-pin 0.1" pitch dual-row header which interfaces to the 16 character × 2 line LCD module.





Board Overview

2–5


Board Reference Type Description

Memory Devices

U21

U17

Flash memory

EEPROM

Communication Ports

Micron PC28F00AP30BF, 1-Gb CFI NOR flash memory.

Microchip Technology Inc. 93LC46B/SNG-ND, 64x16 EEPROM SO.

J29

J93

CN1

Gigabit Ethernet port

JTAG header

USB Type-B connector

RJ-45 connector which provides a 10/100/1000 Ethernet connection through a Marvell 88E1111 PHY and the FPGA-based Altera Triple

Speed Ethernet MAC MegaCore function in SGMII mode.

Connects an Altera USB-Blaster dongle to program the FPGA and

MAX II CPLD devices. The embedded USB-Blaster is disabled when you connect the USB-Blaster to the JTAG header.

Connects a type-B USB cable to enable the JTAG embedded

USB-Blaster to program the FPGA and MAX II CPLD devices.

Power Supply

J1

SW1

J6

J12

J9

J15

J21

J18

J3

U10 and U11

DC input jack

Power switch

S5GX_VCC (0.85 V/0.9 V) banana jack

VCCA_GXB (2.5 V/3.3 V) banana jack

VCCRT_GXB (0.85 V/1.0 V) banana jack

VCCR_GTB (1.0 V) banana jack

VCCL_GTB (1.0 V) banana jack

VCCT_GTB (1.0 V) banana jack

Ground banana jack

Power monitor devices

14-V – 20-V DC female input power jack. Accepts a 2.5-mm male center-positive barrel from 14-V DC power supply.

Switch to power on/off the board.

Banana jack for supplying external V

CC

power to the FPGA. Fuses F1 and F2 must be removed prior to supplying external power to this banana jack.


CCA

power to the FPGA. Fuse F7 must be removed prior to supplying external power to this banana jack.


CCRT_GXB



CCR_GTB



CCL_GTB



CCT_GTB


Banana jack connected to ground.

Linear Technology LTC2978, octal PMBus power supply monitor and controller.




Featured Device: Stratix V GT FPGA

Featured Device: Stratix V GT FPGA

The development board features the Stratix V GT 5SGTMC7K2F40C2 device (U29) in a 1517-pin FineLine BGA package.

f

For more information about the Stratix V device family, refer to the

Stratix V Device

Handbook

.

Table 2–2

describes the features of the Stratix V GT 5SGTMC7K2F40C2 device.

Table 2–2. Stratix V GT Device Features

ALMs

234,720

Equivalent

LEs

622,000

Registers

939,000

M20K

Blocks

2,560

MLAB

Blocks (Mb)

7.16

18-bit × 18-bit

Multipliers

512

PLLs

28

Transceiver

Channels

(12.5 Gbps)

Package Type

36

1517-pin

FineLine BGA

Table 2–3

lists the Stratix V GT component reference and manufacturing information.

Table 2–3. Stratix V GT Component Reference and Manufacturing Information

Board

Reference

Description Manufacturer

Manufacturing

Part Number

U29

FPGA, Stratix V GT F1517, 622K

LEs, lead-free

Altera Corporation 5SGTMC7K2F40C2

Manufacturer

Website

www.altera.com

I/O Resources

Table 2–4

summarizes the FPGA I/O usage by function on the Stratix V GT transceiver signal integrity development board.

Table 2–4. Stratix V GT I/O Usage Summary (Part 1 of 3)

Function I/O Type I/O Count

FPGA Transceiver Clocks

Programmable differential clock LVDS input

Programmable differential clock



External differential clock inputs

LVDS input

LVDS input

LVDS input

LVDS input

Description

4

4

4

4

Differential REFCLK input to feed the even-numbered channels on the left side of the Stratix V GT device.

Differential REFCLK input to feed the odd-numbered channels on the left side of the Stratix V GT device.

Differential REFCLK input to feed the even-numbered channels on the right side of the Stratix V GT device.

Differential REFCLK input to feed the odd-numbered channels on the right side of the Stratix V GT device.

4 pairs Differential REFCLK input for one SMA pair per clock buffer.

FPGA Global Clocks

50-MHz clock

Spread Spectrum clock

SMA differential clock input

2.5-V CMOS input

2.5-V CMOS input

LVDS input

1

2

2

Global clock input.

Differential global clock.

Differential global clock.








Temperature Monitor

Temperature sense diodes

Power Monitor Devices

LTC2978 controller

Temperature Measure

MAX1619 interface

Fan

FAN_On

FAN_LED

USB-Blaster

JTAG USB-Blaster or JTAG header

FPP Configuration

FPGA Dclk

FPGA D[15:0]

MSEL [4:0]

NCONFIG

NSTATUS

NCE

CONFIG_DONE

Flash Memory

ADDR[26:1]

DATA[15:0]

Analog

2.5-V CMOS

2.5V CMOS

2.5-V CMOS output

2.5-V CMOS output

2.5-V CMOS

2.5-V CMOS input

2.5V CMOS

2.5V CMOS

2.5V CMOS

2.5V CMOS

2.5V CMOS

2.5V CMOS

2

24

4

1

1

4

26

16

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_WAIT

FLASH_CLK

FLASH_RSTn

FLASH_ADVn

FLASH_WPn

Reset

CPU_RESETn

Switches, Buttons, LEDS

User push buttons

User DIP switches

User LEDs

1.8-V CMOS output

1.8-V CMOS input/output

1.8-V CMOS output

1.8-V CMOS output

1.8-V CMOS output

1.8-V CMOS input

1.8-V CMOS output

1.8-V CMOS output

1.8-V CMOS output

1.8-V CMOS output

2.5-V CMOS input

2.5-V CMOS input

2.5-V CMOS input

2.5-V CMOS output

1

1

1

1

1

1

1

1

1

1

1

5

1

1

16

1

4

8

8

Description

Stratix V GT internal sense diode.

Octal PMBus power supply monitor and controller.

Die and ambient temperature sense.

Fan control

Fan LED

Built-in USB-Blaster or JTAG 0.1-mm header for debugging

FPP Dclk

FPP data bus

Dedicated configuration pins





Flash address bus

Flash data bus

Flash chip enable

Flash read strobe

Flash write strobe

Flash ready or busy

Flash clock

Flash reset

Flash address valid

Flash write protect

Nios

®

II CPU reset

4 user push buttons

8 user DIP switches

8 user LEDs (green)

2–7







LCD

16 Character × 2 Line LCD

Ethernet

TXD[3:0]

TXEN

GTXCLK

RXD[3:0]

RXDV

RXCLK

MDC

MDIO

ENET_SGMII_TXP/N

ENET_SGMII_RXP/N

Transceivers

28G channels to MMPX

12.5G channels to Tyco backplane connector

12.5G channels to Amphenol backplane connector

12.5G channels to Molex backplane connector

12.5G channels to SMA

12.5G channels to a SFP+ cage

12.5G channels to XFP cage

Spares

Spare[7:0]

Device I/O Total:

5.0-V LVTTL output

2.5-V CMOS output

2.5-V CMOS output

2.5-V CMOS output

2.5-V CMOS input

2.5-V CMOS input

2.5-V CMOS input

2.5-V CMOS input

2.5-V CMOS inout

LVDS output

LVDS input

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

2.5-V CMOS

11

16

28

28

28

28

4

4

1

1

1

4

4

1

2

2

1

1

8

304

LCD

Description

Ethernet transmit RGMII data bus

Ethernet transmit enable

Ethernet transmit clock

Ethernet receive RGMII data bus

Receive data valid

Receive clock

Ethernet MII clock

Ethernet MII data

Ethernet SGMII transmit data positive/negative

Ethernet SGMII receive data positive/negative

Transceiver channel

Transceiver channel

Transceiver channel

Transceiver channel

Transceiver channel

Transceiver channel

Transceiver channel

Spare signals to the MAX II CPLD





MAX II CPLD System Controller

2–9

MAX II CPLD System Controller

■

■

■

■

■

■

The board utilizes the EPM2210F256C3N System Controller, an Altera MAX II CPLD, for the following purposes:

FPGA configuration from flash memory

Temperature monitoring

Fan control

Virtual JTAG interface for PC-based power and temperature GUI

Control registers for clocks

Control registers for remote system update

■ Register with CPLD design revision and board information (read-only)

Figure 2–2

illustrates the MAX II CPLD System Controller's functionality and external circuit connections as a block diagram.

Figure 2–2. MAX II CPLD System Controller Block Diagram

PC

Embedded

USB-Blaster

JTAG Control

SLD-HUB

S5_VCCA

Measure Results

Temperature

Measure Results

Power Monitor

Encoder

MAX1619

Controller

LTC2978

Controller

Virtual-JTAG

Decoder

Information

Register

FSD Bus

Control

Register

PFL

GPIO

FPGA

Flash

MAX II CPLD

Table 2–5

lists the I/O signals present on the MAX II CPLD System Controller. The signal names and functions are relative to the MAX II device (U19).

Table 2–5. MAX II CPLD System Controller Device Pin-Out (Part 1 of 5)

Schematic Signal

Name

50MHZ_MAXLL_CLK

ALERTn

CONF_DONE

CONFIG_D0

CONFIG_D1

MAX II CPLD

Pin Number

H5

D2

T13

T11

T10

Stratix V GT

Pin Number

—

E8

AB12

AR33

AU32

I/O

Standard

Description

2.5-V 50 MHz clock input

2.5-V Temperature monitor alert

2.5-V Configuration done

2.5-V Configuration data







Name

F_AD15

F_AD16

F_AD17

F_AD18

F_AD19

F_AD20

F_AD21

F_AD22

F_AD7

F_AD8

F_AD9

F_AD10

F_AD11

F_AD12

F_AD13

F_AD14

DCLK

ENET_RSTn

F_AD1

F_AD2

F_AD3

F_AD4

F_AD5

F_AD6

CONFIG_D2

CONFIG_D3

CONFIG_D4

CONFIG_D5

CONFIG_D6

CONFIG_D7

CONFIG_D8

CONFIG_D9

CONFIG_D10

CONFIG_D11

CONFIG_D12

CONFIG_D13

CONFIG_D14

CONFIG_D15

CONFIG_ERR


MAX II CPLD

Pin Number

B12

F15

F16

D16

J16

N13

N14

C14

R9

T8

A15

M16

M15

M14

N16

N15

L14

J15

D14

K14

A11

A12

B13

E15

D15

K5

K4

K3

L5

H4

J4

J3

K2

P12

P11

R11

R10

N12

P10

Stratix V GT

Pin Number

AF14

AD11

AC11

AF11

AE11

AE13

AE12

AJ14

—

U28

AT6

AE14

AD14

AC13

AC12

AG14

AH13

AG13

AF13

AJ13

AJ12

AH12

AG11

AK12

AK11

AN31

AM31

AL30

AK30

AJ30

AJ29

AJ28

AM29

AT32

AW32

AV32

AM32

AL31

AN32

I/O

Standard















2.5-V Configuration error

2.5-V Configuration clock

2.5-V Ethernet LED

2.5-V Flash address bus






















Description






2–11


Name

F_D7

F_D8

F_D9

F_D10

F_D11

F_D12

F_D13

F_D14

F_D15

F_OEn

F_RSTn

F_WEn

F_WPn

FACTORY_IMAGE

FAN_CTRL

FAN_LED

INIT_DONE

JTAG_TCK

JTAG_TMS

F_CLK

F_D0

F_D1

F_D2

F_D3

F_D4

F_D5

F_D6

F_AD23

F_AD24

F_AD25

F_AD26

F_ADVn

F_BSYn

F_CEn


MAX II CPLD

Pin Number

G14

T12

R8

E3

F14

E14

P15

H14

C3

R13

P3

N4

J13

H13

G13

F13

G16

G15

M13

L13

K15

K16

H16

H15

P14

R16

L15

L16

A13

B14

C13

B16

P13

J14

MAX_2_MAX_INITDONE

MAX_FPP_TDI

MAX_FPP_TDO

H2

L6

M5

Stratix V GT

Pin Number

AV13

AW11

AN9

AL8

AM8

AP6

—

D6

AR11

AR10

AT12

AU13

AU12

AU11

AT11

AW13

C6

AN33

AV34

AU34

AP9

AN6

AN11

AM11

AP12

AN12

AN10

AM10

AL12

AL11

AM13

AL13

AP7

AR7

—

—

—

I/O

Standard

Description





2.5-V Flash address valid

2.5-V Flash chip busy

2.5-V Flash chip enable

2.5-V Flash clock

2.5-V Flash data bus
















2.5-V Flash output enable

2.5-V Flash reset

2.5-V Flash write enable

2.5-V Flash write protect

2.5-V Factory image for configuration

2.5-V Fan control

2.5-V Fan LED

2.5-V FPGA initialization done.

2.5-V JTAG chain clock

2.5-V JTAG chain mode

2.5-V

Control signal between the MAX II System Controller and the MAX II embedded USB-Blaster to indicate that initialization is done.

2.5-V Fast Passive Parallel (FPP) programming data in

2.5-V FPP programming data out






Name

OVERTEMPn

PFL_STATUS

PGM0

PGM1

PGM2

PGMSEL

PM1_FAULTB00

PM1_FAULTB01

PM1_FAULTB10

PM1_FAULTB11

PM2_FAULTB00

PM2_FAULTB01

PM2_FAULTB10

PM2_FAULTB11

PM_ALERTB

PM_CNTL0

MAXLL_BEN0

MAXLL_BEN1

MAXLL_BEN2

MAXLL_BEN3

MAXLL_CLK

MAXLL_CSn

MAXLL_OEn

MAXLL_WEn

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

NCONFIG

NSTATUS

PM_CNTL1

PM_PWRGD

PM_RSTN

PM_SHARE_CLK

PR_DONE

PR_ERROR

PR_READY

PR_REQUEST


MAX II CPLD

Pin Number

D5

B1

D4

B4

C6

B3

C5

A2

T5

T4

T7

C4

R12

E4

P4

T6

B5

B6

D7

A5

C7

A4

D6

E6

E7

K13

L11

L12

R14

G4

G1

D13

K12

F5

F2

F6

F1

G3

G2

Stratix V GT

Pin Number

N12

R13

P13

L12

U13

R12

P11

N13

AL10

E7

—

AW10

AV10

AR12

—

U14

K12

K13

V12

J13

M12

AB29

AC27

AD29

AE29

AP15

AT15

W12

Y11

AA12

AA11

W11

U26

AN15

AN14

AM14

AR14

AR13

AR15

I/O

Standard

Description

2.5-V Flash bus MAX II byte enable 0




2.5-V Flash bus MAX II clock

2.5-V Flash bus MAX II chip select

2.5-V Flash bus MAX II output enable

2.5-V Flash bus MAX II write enable

2.5-V DIP - FPGA mode select 0





2.5-V FPGA configuration active LED

2.5-V FPGA configuration ready status LED

2.5-V Over-temperature indicator LED

2.5-V Parallel Flash Loader (PFL) programming status

2.5-V Flash memory PGM select indicator 0



2.5-V Toggles the PGM_LED[0:2] sequence

2.5-V Power monitor bus








2.5-V Power monitor alert

2.5-V Power monitor control bus

2.5-V Power monitor control bus

2.5-V Power monitor power

2.5-V Power monitor reset

2.5-V Power monitor clock

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request






E1

D1

F4

E2

F3

R7

N2

M4

N3

P2

M3

L4

N1

L3

B11

B10

B9

B8

A10

A9

A8

A7

D8

C8

B7

A6

T2

T15

D3

C2

RESETN

S5_RSTN

S5_SMBCLK_TEMP

S5_SMBDATA_TEMP

SCL_OSC

SCL_PM

SDA_OSC

SDA_PM

SPARE0

SPARE1

SPARE2

SPARE3

SPARE4

SPARE5

SPARE6

SPARE7

USB_MAX_D0

USB_MAX_D1

USB_MAX_D2

USB_MAX_D3

USB_MAX_D4

USB_MAX_D5

USB_MAX_D6

USB_MAX_D7

USB_MAX_PWR_ENn

USB_MAX_RDn

USB_MAX_RXFn

USB_MAX_TXEn

USB_MAX_WR

USER_IMAGE



Name

MAX II CPLD

Pin Number

PWR_GOOD

J1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

AH19

AG19

AJ18

AH18

AN19

AM19

AR19

AP19

—

AV19

B8

A8

—

L11

—

M11

Stratix V GT

Pin Number

—

I/O

Standard

Description

—

Power good signal to indicate that all voltage rails have come up to their proper levels.

2.5-V FPGA reset LED

2.5-V FPGA reset

2.5-V Temperature monitor SMB clock

2.5-V Temperature monitor SMB data

2.5-V Configuration clock oscillator

2.5-V Configuration clock power monitor

2.5-V Configuration data oscillator

2.5-V Configuration data power monitor

2.5-V Spare signals to the MAX II CPLD








2.5-V USB configuration data bus








2.5-V USB configuration power enable

2.5-V USB configuration read from FIFO

2.5-V USB configuration receive enable

2.5-V USB configuration transmit enable

2.5-V USB configuration write to FIFO

2.5-V User image for configuration

2–13




Configuration, Status, and Setup Elements

Table 2–6

lists the MAX II CPLD System Controller component reference and manufacturing information.

Table 2–6. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U19

MAX II CPLD 256FBGA -3 LF

3.3 V VCCINT

Altera Corporation EPM2210F256C3N www.altera.com

Configuration, Status, and Setup Elements

This section describes the board's configuration, status, and setup elements.

Configuration

This section describes the FPGA, flash memory, and MAX II CPLD System Controller device programming methods supported by the Stratix V GT transceiver signal integrity development board.

The Stratix V GT transceiver signal integrity development board supports three configuration methods:

■

■

■

Embedded USB-Blaster is the default method for configuring the FPGA at any time using the Quartus II Programmer in JTAG mode with the supplied USB cable.

MAX II and flash FPP download for configuring the FPGA using stored images from the flash on either power-up or pressing the reset push-button (S5).

JTAG header (J93) for initial debugging and to bring up the on-board USB-Blaster circuitry.

FPGA Programming over Embedded USB-Blaster

Programming the FPGA over embedded USB-Blaster is implemented using a type-B

USB connector (CN1), a USB 2.0 PHY device, and an Altera MAX II CPLD

EPM2210F256C3N (U19). This allows configuration of the FPGA using a USB cable that connects directly between the USB port on the board (CN1) and a USB port of a

PC running the Quartus II software. The embedded USB-Blaster in the MAX II CPLD

System Controller acts as a master to the JTAG chain.

A green USB-Blaster LED (D8) indicates the USB-Blaster activity. The embedded

USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain at the JTAG header (J93).






Figure 2–3

shows the block diagram for the embedded USB-Blaster connection.

Figure 2–3. Embedded USB-Blaster Connection

JTAG Header

2–15

USB Type-B

Connector

USB

USB 2.0 PHY

USB FIFO BUS

MAX II

CPLD

JTAG

Stratix V GT

FPGA

MAX II CPLD System Controller

The EPM570M100 MAX II CPLD (U16) is dedicated to the on-board USB-Blaster functionality. The CPLD connects to the FT245BL USB FIFO device on one side and drives the JTAG signals out the other side on the general purpose I/O (GPIO) pins. A

64x16 EEPROM connects to the CPLD device and stores the factory image for

USB–JTAG functionality.

FPGA Programming from Flash Memory

On power-up, the MAX II CPLD System Controller’s parallel flash loader (PFL) configures the FPGA from the flash memory. The system controller uses the Altera

Parallel Flash Loader (PFL) megafunction to read 16-bit data from the flash memory and converts it to FPP format. This 8-bit data is then written to the FPGA’s dedicated configuration pins during configuration.

The FPP configuration is implemented with an Altera MAX II CPLD together with the

Micron PC2800AP30BF 1-Gb CFI NOR-type flash device (U21). The CPLD shares the flash interface with the FPGA. The configuration program select (PGMSEL) jumper

(J28), selects between two Programmer Object Files (.pof) files (factory or user) stored in the flash. The configuration mode select signals, MSEL[4:0], are pulled to [00100]

FPP x16 on the board for FPP mode configuration.

There are three configuration status LEDs, CONFIG_ERR, FACTORY_IMAGE, and

USER_IMAGE

(D9, D10, D11) that indicate the status of the FPP configuration. For information on the configuration status LEDs, refer to

“Status Elements” on page 2–18 .

Table 2–7

lists the PGMSEL jumper settings.

Table 2–7. PGMSEL Jumper Settings

Jumper

Not installed (default)

Installed

PGMSEL Setting

0

1

File Selection

Factory image

User image





Figure 2–4

shows the MAX II and flash FPP configuration.

Figure 2–4. MAX II and Flash FPP Configuration

50 MHz

2.5 V

CLKBUF

Green LED (Factory Image)

Green LED (User Image)

MAX II CPLD

System Controller

CLK

DCLK nSTATUS nCONFIG

CONF_DONE

CONF_D[15:0]

CONFIG_ERR,

FACTORY_IMAGE,

USER_IMAGE LEDs

Red LED (Error Image)

PGM [2:0] PGMSEL

F_RSTn

F_AD[26:1]

F_D[15:0]

F_CLK

F_CEn

F_OEn

F_WEn

ADVn

WPn

RY/BYn

DEV_CLRn

RESETn

CFI Flash

F_AD[26:1]

F_D[15:0]

F_CLK

F_CEn

F_OEn

F_WEn

ADVn

WPn

RY/BYn

RESETn

CLKxP

DCLK nSTATUS nCONFIG

CONF_DONE

D[15:0] nCE

Stratix V GT

FPGA

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

MAX_BYPASS

FSM Bus Interface

DIP Switch

(S7) f

For more information on the flash memory map storage, refer to the

Transceiver Signal

Integrity Development Kit, Stratix V GT Edition User Guide

.

Flash Programming

Flash programming is possible through a variety of methods using the Stratix V GT device.

The first method is to use the factory design called the Board Update Portal. This design is an embedded webserver, which serves the Board Update Portal web page.

The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash over the network.

The secondary method is to use the pre-built PFL design included in the development kit. The development board implements the Altera PFL megafunction for flash programming. The PFL megafunction is a block of logic that is programmed into an

Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings.

Other methods to program the flash can be used as well, including the Nios

®

II processor.






2–17

f

For more information on the Nios II processor, refer to the Nios II Processor page of the Altera website.

FPGA Programming over External USB-Blaster

The JTAG header provides another method for configuring the FPGA (U29) using an external USB-Blaster device with the Quartus II Programmer running on a PC. The external USB-Blaster connects to the board through the JTAG header (J93). The JTAG

DIP switch (S7) allows the MAX II CPLD device to be removed from the JTAG chain so that the FPGA is the only device on the JTAG chain.

JTAG Header

The JTAG header provides another method for configuring the FPGA using an Altera

USB-Blaster dongle with the Quartus II Programmer running on a PC.

Figure 2–5

shows the schematic connections for the dedicated JTAG programming header (J93).

The program MSEL switch (S7) allows the MAX II CPLD device to be removed from the JTAG chain so that the FPGA is the only device on the JTAG chain.

Figure 2–5. JTAG Header

USB Interface

JTAG

Header

9

3

5

1

TDI

TDO

TMS

TCK

IO_TDO

IO_TCK

IO_TMS

IO_TDI

MAX_OEn

MAX CPLD

2

9

5

1

TDI

TMS

TCK

LAST_TDO

Remove jumper to exclude the MAX CPLD device from the JTAG chain.

Jumper

S5GT_TDI

S5GT_TDO

JTAG_TMS

JTAG_TCK

Stratix V GT FPGA

MAX_FPP_TDI MAX_FPP_TDO

JTAG_TCK

JTAG_TMS

MAX II and Flash FPP

Dual

Analog

Switch

LAST_TDO

3

External USB-Blaster Header

The MAX II CPLD System Controller must be in the chain to use some of the GUI interfaces. To connect the MAX II CPLD in chain, set pins 6-7 of the program MSEL switch (S7) to 1.

f

For more information on the following topics, refer to the respective documents:

■

■

Board Update Portal and PFL Design, refer to the

Transceiver Signal Integrity

Development Kit, Stratix V GT Edition User Guide

.

PFL megafunction, refer to

AN 386: Using the Parallel Flash Loader with the Quartus

II Software.





Status Elements

The development board includes board-specific status LEDs and switches for enabling and configuring various features on the board, as well as a 16 character × 2 line LCD for displaying board power and temperature measurements. This section describes these status elements.

Status LEDs

Surface mount LEDs indicate the various status of the board. A logic 0 is driven on the

I/O port to turn the LED on while a logic 1 is driven to turn the LED off.

Table 2–8

lists the LED board references, names, and functional descriptions.

Table 2–8. Board-Specific LEDs

Board

Reference

D3

LED Name

POWER

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

FAN

USB

ERROR

FACTORY

USER

TX

RX

DUPLEX

1000

100

10

—


Name

Description

FAN_LED

USB_LED

CONFIG_ERR

FACTORY_IMAGE

USER_IMAGE

ENET_LED_TX

ENET_LED_RX

ENET_LED_DUPLEX

ENET_LED_LINK1000

ENET_LED_LINK100

ENET_LED_LINK10

Blue LED. Illuminates when 5-V power is active.

Amber LED. Illuminates when an over-temperature condition occurs. This occurrence should automatically turn on the fan.

Green LED. Illuminates when the MAX II CPLD System Controller is actively configuring the FPGA using the embedded

USB-Blaster.

Red LED. Illuminates when the MAX II CPLD System Controller fails to configure the FPGA. Driven by the MAX II CPLD System

Controller.

Green LED. Illuminates when the factory image is successfully loaded into the FPGA. Driven by the MAX II CPLD System

Controller.

Green LED. Illuminates when the user image is successfully loaded into the FPGA. Driven by the MAX II CPLD System

Controller.

Green LED. Blinks to indicate Ethernet PHY transmit activity.

Driven by the Marvell 88E1111 PHY.

Green LED. Blinks to indicate Ethernet PHY receive activity.

Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet full duplex status.

Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed Driven by the Marvell 88E1111 PHY.






Table 2–9

lists the board-specific LEDs component references and manufacturing information.

Table 2–9. Board-Specific LEDs Component References and Manufacturing Information

Board Reference

D8, D10-D17

D9

D3

D7

Description

Green LEDs

Red LED

Blue LED

Amber LED

Lumex Inc.

Lumex Inc.

Lumex Inc.

Lite-On

Manufacturer

Manufacturer

Part Number

Manufacturer

Website

SML-LX1206GC-TR

SML-LX1206IC-TR www.lumex.com

www.lumex.com

SML-LX1206USBC-TR www.lumex.com

LTST-C150KYKT www.lite-on.com

Setup Elements

■

■

■

■

The development board includes several different kinds of setup elements. This section describes the following setup elements:

FPP configuration or MAX II bypass DIP switch

Program select jumper

MAX II reset push button

CPU reset push button

FPP Configuration/MAX II Bypass DIP Switch

The FPP configuration or MAX II bypass DIP switch (S7) controls the FPP configuration mode and also selects the MAX II CPLD to be in the JTAG chain.

Table 2–10 lists the switch settings and descriptions.

Table 2–10. FPP Configuration/MAX II Bypass DIP Switch Settings

Board

Reference (S7)


Name

Description

1–12

2–11

3–10

4–9

5–8

6–7

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

MAX_BYPASS

ON : Logic 0 is selected for MSEL0

OFF : Logic 1 is selected for MSEL0









ON : MAX II CPLD EPM2210 System Controller in-chain

OFF : Bypass MAX II CPLD EPM2210 System Controller

Default

ON

ON

OFF

ON

ON

ON

2–19





Table 2–11

lists the DIP switch component reference and manufacturing information.

Table 2–11. FPP Configuration/MAX II Bypass DIP Switch Component Reference and Manufacturing Information

Board Reference

S7

Description

Six-Position slide DIP switch

Manufacturer

Grayhill

Manufacturer

Part Number

97C06RT

Manufacturer Website

www.grayhill.com

Program Select Jumper

The program select jumper, PGMSEL (J28) is an input to the MAX II CPLD System

Controller. After a power-on or reset configuration, the MAX II CPLD System

Controller configures the FPGA to either factory or user image. For information on the jumper settings, refer to

“FPGA Programming from Flash Memory” on page 2–15

.

Reset Push Button

The reset push button, RESETn, is an input to the MAX II CPLD System Controller. This push button is the default logic reset for the CPLD logic.

Table 2–12 lists the MAX II reset push button component reference and manufacturing

information.

Table 2–12. MAX II Reset Push Button Component Reference and Manufacturing Information

Board Reference

S5

Description

Push Button

Manufacturer

Panasonic Corporation

Manufacturer

Part Number

EVQPAC07K

Manufacturer

Website

www.panasonic.com

CPU Reset Push Button

The CPU reset push button, CPURSTn, (S6) connects to a regular I/O pin of the FPGA and serves as a reset for the NIOS II when you load the application.

Table 2–13 lists the CPU reset configuration push button component reference and

manufacturing information.

Table 2–13. CPU Reset Configuration Push Button Component Reference and Manufacturing Information

Board Reference

S6

Description

Push Button

Manufacturer


Manufacturer

Part Number

EVQPAC07K

Manufacturer

Website

www.panasonic.com





Clock Circuitry

706.25 MHz

Clock

Buffer

Trigger

REFCLK

REFCLK

6-12.5G

Channels

Trigger

Clock

Buffer

SMA

875 MHz

2–21

Clock Circuitry

This section describes the board's dedicated and general purpose clocks.

Dedicated Transceiver Clocks

Four differential clock sources are provided from the I

2

C programmable VCO oscillators to the dedicated REFCLK input pins of transceiver blocks on both sides of the FPGA. The default frequencies for these four oscillators at startup are 625 MHz,

644.53125 MHz, 706.25 MHz, and 875 MHz. The default frequencies can be overridden and you can program a different frequency into the oscillators to support other protocols. Each oscillator supports a programmable frequency range of

10 MHz–1.4 GHz and provides a trigger output to an SMA connector for scope or other lab equipment triggering purposes.

Figure 2–6

shows the default frequencies of all external clocks going to the

Stratix V GT transceiver signal integrity development board.

Figure 2–6. Transceiver Signal Integrity Development Kit Dedicated Transceiver Clocks

SMA

Clock

Buffer

644.53125 MHz

Trigger

REFCLK

REFCLK

Stratix V GT FPGA

6-12.5G

Channels

2-12.5G

Channels

+

1-28G

Channel

REFCLK

REFCLK

REFCLK

REFCLK

6-12.5G

Channels

2-12.5G

Channels

+

1-28G

Channel

REFCLK

REFCLK

Trigger

Clock

Buffer

625 MHz

REFCLK

REFCLK

6-12.5G

Channels

2-12.5G

Channels

+

1-28G

Channel

REFCLK

REFCLK

2-12.5G

Channels

+

1-28G

Channel

REFCLK

REFCLK

Table 2–14 lists the frequency of these oscillators and the application it supports.

Table 2–14. Transceiver On-Board Oscillators

Frequency

644.53125 MHz

625 MHz

706.25 MHz

875 MHz

i/O Standard

LVDS

LVDS

LVDS

LVDS

Clock Buffer

IDT5T9306

IDT5T9306

IDT5T9306

IDT5T9306




Clock Circuitry

In addition to the four oscillators, each side has a dedicated differential REFCLK input from a pair of SMA connectors to allow an external clock source.

General-Purpose Clocks

Three general-purpose clocks are provided to the FPGA global clock inputs for general FPGA design. The clocks consist of the following components:

■

■

A 50-MHz oscillator through an ICS8304 buffer for NIOS II applications at clock input CLK2p. This clock also routes to the MAX II device for FPP configuration and to the clock inputs CLK12p and CLK16p of banks 7 and 8.

A 25-MHz crystal oscillator through an ICS557-03 spread spectrum differential clock buffer. The available frequencies and down spread percentages available from the spread spectrum buffer is shown in

Table 2–15 .

■ An external differential clock source from SMA at CLK10p/n (J70/J71).

Figure 2–7

shows the general purpose clocks going in to the Stratix V GT transceiver signal integrity development board.

Figure 2–7. Transceiver Signal Integrity Development Kit General Purpose Clocks

ICS8304

CLKBUF

MAX II CPLD

(U19)

50 MHz

3

25 MHz

XTAL

CLKIN SMA

(J70/J71)

ICS557

25/100/125/

200-MHz

Spread

Spectrum

CLKBUF

Trigger SMA

Stratix V GT

FPGA

(U29)

Table 2–15

lists the spread spectrum clock settings and frequencies.

Table 2–15. Spread Spectrum Clock Settings and Frequencies

Spread Spectrum Buffer (inputs)

Output Clock Select

SS1/S1

1

1

0

0

SS0/S0

0

1

0

1

25 MHz (default)

100 MHz

125 MHz

200 MHz

Center

Spread (%)

0.25

Down –0.5

Down –0.75

No spread





Transceiver Channels

2–23

Embedded USB-Blaster Clocks

A separate 6-MHz crystal and 24-MHz oscillator are dedicated for the embedded

USB-Blaster circuitry. The 6-MHz oscillator is to clock the FTDI FT245 USB PHY device while the 24-MHz oscillator is to clock the MAX II CPLD device. Refer to

“FPGA Programming over Embedded USB-Blaster” on page 2–14 for the embedded

USB-Blaster implementation.

Table 2–16 lists the crystal oscillators component references and manufacturing

information.

Table 2–16. Crystal Oscillator Component References and Manufacturing Information

Board

Reference

X1


ESC Inc.

Y1

Crystal oscillator, 6.0 MHz, SMD

Crystal oscillator, CMOS, 2.5 V,

24.000 MHz, SMT, ±50ppm

Epson

Manufacturer

Part Number

ECSX-60-32-5P-TR

SG-310SDF 24.0000M-

B3


www.ecsxtal.com

www.epsontoyocom.co.jp/ english/index.html

Transceiver Channels

The transceiver signal integrity development board dedicates 31 (out of 32) 12.5-Gbps transceiver channels from both the left and right sides of the device to various backplane connectors—SFP+ and XFP cages, and SMA connectors. One 12.5-Gbps channel on the 28 Gbps side of the device is a dedicated CMU clock input from the

SMA connectors. For the Stratix V GT device, the four 28-Gbps ATT channels connects to the MMPX connectors.




Transceiver Channels

Figure 2–8

shows the complete transceiver usage diagram.

Figure 2–8. Transceiver Signal Integrity Development Kit Dedicated Transceiver Channels

Tyco BP

Connector

XFP Cage

5-TX/RX

TX/RX

Molex

Connector

5-TX/RX

7-TX/RX

Channels to

28 SMA

Connectors

TX/RX

6-TX/RX

SFP+ Cage

Amphenol

Connector

TX/RX

5-TX/RX

Stratix V GT FPGA

Six 12.5 G

Channels

Two 12.5 G

Channels

+

One 28 G

Channel

2-TX/RX (12.5G)

TX/RX (28G)

Six 12.5 G

Channels

Two 12.5 G

Channels

+

One 28 G

Channel

2-TX/RX (12.5G)

TX/RX (28G)

Six 12.5 G

Channels

Six 12.5 G

Channels

Two 12.5 G

Channels

+

One 28 G

Channel

Two 12.5 G

Channels

+

One 28 G

Channel

TX/RX (28G)

TX/RX

TX/RX (28G)

2-TX/RX (12.5G)

MMPX

MMPX

MMPX

1 CMURX

Clock from SMA

MMPX

Table 2–17 lists the connection requirements for the transceiver channels.

Table 2–17. Transceiver Signal Integrity Development Kit Transceiver Channels (Part 1 of 2)

Signal Group

5-12.5-Gbps TX to Tyco backplane connector (left side of transceiver block)

5-12.5-Gbps RX to Tyco backplane connector (left side of transceiver block)

2-12.5-Gbps TX to Tyco backplane connector (right side of transceiver block)

2-12.5-Gbps RX to Tyco backplane connector (right side of transceiver block)

5-12.5-Gbps TX to Amphenol/FCI backplane connector (left side of transceiver block)

5-12.5-Gbps RX to Amphenol/FCI backplane connector (left side of transceiver block)

2-12.5-Gbps TX to Amphenol/FCI backplane connector (right side of transceiver block)

2-12.5-Gbps RX to Amphenol/FCI backplane connector (right side of transceiver block)

5-12.5-Gbps TX to Molex connector (left side of transceiver block)

5-12.5-Gbps RX to Molex connector (left side of transceiver block)

2-12.5-Gbps TX to Molex connector (right side of transceiver block)

2-12.5-Gbps RX to Molex connector (right side of transceiver block)

Note

Length match between this TX group

Length match between this RX group

Length match between this TX pair

Length match between this RX pair













Backplane Connectors

2–25

Table 2–17. Transceiver Signal Integrity Development Kit Transceiver Channels (Part 2 of 2)

Signal Group

7-12.5-Gbps TX to SMAs (left side of transceiver block)

7-12.5-Gbps RX to SMAs—can be used as CMUclk inputs (left side of transceiver block)

4-28-Gbps TX to MMPX connector (right side of transceiver block)

4-28-Gbps RX to MMPX connector (right side of transceiver block)

1-12.5-Gbps TX/RX to SFP+ cage (left side of transceiver block)

1-12.5-Gbps TX/RX to XFP cage (left side of transceiver block)

1-12.5-Gbps RX channel used as CMUclk input from SMA (right side of transceiver block)

Note





No matching between TX/RX pairs

No matching between TX/RX pairs

Match P/N of RX input

Backplane Connectors

The development board supports three different types of 10Gbase-KR reference backplanes by directly mating with the backplanes made from Tyco, Amphenol, and

Molex manufacturers.

Table 2–18 lists the Amphenol backplane connector pin assignments.

Table 2–18. Amphenol Backplane Connector Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (J32)

F6

C6

D6

C1

D5

C4

D4

E6

F5

E4

F4

C5

G5

H5

E5

D1

C2

D2

E1

F1

E2

Schematic Signal Name

GXB_TXLN_19

GXB_TXLP_19

GXB_TXLN_20

GXB_TXLP_20

GXB_TXLN_21

GXB_TXLP_21

GXB_TXLN_22

GXB_TXLP_22

GXB_TXLN_23

GXB_TXLP_23

GXB_TXRN_18

GXB_TXRP_18

GXB_TXRN_23

GXB_TXRP_23

GXBRXLN_19

GXBRXLP_19

GXBRXLN_20

GXBRXLP_20

GXBRXLN_21

GXBRXLP_21

GXBRXLN_22

I/O Standard

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

Stratix V GT Device

Pin Number

M6

C3

C4

K39

E36

C37

C36

M5

K35

K34

J37

J36

G37

G36

E37

K38

H39

H38

F39

F38

D39

Description

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive





Table 2–18. Amphenol Backplane Connector Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference (J32)

F2

G2

H2

E3

F3

C3

D3


GXBRXLP_22

GXBRXLN_23

GXBRXLP_23

GXBRXRN_18

GXBRXRP_18

GXBRXRN_23

GXBRXRP_23

I/O Standard

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML


Pin Number

D38

B39

B38

L3

L4

B1

B2

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

Description

Table 2–19 lists the Tyco backplane connector pin assignments.

Table 2–19. Tyco Backplane Connector Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (J33)

B3

C3

B6

A6

C2

B5

A5

A2

A3

A9

B9

G18

F17

G17

B2

H12

F15

G15

F18

F11

G11

H11

F14

G14

F12

G12


GXB_TXLN_0

GXB_TXLN_1

GXB_TXLN_2

GXB_TXLN_3

GXB_TXLN_4

GXB_TXLP_0

GXB_TXLP_1

GXB_TXLP_2

GXB_TXLP_3

GXB_TXLP_4

GXB_TXRN_0

GXB_TXRN_5

GXB_TXRP_0

GXB_TXRP_5

GXBRXLN_0

GXBRXLN_1

GXBRXLN_2

GXBRXLN_3

GXBRXLN_4

GXBRXLP_0

GXBRXLP_1

GXBRXLP_2

GXBRXLP_3

GXBRXLP_4

GXBRXRN_0

GXBRXRN_5

I/O Standard

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML


Pin Number

AT39

AP39

AM39

AJ37

AV38

AT38

AP38

AM38

AJ36

AV1

AJ3

AN36

AL36

AK34

AU3

AH5

AU4

AH6

AV39

AU37

AR37

AN37

AL37

AK35

AU36

AR36

Description

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB receive






Table 2–19. Tyco Backplane Connector Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference (J33)

A8

B8


GXBRXRP_0

GXBRXRP_5

I/O Standard

1.4-V PCML

1.4-V PCML


Pin Number

AV2

AJ4

GXB receive

GXB receive

Description

Table 2–20 lists the Molex backplane connector pin assignments.

Table 2–20. Molex Backplane Connector Pin Assignments, Signal Names and Functions

Board

Reference (J34)

L2

H4

M3

L4

G4

L3

K4

J3

E3

G2

F3

H2

E8

H8

H3

K2

E10

H10

D8

G8

G10

F9

J9

C9

E9

H9

B9

D10


GXB_TXLN_6

GXB_TXLN_7

GXB_TXLN_8

GXB_TXLN_9

GXB_TXLN_10

GXB_TXLP_6

GXB_TXLP_7

GXB_TXLP_8

GXB_TXLP_9

GXB_TXLP_10

GXB_TXRN_6

GXB_TXRN_11

GXB_TXRP_6

GXB_TXRP_11

GXBRXLN_6

GXBRXLN_7

GXBRXLN_8

GXBRXLN_9

GXBRXLN_10

GXBRXLP_6

GXBRXLP_7

GXBRXLP_8

GXBRXLP_9

GXBRXLP_10

GXBRXRN_6

GXBRXRN_11

GXBRXRP_6

GXBRXRP_11

I/O Standard

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML


Pin Number

AF39

AD39

AB39

AH38

AE36

AF38

AD38

AB38

AH1

AA3

AH2

AA4

AC36

AB34

AG3

Y5

AG4

Y6

AH39

AE37

AG37

AF35

AD35

AC37

AB35

AG36

AF34

AD34

Description

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB receive

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB transmit

GXB receive

GXB receive

2–27




General User Input/Output

Table 2–21 lists the backplane connector component reference and the manufacturing

information.

Table 2–21. User-Defined Push Button Component Reference and Manufacturing Information

Board

Reference

J32

J33

J34


Manufacturer

Part Number

Connector, 4-pair, 6 position, Amphenol

Xcede

Connector, 8-pair, 6-columns, receptacle,

Tyco Strada

Amphenol

Tyco Electronics

Connector, 4-pair, receptacle, Molex Impact Molex

AX400-00682

2149323-1

76160-5020

Manufacturer

Website

www.amphenol.com

www.te.com

www.molex.com

General User Input/Output

■

■

■

■

This section describes the user I/O interface to the FPGA. This section describes the following I/O elements:

User-defined push buttons

User-defined DIP switch

User-defined LEDs

Character LCD

User-Defined Push Buttons

The development board includes four user-defined push buttons that allow you to interact with the Stratix V GT device. When you press and hold down the push button, the device pin is set to logic 0; when you release the push button, the device pin is set to logic 1. There is no board-specific function for these general user push buttons.

Table 2–22 lists the user-defined push button schematic signal names and their

corresponding Stratix V GT device pin numbers.

Table 2–22. User-Defined Push Button Schematic Signal Names and Functions

Board Reference Schematic Signal Name I/O Standard Stratix V GT Device Pin Number

S1

S2

S3

S4

USER_PB0

USER_PB1

USER_PB2

USER_PB3

2.5-V

2.5-V

2.5-V

2.5-V

H29

G28

K27

J27

Table 2–23 lists the user-defined push button component reference and the


Table 2–23. User-Defined Push Button Component Reference and Manufacturing Information

Board Reference

S1–S4

Description

Push button

Manufacturer


Manufacturer

Part Number

EVQPAC07K


www.panasonic.com






2–29

User-Defined DIP Switch

Board reference SW4 is a 8-pin DIP switch. The switches are user-defined, and are provides additional FPGA input control. When the switch is in the OPEN or ON position, a logic 1 is selected. When the switch is in the CLOSED or OFF position, a logic 0 is selected. There is no board-specific function for these switches.

Table 2–24 lists the user-defined DIP switch schematic signal names and their

corresponding Stratix V GT pin numbers.

Table 2–24. User-Defined DIP Switch Schematic Signal Names and Functions

Board Reference

(SW4)

Schematic Signal Name I/O Standard Stratix V GT Device Pin Number

1

2

3

4

5

6

7

8

S5_UNLOCK

USER_DIP6

USER_DIP5

USER_DIP4

USER_DIP3

USER_DIP2

USER_DIP1

USER_DIP0

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

—

(Connects to USB MAX II pin B6)

H34

F33

G33

H32

D34

E34

D33

Table 2–25 lists the user-defined DIP switch component reference and the


Table 2–25. User-Defined DIP Switch Component Reference and Manufacturing Information

Board Reference

SW4

Description

Eight-Position DIP switch

Manufacturer

Grayhill

Manufacturer

Part Number

76SB08ST


www.grayhill.com

User-Defined LEDs

The development board includes eight user-defined LEDs. Board references D18 through D25 are user LEDs that allow status and debugging signals to be driven to the LEDs from the designs loaded into the Stratix V GT device. The LEDs illuminate when a logic 0 is driven, and turns off when a logic 1 is driven. There is no board-specific function for these LEDs.

Table 2–26 lists the user-defined LED schematic signal names and their corresponding

Stratix V GT pin numbers.

Table 2–26. User-Defined LED Schematic Signal Names and Functions (Part 1 of 2)


D18

D19

D20

D21

USER_LED_0

USER_LED_1

USER_LED_2

USER_LED_3

2.5-V

2.5-V

2.5-V

2.5-V

B32

A32

B34

A34





Table 2–26. User-Defined LED Schematic Signal Names and Functions (Part 2 of 2)


D22

USER_LED_4

2.5-V C34

D23

D24

D25

USER_LED_5

USER_LED_6

USER_LED_7

2.5-V

2.5-V

2.5-V

C33

F32

E32

Table 2–27 lists the user-defined LED component reference and the manufacturing

information.

Table 2–27. User-Defined LED Component Reference and Manufacturing Information

Board Reference Device Description Manufacturer

Manufacturer

Part Number

D18–D25

Green LEDs, 1206, SMT,

Clear Lens, 2.1 V

Lumex Inc.

SML-LX1206GC-TR

Manufacturer

Website

www.lumex.com

Character LCD

The development board includes a single 14-pin 0.1" pitch dual-row header that interfaces to a 16 character × 2 line Lumex LCD display. The LCD has a 14-pin receptacle that mounts directly to the board's 14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes.

Table 2–28 summarizes the LCD pin assignments. The signal names and directions are

relative to the Stratix V GT device.

Table 2–28. LCD Pin Assignments, Schematic Signal Names, and Functions

Board Reference

(J30)

10

11

12

13

14

8

9

6

7

4

5


LCD_D_Cn

LCD_Wen

LCD_EN

LCD_DATA0

LCD_DATA1

LCD_DATA2

LCD_DATA3

LCD_DATA4

LCD_DATA5

LCD_DATA6

LCD_DATA7

I/O Standard

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V


Pin Number

C15

C14

D15

D16

F14

B14

B13

A14

A13

B16

A16

Description

LCD data or command select

LCD write enable

LCD chip select

LCD data bus

LCD data bus

LCD data bus

LCD data bus

LCD data bus

LCD data bus

LCD data bus

LCD data bus






2–31

Table 2–29 shows the LCD pin definitions, and is an excerpt from the Lumex data

sheet.

Table 2–29. LCD Pin Definitions and Functions

Pin

Number

1

2

3

4

5

6

7–14

V

V

V

DD

SS

0

RS

Symbol

R/W

E

DB0–DB7

Level

—

—

—

H/L

H/L

H, H to L

H/L

Function

Power supply

5 V

GND (0 V)

For LCD drive

Register select signal

H: Data input

L: Instruction input

H: Data read (module to MPU)

L: Data write (MPU to module)

Enable

Data bus, software selectable 4-bit or 8-bit mode f

For more information such as timing, character maps, interface guidelines, and other related documentation, visit www.lumex.com

.

Table 2–30 lists the LCD component references and the manufacturing information.

Table 2–30. LCD Component References and Manufacturing Information

Board

Reference


J30

2×7 pin, 100 mil, vertical header Samtec

2×16 character display, 5×8 dot matrix

Lumex Inc.

Manufacturer

Part Number

TSM-107-01-G-DV

LCM-S01602DSR/C

Manufacturer

Website

www.samtec.com

www.lumex.com




Components and Interfaces

Components and Interfaces

■

■

This section describes the development board's communication ports and interface cards relative to the Stratix V GT device. The development board supports the following components and interfaces:

10/100/1000 Ethernet

Transceiver interfaces

■

XFP interface

■

Small Form-Factor Pluggable (SFP+) interface

10/100/1000 Ethernet

The development board supports a 10/100/1000 BASE-T Ethernet connection using a

Marvell 88E1111 PHY device and the Altera Triple-Speed Ethernet MegaCore MAC function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA. The Stratix V GT device can communicate with the LVDS interfaces at up to 1.25 Gbps. The MAC function must be provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5-V and 1.2-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 with internal magnetics that can be used for driving copper lines with

Ethernet traffic.

Figure 2–9

shows the SGMII interface between the FPGA (MAC) and Marvell 88E1111

PHY.

Figure 2–9. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

MAC

S_OUT

±

S_IN

±

SGMII Interface

88E1111

Device

Transformer

RJ45

CAT 5 UTP:

- 10BASE-T

- 100BASE-TX

- 1000BASE-T

Table 2–31 lists the Ethernet PHY interface pin assignments.

Table 2–31. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (U22)

23

70

76

74

73


ENET_INTN

ENET_LED_DUPLEX

ENET_LED_LINK10

ENET_LED_LINK100

ENET_LED_LINK1000

I/O Standard

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

Stratix V GT

Device Pin Number

AL14

—

—

—

—

Description

Management bus Interrupt

Duplex LED

10-Mb link LED

100-Mb link LED

1000-Mb link LED






2–33

Table 2–31. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference (U22)

12

14

16

9

93

91

94

11

24

2

95

92

29

33

39

42

31

34

41

43

82

55

8

25

69

68

28

75

77

81


ENET_LED_RX

ENET_LED_TX

ENET_RSTN

ENET_SGMII_RX_N

ENET_SGMII_RX_P

ENET_SGMII_TX_N

ENET_SGMII_TX_P

ENET_XTAL_25MHZ

GTXCLK

MDC

MDI_N0

MDI_N1

MDI_N2

MDI_N3

MDI_P0

MDI_P1

MDI_P2

MDI_P3

MDIO

RXCLK

RXD0

RXD1

RXD2

RXD3

RXDV

TXD0

TXD1

TXD2

TXD3

TXEN

I/O Standard

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

2.5-V

Stratix V GT


AE16

AB15

AF17

AK17

AL17

AJ16

AJ17

AF16

AC16

AH16

AG17

AD15

—

—

—

—

—

—

—

—

AK15

—

AE15

AB16

—

—

AT6

AJ15

AH15

AL15

Description

RX data active LED

TX data active LED

Device reset

SGMII receive

SGMII receive

SGMII transmit

SGMII transmit

25-MHz clock

Ethernet transmit clock

Management bus data clock

Management bus data

Management bus data

Management bus data

Management bus data

Management bus data

Management bus data

Management bus data

Management bus data

Management bus data input/output

SGMII receive clock

SGMII receive data

SGMII receive data

SGMII receive data

SGMII receive data

SGMII receive data valid

SGMII transmit data

SGMII transmit data

SGMII transmit data

SGMII transmit data

SGMII transmit enable

Table 2–32 lists the Ethernet PHY interface component reference and manufacturing

information.

Table 2–32. Ethernet PHY Component Reference and Manufacturing Information


Manufacturing

Part Number

U22 Ethernet PHY BASE-T device

Marvel

Semiconductor

88E1111-B2-CAAIC000

Manufacturer

Website

www.marvell.com





Transceiver Interfaces

The transceiver signal integrity development board incorporates an XFP and SFP+ transceiver module. Each module has a single duplex channel.

XFP Interface

Table 2–33 lists the XFP connector cage interface pin assignments.

Table 2–33. XFP Interface Pin Assignments, Signal Names and Functions

Board Reference

(U25)

21

4

12

10

11

5

16

24

25

3

28

29

18


Name

GXB_TXLN_5

GXB_TXLP_5

GXB_RXLN_5

GXB_RXLP_5

REFCLK_XFPN

REFCLK_XFPP

XFP_MOD_DESEL

XFP_PDOWN_RST

XFP_T_INTERRUPT

XFP_T_MOD_ABS

XFP_T_SCL

XFP_T_SDA

XFP_TX_DIS

I/O Standard

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.4-V PCML

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

Stratix V GT


AW23

AV22

AW26

AW25

AV25

AW22

AH35

AH34

AK39

AK38

—

—

AV23

Description

GXB transmit

GXB transmit

GXB receive

GXB receive

XFP reference clock

XFP reference clock

Module deselect

Power down reset

Interrupt

Module absent

Two-wire serial interface clock line

Two-wire serial interface data line

Disables transmitter output

Table 2–34 lists the XFP interface component reference and manufacturing

information.

Table 2–34. XFP Interface Component Reference and Manufacturing Information

Board

Reference


Manufacturing

Part Number

U25

XFP 30-pin connector, 30UM gold plating, high speed

XFP cage without light pipe, press fit

Amphenol

Tyco

Amphenol

Tyco

1367500-1

1489951-1

Manufacturer

Website

www.amphenol.com

www.te.com






2–35

SFP+ Interface

Table 2–31 lists the pin assignments for the SFP+ interface (SFPA) and their

corresponding schematic signal names and Stratix V GT pin numbers.

Table 2–35. SFP+ Interface Pin Assignments, Signal Names and Functions

Board Reference

(J51)

5

4

8

6

19

18

12

13


GXB_TXLN_18

GXB_TXLP_18

GXB_RXLN_18

GXB_RXLP_18

SFPA_LOS

SFPA_MOD0_PRSNTN

SFPA_MOD1_SCL

SFPA_MOD2_SDA

I/O Standard

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

7

9

3

2

SFPA_RATESEL0

SFPA_RATESEL1

SFPA_TXDISABLE

SFPA_TXFAULT

1.8-V

1.8-V

1.8-V

1.8-V

Stratix V GT


B28

B26

A26

B25

M35

M34

L37

L36

C27

C26

A28

A25

Description

GXB transmit

GXB transmit

GXB receive

GXB receive

Signal loss indicator

Module present indicator

Two-wire serial interface clock line

Two-wire serial interface data line

Rate select 0. Controls the SFP+ interface receiver.

Rate select 1. Controls the SFP+ interface receiver.

Turns off and disables the transmitter output

Transmitter fault

Table 2–34 lists the SFP+ interface component reference and manufacturing

information.

Table 2–36. SFP+ Interface Component Reference and Manufacturing Information

Board

Reference


Manufacturing

Part Number

J51

SFP+ connector - Mect family standard

SFP right-angle 20-pin SMT

SFP+ cage

Samtec

Molex

MECT-110-01-M-D-RA1

74754-0101

Manufacturer

Website

www.samtec.com

www.molex.com




Flash Memory

Flash Memory

The development board has a 1-Gb CFI-compatible synchronous flash device for non-volatile storage of the FPGA configuration data, board information, test application data, and user code space. The FPGA and MAX II System Controller shares this device.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 µs for a single word and 310 µs for a 32-word buffer. The erase time is 800 ms for a 128 K parameter block.

Table 2–37 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the Stratix V GT device in terms of I/O setting and direction.

Table 2–37. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (U21)

C7

C8

A8

G1

D7

D8

A7

B7

H8

B6

B8

F6

C4

A5

B5

C5

A3

B3

C3

D3

D1

D2

A2

C2

A1

B1

C1


F_AD1

F_AD2

F_AD3

F_AD4

F_AD5

F_AD6

F_AD7

F_AD8

F_AD9

F_AD10

F_AD11

F_AD12

F_AD13

F_AD14

F_AD15

F_AD16

F_AD17

F_AD18

F_AD19

F_AD20

F_AD21

F_AD22

F_AD23

F_AD24

F_AD25

F_AD26

F_ADVN

Name

I/O Standard

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V


Pin Number

AF13

AJ13

AJ12

AH12

AG11

AK12

AK11

AL12

AL11

AM13

AL13

AP7

AC11

AF11

AE11

AE13

AE12

AJ14

AH13

AG13

AE14

AD14

AC13

AC12

AG14

AF14

AD11

Description

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address valid

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus

Address bus





Power Supply

2–37

Table 2–37. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference (U21)

H7

E1

E3

F3

E4

E5

G5

G6

F7

B4

E6

F2

E2

G3

E7

F8

D4

G8

F4

F5

H5

G7

C6


F_BSYN

F_CEN

F_CLK

F_D0

F_D1

F_D2

F_D3

F_D4

F_D5

F_D6

F_D7

F_D8

F_D9

F_D10

F_D11

F_D12

F_D13

F_D14

F_D15

F_OEN

F_RSTN

F_WEN

F_WPN

Name

I/O Standard

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V

1.8-V


Pin Number

AN12

AN10

AM10

AR11

AR10

AT12

AU13

AU12

AR7

AP9

AN6

AN11

AM11

AP12

AU11

AT11

AW13

AV13

AW11

AN9

AL8

AM8

AP6

Description

Ready

Chip enable

Clock

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Data bus

Output enable

Reset

Write enable

Write protect

Table 2–38 lists the flash memory component reference and manufacturing

information.

Table 2–38. Flash Memory Component Reference and Manufacturing Information

Board Reference

U21

Description

1-Gb synchronous flash

Manufacturer

Micron

Manufacturing

Part Number

PC28F00AP30BF

Manufacturer

Website

www.micron.com

Power Supply

The development board’s power is provided through a laptop style DC power input.

The input voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to the various power rails used by the components on the board.

An on-board multi-channel power monitor device (LTC2978) measures both the voltage and current for several specific board rails. This device has the capability to trim voltage outputs ±10%.




Power Supply

Table 2–39 lists the power requirements for each major component on the board.

Table 2–39. Power Requirements

FPGA

Device

MAX II (for FPP configuration)

Flash

MAX II (for USB-Blaster)

EEPROM

USB PHY

Power monitor

Temperature sense ADC

ICS557-03 spread spectrum clock buffer (x1)

ICS8304 clock buffer

IDT5T9306 transceiver REFCLK clock buffers (x4)

T85A23157 dual analog switch

Character LCD

LEDs (x13)

Board power LED

Voltage Name Voltage (V) Note

S5GX_VCC

2p5V

2p5V_FLTR

1p5V

0.85

2.5

2.5

1.5

VCC

VCCHIP

VCCHSSI

VCCIO

VCCPD

VCCREF

VCCPGM

VCCBAT

VCC_CLKIN

Ferrite fitered from 2p5V,

VCCA_PLL, and VCCAUX

VCCPT

VCCH_GXB

VCCD_FPLL

VCCBAT

1.5

BT1 socket

VCCR_GTB (28G channels)

0.85 or 1.0

LDO

VCCT_GTB (28G channels)

0.85 or 1.0

LDO

VCCL_GTB (28G channels)

0.85 or 1.0

LDO

VCCRT_GXB

VCCA_GXB

VCCH_GXB

2p5V

0.85 or 1.0

Low noise switcher

2.5 or 3 Low noise switcher

1.5 Tied (low noise switcher)

2.5

—

2p5V

XFP_1p8V

2p5V

USBVCC

USBVCC

2p5V_USB

5V

3p3V

5.0

2.5

5.0

3.3

2.5

1.8

3.3

5.0

Core

I/O

Core or I/O

—

Core

I/O

—

—

3p3V

3p3V/2p5V

2p5V

5V

5V

2p5V

5V

3.3

3.3/2.5

2.5

5.0

5.0

2.5

5.0

25-MHz clock output to the FPGA

50-MHz clock outputs

Programmable clock outputs

—

—

—

—





Power Supply

2–39

Power Measurement

There are six voltage rails tied to two LTC2978 power monitor devices. These devices are capable of measuring the voltage and current for each voltage rail and also provide power sequencing. A sense resistor at each voltage rail is in place for these measurements. These devices are capable of trimming the output voltage ±10%. An

I

2

C bus connects to the MAX II CPLD and FPGA devices for control.

Table 2–40 lists the voltage rails. Each voltage is identified by its schematic signal

name.

Table 2–40. Voltage Rails

Schematic

Signal Name

S5GX_VCC

VCCR_GTB

VCCT_GTB

VCCL_GTB

VCCRT_GXB

VCCA_GXB

VCCH_GXB

VCCD_FPLL

VCCPT

Production

Silicon

0.85

0.85 or 1.0

0.85 or 1.0

0.85 or 1.0

0.85 or 1.0

2.5 or 3.0

—

—

—

Voltage (V)

Engineering

Silicon

0.9

1.1

1.1

1.1

1.2

3.3

1.6

1.6

1.6

Description

VCC, VCCHIP, VCCHSSI FPGA core power.

Transceiver receiver power for 28G channels.

Transceiver transmit power for 28G channels.

Transceiver clocking power for 28G channels.

Shared VCCR_GXB and VCCT_GXB transceiver power for 12.5G channels.

VCCA_GXB transceiver power.

VCCH_GXB transceiver power.

PLL power.

FPGA power.

The LTC2978 power monitor devices on this board are programmed with a project file that sets up each voltage rail according to a sequence. Each voltage rail adjusts its voltage level to within a certain tolerance. These two voltage rails can be adjusted using switch SW2.

Table 2–41 lists the VCCRT_GXB and VCCA_GXB voltage rails and their voltage level

depending on the switch position.

Table 2–41. Voltage Level Setting

Switch SW2 (Position 1 and 2)

Close (Default)

Open

Schematic Net Name

VCCRT_GXB

VCCA_GXB

VCCRT_GXB

VCCA_GXB

Voltage (V)

1.0

3.0

0.9

2.5

1

If you power off and power on the board again with SW2 in the open position, the voltages for VCCRT_GXB and VCCA_GXB voltage rails read 0.90 V and 2.5 V respectively and will not come up to the proper levels. This is due to the LTC2978 device trying to adjust these rails to their programed values, which it cannot due to the switch position of SW2. The work around to this issue is to set switch SW2 in the close position at power up.




Power Supply

Table 2–42 lists the power monitor devices component reference and manufacturing

information.

Table 2–42. Power Measurement ADC Component References and Manufacturing Information


Manufacturing

Part Number

Manufacturer

Website

U10, U11

IC, power supply monitor w/EPROM, octal PMBUS

Linear Technology LTC2978CUP#PBF www.linear.com

Power Distribution System

Figure 2–10 shows the power distribution system on the development board. The

VCCR_GTB

, VCCT_GTB, and VCCL_GTB power rails are separated on the 28G transceivers but are combined on the 12.5G transceivers.

Figure 2–10. Power Distribution System

14 V - 20 V

DC Input

LTC3855

Switching

Regulator

0.85 V

VCC

VCCHIP

VCCHSSI

LTC3855

Switching

Regulator

2.5 V

5 V

VCCIO

VCCPD

VCCPGM

VCCBAT

2.5 V Devices

Bead

VCCA_PLL

VCCAUX

3.3 V

LTM4615

Dual Switcher

(4 A)

1 LDO (1.5 A)

0.85 V / 1.0 V

2.5 V / 3.0 V

3.3 V Devices

LTC3026

LDO (1.5 A)

Bead

1.8 V

SFP+

XFP

VCCRT_GXB

LTM4608

Switcher

(8 A)

1.5 V

VCCA_GXB

VCCH_GXB

VCCD_PLL

VCCPT

VCCR_GTB

LEGEND

Stratix V GT FPGA Power

Other Power

LCD, Fan

LTC3026

LDO (1.5 A)

LTC3026

LDO (1.5 A)

LTC3026

LDO (1.5 A)

LTC3026

LDO (1.5 A)

VCCT_GXB

VCCL_GTB

Ethernet





Power Supply

2–41

Temperature Sense

The Stratix V GT die uses a MAX1619 temperature sense device for temperature monitoring. The device connects to the MAX II CPLD EPM2210 System Controller and the Stratix V GT device by a 2-wire SMB interface. The MAX1619 device is located at slave address 0011000b (18h).

The OVERTEMPn and TSENSE_ALERTn signals are driven by the MAX1619 temperature sense device based on a programmable threshold temperature. The OVERTEMPn signal is driven to the MAX II System Controller. An over-temperature warning LED (D7) indicates the temperature fault condition.

Table 2–43 lists the temperature sense interface pin assignments, signal names, and

functions.

Table 2–43. Temperature Sense Pin Assignments, Schematic Signal Names, and Functions

Board

Reference

(U12)

14

12

11

9

3

4


Name

SMBCLK_TEMP

SMBDATA_TEMP

ALERTn

OVERTEMPn

TEMPDIODE_P

TEMPDIODE_N

I/O

Standard

3.3-V

3.3-V

3.3-V

3.3-V

3.3-V

3.3-V

MAX II CPLD

System Controller

Pin Number

D3

C2

D2

E4

—

—

Stratix V GT

Device

Pin Number

B8

A8

E8

E7

V11

U11

Description

SMB clock

SMB data

Programmable alert

Fan enable

Current source and remote diode input

Remote diode input

Table 2–44 lists the temperature sense component reference and manufacturing

information.

Table 2–44. Temperature Sense Component Reference and Manufacturing Information


Manufacturing

Part Number

Manufacturer

Website

U12

Temperature sense, remote and local, programmable alert.

Maxim MAX1619MEE+T www.maxim-ic.com




Statement of China-RoHS Compliance

Statement of China-RoHS Compliance

Table 2–45 lists hazardous substances included with the kit.

Table 2–45. Table of Hazardous Substances’ Name and Concentration

Notes

(1)

,

(2)

Part Name

Lead

(Pb)

Cadmium

(Cd)

Hexavalent

Chromium

(Cr6+)

Mercury

(Hg)

Polybrominated biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

Stratix V GT transceiver signal integrity development board

14 V power supply

Type A-B USB cable

X*

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

User guide 0 0 0 0 0 0

Notes to Table 2–45 :

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.




Additional Information

This chapter provides additional information about the document and Altera.

Board Revision History

The following table lists the versions of all releases of the Stratix V GT transceiver signal integrity development board.

Date

January 2013

February 2012

Version Changes

Production silicon New device part number—5SGTMC7K2F40C2.

Engineering silicon Initial release.

Document Revision History

The following table shows the revision history for this document.

Date

May 2014

January 2013

February 2012

Version

1.2

1.1

1.0

Changes

Corrected ALM amount in the

“Board Component Blocks”

section and in Table 2–2

.

■

Revised the FPGA device part number for production silicon release.

■

Added Table 2–41 on page 2–39 to define the voltage levels for VCCRT_GXB and

VCCA_GXB

voltage rails.

■

Removed appendix A and appended the board revision history table in “Additional

Information” chapter.

Initial release.

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support

Technical training

(1)

Product literature

Nontechnical support (general)

(software licensing)

Contact Method

Website

Website

Email

Website

Email

Email

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Address

www.altera.com/support www.altera.com/training [email protected]

www.altera.com/literature [email protected]

[email protected]



1–2 Additional InformationAdditional Information

Typographic Conventions

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital

Letters bold type

Courier type

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Italic Type with Initial Capital Letters

Indicate document titles. For example, Stratix IV Design Guidelines.

Indicates variables. For example, n + 1.

italic type

Variable names are enclosed in angle brackets (< >). For example, <file name> and

<project name>.pof file.

Initial Capital Letters

“Subheading Title”

Indicate keyboard keys and menu names. For example, the Delete key and the

Options menu.

Quotation marks indicate references to sections in a document and titles of

Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi

, and input. The suffix n denotes an active-low signal. For example, resetn.

Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). r

1., 2., 3., and a., b., c., and so on

■

■ ■

1 h f m

An angled arrow instructs you to press the Enter key.

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

Bullets indicate a list of items when the sequence of the items is not important.

The hand points to information that requires special attention.

The question mark directs you to a software help system with related information.

The feet direct you to another document or website with related information.

The multimedia icon directs you to a related multimedia presentation. c w

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The feedback icon allows you to submit feedback to Altera about the document.

Methods for collecting feedback vary as appropriate for each document.




Altera Stratix V GT Edition Transceiver Signal Integrity Development Kit Reference Manual

Assistant Bot

Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

Contents

Chapter 1. Overview

Chapter 2. Board Components

Additional Information

1. Overview

General Description

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Stratix V GT FPGA

I/O Resources

MAX II CPLD System Controller

Configuration, Status, and Setup Elements

Configuration

FPGA Programming over Embedded USB-Blaster

FPGA Programming from Flash Memory

FPGA Programming over External USB-Blaster

JTAG Header

Status Elements

Status LEDs

Setup Elements

FPP Configuration/MAX II Bypass DIP Switch

Program Select Jumper

Reset Push Button

CPU Reset Push Button

Clock Circuitry

Dedicated Transceiver Clocks

General-Purpose Clocks

Embedded USB-Blaster Clocks

Transceiver Channels

Backplane Connectors

General User Input/Output

User-Defined Push Buttons

User-Defined DIP Switch

User-Defined LEDs

Character LCD

Components and Interfaces

10/100/1000 Ethernet

Transceiver Interfaces

XFP Interface

SFP+ Interface

Flash Memory

Power Supply

Power Measurement

Power Distribution System

Temperature Sense

Statement of China-RoHS Compliance

Additional Information

Board Revision History

Document Revision History

How to Contact Altera

Typographic Conventions

Key Features

Frequently Answers and Questions

What is the purpose of the Transceiver Signal Integrity Development Kit, Stratix V GT Edition?

What are the key components of the board?

How can I program the FPGA on the board?

What is the temperature range for the board?

Are there any specific handling precautions for the board?

Related manuals

Altera

Stratix V GT

Altera

Stratix V GX Edition

Altera

Stratix V GX Edition

Altera

Stratix V GT Edition

Altera

Stratix V GX Transceiver Signal Integrity Development Kit

Altera

Stratix IV GX Edition Reference Manual

Altera

Stratix IV GX