CM-A510 Reference Guide
CM-A510 CoM
Reference Guide
Introduction
© 2010 CompuLab Ltd.
All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means whether, electronic, mechanical, or otherwise
without the prior written permission of CompuLab Ltd..
No warranty of accuracy is given concerning the contents of the information contained in this
publication. To the extent permitted by law no liability (including liability to any person by reason of
negligence) will be accepted by CompuLab Ltd., its subsidiaries or employees for any direct or
indirect loss or damage caused by omissions from or inaccuracies in this document.
CompuLab Ltd. reserves the right to change details in this publication without notice.
Product and company names herein may be the trademarks of their respective owners.
CompuLab Ltd.
Malat Bldg., Technion, Haifa
32000, Israel
Tel: +972 (4) 8290100
http://www.compulab.co.il
Fax: +972 (4) 8325251
Revised November 2010
CM-A510 Reference Guide
2
Table of Contents
Table of Contents
1
INTRODUCTION .............................................................................................................. 6
1.1
1.2
1.3
2
OVERVIEW........................................................................................................................ 7
2.1
2.2
2.3
3
About This Document ...................................................................................................... 6
CM-A510 Part Number Legend....................................................................................... 6
Related Documents .......................................................................................................... 6
Highlights......................................................................................................................... 7
Block Diagram ................................................................................................................. 8
CM-A510 Features........................................................................................................... 9
CORE SYSTEM COMPONENTS.................................................................................. 11
3.1 Armada 510 SoC ............................................................................................................ 11
3.2 Multimedia System ........................................................................................................ 12
3.2.1 Video Decode Unit (VMeta)................................................................................. 12
3.2.2 Graphics Processing Unit...................................................................................... 12
3.3 Memory .......................................................................................................................... 13
3.3.1 DRAM................................................................................................................... 13
3.3.2 SPI Flash ............................................................................................................... 13
3.3.3 NAND Flash ......................................................................................................... 13
4
PERIPHERAL INTERFACES ....................................................................................... 14
4.1 Display Interface ............................................................................................................ 15
4.2 Gigabit Ethernet ............................................................................................................. 16
4.2.1 Primary Gigabit Ethernet ...................................................................................... 16
4.2.2 Secondary Gigabit Ethernet .................................................................................. 17
4.3 PCI Express.................................................................................................................... 18
4.4 SATA ............................................................................................................................. 18
4.5 USB 2.0 .......................................................................................................................... 19
4.6 WLAN............................................................................................................................ 20
4.7 Audio.............................................................................................................................. 21
4.7.1 Analog Audio........................................................................................................ 21
4.7.2 I2S ......................................................................................................................... 22
4.7.3 S/PDIF................................................................................................................... 23
4.8 UART’s .......................................................................................................................... 24
4.9 RS232............................................................................................................................. 24
4.10
MMC / SD / SDIO..................................................................................................... 25
4.11
Touch-Screen............................................................................................................. 26
4.12
GPIO.......................................................................................................................... 27
4.13
Camera Interface ....................................................................................................... 28
4.14
I2C.............................................................................................................................. 29
4.15
SPI ............................................................................................................................. 30
Revised November 2010
CM-A510 Reference Guide
3
Table of Contents
4.16
4.17
5
SSP ............................................................................................................................ 30
JTAG ......................................................................................................................... 31
SYSTEM LOGIC.............................................................................................................. 32
5.1 Power Management........................................................................................................ 32
5.1.1 Power Rails ........................................................................................................... 32
5.1.2 Low Power Mode.................................................................................................. 32
5.2 Reset............................................................................................................................... 32
5.3 Boot Options .................................................................................................................. 32
5.4 System and Miscellaneous Signals ................................................................................ 33
5.5 Signal Multiplexing Characteristics............................................................................... 33
5.6 RTC ................................................................................................................................ 34
5.7 LED ................................................................................................................................ 34
6
BASEBOARD INTERFACE ........................................................................................... 35
6.1
6.2
6.3
6.4
7
OPERATIONAL CHARACTERISTICS....................................................................... 41
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
Connector Pin-out .......................................................................................................... 35
Connector Type.............................................................................................................. 38
Mechanical Drawings..................................................................................................... 38
Standoffs ........................................................................................................................ 40
Absolute Maximum Ratings .......................................................................................... 41
Recommended Operating Conditions ............................................................................ 41
DC Electrical Characteristics ......................................................................................... 41
Power Consumption....................................................................................................... 41
ESD Performance........................................................................................................... 41
Thermal Characteristics ................................................................................................. 42
Operating Temperature Ranges...................................................................................... 42
APPLICATION NOTES.................................................................................................. 43
8.1 Baseboard Design Guidelines ........................................................................................ 43
8.2 Baseboard Troubleshooting ........................................................................................... 43
8.3 Ethernet Magnetics’ Implementation............................................................................. 44
8.3.1 Magnetics’ Selection............................................................................................. 44
8.3.2 Magnetics’ Connection ......................................................................................... 44
8.4 Heat-plate Integration..................................................................................................... 44
Revised November 2010
CM-A510 Reference Guide
4
Revision Information
Table 1
Revision Notes
Date
November 2010
Description
First release
Please check for a newer revision of this manual at CompuLab's web site – http://www.compulab.co.il/.
Compare the revision notes of the updated manual from the web site to those of the printed or
electronic version you have.
Revised November 2010
CM-A510 Reference Guide
5
Introduction
1
INTRODUCTION
1.1
About This Document
This document is part of a set of reference documents providing information necessary to operate and
program CompuLab’s CM-A510 Computer-on-Module.
1.2
CM-A510 Part Number Legend
For CM-A510 part number legend, please refer to the ‘Prices’ section at CompuLab website:
http://www.compulab.co.il/a510/html/a510-cm-price.htm.
1.3
Related Documents
For additional information, refer to the documents listed in Table 2.
Table 2
Related Documents
Document
Location
CM-A510 Product Developer Resources
88AP510 Functional Specifications
88AP510 Hardware Specifications
Revised November 2010
http://www.compulab.co.il/
CM-A510 Reference Guide
6
Overview
2 OVERVIEW
2.1
Highlights
· Marvell® ARMADA™ 510 CPU, dual
issue ARMv7, up to 1000 MHz
· Up to 1024 Mbyte DDR3
· Up to 512 Mbyte Flash Disk, including
file-system protection
· WLAN / WiFi 802.11b/g/n Interface
· Graphics controller supporting parallel
RGB and VGA interfaces with HD
1080p maximum resolution and dualhead operation
· H.264, MPEG-4, MPEG-2, VC-1and
additional video codecs implemented
by the VMeta subsystem
· Integrated GPU providing 2D / 3D
graphics acceleration with OpenGL-ES
support
· SATA-II hard disk interface
· 2 x 1000 BaseT Ethernet ports
· 4 x high-speed USB ports
· PCI Express interface
· SDIO / MMC interface
· Camera Interface port
· Audio sub-system with speaker,
microphone and S/PDIF support
· Touch-screen Controller
· Serial ports, I2C, GPIO
· Low standby and active power
consumption
· Small size: 75 x 65 x 8 mm
Revised November 2010
The CM-A510 is a small Computer-onModule board designed to serve as a
building block in embedded applications.
The CM-A510 has all the components
required to run most up to date Linux-based
operating systems. Ready-to-run packages
are available from CompuLab.
The small size and low power consumption
of the CM-A510 allows its integration into
portable and space-constrained designs,
while its low price makes it an ideal
selection for cost-sensitive applications.
The CM-A510 delivers fast processing and
a rich multimedia user experience, in a lowpower design that offers fast Internet
browsing, HD video playback, 3D graphics
and high-speed connectivity.
CM-A510 is based on a high-performance,
low-power Marvell® ARMADA™ 510
system-on-chip with an ARM v6/v7compliant superscalar processor core,
hardware graphics processing unit, video
decoding acceleration hardware and a broad
range of peripherals.
For embedded applications, the CM-A510
provides a variety of display interfaces, PCI
Express bus, two Gigabit Ethernet ports,
high-speed USB ports, SATA interface,
serial ports, general-purpose I/O lines and
many other essential functions. The user
interface is supported by an enhanced
graphics controller, USB interface for
keyboard/mouse and audio sub-system.
CM-A510 Reference Guide
7
Overview
2.2
Block Diagram
Figure 1
CM-A510 Block Diagram
5V DC
Power Management
Circuitry
back-up power
Touch
screen
controller
SPI-1
GPIO
SDIO-0
WiFi
b/g/n
I2C-0
24bit parallel RGB
RTC
Vmeta
Video
Decoder
MMC/SD-0
S/PDIF
MMC/SD-1
UART-0
I2C-0
ARMADA
510
Display
controller
Sheeva
ARM v7
analog VGA
GbE-0
GbE
PHY
BT-656
Revised November 2010
I2S
GbE
MAC
2D / 3D
graphics
accelerator
UART-1
UART-2
PCI
Express
controller
SATA 2.0
controller
NAND
controller
DDR3
512MB / 1GB
NAND
128MB / 512MB
CM-A510 Reference Guide
mic in
stereo out
S/PDIF
RS232
xcvr
COM-A
COM-B
COM-C
PCIe-1
GbE
controller
GbE-1
PCIe-0
SATA
USB2-0
USB2-0
USB2-1
USB2-1
USB 2.0
hub
Camera
SDRAM
controller
AUDIO
codec
SPI-0
SPI flash
(bootable)
1MB
8
Overview
2.3
CM-A510 Features
The "Option" column specifies the configuration code required to have the particular feature.
"+" means that the feature is always available.
Table 3
CPU, Memory and Busses
Feature
Specifications
CPU
RAM
NAND Flash Disk
Boot Flash
PCI Express bus
Table 4
Marvell Armada 510 CPU, 800 / 1000 MHz
ARMv7 architecture, integrated FPU, WMMX2
L1 cache: 32 KB (I-Cache), 32 KB (D-Cache)
L2 cache: 512 KB
DMA, Interrupt controller, Timers
512 - 1024 MB, DDR3, 533 MHz, 32-bit
128 - 512 Mbytes
1 MB, bootable
PCI Express Base Specification, Revision 1.1. One or two lanes.
Note: second lane is shared with optional second Ethernet controller
Specifications
Graphics Controller
Video acceleration
2D / 3D graphics
USB
Gigabit Ethernet
SATA interface
Serial Ports
(UARTs)
Camera Interface
General Purpose I/O
Keyboard & mouse
MMC / SD
Audio
Touchscreen ctrl.
RTC
Table 5
Supply Voltage
Active power
consumption
Standby/Sleep
consumption
Dimensions
Weight
MTBF
Revised November 2010
C
D
N
+
+
Peripherals
Feature
WiFi Interface
Option
16/18/24 bit color, resolution up to 1920 x 1080, frame buffer in
system DDR. Display types support: TFT (parallel RGB), analog
VGA. Dual-head support.
VMeta video decode subsystem running at rate up to 500 MHz.
Supporting H.264, MPEG-4, MPEG-2 and VC-1.
Part of Armada 510 SoC.
Integrated GPU providing 2D / 3D graphics acceleration with
OpenGL-ES support. Part of Armada 510 SoC.
Two Host / Slave USB2 high-speed port, 480 Mbps
Additional 2 x USB2 high-speed host ports, 480 Mbps
Armada 510 integrated MAC + RTL8211D PHY,
10/100/1000BaseT, activity LED’s
Realtek RTL8111 controller, 10/100/1000BaseT, activity LED’s
Armada 510 integrated SATA-II controller + PHY, 3Gb/s speed
3 UART ports, 16550 compatible:
COM-A – RS232 interface, partial modem controls, 250 Kbps
COM-B – 3.3V interface, Rx / Tx only, 900 Kbps
COM-C – 3.3V interface, partial modem controls, 900 Kbps
Direct camera sensor support, max resolution 1920 x 1080, pixel
clock up to 50MHz. ITU BT.656, digital RGB/YCbCr interface.
Up to 38 lines shared with other functions. Can also be used as
interrupt inputs.
USB or redirection from COM port
MMC / SD / SDIO support including SDHC up to 32GB
I2S compliant audio codec, stereo output, stereo line-in, differential
mic input.
S/PDIF output, consumer mode IEC 60958-3
TSC2046 touchscreen controller. Supports 4-wire resistive panels
Real Time Clock, powered by external lithium battery
Implements 802.11b/g/n wireless connectivity standard.
Broadcom 4319 802.11b/g/n chipset. On-board connector for
external antenna.
Option
+
+
+
U2
U4
E1
E2
+
+
+
+
+
+
A
+
I
+
W
Electrical, Mechanical and Environmental Specifications
Single 5V DC
2 – 5 W, depending on configuration and CPU speed
50 - 200 mW, depending on configuration and mode
75 x 65 x 8 mm
31 gram
> 100,000 hours
CM-A510 Reference Guide
9
Overview
Operation temperature
(case)
Storage temperature
Relative humidity
Shock
Vibration
Connectors
Connector insertion /
removal
Revised November 2010
Commercial: 0o to 70o C
Extended: -20o to 70o C
Industrial:
-40o to 85o C
-40o to 85o C
10% to 90% (operation)
05% to 95% (storage)
50G / 20 ms
20G / 0 - 600 Hz
2 x 140 pin, 0.6 mm
50 cycles
CM-A510 Reference Guide
10
Core system components
3
CORE SYSTEM COMPONENTS
3.1
Armada 510 SoC
The Marvell Armada 510 is a high-performance, highly integrated, low-power SoC with a high-end
ARM-compatible processor, a graphics processing unit, high definition video decoding acceleration
hardware and a broad range of peripherals. The Armada 510 integrates an ARMv6/v7-compliant,
high-speed, dual-issue Sheeva CPU core with double precision integrated Floating Point Unit (FPU)
and WMMX2 coprocessor, 32-KB L1 Data cache, 32-KB instruction cache and 512-KB L2 cache. It
also includes an advanced power management unit, an advanced 2D/3D graphics processing unit,
display controllers and a high-definition video decoder.
The Armada 510 integrates the following hardware engines to enhance performance:
·
·
·
·
High-definition Video Decoding Unit (VMeta)
2D/3D Graphics Processing Unit (GPU)
Power Management Unit supporting SoC low power states, Dynamic Frequency Scaling
(DFS) and Dynamic Voltage Scaling (DVS)
Two XOR DMA engines and 16-channel peripheral DMA controller
Figure 2
Revised November 2010
Armada 510 Block Diagram
CM-A510 Reference Guide
11
Core system components
3.2
Multimedia System
3.2.1
Video Decode Unit (VMeta)
The Video Decode unit decodes the compressed video elementary stream to produce the
reconstructed video frames for display or further processing.
VMeta supports the following video formats:
·
·
·
·
·
H.264 MP/HP @L4.1 with arbitrary slice order
VC1 AP @L3, MP @HL
MPEG2 MP @HL
DivX HD Compliant MPEG4
AVS
For additional details, please refer to section 9 of the “88AP510 Functional Specifications”.
3.2.2
Graphics Processing Unit
The Graphics Processing Unit (GPU) is a low-power, high-performance 2D/3D graphics core
designed to support the OpenGL-ES 2.0 Graphics Processing standards.
The Armada 510 GPU provides support for the following imaging and video features:
3D Features:
·
·
·
·
·
·
·
·
·
OpenGL ES 1.1/2.0 compliant
32-bit floating point pipeline including shaders
Up to eight programmable elements per vertex
Unified vertex and pixel shaders
Dependent texture operation with high-performance
Alpha blend
Support for eight simultaneous pixel textures and four simultaneous vertex textures
Point sampling, bi-linear sampling, tri-linear sampling, and cubic textures
Multi-sample Anti-aliasing
2D Features:
·
·
·
·
·
·
·
·
·
Bit, stretch, pattern blits and fast clear
Line drawing
Rectangle fill
Mono expansion for text rendering
ROP2, ROP3, ROP4
Alpha blending
90-/180-/270-degree rotation
Video data format conversion
High-quality scaling
For additional details, please refer to section 10 of “88AP510 Functional Specifications”.
Revised November 2010
CM-A510 Reference Guide
12
Core system components
3.3
Memory
3.3.1
DRAM
The CM-A510 board is assembled with 512 or 1024 Mbytes of DDR3. The DRAM interface is 32bits wide and runs with a 533 MHz clock.
3.3.2
SPI Flash
The CM-A510 is assembled with 1 Mbyte of SPI NOR flash.
The SPI NOR flash is the primary non-volatile memory device of the CM-A510, used for the bootloader and configuration blocks storage.
3.3.3
NAND Flash
The CM-A510 is assembled with 128 or 512 Mbytes of SLC NAND Flash.
The NAND Flash is the secondary non-volatile memory device of the CM-A510, used for OS storage
and flash drive implementation.
Revised November 2010
CM-A510 Reference Guide
13
Peripheral Interfaces
4
PERIPHERAL INTERFACES
The CM-A510 implements a number of peripheral interfaces through the interface connectors (P1 and
P2). The following notes apply to those interfaces:
·
·
·
·
·
Some interfaces/signals are available only with/without certain configuration options. Each
signal’s availability is noted in the “Signal description” table of each interface.
Certain interface pins can be configured as one of several signals. For pin multiplexing
characteristics, please refer to chapter 5.5.
Certain signals are available on more than one interface pin. Only one interface pin can be
used for each signal.
All of the CM-A510 digital interfaces operate at 3.3V CMOS voltage levels, unless otherwise
noted.
Certain software-configurable multi-purpose signals can only be configured on a group basis.
Only the entire group may be assigned with a specific function. Signals within a group cannot
be configured separately for different functions. Signal configuration grouping is noted in the
“Signal description” table of each interface.
The signals for each interface are described in the “Signal description” tables. The following notes
summarize the column headers for these tables:
·
·
·
·
·
“Signal name” – The symbolic name of each signal.
“Pin#” – The pin number on the interface connector.
“Type” – Signal type.
“Description” – Signal description.
“Availability” – Certain signals are not available with/without certain configuration options.
This column summarizes configuration requirements for each signal.
Each interface signal can be one of the following types. Signal type is noted in the “Signal
description” tables for each signal
·
·
·
·
·
·
·
Revised November 2010
“O” – Digital output.
“I” – Digital input.
“IO” – Digital Input/Output.
“AO” – Analog Output.
“AI” – Analog Input.
“OD” – Open Drain Signal (not pulled up on the CM-A510 unless otherwise noted).
“IPU” – Open Drain Signal (pulled up on the CM-A510 unless otherwise noted).
CM-A510 Reference Guide
14
Peripheral Interfaces
4.1
Display Interface
The CM-A510 display sub-system is based on the display controller of the Armada 510 SoC.
The display sub-system incorporates two independent display controllers supporting dual-head
operation and features two separate display interfaces:
·
·
24-bit parallel RGB
Analog VGA.
The display subsystem supports the following main features:
Display controller
·
·
·
·
·
Programmable pixel display modes (12, 16, 18 and 24 bits-per-pixel)
Programmable resolution of up to 1920 x 1080
Overlay and image scaling for video and graphics
Hardware cursor
Rotation of 90-, 180- and 270-degrees
For additional details, please refer to section 11 of the “88AP510 Functional Specifications”.
Table 6
Display interface signals
Signal Name
Pin #
Type
Description
Parallel RGB
LCD_PCLK
LCD_HSYNC
LCD_VSYNC
LCD_E
P1-108
P1-109
P1-107
P1-105
O
O
O
O
LCD_D0
LCD_D1
LCD_D2
LCD_D3
LCD_D4
LCD_D5
LCD_D6
LCD_D7
LCD_D8
LCD_D9
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_D18
LCD_D19
LCD_D20
LCD_D21
LCD_D22
LCD_D23
P1-75
P1-76
P1-77
P1-78
P1-81
P1-82
P1-83
P1-84
P1-85
P1-87
P1-88
P1-89
P1-90
P1-92
P1-93
P1-94
P1-95
P1-96
P1-97
P1-99
P1-100
P1-101
P1-102
P1-104
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
VGA_R
VGA_G
VGA_B
VGA_HSYNC
VGA_VSYNC
P1-28
P1-30
P1-32
P1-34
P1-36
AO
AO
AO
O
O
Pixel clock
Horizontal synchronization
Vertical synchronization
Pixel data enable
Pixel data bit 0
Pixel data bit 1
Pixel data bit 2
Pixel data bit 3
Pixel data bit 4
Pixel data bit 5
Pixel data bit 6
Pixel data bit 7
Pixel data bit 8
Pixel data bit 9
Pixel data bit 10
Pixel data bit 11
Pixel data bit 12
Pixel data bit 13
Pixel data bit 14
Pixel data bit 15
Pixel data bit 16
Pixel data bit 17
Pixel data bit 18
Pixel data bit 19
Pixel data bit 20
Pixel data bit 21
Pixel data bit 22
Pixel data bit 23
RGB444
mode
RGB565
mode
RGB666
mode
RGB888
mode
Red[4]
Red[5]
Red[6]
Red[7]
Green[4]
Green[5]
Green[6]
Green[7]
Blue[4]
Blue[5]
Blue[6]
Blue[7]
-
Red[3]
Red[4]
Red[5]
Red[6]
Red[7]
Green[2]
Green[3]
Green[4]
Green[5]
Green[6]
Green[7]
Blue[3]
Blue[4]
Blue[5]
Blue[6]
Blue[7]
-
Red[2]
Red[3]
Red[4]
Red[5]
Red[6]
Red[7]
Green[2]
Green[3]
Green[4]
Green[5]
Green[6]
Green[7]
Blue[2]
Blue[3]
Blue[4]
Blue[5]
Blue[6]
Blue[7]
-
Red[0]
Red[1]
Red[2]
Red[3]
Red[4]
Red[5]
Red[6]
Red[7]
Green[0]
Green[1]
Green[2]
Green[3]
Green[4]
Green[5]
Green[6]
Green[7]
Blue[0]
Blue[1]
Blue[2]
Blue[3]
Blue[4]
Blue[5]
Blue[6]
Blue[7]
VGA
Revised November 2010
Red video signal
Green video signal
Blue video signal
Horizontal synchronization
Vertical synchronization
CM-A510 Reference Guide
15
Peripheral Interfaces
4.2
Gigabit Ethernet
The CM-A510 incorporates up to two full-featured Gigabit Ethernet interfaces.
4.2.1
Primary Gigabit Ethernet
The CM-A510 primary Gigabit Ethernet interface is implemented with the Armada 510 Gigabit
Ethernet controller and an on-board RTL8211D Realtek PHY. The interface supports the following
main features:
·
·
·
·
·
·
Fully compliant with IEEE 802.3 standard
1000 Mbps operation – full duplex
10 / 100 Mbps operation – half and full duplex
Crossover Detection and Auto-Correction
Auto-negotiation
Activity and speed indicator LED controls
Table 7
Primary Gigabit Ethernet interface signals
Signal Name
Pin #
Type
Description
LAN0_MDIP0
LAN0_MDIN0
LAN0_MDIP1
LAN0_MDIN1
LAN0_MDIP2
LAN0_MDIN2
LAN0_MDIP3
LAN0_MDIN3
LAN0_LED0
LAN0_LED1
LAN0_LED2
P1-2
P1-4
P1-1
P1-3
P1-10
P1-12
P1-9
P1-11
P1-6
P1-5
P1-13
IO
IO
IO
IO
IO
IO
IO
IO
O
O
O
First pair in 1000Base-T / transmit pair in
10Base-T and 100Base-T.
Second pair in 1000Base-T / receive pair in
10Base-T and 100Base-T.
Third pair in 1000Base-T.
Availability
Only available with either ‘E1’ or
‘E2’ configuration options.
Forth pair in 1000Base-T.
Activity LED output. Active low.
10 / 100 / 1000 LED output.
10 / 100 / 1000 + activity LED output.
NOTE: The primary Gigabit Ethernet interface is available only with either ‘E1’ or ‘E2’
configuration options.
NOTE: For magnetics’ selection recommendations, please refer to section 8.3 of this document.
Revised November 2010
CM-A510 Reference Guide
16
Peripheral Interfaces
4.2.2
Secondary Gigabit Ethernet
The CM-A510 secondary Gigabit Ethernet interface is implemented with the RTL8111D Realtek
Gigabit Ethernet controller. The controller is connected to the PCIe-1 interface of the Armada 510
SoC. The interface supports the following main features:
·
·
·
·
Fully compliant with IEEE 802.3 standard
Crossover Detection and Auto-Correction
Auto-negotiation
Activity and speed indicator LED controls
Table 8
Secondary Gigabit Ethernet interface signals
Signal Name
Pin #
Type
Description
LAN1_MDIP0
LAN1_MDIN0
LAN1_MDIP1
LAN1_MDIN1
LAN1_MDIP2
LAN1_MDIN2
LAN1_MDIP3
LAN1_MDIN3
LAN1_LED0
LAN1_LED1
LAN1_LED2
P2-2
P2-4
P2-1
P2-3
P2-10
P2-12
P2-9
P2-11
P2-6
P2-5
P2-13
IO
IO
IO
IO
IO
IO
IO
IO
O
O
O
First pair in 1000Base-T / transmit pair in
10Base-T and 100Base-T
Second pair in 1000Base-T / receive pair in
10Base-T and 100Base-T
Third pair in 1000Base-T
Availability
Only available with the ‘E2’
configuration option.
Forth pair in 1000Base-T
Link 10 + activity LED output
Link 100 + activity LED output
Link 10 / 100 / 1000 + activity LED output.
NOTE: The primary Gigabit Ethernet interface is available only with the ‘E2’ configuration
option.
NOTE: For magnetics’ selection recommendations, please refer to section 8.3 of this document.
Revised November 2010
CM-A510 Reference Guide
17
Peripheral Interfaces
4.3
PCI Express
The CM-A510 features up to two PCI Express ports implemented with the Armada 510 PCI Express
controller. PCIe-0 port is always available. PCIe-1 port is multiplexed with the secondary Gigabit
Ethernet interface. The PCI Express interface provides the following features:
·
·
·
PCI Express Base 1.1 compatible
Root complex port
2.5 GHz signaling
For additional details, please refer to section 20 of “88AP510 Functional Specifications”.
Table 9
PCI Express interface signals
Signal Name
Pin #
Type
PCIE0_TX_P
PCIE0_TX_N
PCIE0_RX_P
PCIE0_RX_N
PCIE0_CLK_P
PCIE0_CLK_N
PCIE0_nCLKREQ
P2-114
P2-112
P2-108
P2-106
P2-101
P2-99
P2-17
O
O
I
I
O
O
IO
Description
Availability
PCIe-0 Interface
PCI Express transmit data pair
PCI Express receive data pair
Always available.
PCI Express reference clock pair
PCI Express clock request input
PCIe-1 Interface
PCIE1_TX_P
PCIE1_TX_N
PCIE1_RX_P
PCIE1_RX_N
PCIE1_CLK_P
PCIE1_CLK_N
PCIE1_nCLKREQ
P2-113
P2-111
P2-107
P2-105
P2-83
P2-81
P2-15
O
O
I
I
O
O
IO
PCI Express transmit data pair
PCI Express receive data pair
Only available without the ‘E2’
configuration option.
PCI Express reference clock pair
PCI Express clock request input
NOTE: PCIe-1 interface is available only without the ‘E2’ configuration option.
4.4
SATA
The CM-A510 incorporates a single SATA-II port implemented with the Armada 510 SATA-II
controller. The interface supports the following main features:
·
·
·
·
·
Fully compatible with the SATA-II phase 1.0 specification
SATA-II 3 Gb/s data rate
SATA-II power management compliant
SATA-II device hot-swap compliant
SATA-II Native Command Queuing (NCQ)
For additional details, please refer to section 21 of the “88AP510 Functional Specifications”.
Table 10
Signal Name
SATA_TX+
SATA_TXSATA_RX+
SATA_RX-
Revised November 2010
SATA-II interface signals
Pin #
Type
P2-126
P2-124
P2-120
P2-118
O
O
I
I
Description
Availability
SATA-II transmit data pair.
Always available.
SATA-II receive data pair.
CM-A510 Reference Guide
18
Peripheral Interfaces
4.5
USB 2.0
The CM-A510 provides up to four USB 2.0 ports implemented with the Armada 510 USB sub-system
and an optional on-board USB 2.0 hub. The USB 2.0 interface provides the following features:
·
·
·
Complies with EHCI (high-speed host controller)
Complies with OHCI (low-speed/full-speed host controller)
Complies with the USB 2.0 standard for high-speed (480M bit/s) functions
Table 11
Signal Name
USB 2.0 Host interface signals
Pin #
Type
Description
Availability
USB0 interface
USB0_DP
USB0_DN
P2-132
P2-130
AOI
AOI
USB port 0 positive data
USB port 0 negative data
USB1_DP
USB1_DN
P2-138
P2-136
AOI
AOI
USB1_CPEN
P1-128
O
USB1_nOVC
P2-140
IPU
USB port 1 positive data
USB port 1 negative data
USB port 1 external 5V
supply enable. Active high.
USB port 1 over current
sense.
Only available with either ‘U2’ or ‘U4’ configuration
options.
USB1 interface
Only available with either ‘U2’ or ‘U4’ configuration
options.
Only available with ‘U4’ configuration option.
USB2 interface
USB2_DP
USB2_DN
P1-131
P1-129
AOI
AOI
USB2_CPEN
P1-126
O
USB2_nOVC
P2-138
IPU
USB3_DP
USB3_DN
P1-137
P1-135
AOI
AOI
USB3_CPEN
P1-133
O
USB3_nOVC
P2-136
IPU
USB port 2 positive data
USB port 2 negative data
USB port 2 external 5V
supply enable. Active high.
USB port 2 over current
sense.
Only available with the ‘U4’ configuration option.
USB3 interface
USB port 3 positive data
USB port 3 negative data
USB port 3 external 5V
supply enable. Active high.
USB port 3 over current
sense.
Only available with the ‘U4’ configuration option.
NOTE: Four USB ports are available only with the ‘U4’ configuration option.
Revised November 2010
CM-A510 Reference Guide
19
Peripheral Interfaces
4.6
WLAN
The CM-A510 incorporates full-featured 802.11 b/g/n capabilities, implemented with the USI WMN-BM-01 WLAN controller module. The WM-N-BM-01 is a complete IEEE 802.11b/g/n solution
based on the Broadcom 4319 chipset.
The CM-A510 WLAN interface supports the following security features:
·
·
·
WEP (64 bit/128 bit)
WPA TKIP
WPA2
The WM-N-BM-01 is connected to the Armada SoC via the SD-1 port.
Antenna Connection
The WM-N-BM-01 requires a single 2.45GHz antenna. The antenna is connected via the onboard
UFL high frequency connector J1. Any type of 2.45GHz WLAN antenna can be used. Please refer to
section 6.3 for connector location.
Table 12
J1 connector data
Manufacturer
Hirose
U.FL-R-MT(10)
Table 13
Mating Connector
Hirose U.FL-LP-040
802.11b/g/n RF system specifications
Parameter
Frequency Band
Maximum receive level
Transmit Power Output
Wide-band Noise
Error Vector Magnitude
Receive Sensitivity
Revised November 2010
Mfg. P/N
Test Condition
Typical Value
Units
PER < 8%
1, 2, 5.5, 11 Mbps
6, 9 Mbps
11n (HT20)
11n (HT40)
@ 869MHz ~ 960MHz
@ 1800MHz ~ 1990MHz
@ 2110MHz ~ 2170MHz
@ 1 Mbps
@ 6 Mbps
@ 11 Mbps
@ 54 Mbps
@ MCS7
@ MCS0
1 Mbps, 8% PER
6 Mbps, 10% PER
11 Mbps, 8% PER
54 Mbps, 10% PER
65 Mbps, 10% PER
135 Mbps, 10% PER
2.400 – 2.497
-10
17
15
14
14
-160
-160
-150
-13
-30
-13
-30
-30
-30
-94
-86
-87
-73
-72
-68
GHz
dBm
dBm
dBm
dBm
dBm
dBm/Hz
dBm/Hz
dBm/Hz
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
dBm
dBm
dBm
CM-A510 Reference Guide
20
Peripheral Interfaces
4.7
Audio
4.7.1
Analog Audio
The CM-A510 analog audio subsystem is implemented with Texas Instruments TLV320AIC23b
audio codec. The analog audio subsystem supports the following features:
·
·
·
·
·
·
Single ended stereo-line output
Single ended stereo-line input
Integrated electret-microphone biasing and buffering solution
8-kHz – 96-kHz Sampling-Frequency Support
100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz)
90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz)
Table 14
Audio Characteristics
Parameter
Test conditions
Min
Typ
Max
Unit
Headphone Output
0-dB full-scale output voltage
1.0
30
40
Rload = 32Ω
Rload = 16Ω
Maximum output power, PO
Signal-to-noise ratio, A-weighted (see
Note 2)
90
Total harmonic distortion
1kHz output
Power supply rejection ratio
Programmable gain
Programmable-gain step size
Mute attenuation
1 kHz, 100 mVp-p
1 kHz output
Vrms
97
dB
Pout = 10mW
Pout = 20mW
0.1
1.0
50
-73
%
%
dB
6
1
80
1 kHz output
Line Input to ADC
Input signal level (0 dB)
Signal-to-noise ratio, A-weighted, 0-dB
gain (see Notes 1 and 2)
Dynamic range, A-weighted, −60-dB
full-scale input (see Note 2)
Total harmonic distortion, −1-dB input,
0-dB gain
Power supply rejection ratio
ADC Channel Separation
Programmable-gain step size
Mute attenuation
Input resistance
Fsample = 48 kHz.
1 kHz, 100 mVp-p
1 kHz input tone
Monotonic
0dB, 1 kHz input tone
12 dB input gain
0 dB input gain
85
1.0
90
Vrms
dB
85
90
dB
-80
dB
50
90
1.5
80
dB
dB
dB
dB
10
30
Input capacitance
20
35
10
kΩ
pF
Microphone Input to ADC
Input signal level (0 dB)
Signal-to-noise ratio, A-weighted, 0-dB
gain (see Notes 1 and 2)
Dynamic range, A-weighted, −60-dB
full-scale input (see Note 2)
Total harmonic distortion, −1-dB input,
0-dB gain
Power supply rejection ratio
Mute attenuation
Input resistance
Input capacitance
Revised November 2010
1 kHz, 100 mVp-p
0dB, 1 kHz input tone
CM-A510 Reference Guide
80
1.0
85
Vrms
dB
80
85
dB
-60
dB
50
80
dB
dB
kΩ
pF
60
8
14
10
21
Peripheral Interfaces
Microphone BIas
Bias voltage
Bias-current source
2.375
2.475
2.575
3
V
mA
For additional details, please refer to the TLV320AIC23B datasheet, available from Texas
Instruments.
Table 15
Analog audio signals
Signal Name
AUDIO_OUT_R
Pin #
Type
P2-139
AO
AUDIO_OUT_L
P2-137
AO
AUDIO_IN_R
AUDIO_IN_L
P2-131
P2-133
AI
AI
MIC_IN
P2-129
AI
MIC_BIAS
P2-125
O
AUDIO_GND
P2-123
P
Description
Availability
Right stereo mixer-channel amplified
headphone output
Left stereo mixer-channel amplified
headphone output
Right stereo line input
Left stereo line input
Buffered amplifier input suitable for use
with electret-microphone
Microphone bias output, suitable for
electret-microphone biasing, 2.475V
nominal voltage.
Dedicated analog audio ground
Only available with the
‘A’ configuration option.
NOTE: The analog audio interface is available only with the ‘A’ configuration option.
4.7.2
I2S
The CM-A510 I2S interface is implemented with the Armada 510 I2S controller. The interface
supports the following main features:
·
·
·
Plain I2S, right-justified and left-justified formats
An audio sample rate of 44.1/48/96 kHz
Sample sizes of 16-bit, 20-bit, 24-bit and 32-bit.
For additional details, please refer to section 12 of “88AP510 Functional Specifications”.
Table 16
I2S signals
Signal Name
I2S1_BCLK
I2S1_DI
I2S1_DO
I2S1_LRCLK
I2S1_MCLK
Pin #
Type
P2-45
P2-47
P2-49
P2-51
P2-53
O
I
O
O
O
Description
Bit clock
Receiver data in
Transmitter data out
Left/right clock
Master clock
Availability
Always available.
Configuration
Group
Digital Audio
NOTE: I2S signals are multiplexed with signals used for other interfaces. For multiplexing
characteristics, please refer to section 5.5 of this document.
NOTE: I2S signals can only be configured on a group basis. Only the entire group may be
assigned with a specific function. Individual I2S signals cannot be configured
separately for different functions.
Revised November 2010
CM-A510 Reference Guide
22
Peripheral Interfaces
4.7.3
S/PDIF
The CM-A510 features an S/PDIF interface implemented with the Armada 510 S/PDIF controller.
The interface supports the following main features:
·
·
·
Compliant with the IEC60958-1, IEC60958-3 and IEC61937 specifications
An audio sample rate of 44.1/48/96 kHz
Sample sizes of 16-bit, 20-bit, 24-bit and 32-bit.
For additional details, please refer to section 12 of the “88AP510 Functional Specifications”.
Table 17
S/PDIF signals
Signal Name
S/PDIF
Pin #
Type
P2-41
O
Description
S/PDIF transmitter data out
Availability
Always available.
NOTE: S/PDIF signals are multiplexed with signals used for other interfaces. For multiplexing
characteristics, please refer to section 5.5 of this document.
Revised November 2010
CM-A510 Reference Guide
23
Peripheral Interfaces
4.8
UART’s
The CM-A510 incorporates three general purpose UART’s. The following features are supported:
·
·
·
·
16550 compatibility
16-byte FIFO for receiver and 16-byte FIFO for transmitter
Programmable baud rate of up to 900 Kbps
Configurable data format
Table 18
UART signals
Signal Name
Pin #
Type
P1-114
P1-112
O
I
Description
Availability
Configuration Group
UART-1
UART1_TXD
UART1_RXD
UART serial data out
UART serial data in
Always
available.
UART1
Always
available.
Each pin is configured
separately.
Always
available.
Each pin is configured
separately.
UART-2
UART2_TXD
UART2_RXD
P1-64
P1-66
O
I
UART serial data out
UART serial data in
UART3_TXD
UART3_RXD
UART3_CTS
UART3_RTS
P1-72
P1-61
P1-70
P1-68
O
I
O
I
UART serial data out
UART serial data in
UART clear to send
UART request to send
UART-3
NOTE: UART signals are multiplexed with signals used for other interfaces. For multiplexing
characteristics, please refer to section 5.5 of this document.
NOTE: UART-1 signals can only be configured on a group basis. Only the entire group may be
assigned with a specific function. Individual UART-1 signals cannot be configured
separately for different functions.
4.9
RS232
The CM-A510 incorporates a single RS232 port. The following features are supported:
·
·
·
·
·
16550 compatibility
16-byte FIFO for receiver and 16-byte FIFO for transmitter
Programmable baud rate of up to 250 Kbps
Configurable data format
RS-232 bus-pin ESD protection exceeds ±15 kV using the Human-Body Model
The RS232 port is derived from UART-0 of the Armada 510 SoC.
NOTE: The RS232 port operates at RS232 voltage levels.
Revised November 2010
CM-A510 Reference Guide
24
Peripheral Interfaces
Table 19
RS232 signals
Signal Name
RS232_TXD
RS232_RXD
RS232_CTS
RS232_RTS
4.10
Pin #
Type
P1-119
P1-117
P1-123
P1-121
O
I
I
O
Description
Availability
RS232 serial data out
RS232 serial data in
RS232 clear to send
RS232 request to send
Always available.
MMC / SD / SDIO
The CM-A510 features two multimedia card high-speed/secure data/secure digital I/O (MMC / SD /
SDIO) host interfaces. The following main features are supported:
·
·
·
·
1-bit/4-bit SD memory, SDIO and MMC cards
Up to 50MHz (SD PHY rev 1.1 high speed)
SDHC (SD PHY rev 2.0)
DMA and PIO operation
For additional details, please refer to section 23 of “88AP510 Functional Specifications”.
NOTE: MMC/SD/SDIO signals are multiplexed with signals used for other interfaces. For
multiplexing characteristics, please refer to section 5.5 of this document.
NOTE: MMC/SD/SDIO signals can only be configured on a group basis. Only the entire group
may be assigned with a specific function. Individual signals cannot be configured
separately for different functions.
Table 20
MMC/SD/SDIO signals
Signal Name
Pin #
Type
Description
Availability
Configuration
Group
SD-0
SD0_DATA0
SD0_DATA1
SD0_DATA2
SD0_DATA3
SD0_CMD
SD0_CLK
SD0_CD
SD0_WP
P2-54
P2-56
P2-58
P2-60
P2-78
P2-76
P1-68
P1-70
IO
IO
IO
IO
IO
O
I
I
Data signal 0
Data signal 1
Data signal 2
Data signal 3
Command signal
Clock output
Card detection input
Card write protection input
Always
available.
SD-0
Always
available.
Each pin is
configured
separately.
SD-1
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD1_CMD
SD1_CLK
Revised November 2010
P2-61
P2-63
P2-65
P2-69
P2-75
P2-73
IO
IO
IO
IO
IO
O
Data signal 0
Data signal 1
Data signal 2
Data signal 3
Command signal
Clock output
CM-A510 Reference Guide
Only
available
without the
‘W’
configuration
option.
SD-1
25
Peripheral Interfaces
4.11
Touch-Screen
The CM-A510 features a resistive touch-screen interface. The interface supports 4-wire touch panels.
The touch-screen controller is connected to the SPI-1 interface of the Armada 510 SoC.
Table 21
Touch-screen signals
Signal Name
TS_X+
TS_XTS_Y+
TS_Y-
Revised November 2010
Pin #
P1-23
P1-21
P1-29
P1-27
Type
AI
AI
AI
AI
Description
Touch screen X+ (right)
Touch screen X- (left)
Touch screen Y+ (top)
Touch screen Y- (bottom)
CM-A510 Reference Guide
Availability
Only available with the
‘I’ configuration option.
26
Peripheral Interfaces
4.12
GPIO
The CM-A510 provides up to 44 GPIO signals. These signals can be configured for the following
applications:
·
·
Data input / output
Interrupt generation
For additional details, please refer to section 28 of “88AP510 Functional Specifications”.
NOTE: GPIO signals are multiplexed with signals used for other interfaces. For multiplexing
characteristics, please refer to section 5.5 of this document.
NOTE: Certain GPIO signals can only be configured on a group basis. Only the entire group
may be assigned with a specific function. Individual signals cannot be configured
separately for different functions.
Table 22
CM-A510
signal
P1-64
P1-66
P1-68
P1-70
P1-72
P1-61
P1-63
P1-65
P1-69
P1-71
P1-40
P1-42
P1-44
P1-46
P1-48
P1-45
P1-47
P1-49
P1-52
P1-51
P1-53
P1-57
P1-54
P1-56
P2-46
P2-78
P2-54
P2-56
P2-58
P2-60
P2-73
P2-75
P2-61
P2-63
P2-65
P2-69
Revised November 2010
GPIO signals
Armada 510
signal
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_38
GPIO_39
GPIO_40
GPIO_41
GPIO_42
GPIO_43
GPIO_44
GPIO_45
GPIO_46
GPIO_47
GPIO_48
GPIO_49
GPIO_50
GPIO_51
Availability
Available with all configurations. Muxed with UART-2, SSP.
Available with all configurations. Muxed with UART-2.
Available with all configurations. Muxed with UART-3, SD-0.
Available with all configurations. Muxed with UART-3, SD-0, I2C-2.
Available with all configurations. Muxed with UART-3, SD-0.
Available with all configurations. Muxed with UART-3, I2C-2.
Only available without ‘I’ option. Muxed with SPI-1, SD-0.
Only available without ‘I’ option. Muxed with SPI-1, SD-0, SSP.
Only available without ‘I’ option. Muxed with SPI-1, SSP.
Only available without ‘I’ option. Muxed with SPI-1, SSP.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with camera interface.
Available with all configurations. Muxed with SD-0.
Available with all configurations. Muxed with SD-0.
Available with all configurations. Muxed with SD-0.
Available with all configurations. Muxed with SD-0.
Available with all configurations. Muxed with SD-0.
Available with all configurations. Muxed with SD-0.
Only available without ‘W’ option. Muxed with SD-1.
Only available without ‘W’ option. Muxed with SD-1.
Only available without ‘W’ option. Muxed with SD-1.
Only available without ‘W’ option. Muxed with SD-1.
Only available without ‘W’ option. Muxed with SD-1.
Only available without ‘W’ option. Muxed with SD-1.
CM-A510 Reference Guide
Configuration
Group
Each pin is
configured
separately.
Camera
SD-0
SD-1
27
Peripheral Interfaces
CM-A510
signal
P2-47
P2-45
P2-53
P2-49
P2-51
P2-41
P1-112
P1-114
4.13
Armada 510
signal
GPIO_52
GPIO_53
GPIO_54
GPIO_55
GPIO_56
GPIO_57
GPIO_62
GPIO_63
Configuration
Group
Availability
Available with all configurations. Muxed with I2S.
Available with all configurations. Muxed with I2S.
Available with all configurations. Muxed with I2S.
Available with all configurations. Muxed with I2S.
Available with all configurations. Muxed with I2S, I2C-2.
Available with all configurations. Muxed with S/PDIF, I2C-2.
Available with all configurations. Muxed with UART-1.
Available with all configurations. Muxed with UART-1.
Digital Audio
UART-1
Camera Interface
The CM-A510 camera interface is implemented with the camera sub-system of the Armada 510 SoC.
The camera interface provides the system interface and the processing capability to connect RAW
image-sensor modules to the CM-A510. For additional details, please refer to section 17 of the
“88AP510 Functional Specifications”.
NOTE: Camera signals can only be configured on a group basis. Only the entire group may be
assigned with a specific function. Individual signals cannot be configured separately for
different functions.
Table 23
Camera interface signals
Signal Name
Pin #
Type
CAM_CLK
CAM_HSYNC
CAM_VSYNC
CAM_SNR_CTL0
CAM_SNR_CTL1
CAM_MCLK
CAM_D0
CAM_D1
CAM_D2
CAM_D3
CAM_D4
CAM_D5
CAM_D6
CAM_D7
P1-57
P1-51
P1-53
P1-54
P1-56
P1-52
P1-40
P1-42
P1-44
P1-46
P1-48
P1-45
P1-47
P1-49
I
I
I
O
O
O
I
I
I
I
I
I
I
I
Revised November 2010
Description
Pixel clock
Horizontal sync input
Vertical sync input
Sensor control 0
Sensor control 1
Pixel master clock
Pixel input data line 0
Pixel input data line 1
Pixel input data line 2
Pixel input data line 3
Pixel input data line 4
Pixel input data line 5
Pixel input data line 6
Pixel input data line 7
CM-A510 Reference Guide
Availability
Always available.
Configuration
Group
Camera
28
Peripheral Interfaces
4.14
I 2C
The CM-A510 features up to three general-purpose I2C interfaces. The following features are
supported:
·
·
Master / slave operation
Standard mode (up to 100K bits/s)
For additional details, please refer to section 25 of “88AP510 Functional Specifications”.
NOTE: I2C signals are multiplexed with signals used for other interfaces. For multiplexing
characteristics, please refer to section 5.5 of this document.
NOTE: Certain I2C signals can only be configured on a group basis. Only the entire group may
be assigned with a specific function. Individual signals cannot be configured separately
for different functions.
Table 24
2
I C signals
Signal Name
Pin #
Type
Description
Availability
Configuration
Group
I2C-0
I2C0_SDA
P2-25
IOD
I2C0_SCL
P2-27
IOD
I2C serial data line. Open drain
buffer. Pulled up to 3.3V
I2C serial clock line. Open
drain buffer. Pulled up to 3.3V
Always available.
Not configurable.
Dedicated to I2C.
Always available.
Each pin is
configured
separately.
Always available.
Digital Audio
I2C-1
I2C1_SDA
I2C1_SCL
P1-70
P1-61
IOD
IOD
I2C serial data line. Open drain
buffer. Pulled up to 3.3V
I2C serial clock line. Open
drain buffer. Pulled up to 3.3V
I2C-2
I2C2_SDA
P2-51
IOD
I2C2_SCL
P2-41
IOD
Revised November 2010
I2C serial data line. Open drain
buffer. Pulled up to 3.3V
I2C serial clock line. Open
drain buffer. Pulled up to 3.3V
CM-A510 Reference Guide
29
Peripheral Interfaces
4.15
SPI
The CM-A510 features an SPI interface implemented with the Armada 510 SPI controller.
For additional details, please refer to section 24 of “88AP510 Functional Specifications”.
NOTE: SPI signals are multiplexed with signals used for other interfaces. For multiplexing
characteristics, please refer to section 5.5 of this document.
Table 25
SPI signals
Signal Name
SPI1_CLK
SPI1_CS
SPI1_MISO
SPI1_MOSI
4.16
Pin #
Type
P1-71
P1-65
P1-63
P1-69
O
O
I
O
Description
SPI clock
SPI chip select
SPI data input
SPI data output
Availability
Configuration
Group
Only available
without the ‘I’
configuration
option.
Each pin is
configured
separately.
SSP
The CM-A510 features an SSP interface implemented with the Armada 510 SSP controller. The
interface supports the following features:
·
·
·
·
Compliant with Texas Instruments’ Synchronous Serial Protocol
Programmable data sample sizes of 8, 16, 18 and 32-bits
Up to 24MHz serial clock rate
Master and slave operation modes
For additional details, please refer to section 27 of “88AP510 Functional Specifications”.
NOTE: SSP signals are multiplexed with signals used for other interfaces. For multiplexing
characteristics, please refer to section 5.5 of this document.
Table 26
SSP signals
Signal Name
SSP_SFRM
SSP_RXD
SSP_TXD
SSP_SCLK
Revised November 2010
Pin #
Type
P1-65
P1-64
P1-69
P1-71
IO
I
O
IO
Description
Serial frame indicator
Serial receive data
Serial transmit data
Serial clock
CM-A510 Reference Guide
Availability
Only available
without the ‘I’
configuration
option.
Configuration
Group
Each pin is
configured
separately.
30
Peripheral Interfaces
4.17
JTAG
The CM-A510 JTAG interface is derived from the Armada 510 SoC JTAG port.
The Armada 510 target debug interface uses the five standard IEEE 1149.1 (JTAG) signals (nTRST,
TCK, TMS, TDI and TDO).
For additional details, please refer to section 8 of “88AP510 Hardware Specifications”.
Table 27
JTAG signals
Signal Name
JTAG_CLK
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_nTRST
Revised November 2010
Pin #
Type
P2-90
P2-94
P2-92
P2-96
P2-88
I
O
I
IO
I
Description
Test clock
Test data output
Test data input
Test mode select
Test logic reset
CM-A510 Reference Guide
31
System Logic
5
SYSTEM LOGIC
5.1
Power Management
5.1.1
Power Rails
The CM-A510 is powered by a single 5V power rail.
Table 28
Power signals
Signal Name
5.1.2
Type
Description
VIN_5V
P
VCC_RTC
P
GND
P
Main power supply. Typical voltage – 5V.
RTC back-up battery power input. Connect to a 3V coin-cell lithium
battery. Leave unconnected if RTC back-up is not required.
Common ground.
Low Power Mode
To be added in a future revision of this document.
5.2
Reset
The nRST_IN signal is the main system reset that invokes a global reset that affects every module on
the CM-A510.
The SYSRST_nOUT is a dedicated system reset out signal that can be used to reset baseboard
peripheral devices. SYSRST_nOUT is asserted low for 20ms on power-on-reset and nRST_IN deassertion.
Table 29
Reset signals
Signal Name
nRST_IN
SYSRST_nOUT
5.3
Pin #
Type
P2-33
P2-20
IPU
O
Description
Main system reset input. Pulled up to 3.3V
System reset output. Leave disconnected if not used.
Boot Options
The CM-A510 supports the following boot options:
·
·
Boot from onboard SPI NOR flash
Boot from external hard drive connected to the SATA interface
The boot device is selected with the BOOT_SOURCE signal. The standard boot option is designed
for normal system operation with the on-board SPI NOR flash acting as the boot media. The alternate
boot option is intended mainly for system debug and production. It can also be used for normal
operation with an external SATA hard drive acting as the boot media.
Table 30
Boot option
Standard
Alternate
Revised November 2010
Boot options
BOOT_SOURCE signal input
Unconnected.
Pulled to 3.3V with 1k resistance.
CM-A510 Reference Guide
Boot device
On-board flash
External SATA hard drive
32
System Logic
Table 31
Boot selection signals
Signal Name
BOOT_SOURCE
5.4
Type
Description
P2-117
I
Boot selection. Pulled down with 8.2k. Leave disconnected for
standard boot sequence.
System and Miscellaneous Signals
Table 32
System signals
Signal Name
FLASH_nWP
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
5.5
Pin #
Pin #
Type
P2-46
P2-35
P2-37
P2-39
P2-119
P2-121
P2-28
P2-30
P2-32
P2-34
I
I
O
I
I
I
-
Description
SPI NOR flash write protection. Active low.
Reserved for future use. Leave unconnected.
Reserved for future use. Leave unconnected.
Reserved for future use. Leave unconnected.
Reserved for future use. Leave unconnected.
Reserved for future use. Leave unconnected.
Reserved for debug and production. Leave unconnected.
Reserved for debug and production. Leave unconnected.
Reserved for debug and production. Leave unconnected.
Reserved for debug and production. Leave unconnected.
Signal Multiplexing Characteristics
Armada 510 pins have up to six alternate function modes. The table below provides a description of
signal multiplexing. Function names marked with gray shading denote the default function intended
in the CM-A510 design.
NOTE: Certain software-configurable multi-purpose signals can only be configured on a group
basis. Only the entire group may be assigned with a specific function. Signals within a
group cannot be configured separately for different functions.
Table 33
Pin #
P1-40
P1-42
P1-44
P1-45
P1-46
P1-47
P1-48
P1-49
P1-51
P1-52
P1-53
P1-54
P1-56
P1-57
P1-61
P1-63
P1-64
P1-65
P1-66
P1-68
P1-69
P1-70
P1-71
Signal multiplexing
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
GPIO24
GPIO25
GPIO26
GPIO29
GPIO27
GPIO30
GPIO28
GPIO31
GPIO33
GPIO32
GPIO34
GPIO38
GPIO39
GPIO35
GPIO19
GPIO20
GPIO14
GPIO21
GPIO15
GPIO16
GPIO22
GPIO17
GPIO23
CAM_D0
CAM_D1
CAM_D2
CAM_D5
CAM_D3
CAM_D6
CAM_D4
CAM_D7
CAM_HSYNC
CAM_MCLK
CAM_VSYNC
CAM_SNR_CTL0
CAM_SNR_CTL1
CAM_CLK
UART1_RTS
UART1_CTS
-
UART3_RXD
UART2_TXD
UART2_RXD
UART3_RTS
UART3_CTS
-
SD1_CD
SD1_WP
SD0_CD
SD1_PWREN
SD0_WP
-
I2C1_SCK
SD1_PWREN
SSP_SFRM
SSP_TXD
I2C1_SDA
SSP_SCLK
SD0_CD
SSP_RXD
SD0_WP
SD0_PWREN
-
SPI1_MISO
SPI1_CS
SPI1_MOSI
SPI1_CLK
Revised November 2010
CM-A510 Reference Guide
33
Config.
Group
Camera
None
None
None
None
None
None
None
None
None
System Logic
Pin #
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Config.
Group
P1-72
P1-112
P1-114
P2-41
P2-45
P2-47
P2-49
P2-51
P2-53
P2-54
P2-56
P2-58
P2-60
P2-61
P2-63
P2-65
P2-69
P2-73
P2-75
P2-76
P2-78
GPIO18
GPIO62
GPIO63
GPIO57
GPIO53
GPIO52
GPIO55
GPIO56
GPIO54
GPIO42
GPIO43
GPIO44
GPIO45
GPIO48
GPIO49
GPIO50
GPIO51
GPIO46
GPIO47
GPIO40
GPIO41
UART1_RXD
UART1_TXD
SPDIFO
I2S1_BCLK
I2S1_DI
I2S1_DO
I2S1_LRCLK
I2S1_MCLK
SD0_DATA0
SD0_DATA1
SD0_DATA2
SD0_DATA3
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD1_CLK
SD1_CMD
SD0_CLK
SD0_CMD
UART3_TXD
I2C2_SCK
I2C2_SDA
-
SD0_PWREN
-
-
-
-
None
UART1
5.6
Digital
Audio
SDIO-0
SDIO-1
SDIO-0
RTC
The CM-A510 RTC is implemented with the internal RTC of the Armada 510 SoC. The RTC
provides time and calendar information, timed interrupt generation and alarm wake-up event
functionality.
Additionally, a backup battery can keep the RTC running to maintain clock and time information
even if the main supply is not present. The backup battery should be connected to the VCC_RTC
power input.
For additional details, please refer to section 29 of “88AP510 Functional Specifications”.
5.7
LED
The CM-A510 features a single general purpose green LED controlled by GPIO65 of the Armada 510
SoC. The LED is ON when GPIO65 is set high.
Revised November 2010
CM-A510 Reference Guide
34
Baseboard Interface
6
BASEBOARD INTERFACE
The CM-A510 connects to the baseboard through P1 and P2 - 0.6 mm pitch 140-pin connectors.
6.1
Connector Pin-out
Table 34
Connector P1
Pin #
CM-A510 Signal
Name
P1-1
P1-3
P1-5
P1-7
P1-9
P1-11
P1-13
P1-15
P1-17
P1-19
P1-21
P1-23
P1-25
P1-27
P1-29
P1-31
P1-33
P1-35
P1-37
LAN0_MDIP1
LAN0_MDIN1
LAN0_LED1
VIN_5V
LAN0_MDIP3
LAN0_MDIN3
LAN0_LED2
N.C.
N.C.
VIN_5V
TS_XTS_X+
N.C.
TS_YTS_Y+
VIN_5V
N.C.
N.C.
VCC_RTC
P1-39
N.C.
P1-40
P1-41
N.C.
P1-42
P1-43
VIN_5V
5.1.1
CAM_D5
GPIO29
CAM_D6
GPIO30
CAM_D7
GPIO31
CAM_HSYNC
GPIO33
CAM_VSYNC
GPIO34
4.13
4.12
4.13
4.12
4.13
4.12
4.13
4.12
4.13
4.12
VIN_5V
5.1.1
P1-56
CAM_CLK
GPIO35
N.C.
UART3_RXD
I2C1_SCL
GPIO19
SPI1_MISO
SD0_CD
GPIO20
SPI1_CS
SD0_WP
SSP_SFRM
GPIO21
4.13
4.12
4.8
4.14
4.12
4.15
4.10
4.12
4.15
4.10
4.16
4.12
VIN_5V
5.1.1
P1-45
P1-47
P1-49
P1-51
P1-53
P1-55
P1-57
P1-59
P1-61
P1-63
P1-65
P1-67
Revised November 2010
Reference
Section
Pin #
4.2.1
4.2.1
4.2.1
5.1.1
4.2.1
4.2.1
4.2.1
P1-2
P1-4
P1-6
P1-8
P1-10
P1-12
P1-14
P1-16
P1-18
P1-20
P1-22
P1-24
P1-26
P1-28
P1-30
P1-32
P1-34
P1-36
P1-38
5.1.1
4.11
4.11
4.11
4.11
5.1.1
5.1.1
CM-A510 Signal
Name
Reference
Section
LAN0_MDIP0
LAN0_MDIN0
LAN0_LED0
GND
LAN0_MDIP2
LAN0_MDIN2
GND
N.C.
N.C.
N.C.
N.C.
N.C.
GND
VGA_R
VGA_G
VGA_B
VGA_HSYNC
VGA_VSYNC
GND
CAM_D0
GPIO24
CAM_D1
GPIO25
CAM_D2
GPIO26
CAM_D3
GPIO27
CAM_D4
GPIO28
4.2.1
4.2.1
4.2.1
5.1.1
4.2.1
4.2.1
5.1.1
GND
5.1.1
CAM_MCLK
GPIO32
CAM_SNR_CTL0
GPIO38
CAM_SNR_CTL1
GPIO39
4.13
4.12
4.13
4.12
4.13
4.12
P1-58
CAM_TW_SCK
4.13
P1-60
CAM_TW_SDA
4.13
P1-62
GND
5.1.1
P1-64
UART2_TXD
SSP_RXD
GPIO14
4.8
4.16
4.12
P1-66
UART2_RXD
GPIO15
4.8
4.12
P1-68
UART3_RTS
SD0_CD
GPIO16
4.8
4.10
4.12
P1-44
P1-46
P1-48
P1-50
P1-52
P1-54
CM-A510 Reference Guide
5.1.1
4.1
4.1
4.1
4.1
4.1
5.1.1
4.13
4.12
4.13
4.12
4.13
4.12
4.13
4.12
4.13
4.12
35
Baseboard Interface
Pin #
CM-A510 Signal
Name
P1-73
P1-75
P1-77
P1-79
P1-81
P1-83
P1-85
P1-87
P1-89
P1-91
P1-93
P1-95
P1-97
P1-99
P1-101
P1-103
P1-105
P1-107
P1-109
SPI1_MOSI
SD0_PWREN
SSP_TXD
GPIO22
SPI1_CLK
SSP_SCLK
GPIO23
N.C.
LCD_D0
LCD_D2
VIN_5V
LCD_D4
LCD_D6
LCD_D8
LCD_D9
LCD_D11
VIN_5V
LCD_D14
LCD_D16
LCD_D18
LCD_D19
LCD_D21
VIN_5V
LCD_E
LCD_VSYNC
LCD_HSYNC
P1-111
N.C.
P1-113
N.C.
P1-115
P1-117
P1-119
P1-121
P1-123
P1-125
P1-127
P1-129
P1-131
P1-133
P1-135
P1-137
P1-139
VIN_5V
RS232_RXD
RS232_TXD
RS232_RTS
RS232_CTS
N.C.
VIN_5V
USB2_DN
USB2_DP
USB3_CPEN
USB3_DN
USB3_DP
VIN_5V
P1-69
P1-71
Table 35
Reference
Section
4.15
4.10
4.16
4.12
4.15
4.16
4.12
4.1
4.1
5.1.1
4.1
4.1
4.1
4.1
4.1
5.1.1
4.1
4.1
4.1
4.1
4.1
5.1.1
4.1
4.1
4.1
Pin #
P1-70
P1-72
P1-74
P1-76
P1-78
P1-80
P1-82
P1-84
P1-86
P1-88
P1-90
P1-92
P1-94
P1-96
P1-98
P1-100
P1-102
P1-104
P1-106
P1-108
P1-110
P1-112
P1-114
5.1.1
4.9
4.9
4.9
4.9
5.1.1
4.5
4.5
4.5
4.5
4.5
5.1.1
P1-116
P1-118
P1-120
P1-122
P1-124
P1-126
P1-128
P1-130
P1-132
P1-134
P1-136
P1-138
P1-140
UART3_CTS
SD0_WP
I2C1_SDA
GPIO17
UART3_TXD
SD0_PWREN
GPIO18
GND
LCD_D1
LCD_D3
N.C.
LCD_D5
LCD_D7
GND
LCD_D10
LCD_D12
LCD_D13
LCD_D15
LCD_D17
GND
LCD_D20
LCD_D22
LCD_D23
N.C.
LCD_CLK
GND
UART1_RXD
GPIO62
UART1_TXD
GPIO63
N.C.
N.C.
N.C.
GND
N.C
USB2_CPEN
USB1_CPEN
USB0_DN
USB0_DP
GND
USB1_DN
USB1_DP
N.C
Reference
Section
4.8
4.10
4.14
4.12
4.8
4.10
4.12
5.1.1
4.1
4.1
4.1
4.1
5.1.1
4.1
4.1
4.1
4.1
4.1
5.1.1
4.1
4.1
4.1
4.1
5.1.1
4.8
4.12
4.8
4.12
5.1.1
4.5
4.5
4.5
4.5
5.1.1
4.5
4.5
Connector P2
Pin #
CM-A510 Signal
Name
Reference
Section
Pin
#
P2-1
P2-3
P2-5
P2-7
P2-9
P2-11
P2-13
P2-15
P2-17
P2-19
P2-21
P2-23
P2-25
P2-27
P2-29
P2-31
P2-33
P2-35
LAN1_MDIP1
LAN1_MDIN1
LAN1_LED1
GND
LAN1_MDIP3
LAN1_MDIN3
LAN1_LED2
PCIE1_CLKREQ
PCIE0_CLKREQ
VIN_5V
N.C.
N.C.
I2C0_SDA
I2C0_SCL
N.C.
VIN_5V
nRST_IN
RESERVED
4.2.2
4.2.2
4.2.2
5.1.1
4.2.2
4.2.2
4.2.2
4.3
4.3
5.1.1
P2-2
P2-4
P2-6
P2-8
P2-10
P2-12
P2-14
P2-16
P2-18
P2-20
P2-22
P2-24
P2-26
P2-28
P2-30
P2-32
P2-34
P2-36
Revised November 2010
CM-A510 Signal
Name
4.14
4.14
5.1.1
5.2
5.4
CM-A510 Reference Guide
CM-A510 Signal
Name
LAN1_MDIP0
LAN1_MDIN0
LAN1_LED0
GND
LAN1_MDIP2
LAN1_MDIN2
GND
N.C.
N.C.
SYSRST_OUTn
N.C.
N.C.
GND
RESERVED
RESERVED
RESERVED
RESERVED
N.C.
Reference
Section
4.2.2
4.2.2
4.2.2
5.1.1
4.2.2
4.2.2
5.1.1
5.1.1
5.4
5.4
5.4
5.4
36
Baseboard Interface
Pin #
CM-A510 Signal
Name
Reference
Section
Pin
#
P2-37
P2-39
RESERVED
RESERVED
SPDIF
I2C2_SCL
GPIO57
VIN_5V
I2S1_BCLK
GPIO53
I2S1_SDI
GPIO52
I2S1_SDO
GPIO55
I2S1_LRCLK
I2C2_SDA
GPIO56
I2S1_MCLK
GPIO54
5.4
5.4
4.7.3
4.14
4.12
5.1.1
4.7.2
4.12
4.7.2
4.12
4.7.2
4.12
4.7.2
4.14
4.12
4.7.2
4.12
P2-38
P2-40
GND
N.C.
P2-42
N.C.
P2-44
N.C.
P2-46
FLASH_nWP
P2-48
N.C.
P2-50
N.C.
P2-52
GND
5.1.1
P2-55
VIN_5V
5.1.1
P2-56
P2-57
N.C.
P2-58
P2-59
N.C.
P2-60
SD0_DATA0
GPIO42
SD0_DATA1
GPIO43
SD0_DATA2
GPIO44
SD0_DATA3
GPIO45
4.10
4.12
4.10
4.12
4.10
4.12
4.10
4.12
P2-62
GND
5.1.1
P2-64
N.C.
P2-41
P2-43
P2-45
P2-47
P2-49
P2-51
P2-53
P2-61
P2-63
P2-65
P2-67
P2-69
P2-71
P2-73
P2-75
SD1_DATA0
GPIO48
SD1_DATA1
GPIO49
SD1_DATA2
GPIO50
VIN_5V
SD1_DATA3
GPIO51
N.C.
SD1_CLK
GPIO46
SD1_CMD
GPIO47
P2-77
N.C.
P2-79
P2-81
P2-83
P2-85
P2-87
P2-89
P2-91
P2-93
P2-95
P2-97
P2-99
P2-101
P2-103
P2-105
P2-107
P2-109
P2-111
P2-113
P2-115
P2-117
P2-119
P2-121
P2-123
P2-125
P2-127
P2-129
P2-131
P2-133
VIN_5V
PCIE1_CLK_N
PCIE1_CLK_P
N.C.
N.C.
SYSRST_INn
VIN_5V
N.C.
N.C.
N.C.
PCIE0_CLK_N
PCIE0_CLK_P
VIN_5V
PCIE1_RX_N
PCIE1_RX_P
N.C.
PCIE1_TX_N
PCIE1_TX_P
VIN_5V
BOOT_SCR0
RESERVED
RESERVED
AUDIO_GND
MIC_BIAS
VIN_5V
MIC_IN
AUDIO_IN_R
AUDIO_IN_L
Revised November 2010
4.10
4.12
4.10
4.12
4.10
4.12
5.1.1
4.10
4.12
4.10
4.12
4.10
4.12
P2-54
P2-66
N.C.
P2-68
N.C.
5.2
5.1.1
4.3
4.3
5.1.1
4.3
4.3
4.3
4.3
5.1.1
5.3
5.4
5.4
4.7.1
4.7.1
5.1.1
4.7.1
4.7.1
4.7.1
Reference
Section
5.1.1
5.4
P2-70
N.C.
P2-72
N.C.
P2-74
GND
5.1.1
SD0_CLK
GPIO40
SD0_CMD
GPIO41
N.C.
N.C.
N.C.
GND
JTAG_nTRST
JTAG_CLK
JTAG_TDI
JTAG_TDO
JTAG_TMS
GND
N.C.
N.C.
N.C.
PCIE0_RX_N
PCIE0_RX_P
GND
PCIE0_TX_N
PCIE0_TX_P
N.C.
SATA_RXSATA_RX+
GND
SATA_TXSATA_TX+
N.C.
N.C.
N.C.
GND
4.10
4.12
4.10
4.12
P2-76
P2-78
5.1.1
4.3
4.3
CM-A510 Signal
Name
P2-80
P2-82
P2-84
P2-86
P2-88
P2-90
P2-92
P2-94
P2-96
P2-98
P2-100
P2-102
P2-104
P2-106
P2-108
P2-110
P2-112
P2-114
P2-116
P2-118
P2-120
P2-122
P2-124
P2-126
P2-128
P2-130
P2-132
P2-134
CM-A510 Reference Guide
5.1.1
0
0
0
0
0
5.1.1
4.3
4.3
5.1.1
4.3
4.3
4.4
4.4
5.1.1
4.4
4.4
5.1.1
37
Baseboard Interface
6.2
Pin #
CM-A510 Signal
Name
P2-135
P2-137
P2-139
VIN_5V
AUDIO_OUT_L
AUDIO_OUT_R
Reference
Section
Pin
#
5.1.1
4.7.1
4.7.1
P2-136
P2-138
P2-140
CM-A510 Signal
Name
USB3_nOVC
USB2_nOVC
USB1_nOVC
Reference
Section
4.5
4.5
4.5
Connector Type
Table 36
Connector type
Part Reference
Mfg.
CM-A510 connector P/N
Baseboard (mating) connector P/N
P1, P2
AMP
1-5353183-0
1-5353190-0 or CON140
Mating connectors and standoffs are available from CompuLab, see [prices] >> [accessories] links at
CompuLab's website.
CompuLab's P/N for the AMP 1-5353190-0 connector is "CON140".
6.3
Mechanical Drawings
Figure 3
Revised November 2010
CM-A510 top
CM-A510 Reference Guide
38
Baseboard Interface
Figure 4
CM-A510 bottom (X-Ray view - as seen from top side)
1.
All dimensions are in millimeters.
2.
Height of all components is <3mm.
3.
Baseboard connectors provide 4mm board-to-board clearance.
4.
Board thickness is 1.6mm.
Mechanical drawings are available in DXF format from CompuLab's website, following [Developer]
>> [CM-A510] >> [CM-A510 - Dimensions and Connectors Location] links.
Revised November 2010
CM-A510 Reference Guide
39
Baseboard Interface
6.4
Standoffs
The CM-A510 has four mounting holes for standoffs. Standoffs are implemented with three parts:
screw, spacer and nut.
Table 37
Part
Standoffs
Description
Screw
M2, 10 mm length
Spacer
M2 x 4 thread, 4.2 mm length
Nut
M2, 1.6-2.0mm width
Revised November 2010
Manufacturer and P/N
· FCI 95121-005
· Acton InoxPro BF22102010
· World Bridge Machinery 380J52080
· Hirosugi ASU-2004
· MAC8 2SP-4
· World Bridge Machinery M2, L=4.2 mm
· FCI 92869-001 (or 002)
· Acton InoxPro BG12102000
· Bossard 1241397 (DIN934-A2 M2)
· World Bridge Machinery 381A52000
CM-A510 Reference Guide
40
Operational Characteristics
7 OPERATIONAL CHARACTERISTICS
7.1
Absolute Maximum Ratings
Table 38
7.2
Absolute Maximum ratings
Parameter
Min
Main power supply voltage (VIN_5V)
VCC_RTC
-0.3
-0.3
Max
Unit
6.0
4.0
V
V
Recommended Operating Conditions
Table 39
Recommended Operating Conditions
Parameter
Main power supply voltage (VIN_5V)
RTC backup battery voltage (VCC_RTC)
7.3
Typ
Min
Typ
Max
Unit
4.75
2.2
5.0
3.3
5.25
3.45
V
V
Min
Typ
Max
Unit
3.6
0.8
0.4
V
V
V
V
3.8
1.0
0.4
V
V
V
DC Electrical Characteristics
Table 40
DC Electrical Characteristics
Parameter
Operating Conditions
3.3V Digital I/O
VIH
VIL
VOH
VOL
2
-0.3
2.4
2
I C (open drain with internal pull up to 3.3V)
VIH
VIL
VOL
2.3
-0.5
-
IOL = 3 mA
IRS232
TX Voltage Swing
RX Voltage Swing
7.4
±5
±5.4
±25
V
V
Power Consumption
To be added in a future revision of this document.
7.5
ESD Performance
Table 41
ESD Performance
Interface
USB host
RS232
Revised November 2010
ESD Performance
±8 kV ESD using HBM
±15 kV ESD using HBM
CM-A510 Reference Guide
41
Operational Characteristics
7.6
Thermal Characteristics
Power dissipation characteristics vary depending on Armada SoC operating frequency and average
workload.
Table 42
SoC operating
frequency
1GHz
800MHz
Thermal Characteristics
Operational
workload
Full
Idle
Full
Idle
Thermal conditions
ΔT between SoC case and
ambient temperature
Operating in open-air, no heat-plate.
Ambient temperature - 25°C.
60°C
45°C
45°C
35°C
When ambient temperature exceeds 35°C or when ΔT > 45°C, the CM-A510 should be provided with
a heat dissipation solution. The following solutions may be used:
·
·
·
7.7
Heat-plate supplied by CompuLab. For further details, please refer to section 8.4 of this
document.
Heat extruder integrated into customer designed enclosure
Enforced airflow
Operating Temperature Ranges
The CM-A510 is available with three options of operating temperature range.
Table 43
CM-A510 Temperature Range Options
Range
Temp.
Commercial
0o to 70o C
Extended
-20o to 70o C
Industrial
-40o to 85o C
Revised November 2010
Description
Sample boards from each batch are tested for the lower and upper
temperature limits. Individual boards are not tested.
Every board undergoes a short test for the lower limit (-20o C)
qualification.
Every board is extensively tested for both lower and upper limits
and at several midpoints.
CM-A510 Reference Guide
42
Application Notes
8
APPLICATION NOTES
8.1
Baseboard Design Guidelines
·
·
·
·
·
·
·
Ensure that all VIN_5V and GND power pins are connected.
Major power rails - VIN_5V and GND must be implemented by planes, rather than traces.
Using at least two planes is essential to ensure the system's signal quality, because the planes
provide a current return path for all interface signals.
It is recommended to put several 100nF and 10/100uF capacitors between VIN_5V and GND
near the mating connectors.
It is recommended to connect the standoff holes of the baseboard to GND, in order to
improve EMC.
Except for a power connection, no other connection is mandatory for CM-A510 operation.
All power-up circuitry and all required pull-ups/pull-downs are present on the module.
If for some reason you decide to place an external pull-up or pull-down resistor on a certain
signal (for example - on the GPIO's), first check the documentation of that signal provided in
this manual. Certain signals have on-board pull-up/pull-down resistors required for proper
initialization. Overriding their values by external components will disable board operation.
You must be familiar with signal interconnection design rules. There are many sensitive
groups of signals. For example:
· PCI Express, SATA, Ethernet and USB signals must be routed in differential pairs and by
a controlled impedance trace.
·
·
8.2
· Audio input must be decoupled from possible sources of baseboard noise.
Be careful when placing components under the CM-A510 module. The baseboard interface
connector provides 4mm mating height. Bear in mind that there are components on the
underside of the CM-A510. Maximum allowable height for components placed under the
CM-A510 is 1mm.
Refer to the SB-A510 baseboard reference design schematics.
Baseboard Troubleshooting
·
·
·
·
·
Using grease solvent and a soft brush, clean the contacts of the mating connectors of both the
module and the baseboard. Remnants of soldering paste can prevent proper contact. Take care
to let the connectors and the module dry entirely before re-applying power – otherwise
corrosion may occur.
Using an oscilloscope, check the voltage levels and quality of the VIN_5V power supply. It
should be as specified in section 7.2. Check that there is no excessive ripple or glitches. First
perform the measurements without plugging in the module. Then plug in the module and
measure again. Measurement should be performed on the pins of the mating connector.
Using an oscilloscope, verify that the GND pins of the mating connector are indeed at zero
voltage level and that there is no ground bouncing. The module must be plugged in during the
test.
Create a "minimum system" - only power, mating connectors, the module and a serial
interface.
Check if the system starts properly. In system larger than the minimum, possible sources of
disturbance could be:
· Devices improperly driving the local bus
Revised November 2010
CM-A510 Reference Guide
43
Application Notes
· External pull-up/pull-down resistors overriding the module’s on-board values, or any
other component creating the same "overriding" effect
·
·
·
·
·
· Faulty power supply
In order to avoid possible sources of disturbance, it is strongly recommended to start with a
minimal system and then to add/activate off-board devices one by one.
Check for the existence of soldering shorts between pins of mating connectors. Even if the
signals are not used on the baseboard, shorting them on the connectors can disable the
module. An initial check can be performed using a microscope. However, if microscope
inspection finds nothing, it is advisable to check using an X-ray, because often, solder bridges
are deep beneath the connector's body. Note that solder shorts are the most frequent factor
disabling module operation.
Check possible signal shorts due to errors of baseboard PCB design or assembly.
Improper functioning of a custom baseboard can accidentally delete the CM-A510 boot-up
code or even damage the module hardware permanently. Before each activation attempt,
check that your module is still functional with a CompuLab SB-A510 baseboard.
It is recommended to assemble more than one baseboard for prototyping, in order to ease
resolution of problems related to specific board assembly.
8.3
Ethernet Magnetics’ Implementation
8.3.1
Magnetics’ Selection
Refer to the table below for compatible magnetic modules. Designers should test and qualify
magnetic modules before using them in an application.
Table 44
Compatible Magnetics
Vendor
UDE
Speed Tech
Pulse Engineering
Pulse Engineering
8.3.2
P/N
RB1-125BAK1A
P65-101-[1|2]AK9
H5007
H1251
Package
Integrated RJ45
Integrated RJ45
16-pin SOIC
16-pin SOIC
Magnetics’ Connection
For magnetic modules connection, please refer to the SB-A510 reference design schematics.
8.4
Heat-plate Integration
To be added in a future revision of this document.
Revised November 2010
CM-A510 Reference Guide
44
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising