173 Boronia Rd, Boronia, (PO Box 30), Victoria, 3155, Australia
Phone: +61 3 9762 3588
Fax: +61 3 9762 5499
email: [email protected]
AVR570 plug-in Atmel RISC CPU module
The AVR570 is a 47mm square module providing potential users of the ATmega128 with a method of using the
most powerful CPU in the 8-bit Atmel range without
needing expensive surface mount design, masking, pickand-place machine programming and production runs to
justify it.
Instead, users can simply lay out a square pad layout for
four, 16-pin 0.1” spaced strip connectors (with 0.025”
square pins, i.e. 0.9mm holes) and have a plug-in module
which is mass-produced by JED and programmed by users using the on-board ISP (In System Programming) connector either stand-alone in a test jig or installed in the final board.
During the debug phase, users can connect the low-cost
Atmel JTAG ICE (In Circuit Emulator) to an optional 10pin socket and debug systems in their final environment,
with all I/O active.
AVR570 CPU module,
High speed RISC CPU with 128K highsecurity FLASH program memory, 4K Byte
of SRAM, 4K Byte of EEPROM;
Module is 47mm square, and uses standard 0.1” spaced connectors on four sides
to connect to user-designed base-board
or JED AVR572 prototype or AVR573 base
Two UART interfaces, available on pins at
CMOS levels, available for RS232, RS485,
Standard functions of the AVR570
On-board reset/power fail detector;
The AVR570 has the close CPU functions provided,
i.e. the crystal for the CPU clock and the power-fail detector/reset generator.
The crystal is on the module, but the pins for the oscillator are still available for external connection offmodule, but via Links 2 and 3 which much be bridged before external use via pins 23 and 24. Normally a 3.6864
MHz crystal is installed, but special requests can be accommodated. (The ATmega128 can run at up to 16 MHz.)
On-board optional 5 volt regulator;
On-board 6-pin ISP programming port and
10-pin JTAG ICE connector;
On-board RESET switch and on-board
Physically and electrically compatible with
ATmega103 CPU module from Olimex Ltd,
but uses newer, more powerful ATmega128 with improved 133 instruction set,
dual UARTs, hardware I2C system and ICE
debug system;
Optional Real Time Clock (DS1305) via SPI
using port G pins for interface, with onboard lithium battery behind board.
While external connection of the clock is possible, the
longer lines for the crystal oscillator pins down to the base
board would be a probable source of radio frequency radiation and is NOT recommended practice. An external
clock could be fed to the CPU via these pins to XTAL1 via
Pin 24. The CPU oscillator output can also be used for off-
Designed and manufactured
in Australia by an Australianowned company.
JED AVR570 ATmega128 CPU Module (Release April 14th, 2003)
module functions, but if this is done, the oscillator power level should be set to CKOPT
ON. If the signal is not used externally, the
oscillator should be set to CKOPT OFF to
reduce RF radiation from the module.
There is a DS1233 CPU Reset generator
on the AVR570 to detect power supply
drops and reset the CPU. It also delays CPU
start-up until after the oscillator starts and
the CPU stabilises. A small slider switch
(SW2) across the RESET line can be used to
reset the CPU when desired during testing.
In-System Programming Port
Connector J2 is a 6-pin male ISP header
on the board for programming the FLASH
memory and the EEPROM memory in the
ATmega128 CPU. This connector is compatible with the Atmel STK500 prototype
board, connector J200.
It is also compatible with programming
devices from PC parallel and serial ports
available from JED, Kanda and Atmel. (A
simple cable scrambler can convert the earlier 10-pin standard to this 6-pin standard.
The signals are electrically identical.)
A small slide switch (SW1) is closed in
the RUN mode, but opened in programming
mode, to isolate any base-board serial devices from the RX0 line into the CPU.
AVR570 ATmega128 CPU module with optional Real Time Clock
This function is provided via 10-pin connector J3.
A cable from here connects to the Atmel JTAG ICE.
The JTAG interface is a 4-wire Test Access Port (TAP)
using the top 4 analog input pins ADC4 ... ADC7 and provides full device FLASH and EEPROM memory programming and on-chip debugging support, allowing realtime emulation of the micro controller while running in
the target system. It gives the user complete control of the
internal resources of the AVR CPU.
Its use reduces the number of analog channels available
during testing. This connector is across the four lines
mentioned, and even if the connector is installed, the analog lines are available on the edge connectors pins 54 ...
57. User’s should not drive these analog data lines while
JTAG ICE is in use. A convenient way might be to have
series resistors which are removed during debug.
SPI functions on their base board. User hardware should
enable the SPI functions for SPI peripherals as needed and
disable the CE or CE* pins on their SPI devices when not
in use so the RTC can use the SPI port when it needs to.
The CE pin (high true) enable for the RTC to use the SPI
port is actually pin 18 of the CPU, which is Port pin PG3.
Link 8 must be linked to connect PG3 to the RTC CE.
(The RTC CE pin is pulled low by a resistor so the RTC
communications is inactive during device programming
and before the port G is enabled as an output and set low.)
A FET is installed with this option in parallel with the
alarm output of the RTC, and this is driven from CPU pin
19, Port pin PG4. This allows the CPU to force the Alarm*
output low (active) on edge pin 18 and so allow alarms to
be set for some future time while the CPU is kept active,
and power is then turned OFF by taking Port pin PG4
LOW. This FET’s gate is also pulled low by a resistor
when PG4 is not initialised.
Option: DS1305 Real-Time-Clock
Option: 5 volt power supply regulator
An optional RTC can be supplied, installed on the
AVR570, along with its associated 32,768 Hz crystal. The
alarm output of the RTC can be connected (via link 5) to
pin edge pin 18, and then on the base board, an inversion
FET can drive the gate of series power P- FET. This is to
enable systems to be built which automatically power up
under control of the alarm system in the RTC.
The RTC uses the Serial Peripheral Interface (SPI) port
on the ATmega128 CPU port pins PB1, PB2 and PB3, and
if the RTC is used, users should reserve these port pins for
To maintain compatibility with the Olimex ATmega103 card, there is provision for an optional 5 volt regulator on the AVR570. This is not recommended unless a
very small system is being built, as the off-board logic
should be run from the same 5-volt power supply as the
CPU, and the TO92 packaged device has only limited dissipation. A 78L05 or a low dropout device can be used.
If used, Link 1 should be connected, and Vcc is available to the base board via pins 21 and 52.
If not used, Vcc is fed to the module via pins 21 and 52.
Option: JTAG In Circuit Emulation (ICE)
JED AVR570 ATmega128 CPU Module (Release April 14th, 2003)
Pin Number
Pin Name
Pin Number
Pin Name
Pin 1
CPU-Pin1: PEN*
Pin 33
CPU-Pin 33: WR*/PG0
Pin 2
CPU-Pin 2: PE0 via SW1/RXD0
Pin 34
CPU-Pin 34: RD*/PG1
Pin 3
CPU-Pin 3: PE1/TXD0
Pin 35
CPU-Pin 35: PC0/A8
Pin 4
CPU-Pin 4: PE2/XCK0
Pin 36
CPU-Pin 36: PC1/A9
Pin 5
CPU-Pin 5: PE3/OC3A
Pin 37
CPU-Pin 37: PC2/A10
Pin 6
CPU-Pin 6: PE4/OC3B
Pin 38
CPU-Pin 38: PC3/A11
Pin 7
CPU-Pin 7: PE5/OC3C
Pin 39
CPU-Pin 39: PC4/A12
Pin 8
CPU-Pin 8: PE6/T3/INT6
Pin 40
CPU-Pin 40: PC5/A13
Pin 9
CPU-Pin 9: PE7/IC3/INT7
Pin 41
CPU-Pin 41: PC6/A14
Pin 10
CPU-Pin 10: PB0/SS*
Pin 42
CPU-Pin 42: PC7/A15
Pin 11
CPU-Pin 11: PB1/SCK
Pin 43
CPU-Pin 43: ALE/PG2
Pin 12
CPU-Pin 12: PB2/MOSI
Pin 44
CPU-Pin 44: PA7/AD7
Pin 13
CPU-Pin 13: PB3/MISO
Pin 45
CPU-Pin 45: PA6/AD6
Pin 14
CPU-Pin 14: PB4/OC0
Pin 46
CPU-Pin 46: PA5/AD5
Pin 15
CPU-Pin 15: PB5/OC1A
Pin 47
CPU-Pin 47: PA4/AD4
Pin 16
CPU-Pin 16: PB6/OC1B
Pin 48
CPU-Pin 48: PA3/AD3
Pin 17
CPU-Pin 17: PB7/OC1C
Pin 49
CPU-Pin 49: PA2/AD2
Pin 18
CPU-Pin 18:PG3/RTC
Int0 out for alarm
Pin 50
CPU-Pin 50: PA1/AD1
Pin 51
CPU-Pin 51: PA0/AD0
Pin 19
CPU-Pin 19: PG4/Batt.
Pin 52
CPU-Pin 52: VCC
Pin 20
CPU-Pin 20: RESET*
Pin 53
CPU-Pin 53: GND
Pin 21
CPU-Pin 21: Vcc
Pin 54
CPU-Pin 54: PF7/ADC7
Pin 22
CPU-Pin 22: Ground
Pin 55
CPU-Pin 55: PF6/ADC6
Pin 23
CPU-Pin 23: X2/nc
Pin 56
CPU-Pin 56: PF5/ADC5
Pin 24
CPU-Pin 24: X1/nc
Pin 57
CPU-Pin 57: PF4/ADC4
Pin 25
CPU-Pin 25: PD0/SCL/INT0*
Pin 58
CPU-Pin 58: PF3/ADC3
Pin 26
CPU-Pin 26: PD1/SDA/INT1*
Pin 59
CPU-Pin 59: PF2/ADC2
Pin 27
CPU-Pin 27: PD2/RXD1/INT2*
Pin 60
CPU-Pin 60: PF1/ADC1
Pin 28
CPU-Pin 28: PD3/TXD1/INT3*
Pin 61
CPU-Pin 61: PF0/ADC0
Pin 29
CPU-Pin 29: PD4/IC1
Pin 62
CPU-Pin 62: AREF
Pin 30
CPU-Pin 30: PD5/XCK1
Pin 63
CPU-Pin 63: AGND
Pin 31
CPU-Pin 31: PD6/T1
Pin 64
CPU-Pin 64: AVCC
Pin 32
CPU-Pin 32: PD7/T2
JED AVR570 ATmega128 CPU Module (Release April 14th, 2003)
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JED AVR570 ATmega128 CPU Module (Release April 14th, 2003)
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