EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller ®

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

EZ-USB

®

FX2LP™ USB Microcontroller

High-Speed USB Peripheral Controller

EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller

Features

■

USB 2.0 USB IF Hi-Speed certified (TID # 40460272)

■

Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor

■

Fit-, form-, and function-compatible with the FX2

❐

❐

❐

Pin-compatible0

Object-code-compatible

Functionally compatible (FX2LP is a superset)

■ Ultra-low power: I

CC

no more than 85 mA in any mode

❐ Ideal for bus- and battery-powered applications

■

Software: 8051 code runs from:

❐

❐

❐

Internal RAM, which is downloaded through USB

Internal RAM, which is loaded from EEPROM

External memory device (128-pin package)

■ 16 KB of on-chip code/data RAM

■ Four programmable BULK, INTERRUPT, and

ISOCHRONOUS endpoints

❐ Buffering options: Double, triple, and quad

■

Additional programmable (BULK/INTERRUPT) 64-byte endpoint

■

8-bit or 16-bit external data interface

■

Smart media standard ECC generation

■

GPIF™ (general programmable interface)

❐

❐

Enables direct connection to most parallel interfaces

Programmable waveform descriptors and configuration registers to define waveforms

❐ Supports multiple ready (RDY) inputs and control (CTL) outputs

■ Integrated, industry-standard, enhanced 8051

❐

❐

❐

❐

❐

❐

48-MHz, 24-MHz, or 12-MHz CPU operation

Four clocks per instruction cycle

Two USARTs

Three counter/timers

Expanded interrupt system

Two data pointers

■

3.3-V operation with 5-V tolerant inputs

■

Vectored USB interrupts and GPIF/FIFO interrupts

■

Separate data buffers for the setup and data portions of a

CONTROL transfer

■

Integrated I

2

C controller; runs at 100 or 400 kHz

■

Four integrated FIFOs

❐

❐

❐

❐

❐

Integrated glue logic and FIFOs lower system cost

Automatic conversion to and from 16-bit buses

Master or slave operation

Uses external clock or asynchronous strobes

Easy interface to ASIC and DSP ICs

■ Available in commercial and industrial temperature grades

(all packages except VFBGA)

Features (CY7C68013A/14A only)

■

CY7C68014A: Ideal for battery-powered applications

❐

Suspend current: 100

A (typ)

■ CY7C68013A: Ideal for nonbattery-powered applications

❐ Suspend current: 300

A (typ)

■

Available in five Pb-free packages with up to 40 GPIOs

❐

128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin

QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin

VFBGA (24 GPIOs)

Features (CY7C68015A/16A only)

■

CY7C68016A: Ideal for battery-powered applications

❐

Suspend current: 100

A (typ)

■ CY7C68015A: Ideal for nonbattery-powered applications

❐ Suspend current: 300

A (typ)

■

Available in Pb-free 56-pin QFN package (26 GPIOs)

■

Two more GPIOs than CY7C68013A/14A enabling additional features in the same footprint

For a complete list of related resources, click here .

Errata: For information on silicon errata, see

“Errata” on page 67. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

• 198 Champion Court

Document Number: 38-08032 Rev. *X

• San Jose

,

CA 95134-1709 • 408-943-2600

Revised January 15, 2015

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

More Information

Cypress provides a wealth of data at www.cypress.com

to help you to select the right device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the application note AN65209 - Getting

Started with FX2LP .

■

■

Overview: USB Portfolio , USB Roadmap

USB 2.0 Product Selectors: FX2LP , AT2LP , NX2LP-Flex , SX2

■ Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with FX2LP are:

❐

❐

AN65209 - Getting Started with FX2LP

AN15456 - Guide to Successful EZ-USB® FX2LP™ and

EZ-USB FX1™ Hardware Design and Debug

❐

❐

❐

❐

❐

AN50963 - EZ-USB® FX1™/FX2LP™ Boot Options

AN66806

AN61345

AN57322

- EZ-USB® FX2LP™ GPIF Design Guide

- Implementing an FX2LP™- FPGA Interface

- Interfacing SRAM with FX2LP over GPIF

AN4053 - Streaming Data through Isochronous/Bulk Endpoints on EZ-USB® FX2 and EZUSB FX2LP

❐ AN63787 - EZ-USB® FX2LP™ GPIF and Slave FIFO Configuration Examples using 8-bit Asynchronous Interface

For complete list of Application notes, click here .

EZ-USB FX2LP Development Kit

The CY3684 EZ-USB FX2LP Development Kit is a complete development resource for FX2LP. It provides a platform to develop and test custom projects using FX2LP. The development kit contains collateral materials for the firmware, hardware, and software aspects of a design using FX2LP.

GPIF™ Designer

FX2LP™ General Programmable Interface (GPIF) provides an independent hardware unit, which creates the data and control signals required by an external interface. FX2LP GPIF Designer allows users to create and modify GPIF waveform descriptors for

EZ-USB FX2/ FX2LP family of chips using a graphical user interface. Extensive discussion of general GPIF discussion and programming using GPIF Designer is included in

FX2LP

Technical Reference Manual

and GPIF Designer User Guide, distributed with GPIF Designer.

AN66806 - Getting Started with

EZ-USB

®

FX2LP™ GPIF can be a good starting point.

■ Code Examples:

❐ USB Hi-Speed

■ Technical Reference Manual (TRM):

❐ EZ-USB FX2LP Technical Reference Manual

■ Reference Designs:

❐ CY4661 - External USB Hard Disk Drives (HDD) with Fingerprint Authentication Security

❐ FX2LP DMB-T/H TV Dongle reference design

■ Models: IBIS

Document Number: 38-08032 Rev. *X Page 2 of 71

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Logic Block Diagram

24 MHz

Ext. XTAL

FX2LP

High-performance micro using standard tools with lower-power options

D+

Integrated full speed and high speed

XCVR

D–

VCC x20

PLL

/0.5

/1.0

/2.0

1.5k

connected for full speed

USB

2.0

XCVR

CY

Smart

USB

1.1/2.0

Engine

8051 Core

12/24/48 MHz, four clocks/cycle

16 KB

RAM

ECC

I

2

C

Master

Additional I/Os (24)

ADDR (9)

GPIF

RDY (6)

CTL (6)

4 kB

FIFO

8/16

Abundant I/O including two USARTs

General programmable I/F to ASIC/DSP or bus standards such as

ATAPI, EPP, etc.

Up to 96 MBytes/s burst rate

Enhanced USB core

Simplifies 8051 code

“Soft Configuration”

Easy firmware changes

FIFO and endpoint memory

(master or slave operation)

Cypress’s EZ-USB

®

FX2LP

 (CY7C68013A/14A) is a low-power version of the EZ-USB FX2

(CY7C68013), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a cost-effective solution that provides superior time-to-market advantages with low power to enable bus-powered applications.

The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second (the maximum allowable

USB 2.0 bandwidth), while still using a low-cost 8051 microcontroller in a package as small as a 56 VFBGA (5 mm x

5 mm). Because it incorporates the USB 2.0 transceiver, the

FX2LP is more economical, providing a smaller-footprint solution than a USB 2.0 SIE or external transceiver implementations.

With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing the development time to ensure USB compatibility.

The general programmable interface (GPIF) and Master/Slave

Endpoint FIFO (8-bit or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as ATA, UTOPIA,

EPP, PCMCIA, and most DSP/processors.

The FX2LP draws less current than the FX2 (CY7C68013), has double the on-chip code/data RAM, and is fit, form, and function compatible with the 56-, 100-, and 128-pin FX2.

Five packages are defined for the family: 56 VFBGA, 56 SSOP,

56 QFN, 100 TQFP, and 128 TQFP.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Contents

Applications ...................................................................... 5

Functional Overview ........................................................ 5

USB Signaling Speed .................................................. 5

8051 Microprocessor ................................................... 5

I

2

C Bus ........................................................................ 5

Buses .......................................................................... 5

USB Boot Methods ...................................................... 6

ReNumeration ............................................................. 6

Bus-Powered Applications .......................................... 6

Interrupt System .......................................................... 6

Reset and Wakeup ...................................................... 9

Program/Data RAM ................................................... 10

Register Addresses ................................................... 11

Endpoint RAM ........................................................... 12

External FIFO Interface ............................................. 13

GPIF .......................................................................... 14

ECC Generation

[8]

..................................................... 14

USB Uploads and Downloads ................................... 14

Autopointer Access ................................................... 14

I

2

C Controller ............................................................. 15

Compatible with Previous Generation

EZ-USB FX2 .............................................................. 15

CY7C68013A/14A and CY7C68015A/16A

Differences ................................................................ 15

Pin Assignments ............................................................ 16

CY7C68013A/15A Pin Descriptions .......................... 23

Register Summary .......................................................... 31

Absolute Maximum Ratings .......................................... 39

Operating Conditions ..................................................... 39

Thermal Characteristics ................................................. 39

DC Characteristics ......................................................... 40

USB Transceiver ....................................................... 40

AC Electrical Characteristics ........................................ 41

USB Transceiver ....................................................... 41

Program Memory Read ............................................. 41

Data Memory Read

................................................... 42

Data Memory Write ................................................... 43

PORTC Strobe Feature Timings ............................... 44

GPIF Synchronous Signals ....................................... 45

Slave FIFO Synchronous Read ................................. 46

Slave FIFO Asynchronous Read ............................... 47

Slave FIFO Synchronous Write ................................. 48

Slave FIFO Asynchronous Write ............................... 49

Slave FIFO Synchronous Packet End Strobe ........... 49

Slave FIFO Asynchronous Packet End Strobe ......... 50

Slave FIFO Output Enable ........................................ 51

Slave FIFO Address to Flags/Data ............................ 51

Slave FIFO Synchronous Address ............................ 51

Slave FIFO Asynchronous Address .......................... 52

Sequence Diagram .................................................... 52

Ordering Information ...................................................... 57

Ordering Code Definitions ......................................... 57

Package Diagrams .......................................................... 59

PCB Layout Recommendations .................................... 64

Quad Flat Package No Leads (QFN)

Package Design Notes ................................................... 65

Acronyms ........................................................................ 66

Document Conventions ................................................. 66

Errata ............................................................................... 67

Part Numbers Affected .............................................. 67

CY7C68013A/14A/15A/16A Qualification Status ...... 67

CY7C68013A/14A/15A/16A Errata Summary ........... 67

Document History Page ................................................. 68

Sales, Solutions, and Legal Information ...................... 71

Worldwide Sales and Design Support ....................... 71

Products .................................................................... 71

PSoC® Solutions ...................................................... 71

Cypress Developer Community ................................. 71

Technical Support ..................................................... 71


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

1. Applications

■ Portable video recorder

■ MPEG/TV conversion

■ DSL modems

■ ATA interface

■ Memory card readers

■ Legacy conversion devices

■ Cameras

■ Scanners

■ Wireless LAN

■ MP3 players

■ Networking

The “Reference Designs” section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Visit www.cypress.com

for more information.

2. Functional Overview

2.1 USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB

Specification Revision 2.0, dated April 27, 2000:

■ Full speed, with a signaling bit rate of 12 Mbps

■ High speed, with a signaling bit rate of 480 Mbps

FX2LP does not support the Low Speed signaling mode of

1.5 Mbps.

2.2 8051 Microprocessor

The 8051 microprocessor embedded in the FX2LP family has

256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs.

2.2.1 8051 Clock Frequency

FX2LP has an on-chip oscillator circuit that uses an external

24-MHz (±100 ppm) crystal with the following characteristics:

■ Parallel resonant

■ Fundamental mode

■ 500-

W drive level

■ 12-pF (5% tolerance) load capacitors

An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY; internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically.

Figure 2-1. Crystal Configuration

C1

24 MHz

C2

12 pF

12 pF

20 × PLL

12-pF capacitor values assume a trace capacitance of 3 pF per side on a four-layer FR4 PCA

The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.

2.2.2 USARTs

FX2LP contains two standard 8051 USARTs, addressed through

Special Function Register (SFR) bits. The USART interface pins are available on separate I/O pins, and are not multiplexed with port pins.

UART0 and UART1 can operate using an internal clock at

230 KBaud with no more than 1% baud rate error. 230 KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and

12 MHz) such that it always presents the correct frequency for the 230-KBaud operation.

[1]

2.2.3 Special Function Registers

Certain 8051 SFR addresses are populated to provide fast access to critical FX2LP functions. These SFR additions are

shown in Table 1 on page 6

. Bold type indicates nonstandard, enhanced 8051 registers. The two SFR rows that end with “0” and “8” contain bit-addressable registers. The four I/O ports A to

D use the SFR addresses used in the standard 8051 for ports 0 to 3, which are not implemented in FX2LP. Because of the faster and more efficient SFR addressing, the FX2LP I/O ports are not addressable in external RAM space (using the MOVX instruction).

2.3 I

2

C Bus

FX2LP supports the I

2

C bus as a master only at 100/400 kHz.

SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3 V, even if no I

2

C device is connected.

2.4 Buses

All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multiplexed on I/O ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus.

Note

1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 1. Special Function Registers

B

C

D

E

9

A

7

8

F

5

6

3

4

1

2

x

0

8x

IOA

SP

DPL0

DPH0

DPL1

DPH1

DPS

PCON

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON

–

9x

IOB

EXIF

MPAGE

–

–

–

–

Ax

IOC

INT2CLR

INT4CLR

–

–

–

–

Bx

IOD

IOE

OEA

OEB

OEC

OED

OEE

–

SCON0

SBUF0

AUTOPTRH1

–

IE

–

EP2468STAT

–

IP

–

EP01STAT

AUTOPTRL1 EP24FIFOFLGS reserved EP68FIFOFLGS

AUTOPTRH2

AUTOPTRL2 reserved

–

–

GPIFTRIG

GPIFSGLDATH

GPIFSGLDATLX

AUTOPTRSET-UP GPIFSGLDATLNOX

Cx

SCON1

SBUF1

–

–

–

–

–

–

–

–

–

Dx Ex

PSW ACC

–

–

–

–

–

–

–

–

– – –

T2CON

EICON EIE

–

RCAP2L

–

–

–

–

RCAP2H

TL2

TH2

–

–

–

–

–

–

– –

–

–

–

–

2.5 USB Boot Methods

During the power-up sequence, internal logic checks the I

2

C port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0), or it boot-loads the

EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2LP enumerates using internally stored descriptors.

The default ID values for FX2LP are VID/PID/DID (0x04B4,

0x8613, 0xAxxx where xxx = Chip revision).

[2]

Table 2. Default ID Values for FX2LP

Vendor ID

Default VID/PID/DID

0x04B4 Cypress Semiconductor

Product ID 0x8613 EZ-USB FX2LP

Device release 0xAnnn Depends on chip revision

(nnn = chip revision where first silicon = 001)

2.6 ReNumeration

Because the FX2LP’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.

When first plugged into USB, the FX2LP enumerates automatically and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP enumerates again, this time as a device defined by the downloaded information.

This patented two step process called ReNumeration

 happens instantly when the device is plugged in, without a hint that the initial download step has occurred.

Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0.

Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device handles device requests over endpoint zero: if RENUM = 0, the

Default USB Device handles device requests; if RENUM = 1, the firmware services the requests.

2.7 Bus-Powered Applications

The FX2LP fully supports bus-powered designs by enumerating with less than 100 mA as required by the USB 2.0 specification.

2.8 Interrupt System

2.8.1 INT2 Interrupt Request and Enable Registers

FX2LP implements an autovector feature for INT2 and INT4.

There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual (TRM) for more details.

2.8.2 USB Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that is required to identify the individual USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter to its stack, and then jumps to the address 0x0043 where it expects to find a “jump” instruction to the USB interrupt service routine.

–

–

–

–

–

EIP

–

–

–

–

–

–

–

Fx

B

–

–

Note

2. The I

2

C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

The FX2LP jump instruction is encoded as follows:

Table 3. INT2 USB Interrupts

Priority

1

2

3

4

5

INT2VEC Value

00 SUDAV

USB INTERRUPT TABLE FOR INT2

Source

Setup data available

04

08

SOF

SUTOK

Start of frame (or microframe)

Setup token received

Notes

0C

10

SUSPEND

USB RESET

6 14

7 18 EP0ACK

8 1C

9

10

11

12

13

14

15

16

17

19

20

21

22

23

24

25

20

24

28

2C

30

34

38

3C

40

18 44

48

4C

50

54

58

5C

60

EP0-IN

EP0-OUT

EP1-IN

EP1-OUT

EP2

EP4

EP6

EP8

IBN

EP0PING

EP1PING

EP2PING

EP4PING

EP6PING

EP8PING

ERRLIMIT

USB suspend request

Bus reset

FX2LP ACK’d the CONTROL Handshake reserved

EP0-IN ready to be loaded with data

EP0-OUT has USB data

EP1-IN ready to be loaded with data

EP1-OUT has USB data

IN: buffer available. OUT: buffer has data




IN-Bulk-NAK (any IN endpoint) reserved

EP0 OUT was pinged and it NAK’d






Bus errors exceeded the programmed limit

–

29

30

31

32

70

74

78

7C

EP2ISOERR

EP4ISOERR

EP6ISOERR

EP8ISOERR

Reserved

Reserved

ISO EP2 OUT PID sequence error




If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high byte (“page”) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page.

2.8.3 FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual

FIFO/GPIF sources. The FIFO/GPIF Interrupt, similar to the USB Interrupt, can employ autovectoring. Table 4 on page 8

shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 4. Individual FIFO/GPIF Interrupt Sources

12

13

14

8

9

10

11

Priority

1

2

3

6

7

4

5

INT4VEC Value

80

84

88

8C

90

94

98

9C

A0

A4

A8

AC

B0

B4

Source

EP2PF

EP4PF

EP6PF

EP8PF

EP2EF

EP4EF

EP6EF

EP8EF

EP2FF

EP4FF

EP6FF

EP8FF

GPIFDONE

GPIFWF

If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP register), the FX 2LP substitutes its INT4VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically inserted INT4VEC byte at

0x0055 directs the jump to the correct address out of the 14

Endpoint 2 programmable flag




Endpoint 2 empty flag

[3]




Endpoint 2 full flag




GPIF operation complete

GPIF waveform

Notes

addresses within the page. When the ISR occurs, the FX2LP pushes the program counter to its stack then jumps to address

0x0053, where it expects to find a “jump” instruction to the ISR

Interrupt service routine.

Note

3. Errata: In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT Endpoint (EP) in the first transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction. For more information, see

the “Errata” on page 67.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

2.9 Reset and Wakeup

2.9.1 Reset Pin

The input pin, RESET#, resets the FX2LP when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C680xxA, the reset period must enable stabilization of the crystal and the PLL. This reset period must be approximately

5 ms after VCC reaches 3.0 V. If the crystal input pin is driven by a clock signal, the internal PLL stabilizes in 200

s after VCC has reached 3.0 V.

[4]

Figure 2-2 on page 9

shows a power-on reset condition and a reset applied during operation. A power-on reset is defined as the time reset that is asserted while power is being applied to the circuit. A powered reset is when the FX2LP is powered on and operating and the RESET# pin is asserted.

Cypress provides an application note which describes and recommends power-on reset implementation. For more information about reset implementation for the FX2 family of products, visit http://www.cypress.com

.

Figure 2-2. Reset Timing Plots

RESET#

V

IL

3.3V

3.0V

VCC

0V

T

RESET

Power on Reset

Table 2-1. Reset Timing Values

Condition

Power-on reset with crystal

Power-on reset with external clock

Powered reset

T

RESET

5 ms

200

s + clock stability time

200

s

2.9.2 Wakeup Pins

The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL.

When WAKEUP is asserted by external logic, the oscillator restarts after the PLL stabilizes, and the 8051 receives a wakeup

RESET#

V

IL

3.3V

VCC

0V

T

RESET

Powered Reset interrupt. This applies irrespective of whether FX2LP is connected to the USB.

The FX2LP exits the power-down (USB suspend) state by using one of the following methods:

■ USB bus activity (if D+/D– lines are left floating, noise on these lines may indicate activity to the FX2LP and initiate a wakeup)

■ External logic asserts the WAKEUP pin

■ External logic asserts the PA3/WU2 pin

The second wakeup pin, WU2, can also be configured as a general-purpose I/O pin. This enables a simple external R-C network to be used as a periodic wakeup source. WAKEUP is by default active LOW.

Note

4. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200

s.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

2.10 Program/Data RAM

2.10.1 SizeThe FX2LP has 16 KB of internal program/data RAM, where PSEN#/RD# signals are internally ORed to enable the 8051 to access it as both program and data memory.

No USB control registers appears in this space.

Two memory maps are shown in the following diagrams:



shows the Internal Code Memory, EA = 0.

shows the External Code Memory, EA = 1.

enables the user to connect a 64 KB memory without requiring address decodes to keep clear of internal memory spaces.

Only the internal 16 KB and scratch pad 0.5 KB RAM spaces have the following access:

■ USB download

■ USB upload

■ Setup data pointer

■ I

2

C interface boot load

2.10.2 Internal Code Memory, EA = 0

This mode implements the internal 16 KB block of RAM (starting at 0) as combined code and data memory. When external RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This

2.10.3 External Code Memory, EA = 1

The bottom 16 KB of program memory is external and therefore the bottom 16 KB of internal RAM is accessible only as a data memory.

Figure 2-3. Internal Code Memory, EA = 0

Inside FX2LP Outside FX2LP

FFFF

7.5 KB

USB regs and

4K FIFO buffers

(RD#,WR#)

E200

E1FF

E000

0.5 KB RAM

Data (RD#,WR#)*

(OK to populate data memory here—RD#/WR# strobes are not active)

40 KB

External

Data

Memory

(RD#,WR#)

48 KB

External

Code

Memory

(PSEN#)

3FFF

16 KB RAM

Code and Data

(PSEN#,RD#,WR#)* to (OK to populate data memory program here—RD#/WR# strobes are not active) memory here—

PSEN# strobe is not active)

0000

Data Code

*SUDPTR, USB upload/download, I

2

C interface boot access


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

2.11 Register Addresses

Figure 2-4. External Code Memory, EA = 1

Outside FX2LP Inside FX2LP

FFFF

7.5 KB

USB regs and

4K FIFO buffers

(RD#,WR#)

E200

E1FF

E000

0.5 KB RAM

Data (RD#,WR#)*

(OK to populate data memory here—RD#/WR# strobes are not active)

40 KB

External

Data

Memory

(RD#,WR#)

64 KB

External

Code

Memory

(PSEN#)

3FFF

16 KB

RAM

Data

(RD#,WR#)*

(Ok to populate data memory here—RD#/WR# strobes are not active)

0000

Data Code

*SUDPTR, USB upload/download, I

2

C interface boot access

FFFF

4 KB EP2-EP8 buffers

(8 x 512)

F000

EFFF

2 KB RESERVED

E800

E7FF

E7C0

E7BF

E780

E77F

E740

E73F

E700

E6FF

64 BEP1IN

64 Bytes EP1OUT

64 Bytes EP0 IN/OUT

64 Bytes RESERVED

8051 Addressable Registers

(512)

E500

E4FF

E480

E47F

E400

E3FF

E200

E1FF

Reserved (128)

128 Bytes GPIF Waveforms

Reserved (512)

512 Bytes

8051 xdata RAM

E000


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

2.12 Endpoint RAM

2.12.1 Size

■ 3 × 64 bytes (Endpoints 0 and 1)

■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)

2.12.2 Organization

■ EP0

■ Bidirectional endpoint zero, 64-byte buffer

■ EP1IN, EP1OUT

■ 64 byte buffers, bulk or interrupt

■ EP2, 4, 6, 8

■ Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4 and

EP8 can be double buffered; EP2 and 6 can be either double, triple, or quad buffered. For Hi-Speed endpoint configuration options, see

Figure 2-5 .

2.12.3 Setup Data Buffer

A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data from a CONTROL transfer.

2.12.4 Endpoint Configurations (Hi-Speed Mode)

Endpoints 0 and 1 are the same for every configuration.

Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT.

The endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. When operating in the Full-Speed BULK mode, only the first 64 bytes of each buffer are used. For example, in Hi-Speed mode, the max packet size is 512 bytes, but in Full-Speed mode, it is 64 bytes. Even though a buffer is configured to a 512-byte buffer, in Full-Speed mode, only the first 64 bytes are used. The unused endpoint buffer space is not available for other operations. An example endpoint configuration is the EP2–1024 double-buffered; EP6–512 quad-buffered (column 8).

Figure 2-5. Endpoint Configuration

EP0 IN&OUT

EP1 IN

EP1 OUT

64

64

64

64

64

64

64

64

64

EP2

512

512

EP4

512

512

EP2

512

512

EP4

512

512

EP2

512

512

EP4

512

512

EP6

512

512

EP8

512

512

1

EP6

512

512

EP6

1024

512

512

2

1024

3

64

64

64

64

64

64

64

64

64

EP2

512

512

EP2

512

512

EP2

512

512

512

512

512

512

512

512

EP6

EP6

512

512

EP8

512

512

4

EP6

512

512

512

512

5

1024

1024

6

64

64

64

EP2

1024

EP2

1024

EP2

1024

1024

EP6

512

512

EP8

512

512

7

64

64

64

1024

EP6

512

512

EP6

1024

512

512

8

64

64

64

1024

1024

9

64

64

64

64

64

64

64

64

64

EP2

EP2 EP2

512

512

1024

1024

512

EP6

512

1024

1024

512

1024

1024

512

EP8

EP8

512

512

512 512

1024

1024

10 11 12


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

2.12.5 Default Full-Speed Alternate Settings

Table 5. Default Full Speed Alternate Settings

[5, 6]

ep0 ep1out

Alternate Setting

ep1in ep2 ep4 ep6 ep8

0

64

0

0

64

64 bulk

64 bulk

1

0 64 bulk out (2×)

0 64 bulk out (2×)

0 64 bulk in (2×)

0 64 bulk in (2×)

2.12.6 Default High Speed Alternate Settings

Table 6. Default Hi-Speed Alternate Settings

[5, 6]

ep0

Alternate Setting

ep1out ep1in ep2 ep4 ep6 ep8

0

0

0

0

64

0

0

0 1

64

512 bulk

[7]

512 bulk

[7]

512 bulk out (2×)

512 bulk out (2×)

512 bulk in (2×)

512 bulk in (2×)

2.13 External FIFO Interface

2.13.1 Architecture

The FX2LP slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories and are controlled by FIFO control signals (such as IFCLK, SLCS#,

SLRD, SLWR, SLOE, PKTEND, and flags).

In operation, some of the eight RAM blocks fill or empty from the

SIE, while the others are connected to the I/O transfer logic. The transfer logic takes two forms: the GPIF for internally generated control signals and the slave FIFO interface for externally controlled transfers.

2.13.2 Master/Slave Control Signals

The FX2LP endpoint FIFOs are implemented as eight physically distinct 256



16 RAM blocks. The 8051/SIE can switch any of the

RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between

“USB FIFOs” and “Slave FIFOs.” Because they are physically the same memory, no bytes are actually transferred between buffers.

At any time, some RAM blocks are filling/emptying with the USB data under SIE control, while other RAM blocks are available to the 8051, the I/O control unit, or both. The RAM blocks operates as single-port in the USB domain, and dual-port in the 8051-I/O

64

64 int

64 int

64 int out (2×)

2

64 bulk out (2×)

64 int in (2×)

64 bulk in (2×)

3

64

64 int

64 int

64 iso out (2×)

64 bulk out (2×)

64 iso in (2×)

64 bulk in (2×)

2

64

64 int

64 int

512 int out (2×)

512 bulk out (2×)

512 int in (2×)

512 bulk in (2×)

64

64 int

3

64 int

512 iso out (2×)

512 bulk out (2×)

512 iso in (2×)

512 bulk in (2×) domain. The blocks can be configured as single-, double-, triple-, or quad-buffered as previously shown.

The I/O control unit implements either an internal master (M for

Master) or external master (S for Slave) interface.

In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 MBytes/s (48

MHz IFCLK with 16-bit interface).

In the Slave (S) mode, FX2LP accepts either an internally derived clock or externally supplied clock (IFCLK, max frequency

48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. When using an external IFCLK, the external clock must be present before switching to the external clock with the IFCLKSRC bit. Each endpoint can individually be selected for byte or word operation by an internal configuration bit and a

Slave FIFO Output Enable signal (SLOE)that enables data of the selected width. External logic must ensure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and

SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE, and

PKTEND are gated by the signal SLCS#.

Notes

5. “0” means “not implemented.”

6. “2×” means “double buffered.”

7. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

2.13.3 GPIF and FIFO Clock Rates

An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz.

Alternatively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the

IFCONFIG register turns this clock output off, if desired. Another bit within the IFCONFIG register inverts the IFCLK signal whether internally or externally sourced.

2.14 GPIF

The GPIF is a flexible 8-bit or 16-bit parallel interface driven by a user-programmable finite state machine. It enables the

CY7C68013A/15A to perform local bus mastering and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia.

The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a

FIFO to the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that is executed to perform the desired data move between the

FX2LP and the external device.

2.14.1 Six Control OUT Signals

The 100-pin and 128-pin packages bring out all six Control

Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define the CTL waveforms. The 56-pin package brings out three of these signals, CTL0–CTL2. CTLx waveform edges can be programmed to make transitions as fast as once per clock

(20.8 ns using a 48-MHz clock).

2.14.2 Six Ready IN Signals

The 100-pin and 128-pin packages bring out all six Ready inputs

(RDY0–RDY5). The 8051 programs the GPIF unit to test the

RDY pins for GPIF branching. The 56-pin package brings out two of these signals, RDY0–1.

2.14.3 Nine GPIF Address OUT Signals

Nine GPIF address lines are available in the 100-pin and 128-pin packages, GPIFADR[8..0]. The GPIF address lines enable indexing through up to a 512-byte block of RAM. If more address lines are needed, then I/O port pins are used.

2.14.4 Long Transfer Mode

In the master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 2

32

transactions.

The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction.

2.15 ECC Generation

[8]

The EZ-USB can calculate ECCs (Error Correcting Codes) on data that passes across its GPIF or Slave FIFO interfaces. There are two ECC configurations: Two ECCs, each calculated over

256 bytes (SmartMedia Standard); and one ECC calculated over

512 bytes.

The ECC can correct any one-bit error or detect any two-bit error.

2.15.1 ECC Implementation

The two ECC configurations are selected by the ECCM bit:

ECCM = 0

Two 3-byte ECCs, each calculated over a 256-byte block of data.

This configuration conforms to the SmartMedia Standard.

Write any value to ECCRESET, then pass data across the GPIF or Slave FIFO interface. The ECC for the first 256 bytes of data is calculated and stored in ECC1. The ECC for the next 256 bytes is stored in ECC2. After the second ECC is calculated, the values in the ECCx registers do not change until ECCRESET is written again, even if more data is subsequently passed across the interface.

ECCM = 1

One 3-byte ECC calculated over a 512-byte block of data.

Write any value to ECCRESET then pass data across the GPIF or Slave FIFO interface. The ECC for the first 512 bytes of data is calculated and stored in ECC1; ECC2 is unused. After the

ECC is calculated, the values in ECC1 do not change even if more data is subsequently passed across the interface, till

ECCRESET is written again.

2.16 USB Uploads and Downloads

The core has the ability to directly edit the data contents of the internal 16-KB RAM and of the internal 512-byte scratch pad

RAM via a vendor-specific command. This capability is normally used when soft downloading the user code and is available only to and from the internal RAM, only when the 8051 is held in reset.

The available RAM spaces are 16 KB from 0x0000–0x3FFF

(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad data RAM).

[9]

2.17 Autopointer Access

FX2LP provides two identical autopointers. They are similar to the internal 8051 data pointers but with an additional feature: they can optionally increment after every memory access. This capability is available to and from both internal and external

RAM. Autopointers are available in external FX2LP registers under the control of a mode bit (AUTOPTRSET-UP.0). Using the external FX2LP autopointer access (at 0xE67B – 0xE67C) enables the autopointer to access all internal and external RAM to the part.

Also, autopointers can point to any FX2LP register or endpoint buffer space. When the autopointer access to external memory is enabled, locations 0xE67B and 0xE67C in XDATA and code space cannot be used.

Notes

8. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.

9. After the data is downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

2.18 I

2

C Controller

FX2LP has one I

2

C port that is driven by two internal controllers, the one that automatically operates at boot time to load

VID/PID/DID and configuration information, and another that the

8051 uses when running to control external I

2

C devices. The I

2

C port operates in master mode only.

2.18.1 I

2

C Port Pins

The I

2

C pins SCL and SDA must have external 2.2-k

 pull-up resistors even if no EEPROM is connected to the FX2LP.

External EEPROM device address pins must be configured

properly. See Table 7 for configuring the device address pins.

Table 7. Strap Boot EEPROM Address Lines to These Values

16

Bytes

128

256

4K

8K

16K

Example EEPROM

24LC00

[10]

24LC01

24LC02

24LC32

24LC64

24LC128

0

0

0

A2

N/A

0

0

0

0

0

A1

N/A

0

0

1

1

1

A0

N/A

0

0

2.18.2 I

2

C Interface Boot Load Access

At power-on reset, the I

2

C interface boot loader loads the

VID/PID/DID configuration bytes and up to 16 KB of program/data. The available RAM spaces are 16 KB from

0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051 is in reset. I

2

C interface boot loads only occur after power-on reset.

2.18.3 I

2

C Interface General-Purpose Access

The 8051 can control peripherals connected to the I

2

C bus using the I2CTL and I2DAT registers. FX2LP provides I

2

C master control only; it is never an I

2

C slave.

2.19 Compatible with Previous Generation

EZ-USB FX2

The EZ-USB FX2LP is form-, fit-, and with minor exceptions, functionally-compatible with its predecessor, the EZ-USB FX2.

This makes for an easy transition for designers wanting to upgrade their systems from the FX2 to the FX2LP. The pinout and package selection are identical and a vast majority of firmware previously developed for the FX2 functions in the

FX2LP.

For designers migrating from the FX2 to the FX2LP, a change in the bill of material and review of the memory allocation (due to increased internal memory) is required. For more information about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the application note titled Migrating from EZ-USB FX2 to EZ-USB

FX2LP available in the Cypress web site .

Table 8. Part Number Conversion Table

EZ-USB FX2

Part Number

EZ-USB FX2LP

Part Number

Package

Description

CY7C68013-56PVC CY7C68013A-56PVXC or

CY7C68014A-56PVXC

56-pin

SSOP

CY7C68013-56PVCT CY7C68013A-56PVXCT or

CY7C68014A-56PVXCT

56-pin

SSOP –

Tape and

Reel

CY7C68013-56LFC CY7C68013A-56LFXC or

CY7C68014A-56LFXC

56-pin QFN

CY7C68013-100AC CY7C68013A-100AXC or

CY7C68014A-100AXC

100-pin

TQFP

CY7C68013-128AC CY7C68013A-128AXC or

CY7C68014A-128AXC

128-pin

TQFP

2.20 CY7C68013A/14A and CY7C68015A/16A

Differences

CY7C68013A is identical to CY7C68014A in form, fit, and functionality. CY7C68015A is identical to CY7C68016A in form, fit, and functionality. CY7C68014A and CY7C68016A have a lower suspend current than CY7C68013A and CY7C68015A respectively and are ideal for power-sensitive battery applications.

CY7C68015A and CY7C68016A are available in 56-pin QFN package only. Two additional GPIO signals are available on the

CY7C68015A and CY7C68016A to provide more flexibility when neither IFCLK or CLKOUT are needed in the 56-pin package.

USB developers wanting to convert their FX2 56-pin application to a bus-powered system directly benefit from these additional signals. The two GPIOs give developers the signals they need for the power-control circuitry of their bus-powered application without pushing them to a high-pincount version of FX2LP.

The CY7C68015A is only available in the 56-pin QFN package

Table 9. CY7C68013A/14A and CY7C68015A/16A

Pin Differences

CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A

IFCLK PE0

CLKOUT PE1

Note

10. This EEPROM does not have address pins.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

3. Pin Assignments

Figure 3-1 on page 17 identifies all signals for the five package

types. The following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 128-pin, 100-pin, and 56-pin packages.

The signals on the left edge of the 56-pin package in Figure 3-1 on page 17

are common to all versions in the FX2LP family with the noted differences between the CY7C68013A/14A and the

CY7C68015A/16A.

Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power on default configuration.

The 100-pin package adds functionality to the 56-pin package by adding these pins:

■ PORTC or alternate GPIFADR[7:0] address signals

■ PORTE or alternate GPIFADR[8] address signal and seven additional 8051 signals

■ Three GPIF Control signals

■ Four GPIF Ready signals

■ Nine 8051 signals (two USARTs, three timer inputs, INT4, and

INT5#)

■ BKPT, RD#, WR#.

The 128-pin package adds the 8051 address and data buses plus control signals. Note that two of the required signals, RD# and WR#, are present in the 100-pin version.

In the 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC. This feature is enabled by setting the

PORTCSTB bit in the CPUCS register.

Section 9.5

displays the timing diagram of the read and write

strobing function on accessing PORTC.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

D7

D6

D5

D4

D3

D2

D1

D0

XTALIN

XTALOUT

RESET#

WAKEUP#

SCL

SDA

Port

56

Figure 3-1. Signal

GPIF Master

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

**PE0 replaces IFCLK

& PE1 replaces CLKOUT on CY7C68015A/16A

**PE0

**PE1

IFCLK

CLKOUT

DPLUS

DMINUS

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

PA5

PA6

PA7

RDY0

RDY1

CTL0

CTL1

CTL2

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

PA5

PA6

PA7

CTL3

CTL4

CTL5

RDY2

RDY3

RDY4

RDY5

100

BKPT

PORTC7/GPIFADR7

PORTC6/GPIFADR6

PORTC5/GPIFADR5

PORTC4/GPIFADR4

PORTC3/GPIFADR3

PORTC2/GPIFADR2

PORTC1/GPIFADR1

PORTC0/GPIFADR0

PE7/GPIFADR8

PE6/T2EX

PE5/INT6

PE4/RxD1OUT

PE3/RxD0OUT

PE2/T2OUT

PE1/T1OUT

PE0/T0OUT

RxD0

TxD0

RxD1

TxD1

INT4

INT5#

T2

T1

T0

EA

128

RD#

WR#

CS#

OE#

PSEN#

A7

A6

A5

A4

A3

A2

A1

A0

A15

A14

A13

A12

A11

A10

A9

A8

Slave FIFO

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

SLRD

SLWR

FLAGA

FLAGB

FLAGC

INT0#/ PA0

INT1#/ PA1

SLOE

WU2/PA3

FIFOADR0

FIFOADR1

PKTEND

PA7/FLAGD/SLCS#


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 3-2. CY7C68013A/CY7C68014A 128-Pin TQFP Pin Assignment

22

23

24

25

19

20

21

15

16

17

18

12

13

14

9

10

11

6

7

8

1

4

5

2

3

35

36

37

38

32

33

34

29

30

31

26

27

28

A11

A12

A13

A14

A15

VCC

GND

NC

NC

NC

AVCC

DPLUS

DMINUS

AGND

CLKOUT

VCC

GND

RDY0/*SLRD

RDY1/*SLWR

RDY2

RDY3

RDY4

RDY5

AVCC

XTALOUT

XTALIN

AGND

INT4

T0

T1

T2

*IFCLK

RESERVED

BKPT

EA

SCL

SDA

OE#

CY7C68013A/CY7C68014A

128-pin TQFP

78

77

76

82

81

80

79

85

84

83

88

87

86

92

91

90

89

95

94

93

102

101

100

99

98

97

96

69

68

67

66

65

72

71

70

75

74

73

PD0/FD8

*WAKEUP

VCC

RESET#

CTL5

A3

A2

A1

A0

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

D7

D6

D5

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

GND

PC7/GPIFADR7

PC6/GPIFADR6

PC5/GPIFADR5

PC4/GPIFADR4

PC3/GPIFADR3

PC2/GPIFADR2

PC1/GPIFADR1

PC0/GPIFADR0

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

VCC

CTL4

CTL3

GND


* denotes programmable polarity

Page 18 of 71

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 3-3. CY7C68013A/CY7C68014A 100-Pin TQFP Pin Assignment

23

24

25

20

21

22

16

17

18

19

13

14

15

26

27

28

29

30

10

11

12

7

8

9

5

6

3

4

1

2

AGND

NC

NC

NC

AVCC

DPLUS

DMINUS

AGND

VCC

GND

INT4

T0

T1

T2

VCC

GND

RDY0/*SLRD

RDY1/*SLWR

RDY2

RDY3

RDY4

RDY5

AVCC

XTALOUT

XTALIN

*IFCLK

RESERVED

BKPT

SCL

SDA

CY7C68013A/CY7C68014A

100-pin TQFP

PD0/FD8

*WAKEUP

VCC

RESET#

CTL5

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

GND

PC7/GPIFADR7

PC6/GPIFADR6

PC5/GPIFADR5

PC4/GPIFADR4

PC3/GPIFADR3

PC2/GPIFADR2

PC1/GPIFADR1

PC0/GPIFADR0

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

VCC

CTL4

CTL3

58

57

56

62

61

60

59

65

64

63

68

67

66

55

54

53

52

51

72

71

70

69

75

74

73

80

79

78

77

76



Page 19 of 71

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 3-4. CY7C68013A/CY7C68014A 56-Pin SSOP Pin Assignment

CY7C68013A/CY7C68014A

56-pin SSOP

25

26

27

21

22

23

24

28

18

19

20

15

16

17

11

12

13

14

8

9

10

6

7

4

5

1

2

3

PD5/FD13

PD6/FD14

PD7/FD15

GND

CLKOUT

VCC

GND

RDY0/*SLRD

RDY1/*SLWR

AVCC

XTALOUT

XTALIN

AGND

AVCC

DPLUS

DMINUS

AGND

VCC

GND

*IFCLK

RESERVED

SCL

SDA

VCC

PB0/FD0

PB1/FD1

PB2/FD2

PB3/FD3

PD4/FD12

PD3/FD11

PD2/FD10

PD1/FD9

PD0/FD8

*WAKEUP

VCC

RESET#

GND

PA7/*FLAGD/SLCS#

PA6/PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

GND

VCC

GND

PB7/FD7

PB6/FD6

PB5/FD5

PB4/FD4

33

32

31

30

36

35

34

29

39

38

37

43

42

41

40

46

45

44

49

48

47

53

52

51

50

56

55

54



CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 3-5. CY7C68013A/14A/15A/16A 56-Pin QFN Pin Assignment

RDY0/*SLRD

RDY1/*SLWR

AVCC

XTALOUT

XTALIN

AGND

AVCC

DPLUS

DMINUS

AGND

VCC

GND

*IFCLK/**PE0

RESERVED

7

8

5

6

3

4

1

2

9

10

11

12

13

14

CY7C68013A/CY7C68014A

&

CY7C68015A/CY7C68016A

56-pin QFN

38

37

36

35

42

41

40

39

34

33

32

31

30

29

RESET#

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA


** denotes CY7C68015A/CY7C68016A pinout


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 3-6. CY7C68013A 56-pin VFBGA Pin Assignment – Top View

1 2 3 4 5 6 7 8

A

B

C

D

E

F

G

H

1A 2A 3A 4A 5A 6A 7A 8A

1B 2B 3B 4B 5B 6B 7B 8B

1C 2C 3C 4C 5C 6C 7C 8C

1D 2D 7D 8D

1E 2E 7E 8E

1F 2F 3F 4F 5F 6F 7F 8F

1G 2G 3G 4G 5G 6G 7G 8G

1H 2H 3H 4H 5H 6H 7H 8H


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

3.1 CY7C68013A/15A Pin Descriptions

Table 10. FX2LP Pin Descriptions

[11]

128

TQFP

100

TQFP

56

SSOP

10 9 10

56

QFN

3

56

VFBGA

Name

2D AVCC

Type Default Reset

[12]

Description

17

13

20

16

12

19

14

13

17

7

6

10

1D

2F

1F

AVCC

AGND

AGND

Power

Power

Ground

Ground

N/A

N/A

N/A

N/A

N/A Analog VCC. Connect this pin to the 3.3 V power source. This signal provides power to the analog section of the chip.

N/A Analog VCC. Connect this pin to the 3.3 V power source. This signal provides power to the analog section of the chip.

N/A Analog Ground. Connect to ground with as short a path as possible.

N/A Analog Ground. Connect to ground with as short a path as possible.

19

18

94

95

–

–

18

17

–

–

–

–

–

–

–

–

16

15

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

9

8

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

1E DMINUS

2E DPLUS

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

D0

D1

I/O/Z

I/O/Z

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

I/O/Z

I/O/Z

Z

Z

L

L

L

L

L

L

L

L

L

L

L

L

L

L

Z

Z

L

L

L

L

L

L

L

L

L

L

L

L

L

L

Z

Z

Z

Z

N/A USB D– Signal. Connect to the USB D– signal.

N/A USB D+ Signal. Connect to the USB D+ signal.

L

L

8051 Address Bus. This bus is driven at all times.

When the 8051 is addressing internal RAM it reflects the internal address.

L

L

96 –

97 –

117

118

–

–

119 –

120 –

126

127

22

23

24 –

25 –

59

60

–

–

128 –

21 –

–

–

–

–

61 –

62 –

63 –

86 –

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

D2

D3

D4

D5

I/O/Z

I/O/Z

I/O/Z

I/O/Z

Z

Z

Z

Z

Z

Z

Z

Z

8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.

87 –

88 –

–

–

–

–

–

–

D6

D7

I/O/Z

I/O/Z

Z

Z

39 – – – – PSEN# Output H H Program Store Enable. This active LOW signal indicates an 8051 code fetch from external memory.

It is active for program memory fetches from

0x4000–0xFFFF when the EA pin is LOW, or from

0x0000–0xFFFF when the EA pin is HIGH.

Notes

11. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in standby.

Note also that no pins should be driven while the device is powered down.

12. The Reset column indicates the state of signals during reset (RESET# asserted) or during Power on Reset (POR).


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


[11]

(continued)

128

TQFP

100

TQFP

56

SSOP

34 28 –

56

QFN

–

56

VFBGA

Name

BKPT

99

35

12

11

1

77

–

11

10

100

49

–

12

11

5

42

–

5

4

54


[12]

Description

8B

–

1C

2C

RESET#

EA

XTALIN

XTALOUT

2B CLKOUT on

CY7C68013

A and

CY7C68014

A

-

-----------------

PE1 on

CY7C68015

A and

CY7C68016

A

Output

Input

Input

Input

L

N/A

N/A

N/A

L Breakpoint. This pin goes active (HIGH) when the

8051 address bus matches the BPADDRH/L registers and breakpoints are enabled in the

BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT register is HIGH, this signal pulses

HIGH for eight 12-/24-/48-MHz clocks. If the

BPPULSE bit is LOW, the signal remains HIGH until the 8051 clears the BREAK bit (by writing 1 to it) in the BREAKPT register.

N/A Active LOW Reset. Resets the entire chip. See

section 2.9 ”Reset and Wakeup” on page 9 for more

details.

N/A External Access. This pin determines where the

8051 fetches code between addresses 0x0000 and

0x3FFF. If EA = 0 the 8051 fetches this code from its internal RAM. IF EA = 1 the 8051 fetches this code from external memory.

N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND.

It is also correct to drive XTALIN with an external

24-MHz square wave derived from another clock source. When driving from an external source, the driving signal should be a 3.3-V square wave.

Output

O/Z

----------

-

I/O/Z

N/A

12 MHz

----------

I

N/A Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND.

If an external clock is used to drive XTALIN, leave this pin open.

Clock

Driven

----------

Z

CLKOUT: 12-, 24- or 48-MHz clock, phase-locked to the 24-MHz input clock. The 8051 defaults to

12-MHz operation. The 8051 may three-state this output by setting CPUCS.1 = 1.

-------------------------------------------------------------------

-----PE1 is a bidirectional I/O port pin.

Port A

82 67 40 33 8G PA0 or

INT0#

I/O/Z I

(PA0)

Z

(PA0)

83 68 41 34 6G PA1 or

INT1#

I/O/Z I

(PA1)

Z

(PA1)

Multiplexed pin whose function is selected by

PORTACFG.0

PA0 is a bidirectional I/O port pin.

INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either edge-triggered (IT0 = 1) or level-triggered (IT0 = 0).

Multiplexed pin whose function is selected by:

PORTACFG.1


INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either edge-triggered (IT1 = 1) or level-triggered (IT1 = 0).


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


[11]

(continued)

128

TQFP

100

TQFP

56

SSOP

84 69 42

56

QFN

35

56

VFBGA

Name

8F PA2 or

SLOE

85

89

90

91

92

70

71

72

73

74

43

44

45

46

47

36

37

38

39

40

7F

6F

8C

7C

6C

PA3 or

WU2

PA4 or

FIFOADR0

PA5 or

FIFOADR1

PA6 or

PKTEND

PA7 or

FLAGD or

SLCS#


[12]

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

(PA2)

I

(PA3)

(PA4)

I

(PA5)

(PA6)

I

I

I

I

(PA7)

Z

(PA2)

Z

(PA3)

Z

(PA4)

Z

(PA5)

Z

(PA6)

Z

(PA7)

Description

Multiplexed pin whose function is selected by two bits:

IFCONFIG[1:0].


SLOE is an input-only output enable with programmable polarity (FIFOPINPOLAR.4) for the slave

FIFOs connected to FD[7..0] or FD[15..0].


WAKEUP.7 and OEA.3


WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to enable it to exit the suspend mode. Asserting this pin inhibits the chip from suspending if WU2EN = 1.


IFCONFIG[1..0].


FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0].


IFCONFIG[1..0].


FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0].

Multiplexed pin whose function is selected by the

IFCONFIG[1:0] bits.


PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is programmable via FIFOPINPOLAR.5.


IFCONFIG[1:0] and PORTACFG.7 bits.


FLAGD is a programmable slave-FIFO output status flag signal.

SLCS# gates all other slave FIFO enable/strobes

Port B

44 34 25 18 3H PB0 or

FD[0]

I/O/Z I

(PB0)

45

46

35

36

26

27

19

20

4F

4H

PB1 or

FD[1]

PB2 or

FD[2]

I/O/Z

I/O/Z

(PB1)

I

I

(PB2)

Z

(PB0)

Z

(PB1)

Z

(PB2)

Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].

PB0 is a bidirectional I/O port pin.

FD[0] is the bidirectional FIFO/GPIF data bus.








CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


[11]

(continued)

128

TQFP

100

TQFP

56

SSOP

47 37 28

56

QFN

21

56

VFBGA

Name

4G PB3 or

FD[3]

54

55

56

57

44

45

46

47

29

30

31

32

22

23

24

25

5H

5G

5F

6H

PB4 or

FD[4]

PB5 or

FD[5]

PB6 or

FD[6]

PB7 or

FD[7]


[12]

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I

(PB3)

(PB4)

I

(PB5)

(PB6)

I

I

I

(PB7)

Z

(PB3)

Z

(PB4)

Z

(PB5)

Z

(PB6)

Z

(PB7)

Description
















PORT C

72 57 – – – PC0 or

GPIFADR0

I/O/Z I

(PC0)

73

74

75

76

77

78

79

58

59

60

61

62

63

64

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

PC1 or

GPIFADR1

PC2 or

GPIFADR2

PC3 or

GPIFADR3

PC4 or

GPIFADR4

PC5 or

GPIFADR5

PC6 or

GPIFADR6

PC7 or

GPIFADR7

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I

(PC1)

(PC2)

I

(PC3)

(PC4)

I

(PC5)

(PC6)

I

I

I

I

(PC7)

Z

(PC0)

Z

(PC1)

Z

(PC2)

Z

(PC3)

Z

(PC4)

Z

(PC5)

Z

(PC6)

Z

(PC7)


PORTCCFG.0

PC0 is a bidirectional I/O port pin.

GPIFADR0 is a GPIF address output pin.


PORTCCFG.1




PORTCCFG.2




PORTCCFG.3




PORTCCFG.4




PORTCCFG.5




PORTCCFG.6




PORTCCFG.7




CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


[11]

(continued)

128

TQFP

100

TQFP

56

SSOP

56

QFN

PORT D

102 80 52 45

56

VFBGA

8A

Name

PD0 or

FD[8]


[12]

I/O/Z I

(PD0)

103

104

105

121

122

123

124

81

82

83

95

96

97

98

53

54

55

56

1

2

3

46

47

48

49

50

51

52

7A

6B

6A

3B

3A

3C

2A

PD1 or

FD[9]

PD2 or

FD[10]

PD3 or

FD[11]

PD4 or

FD[12]

PD5 or

FD[13]

PD6 or

FD[14]

PD7 or

FD[15]

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I

(PD1)

(PD2)

I

(PD3)

(PD4)

I

(PD5)

(PD6)

I

I

I

I

(PD7)

Description

Z

(PD0)

Z

(PD1)

Z

(PD2)

Z

(PD3)

Z

(PD4)

Z

(PD5)

Z

(PD6)

Z

(PD7)


IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.























Port E

108 86 – – – PE0 or

T0OUT

I/O/Z I

(PE0)

109 87 – – – PE1 or

T1OUT

I/O/Z I

(PE1)

Z

(PE0)

Z

(PE1)


PORTECFG.0 bit.

PE0 is a bidirectional I/O port pin.

T0OUT is an active-HIGH signal from 8051

Timer-counter0. T0OUT outputs a high level for one

CLKOUT clock cycle when Timer0 overflows. If

Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is active when the low byte timer/counter overflows.


PORTECFG.1 bit.


T1OUT is an active HIGH signal from 8051

Timer-counter1. T1OUT outputs a high level for one

CLKOUT clock cycle when Timer1 overflows. If

Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is active when the low byte timer/counter overflows.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


[11]

(continued)

128

TQFP

100

TQFP

56

SSOP

110 88 –

56

QFN

–

56

VFBGA

–

Name

PE2 or

T2OUT

111

112

113

114

115

89

90

91

92

93

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

PE3 or

RXD0OUT

PE4 or

RXD1OUT

PE5 or

INT6

PE6 or

T2EX

PE7 or

GPIFADR8


[12]

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

(PE2)

I

(PE3)

(PE4)

I

(PE5)

(PE6)

I

I

I

I

(PE7)

Z

(PE2)

Z

(PE3)

Z

(PE4)

Z

(PE5)

Z

(PE6)

Z

(PE7)

Description


PORTECFG.2 bit.


T2OUT is the active HIGH output signal from 8051

Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows.


PORTECFG.3 bit.


RXD0OUT is an active HIGH signal from 8051

UART0. If RXD0OUT is selected and UART0 is in

Mode 0, this pin provides the output data for UART0 only when it is in sync mode. Otherwise it is a 1.


PORTECFG.4 bit.


RXD1OUT is an active-HIGH output from 8051

UART1. When RXD1OUT is selected and UART1 is in Mode 0, this pin provides the output data for

UART1 only when it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.


PORTECFG.5 bit.


INT6 is the 8051 INT6 interrupt request input signal.

The INT6 pin is edge-sensitive, active HIGH.


PORTECFG.6 bit.


T2EX is an active HIGH input signal to the 8051

Timer2. T2EX reloads timer 2 on its falling edge.

T2EX is active only if the EXEN2 bit is set in T2CON.


PORTECFG.7 bit.



4

5

6

7

8

3

4

5

6

7

8

9

–

–

–

1

2

–

–

–

1A RDY0 or

SLRD

1B

–

–

–

RDY1 or

SLWR

RDY2

RDY3

RDY4

Input

Input

Input

Input

Input

N/A

N/A

N/A

N/A

N/A

N/A Multiplexed pin whose function is selected by the following bits:

IFCONFIG[1..0].

RDY0 is a GPIF input signal.

SLRD is the input-only read strobe with programmable polarity (FIFOPINPOLAR.3) for the slave


N/A Multiplexed pin whose function is selected by the following bits:

IFCONFIG[1..0].

RDY1 is a GPIF input signal.

SLWR is the input-only write strobe with programmable polarity (FIFOPINPOLAR.2) for the slave


N/A RDY2 is a GPIF input signal.




CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


[11]

(continued)

128

TQFP

100

TQFP

56

SSOP

56

QFN

9

69

8

54

–

36

–

29

56

VFBGA

–

Name

RDY5

7H CTL0 or

FLAGA

70

71

66

67

98

32

28

106

31

55

56

51

52

76

26

22

84

25

37

38

–

–

–

20

–

–

–

30

31

–

–

–

13

–

–

–

7G

8H

–

–

–

–

–

–

CTL1 or

FLAGB

CTL2 or

FLAGC

CTL3

CTL4

CTL5

2G IFCLK on

CY7C68013

A and

CY7C68014

A

-

-----------------

PE0 on

CY7C68015

A and

CY7C68016

A

INT4

INT5#

T2

Type

Input

O/Z

O/Z

O/Z

O/Z

Output

Output

I/O/Z

N/A

H

H

H

H

H

H

Z

----------

-

I/O/Z

----------

I


L Multiplexed pin whose function is selected by the following bits:

IFCONFIG[1..0].

CTL0 is a GPIF control output.

FLAGA is a programmable slave-FIFO output status flag signal.

Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.

L

L

Multiplexed pin whose function is selected by the following bits:

IFCONFIG[1..0].


FLAGB is a programmable slave-FIFO output status flag signal.

Defaults to FULL for the FIFO selected by the

FIFOADR[1:0] pins.

Multiplexed pin whose function is selected by the following bits:

IFCONFIG[1..0].


FLAGC is a programmable slave-FIFO output status flag signal.

Defaults to EMPTY for the FIFO selected by the

FIFOADR[1:0] pins.

L

L



L

Z

----------

Z


Interface Clock, used for synchronously clocking data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by setting the bit

IFCONFIG.4 =1.

-------------------------------------------------------------------

----


Input

Input

Input

Default Reset

N/A

N/A

N/A

[12]

Description

N/A INT4 is the 8051 INT4 interrupt request input signal.

The INT4 pin is edge-sensitive, active HIGH.

N/A INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is edge-sensitive, active LOW.

N/A T2 is the active HIGH T2 input signal to 8051

Timer2, which provides the input to Timer2 when

C/T2 = 1. When C/T2 = 0, Timer2 does not use this pin.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

36

37

64

68

81

2

26

43

48


[11]

(continued)

128

TQFP

100

TQFP

56

SSOP

30 24 –

56

QFN

–

56

VFBGA

– T1

Name

29

53

52

51

50

42

41

40

38

23

43

42

41

40

32

31

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

T0

RXD1

TXD1

RXD0

TXD0

CS#

WR#

RD#

OE#


[12]

Input N/A

Input

Input

Output

Input

Output

Output

Output

Output

Output

N/A

N/A

H

N/A

H

H

H

H

H

Description

N/A T1 is the active HIGH T1 signal for 8051 Timer1, which provides the input to Timer1 when C/T1 is 1.

When C/T1 is 0, Timer1 does not use this bit.

N/A T0 is the active HIGH T0 signal for 8051 Timer0, which provides the input to Timer0 when C/T0 is 1.

When C/T0 is 0, Timer0 does not use this bit.

N/A RXD1is an active HIGH input signal for 8051

UART1, which provides data to the UART in all modes.

L TXD1is an active HIGH output pin from 8051

UART1, which provides the output clock in sync mode, and the output data in async mode.

N/A RXD0 is the active HIGH RXD0 input to 8051

UART0, which provides data to the UART in all modes.

L TXD0 is the active HIGH TXD0 output from 8051

UART0, which provides the output clock in sync mode, and the output data in async mode.

H

H

H

H

CS# is the active LOW chip select for external memory.

WR# is the active LOW write strobe output for external memory.

RD# is the active LOW read strobe output for external memory.

OE# is the active LOW output enable for external memory.

33 27 21 14 2H Reserved Input N/A N/A Reserved. Connect to ground.

101 79 51 44 7B WAKEUP

29

30

1

20

33

38

49

53

66

22

23

6

18

24

–

34

–

39

15

16

55

11

17

–

27

–

32

3F

3G

5A

1G

7E

–

SCL

SDA

VCC

VCC

VCC

VCC

8E VCC

–

5C

VCC

VCC

Input

OD

OD

Power N/A

Power N/A

Power N/A

Power N/A

Power N/A

Power N/A

Power N/A

N/A

Z

Z

N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the

8051 to enable it to exit the suspend mode. Holding

WAKEUP asserted inhibits the EZ-USB chip from suspending. This pin has programmable polarity

(WAKEUP.4).

Z

(if booting is done)

Clock for the I

2

C interface. Connect to VCC with a

2.2-k

 resistor, even if no I 2

C peripheral is attached.

Z

(if booting is done)

Data for I

2

C compatible interface. Connect to VCC with a 2.2-k

 resistor, even if no I

2

C compatible

peripheral is attached.

N/A VCC. Connect to the 3.3-V power source.



N/A VCC. Connect to 3.3-V power source.





CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


[11]

(continued)

128

TQFP

100

TQFP

56

SSOP

56

QFN

100 78

107 85

50

–

43

–

56

VFBGA

Name

5B VCC

– VCC


Power N/A

Power N/A

N/A

N/A

[12]

Description

VCC. Connect to the 3.3-V power source.

VCC. Connect to the 3.3-V power source.

3

27

49

58

65

80

50

65

93 75

116 94

125 99

2

21

39

48

35

–

48

–

4

7

19

–

33

28

–

41

–

53

56

12

–

26

4B GND

1H GND

– GND

7D GND

8D GND

– GND

4C GND

– GND

4A GND

Ground N/A

Ground N/A

Ground N/A

Ground N/A

Ground N/A

Ground N/A

Ground N/A

Ground N/A

Ground N/A

N/A

Ground

N/A

Ground

N/A

Ground

N/A

Ground

N/A

Ground

N/A

Ground

N/A

Ground

N/A

Ground

N/A

Ground

14

15

16

13

14

15

–

–

–

–

–

–

–

–

–

NC

NC

NC

N/A

N/A

N/A

N/A

N/A

N/A

N/A No Connect. This pin must be left open.



4. Register Summary

FX2LP register bit definitions are described in the FX2LP TRM in greater detail.

Table 11. FX2LP Register Summary

Hex Size Name

GPIF Waveform Memories

E400 128 WAVEDATA

Description

GPIF Waveform

Descriptor 0, 1, 2, 3 data

D7

b7

E480 128 reserved

GENERAL CONFIGURATION

E50D GPCR2

E600 1 CPUCS

General Purpose Configuration Register 2 reserved

CPU Control & Status 0

E601 1 IFCONFIG

E602 1

E603 1

E604 1

E605 1

E606 1

E607 1

E608 1

E609 1

E60A 1

PINFLAGSAB

PINFLAGSCD

FIFORESET

BREAKPT

BPADDRH

BPADDRL

UART230

[13]

[13]

[13]

FIFOPINPOLAR

REVID

[13]

D6

0

b6

reserved

Interface Configuration

(Ports, GPIF, slave FIFOs)

IFCLKSRC 3048MHZ

FLAGB3 FLAGB2 Slave FIFO FLAGA and

FLAGB Pin Configuration

Slave FIFO FLAGC and

FLAGD Pin Configuration

FLAGD3 FLAGD2

0 Restore FIFOS to default state

NAKALL

Breakpoint Control

Breakpoint Address H

Breakpoint Address L

230 Kbaud internally generated ref. clock

0

A15

A7

0

0

A14

A6

0

Slave FIFO Interface pins polarity

0

Chip Revision rv7

0 rv6

E60B 1

E60C 1

3

E610 1

E611 1

E612 1

E613 1

E614 1

E615 1

REVCTL

[13]

UDMA

Chip Revision Control

GPIFHOLDAMOUNT MSTB Hold Time

(for UDMA) reserved

ENDPOINT CONFIGURATION

EP1OUTCFG

EP1INCFG

Endpoint 1-OUT

Configuration

Endpoint 1-IN

Configuration

EP2CFG

EP4CFG

EP6CFG

0

0

VALID

VALID

Endpoint 2 Configuration VALID



EP8CFG Endpoint 8 Configuration VALID

0

0

0

0

DIR

DIR

DIR

DIR

D5

0

0

A13

A5

0 rv5

0

0

b5

FLAGB1

FLAGD1

PKTEND

TYPE1

TYPE1

TYPE1

TYPE1

TYPE1

TYPE1

D4

0

0

A12

A4

0 rv4

0

0

b4

FLAGB0

FLAGD0

SLOE

TYPE0

TYPE0

TYPE0

TYPE0

TYPE0

TYPE0

D3 reserved FULL_SPEE

D_ONLY reserved reserved

PORTCSTB CLKSPD1 CLKSPD0 CLKINV

IFCLKOE IFCLKPOL ASYNC GSTATE

FLAGA3

FLAGC3

EP3

BREAK

A11

A3

0

SLRD rv3

0

0

0

0

SIZE

0

SIZE

0

b3

D2

EP2

0

b1

D0

b0

reserved

FLAGA0

FLAGC0

EP0

0

0

Default Access

xxxxxxxx RW

00000000 R

00000000 RW

00000000 RW xxxxxxxx W

BPPULSE BPEN

A10 A9

A2

0

A1

0

A8

A0

00000000 rrrrbbbr xxxxxxxx RW xxxxxxxx RW

230UART1 230UART0 00000000 rrrrrrbb rv2

0

0

0

0

0

0

0

0

b2

FLAGA2

FLAGC2

SLWR

D1 reserved

CLKOE

IFCFG1

FLAGA1

FLAGC1

EP1

EF rv1 dyn_out

HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb

0

BUF1

0

BUF1

0

8051RES

IFCFG0

FF rv0 enh_pkt

BUF0

0

BUF0

0

00000010 rrbbbbbr

10000000 RW

00000000 rrbbbbbb

RevA

00000001

R

00000000 rrrrrrbb

10100000 brbbrrrr

10100000 brbbrrrr

10100010 bbbbbrbb

10100000 bbbbrrrr

11100010 bbbbbrbb

11100000 bbbbrrrr


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 11. FX2LP Register Summary (continued)

Hex Size

2

E618 1

E619 1

E61A 1

E61B 1

Name

reserved

EP2FIFOCFG

[13]

EP4FIFOCFG

[13]

EP6FIFOCFG

[13]

EP8FIFOCFG

[13]

E61C 4

E620 1

E621 1

E622 1

E623 1

E624 1

E625 1

E626 1

E627 1

E628 1

E629 1

E62A 1

Description

Endpoint 2 / slave FIFO configuration



Endpoint 8 / slave FIFO configuration reserved

EP2AUTOINLENH

[13

Endpoint 2 AUTOIN

Packet Length H

EP2AUTOINLENL

[13]

Endpoint 2 AUTOIN

Packet Length L

EP4AUTOINLENH

[13]

Endpoint 4 AUTOIN

Packet Length H

EP4AUTOINLENL

[13]

Endpoint 4 AUTOIN

Packet Length L

EP6AUTOINLENH

[13]

Endpoint 6 AUTOIN

Packet Length H

EP6AUTOINLENL

[13]

Endpoint 6 AUTOIN

Packet Length L

EP8AUTOINLENH

[13]

Endpoint 8 AUTOIN

Packet Length H

EP8AUTOINLENL

[13]

Endpoint 8 AUTOIN

Packet Length L

ECCCFG

ECCRESET

ECC1B0

ECC Configuration

ECC Reset

ECC1 Byte 0 Address

0

0

0

0

0

PL7

0

PL7

0

PL7

0

PL7

b7

0 x

LINE15

INFM1

INFM1

INFM1

INFM1

0

PL6

0

PL6

0

PL6

0

PL6

b6

0 x

LINE14

0

PL5

0

PL5

0

PL5

0

PL5

0 x

LINE13

OEP1

OEP1

OEP1

OEP1

b5

0

PL4

0

PL4

0

PL4

0

PL4

0 x

LINE12

b4 b3

AUTOOUT AUTOIN

AUTOOUT AUTOIN

AUTOOUT AUTOIN

AUTOOUT AUTOIN

b2

ZEROLENIN 0

ZEROLENIN 0

ZEROLENIN 0

ZEROLENIN 0

b1

0

PL3

0

PL3

0

PL3

0

PL3

0 x

LINE11

PL10

PL2

0

PL2

PL10

PL2

0

PL2

0 x

LINE10

PL9

PL1

PL9

PL1

PL9

PL1

PL9

PL1

0 x

LINE9

Note

13. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”

PL8

PL0

PL8

PL0

PL8

PL0

PL8

PL0

ECCM x

LINE8

b0 Default Access

WORDWIDE 00000101 rbbbbbrb




00000010 rrrrrbbb

00000000 RW

00000010 rrrrrrbb

00000000 RW

00000010 rrrrrbbb

00000000 RW

00000010 rrrrrrbb

00000000 RW

00000000 rrrrrrrb

00000000 W

00000000 R


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


E630

F.S.

E631

H.S.

E631

F.S

E632

H.S.

E632

F.S

E633

H.S.

E633

F.S

E634

H.S.

E634

F.S

E635

H.S.

E635

F.S

E636

H.S.

Hex Size

E62B 1

E62C 1

Name

ECC1B1

ECC1B2

E62D 1

E62E 1

E62F 1

E630

H.S.

E636

F.S

E637

H.S.

E637

F.S

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

8

E640 1

ECC2B0

ECC2B1

ECC2B2

EP2FIFOPFH

[13]

EP2FIFOPFH

[13]

EP2FIFOPFL

[13]

EP2FIFOPFL

[13]

EP4FIFOPFH

[13]

EP4FIFOPFH

[13]

EP4FIFOPFL

[13]

EP4FIFOPFL

[13]

EP6FIFOPFH

[13]

EP6FIFOPFH

[13]

EP6FIFOPFL

[13]

EP6FIFOPFL

[13]

EP8FIFOPFH

[13]

EP8FIFOPFH

[13]

EP8FIFOPFL

[13]

EP8FIFOPFL

[13]

reserved

EP2ISOINPKTS

E641 1

E642 1

E643 1

EP4ISOINPKTS

EP6ISOINPKTS

EP8ISOINPKTS

Description

ECC1 Byte 1 Address

ECC1 Byte 2 Address

ECC2 Byte 0 Address

ECC2 Byte 1 Address

ECC2 Byte 2 Address

Endpoint 2 / slave FIFO

Programmable Flag H


Programmable Flag H


Programmable Flag L


Programmable Flag L


Programmable Flag H


Programmable Flag H


Programmable Flag L


Programmable Flag L


Programmable Flag H


Programmable Flag H


Programmable Flag L


Programmable Flag L


Programmable Flag H


Programmable Flag H


Programmable Flag L


Programmable Flag L

LINE7

COL5

b7

LINE15

LINE7

COL5

DECIS

DECIS

PFC7

IN:PKTS[1]

OUT:PFC7

DECIS

DECIS

PFC7

PFC7

IN:PKTS[1]

OUT:PFC7

DECIS

DECIS

PFC7

IN: PKTS[1]

OUT:PFC7

COL4

COL4

PFC6

PFC6

PFC6

PFC6

b6

LINE6

LINE14

LINE6

PKTSTAT

PKTSTAT

IN:PKTS[0]

OUT:PFC6

PKTSTAT

PKTSTAT

IN:PKTS[0]

OUT:PFC6

PKTSTAT

PKTSTAT

LINE5

COL3

b5

LINE13

LINE5

COL3

IN:PKTS[2]

OUT:PFC12

COL2

COL2

b4

LINE4

LINE12

LINE4

IN:PKTS[1]

OUT:PFC11

b3

LINE3

COL1

b2

LINE2

COL0

LINE11

LINE3

LINE10

LINE2

COL1 COL0

IN:PKTS[0]

OUT:PFC10

0

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

PFC5

PFC5

0

0

PFC5

PFC5

PFC5

0

0

PFC5

IN: PKTS[0]

OUT:PFC6

PFC5

PFC4

PFC4

IN: PKTS[1]

OUT:PFC10

OUT:PFC10 OUT:PFC9 0

PFC4

IN: PKTS[1]

OUT:PFC7

DECIS

DECIS

IN: PKTS[0]

OUT:PFC6

PKTSTAT

PFC5

PKTSTAT

PFC4 PFC3 PFC2

IN:PKTS[2]

OUT:PFC12

IN:PKTS[1]

OUT:PFC11

IN:PKTS[0]

OUT:PFC10

0

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

PFC4

PFC4

IN: PKTS[1]

OUT:PFC10

IN: PKTS[0]

OUT:PFC9

IN: PKTS[0]

OUT:PFC9

PFC2

PFC2

0

PFC2

0

OUT:PFC10 OUT:PFC9 0

PFC4

PFC4

PFC3

PFC3

PFC3

PFC3

PFC3

PFC3

PFC3

PFC2

PFC2

PFC2

PFC2

EP2 (if ISO) IN Packets per frame (1-3)

AADJ


AADJ


AADJ


AADJ

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

E644 4

E648 1

E649 7

E650 1

E651 1 reserved

INPKTEND

[13]

OUTPKTEND

[13]

INTERRUPTS

EP2FIFOIE

[13]

EP2FIFOIRQ

[13,14]

Force IN Packet End Skip

Force OUT Packet End Skip

0

0

0

0

0

0

0

0

0

0

0

0

EP3

EP3

EP2

EP2

EDGEPF PF

0 PF

E652 1

E653 1

E654 1

E655 1

E656 1

E657 1

E658 1

E659 1

E65A 1

E65B 1

E65C 1

EP4FIFOIE

[13]

EP4FIFOIRQ

[13,14]

EP6FIFOIE

[13]

EP6FIFOIRQ

[13,14]

EP8FIFOIE

[13]

EP8FIFOIRQ

[13,14]

IBNIE

IBNIRQ

[14]

NAKIE

NAKIRQ

[14]

USBIE

Endpoint 2 slave FIFO Flag

Interrupt Enable

0


Interrupt Request

0


Interrupt Enable

0


Interrupt Request

0


Interrupt Enable

0


Interrupt Request

0


Interrupt Enable

0


Interrupt Request

0

0 IN-BULK-NAK Interrupt

Enable

IN-BULK-NAK interrupt

Request

0

Endpoint Ping-NAK / IBN

Interrupt Enable

Endpoint Ping-NAK / IBN

Interrupt Request

USB Int Enables

EP8

EP8

0

0

0

0

0

0

0

0

0

EP6

EP6

EP0ACK

0

0

0

0

0

0

EP8

EP8

EP4

EP4

0

0

0

0

0

0

EP6

EP6

EP2

EP2

HSGRANT URES

EDGEPF PF

0 PF

EDGEPF PF

0 PF

EDGEPF PF

0

EP4

EP4

EP1

EP1

SUSP

PF

EP2

EP2

EP0

EP0

SUTOK

INPPF1

INPPF1

INPPF1

INPPF1

EP0

EP0

FF

FF

FF

FF

FF

FF

FF

FF

EP0

EP0

IBN

IBN

SUDAV

EP1

EP1

EF

EF

EF

EF

EF

EF

EF

EF

0

0

EP1

EP1

SOF

PFC9

PFC1

PFC1

0

0

PFC1

PFC1

PFC9

PFC1

PFC1

0

0

PFC1

PFC1

PFC9

b1

LINE1

LINE17

LINE9

LINE1

0

PFC9

b0

LINE0

LINE16

LINE8

LINE0

0

PFC8

Default Access

00000000 R

00000000 R

00000000 R

00000000 R

00000000 R

10001000 bbbbbrbb

PFC0

PFC8

PFC8

PFC0

PFC0

IN:PKTS[2]

OUT:PFC8

PFC0

10001000 bbbbbrbb

00000000 RW

PFC0

PFC8

00000000 RW

10001000 bbrbbrrb

PFC8

PFC0

PFC0

PFC8

10001000 bbrbbrrb

00000000 RW

00000000 RW

00001000 bbbbbrbb

IN:PKTS[2]

OUT:PFC8

PFC0

00001000 bbbbbrbb

00000000 RW

00000000 RW

00001000 bbrbbrrb

00001000 bbrbbrrb

00000000 RW

00000000 RW

INPPF0

INPPF0

INPPF0

INPPF0

00000001 brrrrrbb

00000001 brrrrrrr

00000001 brrrrrbb

00000001 brrrrrrr xxxxxxxx W xxxxxxxx W

00000000 RW

00000000 rrrrrbbb

00000000 RW

00000000 rrrrrbbb

00000000 RW

00000000 rrrrrbbb

00000000 RW

00000000 rrrrrbbb

00000000 RW

00xxxxxx rrbbbbbb

00000000 RW xxxxxx0x bbbbbbrb

00000000 RW

Note

14. The register can only be reset; it cannot be set.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

E68E 1

E68F 1

E690 1

E691 1

E692 2

E694 1

E695 1

E696 2

E698 1

E699 1

E69A 2

E69C 1

E69D 1

E69E 2


Hex Size

E65D 1

Name

USBIRQ

[14]

E65E 1 EPIE

E65F 1

E660 1

E661 1

E662 1

E663 1

E664 1

E665 1

E666 1

E667 1

E668 1

E669 7

E670 1

EPIRQ

[14]

GPIFIE

[13]

GPIFIRQ

[13]

USBERRIE

USBERRIRQ

[14]

ERRCNTLIM

CLRERRCNT

INT2IVEC

INT4IVEC

INTSET-UP reserved

INPUT / OUTPUT

PORTACFG

Description

USB Interrupt Requests 0

Endpoint Interrupt

Enables

EP8

Endpoint Interrupt

Requests

EP8

b7

GPIF Interrupt Enable 0

GPIF Interrupt Request 0

USB Error Interrupt

Enables

ISOEP8

USB Error Interrupt

Requests

ISOEP8

USB Error counter and limit EC3

Clear Error Counter EC3:0 x

0 Interrupt 2 (USB)

Autovector

Interrupt 4 (slave FIFO &

GPIF) Autovector

Interrupt 2&4 setup

1

0

FLAGD

E671 1

E672 1

PORTCCFG

PORTECFG

I/O PORTA Alternate

Configuration

I/O PORTC Alternate

Configuration

I/O PORTE Alternate

Configuration

GPIFA7

GPIFA8

E673 4

E677 1

E678 1 reserved reserved

I

2

CS

E679 1

E67A 1

E67B 1

E67C 1

I2DAT

I

2

CTL

XAUTODAT1

XAUTODAT2

I²C Bus

Control & Status

I²C Bus

Data

I²C Bus

Control

Autoptr1 MOVX access, when APTREN=1

Autoptr2 MOVX access, when APTREN=1

START d7

0

D7

D7

E67D 1

E67E 1

E67F 1

E680 1

E681 1

E682 1

E683 1

E684 1

E685 1

E686 1

E687 1

E688 2

UDMA CRC

UDMACRCH

[13]

UDMACRCL

[13]

UDMACRC-

QUALIFIER

USB CONTROL

USBCS

SUSPEND

WAKEUPCS

TOGCTL

USBFRAMEH

USBFRAMEL

MICROFRAME

FNADDR reserved

UDMA CRC MSB

UDMA CRC LSB

UDMA CRC Qualifier

USB Control & Status

Put chip into suspend

HSM x

Wakeup Control & Status WU2

Toggle Control Q

USB Frame count H

USB Frame count L

Microframe count, 0-7

USB Function address

0

FC7

0

0

b6

EP0ACK

EP6

EP6

0

0

ISOEP6

ISOEP6

EC2 x

I2V4

0

0

SLCS

GPIFA6

T2EX

STOP d6

0

D6

D6

CRC15 CRC14

CRC7 CRC6

QENABLE 0

0 x

WU

S

0

FC6

0

FA6

E68A 1

E68B 1

E68C 1

E68D 1

ENDPOINTS

EP0BCH

[13]

EP0BCL

[13]

reserved

EP1OUTBC

Endpoint 0 Byte Count H (BC15)

Endpoint 0 Byte Count L (BC7)

Endpoint 1 OUT Byte

Count

0

(BC14)

BC6

BC6 reserved

EP1INBC

EP2BCH

[13]

EP2BCL

[13]

reserved

EP4BCH

[13]

EP4BCL

[13]

reserved

EP6BCH

[13]

EP6BCL

[13]

reserved

EP8BCH

[13]

EP8BCL

[13]

reserved

Endpoint 1 IN Byte Count 0

Endpoint 2 Byte Count H 0

Endpoint 2 Byte Count L BC7/SKIP







BC6

0

BC6

0

BC6

0

BC6

0

BC6

b5 b4

HSGRANT URES

EP4 EP2

EP4 EP2

0

0

ISOEP4

0

0

ISOEP2

ISOEP4

EC1 x

I2V3

I4V3

0

ISOEP2

EC0 x

I2V2

I4V2

0

0

GPIFA5

INT6

LASTRD d5

0

D5

D5

CRC13

CRC5

0

0

GPIFA4

0

GPIFA3

0

GPIFA2

RXD1OUT RXD0OUT T2OUT

0 x

WU2POL

R

0

FC5

0

FA5

0 x

WUPOL

I/O

0

FC4

0

FA4

(BC13)

BC5

BC5

BC5

0

BC5

0

BC5

0

BC5

0

BC5

ID1 d4

0

D4

D4

CRC12

CRC4

0

(BC12)

BC4

BC4

BC4

0

BC4

0

BC4

0

BC4

0

BC4

ID0 d3

0

D3

D3

0

LIMIT3 x

I2V1

I4V1

AV2EN

0

0

0

b3

SUSP

EP1OUT

EP1OUT

0

LIMIT2 x

I2V0

I4V0

0

0

0

0

b2

SUTOK

EP1IN

EP1IN

b1

SOF

EP0OUT

EP0OUT

GPIFWF

GPIFWF

0

0

LIMIT1 x

0

0

INT4SRC

b0

SUDAV

EP0IN

EP0IN 0

Default Access

0xxxxxxx rbbbbbbb

00000000 RW

RW

GPIFDONE 00000000 RW

GPIFDONE 000000xx RW

ERRLIMIT 00000000 RW

ERRLIMIT 0000000x bbbbrrrb

LIMIT0 x

0 xxxx0100 rrrrbbbb xxxxxxxx W

00000000 R

0

AV4EN

10000000 R

00000000 RW

DISCON x

0

EP3

0

FC3

0

FA3

NOSYNSOF RENUM x x

DPEN

EP2

WU2EN

EP1

FC10

FC2

MF2

FA2

FC9

FC1

MF1

FA1

(BC11)

BC3

BC3

BC3

0

BC3

0

BC3

0

BC3

0

BC3

BERR d2

0

D2

D2

(BC10)

BC2

BC2

BC2

BC10

BC2

0

BC2

BC10

BC2

0

BC2

INT1

GPIFA1

T1OUT

BC1

BC9

BC1

BC9

BC1

BC9

BC1

BC9

BC1

ACK d1

STOPIE

D1

D1

(BC9)

BC1

BC1

INT0

GPIFA0

T0OUT

DONE d0

400KHZ

D0

D0

00000000 RW

00000000 RW

00000000 RW

000xx000 bbbrrrrr xxxxxxxx RW

00000000 RW xxxxxxxx RW xxxxxxxx RW

CRC11

CRC3

QSTATE

CRC10 CRC9 CRC8 01001010 RW

CRC2 CRC1 CRC0 10111010 RW

QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb

(BC8)

BC0

BC0

BC0

BC8

BC0

BC8

BC0

BC8

BC0

BC8

BC0

SIGRSUME x0000000 rrrrbbbb x xxxxxxxx W

WUEN

EP0 xx000101 bbbbrbbb x0000000 rrrbbbbb

FC8

FC0

MF0

FA0

00000xxx R xxxxxxxx R

00000xxx R

0xxxxxxx R xxxxxxxx RW xxxxxxxx RW

0xxxxxxx RW

0xxxxxxx RW

00000xxx RW xxxxxxxx RW

000000xx RW xxxxxxxx RW

00000xxx RW xxxxxxxx RW

000000xx RW xxxxxxxx RW


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


Hex Size

E6A0 1

E6A1 1

E6A2 1

E6A3 1

E6A4 1

E6A5 1

E6A6 1

E6A7 1

E6A8 1

E6A9 1

E6AA 1

E6AB 1

E6AC 1

E6AD 1

E6AE 1

E6AF 1

E6B0 1

E6B1 1

E6B2 1

E6B3 1

E6B4 1

E6B5 1

2

E6B8 8

E6C0 1

E6C1 1

E6C2 1

E6C3 1

E6C4 1

E6C5 1

E6C6 1

E6C7 1

E6C8 1

E6C9 1

E6CA 1

E6CB 1

E6CC 1

E6CD 1

E6CE 1

EP0CS

Name

EP1OUTCS

EP1INCS

EP2CS

EP4CS

EP6CS

Description

Endpoint 0 Control and Status

HSNAK

Endpoint 1 OUT Control and Status

0

b7

Endpoint 1 IN Control and

Status

0


0


0


0

0

0

0

0

b6

NPAK2

NPAK2

0

0

0

b5

NPAK1

NPAK1

NPAK1

0

0

0

b4

NPAK0

NPAK0

NPAK0

0

0

0

FULL

FULL

FULL

b3

0

0

0

b2

EMPTY

EMPTY

EMPTY

EP8CS

EP2FIFOFLGS

EP4FIFOFLGS

EP6FIFOFLGS

EP8FIFOFLGS

EP2FIFOBCH

EP2FIFOBCL

EP4FIFOBCH

EP4FIFOBCL

EP6FIFOBCH

EP6FIFOBCL

EP8FIFOBCH

EP8FIFOBCL

SUDPTRH

SUDPTRL

SUDPTRCTL


0

0 Endpoint 2 slave FIFO

Flags

Endpoint 4 slave FIFO

Flags

0

0 Endpoint 6 slave FIFO

Flags

Endpoint 8 slave FIFO

Flags

Endpoint 2 slave FIFO total byte count H

Endpoint 2 slave FIFO total byte count L

0

0

BC7





0

BC7

0

BC7



0

BC7

Setup Data Pointer high address byte

A15

Setup Data Pointer low address byte

A7

Setup Data Pointer Auto

Mode

0

0

0

0

0

0

0

BC6

0

BC6

0

BC6

0

BC6

A14

A6

0

NPAK1

0

0

0

0

0

BC5

0

BC5

0

BC5

0

BC5

A13

A5

0

NPAK0

0

0

0

0

BC12

BC4

0

BC4

0

BC4

0

BC4

A12

A4

0

FULL

0

0

0

0

BC11

BC3

0

BC3

BC11

BC3

0

BC3

A11

A3

0

EMPTY

PF

PF

PF

PF

BC10

BC2

BC10

BC2

BC10

BC2

BC10

BC2

A10

A2

0 reserved

SET-UPDAT 8 bytes of setup data

SET-UPDAT[0] =

bmRequestType

SET-UPDAT[1] = bmRequest

D7 D6 D5 D4 D3 D2

SET-UPDAT[2:3] = wValue

SET-UPDAT[4:5] = wIndex

SET-UPDAT[6:7] = wLength

GPIF

GPIFWFSELECT

GPIFIDLECS

GPIFIDLECTL

GPIFCTLCFG

GPIFADRH

[13]

GPIFADRL

[13]

FLOWSTATE

FLOWSTATE

Waveform Selector

GPIF Done, GPIF IDLE drive mode

GPIF Address H

GPIF Address L

SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1

DONE

Inactive Bus, CTL states 0

CTL Drive Type TRICTL

0

GPIFA7

0

0

0

0

GPIFA6

0

CTL5

CTL5

0

GPIFA5

0

CTL4

CTL4

0

GPIFA4

0

CTL3

CTL3

0

GPIFA3

FIFOWR0

0

CTL2

CTL2

0

GPIFA2

FLOWLOGIC

FLOWEQ0CTL

Flowstate Enable and

Selector

Flowstate Logic

CTL-Pin States in

Flowstate

(when Logic = 0)

FSE

LFUNC1

CTL0E3

0

LFUNC0

CTL0E2

0

TERMA2

CTL0E1/

CTL5

0

TERMA1

CTL0E0/

CTL4

0

TERMA0

CTL3

FS2

TERMB2

CTL2

FLOWEQ1CTL

FLOWHOLDOFF

FLOWSTB

FLOWSTBEDGE

CTL-Pin States in Flowstate (when Logic = 1)

Holdoff Configuration

Flowstate Strobe

Configuration

Flowstate Rising/Falling

Edge Configuration

CTL0E3

0

FLOWSTBPERIOD Master-Strobe Half-Period D7

GPIFTCB3

[13]

GPIF Transaction Count

Byte 3

TC31

CTL0E2

0

D6

TC30

CTL0E1/

CTL5

0

D5

TC29

CTL0E0/

CTL4

0

D4

TC28

CTL3 CTL2

HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE HOCTL2

SLAVE RDYASYNC CTLTOGL SUSTAIN 0 MSTB2

0

D3

TC27

0

D2

TC26

D1

BC1

A9

A1

0

BC1

BC9

BC1

BC9

EF

BC9

BC1

BC9

0

EF

EF

EF

0

0

0

BUSY

b1

BUSY

BUSY

FIFORD1

0

CTL1

CTL1

0

GPIFA1

FS1

TERMB1

CTL1

CTL1

HOCTL1

MSTB1

FALLING

D1

TC25

b0

STALL

STALL

STALL

STALL

STALL

STALL

Default Access

10000000 bbbbbbrb

00000000 bbbbbbrb

00000000 bbbbbbrb

00101000 rrrrrrrb

00101000 rrrrrrrb

00000100 rrrrrrrb

FF

BC8

BC0

BC8

STALL

FF

FF

FF

00000100 rrrrrrrb

00000010 R

00000010 R

00000110 R

00000110 R

00000000 R

00000000 R

00000000 R

BC0

BC8

BC0

BC8

00000000 R

00000000 R

00000000 R

00000000 R

BC0

A8

00000000 R xxxxxxxx RW

0 xxxxxxx0 bbbbbbbr

SDPAUTO 00000001 RW

D0

FIFORD0

IDLEDRV

CTL0

CTL0

GPIFA8

GPIFA0

FS0

TERMB0

CTL0

11100100 RW

10000000 RW

11111111 RW

00000000 RW

00000000 RW

00000000 RW

00000000 brrrrbbb

00000000 RW

00000000 RW

CTL0

HOCTL0

MSTB0

RISING

D0

TC24 xxxxxxxx R

00000000 RW

00010010 RW

00100000 RW

00000001 rrrrrrbb

00000010 RW

00000000 RW


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


Hex Size

E6CF 1

E6D0 1

E6D1 1

2

E6D2 1

E6D3 1

E6D4 1

3

E6DA 1

E6DB 1

E6DC 1

3

E6E2 1

E6E3 1

E6E4 1

3

E6EA 1

E6EB 1

E6EC 1

3

E6F0 1

E6F1 1

E6F2 1

E6F3 1

Name

GPIFTCB2

GPIFTCB1

GPIFTCB0

[13]

[13]

[13]

Description


Byte 2


Byte 1


Byte 0

TC23

TC15

TC7

b7

reserved reserved reserved

EP2GPIFFLGSEL

[13]

EP2GPIFPFSTOP

Endpoint 2 GPIF Flag select

Endpoint 2 GPIF stop transaction on prog. flag

0

0

Endpoint 2 GPIF Trigger x EP2GPIFTRIG

[13]


EP4GPIFFLGSEL

[13]

EP4GPIFPFSTOP


Endpoint 4 GPIF stop transaction on GPIF Flag

0

0


[13]


EP6GPIFFLGSEL

[13]

EP6GPIFPFSTOP



0

0


[13]


EP8GPIFFLGSEL

[13]

EP8GPIFPFSTOP



0

0

EP8GPIFTRIG

[13]

reserved

XGPIFSGLDATH

Endpoint 8 GPIF Trigger x

XGPIFSGLDATLX

GPIF Data H

(16-bit mode only)

D15

Read/Write GPIF Data L & trigger transaction

D7

XGPIFSGLDATLNOX Read GPIF Data L, no transaction trigger

GPIFREADYCFG Internal RDY, Sync/Async,

RDY pin states

D7

INTRDY

TC22

b6

TC14

TC6

0

0 x

0

0 x

0

0 x

0

0 x

D14

D6

D6

SAS

E6F4 1

E6F5 1

E6F6 2

E740 64

E780 64

E7C0 64

GPIFREADYSTAT

GPIFABORT reserved

ENDPOINT BUFFERS

GPIF Ready Status 0

Abort GPIF Waveforms x

EP0BUF

EP10UTBUF

EP1INBUF

E800 2048 reserved

F000 1024 EP2FIFOBUF

F400 512 EP4FIFOBUF

EP0-IN/-OUT buffer

EP1-OUT buffer

EP1-IN buffer

D7

D7

D7

512/1024 byte EP 2 / slave

FIFO buffer (IN or OUT)

D7

512 byte EP 4 / slave FIFO buffer (IN or OUT)

D7

F600 512 reserved

F800 1024 EP6FIFOBUF

FC00 512 EP8FIFOBUF

512/1024 byte EP 6 / slave

FIFO buffer (IN or OUT)

D7

512 byte EP 8 / slave FIFO buffer (IN or OUT)

D7

FE00 512 reserved

0 x

D6

D6

D6

D6

D6

D6

D6

0

0 x

0

0 x

0

0 x

RDY5 x

D5

D5

D5

D5

D5

TC21

b5

TC13

TC5

0

0 x

D13

D5

D5

TCXRDY5

D12

D4

D4

0

0

0 x

D5

D5

0

0 x

0

0 x

0

0 x

TC20

b4

TC12

TC4

TC19

b3

TC11

TC3

TC18

b2

TC10

TC2

TC17

b1

TC9

TC1

TC16

b0

TC8

TC0

RDY4 x

D4

D4

D4

D4

D4

D4

D4

0

0 x

0

0 x

0

0 x

0

0 x

D11

D3

D3

0

RDY3 x

D3

D3

D3

D3

D3

D3

D3

0

0 x

0

0 x

0

0 x

0

0 x

D10

D2

D2

0

RDY2 x

D2

D2

D2

D2

D2

D2

D2

FS1

0 x

FS1

0 x

FS1

0 x

D9

D1

D1

0

FS1

0 x

RDY1 x

D1

D1

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Default Access

00000000 RW

00000000 RW

00000001 RW

00000000 RW

FS0 00000000 RW

FIFO2FLAG 00000000 RW x xxxxxxxx W

FS0 00000000 RW


FS0 00000000 RW


D8

D0

D0

0

FS0 00000000 RW

FIFO8FLAG 00000000 RW x xxxxxxxx W xxxxxxxx RW xxxxxxxx RW xxxxxxxx R

00000000 bbbrrrrr

RDY0 x

D0

D0

00xxxxxx R xxxxxxxx W xxxxxxxx RW xxxxxxxx RW xxxxxxxx RW

RW xxxxxxxx RW xxxxxxxx RW xxxxxxxx RW xxxxxxxx RW


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


Hex Size

xxxx

Name

I²C Configuration Byte

Description

0

b7 b6

DISCON

8E

8F

90

91

92

8A

8B

8C 1

8D 1

1

1

1

1

1

1

1

84

85

86

87

88

80

81

82

83

1

1

1

1

1

1

1

1

1

89

93

98

99

9A

9B

1

5

1

1

1

1

Special Function Registers (SFRs)

IOA

[15]

Port A (bit addressable) D7

SP

DPL0

DPH0

DPL1

[15]

DPH1

[15]

DPS

[15]

PCON

TCON

Stack Pointer

Data Pointer 0 L

Data Pointer 0 H

Data Pointer 1 L

Data Pointer 1 H

Data Pointer 0/1 select

Power Control

D7

A7

A15

A7

A15

0

SMOD0

TF1

TMOD

Timer/Counter Control

(bit addressable)

Timer/Counter Mode

Control

GATE

TL0

TL1

TH0

TH1

CKCON

[15]

reserved

IOB

[15]

EXIF

[15]

MPAGE

[15]

Timer 0 reload L

Timer 1 reload L

Timer 0 reload H

Timer 1 reload H

Clock Control

Port B (bit addressable)

External Interrupt Flag(s)

Upper Addr Byte of MOVX using @R0 / @R1

D7

D7

D15

D15 x

D7

IE5

A15 reserved

SCON0

SBUF0

AUTOPTRH1

AUTOPTRL1

[15]

[15]

Serial Port 0 Control

(bit addressable)

SM0_0

Serial Port 0 Data Buffer D7

Autopointer 1 Address H A15

Autopointer 1 Address L A7

CT

D6

D6

D14

D14 x

D6

IE4

A14

SM1_0

D6

A14

A6

A0

A1

A2

A3

A8

9C 1

9D 1

9E

9F

1

1

1

5

1

1

1 reserved

AUTOPTRH2

[15]

AUTOPTRL2

[15]

reserved

IOC

[15]

INT2CLR

[15]

INT4CLR

[15]

reserved

IE

Autopointer 2 Address H A15

Autopointer 2 Address L A7

Port C (bit addressable) D7

Interrupt 2 clear x

Interrupt 4 clear x

A14

A6

D6 x x

Interrupt Enable

(bit addressable)

EA ES1

A9 1

AA 1

AB 1

AC 1 reserved

EP2468STAT

[15]

EP24FIFOFLGS

[15]

EP68FIFOFLGS

[15]

Endpoint 2,4,6,8 status flags

Endpoint 2,4 slave FIFO status flags

Endpoint 6,8 slave FIFO status flags

EP8F

0

0

EP8E

EP4PF

EP8PF

AD 2

AF 1

B0

B1

1

1

B2

B3

B4

B5

B6

B7

B8

1

1

1

1

1

1

1 reserved

AUTOPTRSETUP

[15]

IOD

[15]

IOE

[15]

OEA

[15]

OEB

[15]

OEC

[15]

OED

[15]

OEE

[15]

reserved

IP

Autopointer 1&2 setup 0

Port D (bit addressable) D7

Port E

(NOT bit addressable)

D7

Port A Output Enable

Port B Output Enable

Port C Output Enable

D7

D7

D7

Port D Output Enable

Port E Output Enable

D7

D7

0

D6

D6

D6

D6

D6

D6

D6

Interrupt Priority (bit addressable)

1 PS1

B9 1

BA 1

BB 1 reserved

EP01STAT

[15]

GPIFTRIG

[15, 13]

Endpoint 0&1 Status

Endpoint 2,4,6,8 GPIF slave FIFO Trigger

0

DONE

0

0

BC 1

BD 1 reserved

GPIFSGLDATH

[15]

GPIF Data H (16-bit mode only)

D15 D14

Notes

15. SFRs not part of the standard 8051 architecture.

16. If no EEPROM is detected by the SIE then the default is 00000000.

D6

D6

A6

A14

0 x

A6

A14

TR1

0

0

0

b5

EP6F

EP4EF

EP8EF

D13

0

D5

D5

D5

D5

D5

D5

D5

PT2

M1

D5

D5

D13

D13

T2M

D5

D5

A5

A13

0

1

A5

A13

TF0

D5

I²CINT

A13

SM2_0

D5

A13

A5

A13

A5

D5 x x

ET2

0

0

REN_0

D4

A12

A4

A12

A4

D4 x x

ES0

EP6E

EP4FF

EP8FF

0

D4

D4

D4

D4

D4

D4

D4

PS0

D12

0

b4

0

b3

0

b2

M0

D4

D4

D12

D12

T1M

D4

D4

A4

A12

0

1

A4

A12

TR0

D4

USBNT

A12

0 x

D3

D3

A3

A11

A3

A11

IE1

GATE

D3

D3

D11

D11

T0M

D3

1

A11

0 x

D2

D2

A2

A10

A2

A10

IT1

CT

D2

D2

D10

D10

MD2

D2

0

A10

M1

D1

D1

D9

D9

MD1

0 x

A1

A9

IE0

D1

D1

A1

A9

D1

0

A9

0

b1

M0

D0

D0

D8

D8

MD0

D0

D0

A0

A8

A0

A8

SEL

IDLE

IT0

D0

0

A8

b0

400KHZ

Default Access

xxxxxxxx

[16]

n/a xxxxxxxx RW

00000111 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00110000 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00000001 RW xxxxxxxx RW

00001000 RW

00000000 RW

0

0

TB8_0

D3

A11

A3

A11

A3

D3 x x

ET1

RB8_0

D2

A10

A2

A10

A2

D2 x x

EX1

EP4F

0

0

0

D3

D3

D3

D3

D3

D3

D3

PT1

D11

EP4E

EP2PF

EP6PF

APTR2INC APTR1INC APTREN

D2 D1 D0

D2 D1 D0

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

PX1 PT0 PX0

00000110 RW xxxxxxxx RW xxxxxxxx RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

10000000 RW

EP1INBSY EP1OUTBSY EP0BSY

RW EP1 EP0

00000000 R

10000xxx brrrrbbb

D10

A9

A1

D1 x x

ET0

TI_0

D1

A9

A1

EP2F

EP2EF

EP6EF

D9

RI_0

D0

A8

A0

A8

A0

D0 x x

EX0

EP2E

EP2FF

EP6FF

D8

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW xxxxxxxx RW xxxxxxxx W xxxxxxxx W

00000000 RW

01011010 R

00100010 R

01100110 R xxxxxxxx RW


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

E9

F0

F1

F8

D1

D8

D9

E0


Hex Size

BE 1

Name

GPIFSGLDATLX

[15]

BF 1

C0 1

GPIFSGLDATL-

NOX

[15]

SCON1

[15]

Description

GPIF Data L w/ Trigger D7

GPIF Data L w/ No Trigger D7

b7

Serial Port 1 Control (bit addressable)

SM0_1

Serial Port 1 Data Buffer D7 C1

C2

C8

1

6

1

SBUF1

[15]

reserved

T2CON Timer/Counter 2 Control

(bit addressable)

TF2

C9 1

CA 1 reserved

RCAP2L D7

D6

D6

b6

SM1_1

D6

EXF2

D6

CB 1

CC 1

CD 1

CE 2

D0 1

RCAP2H

TL2

TH2 reserved

PSW

Capture for Timer 2, auto-reload, up-counter

Capture for Timer 2, auto-reload, up-counter

Timer 2 reload L

Timer 2 reload H

D7

D7

D15

Program Status Word (bit addressable)

CY

D6

D6

D14

AC

7

1

7

1 reserved

EICON

[15]

reserved

ACC

External Interrupt Control SMOD1

Accumulator (bit addressable)

D7

1

D6

E1

E8

7

1 reserved

EIE

[15]

External Interrupt Enable(s)

1 1

7

1

7

1 reserved

B reserved

EIP

[15]

B (bit addressable) D7

External Interrupt Priority

Control

1

D6

1

F9 7 reserved

1

D5

D5

D5

D13

F0

b5

D5

D5

SM2_1

D5

RCLK

ERESI

D5

D5

1

D4

D4

D4

D12

RS1

RESI

D4

EX6

D4

PX6

b4

D4

D4

REN_1

D4

TCLK

D3

D3

b3

TB8_1

D3

EXEN2

b2

D2

D2

RB8_1

D2

TR2

D1

D1

TI_1

D1

b1

CT2

D0

D0

RI_1

D0

b0

CPRL2

Default Access

xxxxxxxx RW xxxxxxxx R

00000000 RW

00000000 RW

00000000 RW

D3

D3

D3

D11

RS0

INT6

D3

EX5

D3

PX5

D2

D2

D2

D10

OV

0

D2

EX4

D2

PX4

D1

D1

D1

D9

F1

0

D1

EI²C

D1

PI²C

D0

D0

D0

D8

P

0

D0

EUSB

D0

PUSB

00000000 RW

00000000 RW

00000000 RW

00000000 RW

00000000 RW

01000000 RW

00000000 RW

11100000 RW

00000000 RW

11100000 RW

R = all bits read-only

W = all bits write-only r = read-only bit w = write-only bit b = both read/write bit


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

5. Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Storage temperature ................................ –65

C to +150 C

Ambient temperature with power supplied (commercial).......................... 0 °C to +70 °C

Ambient temperature with power supplied (industrial)....................... –40

C to + 105 C

Supply voltage to ground potential ...............–0.5 V to +4.0 V

DC input voltage to any input pin

[17]

............................ 5.25 V

DC voltage applied to outputs in high Z state ..................................... –0.5 V to V

CC

+ 0.5 V

Power dissipation ..................................................... 300 mW

Static discharge voltage............. ...............................>2000 V

Max output current, per I/O port .................................. 10 mA

Max output current, all five I/O ports

(128-pin and 100-pin packages) .................................. 50 mA

6. Operating Conditions

T

A

(ambient temperature under bias)

Commercial .................................................... 0 °C to +70 °C

T

A

(ambient temperature under bias)

Industrial ................................................... –40 °C to +105 °C

Supply voltage ..........................................+3.00 V to +3.60 V

Ground voltage ................................................................. 0 V

F

OSC

(oscillator or crystal frequency) ..... 24 MHz ± 100 ppm, parallel resonant

7. Thermal Characteristics

The following table displays the thermal characteristics of various packages:

Table 12. Thermal Characteristics

Package

56 SSOP

100 TQFP

128 TQFP

56 QFN

56 VFBGA

Ambient

Temperature (°C)

70

70

70

70

70



Jc

Junction to Case

Thermal Resistance (°C/W)

24.4

11.9

15.5

10.6

30.9



Ja

Junction to Ambient Thermal

Resistance (°C/W)

47.7

45.9

43.2

25.2

58.6

The junction temperature

 j

, can be calculated using the following equation:

 j

= P*



Ja

+

 a

Where,

P = Power



Ja

= Junction to ambient temperature (



Jc

+



Ca

)

 a

= Ambient temperature (70 °C)

The case temperature

 c

, can be calculated using the following equation:

 c

= P*



Ca

+

 a where,

P = Power



Ca

= Case to ambient temperature

 a

= Ambient temperature (70 °C)

Note

17. Do not power I/O with the chip power OFF.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

8. DC Characteristics

Table 13. DC Characteristics

Parameter

VCC

Description

Supply voltage

VCC Ramp Up 0 to 3.3 V

V

IH

V

IL

V

IH_X

V

IL_X

I

I

V

OH

V

OL

I

OH

I

OL

C

IN

Input HIGH voltage

Input LOW voltage

Crystal input HIGH voltage

Crystal input LOW voltage

Input leakage current

Output voltage HIGH

Output LOW voltage

Output current HIGH

Output current LOW

Input pin capacitance

I

SUSP

I

CC

Suspend current

CY7C68014/CY7C68016

Suspend current

CY7C68013/CY7C68015

Supply current

T

RESET

Reset time after valid power

Pin reset after powered on

8.1 USB Transceiver

USB 2.0 compliant in Full Speed and Hi-Speed modes.

–

–

–

–

–

–

0< V

IN

< V

CC

I

OUT

= 4 mA

I

OUT

= –4 mA

–

Conditions

–

Except D+/D–

D+/D–

Connected

Disconnected

Connected

Disconnected

8051 running, connected to USB HS

8051 running, connected to USB FS

V

CC

min = 3.0 V

–

–

–

–

2.4

–

–

–

Min

3.00

200

2

–0.5

2

–0.5

–

–

–

–

–

5.0

200 mA mA mA ms

s

V mA mA pF pF

A

A mA

V

V

V

A

V

Unit

V

s

V

–

0.4

4

4

10

15

380

[18]

150

[18]

1.2

[18]

1.0

[18]

85

65

–

–

Max

3.60

–

5.25

0.8

5.25

0.8

±10

–

–

300

100

–

–

–

–

–

–

–

–

Typ

3.3

–

–

0.5

0.3

50

35

–

–

Note

18. Measured at Max V

CC

, 25 °C.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9. AC Electrical Characteristics

9.1 USB Transceiver

USB 2.0 compliant in Full-Speed and Hi-Speed modes.

9.2 Program Memory Read

Figure 9-1. Program Memory Read Timing Diagram t

CL

CLKOUT

[19]

A[15..0] t

AV t

AV t

STBL t

STBH

PSEN# t

ACC1

[20]

D[7..0] t

DH

data in

OE# t

SOEL t

SCSL

CS#

Table 14. Program Memory Read Parameters

t

CL

Parameter Description

1/CLKOUT frequency t

AV t

STBL t

STBH t

SOEL t

SCSL t

DSU t

DH

Delay from clock to valid address

Clock to PSEN LOW

Clock to PSEN HIGH

Clock to OE LOW

Clock to CS LOW

Data setup to clock

Data hold time

0

–

0

0

Min

–

–

–

–

9.6

0

–

–

–

–

Typ

20.83

41.66

83.2

–

–

–

Max

–

–

–

10.7

8

8

11.1

13

–

– ns ns ns ns

Unit

ns ns ns ns ns ns

Notes

48 MHz

24 MHz

12 MHz

–

–

–

–

–

–

–

Notes

19. CLKOUT is shown with positive polarity.

20. t t

ACC1

is computed from these parameters as follows:

ACC1

(24 MHz) = 3*t

CL

– t

AV t

ACC1

(48 MHz) = 3*t

CL

– t

AV

– t

DSU

– t

DSU

= 106 ns.

= 43 ns.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.3 Data Memory Read

[21]

t

CL

Figure 9-2. Data Memory Read Timing Diagram

Stretch = 0

CLKOUT

[19]

A[15..0]

RD# t

AV t

STBH t

AV

CS#

OE#

D[7..0] t

CL t

STBL t

SCSL t

SOEL

[22]

t

ACC2 t

DSU

data in

Stretch = 1 t

DH

CLKOUT

[19]

A[15..0] t

AV

RD#

CS#

D[7..0] t

ACC3

[22]

t

DSU

data in

t

DH

Table 15. Data Memory Read Parameters

t

CL


1/CLKOUT frequency

Min

–

–

–

Typ

20.83

41.66

83.2

Max

–

–

–

Unit

ns ns ns

Notes

48 MHz

24 MHz

12 MHz t

AV t

STBL t

STBH t

SCSL


Clock to RD LOW

Clock to RD HIGH

Clock to CS LOW

–

–

–

–

–

–

–

–

10.7

11

11

13 ns ns ns ns

–

–

–

– t

SOEL t

DSU

Clock to OE LOW

Data setup to clock

–

9.6

–

–

11.1

– ns ns

–

– t

DH

Data hold time 0 – – ns –

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either

RD# or WR# is active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on the stretch value.

Notes

21. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including typical strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual . The address cycle width can be interpreted from these.

22. t

ACC2 t

ACC2 t

ACC2 t

ACC3 t

ACC3

and t

ACC3

are computed from these parameters as follows:

(24 MHz) = 3*t

CL

– t

(48 MHz) = 3*t

CL

– t

AV

–t

AV

(24 MHz) = 5*t

CL

– t

AV

– t

DSU

= 106 ns

DSU

–t

DSU

= 43 ns

= 190 ns

(48 MHz) = 5*t

CL

– t

AV

– t

DSU

= 86 ns


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.4 Data Memory Write

[23]

t

CL

CLKOUT

A[15..0]

WR#

CS# t

AV t

SCSL t

ON1

D[7..0] t

STBL

Figure 9-3. Data Memory Write Timing Diagram

data out

t

STBH t

AV t

OFF1 t

CL

Stretch = 1

CLKOUT

A[15..0]

WR# t

AV

CS#

D[7..0] t

ON1 t

OFF1

data out

Table 16. Data Memory Write Parameters

Parameter

t

AV t

STBL t

STBH t

SCSL t

ON1 t

OFF1

Description


Clock to WR pulse LOW

Clock to WR pulse HIGH

Clock to CS pulse LOW

Clock to data turn-on

Clock to data hold time

Min

0

0

0

–

0

0

Max

10.7

11.2

11.2

13.0

13.1

13.1

Unit

ns ns ns ns ns ns

Notes

–

–

–

–

–

–

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on the stretch value.

Note

23. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including typical strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual . The address cycle width can be interpreted from these.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.5 PORTC Strobe Feature Timings

The RD# and WR# are present in the 100-pin version and the

128-pin package. In these 100-pin and 128-pin versions, an

8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from or writes to PORTC. This feature is enabled by setting PORTCSTB bit in CPUCS register.

The RD# and WR# strobes are asserted for two CLKOUT cycles when PORTC is accessed.

The WR# strobe is asserted two clock cycles after PORTC is updated and is active for two clock cycles after that, as shown in

Figure 9-4 .

As for read, the value of PORTC three clock cycles before the assertion of RD# is the value that the 8051 reads in. The RD# is pulsed for two clock cycles after three clock cycles from the point when the 8051 has performed a read function on PORTC.

The RD# signal prompts the external logic to prepare the next data byte. Nothing gets sampled internally on assertion of the

RD# signal itself; it is just a prefetch type signal to get the next data byte prepared. So, using it with that in mind easily meets the setup time to the next read.

The purpose of this pulsing of RD# is to allow the external peripheral to know that the 8051 is done reading PORTC and the data was latched into PORTC three CLKOUT cycles before asserting the RD# signal. After the RD# is pulsed, the external logic can update the data on PORTC.

Following is the timing diagram of the read and write strobing

function on accessing PORTC. Refer to Section 9.3

and Section

9.4

for details on propagation delay of RD# and WR# signals.

Figure 9-4. WR# Strobe Function when PORTC is Accessed by 8051 t

CLKOUT

CLKOUT

PORTC IS UPDATED

WR# t

STBL t

STBH

CLKOUT

8051 READS PORTC

RD#

Figure 9-5. RD# Strobe Function when PORTC is Accessed by 8051 t

CLKOUT

DATA MUST BE HELD FOR 3 CLK CYLCES t

STBL

DATA CAN BE UPDATED BY EXTERNAL LOGIC t

STBH


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.6 GPIF Synchronous Signals

Figure 9-6. GPIF Synchronous Signals Timing Diagram

[24]

t

IFCLK

IFCLK t

SGA

GPIFADR[8:0]

RDY

X t

SRY

DATA(input) valid t

RYH t

SGD t

DAH

CTL

X

DATA(output) t

XCTL

N t

XGD

N+1

Table 17. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK

[24, 25]

Parameter Description Min Max

t

IFCLK t

SRY t

RYH t

SGD t

DAH t

SGA t

XGD t

XCTL t

IFCLKR t

IFCLKF t

IFCLKOD t

IFCLKJ

IFCLK Period

RDY

X

to clock setup time

Clock to RDY

X

GPIF data to clock setup time

GPIF data hold time

Clock to GPIF address propagation delay

Clock to GPIF data output propagation delay

Clock to CTL

X

output propagation delay

IFCLK rise time

IFCLK fall time

IFCLK output duty cycle

IFCLK jitter peak to peak

20.83

8.9

0

9.2

0

–

–

–

–

–

–

– t

IFCLK t

SRY t

RYH t

SGD t

DAH t

SGA t

XGD t

XCTL

Table 18. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK

[25]

Parameter

IFCLK period

[26]

Description

RDY

X

to clock setup time 2.9

Clock to RDY

X

3.7

GPIF data to clock setup time 3.2

GPIF data hold time 4.5

Clock to GPIF address propagation delay

Clock to GPIF data output propagation delay

Clock to CTL

X

output propagation delay

Min

20.83

–

–

–

–

–

7.5

11

–

–

–

6.7

–

–

–

–

Notes

24. Dashed lines denote signals with programmable polarity.

25. GPIF asynchronous RDY x

signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.

26. IFCLK must not exceed 48 MHz.

–

–

–

–

Min

–

–

–

–

–

–

49

–

Typ

–

–

–

–

Max

–

–

–

–

900

900

51

300

Max

200

–

–

–

–

11.5

15

10.7

ns ns ns ns ns

Unit

ns ns ns

Unit

ns ns ns ns ns ns ns ns ps ps

% ps


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.1 Slave FIFO Synchronous Read

Figure 9-7. Slave FIFO Synchronous Read Timing Diagram

[24]

t

IFCLK

IFCLK

SLRD t

SRD t

RDH t

XFLG

FLAGS

DATA N t

OEon

N+1 t

XFD t

OEoff

SLOE

Table 19. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK

[25]

Parameter

t

IFCLK t

SRD t

RDH t

OEon t

OEoff t

XFLG t

XFD t

IFCLKR t

IFCLKF t

IFCLKOD t

IFCLKJ

Description

IFCLK period

SLRD to clock setup time

Clock to SLRD hold time

SLOE turn on to FIFO data valid

SLOE turn off to FIFO data hold

Clock to FLAGS output propagation delay

Clock to FIFO data output propagation delay

IFCLK rise time

IFCLK fall time

IFCLK output duty cycle

IFCLK jitter peak to peak

Min

–

–

–

–

20.83

18.7

0

–

–

–

–

Max

–

–

–

10.5

10.5

9.5

11

–

–

–

–

–

–

–

–

Min

–

–

–

–

–

49

–

Typ

–

–

–

–

Max

–

–

–

900

900

51

300

Unit

ns ns ns ps ns ns ns ns ps

% ps


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 20. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK

[25]

Parameter

t

IFCLK t

SRD t

RDH t

OEon t

OEoff t

XFLG t

XFD

IFCLK period

Description

SLRD to clock setup time

Clock to SLRD hold time

SLOE turn on to FIFO data valid

SLOE turn off to FIFO data hold


Clock to FIFO data output propagation delay

Min

20.83

12.7

3.7

–

–

–

–

9.8 Slave FIFO Asynchronous Read

Figure 9-8. Slave FIFO Asynchronous Read Timing Diagram

[24]

t

RDpwh

SLRD t

RDpwl t

XFLG

FLAGS t

XFD

Max

200

–

–

10.5

10.5

13.5

15

N+1 DATA

SLOE

N t

OEon t

OEoff

Table 21. Slave FIFO Asynchronous Read Parameters

[27]

Parameter

t

RDpwl t

RDpwh t

XFLG t

XFD t

OEon t

OEoff

Description

SLRD pulse width LOW

SLRD pulse width HIGH

SLRD to FLAGS output propagation delay

SLRD to FIFO data output propagation delay

SLOE turn-on to FIFO data valid

SLOE turn-off to FIFO data hold

–

–

–

–

Min

50

50

Max

–

–

70

15

10.5

10.5

Unit

ns ns ns ns ns ns ns ns ns ns

Unit

ns ns ns

Note

27. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.9 Slave FIFO Synchronous Write

Figure 9-9. Slave FIFO Synchronous Write Timing Diagram

[24]

t

IFCLK

IFCLK

SLWR t

SWR t

WRH

DATA

Z t

SFD

N t

FDH

Z

FLAGS t

XFLG

Table 22. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK

[25]

Parameter

t

IFCLK t

SWR t

WRH t

SFD t

FDH t

XFLG

IFCLK period

Description

SLWR to clock setup time

Clock to SLWR hold time

FIFO data to clock setup time

Clock to FIFO data hold time

Clock to FLAGS output propagation time

Min

20.83

10.4

0

9.2

0

–

Table 23. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK

[25]

Parameter

t

IFCLK t

SWR t

WRH t

SFD t

FDH t

XFLG

IFCLK Period

Description

SLWR to clock setup time

Clock to SLWR hold time

FIFO data to clock setup time

Clock to FIFO data hold time

Clock to FLAGS output propagation time

Min

20.83

12.1

3.6

3.2

4.5

–

Max

–

–

–

–

–

9.5

Max

200

–

–

–

–

13.5

Unit

ns ns ns ns ns ns

Unit

ns ns ns ns ns ns


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.10 Slave FIFO Asynchronous Write

Figure 9-10. Slave FIFO Asynchronous Write Timing Diagram

[24]

t

WRpwh t

WRpwl t

SFD t

FDH

DATA

FLAGS t

XFD

Table 24. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK

[27]

Parameter

t

WRpwl t

WRpwh t

SFD t

FDH t

XFD

SLWR pulse LOW

SLWR pulse HIGH

Description

SLWR to FIFO DATA setup time

FIFO DATA to SLWR hold time

SLWR to FLAGS output propagation delay

Min

50

70

10

10

–

Max

–

–

–

–

70

9.11 Slave FIFO Synchronous Packet End Strobe

Figure 9-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram

[24]

Unit

ns ns ns ns ns

IFCLK t

PEH

PKTEND

FLAGS t

SPE t

XFLG

Table 25. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK

[25]

Parameter

t

IFCLK t

SPE t

PEH t

XFLG

IFCLK period

Description

PKTEND to clock setup time

Clock to PKTEND hold time


Min

20.83

14.6

0

–

Max

–

–

–

9.5

Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK

[25]

Parameter

t

IFCLK t

SPE t

PEH t

XFLG

IFCLK period

Description

PKTEND to clock setup time

Clock to PKTEND hold time


Min

20.83

8.6

2.5

–

Max

200

–

–

13.5


Unit

ns ns ns ns

Unit

ns ns ns ns

Page 49 of 71

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

There is no specific timing requirement that should be met for asserting the PKTEND pin to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter. The setup time t

SPE met.

and the hold time t

PEH

must be

Although there are no specific timing requirements for PKTEND assertion, there is a specific corner-case condition that needs attention while using the PKTEND pin to commit a one byte or word packet. There is an additional timing requirement that needs to be met when the FIFO is configured to operate in auto mode and it is required to send two packets back to back: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte or word packet committed manually using the PKTEND pin. In this scenario, the user must ensure to assert PKTEND, at least one clock cycle after the rising edge that caused the last byte or word to be clocked into the previous auto

committed packet. Figure 9-12 shows this scenario. X is the

value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode.

Figure 9-12 shows a scenario where two packets are committed.

The first packet gets committed automatically when the number of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet being committed manually using PKTEND.

Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically).

Failing to adhere to this timing results in the FX2 failing to send the one byte or word short packet.

Figure 9-12. Slave FIFO Synchronous Write Sequence and Timing Diagram

[24]

t

IFCLK

IFCLK t

SFA t

FAH

FIFOADR

>= t

SWR

>= t

WRH

SLWR

DATA t

SFD

X-4 t

FDH t

SFD t

FDH

X-3 t

SFD

X-2 t

FDH t

SFD

X-1 t

FDH t

SFD t

FDH

X t

SFD

1 t

FDH

At least one IFCLK cycle t

SPE t

PEH

PKTEND

9.12 Slave FIFO Asynchronous Packet End Strobe

Figure 9-13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram

[24]

t

PEpwh

PKTEND t

PEpwl

FLAGS t

XFLG

Table 27. Slave FIFO Asynchronous Packet End Strobe Parameters

[27]

Parameter

t

PEpwl t

PWpwh t

XFLG

Description

PKTEND pulse width LOW

PKTEND pulse width HIGH

PKTEND to FLAGS output propagation delay

Min

50

50

–

Max

–

–

115

Unit

ns ns ns


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.13 Slave FIFO Output Enable

Figure 9-14. Slave FIFO Output Enable Timing Diagram

[24]

SLOE t

OEon t

OEoff

DATA

Table 28. Slave FIFO Output Enable Parameters

Parameter

t

OEon t

OEoff

Description

SLOE assert to FIFO DATA output

SLOE deassert to FIFO DATA hold

Min Max

10.5

10.5

9.14 Slave FIFO Address to Flags/Data

Figure 9-15. Slave FIFO Address to Flags/Data Timing Diagram

[24]

FIFOADR [1.0] t

XFLG

FLAGS

DATA t

XFD

N N+1

Table 29. Slave FIFO Address to Flags/Data Parameters

Parameter

t

XFLG t

XFD

Description

FIFOADR[1:0] to FLAGS output propagation delay

FIFOADR[1:0] to FIFODATA output propagation delay

Min

–

–

Max

10.7

14.3

9.15 Slave FIFO Synchronous Address

Figure 9-16. Slave FIFO Synchronous Address Timing Diagram

[24]

IFCLK

SLCS/FIFOADR [1:0] t

SFA t

FAH

Table 30. Slave FIFO Synchronous Address Parameters

[25]

Parameter

t

IFCLK t

SFA t

FAH

Interface clock period

Description

FIFOADR[1:0] to clock setup time

Clock to FIFOADR[1:0] hold time

Min

20.83

25

10

Max

200

–

–

Unit

ns ns

Unit

ns ns

Unit

ns ns ns


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.16 Slave FIFO Asynchronous Address

Figure 9-17. Slave FIFO Asynchronous Address Timing Diagram

[24]

SLCS/FIFOADR [1:0] t

SFA t

FAH

SLRD/SLWR/PKTEND

Table 31. Slave FIFO Asynchronous Address Parameters

[27]

t t

SFA

FAH


FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time

RD/WR/PKTEND to FIFOADR[1:0] hold time

Min

10

10

Max

–

–

9.17 Sequence Diagram

9.17.1 Single and Burst Synchronous Read Example

Figure 9-18. Slave FIFO Synchronous Read Sequence and Timing Diagram

[24]

t

IFCLK

IFCLK t

SFA t

FAH t

SFA

FIFOADR

t=0

T=0

t

SRD t

RDH

>= t

SRD

>= t

RDH

SLRD

t=3 t=2

T=2

t

FAH

T=3

Unit

ns ns

SLCS t

XFLG

FLAGS

DATA t t

XFD

Data Driven: N

N+1

OEon t

OEoff t

OEon t

XFD

N+1 N+2 t

XFD

N+3 t

XFD

N+4 t

OEoff

SLOE

t=4

T=1

T=4 t=1

Figure 9-19. Slave FIFO Synchronous Sequence of Events Diagram

FIFO POINTER

IFCLK

N

FIFO DATA BUS

Not Driven

SLOE

IFCLK

N

SLRD

Driven: N

IFCLK

N+1

SLOE

SLRD

N+1

IFCLK

N+1

Not Driven

SLOE

IFCLK

N+1

SLRD

N+1

IFCLK

N+2

N+2

IFCLK

N+3

N+3

IFCLK

N+4

SLRD

N+4

IFCLK

N+4

SLOE

N+4

IFCLK

N+4

Not Driven


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


shows the timing relationship of the

SLAVE FIFO signals during a synchronous FIFO read using

IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read.

■ At t = 0, the FIFO address is stable and the signal SLCS is asserted (SLCS may be tied LOW in some applications). Note that t

SFA

has a minimum of 25 ns. This meansthat when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle.

■ At t = 1, SLOE is asserted. SLOE is an output enable only, whose sole function is to drive the data bus. The data that is driven on the bus is the data that the internal FIFO pointer is currently pointing to. In this example it is the first data value in the FIFO. Note: the data is prefetched and is driven on the bus when SLOE is asserted.

■ At t = 2, SLRD is asserted. SLRD must meet the setup time of t

SRD

(time from asserting the SLRD signal to the rising edge of the IFCLK) and maintain a minimum hold time of t

RDH

(time from the IFCLK edge to the deassertion of the SLRD signal).

If the SLCS signal is used, it must be asserted before SLRD is asserted (The SLCS and SLRD signals must both be asserted to start a valid read condition).

■ The FIFO pointer is updated on the rising edge of the IFCLK, while SLRD is asserted. This starts the propagation of data from the newly addressed location to the data bus. After a propagation delay of t

XFD

(measured from the rising edge of

IFCLK) the new data value is present. N is the first data value read from the FIFO. To have data on the FIFO data bus, SLOE

MUST also be asserted.

The same sequence of events are shown for a burst read and are marked with the time indicators of T = 0 through 5.

Note

For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock, the FIFO pointer is updated and incremented to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus.

9.17.2 Single and Burst Synchronous Write

Figure 9-20. Slave FIFO Synchronous Write Sequence and Timing Diagram

[24]

t

IFCLK

IFCLK t

SFA t

FAH t

SFA t

FAH

FIFOADR

t=0

>= t

WRH t

SWR t

WRH

T=0

>= t

SWR

SLWR

t=2 t=3

T=2 T=5

SLCS t

XFLG t

XFLG

FLAGS

DATA

t=1

t

SFD t

FDH

N

T=1

t

SFD

N+1 t

FDH

T=3

t

SFD t

FDH

N+2

T=4

t

SFD

N+3 t

FDH t

SPE t

PEH

PKTEND


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 9-20 shows the timing relationship of the SLAVE FIFO

signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of three bytes and committing all four bytes as a short packet using the PKTEND pin.

■ At t = 0 the FIFO address is stable and the signal SLCS is asserted. (SLCS may be tied LOW in some applications) Note that t

SFA has a minimum of 25 ns. This means when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle.

■ At t = 1, the external master/peripheral must outputs the data value onto the data bus with a minimum set up time of t

SFD before the rising edge of IFCLK.

■ At t = 2, SLWR is asserted. The SLWR must meet the setup time of t

SWR

(time from asserting the SLWR signal to the rising edge of IFCLK) and maintain a minimum hold time of t

WRH

(time from the IFCLK edge to the deassertion of the SLWR signal).

If the SLCS signal is used, it must be asserted with SLWR or before SLWR is asserted (The SLCS and SLWR signals must both be asserted to start a valid write condition).

■ While the SLWR is asserted, data is written to the FIFO and on the rising edge of the IFCLK, the FIFO pointer is incremented.

The FIFO flag is also updated after a delay of t

XFLG rising edge of the clock.

from the

The same sequence of events are also shown for a burst write and are marked with the time indicators of T = 0 through 5.

Note For the burst mode, SLWR and SLCS are left asserted for the entire duration of writing all the required data values. In this burst write mode, after the SLWR is asserted, the data on the

FIFO data bus is written to the FIFO on every rising edge of

IFCLK. The FIFO pointer is updated on each rising edge of

IFCLK. In

Figure 9-20 , after the four bytes are written to the

FIFO, SLWR is deasserted. The short 4 byte packet can be committed to the host by asserting the PKTEND signal.

There is no specific timing requirement that should be met for asserting PKTEND signal with regards to asserting the SLWR signal. PKTEND can be asserted with the last data value or thereafter. The only requirement is that the setup time t the hold time t

PEH

SPE

and

must be met. In the scenario of

Figure 9-20

, the number of data values committed includes the last value written to the FIFO. In this example, both the data value and the

PKTEND signal are clocked on the same rising edge of IFCLK.

PKTEND can also be asserted in subsequent clock cycles. The

FIFOADDR lines should be held constant during the PKTEND assertion.

Although there are no specific timing requirement for the

PKTEND assertion, there is a specific corner-case condition that needs attention while using the PKTEND to commit a one byte/word packet. Additional timing requirements exist when the

FIFO is configured to operate in auto mode and it is desired to send two packets: a full packet (‘full’ defined as the number of bytes in the FIFO meeting the level set in the AUTOINLEN register) committed automatically followed by a short one byte or word packet committed manually using the PKTEND pin.

In this case, the external master must ensure to assert the

PKTEND pin at least one clock cycle after the rising edge that caused the last byte or word that needs to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to

Figure 9-12 on page 50 for further details on this timing.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.17.3 Sequence Diagram of a Single and Burst Asynchronous Read

Figure 9-21. Slave FIFO Asynchronous Read Sequence and Timing Diagram

[24]

t

SFA t

FAH t

SFA t

FAH

FIFOADR

t=0

t

RDpwl t

RDpwh

T=0

t

RDpwl t

RDpwh t

RDpwl t

RDpwh t

RDpwl t

RDpwh

SLRD

t=2 t=3

T=2 T=3

T=4 T=5 T=6

SLCS t

XFLG t

XFLG

FLAGS

DATA

Data (X)

Driven t

XFD

N t

OEon t

OEoff

N t

OEon t

XFD

N+1 t

XFD

N+2 t

XFD

N+3 t

OEoff

SLOE

t=1 t=4

T=1 T=7

Figure 9-22. Slave FIFO Asynchronous Read Sequence of Events Diagram

FIFO POINTER

N

FIFO DATA BUS Not Driven

SLOE

N

Driven: X

SLRD

N

SLRD

N+1

SLOE

N N

N+1

SLOE

N+1

SLRD

N+1

SLRD

N+2

SLRD

N+2

SLRD

N+3

Not Driven N N+1 N+1 N+2 N+2

SLOE

N+3

Not Driven


signals during an asynchronous FIFO read. It shows a single read followed by a burst read.

■

At t = 0, the FIFO address is stable and the SLCS signal is asserted.

■

At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is the previous data, the data that was in the FIFO from anearlier read cycle.

■

At t = 2, SLRD is asserted. The SLRD must meet the minimum active pulse of t

RDpwl t

RDpwh

and minimum de-active pulse width of

. If SLCS is used, then SLCS must be asserted before

SLRD is asserted (The SLCS and SLRD signals must both be asserted to start a valid read condition.)

■

The data that is driven, after asserting SLRD, is the updated data from the FIFO. This data is valid after a propagation delay of t

XFD

from the activating edge of SLRD. In

Figure 9-21 , data

N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (SLRD is asserted), SLOE must be in an asserted state. SLRD and SLOE can also be tied together.

The same sequence of events is also shown for a burst read marked with T = 0 through 5.

Note In the burst read mode, during SLOE is asserted, the data bus is in a driven state and outputs the previous data. After SLRD is asserted, the data from the FIFO is driven on the data bus

(SLOE must also be asserted) and then the FIFO pointer is incremented.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

9.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

Figure 9-23. Slave FIFO Asynchronous Write Sequence and Timing Diagram

[24]

t

SFA t

FAH t

SFA

FIFOADR

t=0

t

WRpwl t

WRpwh

T=0

t

WRpwl t

WRpwh t

WRpwl t

WRpwh t

WRpwl t

WRpwh

SLWR

t =1 t=3

T=1 T=3 T=4

T=6

T=7

T=9

SLCS t

XFLG

FLAGS

DATA t

SFD t

FDH

N

t=2

t

SFD t

FDH

N+1

T=2

PKTEND


write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the

4byte short packet using PKTEND.

■ At t = 0 the FIFO address is applied, ensuring that it meets the setup time of t

SFA

. If SLCS is used, it must also be asserted

(SLCS may be tied LOW in some applications).

■ At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of t

WRpwl t

WRpwh

and minimum de-active pulse width of

. If the SLCS is used, it must be asserted with SLWR or before SLWR is asserted.

■ At t = 2, data must be present on the bus t

SFD deasserting edge of SLWR.

before the

■ At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then increments the FIFO pointer.

The FIFO flag is also updated after t

XFLG

from the deasserting edge of SLWR.

t

SFD t

FDH

N+2

T=5

t

SFD t

FDH

N+3

T=8

t

FAH t

XFLG t

PEpwl t

PEpwh

The same sequence of events is shown for a burst write and is indicated by the timing marks of T = 0 through 5.

Note In the burst write mode, after SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incremented.

In Figure 9-23

, after the four bytes are written to the FIFO and

SLWR is deasserted, the short 4-byte packet can be committed to the host using PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after

SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines have to held constant during the

PKTEND assertion.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

10. Ordering Information

Table 32. Ordering Information

Ordering Code Package Type RAM Size # Prog I/Os

Ideal for Battery Powered Applications

CY7C68014A-128AXC 128 TQFP – Pb-free

CY7C68014A-100AXC

CY7C68014A-56PVXC

100 TQFP – Pb-free

56 SSOP – Pb-free

CY7C68014A-56LTXC

CY7C68016A-56LTXC

56 QFN - Pb-free

56 QFN - Pb-free

CY7C68016A-56LTXCT 56 QFN - Pb-free

Ideal for Non Battery Powered Applications

CY7C68013A-128AXC

CY7C68013A-128AXI

CY7C68013A-100AXC

CY7C68013A-100AXI

CY7C68013A-56PVXC

CY7C68013A-56PVXCT

CY7C68013A-56PVXI

CY7C68013A-56BAXC


128 TQFP – Pb-free (Industrial)


100 TQFP – Pb-free (Industrial)

56 SSOP – Pb-free

56 SSOP – Pb-free

56 SSOP – Pb-free (Industrial)

56 VFBGA – Pb-free

CY7C68013A-56BAXCT

CY7C68013A-56LTXC

CY7C68013A-56LTXCT

CY7C68013A-56LTXI

CY7C68015A-56LTXC

Development Tool Kit

CY3684

Reference Design Kit

CY4611B

56 VFBGA – Pb-free

56 QFN – Pb-free

56 QFN – Pb-free

56 QFN – Pb-free (Industrial)

56 QFN – Pb-free

EZ-USB FX2LP development kit

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

16 K

40

40

24

24

26

26

USB 2.0 to ATA/ATAPI reference design using EZ-USB FX2LP

24

24

24

24

40

40

40

40

24

24

24

24

26

8051 Address

/Data Bus

16-/8-bit

–

–

–

–

–

16-/8-bit

16-/8-bit

–

–

–

–

–

–

–

–

–

–

–

Serial Debug

[28]

Y

Y

N

N

N

N

N

N

N

N

Y

Y

Y

Y

N

N

N

N

N

Ordering Code Definitions

Note

28. As UART is not available in the 56-pin package of CY7C68013A, serial port debugging using Keil Monitor is not possible.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

CY 7 C 68 XXXX - XXXXX (C, I) (T)

Tape and Reel

Thermal Rating:

C = Commercial

I = Industrial

Package Type:

LTX = QFN (Saw Type) Pb-free

LFX = QFN (Punch Type) Pb-free

Part Number

Family Code: 68 = USB

Technology Code: C = CMOS

Marketing Code: 7 = Cypress Products

Company ID: CY = Cypress


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

11. Package Diagrams

The FX2LP is available in five packages:

■ 56-pin SSOP

■ 56-pin QFN

■ 100-pin TQFP

■ 128-pin TQFP

■ 56-ball VFBGA

Figure 11-1. 56-Pin Shrunk Small Outline Package O56 (51-85062)


51-85062 *F

Page 59 of 71

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 11-2. 56-Pin QFN 8 × 8 mm Sawn Version (001-53450)

001-53450 *D


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A100RA (51-85050)

51-85050 *E


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 11-4. 128-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128 (51-85101)

51-85101 *F


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 11-5. 56-Pin VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901)

001-03901 *E


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

12. PCB Layout Recommendations

Follow these recommendations to ensure reliable highperformance operation:

[29]

■ Four-layer, impedance-controlled boards are required to maintain signal quality.

■ Specify impedance targets (ask your board vendor what they can achieve).

■ To control impedance, maintain trace widths and trace spacing.

■ Minimize stubs to minimize reflected signals.

■ Connections between the USB connector shell and signal ground must be near the USB connector.

■ Bypass and flyback caps on VBUS, near connector, are recommended.

■ DPLUS and DMINUS trace lengths should be kept to within

2 mm of each other in length, with preferred length of 20 to

30 mm.

■ Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to split under these traces.

■ Do not place vias on the DPLUS or DMINUS trace routing.

■ Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.

Note

29. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com

and High Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf

.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

13. Quad Flat Package No Leads (QFN) Package Design Notes

Electrical contact of the part to the PCB is made by soldering the leads on the bottom surface of the package to the PCB.

Therefore, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. Design a copper (Cu) fill in the PCB as a thermal pad under the package. Heat is transferred from the FX2LP through the device’s metal paddle on the bottom side of the package.

Heat from here is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 × 5 array of via. A via is a plated-through hole in the

PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process.

For further information on this package design, refer to application notes for Surface Mount Assembly of Amkor's

MicroLeadFrame (MLF) Packages. You can find this on Amkor's website http://www.amkor.com.

This application note provides detailed information about boardmounting guidelines, soldering flow, rework process, etc.

Figure 13-1 shows a cross-sectional area underneath the

package. The cross section is of only one via. The solder paste template should be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be

5 mil. Use the No Clean type 3 solder paste for mounting the part.

Nitrogen purge is recommended during reflow.

Figure 13-2 is a plot of the solder mask pattern and Figure 13-3

displays an X-Ray image of the assembly (darker areas indicate solder).

Figure 13-1. Cross-section of the Area Underneath the QFN Package

0.017” dia

Solder Mask

Cu Fill

Cu Fill

0.013” dia

PCB Material

PCB Material

Via hole for thermally connecting the

QFN to the circuit board ground plane.

This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane

Figure 13-2. Plot of the Solder Mask (White Area)

Figure 13-3. X-ray Image of the Assembly


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Acronyms

Acronyms Used in this Document

Acronym

ASIC

ATA

Description

application-specific integrated circuit advanced technology attachment

DSL

DSP digital service line digital signal processor

EEPROM electrically erasable programmable read only memory

EPP

FIFO enhanced parallel port first in first out

GPIO general purpose input output

LAN

MPEG

PCMCIA local area network moving picture experts group personal computer memory card international association

Document Conventions

Units of Measure

Symbol Unit of Measure

Mbps

MBPs

megabits per second

megabytes per second

QFN quad flat no leads

SIE

SOF

SSOP

TQFP

USART

USB

UTOPIA

VFBGA serial interface engine start of frame super small outline package thin quad flat pack universal serial asynchronous receiver/transmitter universal serial bus universal test and operations physical-layer interface very fine ball grid array


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Errata

This section describes the errata for the EZ-USB

®

FX2LP™ CY7C68013A/14A/15A/16A Rev. B silicon. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

CY7C68013A

CY7C68014A

CY7C68015A

CY7C68016A

Package Type

All

All

All

All

CY7C68013A/14A/15A/16A Qualification Status

In production

Operating Range

Commercial

Commercial

Commercial

Commercial

CY7C68013A/14A/15A/16A Errata Summary

This table defines the errata for available CY7C68013A/14A/15A/16A family devices. An "X" indicates that the errata pertain to the selected device.

Items

[1] Empty Flag Assertion

CY7C68013A/14A/15A/16A

X

Silicon Revision

B

Fix Status

No silicon fix planned currently. Use the workaround

1. Empty Flag Assertion

■

Problem Definition

In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT

Endpoint (EP) in the first transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction.

■

Parameters Affected

NA

■

Trigger Condition(S)

In Slave FIFO Asynchronous Word Wide Mode, after firmware boot and initialization, EP2 OUT endpoint empty flag indicates the status as ‘Empty’. When data is received in EP2, the status changes to ‘Not-Empty’. However, if data transferred to EP2 is a single word, then asserting SLRD with FIFOADR pointing to any other endpoint changes ‘Not-Empty’ status to ‘Empty’ for EP2 even though there is a word data (or it is untouched). This is noticed only when the single word is sent as the first transaction and not if it follows a multi-word packet as the first transaction.

■

Scope of Impact

External interface does not see data available in EP2 OUT endpoint and can end up waiting for data to be read.

■

Workaround

One of the following workarounds can be used:

• Send a pulse signal to the SLWR pin, with FIFOADR pins pointing to an endpoint other than EP2, after firmware initialization and before or after transferring the data to EP2 from the host

• Set the length of the first data to EP2 to be more than a word

• Prioritize EP2 read from the Master for multiple OUT EPs and single word write to EP2

• Write to an IN EP, if any, from the Master before reading from other OUT EPs (other than EP2) from the Master.

■

Fix Status

There is no silicon fix planned for this currently; use the workarounds provided.


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document History Page

Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB

®

FX2LP™ USB Microcontroller High-

Speed USB Peripheral Controller

Document Number: 38-08032

Rev.

**

*A

*B

*C

*D

*E

*F

*G

*H

*I

*J

ECN No.

124316

128461

130335

131673

230713

242398

271169

316313

338901

371097

397239

Orig. of

Change

VCS

VCS

KKV

KKU

KKU

TMD

MON

MON

MON

MON

MON

Submission

Date

03/17/03 New datasheet

Description of Change

09/02/03 Added PN CY7C68015A throughout datasheet

Modified

Figure 2-1

to add ECC block and fix errors

Removed word “compatible” where associated with I

2

C

Corrected grammar and formatting in various locations

Updated Sections 3.2.1, 3.9, 3.11,

Table 8

, Section 5.0

Added Sections 3.15, 3.18.4, 3.20

Modified

Figure 2-5

for clarity

Updated

Figure 11-2 to match current spec revision

10/09/03 Restored PRELIMINARY to header (had been removed in error from rev. *A)

02/12/04 Section 8.1 changed “certified” to “compliant”

Table 13

added parameter V

IH_X

and V

IL_X

Added Sequence diagrams Section 9.16

Updated Ordering information with lead-free parts

Updated Registry Summary

Section 3.12.4:example changed to column 8 from column 9

Updated

Figure 9-3

memory write timing Diagram

Updated section 3.9 (reset)

Updated section 3.15 ECC Generation

See ECN Changed Lead free Marketing part numbers in

Table 32 as per spec change in

28-00054.

See ECN Minor Change: datasheet posted to the web,

See ECN Added USB-IF Test ID number

Added USB 2.0 logo

Added values for Isusp, Icc, Power Dissipation, Vih_x, Vil_x

Changed VCC from + 10% to + 5%

Changed PKTEND to FLAGS output propagation delay (asynchronous

interface) in Table 27

from a max value of 70 ns to 115 ns

See ECN Removed CY7C68013A-56PVXCT part availability

Added parts ideal for battery powered applications: CY7C68014A,

CY7C68016A

Provided additional timing restrictions and requirement about the use of

PKETEND pin to commit a short one byte/word packet subsequent to committing a packet automatically (when in auto mode).

Added Min Vcc Ramp Up time (0 to 3.3v)

See ECN Added information about the AUTOPTR1/AUTOPTR2 address timing with regards to data memory read/write timing diagram.

Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay

(t

XFD

) for Slave FIFO Synchronous Read

Changed

Table 32

to include part CY7C68016A-56LFXC in the part listed for battery powered applications

Added register GPCR2 in register summary

See ECN Added timing for strobing RD#/WR# signals when using PortC strobe feature

(Section 9.5)

See ECN Removed XTALINSRC register from register summary.

Changed Vcc margins to +10%

Added 56-pin VFBGA Pin Package Diagram

Added 56-pin VFBGA definition in pin listing

Added RDK part number to the Ordering Information table


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


(continued)


®




Rev.

*K

*L

*M

*N

*O

*P

*Q

*R

*S

*T

*U

*V

ECN No.

420505

Orig. of

Change

MON

2064406 CMCC/PY

RS

2710327

2727334

2756202

2785207

2811890

2896281

3035980

3161410

3195232

3512313

DPT

ODC

ODC

ODC

ODC

ODC

ODC

AAE

ODC

GAYA

Submission

Date


See ECN

Remove SLCS from figure in Section 9.10.

Removed indications that SLRD can be asserted simultaneously with SLCS in

Section 9.17.2 and Section 9.17.3

Added Absolute Maximum Temperature Rating for industrial packages in

Section 5.

Changed number of packages stated in the description in Section 3. to five.

Added

Table 12 on Thermal Coefficients for various packages

See ECN Changed TID number

Removed T0OUT and T1OUT from CY7C68015A/16A

Updated t

SWR

Min value in Figure 9-9

Updated 56-lead QFN package diagram

05/22/2009 Added 56-Pin QFN (8 X 8 mm) package diagram

Updated ordering information for CY7C68013A-56LTXC,

CY7C68013A-56LTXI, CY7C68014A-56LTXC, CY7C68015A-56LTXC, and

CY7C68016A-56LTXC parts.

07/01/09 Removed sentence on E-Pad size change from *F revision in the Document

History Page

Updated 56-Pin Sawn Package Diagram

08/26/2009 Updated Ordering Information table and added note 24.

10/12/2009 Added information on Pb-free parts in the Ordering information table.

11/20/2009 Updated Program I/Os for the CY7C68016A-56LTXC and

CY7C68016A-56LTXCT parts in “Ordering Information” on page 57.

03/19/10 Removed inactive parts from the ordering information table. Updated package diagrams.Updated links in Sales, Solutions and Legal Information.

09/22/10 Updated template.

Changed PPM requirement for the external crystal from +/- 10 ppm to +/- 100 ppm under Electrical specifications.

Added table of contents, ordering code definitions, acronym table, and units of measure.

02/03/2011 Replaced 56-Pin QFN 8 × 8 mm Punch Version Package Diagram (Figure 11.2) and 56-Pin QFN 8 × 8 mm Sawn Version Package Diagram (Figure 11.3).

Updated Package Diagrams (Figure 11.4, Figure 11.5).

03/14/2011 Updated table numbering.

Added typical values to Table 17 on page 45 and

Table 19 on page 46

based on data obtained from SHAK-63 and SHAK 69.

Updated

Table 12, “Thermal Characteristics,” on page 39 (CDT 89510)

Updated package diagram 001-03901 to *D.

02/01/2012 Removed obsolete part CY7C68014A-56BAXC

Removed pruned part CY7C68016A-56LFXC

Added parts CY7C68013A-56BAXCT and CY7C68013A-56PVXCT

Updated

Package Diagrams


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A


(continued)


®




Rev.

*W

ECN No.

3998554

Orig. of

Change

GAYA

Submission

Date


07/19/2013

Added Errata footnote (Note 3).

*X 4617527 GAYA

Updated

Functional Overview :

Updated

Interrupt System :

Updated

FIFO/GPIF Interrupt (INT4) :

Added Note 3 and referred the same note in “Endpoint 2 empty flag” in Table 4

.

Updated

Package Diagrams :

spec 51-85062 – Changed revision from *E to *F.

spec 001-53450 – Changed revision from *B to *C.

Added

Errata

.

Updated in new template.

01/15/2015 Updated

Figure 9-2

Added a note to sections Data Memory Read

[21]

and

Data Memory Write

[23]

sections

Updated template to include the More Information

section

Updated

Figure 11-2 ,

Figure 11-3

,

Figure 11-4

Updated

Table 10 with Reset state information for pins

Sunset Review


CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Sales, Solutions, and Legal Information

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Document Number: 38-08032 Rev. *X Revised January 15, 2015 Page 71 of 71

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