datasheet for VL493T2863T

datasheet for VL493T2863T
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
General Information
1GB 128Mx72 DDR2 SDRAM ECC SO-RDIMM 200-PIN WITH THERMAL SENSOR
Description:
The VL493T2863T is a 128Mx72 Double Data Rate DDR2 SDRAM high density SO-RDIMM. This memory
module is single rank, consists of nine CMOS 128Mx8 bit with 8 banks DDR2 Synchronous DRAMs in BGA
packages, two 25-bit Registered buffers in BGA package, a zero delay PLL clock in BGA package, and a 2K
EEPROM with Thermal Sensor in an 8-pin MLF package. This module is a 200-pin small-outline dual in-line
memory module and is intended for mounting into an edge connector socket. Decoupling capacitors are
mounted on the printed circuit board for each DDR2 SDRAM.
Features:
•
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200-pin, registered small-outline dual in-line memorymodule (SO-RDIMM)
Data transfer rates: PC2-6400, PC2-5300, PC2-4200
Supports ECC error detection and correction
Power supply: VDD = VDDQ = 1.8V ± 0.1V
JEDEC standard 1.8V I/O (SSTL_18-Compatible)
VDDSPD = 3.0V to 3.6V
On-die termination (ODT)
Differential data strobe (DQS, DQS#) option
Differential clock inputs (CK, CK#)
7.8us average periodic refresh interval
Programmable CAS# Latency: 6 (DDR2-800), 5 (DDR2-667), 4 (DDR2-533)
Posted CAS# additive Latency: 0, 1, 2, 3, and 4
Eight internal banks for concurrent operation (component)
On memory PLL Clock and Register drivers
Serial presence detect (SPD) with EEPROM built-in Thermal Sensor
Thermal sensor range: -200C to +1250C (+/- 10C Accuracy)
Gold edge contacts
Lead-free RoHS
PCB: Height 30.00mm (1.181"), double sided components
JEDEC pin out
Order Information:
VL493T2863T-E7 S X
Pin Name
Function
A 0 ~ A 13
Address Inputs
BA0 ~ BA2
Bank Address Inputs
DQ0 ~ DQ63
Data Input/Output
C B0 ~ C B7
Check Bits
DQS0 ~ DQS8
Data Strobes
DQS0# ~ DQS8#
Data Strobes Complement
DM0 ~ DM8
Data Masks
ODT0
On-die Termination Control
CK,CK#
Clock Input
C KE0
Clock Enables
C S 0#
Chip Selects
RAS#
Row Address Strobes
C AS#
Column Address Strobes
WE#
Write Enable
RESET#
Register Reset Input
VD D
Voltage Supply 1.8V +/- 0.1V
A10/AP
Address Input/Auto Precharge
VD D SPD
SPD Voltage Supply 3.0V to 3.6V
VSS
Ground
SA0 ~ SA1
SPD Address
SD A
SPD Data Input/Output
SC L
SPD Clock Input
VREF
SSTL_18 Reference Voltage
NC
No Connect
DRAM DIE (option)
DRAM MANUFACTURER
S - SAMSUNG
M - MICRON
MODULE SPEED
E7: PC2-6400 @ CL6
E6: PC2-5300 @ CL5
D5: PC2-4200 @ CL4
VL : Lead-free/RoHS
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 1 OF 10
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
Pin Configuration
200-PIN DDR2 SO-RDIMM FRONT
200-PIN DDR2 SO-RDIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
51
DQ18
101
VD D
151
VSS
2
VSS
52
VSS
102
A6
152
VSS
3
DQ0
53
DQ19
103
A5
153
DQS5#
4
DQ4
54
DQ28
104
A4
154
DM5
5
VSS
55
VSS
105
A3
155
DQS5
6
DQ5
56
DQ29
106
VD D
156
VSS
7
DQ1
57
DQ24
107
A2
157
VSS
8
VSS
58
VSS
108
A1
158
DQ46
9
DQS0#
59
DQ25
109
VD D
159
DQ42
10
DM0
60
DM3
110
A0
160
DQ47
11
DQS0
61
VSS
111
A10/AP
161
DQ43
12
VSS
62
VSS
112
BA1
162
VSS
13
VSS
63
DQS3#
113
BA0
163
VSS
14
DQ6
64
DQ30
114
VD D
164
DQ52
15
DQ2
65
DQS3
115
RAS#
165
DQ48
16
DQ7
66
DQ31
116
WE#
166
DQ53
17
DQ3
67
VSS
117
VD D
167
DQ49
18
VSS
68
VSS
118
C S 0#
168
VSS
19
VSS
69
DQ26
119
C AS#
169
VSS
20
DQ12
70
C B4
120
ODT0
170
DM6
21
DQ8
71
DQ27
121
NC
171
DQS6#
22
DQ13
72
C B5
122
A 13
172
VSS
23
DQ9
73
VSS
123
VD D
173
DQS6
24
VSS
74
VSS
124
VD D
174
DQ54
25
VSS
75
C B0
125
NC
175
VSS
26
DM1
76
DM8
126
CK
176
DQ55
27
DQS1#
77
C B1
127
NC
177
DQ50
28
VSS
78
VSS
128
C K#
178
VSS
29
DQS1
79
VSS
129
DQ32
179
DQ51
30
DQ14
80
C B6
130
VSS
180
DQ60
31
VSS
81
DQS8#
131
VSS
181
VSS
32
DQ15
82
C B7
132
DQ36
182
DQ61
33
DQ10
83
DQS8
133
DQ33
183
DQ56
34
VSS
84
VSS
134
DQ37
184
VSS
35
DQ11
85
VSS
135
DQS4#
185
DQ57
36
DQ20
86
C B2
136
VSS
186
DM7
37
VSS
87
C KE0
137
DQS4
187
VSS
38
DQ21
88
C B3
138
DM4
188
DQ62
39
DQ16
89
NC
139
VSS
189
DQS7#
40
VSS
90
VSS
140
VSS
190
VSS
41
DQ17
91
NC
141
DQ34
191
DQS7
42
RESET#
92
BA2
142
DQ38
192
DQ63
43
VSS
93
VD D
143
DQ35
193
DQ58
44
DM2
94
NC
144
DQ39
194
SD A
45
DQS2#
95
A 12
145
VSS
195
VSS
46
VSS
96
A11
146
VSS
196
SC L
47
DQS2
97
A9
147
DQ40
197
DQ59
48
DQ22
98
VD D
148
DQ44
198
SA1
49
VSS
99
A7
149
DQ41
199
VD D SPD
50
DQ23
100
A8
150
DQ45
200
SA0
Note: 1. RESET (pin 42) RESET is connected to both OE of the PLL and Reset of the register for 72-bit Registered SO-RDIMM ONLY
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 2 OF 10
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
Functional Block Diagram
RCS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS1#
DM1
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5#
DM5
DM/
RDQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6#
DM6
DQS2
DQS2#
DM2
DM/
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
CS# DQS DQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DQS3#
DM3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D6
DQS7
DQS7#
DM7
DM/
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
CS# DQS DQS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D7
VDDSPD
DQS8
DQS8#
DM8
DM/
RDQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
VDDSPD = 3.3V
Thermal Sensor & SPD
D8
SCL
SDA
WP A0
A1
SA0 SA1
1:1
R
E
G
I
S
T
E
R
RESET#**
D0-D8
D0-D8
D0-D8
VREF
VSS
A2
SA2
120
CK
CK#
CS0#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
Serial PD
VDD/ VDDQ
RCS0# -> CS# : DDR2 SDRAMs D0-D8
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D8
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8
RRAS# -> RAS:# DDR2 SDRAMs D0-D8
RCAS# -> CAS:# DDR2 SDRAMs D0-D8
RWE# -> WE# : DDR2 SDRAMs D0-D8
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RODT0 -> ODT : DDR2 SDRAMs D0-D8
PLL
CK
CK#
RESET#**
Notes:
Unless otherwise noted, resistor values are 22 Ohms +/- 5%
RST#
CK**
** RESET#, CK and CK# connects to Register.
CK #**
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 3 OF 10
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
REGISTER X 2
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
Absolute Maximum Ratings
Symbol
Parameter
MIN
MAX
Unit
VDD
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage temperature
-55
100
Command/Address,
RAS#, CAS#, WE#,
CKE, ODT, BA
-5
5
C S#
5
5
VIN, VOUT
TSTG
Input leakage current; Any input
0V<VIN<VDD; VREF input
0V<VIN<0.95V; Other pins not under
test = 0V
IL
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT
are disabled
IOZ
C K, C K#
-250
C
uA
+250
uA
DM
-5
5
uA
DQ, DQS, DQS#
-5
5
uA
-18
18
uA
VREF leakage current; VREF = Valid VREF level
IVREF
0
DC Operating Conditions
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
VD D
1.7
1.8
1.9
V
1
I/O Supply voltage
VD D Q
1.7
1.8
1.9
V
4
VDDL Supply voltage
VD D L
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
Supply voltage
Notes: 1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise on VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2
percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 4 OF 10
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
Operating Temperature Condition
Parameter
Operating temperature
Symbol
Rating
TOPER
0 to 95
Units
0
Notes
C
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JEDEC JESD51.2
2. At 0 - 850C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
85°C < TOPER <= 95°C
Input DC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Input AC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage DDR2-533
VIH(AC)
VREF + 0.250
-
V
AC Input High (Logic 1) Voltage DDR2-667 & DDR2-800
VIH(AC)
VREF + 0.200
-
V
AC Input Low (Logic 0) Voltage DDR2-533
VIL(AC)
-
VREF - 0.250
V
AC Input Low (Logic 0) Voltage DDR2-667 & DDR2-800
VIL(AC)
-
VREF - 0.200
V
Input/Output
Capacitance
0
TA=25 C, f=100MHz
Parameter
Symbol
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
E7/E6
(DDR2-800/677)
D5
(DDR2-533)
Unit
Min
Max
Min
Max
CIN1
6.5
7.5
6.5
7.5
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1), (CS0#, CS1#)
CIN2
6.5
7.5
6.5
7.5
pF
Input capacitance (CK0, CK0#)
CIN3
6
7
6
7
pF
Input/Output capacitance (DQ, DQS, DQS#, DM, CB)
CIO
9
11
9
12
pF
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 5 OF 10
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
IDD Specification
Condition
Symbol
E7
E6
D5
(DDR2-800) (DDR2-667) (DDR2-533)
Unit
Operating one bank active-precharge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0*
1210
1165
1120
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4; CL = CL(IDD);tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1*
1300
1255
1210
mA
Precharge pow er-dow n current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
IDD2P**
535
535
535
mA
Precharge quiet standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
IDD2Q**
760
760
760
mA
Precharge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are SWITCHING.
IDD2N**
850
805
805
mA
Active pow er-dow n current;
All banks open; tCK= tCK(IDD); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs
are FLOATING.
760
760
715
mA
IDD3P**
562
562
562
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open;tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD));CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD3N**
985
940
940
mA
Operating burst w rite current;
All banks open; Continuous burst writes; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4W*
1705
1570
1480
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD4R*
1795
1660
1570
mA
Burst auto refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.
IDD5**
1795
1750
1750
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING.
IDD6**
135
135
135
mA
IDD7*
2740
2560
2560
mA
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD);
tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Note: IDD specification is based on Samsung D-die component.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2 (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 6 OF 10
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
AC Timing Parameters & Specifications
E7
Parameter
Symbol
(DDR2-800)
E6
D5
(DDR2-667)
(DDR2-533)
U nit
Min
Max
Min
Max
Min
Max
C L=6
tCK (6)
2500
8000
-
-
-
-
ps
C L=5
tCK (5)
3000
8000
3000
8000
3,750
8,000
ps
C L=4
tCK (4)
3750
8000
3750
8000
3,750
8,000
ps
C L=3
tCK (3)
-
-
5000
8000
5,000
8,000
ps
C K hi gh-level wi dth
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
C K low-level wi dth
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock peri od
tHP
MIN
(tCH,tCL)
C lock ji tter
tJIT
-100
100
-125
125
-125
125
ps
D Q output access ti me from C K/C K#
tAC
-400
400
-450
+450
-500
+500
ps
D ata-out hi gh i mpedance wi ndow from C K/C K#
tHZ
tAC (MAX)
ps
D ata-out low-i mpedance wi ndow from C K/C K#
tLZ
tAC (MIN)
tAC (MAX)
ps
D Q and D M i nput setup ti me relati ve to D QS
tDS
50
100
100
D Q and D M i nput hold ti me relati ve to D QS
tDH
125
175
225
D Q and D M i nput pulse wi dth (for each i nput)
tDIPW
0.35
0.35
0.35
D ata hold skew factor
tQHS
D Q–D QS hold, D QS to fi rst D Q to go nonvali d,
p e r a cce ss
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
D ata vali d output wi ndow (D VW)
tDVW
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
D QS i nput hi gh pulse wi dth
tDQSH
0.35
0.35
0.35
tCK
D QS i nput low pulse wi dth
tDQSL
0.35
0.35
0.35
tCK
D QS output access ti me fromC K/C K#
tDQSCK
-350
D QS falli ng edge to C K ri si ng – setup ti me
tDSS
0.2
0.2
0.2
tCK
D QS falli ng edge from C K ri si ng – hold ti me
tDSH
0.2
0.2
0.2
tCK
D QS–D Q skew, D QS to last D Q vali d, per group,
p e r a cce ss
tDQSQ
D QS read preamble
tRPRE
0.9
1.1
0.9
1.1
D QS read postamble
tRPST
0.4
0.6
0.4
0.6
D QS wri te preamble setup ti me
tWPRES
0
0
0
ps
D QS wri te preamble
tWPRE
0.35
0.35
0.35
tCK
D QS wri te postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Wri te command to fi rst D QS latchi ng transi ti on
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Data Strobe
Data
Clock
C lock cycle ti me
MIN
(tCH,tCL)
tAC (MAX)
tAC (MAX)
tAC (MAX)
tAC (MIN)
300
350
MIN
(tCH,tCL)
tAC (MAX)
tAC (MIN)
340
-400
200
+400
tCK
400
-450
240
+450
ps
ps
300
ps
0.9
1.1
tCK
0.4
0.6
tCK
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 7 OF 10
ps
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
AC Timing Parameters & Specifications ( cont')
E7
Parameter
Symbol
(DDR2-800)
Power-Down
ODT
Self Refresh
Command and Address
Min
Max
E6
D5
(DDR2-667)
(DDR2-533)
Min
Max
Min
Unit
Max
Address and control input pulse width for each
input
tIPW
0.6
0.6
0.6
tCK
Address and control input setup time
tIS
175
200
250
ps
Address and control input hold time
tIH
250
275
375
ps
CAS# to CAS# command delay
tCCD
2
2
2
ps
ACTIVE to ACTIVE (same bank) command
tRC
60
60
60
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
7.5
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
15
15
15
ns
Four Bank Activate period
tFAW
37.5
ACTIVE to PRECHARGE command
tRAS
45
Internal READ to precharge command delay
tRTP
7.5
7.5
7.5
ns
Write recovery time
tWR
15
15
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
ns
Internal WRITE to READ command delay
tWTR
10
7.5
7.5
ns
PRECHARGE command period
tRP
15
15
15
ns
37.5
70,000
40
37.5
70,000
40
ns
70,000
ns
PRECHARGE ALL command period
tRPA
tRP+tCK
tRP+tCK
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
2
2
2
tCK
CKE low to CK,CK# uncertainty
tDELAY
tIS+tCK+tIH
tIS+tCK+tIH
tIS+tCK+tIH
ns
tRFC
127.5
REFRESH to Active or Refresh to Refresh
command interval
70,000
127.5
7.8
70,000
127.5
7.8
70,000
7.8
ns
us
Average periodic refresh interval
tREFI
Exit self refresh to non-READ command
tXSNR
tRFC(MIN)+10
tRFC(MIN)+10
tRFC(MIN)+10
ns
Exit self refresh to READ
tXSRD
200
200
200
tCK
Exit self refresh timing reference
tISXR
tIS
ODT turn-on delay
tAOND
2
2
2
2
2
2
tCK
ODT turn-on
tAON
tAC(MIN)
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
1000
ps
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
ps
tAONPD
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
ps
ODT to power-down entry latency
tANPD
3
3
3
tCK
ODT power-down exit latency
tAXPD
10
8
8
tCK
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
8-AL
7-AL
6-AL
tCK
Exit precharge power-down to any non-READ
command.
tXP
2
2
2
tCK
CKE minimum high/low time
tCKE
3
3
3
tCK
ODT turn-on (power-down mode)
tIS
tIS
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 8 OF 10
ps
Product Specifications
PART NO:
REV: 1.1
VL493T2863T-E7/E6/D5
Package Dimensions
FRONT VIEW
3.66 MAX
67.60
4.00 +/- 0.10 (2X)
30.00
1.80 (2X)
TYP
20.00 TYP
6.00 TYP
2.55 TYP
1.00 +/- 0.10
2.15 TYP
0.45 TYP
1.00 TYP
PIN 1
0.60 TYP
PIN 199
63.60 TYP
BACK VIEW
4.00 +/- 0. 10
PIN 200
4.20 TYP
47.40 TYP
PIN 2
11.40 TYP
15.35 TYP
NOTE:
All dimesions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 9 OF 10
Product Specifications
PART NO:
VL493T2863T-E7/E6/D5
Revision History:
Date
Rev.
P ag e
C h an g es
04/06/2009
1.0
All
Spec release
20 /12/2010
1.1
1
Update General Information
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 10 OF 10
REV: 1.1
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