WM8235 Product Datasheet
WM8235
210MSPS 9-Channel AFE with Sensor
Timing Generation and LVDS/CMOS Data Output
DESCRIPTION
The WM8235 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 23MSPS per channel.
The device has nine analogue signal processing channels each of which contains Reset Level Clamping, Correlated
Double Sampling (also Sample and Hold), Programmable
Gain, Automatic Gain Control (AGC) and Offset adjust functions.
The output from each of these channels is time multiplexed, in pairs, into three high-speed 16-bit Analogue to Digital
Converters. The digital data is available in a variety of output formats via the flexible data port.
The WM8235 has a user selectable LVDS or CMOS output architecture.
An internal 5-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device.
A programmable automatic Black-Level Calibration function is available to adjust the DC offset of the output data.
The WM8235 features a sensor timing clock generator for both CCD and CIS sensors. The clock generator can accept a slow or fast reference clock input and also has a flexible timing adjustment function for output timing clocks to allow use of many different sensors.
FEATURES
210MSPS conversion rate
16-bit ADC resolution
Current consumption
– 390mA
3.3V single supply operation
Sample and hold / correlated double sampling
Programmable offset adjust (8-bit resolution)
Flexible clamp timing
Pixel clamp / line clamp mode
Programmable clamp voltage
Programmable CIS/CCD timing generator
Internally generated voltage references
Compliant for Spread Spectrum Clock
LVDS/CMOS output options
LVDS 5pair 490MHz 35-bit data
CMOS 90MHz output maximum
Complete on chip clock generator. MCLK 5MHz to 23MHz
Internal timing adjustment
Automatic Gain Control
Automatic Black Level Calibration
56-lead QFN package 7mm x 7mm
Serial control interface
APPLICATIONS
Digital copiers
USB2.0 compatible scanners
Multi-function peripherals
High-speed CCD/CIS sensor interface http://www.cirrus.com
Copyright
Cirrus Logic, Inc., 2010
–2015
(All Rights Reserved)
Rev 4.5
DEC
‘15
WM8235
BLOCK DIAGRAM
VRLC /VBIAS
AVDD1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
CDS
S/H
CDS
S/H
CDS
S/H
CDS
S/H
CDS
S/H
CDS
S/H
CDS
S/H
CDS
S/H
CDS
S/H
AGND1
OFFSET
DAC
+
OFFSET
DAC
+
OFFSET
DAC
+
OFFSET
DAC
+
OFFSET
DAC
+
OFFSET
DAC
+
OFFSET
DAC
+
OFFSET
DAC
+
OFFSET
DAC
+
VREF1C VREF2C VREF3C
VREF
/BIAS
PGA
I/P SIGNAL
POLARITY
ADJUST
PGA
I/P SIGNAL
POLARITY
ADJUST
PGA
I/P SIGNAL
POLARITY
ADJUST
PGA
I/P SIGNAL
POLARITY
ADJUST
PGA
I/P SIGNAL
POLARITY
ADJUST
PGA
I/P SIGNAL
POLARITY
ADJUST
PGA
I/P SIGNAL
POLARITY
ADJUST
PGA
I/P SIGNAL
POLARITY
ADJUST
PGA
I/P SIGNAL
POLARITY
ADJUST
+
+
M
U
X
+
+
+
M
U
X
+
+
+
M
U
X
+
WM8235
DBVDD
16bit
ADC
10/16
+
16bit
ADC
10/16
+
&
D
A
T
A
M
A
P
P
I
N
G
C
O
N
T
R
O
L
D
I
G
I
T
A
L
7
7
7
LVDS(
Chanel link)/
CMOS
7
7
7
16bit
ADC
10/16
+
LDO1
LDO2
HZCTRL
D1P/OP[0]
D1N/OP[1]
D2P/OP[2]
D2N/OP[3]
D3P/OP[4]
D3N/OP[5]
D4P/OP[6]
D4N/OP[7]
D5P/OP[8]
D5N/OP[9]
DCLKP/OC[1]
DCLKN/OC[2]
LDO1VDD
LDO1GND
LDO1VOUT
LDO2VDD
LDO2GND
LDO2VOUT
BLACK LEVEL
CALIBRATION
RLC
DAC
AUTO GAIN
CONTROL
CCD SENSOR
TIMING GENERATION
Phase
Adjustment
MCLK
SERIAL
CONTROL
INTERFACE
SDO
SEN
SCK
SDI
MON DSLCT1 DSLCT2 DBGND
2 Rev 4.5
WM8235
TABLE OF CONTENTS
RECOMMENDED OPERATING CONDITIONS .............................................................. 7
Rev 4.5
3
WM8235
PROGRAMMABLE AUTOMATIC BLACK LEVEL CALIBRATION (BLC) ...............................45
RECOMMENDED EXTERNAL COMPONENT VALUES...................................................... 149
4 Rev 4.5
PIN CONFIGURATION
WM8235
56 55 54 53 52 51 50 49 48 47 46 45 44 43
VREF2C
1
VRLC/VBIAS 2
VREF3C 3
VREF1C 4
SEN 5
SDO 6
SCK 7
SDI 8
LDO2VDD 9
LDO2GND 10
LDO2VOUT 11
DSLCT2 12
MCLK
13
DSLCT1
14
WM8235
15 16 17 18 19 20 21 22 23 24 25 26 27 28
42 CLK8
41 CLK7
40 CLK6
39 CLK5
38 CLK4
37 CLK3
36
CLK2
35 CLK1
34 TGSYNC
33
LDOV1DD
32
LDO1GND
31
LDO1VOUT
30
MON
29
HZCTRL
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
WM8235GEFL/V -40 to 85 o
C
-40 to 85 o
C
PACKAGE
56-lead QFN
(7 x 7 x 0.85 mm)
(Pb-free)
56-lead QFN
(7 x 7 x 0.85 mm)
(Pb-free, tape and reel)
MOISTURE
SENSITIVITY
LEVEL
MSL3
MSL3
PEAK
SOLDERING
TEMPERATURE
260
C
260
C WM8235GEFL/RV
Reel quantity = 2,200
Rev 4.5
5
WM8235
8
9
10
11
5
6
7
40
41
42
43
44
45
46
36
37
38
39
32
33
34
35
23
24
25
26
19
20
21
22
12
13
14
15
16
17
18
27
28
29
30
31
PIN DESCRIPTION
PIN
1
2
3
4
NAME
VREF2C
VRLC
VREF3C
VREF1C
SEN
SDO
SCK
SDI
LDO2VDD
LDO2GND
LDO2VOUT
TYPE DESCRIPTION
Analogue output Mid reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Analogue I/O
Reference voltage input/output
Analogue output Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Analogue output Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Digital input Enables the serial interface when high.
Digital output
Serial interface data output
Digital input Serial interface clock
Digital input
Supply
Supply
Supply
Serial interface data input
Analogue supply
Analogue ground
LDO output
This pin must be connected to AGND via a decoupling capacitor.
DSLCT2
MCLK
Analogue input Device select 2
Analogue input Master clock
DSLCT1
D5N/OP[9]
D5P/OP[8]
D4N/OP[7]
Analogue input Device select 1
LVDS output LVDS Data output 5
– Negative / CMOS output 9
LVDS output LVDS Data output 5
– Positive / CMOS output 8
LVDS output LVDS Data output 4
– Negative / CMOS output 7
D4P/OP[6] LVDS output LVDS Data output 4
– Positive / CMOS output 6
DCLKN/OC[2] LVDS output
LVDS Clock Output
– Negative/ CMOS flag output
DCLKP/OC[1] LVDS output LVDS Clock Output
– Positive/ CMOS clock output
DBGND
DBVDD
D3N/OP[5]
D3P/OP[4]
D2N/OP[3]
D2P/OP[2]
D1N/OP[1]
D1P/OP[0]
Supply
Analogue ground
Supply Analogue supply
LVDS output LVDS Data output 3
– Negative / CMOS output 5
LVDS output LVDS Data output 3
– Positive / CMOS output 4
LVDS output LVDS Data output 2
– Negative / CMOS output 3
LVDS output LVDS Data output 2
– Positive / CMOS output 2
LVDS output LVDS Data output 1
– Negative / CMOS output 1
LVDS output LVDS Data output 1
– Positive / CMOS output 0
HZCTRL
MON
LDO1VOUT
LDO1GND
LDO1VDD
TGSYNC
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
AGND3
IN1
IN2
IN3
Digital input Internal use only. Must be connected to AGND
Analogue output Clock monitor
Supply LDO output.
Supply
This pin must be connected to AGND via a decoupling capacitor.
Analogue ground
Supply
Digital input
Analogue supply
Sensor Timing Sync pulse from host
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output Sensor Timing Output 6
Digital output Sensor Timing Output 7
Digital output Sensor Timing Output 8
Supply Analogue ground
Analogue input
Analogue input
Analogue input
Sensor Timing Output 1
Sensor Timing Output 2
Sensor Timing Output 3
Sensor Timing Output 4
Sensor Timing Output 5
Analogue input 1
Analogue input 2
Analogue input 3
6 Rev 4.5
WM8235
PIN
47
48
49
50
51
52
53
54
55
56
NAME
AGND2
AVDD2
IN4
IN5
IN6
IN7
IN8
IN9
AVDD1
AGND1
TYPE
Supply
Supply
DESCRIPTION
Analogue ground
Analogue supply
Analogue input Analogue input 3
Analogue input Analogue input 4
Analogue input Analogue input 3
Analogue input
Analogue input 4
Analogue input Analogue input 5
Analogue input
Analogue input 6
Supply Analogue supply
Supply Analogue ground
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
Cirrus Logic tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30
C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Analogue supply voltage: AVDD1-2, LDO1VDD-LDO2VDD, DBVDD
MIN
GND - 0.3V
MAX
GND + 5V
Analogue grounds: AGND1-3, LDO1GND-LDO2GND, DBGND
Analogue inputs (IN1-6)
Other Analogue pins
Digital I/O pins
Operating temperature range: T
A
Storage temperature prior to soldering
GND - 0.3V
GND - 0.3V
GND + 0.3V
AVDD + 0.3V
GND - 0.3V AVDD + 0.3V
GND - 0.3V AVDD + 0.3V
-40
C +85
30
C max / 85% RH max
C
-65
C +150
C
Storage temperature after soldering
Notes:
1.
2.
GND denotes the voltage of any ground pin.
AGND, LDOGND and DBGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
Operating temperature range
Analogue Supply voltage
SYMBOL
T
A
AVDD1-2
LDO1VDD-
LDO2VDD
DBVDD
MIN
-40
2.97
TYP
3.3
MAX
85
3.63
UNITS
C
V
Rev 4.5
7
WM8235
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, T
A
= 25
C, MCLK= 23.3MHz unless otherwise stated.
UNIT PARAMETER SYMBOL TEST
CONDITIONS
MIN
Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)
Conversion rate per channel
Full-scale input voltage
(see Note 1)
ADCFS=0, Max Gain
ADCFS=0, Min Gain
ADCFS=1, Max Gain
ADCFS=1, Min Gain
5
Input signal voltage range V
IN
Input capacitance
Full-scale transition error
Zero-scale transition error
Differential non-linearity
Integral non-linearity (pk-pk/2)
Channel to channel crosstalk
C
IN
INL
DNL
Channel to channel gain matching Min Gain
Output noise
Max Gain
SF_INP=0
SF_INP=1
Inputs to AGND
Gain = 0dB;
AGAIN[4:0] = 02(hex)
DGAIN[11:0] = 6AB(hex)
Gain = 0dB;
AGAIN[4:0] = 02(hex)
DGAIN[11:0] = 6AB(hex)
10-bit
10-bit
10-bit, Unity Gain
(Unused channels grounded)
10-bit
AGND
AGND
BLC disabled Channel to channel offset matching
Programmable Gain Amplifier
Total Resolution (Ga + Gd)
Analogue Gain
Max gain, each channel (Ga)
Min gain, each channel (Ga)
Digital Gain
Max gain, each channel (Gd)
Min gain, each channel (Gd)
Max gain, each channel
(Ga + Gd)
Min gain, each channel
(Ga + Gd)
Analogue to Digital Converter
Resolution
Speed
G
T
Ga
Ga
MAX
Ga
MIN
Gd
Gd
MAX
Gd
MIN
G
G
T
T
MAX
MIN
AGAIN[4:0] = 1F(hex)
AGAIN[4:0] = 0(hex)
DGAIN[11:0] = FFF(hex)
DGAIN[11:0] = 400 (hex)
AGAIN[4:0] = 1F(hex)
DGAIN[11:0] = FFF(hex)
AGAIN[4:0] = 0(hex)
DGAIN[11:0] = 400 (hex)
TYP
0.12
2.0
0.18
3.0
10
20
20
+/-0.5
+/-1
5
15
0.5
+/-0.5
70
23.3
AVDD
1.2
12
+/-1.5
+/-4
2.5
210
12
0.6 + 0.3 * AGAIN[4:0]
8.00 9.9 11.43
0.44 0.6
DGAIN[11:0] / 2
11
0.77
2
0.5
19.8
0.3
16
MAX
70
MSPS
Vp-p
Vp-p
Vp-p
Vp-p
V
V pF mV mV
LSB
LSB
%
%
LSB rms
LSB mV bits
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V bits
MSPS
8 Rev 4.5
WM8235
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, T
A
= 25
C, MCLK= 23.3MHz unless otherwise stated.
PARAMETER SYMBOL TEST
CONDITIONS
MIN TYP MAX UNIT
References
Upper reference voltage
V
REF1C
Lower reference voltage
V
V
V
REF3C
REF2C
REF1C3C
ADCFS=0
ADCFS=1
ADCFS=0
ADCFS=1
ADCFS=0
ADCFS=1
1.14
0.72
1.00
2.05
2.25
1.25
1.05
1.2
0.8
1.2
1
1.26
0.88
1.35
V
V
V
V
V
V
V
Input return bias voltage
Diff. Reference voltage
(VREF1C-VREF3C)
Output resistance
VREF1C, VREF3C, VREF2C
VRLC/Reset-Level Clamp (RLC)
VRLC input voltage range
(see Note 2)
RLC switching impedance
RLC short-circuit current
RLC output resistance
RLC Hi-Z leakage current
RLCDAC resolution
RLCDAC step size
RLCDAC output voltage at code 0(hex)
RLCDAC output voltage at code 1F(hex)
V
V
V
VRLC
RLCSTEP
RLCBOT
RLCTOP
SF_INP=0
SF_INP=1
VRLC = 0 to AVDD
VRLC_TOP_SEL=0
VRLC_TOP_SEL=1
VRLC_TOP_SEL=0,
VRLC_VSEL[4:0]=00000
VRLC_TOP_SEL=1,
VRLC_VSEL[4:0]=00000
VRLC_TOP_SEL=0,
VRLC_VSEL[4:0]=11111
VRLC_TOP_SEL=1,
VRLC_VSEL[4:0]=11111
0.11
0.11
50
2
2
5
0.09
0.048
0.2
0.11
3.0
1.6
0.5
0.5
3.0
1.2
1
V
mA
A bits
V/step
V
V
V
V
LSB
LSB
VRLC DNL
VRLC INL
Offset DAC, Monotonicity Guaranteed
Resolution
Differential non-linearity DNL
Integral non-linearity
Step size
Output voltage
INL
Code 00(hex)
Code FF(hex)
-400
+100
8
0.5
0.5
2.04
-250
+250
1
1
-100
+400 bits
LSB
LSB mV/step mV mV
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
Low level input voltage
V
V
IH
IL
0.7
AVDD
V
V
High level input current
Low level input current
Input capacitance
I
I
IH
IL
C
I
5
0.2
AVDD
1
1
A
A pF
Rev 4.5
9
WM8235
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, T
A
= 25
C, MCLK= 23.3MHz unless otherwise stated.
PARAMETER SYMBOL TEST
CONDITIONS
MIN TYP MAX UNIT
CMOS Outputs
High level output voltage
Low level output voltage
High impedance output current
TG Outputs
High level output voltage
V
OH
V
OL
I
OZ
I
OH
= 6mA
I
OL
= 1mA
AVDD
– 0.5
0.5
1
V
V
A
Low level output voltage
High impedance output current
Digital IO Pins
Applied high level input voltage
V
OHTG
V
OLTG
I
OZTG
I
OH
= 1mA
I
OL
= 1mA
Grounded
AVDD
– 0.5
0.5
1
V
V
A
Applied low level input voltage
V
IH
V
IL
0.7
AVDD
0.2
AVDD
V
V
High level output voltage
Low level output voltage
Low level input current
High level input current
Input capacitance
Output Impedance
High impedance output current
LVDS Outputs
Differential load impedance
Differential steady-state output voltage magnitude
Change in the steady-state differential output voltage magnitude between opposite binary states
Steady-state common-mode output voltage
Peak-to-peak common-mode output
Short-circuit output current
High-impedance state output current
Supply Currents
Total supply current
active
V
OH
V
OL
I
IL
I
IH
C
I
R
O
I
OZ
R
L
|V
OD
|
Δ|V
OD
|
V
OC
(SS)
V
OC
(PP)
I
OS
I
OZ
I
OH
= 1mA
I
OL
= 1mA
I
O
= 1mA
LVDS_AMP=011,
R
L
=100Ω
R
L
=100Ω
R
L
=100Ω
AVDD
– 0.5
90
–6
–10
5
38
100
200
1.25
20
0.5
1
1
1
110
15
50
6
10
V
V
A
A pF
Ω
A
Ω mV mV
V mV mA uA
SF_INP=0, SF_VRLC=0 390 mA
SF_INP=1, SF_VRLC=1 440 mA
Total supply current
full power down mode
1.2 mA
Notes:
1. Full-scale input voltage denotes the differential input signal amplitude (V
IN
-VRLC in non-CDS mode, V
IN
-RESET level in
CDS mode) that corresponds to the ADC full-scale input level.
2. If AVDD < 3.0V, the VRLC input voltage must not exceed AVDD.
10 Rev 4.5
WM8235
INTERNAL POWER ON RESET CIRCUIT
AVDD
VDD
LDOOUT
T
Power On Reset
Circuit
GND
INTERNAL PORB
AGND
Figure 1 Internal Power On Reset Circuit Schematic
The WM8235 includes an internal Power-On-Reset Circuit, as shown in Figure 1, which is used reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors LDOOUT. It asserts PORB low if AVDD or LDOOUT is below a minimum threshold.
LDOOUT
LDOGND
V pord_on
AVDD
V pora
AGND
HI
INTERNAL PORB
LO
No Power
POR
Undefined
Internal
POR active
Device Ready
V pora_off
Internal POR active
Figure 2 Typical Power up Sequence where AVDD is Powered before LDOOUT
Figure 2 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When LDOOUT rises to Vpord_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off.
SYMBOL
Vpora
Vpora_off
Vpord_on
MIN
0.4
0.4
0.5
TYP
0.6
0.6
0.7
MAX
0.8
0.8
0.9
Table 1 Typical POR Operation (typical values, not tested)
UNIT
V
V
V
Rev 4.5
11
WM8235
SIGNAL TIMING REQUIREMENTS
SERIAL CONTROL INTERFACE
t
CSU t
CHO
SEN
(input) t
SCY
SCK
(input) t
SCH t
SCL
SDI
(input) t
DSU t
DHO
SDO
(output) t
DL
Figure 3 Serial Interface Timing
PARAMETER
SEN falling edge to SCK rising edge
SCK falling edge to SEN rising edge
SCK pulse cycle time
SCK pulse width low
SCK pulse width high
SDI to SCK set-up time
SDI to SCK hold time
SCK falling edge to SDO transition
SYMBOL
t
CSU t
CHO t
SCY t
SCL t
SCH t
DSU t
DHO t
DL
TEST CONDITIONS MIN
20
20
83.3
33
33
20
20
TYP MAX
33
UNITS
ns ns ns ns ns ns ns ns
The internal control registers are programmable via the serial digital control interface. The register contents can be read back via the serial interface on pin SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. This ensures that all registers are set to their default values.
DEVICE IDENTIFICATION
Up to 4 WM8235 devices can share a common set of serial interface pins. Each device on the common interface bus must be given a different device ID. The device ID is set by the input pin
DSLCT2 and DSLCT1as shown in Table 2.
DSLCT2 DSLCT1
L
L
H
H
L
H
L
H
Table 2 Device Identification
DEVICE ID
(ID[1:0])
00
01
10
11
12 Rev 4.5
WM8235
REGISTER WRITE
Figure 4 shows sequence of operations for performing a register write. Three pins, SCK, SDI and
SEN are used for the control interface. A 16-bit address (R/W, CS0, CS1, CS2, A11 to A0) is clocked in through SDI, MSB first, followed by an 8
–bit data word (b7 to b0), also MSB first. Setting address bit R/W to 0 indicates that the operation is a register write. The device ID bits (CS0 and CS1) indicate which device is being written to on a shared control bus. A register write with CS2 set to 1 writes data to all devices on the common bus. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a rising edge on the SEN pin transfers the data to the appropriate internal register.
DESCRIPTION CS2
0
1
CS1
(DSLCT2)
ID[1:0]
CS0
(DSLCT1)
X
Table 3 Device Identification
X
Indicated a device to write data
Writes data to all devices
SEN
SCK
SDI
0 CS2
CS0 A11 A2 A1 A0 B7 B6 B5 B2 B1 B0
R/W
3bit device ID 12-bit Control register address 8-bit control register data
Figure 4 Serial Interface Register Write
REGISTER READ-BACK
described above but with address bit R/W set to 1, followed by an 8-bit dummy data word. Writing address (A11 to A0) will cause the contents (B7 to B0) of corresponding register in the addressed device to be output MSB first on pin SDO (on the following edge of SCK). In this mode, the CS2 register should be set to 0.
SEN
SCK
SDI
SDO
1
R/W
0
3bit device ID
CS0 A11
Hi-Z
A2 A1 A0 X
X: Don’t care
X X
B7 B6 B5
12-bit Read back register address 8-bit outputl register data
X X X
B2 B1 B0
Hi-Z
Figure 5 Serial Interface Register Read-back
Rev 4.5
13
INPUT VIDEO SAMPLING
NON-CDS (S/H) MODE
tMCLKD tPER
MCLK (input)
Input Video (Input)
VSMP_RISE[5:0]
VSMP_FALL[5:0]
VSMP (Internal) tVSMPH tMCLKH tMCLKL tVSMPD
Figure 6 Input Video Timing (non-CDS (S/H) mode)
CDS MODE
t
MCLKD
MCLK (input) t
PER
Input Video (Input)
RSMP (Internal) t
RSMPD
RSMP_RISE[5:0]
RSMP_FALL[5:0] t
RSMPH
VSMP_RISE[5:0]
VSMP_FALL[5:0] t
VSMPH
VSMP (Internal) t
MCLKH t
MCLKL t
VSMPD
WM8235
Figure 7 Input Video Timing (CDS mode)
14 Rev 4.5
WM8235
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, T
A
= 25
C, MCLK= 23.3MHz unless otherwise stated.
PARAMETER
MCLK cycle period (see note 2)
MCLK high period (see note 2)
MCLK low period (see note 2)
MCLK rising edge to DLL tap 0
Aperture delay
(from RSMP falling edge)
Aperture delay
(from VSMP falling edge)
RSMP high period
VSMP high period
REGISTER
ADDRESS
R130 (82h)
RSMP rise
R131 (83h)
RSMP fall
R132 (84h)
VSMP rise
R133 (85h)
VSMP fall
BIT
5:0
5:0
5:0
5:0
LABEL
SYMBOL
t t
PER t
MCLKH t
MCLKL t
MCLKD t
RSMPD
VSMPD
RSMP_RISE[5:0]
RSMP_FALL[5:0]
VSMP_RISE[5:0]
VSMP_FALL[5:0]
TEST CONDITIONS
DEFAULT
01_1100
10_0110
00_1000
10_1000
MIN
42.9 t t
RSMPH
VSMPH
5
5
RSMP falling edge to VSMP rising edge
VSMP falling edge to RSMP rising edge
Output data latency
(from 1 st
falling edge of VSMP)
Notes:
tRV tVR
LAT
LVDS 10-bit 5pair mode
Other output modes
0.5
0.5
7
6
1. 1clock = t
PER
(MCLK cycle period)
2. MCLK cycle period and MCLK high/low period are measured at 50% of the respective rising/falling edges
8 * t
PER
/60
DESCRIPTION
RSMP rise edge (0 to 59)
RSMP fall edge (0 to 59)
VSMP rise edge (0 to 59)
VSMP fall edge (0 to 59)
TYP
5
5
MAX
200
0.4 * t
PER
0.5 * t
PER
0.6 * t
PER
0.4 * t
PER
0.5 * t
PER
0.6 * t
PER
20
UNITS
ns ns ns ns ns ns ns ns ns ns clock clock
Rev 4.5
15
OUTPUT DATA TIMING (CMOS OUTPUT)
t
SKOP
OP[10:0]
(Output)
WM8235
OC1
(Output)
Figure 8 CMOS Output Data Timing
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, T
A
= 25
C, MCLK= 23.3MHz unless otherwise stated.
PARAMETER
Data output skew
SYMBOL
t
SKOP
TEST CONDITIONS MIN TYP
+/-500
MAX UNITS
ps
OUTPUT DATA TIMING (LVDS OUTPUT)
t
SKLV t
SKLV
D1,D2,D3
D4,D5
80%
DCLK
20% t
LVTf t
LVTr
Figure 9 CMOS Output Data Timing
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, T
A
= 25
C, MCLK= 15MHz unless otherwise stated.
PARAMETER
LVDS output skew
LVDS output signal rise time
LVDS output signal fall time
SYMBOL
t
SKLV t
LVTr t
LVTf
TEST CONDITIONS MIN TYP
+/-250
MAX
1
1
UNITS
ps ns ns
16 Rev 4.5
WM8235
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on the front page of this datasheet.
The WM8235 samples up to nine inputs (IN1, IN2, IN3, IN4, IN5, IN6, IN7, IN8 and IN9) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using between one and nine processing channels.
Each processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and a 12-bit
Programmable Gain Amplifier (PGA).
The processing channel outputs are switched, in pairs, alternately by a 3:1 multiplexer to the three
ADC inputs.
The ADC then converts each resulting analogue signal to a digital word. The digital output from the
ADC is presented in a variety of possible output formats in LVDS and CMOS format.
On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial interface.
The device has an automatic Black-Level Calibration function which allows the D.C. offset determined during the optically-black pixels at the beginning of the linear sensor to be removed during the imagepixels.
The WM8235 also has an Automatic Gain Control function which automatically adjusts the gain to an appropriate level for a detected input level.
The device incorporates a sensor timing generation function which allows CCD and CMOS sensor timing to be controlled directly from the device using internal clock generation and register settings.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8235 lies within the supply voltage range (0V to AVDD), the output signal from a CCD is usually level shifted by coupling through a capacitor, C
IN.
The RLC circuit clamps the WM8235 side of this capacitor to a suitable voltage through a CMOS switch during the CCD reset period (pixel clamping) or during the black pixels (line clamping). In order for clamping to produce correct results the input voltage during the clamping must be a constant value.
Note that if the A.C. coupling capacitor (C
IN
) is used in non-CDS mode (CDS=0), then to minimise code drift, line clamping should be used and internal input voltage buffers enabled using the SF_INP and SF_VRLC register bit.
Alternatively, if the input signal contains a stable reference/reset level in CDS mode, then pixel clamping should be used (CLPMD=1), and the voltage buffers need not be enabled. Note that the pixel clamping is used only CDS mode (CDS=1).
This figure shows a single channel; however, all 9 channels are identical, each with its own clamp switch controlled by the common CLMP signal.
The method of control chosen depends upon the characteristics of the input video. The VRLCEN register bit must be set to 1 to enable clamping; otherwise, the RLC switch cannot be closed (by default VRLCEN=1).
Note that unused inputs should be grounded through a decoupling capacitor, if reset level clamping is used.
Rev 4.5
17
WM8235
C
IN
IN*
VSMP 'Video' sample capacitor
CONTROL
INTERFACE
CLAMP
RLC switch
VSMP (if CDS=0)
RSMP (if CDS=1)
CLAMP
VSMP
VSMP (if CDS=0)
RSMP (if CDS=1)
'Reference' sample capacitor
VRLC/
VBIAS
5-BIT
RLCDAC
VRLC_VSEL[4:0]
VRLCEN
Figure 10 RLC Clamp Control Options
In CDS operation, when an input waveform has a stable reference level on every pixel, it may be desirable to clamp every pixel during this period. Setting CLAMP=high means that the RLC switch is
closed whenever the RSMP is high, as shown in Figure 11.
In non-CDS operation, setting CLAMP=high means that the RLC switch is closed whenever the
VSMP is high, as shown in Figure 12.
reference
("black") level video level
INPUT VIDEO
SIGNAL
Pixel counter
VSMP
RSMP
CLAMP
RLC switch control
"CLAMP"
Video sample taken on fallling edge of VSMP
Reset/reference sample taken on fallling edge of RSMP
RLC switch closed when RSMP=1
Figure 11 Line Clamp Operation, CDS operation shown
INPUT VIDEO
SIGNAL
Pixel counter
VSMP
CLAMP
RLC switch control
"CLAMP"
Video sample taken on fallling edge of VSMP video level
RLC switch closed when VSMP=1
Figure 12 Line Clamp Operation, non-CDS operation shown
18 Rev 4.5
WM8235
CDS/NON-CDS PROCESSING
For CCD type input signals, containing a fixed reference/reset level, the signal may be processed using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise. With
CDS processing, the input waveform is sampled at two different points in time for each pixel, once during the reference/reset level and once during the video level. To sample using CDS, register bit
CDS must be set to 1 (default = 0). This causes the signal reference to come from the video
reference level as shown in Figure 13.
For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled during VSMP low period in this mode. Note that if the A.C. coupling capacitor (C
IN
) is used in non-CDS mode (CDS=0), then to minimise code drift, line clamping should be used and internal input voltage buffers enabled using the SF_INP and
SF_VRLC registers. Alternatively, if the input signal contains a stable reference/reset level, then pixel clamping should be used, and the voltage buffers need not be enabled.
C
IN
IN*
VRLC/
VBIAS
CLAMP
RLC switch
VSMP
VSMP (if CDS=0)
RSMP (if CDS=1)
'Video' sample capacitor
CONTROL
INTERFACE
CLAMP
VSMP
VSMP (if CDS=0)
RSMP (if CDS=1)
'Reference' sample capacitor
5-BIT
RLCDAC
VRLC_VSEL[4:0]
VRLCEN
Figure 13 CDS/non-CDS Input Configuration
Rev 4.5
19
WM8235
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by a 12-bit PGA. The gain and offset for each channel are independently programmable by writing to control bits DACINP[7:0] for the Offset DAC, and AGAIN[4:0] and DGAIN[11:0] for the PGA.
The gain characteristic of the WM8235 PGA is shown in Figure 14.
9.9
7.8
5.4
9.9V/V
32step
1.99
APGA = 0.6 + 0.3 * AGAIN[4:0]
DPGA = DGAIN[11:0] / 2^11
Total Gain Range
0.3V/V≦ APGA*DPGA ＜ 19.8V/V
1.99V/V
3.0
3072 step
1.0
0.6
0 8 16 24
GAIN CODE (AGAIN[4:0])
Figure 14 PGA Gain Characteristic
31
0.6V/V 0.5
1024 2048 3072
GAIN CODE (DGAIN[11:0])
4095
0.5V/V
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA can be offset to match the full-scale range of the differential ADC
(1.5*[VREF1C-VREF3C]).
For negative-going input video signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range by setting register bits PGAFS=0. For positive going input signals the black level should be offset to the bottom of the ADC range by setting PGAFS=1.
PGAFS= 0, PGA gain=0.9V/V, Offset = 0V
Output code
= (V
RLC
- V
IN
) * Gain * 65535/(1.5*[VREF1C-VREF3C])
VRLC/VBIAS
PGAFS= 1, PGA gain=0.9V/V, Offset = 0V
Output code
= (V
IN
- V
RLC
) * Gain * 65535/(1.5*[VREF1C-VREF3C])
V
IN
(INPx)
1.33V
or
2.0V
1.33V
or
2.0V
OP=0 OP=32768
V
IN
(INPx)
OP=65535 OP=0 OP=32768
VRLC/VBIAS
OP=65535
Figure 15 ADC Input Black Level Adjust Settings
20 Rev 4.5
OVERALL SIGNAL FLOW SUMMARY
Figure 16 represents the processing of the video signal through the WM8235.
WM8235
V
IN
V
RESET
CDS = 1
INPUT
SAMPLING
BLOCK
V
1
+
-
INPUT
INVERT
BLOCK
V1=V1 if PGAFS = 1
V1= -V1 if PGAFS = 0
CDS = 0
V
VRLC
OFFSET DAC
BLOCK
V
2
+
-
PGA
BLOCK
V
3
X analog
APGA gain
A= 0.6+0.3*AGAIN[4:0]
Offset
DAC
250mV*(DAC[7:0]-127.5)/127.5
VRLCEN=0 VRLCEN=1
ADC BLOCK
16bits
D
1
digital
RLC
DAC
See parametrics for
DAC voltages.
V
IN
is IN*
V
RESET
is V
IN
sampled during reset clamp
V
RLC
is voltage applied to VRLC/VBIAS pin
Figure 16 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V
1
. For CDS, this is the difference between the input video level V
IN
and the input reset level V
RESET
. For non-CDS this is the difference between the input video level V
IN
and the voltage on the VRLC/VBIAS pin, V
VRLC
, optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V
2
.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V
3
.
The ADC BLOCK then converts the analogue signal, V
3
, to a 16-bit unsigned digital output, D
1
.
Rev 4.5
21
WM8235
ADC PGA BIAS CURRENT CONTROL
The WM8235 can be changed the bias current for PGA and ADC comparator as the following step. It would be effective for high frequency operation.
1. R1C0h=1
2. R1CBh=11h
REGISTER
ADDRESS
R448 (1C0h)
User access control2
BIT
0
LABEL
User_KEY2
DEFAULT
0 0 = User access2 disabled
1 = User access2 enabled
DESCRIPTION
REGISTER
ADDRESS
R459 (1CBh)
Comp control
BIT
1:0
LABEL
PT_COMP
DEFAULT
01
DESCRIPTION
01 = Standard operation
11 = High performance operation
Other = Inhibit.
Notes:
1.
2.
To change the Comp control, the USER_KEY2 bit must be set to ‘1’.
If it’s not required to change this register, must be set as default.
22 Rev 4.5
WM8235
PLL DLL SETUP
WM8235 is supporting wide range of input frequency. PLL_EXDIV_SEL[2:0], LVDLGAIN[1:0] and
DLGAIN[1:0] must be configured by MCLK clock rate and data output format.
Note that after PLL and DLL configuration, the device must be reset as the following step.
R03[1:0]=11 (PDMD=1, PD=1)
Delay 1ms
R03[1:0]=00 (Normal operation)
Also, several LVDS operation mode is required to change internal LDO configuration to perform
LVDS clocking properly. The following register need to set to change the LDO configuration.
R1B0h=1
R1B4h=12h
17.5
~
23.3
15.0
~
17.49
12.0
~
14.99
10.0
~
11.99
8.33
~
9.99
7.5
~
8.32
5.0
~
7.49
000 000 001 001
WM8235
CMOS 10 bit
LVDS 5pair 10bit
LVDS 5pair 16bit
LVDS 3pair 10bit
LVDS 4pair 12bit
LVDS 3pair 16bit
Max sample rate
10MHz
23.3MHz
15.56MHz
14.0MHz
7.0MHz
MCLK Clock rate
[MHz]
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
DLGAIN[1:0]
LDO setting
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
DLGAIN[1:0]
LDO setting
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
DLGAIN[1:0]
LDO setting
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
DLGAIN[1:0]
LDO setting
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
DLGAIN[1:0]
LDO setting
10 10 10 10
001 001 001 001 001 010 010
00 00 01 01 01 01 01
01 01
12h 12h
10 10 10 10 10
000 000 000 000 001 001
00
01
00
10
00
10
01
10
01
10
01
10
12h 12h 12h
000 000 000 001 001
00
10
00
10
12h 12h
01
10
01
10
01
10
001
00
10
12h
Table 4 PLL and DLL Setting
Rev 4.5
23
WM8235
REGISTER
ADDRESS
R28 (1Ch)
PLL divider control 1
BIT
6:4
LABEL
PLL_EXDIV_
SEL[2:0]
DEFAULT
001
DESCRIPTION
Select EX DIV ratio.
Need to set according to input frequency. See Table 4.
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16
101 to 111 = reserved.
REGISTER
ADDRESS
R128 (80h)
DLL config 1
BIT
5:4
LABEL
DLGAIN[1:0]
DEFAULT
10
DESCRIPTION
gain control of DLL delay line
Need to set according to input frequency. See Table 4.
REGISTER
ADDRESS
R129 (81h)
DLL config 2
BIT
5:4
LABEL
LVDLGAIN[1:0]
DEFAULT
01
DESCRIPTION
gain control of LVDS DLL delay line
Need to set according to input frequency. See Table 4.
REGISTER
ADDRESS
R432 (1B0h)
User access control
BIT
0
LABEL
USER_KEY
DEFAULT
0 0 = User access disabled
1 = User access enabled
REGISTER
ADDRESS
R436 (1B4h)
LDO2 control
BIT
4:0
LABEL
LDO2 VSEL
DEFAULT
1_0000 1_0000 = 1.8V
1_0010 = 2.0V
Notes:
1.
2.
To change the LDO2 control, the USER_KEY bit must be set to ‘1’.
If it’s not required to change this register, it must be set as default.
DESCRIPTION
DESCRIPTION
24 Rev 4.5
WM8235
OUTPUT DATA FORMAT
The output from the WM8235 can be presented in several different formats under control of the
CMOSMODE and the LVDSMODE register. Depending on the output modes, maximum MCLK rate is different as sown in Table 5.
MODES DESCRIPTION
1
2
3
4
LVDS 10-bit 5pair
LVDS 16-bit 5pair
LVDS 10-bit 3pair
LVDS 16-bit 3pair
5
6
LVDS 12-bit 4pair
CMOS 10-bit
Table 5 Output Format and Data Rate
OUTPUT
DATA RATE
MCLK x21
MCLK x31.5
MCLK x31.5
MCLK x63
MCLK x31.5
MCLK x9
MAXIMUM
MCLK RATE
23.3MSPS
15.5MSPS
14.0MSPS
7MSPS
14.0MSPS
10MSPS
LVDS 10-BIT 5PAIR MODE
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
ADC1
ADC2
ADC3
MCLK x3 (ADCLK)
IN1
IN4
IN7
IN2
IN5
IN8
IN3
IN6
IN9
MCLK x3 (OCLK)
D5
D4
D3
D2
D1
DCLK
A
H H L L L H H
B
H H L L L H H
MCLK x21 (LVCK)
C
H H L L L H H
A
D5
D4
D3
D2
D1
DCLK
S0
IN1[4]
S4
IN2[6]
IN3[3]
H
S1
IN1[5]
IN2[0]
IN2[7]
IN3[4]
H
S2
IN1[6]
IN2[1]
IN2[8]
IN3[5]
L
IN1[0]
IN1[7]
IN2[2]
IN2[9]
IN3[6]
L
IN1[1]
IN1[8]
IN2[3]
IN3[0]
IN3[7]
L
IN1[2]
IN1[9]
IN2[4]
IN3[1]
IN3[8]
H
IN1[3]
S3
IN2[5]
IN3[2]
IN3[9]
H
Rev 4.5
25
26
WM8235
B
D5
D4
D3
D2
D1
DCLK
S0
IN4[4]
S4
IN5[6]
IN6[3]
H
S1
IN4[5]
IN5[0]
IN5[7]
IN6[4]
H
C
D5
D4
D3
D2
D1
DCLK
S0
IN7[4]
S4
IN8[6]
IN9[3]
H
S1
IN7[5]
IN8[0]
IN8[7]
IN9[4]
H
Table 6 10-bit 5pair LVDS Output Format
S2
IN7[6]
IN8[1]
IN8[8]
IN9[5]
L
S2
IN4[6]
IN5[1]
IN5[8]
IN6[5]
L
IN4[0]
IN4[7]
IN5[2]
IN5[9]
IN6[6]
L
IN7[0]
IN7[7]
IN8[2]
IN8[9]
IN9[6]
L
IN4[1]
IN4[8]
IN5[3]
IN6[0]
IN6[7]
L
IN7[1]
IN7[8]
IN8[3]
IN9[0]
IN9[7]
L
IN4[2]
IN4[9]
IN5[4]
IN6[1]
IN6[8]
H
IN7[2]
IN7[9]
IN8[4]
IN9[1]
IN9[8]
H
IN7[3]
S3
IN8[5]
IN9[2]
IN9[9]
H
LVDS 16-BIT 5PAIR MODE
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
ADC1
ADC2
ADC3
MCLK x3 (ADCLK)
IN1
IN4
IN7
IN2
IN5
IN8
IN3
IN6
IN9
IN1
IN4
IN7
IN3
IN6
IN9
MCLK x4.5 (OCLK)
D5
D4
D3
D2
D1
DCLK
A B C D E A2 D2
H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H
MCLK x31.5 (LVCK)
A
D5
D4
D3
D2
D1
DCLK
S0
IN1[4]
S1
IN1[5]
S2
IN1[6]
IN1[0]
IN1[7]
IN1[1]
IN1[8]
IN1[11] IN1[12] IN1[13] IN1[14] IN1[15]
IN2[2] IN2[3] IN2[4] IN2[5] IN2[6]
IN2[9]
H
IN1[2]
IN1[9]
IN2[0]
IN2[7]
IN1[3]
IN1[10]
IN2[1]
IN2[8]
IN2[10] IN2[11] IN2[12] IN2[13] IN2[14] IN2[15]
H L L L H H
IN4[3]
S3
IN5[5]
IN6[2]
IN6[9]
H
Rev 4.5
Rev 4.5
WM8235
C
D5
D4
D3
D2
D1
DCLK
B
D5
D4
D3
D2
D1
DCLK
D
D5
D4
D3
D2
D1
DCLK
E
D5
D4
D3
D2
D1
DCLK
A2
D5
D4
D3
D2
D1
DCLK
S0
IN3[4] IN3[5] IN3[6] IN3[7] IN3[8]
IN3[11] IN3[12] IN3[13] IN3[14] IN3[15]
IN4[2]
IN4[9]
H
IN6[9]
H
S0
IN8[2]
IN8[9]
H
S1 S2 IN[0] IN3[1]
S0
IN5[4]
S1
IN5[5]
S2
IN5[6]
IN5[0]
IN5[7]
IN5[1]
IN5[8]
IN5[11] IN5[12] IN5[13] IN5[14] IN5[15]
IN6[2] IN6[3] IN6[4] IN6[5] IN6[6]
IN3[2]
IN3[9]
IN4[0]
IN5[2]
IN5[9]
IN6[0]
IN6[7]
IN3[3]
IN3[10]
IN4[1]
IN4[3] IN4[4] IN4[5] IN4[6] IN4[7] IN4[8]
IN4[10] IN4[11] IN4[12] IN4[13] IN4[14] IN4[15]
H L L L H H
IN5[3]
IN5[10]
IN6[1]
IN6[8]
IN6[10] IN6[11] IN6[12] IN6[13] IN6[14] IN6[15]
H L L L H H
S1
IN7[4] IN7[5] IN7[6] IN7[7] IN7[8]
IN7[11] IN7[12] IN7[13] IN7[14] IN7[15]
IN8[3]
IN8[10]
H
S2
IN8[4]
IN8[11]
L
IN7[0]
IN8[5]
IN8[12]
L
IN7[1]
IN8[6]
IN8[13]
L
IN7[2]
IN7[9]
IN8[0]
IN8[7]
IN8[14]
H
IN7[3]
IN7[10]
IN8[1]
IN8[8]
IN8[15]
H
S0
IN9[4]
S1
IN9[5]
S2
IN9[6]
IN9[0]
IN9[7]
IN9[1]
IN9[8]
IN9[11] IN9[12] IN9[13] IN9[14] IN9[15]
IN1[2] IN1[3] IN1[4] IN1[5] IN1[6]
IN1[9]
H
IN9[2]
IN9[9]
IN1[0]
IN1[7]
IN9[3]
IN9[10]
IN1[1]
IN1[8]
IN1[10] IN1[11] IN1[12] IN1[13] IN1[14] IN1[15]
H L L L H H
S0 S1 S2 IN2[0] IN2[1]
IN2[4] IN2[5] IN2[6] IN2[7] IN2[8]
IN2[11] IN2[12] IN2[13] IN2[14] IN2[15]
IN3[2]
IN3[9]
H
IN3[3]
IN3[10]
H
IN3[4]
IN3[11]
L
IN3[5]
IN3[12]
L
IN3[6]
IN3[13]
L
IN2[2]
IN2[9]
IN3[0]
IN3[7]
IN3[14]
H
IN2[3]
IN2[10]
IN3[1]
IN3[8]
IN3[15]
H
27
28
WM8235
B2
D5
D4
D3
D2
D1
DCLK
S0 S1 S2 IN4[0] IN4[1]
IN4[4] IN4[5] IN4[6] IN4[7] IN4[8]
IN4[11] IN4[12] IN4[13] IN4[14] IN4[15]
IN5[2]
IN5[9]
IN4[2]
IN4[9]
IN5[0]
IN4[3]
IN4[10]
IN5[1]
IN5[3] IN5[4] IN5[5] IN5[6] IN5[7] IN5[8]
IN5[10] IN5[11] IN5[12] IN5[13] IN5[14] IN5[15]
H H L L L H H
C2
D5
D4
D3
D2
D1
DCLK
S0
IN6[4]
S1
IN6[5]
S2
IN6[6]
IN6[0]
IN6[7]
IN6[1]
IN6[8]
IN6[2]
IN6[9]
IN6[3]
IN6[10]
IN6[11] IN6[12] IN6[13] IN6[14] IN6[15]
IN7[2] IN7[3] IN7[4] IN7[5] IN7[6]
IN7[9]
IN7[0]
IN7[7]
IN7[1]
IN7[8]
IN7[10] IN7[11] IN7[12] IN7[13] IN7[14] IN7[15]
H H L L L H H
D2
D5
D4
D3
D2
D1
DCLK
Table 7 16-bit 5pair LVDS Output Format
S0 S1 S2 IN8[0] IN8[1]
IN8[4] IN8[5] IN8[6] IN8[7] IN8[8]
IN8[11] IN8[12] IN8[13] IN8[14] IN8[15]
IN9[2]
IN9[9]
H
IN9[3]
IN9[10]
H
IN9[4]
IN9[11]
L
IN9[5]
IN9[12]
L
IN9[6]
IN9[13]
L
IN8[2]
IN8[9]
IN9[0]
IN9[7]
IN9[14]
H
IN8[3]
IN8[10]
IN9[1]
IN9[8]
IN9[15]
H
LVDS 10-BIT 3PAIR MODE
WM8235
CMOS 10 bit
LVDS 5pair 10bit
LVDS 5pair 16bit
LVDS 3pair 10bit
LVDS 3pair 16bit
Max sample rate MCLK Clock rate
PLL_EXDIV_SEL[2:0]
10MHz
LVDLGAIN[1:0]
DLGAIN[1:0]
23.3MHz
LDO configuration
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
15.56MHz
DLGAIN[1:0]
LDO configuration
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
14.0MHz
DLGAIN[1:0]
LDO configuration
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
7.0MHz
DLGAIN[1:0]
LDO configuration
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
DLGAIN[1:0]
LDO configuration
23.3
20 18 17.5
15 13.3 12.5
12 10 8.3
7.5
7 5
000 000 001 001 001
10 10 10 10 10
001 001 001 001 001 001 001 001 001 001 010 010 010
00 00 00 00 00 01 01 01 01 01 01 01 01
01 01 01 01 01 10 10 10 10 10 10 10 10
12h 12h 12h 12h 12h
000 000 000 000 000 000 001 001 001
00 00 00 00 00 01 01 01 01
01 10 10 10 10 10 10 10 10
12h 12h 12h 12h 12h
000 000 000 000 000 001 001 001
00 00 00 00 01 01 01 01
10 10 10 10 10 10 10 10
12h 12h 12h 12h
001 001
00 00
10 10
12h 12h
Rev 4.5
Rev 4.5
A
D3
D2
D1
DCLK
B
D3
D2
D1
DCLK
C
D3
D2
D1
DCLK
D
D3
D2
D1
DCLK
E
D3
D2
D1
DCLK
A2
D3
D2
D1
DCLK
B2
D3
D2
D1
DCLK
WM8235
S0
IN1[6]
IN2[3]
H
IN1[0]
IN1[7]
IN2[4]
H
IN1[1]
IN1[8]
IN2[5]
L
IN1[2]
IN1[9]
IN2[6]
L
IN1[3]
IN2[0]
IN2[7]
L
IN1[4]
IN2[1]
IN2[8]
H
IN1[5]
IN2[2]
IN2[9]
H
S0
IN3[6]
IN4[3]
H
IN3[0]
IN3[7]
IN4[4]
H
IN3[1]
IN3[8]
IN4[5]
L
IN3[2]
IN3[9]
IN4[6]
L
IN3[3]
IN4[0]
IN4[7]
L
IN3[4]
IN4[1]
IN4[8]
H
IN3[5]
IN4[2]
IN4[9]
H
S0
IN5[6]
IN6[3]
H
IN5[0]
IN5[7]
IN6[4]
H
IN5[1]
IN5[8]
IN6[5]
L
IN5[2]
IN5[9]
IN6[6]
L
IN5[3]
IN6[0]
IN6[7]
L
IN5[4]
IN6[1]
IN6[8]
H
IN5[5]
IN6[2]
IN6[9]
H
S0
IN7[6]
IN8[3]
H
IN7[0]
IN7[7]
IN8[4]
H
IN7[1]
IN7[8]
IN8[5]
L
IN7[2]
IN7[9]
IN8[6]
L
IN7[3]
IN82[0]
IN8[7]
L
IN7[4]
IN8[1]
IN8[8]
H
IN7[5]
IN8[2]
IN8[9]
H
S0
IN9[6]
IN1[3]
H
IN9[0]
IN9[7]
IN1[4]
H
IN9[1]
IN9[8]
IN1[5]
L
IN9[2]
IN9[9]
IN1[6]
L
IN9[3]
IN1[0]
IN1[7]
L
IN9[4]
IN1[1]
IN1[8]
H
IN9[5]
IN1[2]
IN1[9]
H
S0
IN2[6]
IN3[3]
H
IN2[0]
IN2[7]
IN3[4]
H
IN2[1]
IN2[8]
IN3[5]
L
IN2[2]
IN2[9]
IN3[6]
L
IN2[3]
IN3[0]
IN3[7]
L
IN2[4]
IN3[1]
IN3[8]
H
IN2[5]
IN3[2]
IN3[9]
H
S0
IN4[6]
IN5[3]
H
IN4[0]
IN4[7]
IN5[4]
H
IN4[1]
IN4[8]
IN5[5]
L
IN4[2]
IN4[9]
IN5[6]
L
IN4[3]
IN5[0]
IN5[7]
L
IN4[4]
IN5[1]
IN5[8]
H
IN4[5]
IN5[2]
IN5[9]
H
29
30
WM8235
C2
D3
D2
D1
DCLK
S0
IN6[6]
IN7[3]
H
IN6[0]
IN6[7]
IN7[4]
H
IN6[1]
IN6[8]
IN7[5]
L
D2
D3
D2
D1
DCLK
S0
IN8[6]
IN9[3]
H
IN8[0]
IN8[7]
IN9[4]
H
Table 8 10-bit 3pair LVDS Output Format
IN8[1]
IN8[8]
IN9[5]
L
IN6[2]
IN6[9]
IN7[6]
L
IN8[2]
IN8[9]
IN9[6]
L
IN6[3]
IN7[0]
IN7[7]
L
IN8[3]
IN9[0]
IN9[7]
L
IN6[4]
IN7[1]
IN7[8]
H
IN8[4]
IN9[1]
IN9[8]
H
IN6[5]
IN7[2]
IN7[9]
H
IN8[5]
IN9[2]
IN9[9]
H
LVDS 16-BIT 3PAIR MODE
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
ADC1
ADC2
ADC3
D3
D2
D1
DCLK
MCLK x3 (ADCLK)
IN1
IN4
IN7
MCLK x9 (OCLK)
A B C D E F G H I
H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H
MCLK x63 (LVCK)
IN2
IN5
IN8
IN3
IN6
IN9
A
D3
D2
D1
DCLK
S0 S1 S2 IN1[0] IN1[1]
IN1[4] IN1[5] IN1[6] IN1[7] IN1[8]
IN1[11] IN1[12] IN1[13] IN1[14] IN1[15]
H H L L L
IN1[2]
IN1[9]
S3
H
IN1[3]
IN1[10]
S4
H
B
D3
D2
D1
DCLK
S0
IN2[4]
S1
IN2[5]
S2
IN2[6]
IN2[0]
IN2[7]
IN2[1]
IN2[8]
IN2[11] IN2[12] IN2[13] IN2[14] IN2[15]
H H L L L
IN2[2]
IN2[9]
S3
H
IN2[3]
IN2[10]
S4
H
Rev 4.5
Rev 4.5
WM8235
I
D3
D2
D1
DCLK
S0
IN9[4]
S1
IN9[5]
S2
IN9[6]
IN9[0]
IN9[7]
IN9[1]
IN9[8]
IN9[11] IN9[12] IN9[13] IN9[14] IN9[15]
H H L L L
Table 9 16-bit 3pair LVDS Output Format
IN9[2]
IN9[9]
S3
H
IN9[3]
IN9[10]
S4
H
Note:
A: IN1, B:IN2, C:IN3, D:IN4, E:IN5, F:IN6, G:IN7, H:IN8, I:IN9.
LVDS 12-BIT 4PAIR MODE
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
ADC1
ADC2
ADC3
MCLK x3 (ADCLK)
IN1
IN4
IN7
IN2
IN5
IN8
IN3
IN6
IN9
IN1
IN4
IN7
IN3
IN6
IN9
MCLK x4.5 (OCLK)
D4
D3
D2
D1
DCLK
A B C D E A2 D2
H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H H H L L L H H
MCLK x31.5 (LVCK)
A
D4
D3
D2
D1
DCLK
S0
IN1[6]
S2
IN2[5]
H
IN1[0]
IN1[7]
S3
IN2[6]
H
IN1[1]
IN1[8]
IN2[0]
IN2[7]
L
IN1[2]
IN1[9]
IN2[1]
IN2[8]
L
IN1[3] IN1[4]
IN1[10] IN1[11]
IN2[2]
IN2[9]
L
IN2[3]
H
IN1[5]
S1
IN2[4]
IN2[10] IN2[11]
H
B
D4
D3
D2
D1
DCLK
S0
IN3[6]
S2
IN4[5]
H
IN3[0]
IN3[7]
S3
IN4[6]
H
IN3[1]
IN3[8]
IN4[0]
IN4[7]
L
IN3[2]
IN3[9]
IN4[1]
IN4[8]
L
IN3[3] IN3[4]
IN3[10] IN3[11]
IN4[2]
IN4[9]
L
IN4[3]
H
IN3[5]
S1
IN4[4]
IN4[10] IN4[11]
H
31
32
D
D4
D3
D2
D1
DCLK
C
D4
D3
D2
D1
DCLK
E
D4
D3
D2
D1
DCLK
A2
D4
D3
D2
D1
DCLK
B2
D4
D3
D2
D1
DCLK
C2
D4
D3
D2
D1
DCLK
WM8235
S0
IN5[6]
S2
IN6[5]
H
IN5[0]
IN5[7]
S3
IN6[6]
H
IN5[1]
IN5[8]
IN6[0]
IN6[7]
L
IN5[2]
IN5[9]
IN6[1]
IN6[8]
L
IN5[3] IN5[4]
IN5[10] IN5[11]
IN6[2]
IN6[9]
L
IN6[3]
H
IN5[5]
S1
IN6[4]
IN6[10] IN6[11]
H
S0
IN7[6]
S2
IN8[5]
H
IN7[0]
IN7[7]
S3
IN8[6]
H
IN7[1]
IN7[8]
IN8[0]
IN8[7]
L
IN7[2]
IN7[9]
IN8[1]
IN8[8]
L
IN7[3] IN7[4]
IN7[10] IN7[11]
IN8[2]
IN8[9]
L
IN8[3]
H
IN7[5]
S1
IN8[4]
IN8[10] IN8[11]
H
S0
IN9[6]
S2
IN1[5]
H
IN9[0]
IN9[7]
S3
IN1[6]
H
IN9[1]
IN9[8]
IN1[0]
IN1[7]
L
IN9[2]
IN9[9]
IN1[1]
IN1[8]
L
IN9[3] IN9[4]
IN9[10] IN9[11]
IN1[2]
IN1[9]
L
IN1[3]
H
IN9[5]
S1
IN1[4]
IN1[10] IN1[11]
H
S0
IN2[6]
S2
IN3[5]
H
IN2[0]
IN2[7]
S3
IN3[6]
H
IN2[1]
IN2[8]
IN3[0]
IN3[7]
L
IN2[2]
IN2[9]
IN3[1]
IN3[8]
L
IN2[3] IN2[4]
IN2[10] IN2[11]
IN3[2]
IN3[9]
L
IN3[3]
H
IN2[5]
S1
IN3[4]
IN3[10] IN3[11]
H
S0
IN4[6]
S2
IN5[5]
H
IN4[0]
IN4[7]
S3
IN5[6]
H
IN4[1]
IN4[8]
IN5[0]
IN5[7]
L
IN4[2]
IN4[9]
IN5[1]
IN5[8]
L
IN4[3] IN4[4]
IN4[10] IN4[11]
IN5[2]
IN5[9]
L
IN5[3]
H
IN4[5]
S1
IN5[4]
IN5[10] IN5[11]
H
S0
IN6[6]
S2
IN7[5]
H
IN6[0]
IN6[7]
S3
IN7[6]
H
IN6[1]
IN6[8]
IN7[0]
IN7[7]
L
IN6[2]
IN6[9]
IN7[1]
IN7[8]
L
IN6[3] IN6[4]
IN6[10] IN6[11]
IN7[2]
IN7[9]
L
IN7[3]
H
IN6[5]
S1
IN7[4]
IN7[10] IN7[11]
H
Rev 4.5
WM8235
D2
D4
D3
D2
D1
DCLK
S0
IN8[6]
S2
IN9[5]
H
IN8[0]
IN8[7]
S3
IN9[6]
H
Table 10 12-bit 4pair LVDS Output Format
IN8[1]
IN8[8]
IN9[0]
IN9[7]
L
IN8[2]
IN8[9]
IN9[1]
IN9[8]
L
IN8[3] IN8[4]
IN8[10] IN8[11]
IN9[2]
IN9[9]
L
IN9[3]
H
IN8[5]
S1
IN9[4]
IN9[10] IN9[11]
H
LVDS DATA OUTPUT ORDER
The WM8235 can be presented 2 types of LVDS data output order, Ascending order mode and
Descending order mode as the following.
Ascending Order Mode
10bit 5pair mode
D5 S0
D4
D3
IN1[4]
S4
S1
IN1[5]
IN2[0]
S2
IN1[6]
IN2[1]
IN1[0]
IN1[7]
IN2[2]
IN1[1]
IN1[8]
IN2[3]
IN1[2]
IN1[9]
IN2[4]
IN1[3]
S3
IN2[5]
D2
D1
DCLK
IN2[6] IN2[7] IN2[8] IN2[9] IN3[0] IN3[1] IN3[2]
IN3[3] IN3[4] IN3[5] IN3[6] IN3[7] IN3[8] IN3[9]
H H L L L H H
Decending Order Mode
10bit 5pair mode
D5 S4
D4
D3
IN1[5]
S0
S3
IN1[4]
IN2[9]
S2
IN1[3]
IN2[8]
IN1[9]
IN1[2]
IN2[7]
IN1[8]
IN1[1]
IN2[6]
IN1[7]
IN1[0]
IN2[5]
IN1[6]
S1
IN2[4]
D2
D1
DCLK
IN2[3] IN2[2] IN2[1] IN2[0] IN3[9] IN3[8] IN3[7]
IN3[6] IN3[5] IN3[4] IN3[3] IN3[2] IN3[1] IN3[0]
H H L L L H H
16bit 5pair mode
D5 S0 S1 S2 IN1[0] IN1[1] IN1[2] IN1[3]
D4 IN1[4] IN1[5] IN1[6] IN1[7] IN1[8] IN1[9] IN1[10]
D3 IN1[11] IN1[12] IN1[13] IN1[14] IN1[15] IN2[0] IN2[1]
D2
D1
DCLK
IN2[2] IN2[3] IN2[4] IN2[5] IN2[6] IN2[7] IN2[8]
IN2[9] IN2[10] IN211] IN2[12] IN2[13] IN2[14] IN2[15]
H H L L L H H
10bit 3pair mode
D3
D2
D1
DCLK
S0
IN2[3]
H
IN1[0] IN1[1] IN1[2] IN1[3] IN1[4] IN1[5]
IN1[6] IN1[7] IN1[8] IN1[9] IN2[0] IN2[1] IN2[2]
IN2[4]
H
IN2[5]
L
IN2[6]
L
IN2[7]
L
IN2[8]
H
IN2[9]
H
16bit 3pair mode
D3
D2
S0 S1 S2 IN1[0] IN1[1] IN1[2] IN1[3]
IN1[4] IN1[5] IN1[6] IN1[7] IN1[8] IN1[9] IN1[10]
D1
DCLK
IN111] IN1[12] IN1[13] IN1[14] IN1[15] S3
H H L L L H
S4
H
12bit 4pair mode
D4 S0 IN1[0] IN1[1] IN1[2] IN1[3] IN1[4] IN1[5]
D3
D2
D1
DCLK
IN1[6]
S2
IN2[5]
H
IN1[7]
S3
IN2[6]
H
IN1[8]
IN2[0]
IN2[7]
L
IN1[9] IN1[10] IN1[11]
IN2[1]
IN2[8]
L
IN2[2] IN2[3]
S1
IN2[4]
IN2[9] IN2[10] IN211]
L H H
16bit 5pair mode
D5 S2 S1 S0 IN1[15] IN1[14] IN1[13] IN1[12]
D4 IN1[11] IN1[10] IN1[9] IN1[8] IN1[7] IN1[6] IN1[5]
D3 IN1[4] IN1[3] IN1[2] IN1[1] IN1[0] IN2[15] IN2[14]
D2 IN2[13] IN2[12] IN2[11] IN2[10] IN2[9] IN2[8] IN2[7]
D1 IN2[6] IN2[5] IN2[4] IN2[3] IN2[2] IN2[1] IN2[0]
DCLK H H L L L H H
10bit 3pair mode
D3
D2
D1
DCLK
S0
IN2[6]
H
IN1[9] IN1[8] IN1[7] IN1[6] IN1[5] IN1[4]
IN1[3] IN1[2] IN1[1] IN1[0] IN2[9] IN2[8] IN2[7]
IN2[5]
H
IN2[4]
L
IN2[3]
L
IN2[2]
L
IN2[1]
H
IN2[0]
H
16bit 3pair mode
D3 S4 S3 S2 IN1[15] IN1[14] IN1[13] IN1[12]
D2 IN1[11] IN1[10] IN1[9] IN1[8] IN1[7] IN1[6] IN1[5]
D1
DCLK
IN1[4] IN1[3] IN1[2] IN1[1] IN1[0]
H H L L L
S1
H
S0
H
12bit 4pair mode
D4 S3 IN1[11] IN1[10] IN1[9] IN1[8] IN1[7] IN1[6]
D3
D2
D1
DCLK
IN1[5]
S1
IN2[6]
H
IN1[4]
S0
IN2[5]
H
IN1[3]
L
IN1[2]
L
IN1[1]
IN2[11] IN2[10] IN2[9]
IN2[4] IN2[3] IN2[2]
L
IN1[0]
IN2[8]
IN2[1]
H
S2
IN2[7]
IN2[0]
H
Rev 4.5
33
WM8235
REGISTER
ADDRESS
R7 (07h) output
control
BIT
3
LABEL DEFAULT DESCRIPTION
LVDSORDER 0 control LVDS data output order
0 = descending order
1 = ascending order
LVDS SYNCHRONOUS OUTPUT
The LVDS synchronous output function can be used in LVDS 16-bit 5pair mode, 10-bit 3pair mode and 12-bit 4 pair mode. In these LVDS output mode, the output data packet cycle is not same as
MCLK clock period, so that the output data at pixel counter = 0 will not be same format when the line length is odd number.
If OUTSYNC = 1, the LVDS output format will be synchronized to pixel counter = 0.
When the line length is even number, the output data at pixel counter = 0 will be always same format, so that the OUTSYNC is invalid. Also, the OUTSYNC is invalid in other LVDS and CMOS format. The following shows detailed information of this mode.
Odd number line length
In odd number line length operation, the output data at pixel counter = 0 will not be same format as
Odd number line length, OUTSYNC = 0
Line 0
Pix counter
0 1 2
LVDS data output
A B C D E
A
2
B
2
C
2
D
2
A B C D E
Line 1
1
Line 2
Last pixel 0 2 Last pixel 0 1
D
2
A B C D E
A
2
B
2
C
2
D
2
A B C D E
A
2
B
2
C
2
D
2
A E
A
2
B
2
C
2
D
2
A B C D E
A
2
B
2
C
2
D
2
Figure 17 LVDS output data cycle (odd number line length, OUTSYNC=0)
Odd number line length, OUTSYNC = 1
Line 0
Pix counter
0 1 2 Last pixel 0
Line 1
1 2 Last pixel 0
Line 2
1
LVDS data output
A B C D E
A
2
B
2
C
2
D
2
A B C D E
D
2
A B C D E A B C D E
A
2
B
2
C
2
D
2
A B C D E
D
2
A B C D A B C D E
A
2
B
2
C
2
D
2
Figure 18 LVDS output data cycle (odd number line length, OUTSYNC=1)
Even number line length
When the line length is even number, the output data at pixel counter = 0 will be always same format, so that the OUTSYNC is invalid.
Even number line length (OUTSYNC is invalid)
Line 0
Pix counter
0 1 2
LVDS data output
A B C D E
A
2
B
2
C
2
D
2
A B C D E
Line 1
1 Last pixel 0 2
E
A
2
B
2
C
2
D
2
A B C D E
A
2
B
2
C
2
D
2
A B C D E
Line 2
Last pixel 0 1
E
A
2
B
2
C
2
D
2
A B C D E
A
2
B
2
C
2
D
2
Figure 19 LVDS output data cycle (even number line length)
34 Rev 4.5
WM8235
CMOS OUTPUT MODE
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
ADC1
ADC2
ADC3
MCLK x3 (ADCLK)
IN1
IN4
IN7
MCLK x9 (OCLK)
OP9
OP8
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
MCLK x9 (OC1)
A
OP9
OP8
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
IN1[9]
IN1[8]
IN1[7]
IN1[6]
IN1[5]
IN1[4]
IN1[3]
IN1[2]
IN1[1]
IN1[0]
IN2[9]
IN2[8]
IN2[7]
IN2[6]
IN2[5]
IN2[4]
IN2[3]
IN2[2]
IN2[1]
IN2[0]
Table 11 10-bit CMOS Output Format
IN3[9]
IN3[8]
IN3[7]
IN3[6]
IN3[5]
IN3[4]
IN3[3]
IN3[2]
IN3[1]
IN3[0]
IN4[9]
IN4[8]
IN4[7]
IN4[6]
IN4[5]
IN4[4]
IN4[3]
IN4[2]
IN4[1]
IN4[0]
IN5[9]
IN5[8]
IN5[7]
IN5[6]
IN5[5]
IN5[4]
IN5[3]
IN5[2]
IN5[1]
IN5[0]
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN2
IN5
IN8
A
IN6[9]
IN6[8]
IN6[7]
IN6[6]
IN6[5]
IN6[4]
IN6[3]
IN6[2]
IN6[1]
IN6[0]
IN7[9]
IN7[8]
IN7[7]
IN7[6]
IN7[5]
IN7[4]
IN7[3]
IN7[2]
IN7[1]
IN7[0]
IN3
IN6
IN9
IN8[9]
IN8[8]
IN8[7]
IN8[6]
IN8[5]
IN8[4]
IN8[3]
IN8[2]
IN8[1]
IN8[0]
IN9[9]
IN9[8]
IN9[7]
IN9[6]
IN9[5]
IN9[4]
IN9[3]
IN9[2]
IN9[1]
IN9[0]
CLOCK TIMING CONFIGURATION
The RSMP signal, VSMP signal and clock output from CLK pin are generated internally by 60 tap
DLL circuit. The rising and falling timing of each clock is set by DLL tap setting. The following setting and timing chart shows example configuration for RSMP, VSMP and CLK1.
RSMP: 0x82(RSMP_RISE)=0x07(dec7), 0x83(RSMP_FALL)=0x10(dec16)
VSMP: 0x84(VSMP_RISE)=0x1C(dec28), 0x85(VSMP_FALL=0x29(dec41)
CLK1: 0x87(CLK1_RISE)=0x39(dec57), 0x88(CLK1_FALL)=0x0B(dec11)
Rev 4.5
35
MCLK (input) tMCLKD
Tap 0 tPER/60
7 16 tPER
RSMP
28
VSMP
57 11
CLK1
DLL TAP
59 0 1 2 30
Figure 20 Example of Clock Timing configuration
REGISTER
ADDRESS
R130 (82h) RSMP rise
R131 (83h) RSMP fall
R132 (84h)
VSMP rise
R133 (85h)
VSMP fall
R134 (86h)
TGCKO rise
R135 (87h)
CLK1 rise
R136 (88h)
CLK1 fall
R137 (89h)
CLK2 rise
R138 (8Ah)
CLK2fall
R139 (8Bh)
CLK3 rise
R140 (8Ch)
CLK3 fall
R141 (8Dh)
CLK4 rise
R142 (8Eh)
CK4 fall
R143 (8Fh)
CLK5 rise
R144 (90h)
CLK5 fall
R145 (91h)
CLK6 rise
R146 (92h)
CLK6 fall
BIT
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
LABEL
RSMP_RISE
[5:0]
RSMP_FALL
[5:0]
VSMP_RISE
[5:0]
VSMP_FALL
[5:0]
TCLKO_RISE
[5:0]
CLK1_RISE[5:0]
CLK1_FALL[5:0]
CLK2_RISE[5:0]
CLK2_FALL[5:0]
CLK3_RISE[5:0]
CLK3_FALL[5:0]
CLK4_RISE[5:0]
CK4_FALL[5:0]
CLK5_RISE[5:0]
CLK5_FALL[5:0]
CLK6_RISE[5:0]
CLK6_FALL[5:0]
DEFAULT
01_1100
RSMP rise edge
10_0110 RSMP fall edge
00_0000 VSMP rise edge
00_1000 VSMP fall edge
11_0111 TCLKO rise edge
00_1010 CLK1 rise edge
01_1001 CLK1 fall edge
01_1001 CLK2 rise edge
10_1000
CLK2 fall edge
10_1000 CLK3 rise edge
00_1010 CLK3 fall edge
00_0000
CLK4 rise edge
00_0000 CK4 fall edge
00_1010 CLK5 rise edge
10_1000 CLK5 fall edge
00_1010 CLK6 rise edge
10_1000
CLK6 fall edge
41
DESCRIPTION
WM8235
Tap 0
57
59 0 1
36 Rev 4.5
WM8235
SENSOR TIMING GENERATION
WM8235 provide two types of clock internally. C_CK* are high speed clocks, these clocks can set the clock phase by using fine pitch phase control. P_CK* are pixel rate signals which is selected by PO0 to PO7. WM8235 has eleven TG outputs pins. CLK1 is for clock type use only. CLK2, CLK3, CLK4,
CLK5 and CLK6 are selectable high speed type signal or pulse type signal. CLK7 and CLK8 are pulse type use only.
PO0
PO1
PO2
PO3
PO4
PO5
PO6
PO7
C_CK1
C_CK2
C_CK3
C_CK4
C_CK5
C_CK6
P_CK2
P_CK3
P_CK4
P_CK5
P_CK6
P_CK7
P_CK8 delay delay delay delay delay delay delay
OE
CLK1
OE
CLK2
OE
CLK3
OE
CLK4
OE
CLK5
OE
CLK6
OE
CLK7
OE
CLK8
MCLK (input)
VSMP (Internal)
TGCK (Internal)
Pixel Counter
(Internal)
CK1,2,3,4,5,6
(Clock Output)
TGCO (Internal)
CK2,3,4,5,6,7,8
(Pulse output) tMCLKD
VSMP_RISE[5:0]
VSMP_FALL[5:0] tPER
Duty=50%
2*tPER/60
CK_RISE[5:0]
CK_FALL[5:0]
TCLKO_RISE[5:0]
Duty=50%
DEL_PCK [1:0]
Figure 21 TG Output Timing
Rev 4.5
37
WM8235
REGISTER
ADDRESS
R176 (B0h)
– R177 (B1h)
R135 (81h)
– R146 (92h)
BIT LABEL DEFAULT DESCRIPTION
master
TGEN(Serial I/F)
VSMP
TGCK
Pixel counter
VSMP
TGCK
2*tPER/60
L=LLENGTH[14:0]
TGSYNC(Output) pixcnt=0 pixcnt=0 pixcnt=0
TPn=P1 TPm=P2
POn(Internal)
CLKn(TG pulse out)
PO_ Flag
(LVDS/CMOS out) tPCKD tTRIGD
FLAGPIX=P1
Datatrig(Internal)
Datatrig
(LVDS/CMOS output) tTRIGD
Figure 22 Master Mode Pixel Counter and Line Start Timing
TG SLAVE MODE OPERATION
In slave mode, line length depends on TGSYNC input. The pixel counter is reset by TGSYNC input. slave
5:0
5:0
5:0
DEL_PCK*[1:0] 00
CLK*_RISE[5:0]
CLK*_FALL[5:0]
TG MASTER MODE OPERATION
control delay for pulse output
00 = 0nsec, 01 = 1nsec, 10 = 2nsec, 11 = 3nsec
CLK* rise edge (0 to 59)
CLK* fall edge (0 to 59)
In master mode, line length is defined by LLENGTH register.
VSMP
TGCK
2*tPER/60
TGSYNC t
SYH tSCKSY
TGEN(Serial I/F)
VSMP
TGCK
TGSYNC(Input)
Linestart(Internal)
Pixel counter tSYH tCOUNTD pixcnt=0
Q=OFFSET[3:0]
0 tSYL
TPn=P1 TPm=P2 pixcnt=0
32767 pixcnt=0
POn(Internal)
CLKn(TG pulse out)
PO_Flag
(LVDS/CMOS out) tPCKD tTRIGD
FLAGPIX=P1
Flag(Internal)
Flag
(LVDS/CMOS out) tTRIGD
Figure 23 Slave Mode Pixel Counter and Line Start Timing
38 Rev 4.5
WM8235
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, T
A
= 25
C, unless otherwise stated.
PARAMETER
TGSYNC Setup time
(only for slave mode)
Pixel counter start timing
(only for slave mode)
TGSYNC high period
(only for slave mode)
TGSYNC low period
(only for slave mode)
Data trigger timing delay
SYMBOL
t t
COUNTD t
SCKSY t t
SYH
SYL
TRIGD
TEST CONDITIONS MIN
t
PER
/ 4
1
1 t
TYP
PER
/ 2
2
MAX
3 * t
PER
/ 4 t
PCKD
LVDS 10-bit 5pair mode
Other output mode
11
10
2 TG pulse output timing delay
Note:
1clock = t
PER
(MCLK cycle period)
REGISTER
ADDRESS
R160 (A0h)
BIT
7:4
2
LABEL DEFAULT DESCRIPTION
R161 (A1h)
R162 (A2h)
1
0
7:0
6:0
OFFSET[3:0]
POLSYNC
TGMD
TG_EN
LLENGTH[7:0]
LLENGTH[6:0]
0000
0
0
0 offset count (only for slave mode) polarity of Sync signal
0 = positive edge, 1 = negative edge
TG operation mode
0 = slave, 1 = master
TG enable
0 = disable, 1 = enable
0000_0000 the number of pixels in 1line (only for master mode)
000_0000 the number of pixels in 1line (only for master mode)
TG PULSE AND TRIGGER DATA
UNITS
ns clock clock clock clock clock clock
C_CK1
C_CK2
VSMP
TGCK pixcnt
P_CK1
(Selected from P0-P7)
P_CK2
(Selected from P0-P7)
P_CK3
(Selected from P0-P7)
DataTrig
(FLUGPIX is selected )
Datatrig_out
(FLUGPIX is selected )
DataTrig
(PO* is Selectd )
DataTrig_out
(PO* is Selectd )
TP1
TP1
TP2 TP3
TP2
TP3
FLUGPIX t
TRIGD
Figure 24 TG Pulse Toggle Setting and Data Trigger Timing
t
TRIGD
TP3
TP3
TP4 TP5
TP4
TP5
TP4
TRIGD
TP6
TP6
Rev 4.5
39
40
WM8235
TG PULSE
WM8235 can be generated 8 TG pulse internally (PO0
– PO7). These pulses are generated by toggle point setting register (TP*) and polarity setting register (POL*_PO*). WM8235 provided up to 32 toggle point by using TP0 to TP31. PO0-PO7 signals can be assigned to CLK2-CLK8 by SEL_PCK* and SEL_CLK* register.
TRIGGER DATA
WM8235 can implement trigger data in LVDS flag data (S0, S1, S2, S3 and S4). This can be selected from two methods. One is FLAGPIX register, this can be set one pixel by each line. The
other is to apply PO* pulse. Figure 24 shows the trigger data implementation timing.
CHANNEL ID
Also WM8235 can implement channel identification data instead of trigger data. Table 12 shows the
matrix of input channel and channel ID.
IN4
IN5
IN6
IN7
IN1
IN2
IN3
IN8
IN9
Table 12 Channel ID
0
0
0
0
ID[3]
0
0
0
1
1
ID[2]
0
0
0
1
1
1
1
0
0
ID[1]
0
1
1
0
0
1
1
0
0
ID[0]
1
0
1
0
1
0
1
0
1
Channel ID can be assigned to flag data (S0, S1, S2, S3 or S4). The following is the example of channel ID assignment.
Example: Assigned channel ID to flag data as ID[3]=S0, ID[2] =S1, ID[1]=S2, ID[0]=S3.
If output data is as follows, channel ID will be IN1. (i.e. ID[3]=S0=0, ID[2]=S1=0, ID[1]=S2=0,
ID[0]=S3=1)
A
D5
D4
D3
D2
D1
DCLK
S0
IN1[4]
S4
S1
IN1[5]
IN2[0]
S2
IN1[6]
IN2[1]
IN1[0]
IN1[7]
IN2[2]
IN1[1]
IN1[8]
IN2[3]
IN1[2]
IN1[9]
IN2[4]
IN1[3]
S3
IN2[5]
IN2[6] IN2[7] IN2[8] IN2[9] IN3[0] IN3[1] IN3[2]
IN3[3] IN3[4] IN3[5] IN3[6] IN3[7] IN3[8] IN3[9]
H H L L L H H
Rev 4.5
WM8235
Channel ID Setting Limitation
There are some notices to assign channel ID. It’s depending on LVDS output format. (refer to
OUTPUT DATA FORMAT)
1) 10-bit 5pair mode LVDS output
In this mode, channel ID will be IN1, IN4 or IN7 only.
Case-1 ID indicate IN1
A
D5
D4
D3
D2
D1
DCLK
S0 S1 S2 IN1[0] IN1[1] IN1[2] IN1[3]
IN1[4] IN1[5] IN1[6] IN1[7] IN1[8] IN1[9] S3
S4 IN2[0] IN2[1] IN2[2] IN2[3] IN2[4] IN2[5]
IN2[6] IN2[7] IN2[8] IN2[9] IN3[0] IN3[1] IN3[2]
IN3[3] IN3[4] IN3[5] IN3[6] IN3[7] IN3[8] IN3[9]
H H L L L H H
Case-2 ID indicate IN4
B
D5
D4
D3
D2
D1
DCLK
S0
IN4[4]
S4
IN5[6]
IN6[3]
H
Case-3 ID indicate IN7
C
D5
D4
D3
D2
D1
DCLK
S0
IN7[4]
S4
IN8[6]
IN9[3]
H
S1
IN4[5]
IN5[0]
IN5[7]
IN6[4]
H
S1
IN7[5]
IN8[0]
IN8[7]
IN9[4]
H
S2
IN4[6]
IN5[1]
IN5[8]
IN6[5]
L
S2
IN7[6]
IN8[1]
IN8[8]
IN9[5]
L
IN4[0]
IN4[7]
IN5[2]
IN5[9]
IN6[6]
L
IN7[0]
IN7[7]
IN8[2]
IN8[9]
IN9[6]
L
IN4[1]
IN4[8]
IN5[3]
IN6[0]
IN6[7]
L
IN7[1]
IN7[8]
IN8[3]
IN9[0]
IN9[7]
L
IN4[2]
IN4[9]
IN5[4]
IN6[1]
IN6[8]
H
IN7[2]
IN7[9]
IN8[4]
IN9[1]
IN9[8]
H
IN7[3]
S3
IN8[5]
IN9[2]
IN9[9]
H
IN4[3]
S3
IN5[5]
IN6[2]
IN6[9]
H
Rev 4.5
41
REGISTER
ADDRESS
R171 (ABh)
- R175 (AFh)
R208 (D0h)
- R270 (10Eh)
R271 (10Fh)
- R310 (136h)
R163 (A3h)
R164 (A4h)
R180 (B4h)
42
R10 (0Ah)
R11 (0Bh)
WM8235
6:0
7:0
6:0
3:0
BIT
2) 16-bit 5pair mode LVDS output
This mode has only three data flags as S0, S1 and S2. Therefore it cannot assign all channel ID to data flags.
A
D5
D4
D3
D2
D1
DCLK
S0
IN1[4]
S1
IN1[5]
S2
IN1[6]
IN1[0]
IN1[7]
IN1[1]
IN1[8]
IN1[2]
IN1[9]
IN1[3]
IN1[10]
IN1[11] IN1[12] IN1[13] IN1[14] IN1[15] IN2[0]
IN2[2] IN2[3] IN2[4] IN2[5] IN2[6] IN2[7]
IN2[1]
IN2[8]
IN2[9] IN2[10] IN2[11] IN2[12] IN2[13] IN2[14] IN2[15]
H H L L L H H
LABEL DEFAULT DESCRIPTION
7
SEL_PCK*
SEL_CLK*
EN_TP*
000
0
0 pulse mapping control for CLK*
000 = PO1, 001 = PO2, 010 = PO3, 011 = PO4
100 = PO5, 101 = PO6, 110 = PO7, 111 = PO8 mapping control
0 = output clock, 1 = output pulse enable toggle point
0 = disable and subsequent toggle point
1 = enable toggle point pixel count of toggle point polarity of PO* pulse at TP*
TP*
POL*_PO*
FLAGPIX[7:0]
FLAGPIX[6:0]
SEL_FLAG[3:0]
7:4
3:0
7:4
FLAG_S1[3:0]
FLAG_S0[3:0]
FLAG_S3[3:0]
0000_0000 flag pixel
000_0000 flag pixel
0000 select signal to be output as datatrig
0xxx = flagpix, 1000 = PO0, 1001 = PO1, 1010 = PO2,
1011 = PO3, 1100 = PO4, 1101 = PO5, 1110 = PO6
1111 = PO7
0001 output dataflag as S1
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = channel ID[3]
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high
0000
0001 output dataflag as S0
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = channel ID[3]
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high output dataflag as S3
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
Rev 4.5
WM8235
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
R12 (0Ch)
3:0
3:0
CKGO3
(Internal)
VSMP
TGCK pixcnt
TGCKO
CKGO3 + M2
C_CK3
N-1 N N+1 N+2 [email protected] N
Figure 25 TG Mask Timing
FLAG_S2[3:0]
FLAG_S4[3:0]
0000
0000
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = channel ID[3]
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high output dataflag as S2
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = channel ID[3]
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high output dataflag as S4
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = channel ID[3]
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high
TG MASK TIMING
The WM8235 has TG clock mask function. M1, M2 and M3 pulse specifies the mask period; T1 and
T2 pulses are used for changing the signal polarity during the mask period. C_CK1 and C_CK2 are applied to the M pulse only; they cannot be applied to the T pulse. C_CK3 and C_CK4 are applied to
M1 and T1; C_CK5 and C_CK6 are applied to M2 and T2. The mask timing is synchronized with
TGCKO rise edge.
N+3 P1 TP1
TP1
P2 TP2 M-2
TP2
M-1 M M+1
M-1 [email protected] M-1
M+2 M+3 k
TG CLOCK
C_CK1
C_CK2
C_CK3
C_CK4
C_CK5
C_CK6
APPLIED
“M” PULSE
M3
M1
M2
APPLIED
“T” PULSE
none
T1
T2
Rev 4.5
43
WM8235
REGISTER
ADDRESS
R195 (C3h)
R196 (C4h)
R197 (C5h)
R198 (C6h)
R199 (C7h)
R200 (C8h)
R201 (C9h)
R202 (CAh)
R203 (CBh)
R204 (CCh)
R205 (CDh)
R206 (CEh)
R271 (010Fh)
– R278 (116h)
BIT
Cycmd [Serial I/F]
TGSYNC pixel counter cyccnt
Generated pulse0
Generated pulse1
Generated pulse2
Generated pulse3 cycen_p0 cycen_p1 cycen_p2 cycen_p3
PO0
PO1
PO2
PO3
000
High
High
High
High
Figure 26 TG Cycle Mode
LABEL
15'h7FFF
001 010
DEFAULT
100 001
01
0
100
DESCRIPTION
7:0
6:0
7:0
6:0
7:0
6:0
7:0
6:0
7:0
6:0
7:0
6:0
7:0
7:0
M1_RISE[7:0]
M1_RISE[6:0]
M1_FALL[7:0]
M1_FALL[6:0]
M2_RISE[7:0]
M2_RISE[6:0]
M2_FALL[7:0]
M2_FALL[6:0]
M3_RISE[7:0]
M3_RISE[6:0]
M3_FALL[7:0]
M3_FALL[6:0]
POL*_T1
POL*_T2
TG CYCLE MODE
0000_0000
000_0000
0000_0000
000_0000
0000_0000
000_0000
0000_0000
000_0000
0000_0000
000_0000
0000_0000
000_0000
1111_1111
1111_1111
M1 pulse rise count (mask start)
M1 pulse rise count (mask start)
M1 pulse fall count (mask end)
M1 pulse fall count (mask end)
M2 pulse rise count (mask start)
M2 pulse rise count (mask start)
M2 pulse fall count (mask end)
M2 pulse fall count (mask end)
M3 pulse rise count (mask start)
M3 pulse rise count (mask start)
M3 pulse fall count (mask end)
M3 pulse fall count (mask end) polarity of T1 pulse at TP* polarity of T2 pulse at TP*
TG cycle mode can be set the different TG pulse line by line. This mode is for slave mode only.
No SH
No pulse generation
No SH
No pulse generation
001 010 cycpat_p0[0] cycpat_p1[0] cycpat_p2[0] cycpat_p3[0] cycpat_p0[1] cycpat_p1[1] cycpat_p2[1] cycpat_p3[1] cycpat_p0[2] cycpat_p1[2] cycpat_p2[2] cycpat_p3[2] cycpat_p0[0] cycpat_p1[0] cycpat_p2[0] cycpat_p3[0] cycpat_p0[1] cycpat_p1[1] cycpat_p2[1] cycpat_p3[1] cycpat_p0[2] cycpat_p1[2] cycpat_p2[2] cycpat_p3[2] cycpat_p0[0] cycpat_p1[0] cycpat_p2[0] cycpat_p3[0] cycpat_p0[1] cycpat_p1[1] cycpat_p2[1] cycpat_p3[1]
000
High
High
High
High
REGISTER
ADDRESS
R160 (A0h)
BIT
3
LABEL
CYCMD
DEFAULT
0
DESCRIPTION
R181 (B5h)
– R184 (B8h)
CYCPAT_PO*[2:0] 000 cycle mode enable
0 = normal (same operation at every line)
1 = cycle mode
PO* cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
44 Rev 4.5
WM8235
PROGRAMMABLE AUTOMATIC BLACK LEVEL CALIBRATION (BLC)
The Programmable Automatic Black-Level Calibration (BLC) function is to adjust the D.C. offset of the output data such that the digital output code for black pixels is calibrated to a target black level value. The D.C. offset is determined during the optically-black pixels at the beginning of the linear
sensor and removed during the image-pixels as shown in Figure 27.
Black Pixel Period Image Pixel Period
Rev 4.5
Determine Black
Level Offset
Remove Black Level Offset from Image Pixels
Figure 27 Linear Sensor Model
The automatic black level calibration operates assuming 12-bits ADC resolution. Adjustments to calculations must be made for different ADC resolutions.
The black level calibration process occurs in two stages as shown in Figure 28 below:
Coarse Adjust Calibration - This is a mixed signal loop which removes the coarse offset by adjusting the offset DAC.
Fine Adjust Calibration - This is a digital loop which removes the remaining offset with better noise tolerance, utilising ADC over-range to improve the dynamic range of the system.
Adjusted
ADC Output
Input Black Level V1
Offset
DAC
PGA
Coarse Adjust
Calibration
Mixed
Signal
LOOP
Digits
ADC
Fine Adjust
Calibration
Digital
LOOP
Digits
TARGET BL
Figure 28 BLC Top-Level Circuitry
TARGET CODES
The user must specify a target black level for each channel through the registers TARGETINP*. If, during the black-pixel period, the average ADC output code was, for example, 100 and the user specified the target black level code to be 10, the BLC circuitry would determine 90 codes should be subtracted from the ADC output. These 90 codes will then be subtracted from every image-pixel code output from the ADC.
Note: Changing the PGA gain affects the black-level through the device; the gain should therefore not be changed during a BLC procedure. If the PGA gain changes, then the BLC routine should be re-run.
The automatic black level calibration feature operates with the assumption of a 12-bit ADC resolution.
The register settings for Target Codes (TARGETINP*) should be set differently depending on the
45
WM8235
ADC resolution being used. As TARGETINP* is an 8 bit register, the 4 MSBs of a data output code cannot be changed.
16-bit ADC Resolution
For 16-bit resolution the target code entered into TARGETINP* will ignore the 4 MSBs and 4 LSBs of the 16-bit data output. For example if the desired code out is 0000111111110001, the value entered into TARGETINP* would be 11111111.
10-bit ADC Resolution
For 10-bit resolution the 4 MSBs of the 10bit data output code will be ignored. The 2 LSBs of the target code should be set to ‘00’. For example if the desired code out is 0000111111, the value entered into TARGETINP* would be 11111100.
BLC SCENARIOS OF OPERATION
The BLC can be used in various ways to suit the application, for example calibration can be done once per page or once per line. Three potential scenarios of operation are suggested below.
Note: The registers FRAME_START and SEQ_START when set high by the user will automatically be set low by the device.
SCENARIO 1
In this scenario, Coarse Adjust Calibration is enabled for the 1 st
line; Fine Adjust Calibration is enabled for every line, with the Fine Adjust Calibration result recalculated every line. This scenario is suitable for dealing with large amounts of D.C. drift throughout a frame; but this is at a cost of potential line-by-line variation in the Fine Adjust result (dependent on sensor noise and the PGA
gain). Table 13 shows which registers are required for this scenario with example settings.
SETUP
REGISTER
BPIX_AVAIL CADUR
Value
50 2
Table 13 Example Register Settings for Scenario 1
FRAME_START
1
FA_EVERYLINE
1
Black Pixels Image Pixels
Auto Fine Adjust clear
Fine Adjust cleared
Fine Adjust cleared
Fine Adjust cleared
Fine Adjust cleared
Fine Adjust cleared
Fine Adjust cleared
Fine Adjust cleared
Fine Adjust cleared
Fine Adjust cleared
Fine Adjust cleared
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
- - -
- - -
- - -
Line n
Figure 29 Scenario 1
46 Rev 4.5
WM8235
SCENARIO 2
In this scenario, Coarse Adjust and Fine Adjust Calibration is enabled for the 1 st
line, with the Fine
Adjust result updated on the 1 st
line only. This scenario is suitable for adjusting for black-level D.C. drift on a frame-by-frame basis; there will be no line-by-line variation in the black-level from the BLC
circuitry. Table 14 shows which registers are required for this scenario with example settings.
SETUP
REGISTER
BPIX_AVAIL CADUR
Value
50 2
Table 14 Example Register Settings for Scenario 2
FRAME_START
1
Black Pixels Image Pixels
Auto Fine Adjust clear Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
- - -
- - -
- - -
Line n
Figure 30 Scenario 2
Rev 4.5
47
WM8235
SCENARIO 3
In this scenario, Coarse Adjust Calibration is enabled for the 1 st
line; Fine Adjust Calibration is enabled for every line, with the Fine Adjust result accumulated throughout frame and used every line.
This scenario allows any variation in the black-level to be tracked throughout the frame by accumulating the Fine Adjust result over multiple lines. This method does not deal with as large amounts of D.C. drift throughout the frame as scenario 1, but it will produce less line-by-line variation.
Table 15 shows which registers are required for this scenario with example settings.
SETUP
REGISTER
BPIX_AVAIL CADUR FRAME_START
Value
50 2 1
Table 15 Example Register Settings for Scenario 3
FA_EVERYLINE
1
FA_ACCUM
1
Black Pixels Image Pixels
Auto Fine Adjust clear
Fine Adjust not cleared
Fine Adjust not cleared
Fine Adjust not cleared
Fine Adjust not cleared
Fine Adjust not cleared
Fine Adjust not cleared
Fine Adjust not cleared
Fine Adjust not cleared
Fine Adjust not cleared
Fine Adjust not cleared
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Use Fine Adjust Result here
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
- - -
- - -
- - -
Line n
Figure 31 Scenario 3
48 Rev 4.5
WM8235
AUTOMATIC GAIN CONTROL (AGC)
The Automatic Gain Control (AGC) function is to adjust the gain to an appropriate level for a range of input signal levels. The AGC function is enabled by AGC_EN register set to 1. The gain control
process has three stages as shown in Figure 32 below:
SPI SPI
First rising edge of
PEAK_DET after
AGE_EN=0
AGC_EN
Status of AGC
Disable
PEAK_DET
(internal)
PEAK
(read only)
AGAIN
DGAIN
FLAG_AGC
(read only)
Disable
AGAIN
1line
0
Peak detection for analogue gain
N line = AGC_APD[2:0]
Peak detection for digital gain
Gain caluculation
M line = AGC_DPD[2:0]
Peak
(1)
Peak
(2)
Peak
(N)
Cleared peak value
Peak
(1)
Peak
(2)
Peak
(M)
Again(N)
DGAIN DGAIN(x1)
Applied calibrated gain
Dgain(M)
0
AGAIN
DGAIN
Figure 32 Automatic Gain Control
Analogue Gain Calibration
The analogue gain keep the previous setting (AGAIN) and the digital gain set to x1
(DGAIN=12’d2048) automatically. During the PEAK_DET=high period, peak detection is executed then calculate an appropriate analogue gain (Again(N)) while PEAK_DET=low period. This period needs 200 pixels at least. The number of peak detection cycle is selectable by AGC_APD register.
Minimum cycle is 0 (In this case the analogue gain calibration is not executed), Maximum cycle is 7 lines. The peak value is cleared when analogue peak detection finished.
Digital Gain Calibration
The analogue gain is set to the calibrated value (Again(N)), and the digital gain is set to x1
(DGAIN=12’d2048) automatically. Then peak detection and digital gain calibration are executed. Also, the number of peak detection line is selectable by AGC_DPD register. Minimum cycle is 0 (In this case the digital gain calibration is not executed), Maximum cycle is 7 lines.
Applied Calibrated Analogue and Digital Gain
The analogue and digital gain are holding calibrated value until AGC_EN register set to 0.
Again(N) = AGC_TARGETINP* / peak(n) x AGAIN
Dgain(M) = (AGC_TARGETINP*
– TARGETINP*) / (peak(M) – TARGETINP*)
Rev 4.5
49
REGISTER
ADDRESS
R72 (48h)
R73 (49h)
R74 (4Ah)
R75 (4Bh)
R76 (4Ch)
R77 (4Dh)
R78 (4Eh)
R79 (4Fh)
R80 (50h)
R87 (57h)
R88 (58h)
R96 (60h)
R97 (61h)
R98 (62h)
R99 (63h)
R100 (64h)
R101 (65h)
R102 (66h)
R103 (67h)
R89 (59h)
R90 (5Ah)
R91 (5Bh)
R92 (5Ch)
R93 (5Dh)
R94 (5Eh)
R95 (5Fh)
WM8235
2
1
0
6:4
2:0
7:0
1:0
7:0
1:0
7:0
1:0
7:0
7:0
1:0
7:0
1:0
7:0
1:0
1:0
7:0
BIT
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:4
LABEL DEFAULT DESCRIPTION
TARGETIN1[7:0]
TARGETIN2[7:0]
TARGETIN3[7:0]
TARGETIN4[7:0]
TARGETIN5[7:0]
TARGETIN6[7:0]
TARGETIN7[7:0]
TARGETIN8[7:0]
TARGETIN9[7:0]
AGCAVE[3:0]
AGC_ERRFLAG
AGC_ENDFLAG
AGC_EN
AGC_DPD[2:0]
AGC_APD[2:0]
AGC_TARGETIN1
[7:0]
AGC_TARGETIN1
[9:8]
AGC_TARGETIN2
[7:0]
AGC_TARGETIN2
[9:8]
AGC_TARGETIN3
[7:0]
AGC_TARGETIN3
[9:8]
AGC_TARGETIN4
[7:0]
AGC_TARGETIN4
[9:8]
AGC_TARGETIN5
[7:0]
AGC_TARGETIN5
[9:8]
AGC_TARGETIN6
[7:0]
AGC_TARGETIN6
[9:8]
AGC_TARGETIN4
[7:0]
AGC_TARGETIN4
[9:8]
AGC_TARGETIN5
[7:0]
0000_0000 target black level for IN1[7:0]
0000_0000 target black level for IN2[7:0]
0000_0000 target black level for IN3[7:0]
0000_0000 target black level for IN4[7:0]
0000_0000 target black level for IN5[7:0]
0000_0000 target black level for IN6[7:0]
0000_0000 target black level for IN7[7:0]
0000_0000 target black level for IN8[7:0]
0000_0000 target black level for IN9[7:0]
0000 averaging factor before peak detection
0000 = no average, 0001 = 2, 0010 = 4, 0011 = 8
…, 1010
= 1024 (1011 = 1100 = 1101 = 1110 = 1111 = reserved)
0
0
0
AGC error flag
0 = no error detected, 1 = AGC finish with error
AGC end flag
0 = not end or not run, 1 = AGC sequence was done
AGC enable
0 = disable, 1 = enable
000
000
0000_0000 the number of peak detection iterations to calculate digital gain the number of peak detection iterations to calculate analogue gain
LSB of AGC target level for IN1
00
0000_0000
00
0000_0000
00
0000_0000
00
0000_0000
00
0000_0000
00
0000_0000
00
0000_0000
MSB of AGC target level for IN1
LSB of AGC target level for IN2
MSB of AGC target level for IN2
LSB of AGC target level for IN3
MSB of AGC target level for IN3
LSB of AGC target level for IN4
MSB of AGC target level for IN4
LSB of AGC target level for IN5
MSB of AGC target level for IN5
LSB of AGC target level for IN6
MSB of AGC target level for IN6
LSB of AGC target level for IN4
MSB of AGC target level for IN4
LSB of AGC target level for IN5
50 Rev 4.5
WM8235
REGISTER
ADDRESS
R104 (68h)
BIT LABEL DEFAULT DESCRIPTION
R105 (69h)
R106 (6Ah)
R191 (BFh)
R192 (C0h)
R193 (C1h)
R194 (C2h)
1:0
7:0
1:0
7:0
6:0
7:0
6:0
AGC_TARGETIN5
[9:8]
AGC_TARGETIN6
[7:0]
AGC_TARGETIN6
[9:8]
PEAKDET_RISE
[7:0]
PEAKDET_RISE
[14:8]
PEAKDET_FALL
[7:0]
PEAKDET_FALL
[14:8]
00
0000_0000
00
MSB of AGC target level for IN5
LSB of AGC target level for IN6
MSB of AGC target level for IN6
0000_0000 LSB of PEAKDET_RISE[14:0] peak detection start pixel count
000_0000 MSB of PEAKDET_RISE[14:0] peak detection start pixel count
0000_0000
LSB of PEAKDET_FALL[14:0] peak detection start pixel count
000_0000 MSB of PEAKDET_FALL[14:0] peak detection start pixel count
LINE-BY-LINE OPERATION
Certain linear sensors give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels.
The WM8235 can accommodate this type of input by setting the LINEBYLINE register bit high. The offset and gain values that are applied to every input channel can be selected, by internal multiplexers, to come from IN7, IN8 or IN9 offset and gain registers. This allows the gain and offset values for each of the input colours to be setup individually at the start of a scan.
When register bit ACYC=0 the gain and offset multiplexers are controlled via the INTM[1:0] register bits. When INTM=00 the IN7 offset and gain control registers are used to control every input channel,
INTM=01 selects the IN8 offset and gain registers and INTM=10 selects the IN9 offset and gain registers to control every input channel.
When register bit ACYC=1,
‘auto-cycling’ is enabled, and the input channel switches to the next offset and gain registers in the sequence by TGSYNC. The sequence is IN7 IN8 IN9 IN7
… offset and gain registers applied to every input channel.
INTM=00
INTM=01
INTM=10
INTM=11
LINEBYLINE 0x23[0]
INTM 0x23[3:2]
ACYC 0x23[1]
TGSYNC
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
AGAININ7, DGAININ7, DACIN7
AGAININ8, DGAININ8, DACIN8
AGAININ9, DGAININ9, DACIN9
Reserved
00
Normal Operation
0
ACYC=0
ACYC=1
AGAININ1, DGAININ1, DACIN1
AGAININ2, DGAININ2, DACIN2
AGAININ3, DGAININ3, DACIN3
AGAININ4, DGAININ4, DACIN4
AGAININ5, DGAININ5, DACIN5
AGAININ6, DGAININ6, DACIN6
AGAININ7, DGAININ7, DACIN7
AGAININ8, DGAININ8, DACIN8
AGAININ9, DGAININ9, DACIN9
01
INTM Mode (depends on INTM register)
Auto Cycling mode (IN7 -> IN8 -> IN9)
AGAININ8,
DGAININ8,
DACIN8
00
AGAININ7,
DGAININ7,
DACIN7
LINEBYLINE
INTM Mode
1
01
Must be set to 0
AGAININ8,
DGAININ8,
DACIN8
AGAININ9,
DGAININ9,
DACIN9
11
Normal Operation
0
AGAININ1, DGAININ1, DACIN1
AGAININ2, DGAININ2, DACIN2
AGAININ3, DGAININ3, DACIN3
AGAININ4, DGAININ4, DACIN4
AGAININ5, DGAININ5, DACIN5
AGAININ6, DGAININ6, DACIN6
AGAININ7, DGAININ7, DACIN7
AGAININ8, DGAININ8, DACIN8
AGAININ9, DGAININ9, DACIN9
Figure 33 Line-by-Line Operation (ACYC=0, INTM mode)
Rev 4.5
51
ACYC=0
ACYC=1
INTM Mode (depends on INTM register)
Auto Cycling mode (IN7 -> IN8 -> IN9)
LINEBYLINE 0x23[0]
ACYC 0x23[1]
0
Normal Operation
0
TGSYNC
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
AGAININ1, DGAININ1, DACIN1
AGAININ2, DGAININ2, DACIN2
AGAININ3, DGAININ3, DACIN3
AGAININ4, DGAININ4, DACIN4
AGAININ5, DGAININ5, DACIN5
AGAININ6, DGAININ6, DACIN6
AGAININ7, DGAININ7, DACIN7
AGAININ8, DGAININ8, DACIN8
AGAININ9, DGAININ9, DACIN9
LINEBYLINE
Auto Cycling Mode
1
1
AG7,
DG7,
DA7
AGAININ8,
DGAININ8,
DACIN8
AGAININ9,
DGAININ9,
DACIN9
AGAININ7,
DGAININ7,
DACIN7
AGAININ8,
DGAININ8,
DACIN8
AGAININ9,
DGAININ9,
DACIN9
AGAININ7,
DGAININ7,
DACIN7
AGAININ8,
DGAININ8,
DACIN8
AGAININ9,
DGAININ9,
DACIN9
AG7,
DG7,
DA7
WM8235
Normal Operation
0
AGAININ1, DGAININ1, DACIN1
AGAININ2, DGAININ2, DACIN2
AGAININ3, DGAININ3, DACIN3
AGAININ4, DGAININ4, DACIN4
AGAININ5, DGAININ5, DACIN5
AGAININ6, DGAININ6, DACIN6
AGAININ7, DGAININ7, DACIN7
AGAININ8, DGAININ8, DACIN8
AGAININ9, DGAININ9, DACIN9
Figure 34 Line-by-Line Operation (ACYC=1, Auto-cycling mode)
REGISTER
ADDRESS
R35 (23h)
DAC IN1
BIT
3:2
LABEL
INTM[1:0]
DEFAULT
00
1
0
ACYC
LINEBYLINE
0
0
DESCRIPTION
When LINEBYLINE=1, controls the GAIN and DAC mux selector when ACYC=0
00 = IN7
01 = IN8
10 = IN9
11 = reserved when LINEBYLINE=1, determines the function of the MUX control
0 = decided by INTM register
1= auto-cycling enabled select line by line operation
0=normal operation
1=Line by Line operation
52 Rev 4.5
WM8235
TEST PATTERN GENERATOR
WM8235 has test pattern generator which can be used for interface verification between AFE data output and back-end devices without sensor signal input. This function can be presented in several different patterns by PGPAT[1:0] and PGMARCH registers as shown below. The PGLEVEL,
PGWIDTH1 and PGWIDTH2 are the parameter to define the pattern level and width. The PGLEVEL register has 16bit length, PGWIDTH1 and PGWIDTH2 has 8bit length.
Note that test pattern generator is required TGSYNC input. (i.e. this can be used under TG slave mode operation only.) d=PGLEVEL
A=PGWIDTH1
B=PGWIDTH2
PGEN (register)
TGSYNC (input)
PGPAT=00
(Fixed Pattern)
PGPAT=01
(Vertical RAMP)
PGPAT=10
(Horizontal RAMP)
PGPAT=11
(Patch)
0
0
0
0 d
A d
0 md
A
0
B
B A d
A
Figure 35 Test Pattern Output Data Formats
d
A
0
B d
A
2d
0 0 nd d
0
0
Return to 0 at 65535
65535
0
0
0 d=PGLEVEL
A=PGWIDTH1
B=PGWIDTH2
PGINV=0
PGPAT=01
(Vertical RAMP)
TGSYNC
A
A
A
A
A
A
A
0 d
2d
3d
4d
5d
6d
PGINV=1
A
A
A
A
A
A
A
~0
~d
~2d
~3d
~4d
~5d
~6d
PGPAT=10
(Horizontal RAMP)
TGSYNC
A
A
A
A
A
A
A
A
0
A A A A A A A d 2d 3d 4d 5d 6d 7d
A d
A d
A d
A d
A d
A d
A d
A
A A A A A A A A
~0 ~d ~2d ~3d ~4d ~5d ~6d ~7d
PGPAT=11
TGSYNC
(Patch)
B A d d
0 d
0 d d d
B A B A d
B A
A ~d
~d
~0
~d
~0
~d
~d
~d
B
A
B
A
B
Figure 36 Test Pattern Output image
Rev 4.5
53
WM8235
PGEN (register)
TGSYNC (input)
PGMARCH=1
(Marching mode)
0 d[15:0]
{d[14:0], d[15]}
{d[13:0], d[15:14]}
{d[12:0], d[15:13]}
{d[1:0], d[15:2]}
{d[0], d[15:1]} d[15:0]
{d[14:0], d[15]}
1 bit shift per TGSYNC
0
Figure 37 Test Pattern Output Data Formats (Marching mode)
REGISTER
ADDRESS
R20 (14h) PG config
BIT
7
LABEL
PGMARCH
DEFAULT
0
6:5
4
3
2
1
0
PGPAT[1:0]
PGINV
SEL_PGZ
SEL_PGY
SEL_PGX
PGEN
00
0
0
0
0
0
DESCRIPTION
pattern generator marching mode enable
0 = controlled by PGPAT
1 = marching pattern select pattern generator output
00 = fixed value
01 = vertical ramp
10 = horizontal ramp
11 = patch invert pattern generator output
0 = normal
1 = invert select output of pattern generator (IN7, IN8, IN9)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs select output of pattern generator (IN4, IN5, IN6))
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs select output of pattern generator (IN1, IN2, IN3)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs enable pattern generator
0 = disable
1 = enable
REGISTER
ADDRESS
R21 (15h)
PGCODE
LSB
BIT
7:0
LABEL
PGLEVEL[7:0]
DEFAULT
0000_0000
DESCRIPTION
parameter of pattern generator
REGISTER
ADDRESS
R22 (16h)
PGCODE
MSB
BIT
7:0
LABEL
PGLEVEL[7:0]
DEFAULT
0000_0000
DESCRIPTION
parameter of pattern generator
REGISTER
ADDRESS
R23 (17h) PG width 1
BIT
7:0
LABEL
PGWIDTH1[7:0]
DEFAULT
0000_0000
DESCRIPTION
parameter of pattern generator
54 Rev 4.5
WM8235
REGISTER
ADDRESS
R24 (18h) PG width 2
BIT
7:0
LABEL DEFAULT DESCRIPTION
PGWIDTH2[7:0] 0000_0000 parameter of pattern generator
REGISTER SETTING PROCEDURE
OVERALL
Figure 38 shows the overall procedure for WM8235 register setting. Every register can be configured
without MCLK and TGSYNC input, but the following Note1~3 must be followed before starting normal operation.
POWER ON
Present External clock
MCLK (*1), TGSYNC (*2)
PLL/DLL
Configuration(*3)
Offset DAC configuration
Sampling configuration
PGA configuration
Clamp configuration(*4)
TG Clock/Pulse configuration
VRLC configuration
Data output configuration
System Reset (*3)
NORMAL OPERATION
Figure 38 Overall Procedure
Notes:
1. MCLK must be present before System Reset. Also, System Reset must be done when MCLK is interrupted during normal operation.
2. TGSYNC input is required in TG slave mode. Also, this must be present before normal operation.
3. System Reset must be done after PLL/DLL configuration.
Rev 4.5
55
WM8235
PLL/DLL CONFIGURATION
PLL and DLL registers must be configured depending on the MCLK frequency and data output format.
See
“PLL DLL Setup” section for details of configuring PLL/DLL registers. The device must be reset
after PLL/DLL configuration as shown in Figure 40.
PLL/DLL configuration
PLL configuration
0x1C[6:4]
PLL_EXDIV_SEL
DLL configuration
0x80[5:4] DLGAIN
0x81[5:4] LVDLGAIN
LDO configuration
(if required)
0x1B0[0] USER_KEY
0x1B4[4:0] LDO2_VSEL
System reset
Figure 39 PLL/DLL Configuration
System reset
Power down
(Sleep mode)
0x03[1] PDMD=1
0x03[0] PD=1
Back to
Normal operation
0x03[1] PDMD=0
0x03[0] PD=0
Figure 40 System Reset
SAMPLING CONFIGURATION
Sampling configuration is the setting for input signal polarity and sampling timing. See
” section for details of configuring this register.
Non-CDS mode (S/H mode): RSMP configuration is not required.
CDS mode: RSMP and VSMP configurations are required.
Sampling configuration
Input signal polarity configuration
0x04[6]
PGAFS
Sampling mode selection
0x04[0]
CDS=0
Non-CDS mode
0x04[0]
CDS=1
CDS mode
VSMP configuration
0x84 VSMP_RISE
0x85 VSMP_FALL
RSMP, VSMP configuration
0x82,0x83 RSMP_RISE, RSMP_FALL
0x84,0x85 VRMP_RISE, VSMP_FALL
Figure 41 Sampling Configuration
56 Rev 4.5
Rev 4.5
WM8235
CLAMP CONFIGURATION
Clamp configuration is the setting for clamp modes and clamp timing configuration in line clamp mode. See
“Reset Level Clamping (RLC)” section and “CDS/Non-CDS Processing” section for details
of configuring this register.
TG enabled: This must be enabled when AGC function is used.
Line clamp configuration: Line clamp operation is enabled during CLAMP_RISE ~ CLAMP_FALL period. Also, the source follower should be set to prevent clamp voltage drop in line clamp mode.
Pixel clamp (Bit clamp) mode: The pixel clamping is enabled during RSMP = high period. This mode can be used in CDS operation only.
Clamp configuration
Clamp mode selection
0x04[1]
CLPMD=0
Line clamp
0x04[1]
CLPMD=1
Bit clamp
TG enabled (*1)
Pixel clamp mode (*3)
TG mode selection
Master mode
0xA0[1] TGMD=1
Line length configuration
0xA1,0xA2 LLENGTH
TG enabled
0xA0[0] TG_EN
Slave mode
0xA0[1] TGMD=0
Line clamp configuration
Clamp timing configuration
0xB9,0xBA CLAMP_RISE
0xBB,0xBC CLAMP_FALL
Source follower configuration (*2)
0x05[1] SF_INP
0x05[0] SF_VRLC
Figure 42 Clamp Configuration
Notes:
1. This must be set when Line clamp is used.
2. SF_INP and SF_VRLC must be set both when source follower enabled
3. Pixel clamp can be used in CDS operation only.
VRLC CONFIGURATION
VRLC configuration is the setting for VRLC voltage, which is used for input signal clamp voltage at line clamp operation. The VRLC voltage is also used as the reference level of non-CDS (S/H) operation. See
“Reset Level Clamping (RLC)” section and “CDS/Non-CDS Processing” section for
details of configuring this register.
VRLC configuration
0x06[7]
VRLCEN=1
VRLC configuration
0x06[7]
VRLCEN=0
VRLC output range configuration
0x04[7] VRLC_TOP_SEL
VRLC output voltage configuration
0x06[4:0] VRLC_VSEL
VRLC disabled
(External VRLC operation)
Figure 43 VRLC Configuration
57
WM8235
OFFSET DAC CONFIGURATION
The offset DAC is used for black level offset compensation. WM8235 has BLC function to calibrate black level. In this mode, the offset DAC will be configured automatically. When this function is not needed, the offset DAC can be configured manually. See
“Overall Signal Flow Summary” section for
details of offset DAC configuration, and see
“BLC Scenarios of Operation” for details of BLC
sequence.
Offset DAC configuration
No
Using BLC function
Yes
Offset DAC configuration
0x24~0x2C DACIN*
BLC configuration
Figure 44 Offset DAC Configuration
BLC configuration
TG enabled: This must be enabled when AGC function is used.
BLC start pixel configuration: This is start pixel configuration for BLC.
BLC period configuration: BLC will operate while this period from BLC start pixel.
BLC target level configuration: This is configuration for the target level of black pixel.
Coarse adjust configuration:
CADUR: This is the coarse adjust iteration setting during BLC period.
CA_EVERYLINE: When this register set, coarse adjust will operate on every line.
Fine adjust configuration: This is configuration for Coarse adjust iteration.
FA_EN: When this register set, fine adjust will operate during BLC period.
FA_EVERYLINE: When this register set, fine adjust will operate on every line.
58 Rev 4.5
WM8235
BLC configuration
TG enabled (*1)
TG mode selection
Master mode
0xA0[1] TGMD=1
Line length configuration
0xA1,0xA2 LLENGTH
TG enabled
0xA0[0] TG_EN
Slave mode
0xA0[1] TGMD=0
BLC start pixel configuration
0xBD,0xBE OB_START
Coarse adjust configuration
0x51[2:0] CADUR
0x51[3] CA_EVERYLINE
BLC period configuration
0x53,0x54 BPIX_AVAIL
Fine adjust configuration
0x51[4] FA_EN
0x51[6] FA_EVERYLINE
BLC target level configuration
0x48~0x50 TARGETINn*
Set the frame start indicator (*2)
0x52[0] FRAME_START
TGSYNC
Start the frame sequence
Figure 45 BLC Configuration
Notes:
1. This must be set when BLC is used.
2. With this register set, frame sequence will be started after TGSYNC is recognized. Therefore this should be set within the last line of previous frame.
PGA CONFIGURATION
The WM8235 provides an Automatic Gain Control (AGC) function. The output code is calibrated to target level by this automatic gain control function. See
“Automatic Gain Control (AGC)” section for
details of AGC sequence. Also, see the following instruction to configure AGC related registers. The analogue PGA (APGA) and digital PGA (DPGA) can be configured manually when AGC is not required. See
“Offset Adjust and Programmable Gain” section for details of PGA configuration.
PGA configuration
Using AGC function
No
Yes
Manual PGA configuration
APGA configuration
0x2D~0x35 AGAININ*
DPGA configuration
0x36~0x47 DGAININ*
AGC configuration
Figure 46 PGA Configuration
Rev 4.5
59
WM8235
AGC CONFIGURATION
Figure 47 shows the procedure for AGC Configuration.
TG enabled: This must be enabled when AGC function is used.
AGC averaging factor configuration: This is averaging factor for peak level detection.
AGC APD/DPD configuration: This is line iteration setting for peak level detection.
AGC target level configuration: The output code will be calibrated to this target level after APGA and DPGA calibration. APGA and DPGA keep calibrated gain value while AGC is enabled.
(AGC_EN=1)
Peak detection period configuration: This is the setting for peak detection period.
AGC configuration
TG enabled (*1)
TG mode selection
Master mode
0xA0[1] TGMD=1
Line length configuration
0xA1,0xA2 LLENGTH
TG enabled
0xA0[0] TG_EN
Slave mode
0xA0[1] TGMD=0
AGC averaging factor configuration
0x57[7:4] AGCAVE
AGC target level configuration
0x59~0x6A
AGC_TARGETIN*
AGC APD configuration
0x58[2:0] AGC_APD
Peak detection period configuration
0xBF,0xC0 PEAKDET_RISE
0xC1,0xC2 PEAKDET_FALL
AGC DPD configuration
0x58[6:4] AGC_DPD
AGC enabled (*2)
0x57[0] AGC_EN=1
TGSYNC
Start AGC operation
Figure 47 AGC Configuration
Notes:
1. This must be set when AGC is used.
2. With this register set, AGC sequence will be started after TGSYNC is recognized.
60 Rev 4.5
Rev 4.5
WM8235
TG CLOCK CONFIGURATION
Figure 48 shows the procedure for TG Clock Timing and Mask Configuration. CLK1~CLK6 can be
configured as clock type output. See
“Sensor Timing Generation” section for details of TG function.
TG enabled: This must be enabled when TG mask function is used.
Mask period configuration: TG clock will be masked while mask signal is high. The rising and falling timing is configured by M*_RISE/FALL register. See
“TG Mask Timing” section for details of
this function.
Toggle point configuration: Pulse toggle timing is configured by toggle point setting (TP0~TP31).
TP* register consists of toggle point setting bit (TP value bit) and enable bit. The enable bit must be set when TP is used. Unused TP can be disabled, but it must be followed Note-2 as described below.
T1 and T2 polarity configuration: T1 and T2 are internal signal to set the TG signal polarity during mask period. See
“TG Mask Timing” section for details of this function.
TG Clock configuration
No
CLK1~6 rise/fall timing configuration
0x87~0x92
CLK*_RISE/FALL
TG enabled (*1)
Using TG Mask function
Yes
Slave mode
0xA0[1] TGMD=0
TG mode selection
Master mode
0xA0[1] TGMD=1
Line length configuration
0xA1,0xA2 LLENGTH
TG enabled
0xA0[0] TG_EN
Mask configuration
Mask period configuration
0xC3~0xCE
M*_RISE/FALL
Using T1,T2 function
Toggle setting for
M1 and M2 period
Yes
No
Toggle point
Configuration (*2)
0xCF~0x10E TP0~TP31
T1 and T2 polarity configuration
0x10F~0x116 POL*_T*
TG output enabled
CLK pin enabled
0xA5 OE_CK*=1
TG signal output enabled
0xA9 EN_CK*=1
Figure 48 TG Clock Configuration
Notes:
1. This must be set when the TG-MASK function is used.
2. When configure Toggle point (TP), it must be used from TP0 in ascending order. Also, TP pixel counter value must be se t as TP0<TP1<TP2 …..
61
62
WM8235
TG PULSE CONFIGURATION
Figure 49 shows the procedure for TG Pulse Configuration. CLK2~CLK8 can be configured as pulse
type output. See
“Sensor Timing Generation” section for details of TG function.
TG enabled: This must be enabled when TG pulse function is used.
Toggle point configuration: Pulse toggle timing is configured by toggle point setting (TP0~TP31).
TP* register consists of toggle point setting bit (TP pixel counter value bit) and enable bit. The enable bit must be set when TP is used. Unused TP can be disabled, but this must be followed Note-1 as described below.
PO0~PO7 configuration: PO0~PO7 are internal pulse for CLK pulse output. Pulse toggle timing is configured by polarity setting register (0x117~0x136 POL*_PO*).
CLK2~6 pulse out configuration: CLK2~CLK6 can select output signal type, clock type or pulse type by SEL_CK* register bit. This register must be set when pulse output is required.
PO assignment: Internal PO* pulse will be assigned to CLK2~CLK8 pin with this register.
TG Pulse configuration
TG enabled
Slave mode
0xA0[1] TGMD=0
TG mode selection
Master mode
0xA0[1] TGMD=1
Line length configuration
0xA1,0xA2 LLENGTH
TG enabled
0xA0[0] TG_EN
Pulse configuration
Toggle point
Configuration (*1)
0xCF~0x10E
TP*, GEN_TP0, EN_TP*
CLK2~6 pulse out
Configuration
0xAB~0xAD SEL_CK*=1
PO0~PO7 configuration
0x117~0x136 POL*_PO*
PO assignment
0xAB~0xAE SEL_PCK*
TG output enabled
CLK pin enabled
0xA5 OE_CK*=1
TG signal output enabled
0xA9 EN_CK*=1
Figure 49 TG Pulse Configuration
Notes:
1. When configure Toggle point (TP), it must be used from TP0 in ascending order. Also, TP pixel counter value must be set as TP0<TP1<TP2 …..
Rev 4.5
Rev 4.5
WM8235
DATA OUTPUT CONFIGURATION
Figure 50 shows the procedure for Data Output Configuration. WM8235 provides 10-bit CMOS output
and various LVDS output formats. See
“Output Data Format” section for details of LVDS and CMOS
output format.
DATA output configuration
Output mode
Selection
0x07[5]
CMOSMODE=0
0x07[5]
CMOSMODE=1
CMOS output configuration
LVDS output configuration
PLL/DLL
Configuration (*1)
Data output enabled
Output pin enabled
0x07[7] OE_OP=1
Data output enabled
0x07[6] OUTPD=0
Figure 50 Data Output Configuration
Notes: 1. For details, see
“PLL/DLL Configuration” section.
CMOS Output Configuration
Figure 51 shows the procedure for CMOS Output Configuration. Output drivability must be set when
CMOS output is selected. In CMOS output mode, flag signal will be output from DCLKN/OC[2] pin.
CMOS output configuration
Output drivability configuration (*1)
0x0D[2:0] OP_DRV
Output flag configuration
TG enabled (*2)
Use flag signal
Yes
TG mode selection
Master mode
0xA0[1] TGMD=1
Line length configuration
0xA1,0xA2 LLENGTH
TG enabled
0xA0[0] TG_EN
Slave mode
0xA0[1] TGMD=0
No
PO* pulse
Flag signal
Selection
0xB4[3:0]
SEL_FLAG
Flagpix
Flag output timing configuration
0xA3,0xA4 FLAGPIX
Flag output
(PO* period)
Flag output
(1 pixel period)
Figure 51 CMOS Output Configuration
63
WM8235
Notes:
1. OP_DRV is valid when 0x0D[3] DRV_CTRL set to 0.When DRV_CTRL set to 1, OP_DRV is invalid, and drivability of output pin can be configured individually by 0x0E~0x13 OP*_DRV and
OC*_DRV.
2. This must be set when flag is used.
LVDS Output Configuration
Figure 52 shows the procedure for LVDS Output Configuration.
LVDS format configuration: LVDS format can be configured by this register. See
” section for details of each format.
Data output order configuration: Data output order can be set by this register. See
” section for details of output order.
LVDS amplitude configuration: This is LVDS signal amplitude configuration. The LVDS amplitude is configured using the LVDS_AMP register field. Selections in the range 50mV to 200mV are supported. Note that the default code (110) should not be used.
LVDS VCM level configuration: This is LVDS common mode voltage configuration.
LVDS DCLK pattern configuration: This is DCLK output pattern configuration.
Output flag configuration: Flag type can be selected from start flag or cannel ID. See
and
“Channel ID” section for details of output flag. When this is not used, flag data (S~S4) will be
always 0.
64 Rev 4.5
LVDS output configuration
Output signal configuration
LVDS format configuration
0x07[2:0] LVDSMODE
LVDS VCM level configuration
0x08[2:0] LVDS_VCM
Data output order configuration
0x07[3] LVDSORDER
LVDS DCLK pattern configuration
0x09[6:0] LVCKPAT
LVDS amplitude configuration
0x08[5:3] LVDS_AMP
Use flag signal
No
Yes
Output flag configuration
Channel ID
Flag type
Selection
0x0A~0x0C
FLAG_S*
Start flag
TG enabled (*1)
Channel ID output
Slave mode
0xA0[1] TGMD=0
TG mode selection
Master mode
0xA0[1] TGMD=1
Line length configuration
0xA1,0xA2 LLENGTH
TG enabled
0xA0[0] TG_EN
PO* pulse
Flag signal
Selection
0xB4[3:0]
SEL_FLAG
Flagpix
Flag output timing configuration
0xA3,0xA4 FLAGPIX
Flag output
(PO* period)
Flag output
(1 pixel period)
WM8235
Figure 52 LVDS Output Configuration
Notes:
1. This must be set when start flag is used.
Rev 4.5
65
WM8235
REGISTER MAP
The WM8235 can be configured using the Control Interface. All registers not listed and all unused bits should be set to '0'.
REG NAME
R0 (0h)
Software Reset/Chip ID 1
R1 (1h)
Chip ID 2
R2 (2h) Chip Rev
R3 (3h)
Setup Reg 1
R4 (4h)
Setup Reg 2
R5 (5h) Setup Reg 3
7
0
6
0
0 0
VVRLC_TOP_SEL PGAFS
0 0
R6 (6h)
VRLC control
R7 (7h) output control
R8 (8h)
LVDS control
R9 (9h) LVDS clock pattern
VRLCEN
OE_OP
0
0
5
0
0
ADCFS
0
VRLC_ISEL[1:0]
OUTPD
LVDS_POL
CMOSMODE
4
SW_RESET_CHIP_ID[7:0]
0
CHZPD
0
CHIP_ID[7:0]
SF_BYPLS PT_SF[1:0]
OUTSYNC LVDSORDER
LVDS_AMP[2:0]
3
CHYPD
0
LVCKPAT[6:0]
2
CHIP_REV[3:0]
CHXPD
0
VRLC_VSEL[4:0]
1
PDMD
CLPMD
SF_INP
LVDSMODE[2:0]
LVDS_VCM[2:0]
0
PD
CDS
SF_VRLC
R10 (Ah) flag control 1
R11 (Bh) flag control 2
R12 (Ch) flag control 3
R13 (Dh) CMOS drivability control 1
R14 (Eh) CMOS drivability control 2
R15 (Fh) CMOS drivability control 3
R16 (10h) CMOS drivability control 4
R17 (11h) CMOS drivability control 5
R18 (12h) CMOS drivability control 6
R19 (13h) CMOS drivability control 7
R20 (14h) PG config
R21 (15h) PGCODE LSB
R22 (16h) PGCODE MSB
R23 (17h) PG width 1
R24 (18h) PG width 2
0
0
0
0
0
0
0
0
PGMARCH
0
0
FLAG_S1[3:0]
FLAG_S3[3:0]
0
0
OP1_DRV[2:0]
OP3_DRV[2:0]
OP5_DRV[2:0]
OP7_DRV[2:0]
OP9_DRV[2:0]
OC2_DRV[2:0]
PGPAT[1:0]
0
0 DRV_CTRL
0
0
0
0
0
0
PGINV SEL_PGZ
PGLEVEL[7:0]
PGLEVEL[14:8]
PGWIDTH1[7:0]
PGWIDTH2[7:0]
FLAG_S0[3:0]
FLAG_S2[3:0]
FLAG_S4[3:0]
OP_DRV[2:0]
SEL_PGY
OP0_DRV[2:0]
OP2_DRV[2:0]
OP4_DRV[2:0]
OP6_DRV[2:0]
OP8_DRV[2:0]
OC1_DRV[2:0]
SEL_PGX PGEN
0
0
0
0
0
0
R25 (19h) clock monitor
R26 (1Ah) PLL control 1
R27 (1Bh) PLL control 2
R28 (1Ch) PLL divider control 1
R29 (1Dh) PLL divider control 2
R35 (23h) Cycle mode control
R36 (24h) DAC IN1
R37 (25h) DAC IN2
R38 (26h) DAC IN3
R39 (27h) DAC IN4
R40 (28h) DAC IN5
R41 (29h) DAC IN6
R42 (2Ah) DAC IN7
R43 (2Bh) DAC IN8
R44 (2Ch) DAC IN9
R45 (2Dh) AGAIN IN1
R46 (2Eh) AGAIN IN2
R47 (2Fh) AGAIN IN3
R48 (30h) AGAIN IN4
R49 (31h) AGAIN IN5
R50 (32h) AGAIN IN6
R51 (33h) AGAIN IN7
0
0
0
0
0
0
0
0
0
0
0
PLL_LPF_SEL 0
PLL_EXDIV_SEL[2:0]
0
0
0
0
0
PLL_POSTDIV2_SEL[1:0]
0 0
DACIN1[7:0]
DACIN2[7:0]
0
0
MONCLK[2:0]
PLL_LPF_RST PLL_CP_PD PLL_VCO_PD
PLL_PFD_CTRL[1:0] PLL_CP_GAIN[1:0]
PLL_FBDIV_SEL[3:0]
PLL_POSTDIV1_SEL[3:0]
INTM[1:0] ACYC LINBYLINE
DACIN3[7:0]
DACIN4[7:0]
DACIN5[7:0]
DACIN6[7:0]
DACIN7[7:0]
DACIN8[7:0]
DACIN9[7:0]
0
0
0
0
0
0
0
0
AGAININ1[4:0]
AGAININ2[4:0]
AGAININ3[4:0]
AGAININ4[4:0]
0
0
0
0
0
0
AGAININ5[4:0]
AGAININ6[4:0]
AGAININ7[4:0]
80h
80h
80h
01h
80h
80h
80h
80h
14h
00h
80h
80h
00h
00h
09h
14h
01h
01h
01h
01h
01h
01h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
10h
00h
00h
00h
DEFAULT
35h
82h
00h
00h
40h
1Ch
8Ah
40h
35h
63h
66 Rev 4.5
WM8235
R78 (4Eh) BLC IN7 target
R79 (4Fh) BLC IN8 target
R80 (50h) BLC IN9 target
R81 (51h) BLC control 1
R82 (52h) BLC control 2
R83 (53h) BLC control 3
R84 (54h) BLC control 4
R85 (55h) BLC control 5
R86 (56h) BLC control 6
R87 (57h) AGC config 1
R88 (58h) AGC config 2
R89 (59h) AGC target IN1 LSB
R90 (5Ah) AGC target IN1 MSB
R91 (5Bh) AGC target IN2 LSB
R92 (5Ch) AGC target IN2 MSB
R93 (5Dh) AGC target IN3 LSB
R94 (5Eh) AGC target IN3 MSB
R95 (5Fh) AGC target IN4 LSB
R96 (60h) AGC target IN4 MSB
R97 (61h) AGC target IN5 LSB
R98 (62h) AGC target IN5 MSB
R99 (63h) AGC target IN6 LSB
R100 (64h) AGC target IN6 MSB
R101 (65h) AGC target IN7 LSB
R102 (66h) AGC target IN7 MSB
REG NAME
R52 (34h) AGAIN IN8
R53 (35h) AGAIN IN9
R54 (36h) DGAIN IN1 LSB
R55 (37h) DGAIN IN1 MSB
R56 (38h) DGAIN IN2 LSB
R57 (39h) DGAIN IN2 MSB
R58 (3Ah) DGAIN IN3 LSB
R59 (3Bh) DGAIN IN3 MSB
R60 (3Ch) DGAIN IN4 LSB
R61 (3Dh) DGAIN IN4 MSB
R62 (3Eh) DGAIN IN5 LSB
R63 (3Fh) DGAIN IN5 MSB
R64 (40h) DGAIN IN6 LSB
R65 (41h) DGAIN IN6 MSB
R66 (42h) DGAIN IN7 LSB
R67 (43h) DGAIN IN7 MSB
R68 (44h) DGAIN IN8 LSB
R69 (45h) DGAIN IN8 MSB
R70 (46h) DGAIN IN9 LSB
R71 (47h) DGAIN IN9 MSB
R72 (48h) BLC IN1 target
R73 (49h) BLC IN2 target
R74 (4Ah) BLC IN3 target
R75 (4Bh) BLC IN4 target
R76 (4Ch) BLC IN5 target
R77 (4Dh) BLC IN6 target
Rev 4.5
7
0
0
6 5
0
0
DGAININ1[3:0]
0
0
FRAME_SEQ FA_EVERYLINE FA_ACCUM
0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
AGCAVE[3:0]
0
AGC_DPD[2:0]
0
0
0
0
0
0
0
DGAININ2[3:0]
DGAININ3[3:0]
DGAININ4[3:0]
DGAININ5[3:0]
DGAININ6[3:0]
DGAININ7[3:0]
DGAININ8[3:0]
DGAININ9[3:0]
0
0
0
0
0
0
0
0
4 3
0
DGAININ1[11:4]
0
DGAININ2[11:4]
0
DGAININ3[11:4]
0
DGAININ4[11:4]
0
DGAININ5[11:4]
0
DGAININ6[11:4]
0
DGAININ7[11:4]
0
DGAININ8[11:4]
0
DGAININ9[11:4]
TARGETIN1[7:0]
TARGETIN2[7:0]
TARGETIN3[7:0]
TARGETIN4[7:0]
TARGETIN5[7:0]
TARGETIN6[7:0]
TARGETIN7[7:0]
TARGETIN8[7:0]
TARGETIN9[7:0]
FA_EN CA_EVERYLINE
2
AGAININ8[4:0]
AGAININ9[4:0]
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CADUR[2:0]
SEQ_START FRAME_START 0 0
BPIX_AVAIL[7:0]
0
LINE_DEL[7:0]
0
0 0
0
0
AGC_TARGETIN1[7:0]
0 0
AGC_TARGETIN2[7:0]
0 0
AGC_TARGETIN3[7:0]
0 0
AGC_TARGETIN4[7:0]
0 0
0
0
0
0
0
0
BPIX_AVAIL[9:8]
0 LINE_DEL[8]
AGC_ERRFLAG AGC_ENDFLAG AGC_EN
AGC_APD[2:0]
AGC_TARGETIN1[9:8]
AGC_TARGETIN2[9:8]
AGC_TARGETIN3[9:8]
AGC_TARGETIN4[9:8]
80h
00h
00h
00h
00h
00h
00h
80h
00h
80h
00h
80h
00h
80h
00h
DEFAULT
01h
01h
00h
80h
00h
80h
00h
80h
00h
80h
00h
AGC_TARGETIN5[7:0]
0 0
AGC_TARGETIN6[7:0]
0 0
AGC_TARGETIN7[7:0]
0 0
0
0
0
AGC_TARGETIN5[9:8]
AGC_TARGETIN6[9:8]
AGC_TARGETIN7[9:8]
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
67
WM8235
R132 (84h) VSMP rise
R133 (85h) VSMP fall
R134 (86h) TGCKO rise
R135 (87h) CLK1 rise
R136 (88h) CLK1 fall
R137 (89h) CLK2 rise
R138 (8Ah) CLK2fall
R139 (8Bh) CLK3 rise
R140 (8Ch) CLK3 fall
R141 (8Dh) CLK4 rise
R142 (8Eh) CLK4 fall
R143 (8Fh) CLK5 rise
R144 (90h) CLK5 fall
R145 (91h) CLK6 rise
R146 (92h) CLK6 fall
R160 (A0h) TG config 1
R161 (A1h) TG config 2
R162 (A2h) TG config 3
R163 (A3h) TG config 4
R164 (A4h) TG config 5
R165 (A5h) TG config 6
R167 (A7h) TG config 8
R169 (A9h) TG config 10
R171 (ABh) TG config 12
R172 (ACh) TG config 13
REG NAME
R103 (67h) AGC target IN8 LSB
R104 (68h) AGC target IN8 MSB
R105 (69h) AGC target IN9 LSB
R106 (6Ah) AGC target IN9 MSB
R107 (6Bh) AGC peak level IN1 LSB
R108 (6Ch) AGC peak level IN1 MSB
R109 (6Dh) AGC peak level IN2 LSB
R110 (6Eh) AGC peak level IN2 MSB
R111 (6Fh) AGC peak level IN3 LSB
R112 (70h) AGC peak level IN3 MSB
R113 (71h) AGC peak level IN4 LSB
R114 (72h) AGC peak level IN4 MSB
R115 (73h) AGC peak level IN5 LSB
R116 (74h) AGC peak level IN5 MSB
R117 (75h) AGC peak level IN6 LSB
R118 (76h) AGC peak level IN6 MSB
R119 (77h) AGC peak level IN7 LSB
R120 (78h) AGC peak level IN7 MSB
R121 (79h) AGC peak level IN8 LSB
R122 (7Ah) AGC peak level IN8 MSB
R123 (7Bh) AGC peak level IN9 LSB
R124 (7Ch) AGC peak level IN9 MSB
R128 (80h) DLL config 1
R129 (81h) DLL config 2
R130 (82h) RSMP rise
R131 (83h) RSMP fall
68
7
0
0
0
0
0
0
0
0
0
0
0
0
OE_CLK8
INV_CLK8
EN_CLK8
SEL_CLK3
SEL_CLK5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OFFSET[3:0]
5
0
0
0
0
0
4 3
AGC_TARGETIN8[7:0]
0 0
AGC_TARGETIN9[7:0]
0 0
0
PEAK_IN1[7:0]
0
PEAK_IN2[7:0]
0
PEAK_IN3[7:0]
0
0
PEAK_IN4[7:0]
0
2
0
0
0
0
0
0
0
0
0
0
PEAK_IN5[7:0]
0
0
PEAK_IN6[7:0]
0
0
PEAK_IN7[7:0]
0
0
PEAK_IN8[7:0]
0
0
0
0
0
0
0
DLGAIN[1:0]
LVDLGAIN[1:0]
0
PEAK_IN9[7:0]
0
0 0
0
0
0
0
DLLRST
0
RSMP_RISE[5:0]
RSMP_FALL[5:0]
VSMP_RISE[5:0]
VSMP_FALL[5:0]
TCLKO_RISE[5:0]
CLK1_RISE[5:0]
CLK1_FALL[5:0]
CLK2_RISE[5:0]
CLK2_FALL[5:0]
CLK3_RISE[5:0]
CLK3_FALL[5:0]
CLK4_RISE[5:0]
CLK4_FALL[5:0]
CLK5_RISE[5:0]
CLK5_FALL[5:0]
CLK6_RISE[5:0]
CLK6_FALL[5:0]
CYCMD POLSYNC
OE_CLK7
INV_CLK7
EN_CLK7
OE_CLK6
INV_CLK6
EN_CLK6
SEL_PCK3[2:0]
SEL_PCK5[2:0]
LLENGTH[7:0]
LLENGTH[14:8]
FLAGPIX[7:0]
OE_CLK5
INV_CLK5
EN_CLK5
FLAGPIX[14:8]
OE_CLK4
INV_CLK4
EN_CLK4
SEL_CLK2
SEL_CLK4
OE_CLK3
INV_CLK3
EN_CLK3
1
AGC_TARGETIN8[9:8]
AGC_TARGETIN9[9:8]
PEAK_IN1[9:8]
PEAK_IN2[9:8]
PEAK_IN3[9:8]
PEAK_IN4[9:8]
PEAK_IN5[9:8]
PEAK_IN6[9:8]
PEAK_IN7[9:8]
PEAK_IN8[9:8]
PEAK_IN9[9:8]
CKOSTB AFECKSTB
LVDLLRST LVDLLSTB
TGMD
0
TG_EN
OE_CLK2
INV_CLK2
EN_CLK2
SEL_PCK2[2:0]
SEL_PCK4[2:0]
OE_CLK1
INV_CLK1
EN_CLK1
28h
0Ah
28h
00h
0Ah
00h
00h
0Ah
19h
19h
28h
28h
00h
08h
37h
0Ah
00h
00h
00h
00h
FFh
00h
00h
00h
00h
00h
00h
00h
20h
10h
1Ch
26h
00h
00h
00h
00h
00h
00h
00h
00h
DEFAULT
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Rev 4.5
WM8235
R200 (C8h) Mask pulse 2 rise MSB
R201 (C9h) Mask pulse 2 fall LSB
R202 (CAh) Mask pulse 2 fall MSB
R203 (CBh) Mask pulse 3 rise LSB
R204 (CCh) Mask pulse 3 rise MSB
R205 (CDh) Mask pulse 3 fall LSB
R206 (CEh) Mask pulse 3 fall MSB
R207 (CFh) Toggle point 0 LSB
R208 (D0h) Toggle point 0 MSB
R209 (D1h) Toggle point 1 LSB
R210 (D2h) Toggle point 1 MSB
R211 (D3h) Toggle point 2 LSB
R212 (D4h) Toggle point 2 MSB
R213 (D5h) Toggle point 3 LSB
R214 (D6h) Toggle point 3 MSB
R215 (D7h) Toggle point 4 LSB
R216 (D8h) Toggle point 4 MSB
R217 (D9h) Toggle point 5 LSB
R218 (DAh) Toggle point 5 MSB
R219 (DBh) Toggle point 6 LSB
R220 (DCh) Toggle point 6 MSB
R221 (DDh) Toggle point 7 LSB
R222 (DEh) Toggle point 7 MSB
R223 (DFh) Toggle point 8 LSB
R224 (E0h) Toggle point 8 MSB
REG NAME
R173 (ADh) TG config 14
R174 (AEh) TG config 15
R176 (B0h) TG config 17
R177 (B1h) TG config 18
R178 (B2h) TG config 19
R179 (B3h) TG config 20
R180 (B4h) TG config 21
R181 (B5h) TG config 22
R182 (B6h) TG config 23
R183 (B7h) TG config 24
R184 (B8h) TG config 25
R185 (B9h) clamp enable rise LSB
R186 (BAh) clamp enable rise MSB
R187 (BBh) clamp enable fall LSB
R188 (BCh) clamp enable fall MSB
R189 (BDh) OB start LSB
R190 (BEh) OB start MSB
R191 (BFh) peak_det rise LSB
R192 (C0h) peak_det rise MSB
R193 (C1h) peak_det fall LSB
R194 (C2h) peak_det fall MSB
R195 (C3h) Mask pulse 1 rise LSB
R196 (C4h) Mask pulse 1 rise MSB
R197 (C5h) Mask pulse 1 fall LSB
R198 (C6h) Mask pulse 1 fall MSB
R199 (C7h) Mask pulse 2 rise LSB
Rev 4.5
0
0
0
0
0
0
0
7 6
0
0
DEL_PCK5[1:0]
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GEN_TP0
EN_TP1
EN_TP2
EN_TP3
EN_TP4
EN_TP5
EN_TP6
EN_TP7
EN_TP8
5 4
SEL_PCK7[2:0]
0 0
DEL_PCK4[1:0]
DEL_PCK8[1:0]
0
0
0
CYCPAT_PO1[2:0]
CYCPAT_PO3[2:0]
CYCPAT_PO5[2:0]
CYCPAT_PO7[2:0]
0
INV_M3
0
3
SEL_CLK6
0
DEL_PCK3[1:0]
DEL_PCK7[1:0]
0
INV_M2
0
0
0
0
CLAMP_RISE[7:0]
CLAMP_RISE[14:8]
CLAMP_FALL[7:0]
CLAMP_FALL[14:8]
2
0
INV_M1
SEL_PCK6[2:0]
SEL_PCK8[2:0]
INV_T2
SEL_FLAG[3:0]
1
0
CYCPAT_PO0[2:0]
CYCPAT_PO2[2:0]
CYCPAT_PO4[2:0]
CYCPAT_PO6[2:0]
0
DEL_PCK2[1:0]
DEL_PCK6[1:0]
0
INV_T1
OB_START[7:0]
OB_START[14:8]
PEAKDET_RISE[7:0]
PEAKDET_RISE[14:8]
PEAKDET_FALL[7:0]
PEAKDET_FALL[14:8]
M1_RISE[7:0]
M1_RISE[14:8]
M1_FALL[7:0]
M1_FALL[14:8]
M2_RISE[7:0]
M2_RISE[14:8]
M2_FALL[7:0]
M2_FALL[14:8]
M3_RISE[7:0]
M3_RISE[14:8]
M3_FALL[7:0]
M3_FALL[14:8]
TP0[7:0]
TP0[14:8]
TP1[7:0]
TP1[14:8]
TP2[7:0]
TP2[14:8]
TP3[7:0]
TP3[14:8]
TP4[7:0]
TP4[14:8]
TP5[7:0]
TP5[14:8]
TP6[7:0]
TP6[14:8]
TP7[7:0]
TP7[14:8]
TP8[7:0]
TP8[14:8]
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
DEFAULT
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
69
WM8235
R251 (FBh) Toggle point 22 LSB
R252 (FCh) Toggle point 22 MSB
R253 (FDh) Toggle point 23 LSB
R254 (FEh) Toggle point 23 MSB
R255 (FFh) Toggle point 24 LSB
R256 (100h) Toggle point 24 MSB
R257 (101h) Toggle point 25 LSB
R258 (102h) Toggle point 25 MSB
R259 (103h) Toggle point 26 LSB
R260 (104h) Toggle point 26 MSB
R261 (105h) Toggle point 27 LSB
R262 (106h) Toggle point 27 MSB
R263 (107h) Toggle point 28 LSB
R264 (108h) Toggle point 28 MSB
R265 (109h) Toggle point 29 LSB
R266 (10Ah) Toggle point 29 MSB
R267 (10Bh) Toggle point 30 LSB
R268 (10Ch) Toggle point 30 MSB
R269 (10Dh) Toggle point 31 LSB
R270 (10Eh) Toggle point 31 MSB
R271 (10Fh) Polarity setting of T1 1
R272 (110h) Polarity setting of T1 2
R273 (111h) Polarity setting of T1 3
R274 (112h) Polarity setting of T1 4
R275 (113h) Polarity setting of T2 1
REG NAME
R225 (E1h) Toggle point 9 LSB
R226 (E2h) Toggle point 9 MSB
R227 (E3h) Toggle point 10 LSB
R228 (E4h) Toggle point 10 MSB
R229 (E5h) Toggle point 11 LSB
R230 (E6h) Toggle point 11 MSB
R231 (E7h) Toggle point 12 LSB
R232 (E8h) Toggle point 12 MSB
R233 (E9h) Toggle point 13 LSB
R234 (EAh) Toggle point 13 MSB
R235 (EBh) Toggle point 14 LSB
R236 (ECh) Toggle point 14 MSB
R237 (EDh) Toggle point 15 LSB
R238 (EEh) Toggle point 15 MSB
R239 (EFh) Toggle point 16 LSB
R240 (F0h) Toggle point 16 MSB
R241 (F1h) Toggle point 17 LSB
R242 (F2h) Toggle point 17 MSB
R243 (F3h) Toggle point 18 LSB
R244 (F4h) Toggle point 18 MSB
R245 (F5h) Toggle point 19 LSB
R246 (F6h) Toggle point 19 MSB
R247 (F7h) Toggle point 20 LSB
R248 (F8h) Toggle point 20 MSB
R249 (F9h) Toggle point 21 LSB
R250 (FAh) Toggle point 21 MSB
70
7
EN_TP9
EN_TP10
EN_TP11
EN_TP12
EN_TP13
EN_TP14
EN_TP15
EN_TP16
EN_TP17
EN_TP18
EN_TP19
EN_TP20
EN_TP21
EN_TP22
EN_TP23
EN_TP24
EN_TP25
EN_TP26
EN_TP27
EN_TP28
EN_TP29
EN_TP30
6 5
EN_TP31
POL7_T1
POL15_T1
POL23_T1
POL31_T1
POL7_T2
POL6_T1
POL14_T1
POL22_T1
POL30_T1
POL6_T2
POL5_T1
POL13_T1
POL21_T1
POL29_T1
POL5_T2
TP22[7:0]
TP22[14:8]
TP23[7:0]
TP23[14:8]
TP24[7:0]
TP24[14:8]
TP25[7:0]
TP25[14:8]
TP26[7:0]
TP26[14:8]
TP27[7:0]
TP27[14:8]
TP28[7:0]
TP28[14:8]
TP29[7:0]
TP29[14:8]
POL4_T1
POL12_T1
POL20_T1
POL28_T1
POL4_T2
TP30[7:0]
TP30[14:8]
TP31[7:0]
TP31[14:8]
POL3_T1
POL11_T1
POL19_T1
POL27_T1
POL3_T2
4 3
TP9[7:0]
TP9[14:8]
TP10[7:0]
TP10[14:8]
TP11[7:0]
TP11[14:8]
TP12[7:0]
TP12[14:8]
TP13[7:0]
TP13[14:8]
TP14[7:0]
TP14[14:8]
TP15[7:0]
TP15[14:8]
TP16[7:0]
TP16[14:8]
TP17[7:0]
TP17[14:8]
TP18[7:0]
TP18[14:8]
TP19[7:0]
TP19[14:8]
TP20[7:0]
TP20[14:8]
TP21[7:0]
TP21[14:8]
2 1
POL2_T1
POL10_T1
POL18_T1
POL26_T1
POL2_T2
POL1_T1
POL9_T1
POL17_T1
POL25_T1
POL1_T2
0
POL0_T1
POL8_T1
POL16_T1
POL24_T1
POL0_T2
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
DEFAULT
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Rev 4.5
WM8235
REG NAME
R276 (114h) Polarity setting of T2 2
R277 (115h) Polarity setting of T2 3
R278 (116h) Polarity setting of T2 4
R279 (117h) Polarity setting of P0 1
R280 (118h) Polarity setting of P0 2
R281 (119h) Polarity setting of P0 3
R282 (11Ah) Polarity setting of P0 4
R283 (11Bh) Polarity setting of P1 1
R284 (11Ch) Polarity setting of P1 2
R285 (11Dh) Polarity setting of P1 3
R286 (11Eh) Polarity setting of P1 4
R287 (11Fh) Polarity setting of P2 1
R288 (120h) Polarity setting of P2 2
R289 (121h) Polarity setting of P2 3
R290 (122h) Polarity setting of P2 4
R291 (123h) Polarity setting of P3 1
R292 (124h) Polarity setting of P3 2
R293 (125h) Polarity setting of P3 3
R294 (126h) Polarity setting of P3 4
R295 (127h) Polarity setting of P4 1
R296 (128h) Polarity setting of P4 2
R297 (129h) Polarity setting of P4 3
R298 (12Ah) Polarity setting of P4 4
R299 (12Bh) Polarity setting of P5 1
R300 (12Ch) Polarity setting of P5 2
R301 (12Dh) Polarity setting of P5 3
R302 (12Eh) Polarity setting of P5 4
R303 (12Fh) Polarity setting of P6 1
R304 (130h) Polarity setting of P6 2
R305 (131h) Polarity setting of P6 3
R306 (132h) Polarity setting of P6 4
R307 (133h) Polarity setting of P7 1
R308 (134h) Polarity setting of P7 2
R309 (135h) Polarity setting of P7 3
R310 (136h) Polarity setting of P7 4
7 6 5 4 3 2 1 0
POL15_T2
POL23_T2
POL14_T2
POL22_T2
POL13_T2
POL21_T2
POL12_T2
POL20_T2
POL11_T2
POL19_T2
POL10_T2
POL18_T2
POL9_T2
POL17_T2
POL8_T2
POL16_T2
POL31_T2 POL30_T2 POL29_T2 POL28_T2 POL27_T2 POL26_T2 POL25_T2 POL24_T2
POL7_PO0 POL6_PO0 POL5_PO0 POL4_PO0 POL3_PO0 POL2_PO0 POL1_PO0 POL0_PO0
POL15_PO0 POL14_PO0 POL13_PO0 POL12_PO0 POL11_PO0 POL10_PO0 POL9_PO0 POL8_PO0
POL23_PO0 POL22_PO0 POL21_PO0 POL20_PO0 POL19_PO0 POL18_PO0 POL17_PO0 POL16_PO0
POL31_PO0 POL30_PO0 POL29_PO0 POL28_PO0 POL27_PO0 POL26_PO0 POL25_PO0 POL24_PO0
POL7_PO1 POL6_PO1 POL5_PO1 POL4_PO1 POL3_PO1 POL2_PO1 POL1_PO1 POL0_PO1
POL15_PO1 POL14_PO1 POL13_PO1 POL12_PO1 POL11_PO1 POL10_PO1 POL9_PO1 POL8_PO1
POL23_PO1 POL22_PO1 POL21_PO1 POL20_PO1 POL19_PO1 POL18_PO1 POL17_PO1 POL16_PO1
POL31_PO1 POL30_PO1 POL29_PO1 POL28_PO1 POL27_PO1 POL26_PO1 POL25_PO1 POL24_PO1
POL7_PO2 POL6_PO2 POL5_PO2 POL4_PO2 POL3_PO2 POL2_PO2 POL1_PO2 POL0_PO2
POL15_PO2 POL14_PO2 POL13_PO2 POL12_PO2 POL11_PO2 POL10_PO2 POL9_PO2 POL8_PO2
POL23_PO2 POL22_PO2 POL21_PO2 POL20_PO2 POL19_PO2 POL18_PO2 POL17_PO2 POL16_PO2
POL31_PO2 POL30_PO2 POL29_PO2 POL28_PO2 POL27_PO2 POL26_PO2 POL25_PO2 POL24_PO2
POL7_PO3 POL6_PO3 POL5_PO3 POL4_PO3 POL3_PO3 POL2_PO3 POL1_PO3 POL0_PO3
POL15_PO3 POL14_PO3 POL13_PO3 POL12_PO3 POL11_PO3 POL10_PO3 POL9_PO3 POL8_PO3
POL23_PO3 POL22_PO3 POL21_PO3 POL20_PO3 POL19_PO3 POL18_PO3 POL17_PO3 POL16_PO3
POL31_PO3 POL30_PO3 POL29_PO3 POL28_PO3 POL27_PO3 POL26_PO3 POL25_PO3 POL24_PO3
POL7_PO4 POL6_PO4 POL5_PO4 POL4_PO4 POL3_PO4 POL2_PO4 POL1_PO4 POL0_PO4
POL15_PO4 POL14_PO4 POL13_PO4 POL12_PO4 POL11_PO4 POL10_PO4 POL9_PO4 POL8_PO4
POL23_PO4 POL22_PO4 POL21_PO4 POL20_PO4 POL19_PO4 POL18_PO4 POL17_PO4 POL16_PO4
POL31_PO4 POL30_PO4 POL29_PO4 POL28_PO4 POL27_PO4 POL26_PO4 POL25_PO4 POL24_PO4
POL7_PO5 POL6_PO5 POL5_PO5 POL4_PO5 POL3_PO5 POL2_PO5 POL1_PO5 POL0_PO5
POL15_PO5 POL14_PO5 POL13_PO5 POL12_PO5 POL11_PO5 POL10_PO5 POL9_PO5 POL8_PO5
POL23_PO5 POL22_PO5 POL21_PO5 POL20_PO5 POL19_PO5 POL18_PO5 POL17_PO5 POL16_PO5
POL31_PO5 POL30_PO5 POL29_PO5 POL28_PO5 POL27_PO5 POL26_PO5 POL25_PO5 POL24_PO5
POL7_PO6 POL6_PO6 POL5_PO6 POL4_PO6 POL3_PO6 POL2_PO6 POL1_PO6 POL0_PO6
POL15_PO6 POL14_PO6 POL13_PO6 POL12_PO6 POL11_PO6 POL10_PO6 POL9_PO6 POL8_PO6
POL23_PO6 POL22_PO6 POL21_PO6 POL20_PO6 POL19_PO6 POL18_PO6 POL17_PO6 POL16_PO6
POL31_PO6 POL30_PO6 POL29_PO6 POL28_PO6 POL27_PO6 POL26_PO6 POL25_PO6 POL24_PO6
POL7_PO7 POL6_PO7 POL5_PO7 POL4_PO7 POL3_PO7 POL2_PO7 POL1_PO7 POL0_PO7
POL15_PO7 POL14_PO7 POL13_PO7 POL12_PO7 POL11_PO7 POL10_PO7 POL9_PO7 POL8_PO7
POL23_PO7 POL22_PO7 POL21_PO7 POL20_PO7 POL19_PO7 POL18_PO7 POL17_PO7 POL16_PO7
POL31_PO7 POL30_PO7 POL29_PO7 POL28_PO7 POL27_PO7 POL26_PO7 POL25_PO7 POL24_PO7
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
DEFAULT
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
EXTENDED PAGE REGISTERS
R432 (1B0h) User access control
R436 (1B4h) LDO2 control
R448 (1C0h) USER_KEY2
R459 (1CBh) Comp control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.
4.
Notes:
1.
2.
To change the LDO2 control, the USER_KEY bit must be set to ‘1’.
If it’s not required to change this register, it must be set as default.
To change the Comp control, the USER_KEY2 bit must be set to ‘1’.
If it’s not required to change this register, must be set as default.
0
0
0
0
LDO2 VSEL
0
0
0 USER_KEY
0 USER_KEY2
PT_COMP[1:0]
00h
10h
00h
01h
Rev 4.5
71
WM8235
REGISTER BITS BY ADDRESS
DEFAULT REGISTER
ADDRESS
R0 (00h)
Software
Reset/Chip
ID 1
BIT
7:0
LABEL
SW_RESET_
CHIP_ID[7:0]
Register 00h Software Reset/Chip ID 1
DESCRIPTION
0011_0101 A write issues a software reset, and returns all control registers to their default values.
A read returns lower bits of the device ID
REGISTER
ADDRESS
R1 (01h)
Chip ID 2
BIT
7:0
Register 01h Chip ID 2
LABEL DEFAULT DESCRIPTION
CHIP_ID[7:0] 1000_0010 A read returns upper bits of the device ID
REGISTER
ADDRESS
R2 (02h)
Chip Rev
BIT
3:0
Register 02h Chip Rev
LABEL
CHIP_REV[3:0]
DEFAULT
0000
DESCRIPTION
A read returns the device revision number
REGISTER
ADDRESS
R3 (03h)
Setup Reg 1
BIT
4
LABEL
CHZPD
DEFAULT
0
DESCRIPTION
3
2
1
0
CHYPD
CHXPD
PDMD
PD
0
0
0
0
ADC powerdown control for channel 7&8&9
(related PGA and digits goes power down)
0 = normal operation
1 = power down
ADC powerdown control for channel 4&5&6
(related PGA and digits goes power down)
0 = normal operation
1 = power down
ADC powerdown control for channel 1&2&3
(related PGA and digits goes power down)
0 = normal operation
1 = power down power down mode
0 : standby
1 : sleep power down
0 : normal operation
1 : power down
Register 03h Setup Reg 1
REGISTER
ADDRESS
R4 (04h)
Setup Reg 2
BIT
7
LABEL
VRLC_TOP_SE
L
DEFAULT
0
72
6 PGAFS 1
DESCRIPTION
selects output range of VRLCDAC
0 = AVDD
1 = 1.6V control PGA input polarity
0 = negative
1 = positive
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
5
1
0
ADCFS
CLPMD
CDS
0
0
0 control ADC full scale range
0 = 1.2V
1 = 1.8V select clamp mode
0 = line clamp
1 = bit clamp
CDS mode control
0 = S/H mode
1 = CDS mode
Register 04h Setup Reg 2
REGISTER
ADDRESS
R5 (05h)
Setup Reg 3
BIT
4
LABEL
SF_BYPLS
DEFAULT DESCRIPTION
3:2
1
0
PT_SF[1:0]
SF_INP
SF_VRLC
1
11
0
0 bypass level shift of VRLC source follower
0 = use level shifter
1 = bypass level shifter source follower power trim
00 = 1mA
01 = 2mA
10 = 3mA
11 = 4mA control source follower on signal inputs INP*
0 = disabled
1 = enabled control source follower on VRLC
0 = disabled
1 = enabled
Register 05h Setup Reg 3
REGISTER
ADDRESS
R6 (06h)
VRLC control
BIT LABEL DEFAULT DESCRIPTION
7
6:5 VRLC_ISEL[1:0]
4:0
VRLCEN
VRLC_VSEL[4:0
]
1
00 enable for VRLC DAC
0 = disabled
1 = enabled selects output current capability
00 = Up to 2mA
01 = Up to 3mA
10 = Up to 4mA
11 = reserved (Up to 2mA)
0_1010 VRLC output voltage setting when VRLC_TOP_SEL=0 (AVDD)
3.3/AVDD * ( 0.2 + 0.09xVRLC_VSEL[4:0]) when VRLC_TOP_SEL=1 (1.6V)
1.6 - 0.048*(31-VRLC_VSEL[4:0])
Register 06h VRLC control
Rev 4.5
WM8235
REFER TO
REFER TO
REFER TO
73
REGISTER
ADDRESS
R7 (07h) output
control
BIT
7
6
5
4
3
LABEL
OE_OP
OUTPD
CMOSMODE
OUTSYNC
LVDSORDER
2:0 LVDSMODE[2:0
]
DEFAULT
0
1
0
0
0
000
DESCRIPTION
output enable of dataout (CMOS/LVDS) when HIZCTRL=0
0= Hi-Z
1= enable dataout when HIZCTRL=1
OE_OP state is neglected and enable dataout control data output
0 = enable data output
1 = mask data output (data out=0) enable CMOS output mode
0 = LVDS output mode based on LVDSMODE[2:0]
1 = CMOS output mode enable syncronous output mode
0 = continuous
1 = syncronized dataout with LineStart signal control LVDS data output order
0 = descending order
1 = ascending order select LVDS dataoutput format
000 = 10bit 5pair + clk
001 = 10bit 3pair + clk
011 = 12bit 4pair + clk
101 = 16bit 5pair + clk
110 = 16bit 3pair + clk
Others = reserved
Register 07h output control
REGISTER
ADDRESS
R8 (08h)
LVDS control
BIT
6
LABEL
LVDS_POL
DEFAULT
0
5:3 LVDS_AMP[2:0]
2:0 LVDS_VCM[2:0]
110
101
DESCRIPTION
invert LVDS outputs polarity
0 = normal
1 = inverted
LVDS amplitude select
000 = 50mV
001 = 100mV
010 = 150mV
011 = 200mV
All other codes are Reserved.
Note that the default code (110) should not be used.
LVDS common mode select
000 = 0.70V
001 = 0.80V
010 = 0.90V
011 = 1.00V
100 = 1.15V
101 = 1.25V
110 = 1.35V
111 = 1.45V
Register 08h LVDS control
WM8235
REFER TO
REFER TO
74 Rev 4.5
REGISTER
ADDRESS
R9 (09h)
LVDS clock pattern
BIT
6:0
LABEL
LVCKPAT[6:0]
Register 09h LVDS clock pattern
DEFAULT
110_0011
LVDS clock pattern
(output MSB first)
DESCRIPTION
REGISTER
ADDRESS
R10 (0Ah) flag control 1
BIT
7:4
3:0
LABEL
FLAG_S1[3:0]
FLAG_S0[3:0]
DEFAULT
0001
0000
DESCRIPTION
output dataflag as S1
(valid only LVDS mode)
0000 = always low
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = always high output dataflag as S0
(valid only LVDS mode)
0000 = always low
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = always high
Register 0Ah flag control 1
REGISTER
ADDRESS
R11 (0Bh)
flag control 2
BIT
7:4
LABEL
FLAG_S3[3:0]
DEFAULT
0000
DESCRIPTION
output dataflag as S3
(valid only LVDS mode)
0000 = always low
0001 = start flag
Rev 4.5
WM8235
REFER TO
REFER TO
REFER TO
75
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
3:0 FLAG_S2[3:0] 0000
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = always high output dataflag as S2
(valid only LVDS mode)
0000 = always low
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = always high
Register 0Bh flag control 2
REGISTER
ADDRESS
R12 (0Ch) flag control 3
BIT
3:0
LABEL
FLAG_S4[3:0]
DEFAULT
0000
DESCRIPTION
output dataflag as S4
(valid only LVDS mode)
0000 = always low
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
76
WM8235
REFER TO
REFER TO
Rev 4.5
WM8235
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION REFER TO
1110 = reserved
1111 = always high
Register 0Ch flag control 3
REGISTER
ADDRESS
R13 (0Dh)
CMOS drivability control 1
BIT
3
LABEL
DRV_CTRL
2:0 OP_DRV[2:0]
DEFAULT
0
000
DESCRIPTION
CMOS output drivability control mode
0 = OP_DRV controls drivability of all output pins OP*
1 = OP_DRV is invalid, and OP*_DRV control drivability of output pin OP*
CMOS output drivability control when DRV_CTRL=0
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
REFER TO
Register 0Dh CMOS drivability control 1
REGISTER
ADDRESS
R14 (0Eh)
CMOS drivability control 2
BIT
6:4
2:0
LABEL
OP1_DRV[2:0]
OP0_DRV[2:0]
DEFAULT
000
000
DESCRIPTION
CMOS output (OP2) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
CMOS output (OP1) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 0Eh CMOS drivability control 2
REGISTER
ADDRESS
R15 (0Fh)
CMOS drivability control 3
BIT
6:4
LABEL
OP3_DRV[2:0]
DEFAULT
000
Rev 4.5
DESCRIPTION
CMOS output (OP4) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
REFER TO
REFER TO
77
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
2:0 OP2_DRV[2:0] 000
CMOS output (OP3) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 0Fh CMOS drivability control 3
REGISTER
ADDRESS
R16 (10h)
CMOS drivability control 4
BIT
6:4
2:0
LABEL
OP5_DRV[2:0]
OP4_DRV[2:0]
DEFAULT
000
000
DESCRIPTION
Register 10h CMOS drivability control 4
REGISTER
ADDRESS
R17 (11h)
CMOS drivability control 5
BIT
6:4
LABEL
OP7_DRV[2:0]
DEFAULT
000
2:0 OP6_DRV[2:0] 000
DESCRIPTION
CMOS output (OP8) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
CMOS output (OP7) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 11h CMOS drivability control 5
CMOS output (OP6) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
CMOS output (OP5) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
78
WM8235
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R18 (12h)
CMOS drivability control 6
BIT
6:4
2:0
LABEL
OP9_DRV[2:0]
OP8_DRV[2:0]
DEFAULT
000
000
DESCRIPTION
CMOS output (OP10) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
CMOS output (OP9) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 12h CMOS drivability control 6
REGISTER
ADDRESS
R19 (13h)
CMOS drivability control 7
BIT
6:4
LABEL
OC2_DRV[2:0]
DEFAULT
000
2:0 OC1_DRV[2:0] 000
DESCRIPTION
CMOS output (OC2) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
CMOS output (OC1) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 13h CMOS drivability control 7
REGISTER
ADDRESS
R20 (14h)
PG config
BIT
7
LABEL
PGMARCH
DEFAULT
0
DESCRIPTION
Rev 4.5
6:5
4
PGPAT[1:0]
PGINV
00
0 pattern generator marching mode enable
0 = controlled by PGPAT
1 = marching pattern select pattern generator output
00 = fixed value
01 = vertical ramp
10 = horizontal ramp
11 = patch invert pattern generator output
0 = normal
1 = invert
WM8235
REFER TO
REFER TO
REFER TO
79
WM8235
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION REFER TO
3
2
1
0
SEL_PGZ
SEL_PGY
SEL_PGX
PGEN
0
0
0
0 select output of pattern generator (IN7, IN8, IN9)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs select output of pattern generator (IN4, IN5, IN6)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs select output of pattern generator (IN1, IN2, IN3)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs enable pattern generator
0 = disable
1 = enable
Register 14h PG config
REGISTER
ADDRESS
R21 (15h)
PGCODE
LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
PGLEVEL[7:0] 0000_0000 parameter of pattern generator
Register 15h PGCODE LSB
REFER TO
REGISTER
ADDRESS
R22 (16h)
PGCODE
MSB
BIT
7:0
DEFAULT DESCRIPTION
PGLEVEL[7:0] 0000_0000 parameter of pattern generator
Register 16h PGCODE MSB
LABEL
REGISTER
ADDRESS
R23 (17h)
PG width 1
BIT LABEL DEFAULT DESCRIPTION
7:0 PGWIDTH1[7:0] 0000_0000 parameter of pattern generator
Register 17h PG width 1
REGISTER
ADDRESS
R24 (18h)
PG width 2
BIT LABEL DEFAULT DESCRIPTION
7:0 PGWIDTH2[7:0] 0000_0000 parameter of pattern generator
Register 18h PG width 2
REGISTER
ADDRESS
R25 (19h) clock monitor
BIT
2:0
LABEL
MONCLK[2:0]
DEFAULT
000
DESCRIPTION
80
select monitor output
0xx = Low (monitor disabled)
100 = RSMP
101 = VSMP
110 = ACLK
111 = OCLK
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
WM8235
Register 19h clock monitor
REGISTER
ADDRESS
R26 (1Ah)
PLL control 1
BIT
2
LABEL
PLL_LPF_RST
DEFAULT
0
1
0
PLL_CP_PD
PLL_VCO_PD
0
0
DESCRIPTION
Reset Loop Filter.
0 = normal
1 = reset power down Charge Pump.
0 = normal
1 = power down power down VCO
0 = normal
1 = power down
Register 1Ah PLL control 1
REGISTER
ADDRESS
R27 (1Bh)
PLL control 2
BIT
7
6
3:2
1:0
LABEL
PLL_LPF_SEL
PLL_LPF_SEL
PLL_PFD_
CTRL[1:0]
PLL_CP_
GAIN[1:0]
DEFAULT
0
0
10
01
DESCRIPTION
PLL_LPF_SEL[1] is unused.
Control Loop Filter to improve the performance.
Note: these settings are applicable for the specific conditions. x0 = normal filter x1 = larger resistor to improve PLL cutoff freq (for SSC)
PLL_LPF_SEL[1] is unused.
Control Loop Filter to improve the performance.
Note: these settings are applicable for the specific conditions. x0 = normal filter x1 = larger resistor to improve PLL cutoff freq (for SSC)
Control reset delay to improve PFD sensitivity.
00 = 1ns delay
01 = 2.2ns delay
10 = 3.4ns delay (default)
11 = 5.8ns delay
Control Charge Pump current.
00 = 0.5uA
01 = 1uA (default)
10 = 2uA
11 = 4uA
Register 1Bh PLL control 2
REGISTER
ADDRESS
R28 (1Ch)
PLL divider control 1
BIT
6:4
LABEL
PLL_EXDIV_
SEL[2:0]
DEFAULT
001
DESCRIPTION
Select EX DIV ratio.
Need to set according to input frequency. See details in
000 = 1
001 = 2
010 = 4
011 = 8
Rev 4.5
REFER TO
REFER TO
REFER TO
81
WM8235
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION REFER TO
3:0 PLL_FBDIV_
SEL[3:0]
Register 1Ch PLL divider control 1
REGISTER
ADDRESS
R29 (1Dh)
PLL divider control 2
BIT LABEL
5:4 PLL_POSTDIV2
_SEL[1:0]
DEFAULT
01
3:0 PLL_POSTDIV1
_SEL[3:0]
0100
DESCRIPTION
Select POST DIV2 ratio.
(Read Only)
00 = 1
01 = 2
10 = 4
11 = 6
Select POST DIV1 ratio. (Read Only)
0000 = 1
0001 = 2
0010 = 3
0011 = 4
0100 = 6
0101 = 8
0110 = 9
0111 = 12
1000 = 18
1001 to 1111 = reserved.
Register 1Dh PLL divider control 2
REGISTER
ADDRESS
R35 (23h)
Cycle mode control
BIT
3:2
LABEL
INTM[1:0]
0100
DEFAULT
00
100 = 16
101 to 111 = reserved.
Select FB DIV ratio. (ReadOnly)
0000 = 1
0001 = 2
0010 = 3
0011 = 4
0100 = 6
0101 = 8
0110 = 9
0111 = 12
1000 = 18
1001 to 1111 = reserved.
DESCRIPTION
82
1
0
ACYC
LINEBYLINE
0
0
REFER TO
REFER TO
When LINEBYLINE=1, controls the GAIN and DAC mux selector when ACYC=0
00 = IN7
01 = IN8
10 = IN9
11 = reserved when LINEBYLINE=1, determines the function of the MUX control
0 = decided by INTM register
1= auto-cycling enabled select line by line operation
0=normal operation
1=Line by Line operation
Rev 4.5
Register 23h cycle mode control
REGISTER
ADDRESS
R36 (24h)
DAC IN1
BIT
7:0
Register 24h DAC IN1
LABEL DEFAULT DESCRIPTION
DACIN1[7:0] 1000_0000 DACIN1offset value
250 * (DACIN1[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R37 (25h)
DAC IN2
BIT
7:0
Register 25h DAC IN2
LABEL DEFAULT DESCRIPTION
DACIN2[7:0] 1000_0000 DACIN2 offset value
250 * (DACIN2[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R38 (26h)
DAC IN3
BIT
7:0
Register 26h DAC IN3
LABEL DEFAULT DESCRIPTION
DACIN3[7:0] 1000_0000 DACIN3offset value
250 * (DACIN3[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R39 (27h)
DAC IN4
BIT
7:0
Register 27h DAC IN4
LABEL DEFAULT DESCRIPTION
DACIN4[7:0] 1000_0000 DACIN4offset value
250 * (DACIN4[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R40 (28h)
DAC IN5
BIT
7:0
Register 28h DAC IN5
LABEL DEFAULT DESCRIPTION
DACIN5[7:0] 1000_0000 DACIN5offset value
250 * (DACIN5[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R41 (29h)
DAC IN6
BIT
7:0
Register 29h DAC IN6
LABEL DEFAULT DESCRIPTION
DACIN6[7:0] 1000_0000 DACIN6 offset value
250 * (DACIN6[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R42 (2Ah)
DAC IN7
BIT
7:0
Register 2Ah DAC IN7
LABEL DEFAULT DESCRIPTION
DACIN7[7:0] 1000_0000 DACIN7offset value
250 * (DACIN7[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R43 (2Bh)
Rev 4.5
BIT
7:0
LABEL DEFAULT
DACIN8[7:0] 1000_0000 DACIN8offset value
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
83
REGISTER
ADDRESS
DAC IN8
BIT
Register 2Bh DAC IN8
LABEL DEFAULT DESCRIPTION
250 * (DACIN8[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R44 (2Ch)
DAC IN9
BIT
7:0
Register 2Ch DAC IN9
LABEL DEFAULT DESCRIPTION
DACIN9[7:0] 1000_0000 DACIN9offset value
250 * (DACIN9[7:0] -127.5) / 127.5 [mV]
REGISTER
ADDRESS
R45 (2Dh)
AGAIN IN1
BIT
4:0
Register 2Dh AGAIN IN1
LABEL
AGAININ1[4:0]
DEFAULT DESCRIPTION
0_0001 PGAIN1 gain control gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
REGISTER
ADDRESS
R46 (2Eh)
AGAIN IN2
BIT
4:0
Register 2Eh AGAIN IN2
LABEL
AGAININ2[4:0]
DEFAULT DESCRIPTION
0_0001 PGA IN2 gain code gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
REGISTER
ADDRESS
R47 (2Fh)
AGAIN IN3
BIT
4:0
Register 2Fh AGAIN IN3
LABEL
AGAININ3[4:0]
DEFAULT DESCRIPTION
0_0001 PGA IN3 gain code gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
REGISTER
ADDRESS
R48 (30h)
AGAIN IN4
BIT
4:0
Register 30h AGAIN IN4
LABEL
AGAININ4[4:0]
DEFAULT DESCRIPTION
0_0001 PGA IN4 gain code gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
REGISTER
ADDRESS
R49 (31h)
AGAIN IN5
BIT
4:0
Register 31h AGAIN IN5
LABEL
AGAININ5[4:0]
DEFAULT DESCRIPTION
0_0001 PGA IN5 gain code gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
REGISTER
ADDRESS
R50 (32h)
AGAIN IN6
BIT
4:0
Register 32h AGAIN IN6
LABEL
AGAININ6[4:0]
DEFAULT DESCRIPTION
0_0001
PGA IN6 gain code gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
84
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R51 (33h)
AGAIN IN7
BIT
4:0
Register 33h AGAIN IN7
LABEL
AGAININ7[4:0]
DEFAULT DESCRIPTION
0_0001
PGA IN7 gain code gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
REGISTER
ADDRESS
R52 (34h)
AGAIN IN8
BIT
4:0
Register 34h AGAIN IN8
LABEL
AGAININ8[4:0]
DEFAULT DESCRIPTION
0_0001 PGA IN8 gain code gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
REGISTER
ADDRESS
R53 (35h)
AGAIN IN9
BIT
4:0
Register 35h AGAIN IN9
LABEL
AGAININ9[4:0]
DEFAULT DESCRIPTION
0_0001 PGA IN9 gain code gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
REGISTER
ADDRESS
R54 (36h)
DGAIN IN1
LSB
BIT
7:4
LABEL
DGAININ1[3:0]
DEFAULT
0000
DESCRIPTION
lower bits of digital gain IN1 digital gain(V/V) = DGAIN[11:0]/2^11
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 36h DGAIN IN1 LSB
REGISTER
ADDRESS
R55 (37h)
DGAIN IN1
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ1[11:4] 1000_0000 upper bits of digital gain IN1
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 37h DGAIN IN1 MSB
REGISTER
ADDRESS
R56 (38h)
Rev 4.5
BIT
7:4
LABEL
DGAININ2[3:0]
DEFAULT
0000 lower bits of digital gain IN2
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
85
REGISTER
ADDRESS
DGAIN IN2
LSB
BIT LABEL DEFAULT DESCRIPTION
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 38h DGAIN IN2 LSB
REGISTER
ADDRESS
R57 (39h)
DGAIN IN2
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ2[11:4] 1000_0000 upper bits of digital gain IN2
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 39h DGAIN IN2 MSB
REGISTER
ADDRESS
R58 (3Ah)
DGAIN IN3
LSB
BIT
7:4
LABEL
DGAININ3[3:0]
DEFAULT
0000
DESCRIPTION
lower bits of digital gain IN3
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Ah DGAIN IN3 LSB
REGISTER
ADDRESS
R59 (3Bh)
DGAIN IN3
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ3[11:4] 1000_0000 upper bits of digital gain IN3
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Bh DGAIN IN3 MSB
86
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R60 (3Ch)
DGAIN IN4
LSB
BIT
7:4
LABEL
DGAININ4[3:0]
DEFAULT
0000
DESCRIPTION
lower bits of digital gain IN4
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Ch DGAIN IN4 LSB
REGISTER
ADDRESS
R61 (3Dh)
DGAIN IN4
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ4[11:4] 1000_0000 upper bits of digital gain IN4
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Dh DGAIN IN4 MSB
REGISTER
ADDRESS
R62 (3Eh)
DGAIN IN5
LSB
BIT
7:4
LABEL
DGAININ5[3:0]
DEFAULT
0000
DESCRIPTION
lower bits of digital gain IN5
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Eh DGAIN IN5 LSB
REGISTER
ADDRESS
R63 (3Fh)
DGAIN IN5
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ5[11:4] 1000_0000 upper bits of digital gain IN5
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Fh DGAIN IN5 MSB
Rev 4.5
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
87
REGISTER
ADDRESS
R64 (40h)
DGAIN IN6
LSB
BIT
7:4
LABEL
DGAININ6[3:0]
DEFAULT
0000
DESCRIPTION
lower bits of digital gain IN6
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 40h DGAIN IN6 LSB
REGISTER
ADDRESS
R65 (41h)
DGAIN IN6
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ6[11:4] 1000_0000 upper bits of digital gain IN6
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 41h DGAIN IN6 MSB
REGISTER
ADDRESS
R66 (42h)
DGAIN IN7
LSB
BIT
7:4
LABEL
DGAININ7[3:0]
DEFAULT
0000
DESCRIPTION
lower bits of digital gain IN7
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 42h DGAIN IN7 LSB
REGISTER
ADDRESS
R67 (43h)
DGAIN IN7
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ7[11:4] 1000_0000 upper bits of digital gain IN7
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 43h DGAIN IN7 MSB
88
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R68 (44h)
DGAIN IN8
LSB
BIT
7:4
LABEL
DGAININ8[3:0]
DEFAULT
0000
DESCRIPTION
lower bits of digital gain IN8
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 44h DGAIN IN8 LSB
REGISTER
ADDRESS
R69 (45h)
DGAIN IN8
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ8[11:4] 1000_0000 upper bits of digital gain IN8
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 45h DGAIN IN8 MSB
REGISTER
ADDRESS
R70 (46h)
DGAIN IN9
LSB
BIT
7:4
LABEL
DGAININ9[3:0]
DEFAULT
0000
DESCRIPTION
lower bits of digital gain IN9
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 46h DGAIN IN9 LSB
REGISTER
ADDRESS
R71 (47h)
DGAIN IN9
MSB
BIT LABEL DEFAULT DESCRIPTION
7:0 DGAININ9[11:4] 1000_0000 upper bits of digital gain IN9
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 47h DGAIN IN9 MSB
Rev 4.5
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
89
REGISTER
ADDRESS
R72 (48h)
BLC IN1
target
BIT LABEL DEFAULT DESCRIPTION
7:0 TARGETIN1[7:0
]
0000_0000 target black level for IN1
Register 48h BLC IN1 target
REGISTER
ADDRESS
R73 (49h)
BLC IN2 target
BIT LABEL DEFAULT DESCRIPTION
7:0 TARGETIN2[7:0
]
0000_0000 target black level for IN2
Register 49h BLC IN2 target
REGISTER
ADDRESS
R74 (4Ah)
BLC IN3 target
BIT LABEL DEFAULT DESCRIPTION
7:0 TARGETIN3[7:0
]
0000_0000 target black level for IN3
Register 4Ah BLC IN3 target
REGISTER
ADDRESS
R75 (4Bh)
BLC IN4 target
BIT
Register 4Bh BLC IN4 target
LABEL DEFAULT DESCRIPTION
7:0 TARGETIN4[7:0
]
0000_0000 target black level for IN4
REGISTER
ADDRESS
R76 (4Ch)
BLC IN5 target
BIT
Register 4Ch BLC IN5 target
LABEL DEFAULT DESCRIPTION
7:0 TARGETIN5[7:0
]
0000_0000 target black level for IN5
REGISTER
ADDRESS
R77 (4Dh)
BLC IN6 target
BIT
Register 4Dh BLC IN6 target
LABEL DEFAULT DESCRIPTION
7:0 TARGETIN6[7:0
]
0000_0000 target black level for IN6
REGISTER
ADDRESS
R78 (4Eh)
BLC IN7
target
BIT LABEL DEFAULT DESCRIPTION
7:0 TARGETIN7[7:0
]
0000_0000 target black level for IN7
Register 4Eh BLC IN7 target
90
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
WM8235
REGISTER
ADDRESS
R79 (4Fh)
BLC IN8 target
BIT LABEL DEFAULT DESCRIPTION
7:0 TARGETIN8[7:0
]
0000_0000 target black level for IN8
Register 4Fh BLC IN8 target
REGISTER
ADDRESS
R80 (50h)
BLC IN9 target
BIT LABEL DEFAULT DESCRIPTION
7:0 TARGETIN9[7:0
]
0000_0000 target black level for IN9
Register 50h BLC IN9 target
REFER TO
REFER TO
REGISTER
ADDRESS
R81 (51h)
BLC control 1
BIT
7
6
5
4
3
2:0
LABEL
FRAME_SEQ
FA_EVERYLINE
FA_ACCUM
FA_EN
CA_EVERYLIN
E
CADUR[2:0]
DEFAULT
0
0
0
0
0
000
DESCRIPTION
control frame sequence mode
0 = line by line
1 = frame sequence mode control fine adjustment
0 = Fine adjust only used on the 1st line of a frame
1 = Fine adjust used on every line of a frame makes the fine adjust calibration accumulate a result over multiple lines
0 = not accumulate
1 = accumulate enables the fine adjust operation
0 = disable
1 = enable control coarse ajustment
0 = Coarse adjust only used on the 1st line of a frame
1 = Coarse adjust used on every line of a frame controls the number of coarse adjust iterations to be perfomed
000 = disable
001 = 1time
010 = 2time
011 = 3time
…
111 = 7time
REFER TO
Register 51h BLC control 1
REGISTER
ADDRESS
R82 (52h)
BLC control 2
BIT
1
LABEL
SEQ_START
DEFAULT
0
Rev 4.5
0 FRAME_START 0
DESCRIPTION
register flag to indicate that the next start-of-line indicator is the first line of the first frame in a frame-sequence. This register is automatically set to zero at the end of the BLC operation on the first line
0 = no effect
1 = first frame of frame-sequence mode
Register flag to indicate that the next start-of-line indicator is the first line in a frame. This register is automatically set
REFER TO
91
WM8235
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION REFER TO
to zero at the end of the BLC operation on the first line
0 = no effect
1 = start of line
Register 52h BLC control 2
REGISTER
ADDRESS
R83 (53h)
BLC control 3
BIT LABEL DEFAULT DESCRIPTION
7:0 BPIX_AVAIL[7:0
]
0000_0000 LSBs of the number of black-pixels available over which to perform the coarse and/or fine adjust calibration
00_0000_0000 = no pixel available
11_1111_1111 = 1023 pixels
Register 53h BLC control 3
REFER TO
REGISTER
ADDRESS
R84 (54h)
BLC control
4
BIT LABEL
1:0 BPIX_AVAIL[9:8
]
DEFAULT
00
DESCRIPTION
MSBs of the number of black-pixels available over which to perform the coarse and/or fine adjust calibration
00_0000_0000 = no pixel available
11_1111_1111 = 1023 pixels
REFER TO
Register 54h BLC control 4
REGISTER
ADDRESS
R85 (55h)
BLC control 5
BIT
7:0
LABEL DEFAULT DESCRIPTION
LINE_DEL[7:0] 0000_0000 LSBs of the number of lines from the start of a frame to delay the start of BLC operation
0_0000_0000 = no delay
1_1111_1111 = 511 line
Register 55h BLC control 5
REGISTER
ADDRESS
R86 (56h)
BLC control 6
BIT
0
LABEL
LINE_DEL[8]
DEFAULT
0
DESCRIPTION
MSBs of the number of lines from the start of aframe to delay the start of BLC operation
0_0000_0000 = no delay
1_1111_1111 = 511 line
Register 56h BLC control 6
REFER TO
REFER TO
REGISTER
ADDRESS
R87 (57h)
AGC config 1
BIT
7:4
LABEL
AGCAVE[3:0]
DEFAULT
0000
DESCRIPTION REFER TO
92
averaging factor before peak detection
0000 = no average
0001 = 2
0010 = 4
0011 = 8
…
1010 = 1024
1011 = reserved
1100 = reserved
Rev 4.5
WM8235
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION REFER TO
2
1
0
AGC_ERRFLAG
AGC_ENDFLAG
AGC_EN
0
0
0
1101 = reserved
1110 = reserved
1111 = reserved
AGC error flag
0 = no error detected
1 = AGC finish with error
AGC end flag
0 = not end or not run
1 = AGC sequence was done
AGC enable
0 = disable
1 = enable
Register 57h AGC config 1
REGISTER
ADDRESS
R88 (58h)
AGC config 2
BIT
6:4
LABEL
AGC_DPD[2:0]
DEFAULT
000
2:0 AGC_APD[2:0] 000
DESCRIPTION
the number of peak detection iterations to calculate digital gain
000 = no digital gain adjustment
001 = 1line
010 = 2line
…
111 = 7line the number of peak detection iterations to calculate analogue gain
000 = no analogue gain adjustment
001 = 1line
010 = 2line
…
111 = 7line
REFER TO
Register 58h AGC config 2
REGISTER
ADDRESS
R89 (59h)
AGC target
IN1 LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
AGC_TARGET
IN1[7:0]
0000_0000 LSBs of AGC target level for IN1
Register 59h AGC target IN1 LSB
REGISTER
ADDRESS
R90 (5Ah)
AGC target
IN1 MSB
BIT
1:0
LABEL
AGC_TARGET
IN1[9:8]
Register 5Ah AGC target IN1 MSB
DEFAULT
00
DESCRIPTION
MSBs of AGC target level for IN1
REGISTER
ADDRESS
R91 (5Bh)
Rev 4.5
BIT
7:0
LABEL DEFAULT
AGC_TARGET 0000_0000 LSBs of AGC target level for IN2
DESCRIPTION
REFER TO
REFER TO
REFER TO
93
REGISTER
ADDRESS
AGC target
IN2 LSB
BIT LABEL
IN2[7:0]
Register 5Bh AGC target IN2 LSB
DEFAULT DESCRIPTION
REGISTER
ADDRESS
R92 (5Ch)
AGC target
IN2 MSB
BIT
1:0
LABEL
AGC_TARGET
IN2[9:8]
Register 5Ch AGC target IN2 MSB
DEFAULT
00
DESCRIPTION
LSBs of AGC target level for IN2
REGISTER
ADDRESS
R93 (5Dh)
AGC target
IN3 LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
AGC_TARGET
IN3[7:0]
0000_0000 LSBs of AGC target level for IN3
Register 5Dh AGC target IN3 LSB
REGISTER
ADDRESS
R94 (5Eh)
AGC target
IN3 MSB
BIT
1:0
LABEL
AGC_TARGET
IN3[9:8]
Register 5Eh AGC target IN3 MSB
DEFAULT
00
DESCRIPTION
MSBs of AGC target level for IN3
REGISTER
ADDRESS
R95 (5Fh)
AGC target
IN4 LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
AGC_TARGET
IN4[7:0]
0000_0000 LSBs of AGC target level for IN4
Register 5Fh AGC target IN4 LSB
REGISTER
ADDRESS
R96 (60h)
AGC target
IN4 MSB
BIT
1:0
LABEL
AGC_TARGET
IN4[9:8]
Register 60h AGC target IN4 MSB
DEFAULT
00
DESCRIPTION
MSBs of AGC target level for IN4
REGISTER
ADDRESS
R97 (61h)
AGC target
IN5 LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
AGC_TARGET
IN5[7:0]
0000_0000 LSBs of AGC target level for IN5
Register 61h AGC target IN5 LSB
94
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R98 (62h)
AGC target
IN5 MSB
BIT
1:0
LABEL
AGC_TARGET
IN5[9:8]
Register 62h AGC target IN5 MSB
DEFAULT
00
DESCRIPTION
MSBs of AGC target level for IN5
REGISTER
ADDRESS
R99 (63h)
AGC target
IN6 LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
AGC_TARGET
IN6[7:0]
0000_0000 LSBs of AGC target level for IN6
Register 63h AGC target IN6 LSB
REGISTER
ADDRESS
R100 (64h)
AGC target
IN6 MSB
BIT
1:0
LABEL
AGC_TARGET
IN6[9:8]
Register 64h AGC target IN6 MSB
DEFAULT
00
DESCRIPTION
MSBs of AGC target level for IN6
REGISTER
ADDRESS
R101 (65h)
AGC target
IN7 LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
AGC_TARGET
IN7[7:0]
0000_0000 LSBs of AGC target level for IN7
Register 65h AGC target IN7 LSB
REGISTER
ADDRESS
R102 (66h)
AGC target
IN7 MSB
BIT
1:0
LABEL
AGC_TARGET
IN7[9:8]
Register 66h AGC target IN7 MSB
DEFAULT
00
DESCRIPTION
MSBs o AGC target level for IN7
REGISTER
ADDRESS
R103 (67h)
AGC target
IN8 LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
AGC_TARGET
IN8[7:0]
0000_0000 LSBs of AGC target level for IN8
Register 67h AGC target IN8 LSB
REGISTER
ADDRESS
R104 (68h)
AGC target
IN8 MSB
BIT
1:0
LABEL
AGC_TARGET
IN8[9:8]
DEFAULT
00
DESCRIPTION
MSBs of AGC target level for IN8
Rev 4.5
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
95
Register 68h AGC target IN8 MSB
REGISTER
ADDRESS
R105 (69h)
AGC target
IN9 LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
AGC_TARGET
IN9[7:0]
0000_0000 LSBs of AGC target level for IN9
Register 69h AGC target IN9 LSB
REGISTER
ADDRESS
R106 (6Ah)
AGC target
IN9 MSB
BIT
1:0
LABEL
AGC_TARGET
IN9[9:8]
Register 6Ah AGC target IN9 MSB
DEFAULT
00
DESCRIPTION
MSBs of AGC target level for IN9
REGISTER
ADDRESS
R107 (6Bh)
AGC peak level IN1
LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
PEAK_IN1[7:0] 0000_0000 LSBs of detected peak level of IN1 (Read Only)
Register 6Bh AGC peak level IN1 LSB
REGISTER
ADDRESS
R108 (6Ch)
AGC peak level IN1
MSB
BIT
1:0
LABEL
PEAK_IN1[9:8]
Register 6Ch AGC peak level IN1 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN1 (Read Only)
REGISTER
ADDRESS
R109 (6Dh)
AGC peak level IN2
LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
PEAK_IN2[7:0] 0000_0000 LSBs of detected peak level of IN2 (Read Only)
Register 6Dh AGC peak level IN2 LSB
REGISTER
ADDRESS
R110 (6Eh)
AGC peak level IN2
MSB
BIT
1:0
LABEL
PEAK_IN2[9:8]
Register 6Eh AGC peak level IN2 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN2 (Read Only)
96
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R111 (6Fh)
AGC peak level IN3
LSB
BIT
7:0
LABEL
PEAK_IN3[7:0]
Register 6Fh AGC peak level IN3 LSB
DEFAULT DESCRIPTION
0000_0000 LSBs of detected peak level of IN3 (Read Only)
REGISTER
ADDRESS
R112 (70h)
AGC peak level IN3
MSB
BIT
1:0
LABEL
PEAK_IN3[9:8]
Register 70h AGC peak level IN3 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN3 (Read Only)
REGISTER
ADDRESS
R113 (71h)
AGC peak
level IN4
LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
PEAK_IN4[7:0] 0000_0000 LSBs of detected peak level of IN4 (Read Only)
Register 71h AGC peak level IN4 LSB
REGISTER
ADDRESS
R114 (72h)
AGC peak
level IN4
MSB
BIT
1:0
LABEL
PEAK_IN4[9:8]
Register 72h AGC peak level IN4 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN4 (Read Only)
REGISTER
ADDRESS
R115 (73h)
AGC peak level IN5
LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
PEAK_IN5[7:0] 0000_0000 LSBs of detected peak level of IN5 (Read Only)
Register 73h AGC peak level IN5 LSB
REGISTER
ADDRESS
R116 (74h)
AGC peak level IN5
MSB
BIT
1:0
LABEL
PEAK_IN5[9:8]
Register 74h AGC peak level IN5 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN5 (Read Only)
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
97
REGISTER
ADDRESS
R117 (75h)
AGC peak
level IN6
LSB
BIT
7:0
LABEL
PEAK_IN6[7:0]
Register 75h AGC peak level IN6 LSB
DEFAULT DESCRIPTION
0000_0000 LSBs of detected peak level of IN6 (Read Only)
REGISTER
ADDRESS
R118 (76h)
AGC peak level IN6
MSB
BIT
1:0
LABEL
PEAK_IN6[9:8]
Register 76h AGC peak level IN6 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN6 (Read Only)
REGISTER
ADDRESS
R119 (77h)
AGC peak level IN7
LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
PEAK_IN7[7:0] 0000_0000 LSBs of detected peak level of IN7 (Read Only)
Register 77h AGC peak level IN7 LSB
REGISTER
ADDRESS
R120 (78h)
AGC peak
level IN7
MSB
BIT
1:0
LABEL
PEAK_IN7[9:8]
Register 78h AGC peak level IN7 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN7 (Read Only)
REGISTER
ADDRESS
R121 (79h)
AGC peak level IN8
LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
PEAK_IN8[7:0] 0000_0000 LSBs of detected peak level of IN8 (Read Only)
Register 79h AGC peak level IN8 LSB
REGISTER
ADDRESS
R122 (7Ah)
AGC peak
level IN8
MSB
BIT
1:0
LABEL
PEAK_IN8[9:8]
Register 7Ah AGC peak level IN8 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN8 (Read Only)
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
98 Rev 4.5
WM8235
REFER TO REGISTER
ADDRESS
R123 (7Bh)
AGC peak level IN9
LSB
BIT
7:0
LABEL
PEAK_IN9[7:0]
Register 7Bh AGC peak level IN9 LSB
DEFAULT DESCRIPTION
0000_0000 LSBs of detected peak level of IN9 (Read Only)
REGISTER
ADDRESS
R124 (7Ch)
AGC peak level IN9
MSB
BIT
1:0
LABEL
PEAK_IN9[9:8]
Register 7Ch AGC peak level IN9 MSB
DEFAULT
00
DESCRIPTION
MSBs of detected peak level of IN9 (Read Only)
REGISTER
ADDRESS
R128 (80h)
DLL config 1
BIT
5:4
LABEL
DLGAIN[1:0]
DEFAULT
10
DESCRIPTION
2
1
0
DLLRST
CKOSTB
AFECKSTB
0
0
0 gain control of DLL delay line
Need to set according to input frequency. See details in
reset DLL delay line
0 = normal
1= reset DLL standby TG clock output
0 = generate TG clock
1 = stop generation of TG clock standby AFE clock (VSMP/RSMP/ADCK) output
0 = generate AFE clock
1 = stop generation of AFE clock
Register 80h DLL config 1
REGISTER
ADDRESS
R129 (81h)
DLL config 2
BIT
5:4
LABEL
LVDLGAIN[1:0]
DEFAULT
01
1
0
LVDLLRST
LVDLLSTB
0
0
DESCRIPTION
gain control of LVDS DLL delay line
Need to set according to input frequency. See details in
reset LVDS DLL delay line
0 = normal
1 = reset LVDS DLL standby LVDS serializer clock generation
0 = generate LVDS serializer clock
1 = stop generation of LVDS serializer clock
Register 81h DLL config 2
REGISTER
ADDRESS
R130 (82h)
RSMP rise
BIT
5:0
LABEL
RSMP_RISE
[5:0]
DEFAULT DESCRIPTION
Rev 4.5
01_1100 RSMP rise edge
00_0000 = tap0
00_0001 = tap1
…
REFER TO
REFER TO
REFER TO
REFER TO
99
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
Register 82h RSMP rise
REGISTER
ADDRESS
R131 (83h)
RSMP fall
BIT
5:0
LABEL
RSMP_FALL
[5:0]
DEFAULT
10_0110
RSMP fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
DESCRIPTION
Register 83h RSMP fall
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
REGISTER
ADDRESS
R132 (84h)
VSMP rise
BIT
5:0
LABEL
VSMP_RISE
[5:0]
DEFAULT
00_0000 VSMP rise edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
DESCRIPTION
Register 84h VSMP rise
REGISTER
ADDRESS
R133 (85h)
VSMP fall
BIT
5:0
LABEL
VSMP_FALL
[5:0]
DEFAULT
00_1000 VSMP fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
DESCRIPTION
Register 85h VSMP fall
REGISTER
ADDRESS
R134 (86h)
100
BIT
5:0
LABEL
TCLKO_RISE
DEFAULT
11_0111
TCLKO rise edge
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
TGCKO rise
BIT LABEL DEFAULT DESCRIPTION
[5:0]
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 86h TGCKO rise
REGISTER
ADDRESS
R135 (87h)
CLK1 rise
BIT LABEL DEFAULT
5:0 CLK1_RISE[5:0] 00_1010 CLK1 rise edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 87h CLK1 rise
DESCRIPTION
REGISTER
ADDRESS
R136 (88h)
CLK1 fall
BIT LABEL DEFAULT
5:0 CLK1_FALL[5:0] 01_1001 CLK1 fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 88h CLK1 fall
DESCRIPTION
REGISTER
ADDRESS
R137 (89h)
CLK2 rise
BIT LABEL DEFAULT
5:0 CLK2_RISE[5:0] 01_1001 CLK2 rise edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 89h CLK2 rise
DESCRIPTION
Rev 4.5
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
101
REGISTER
ADDRESS
R138 (8Ah)
CLK2fall
BIT LABEL DEFAULT
5:0 CLK2_FALL[5:0] 10_1000
CLK2 fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Ah CLK2fall
DESCRIPTION
REGISTER
ADDRESS
R139 (8Bh)
CLK3 rise
BIT LABEL DEFAULT
5:0 CLK3_RISE[5:0] 10_1000 CLK3 rise edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Bh CLK3 rise
DESCRIPTION
REGISTER
ADDRESS
R140 (8Ch)
CLK3 fall
BIT LABEL DEFAULT
5:0 CLK3_FALL[5:0] 00_1010 CLK3 fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Ch CLK3 fall
DESCRIPTION
REGISTER
ADDRESS
R141 (8Dh)
CLK4 rise
BIT LABEL DEFAULT
5:0 CLK4_RISE[5:0] 00_0000
CLK4 rise edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Dh CLK4 rise
DESCRIPTION
102
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R142 (8Eh)
CLK4 fall
BIT LABEL DEFAULT
5:0 CLK4_FALL[5:0] 00_0000
CLK4 fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Eh CLK4 fall
DESCRIPTION
REGISTER
ADDRESS
R143 (8Fh)
CLK5 rise
BIT LABEL DEFAULT
5:0 CLK5_RISE[5:0] 00_1010 CLK5 rise edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Fh CLK5 rise
DESCRIPTION
REGISTER
ADDRESS
R144 (90h)
CLK5 fall
BIT LABEL DEFAULT
5:0 CLK5_FALL[5:0] 10_1000 CLK5 fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 90h CLK5 fall
DESCRIPTION
REGISTER
ADDRESS
R145 (91h)
CLK6 rise
BIT LABEL DEFAULT
5:0 CLK6_RISE[5:0] 00_1010
CLK6 rise edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 91h CLK6 rise
Rev 4.5
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
103
WM8235
REGISTER
ADDRESS
R146 (92h)
CLK6 fall
BIT LABEL DEFAULT
5:0 CLK6_FALL[5:0] 10_1000
CLK6 fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 92h CLK6 fall
DESCRIPTION
REGISTER
ADDRESS
R160 (A0h)
TG config 1
BIT
7:4
3
2
1
0
LABEL
OFFSET[3:0]
CYCMD
POLSYNC
TGMD
TG_EN
DEFAULT
0000
0
0
0
0
DESCRIPTION
pixel counter offset (valid only in slave mode) cycle mode enable
0 = normal (same operation at everyline)
1 = cycle mode polarity of tgync signal
0 = reset pixel counter at positive edge of tgsync
1 = reset pixel counter at negative edge of tgsync
TG operation mode
0 = slave
1 = master
TG enable
0 = disable
1 = enable
Register A0h TG config 1
REGISTER
ADDRESS
R161 (A1h)
TG config 2
BIT
7:0
Register A1h TG config 2
LABEL DEFAULT DESCRIPTION
LLENGTH[7:0] 0000_0000 LSBs of LLENGTH[14:0] the number of pixels in a line (valid only in master mode)
REFER TO
REFER TO
REFER TO
REGISTER
ADDRESS
R162 (A2h)
TG config 3
BIT LABEL DEFAULT DESCRIPTION
6:0 LLENGTH[14:8] 000_0000 MSBs of LLENGTH the number of pixels in a line (valid only in master mode)
Register A2h TG config 3
REGISTER
ADDRESS
R163 (A3h)
TG config 4
BIT
7:0
Register A3h TG config 4
LABEL DEFAULT DESCRIPTION
FLAGPIX[7:0] 0000_0000 LSBs of FLAGPIX[14:0] flag pixel control pulse flagpix is high when pixel counter equals to flagpix[14:0]
104
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R164 (A4h)
TG config 5
BIT
6:0
Register A4h TG config 5
LABEL DEFAULT DESCRIPTION
FLAGPIX[14:8] 000_0000
MSBs of FLAGPIX[14:0] flag pixel control pulse flagpix is high when pixel counter equals to flagpix[14:0]
REGISTER
ADDRESS
R165 (A5h)
TG config 6
BIT
7
LABEL
OE_CLK8
DEFAULT
1
DESCRIPTION
6
5
4
3
2
1
0
OE_CLK7
OE_CLK6
OE_CLK5
OE_CLK4
OE_CLK3
OE_CLK2
OE_CLK1
1
1
1
1
1
1
1 output enable of "CLK8"
0 = Hi-Z
1 = output output enable of "CLK7"
0 = Hi-Z
1 = output output enable of "CLK6"
0 = Hi-Z
1 = output output enable of "CLK5"
0 = Hi-Z
1 = output output enable of "CLK4"
0 = Hi-Z
1 = output output enable of "CLK3"
0 = Hi-Z
1 = output output enable of "CLK2"
0 = Hi-Z
1 = output output enable of "CLK1"
0 = Hi-Z
1 = output
Register A5h TG config 6
REGISTER
ADDRESS
R167 (A7h)
TG config 8
BIT
7
LABEL
INV_CLK8
DEFAULT
0
DESCRIPTION
Rev 4.5
6
5
4
3
INV_CLK7
INV_CLK6
INV_CLK5
INV_CLK4
0
0
0
0 invert signal output assigned to CLK8
0 = non-inverted
1 = inverted invert signal output assigned to CLK7
0 = non-inverted
1 = inverted invert signal output assigned to CLK6
0 = non-inverted
1 = inverted invert signal output assigned to CLK5
0 = non-inverted
1 = inverted invert signal output assigned to CLK4
0 = non-inverted
WM8235
REFER TO
REFER TO
105
REFER TO
REGISTER
ADDRESS
BIT
2
1
0
LABEL
INV_CLK3
INV_CLK2
INV_CLK1
DEFAULT
0
0
0
DESCRIPTION
1 = inverted invert signal output assigned to CLK3
0 = non-inverted
1 = inverted invert signal output assigned to CLK2
0 = non-inverted
1 = inverted invert signal output assigned to CLK1
0 = non-inverted
1 = inverted
Register A7h TG config 8
REGISTER
ADDRESS
R169 (A9h)
TG config 10
BIT
7
LABEL
EN_CLK8
DEFAULT DESCRIPTION
6
5
4
3
2
1
0
EN_CLK7
EN_CLK6
EN_CLK5
EN_CLK4
EN_CLK3
EN_CLK2
EN_CLK1
0
0
0
0
0
0
0
0 enable signal output CLK8
0 = disable
1 = enable enable signal output CLK7
0 = disable
1 = enable enable signal output CLK6
0 = disable
1 = enable enable signal output CLK5
0 = disable
1 = enable enable signal output CLK4
0 = disable
1 = enable enable signal output CLK3
0 = disable
1 = enable enable signal output CLK2
0 = disable
1 = enable enable signal output CLK1
0 = disable
1 = enable
Register A9h TG config 10
REGISTER
ADDRESS
R171 (ABh)
TG config 12
BIT
7
106
LABEL
SEL_CLK3
6:4 SEL_PCK3[2:0]
DEFAULT
0
000
DESCRIPTION
select signal for CLK3
0 = output clock
1 = output pulse (select by SEL_PCK3[2:0]) select pulse assigned to CLK3 (valid only when
SEL_CLK3=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
WM8235
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
3 SEL_CLK2
2:0 SEL_PCK2[2:0]
Register ACh TG config 13
REGISTER
ADDRESS
BIT LABEL
0
000
Register ABh TG config 12
REGISTER
ADDRESS
R172 (ACh)
TG config 13
BIT
7
LABEL
SEL_CLK5
6:4 SEL_PCK5[2:0]
3 SEL_CLK4
2:0 SEL_PCK4[2:0]
DEFAULT
0
000
0
000
DESCRIPTION
select signal for CLK5
0 = output clock
1 = output pulse (select by SEL_PCK5[2:0]) select pulse assigned to CLK5 (valid only when
SEL_CLK5=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7 select signal for CLK4
0 = output clock
1 = output pulse (select by SEL_PCK4[2:0]) select pulse assigned to CLK4 (valid only when
SEL_CLK4=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
DEFAULT
100 = PO4
101 = PO5
110 = PO6
111 = PO7 select signal for CLK2
0 = output clock
1 = output pulse (select by SEL_PCK2[2:0]) select pulse assigned to CLK2 (valid only when
SEL_CLK2=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
DESCRIPTION
Rev 4.5
WM8235
REFER TO
REFER TO
REFER TO
107
REGISTER
ADDRESS
R173 (ADh)
TG config 14
BIT
6:4
LABEL
SEL_PCK7[2:0]
DEFAULT
000
3
2:0
SEL_CLK6
SEL_PCK6[2:0]
0
000
DESCRIPTION
select pulse assigned to CLK7
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7 select signal for CLK6
0 = output clock
1 = output pulse (select by SEL_PCK6[2:0]) select pulse assigned to CLK6 (valid only when
SEL_CLK6=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
Register ADh TG config 14
REGISTER
ADDRESS
R174 (AEh)
TG config 15
BIT LABEL
2:0 SEL_PCK8[2:0]
DEFAULT
000
DESCRIPTION
select pulse assigned to CLK8
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
Register AEh TG config 15
REGISTER
ADDRESS
R176 (B0h)
TG config 17
BIT LABEL
7:6 DEL_PCK5[1:0]
DEFAULT
00
5:4 DEL_PCK4[1:0]
3:2 DEL_PCK3[1:0]
00
00
DESCRIPTION
control delay of pulse output assigned to CLK5
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec control delay of pulse output assigned to CLK4
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec control delay of pulse output assigned to CLK3
00 = 0nsec
01 = 1nsec
108
WM8235
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
1:0 DEL_PCK2[1:0] 00
10 = 2nsec
11 = 3nsec control delay of pulse output assigned to CLK2
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec
Register B0h TG config 17
REGISTER
ADDRESS
R177 (B1h)
TG config 18
BIT LABEL
5:4 DEL_PCK8[1:0]
DEFAULT
00
3:2 DEL_PCK7[1:0]
1:0 DEL_PCK6[1:0]
00
00
DESCRIPTION
control delay of pulse output assigned to CLK8
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec control delay of pulse output assigned to CLK7
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec control delay of pulse output assigned to CLK6
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec
Register B1h TG config 18
REGISTER
ADDRESS
R179 (B3h)
TG config 20
BIT
4
3
2
1
0
LABEL
INV_M3
INV_M2
INV_M1
INV_T2
INV_T1
DEFAULT
0
0
0
0
0
DESCRIPTION
invert mask pulse "M3"
0 = non-inverted
1 = inverted invert mask pulse "M2"
0 = non-inverted
1 = inverted invert mask pulse "M1"
0 = non-inverted
1 = inverted invert toggle pulse "T2"
0 = non-inverted
1 = inverted invert toggle pulse "T1"
0 = non-inverted
1 = inverted
Register B3h TG config 20
REGISTER
ADDRESS
BIT LABEL
R180 (B4h) 3:0 SEL_FLAG[3:0]
Rev 4.5
DEFAULT
0000
DESCRIPTION
select signal to be output as datatrig
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
109
REGISTER
ADDRESS
TG config 21
BIT LABEL DEFAULT DESCRIPTION
0xxx = flagpix
1000 = PO0
1001 = PO1
1010 = PO2
1011 = PO3
1100 = PO4
1101 = PO5
1110 = PO6
1111 = PO7
Register B4h TG config 21
REGISTER
ADDRESS
R181 (B5h)
TG config 22
BIT
6:4
2:0
LABEL
CYCPAT_PO1
[2:0]
CYCPAT_PO0
[2:0]
DEFAULT
000
000
DESCRIPTION
PO1 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
PO0 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Register B5h TG config 22
REGISTER
ADDRESS
R182 (B6h)
TG config 23
BIT
6:4
LABEL
CYCPAT_PO3
[2:0]
DEFAULT
000
2:0 CYCPAT_PO2
[2:0]
000
DESCRIPTION
PO3 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
PO2 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Register B6h TG config 23
REGISTER
ADDRESS
R183 (B7h)
TG config 24
BIT
6:4
LABEL
CYCPAT_PO5
[2:0]
DEFAULT
000
2:0 CYCPAT_PO4
[2:0]
000
DESCRIPTION
PO5 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
PO4 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Register B7h TG config 24
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
110
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R184 (B8h)
TG config 25
BIT
6:4
LABEL
CYCPAT_PO7
[2:0]
DEFAULT
000
2:0 CYCPAT_PO6
[2:0]
000
DESCRIPTION
PO7 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
PO6 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Register B8h TG config 25
REGISTER
ADDRESS
R185 (B9h) clamp enable rise LSB
BIT
7:0
LABEL
CLAMP_RISE
[7:0]
Register B9h clamp enable rise LSB
DEFAULT DESCRIPTION
0000_0000 LSBs of CLAMP_RISE clamp enable pulse rise pixel
REGISTER
ADDRESS
R186 (BAh) clamp enable rise MSB
BIT
6:0
LABEL
CLAMP_RISE
[14:8]
Register BAh clamp enable rise MSB
DEFAULT DESCRIPTION
000_0000 MSBs of CLAMP_RISE clamp enable pulse rise pixel
REGISTER
ADDRESS
R187 (BBh) clamp enable fall LSB
BIT
7:0
LABEL
CLAMP_FALL
[7:0]
Register BBh clamp enable fall LSB
DEFAULT DESCRIPTION
0000_0000 LSBs of CLAMP_FALL clamp enable pulse fall pixel
REGISTER
ADDRESS
R188 (BCh) clamp enable fall MSB
BIT
6:0
LABEL
CLAMP_FALL
[14:8]
Register BCh clamp enable fall MSB
DEFAULT DESCRIPTION
000_0000
MSBs of CLAMP_FALL clamp enable pulse fall pixel
REGISTER
ADDRESS
R189 (BDh)
OB start
LSB
BIT LABEL DEFAULT DESCRIPTION
7:0 OB_START[7:0] 0000_0000 LSBs of OB_START optical black calibration start pixel count
Register BDh OB start LSB
REGISTER
ADDRESS
Rev 4.5
BIT LABEL DEFAULT DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
111
REGISTER
ADDRESS
R190 (BEh)
OB start
MSB
BIT
6:0
Register BEh OB start MSB
LABEL
OB_START
[14:8]
DEFAULT
000_0000
MSBs of OB_START
DESCRIPTION
optical black calibration start pixel count
REGISTER
ADDRESS
R191 (BFh) peak_det rise
LSB
BIT
7:0
LABEL
PEAKDET_RIS
E
[7:0]
Register BFh peak_det rise LSB
DEFAULT DESCRIPTION
0000_0000 LSBs of PEAKDET_RISE[14:0] peak detection start pixel count
REGISTER
ADDRESS
R192 (C0h) peak_det rise
MSB
BIT
6:0
LABEL
PEAKDET_RIS
E
[14:8]
Register C0h peak_det rise MSB
DEFAULT DESCRIPTION
000_0000 MSBs of PEAKDET_RISE[14:0] peak detection start pixel count
REGISTER
ADDRESS
R193 (C1h) peak_det fall
LSB
BIT LABEL
7:0 PEAKDET_FAL
L
[7:0]
Register C1h peak_det fall LSB
DEFAULT DESCRIPTION
0000_0000 LSBs of PEAKDET_FALL[14:0] peak detection end pixel count
REGISTER
ADDRESS
R194 (C2h) peak_det fall
MSB
BIT LABEL
6:0 PEAKDET_FAL
L
[14:8]
Register C2h peak_det fall MSB
DEFAULT DESCRIPTION
000_0000 MSBs of PEAKDET_FALL[14:0] peak detection end pixel count
REGISTER
ADDRESS
R195 (C3h)
Mask pulse 1 rise LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
M1_RISE[7:0] 0000_0000 LSBs of M1_RISE[14:0] mask pulse "M1" rise pixel count
Register C3h Mask pulse 1 rise LSB
REGISTER
ADDRESS
R196 (C4h)
Mask pulse 1 rise MSB
BIT
6:0
LABEL DEFAULT DESCRIPTION
M1_RISE[14:8] 000_0000 MSBs of M1_RISE[14:0] mask pulse "M1" rise pixel count
Register C4h Mask pulse 1 rise MSB
112
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R197 (C5h)
Mask pulse 1 fall LSB
BIT
7:0
LABEL
M1_FALL[7:0]
Register C5h Mask pulse 1 fall LSB
DEFAULT DESCRIPTION
0000_0000 LSBs of M1_FALL[14:0] mask pulse "M1" fall pixel count
REGISTER
ADDRESS
R198 (C6h)
Mask pulse 1 fall MSB
BIT
6:0
LABEL DEFAULT DESCRIPTION
M1_FALL[14:8] 000_0000 MSBs of M1_FALL[14:0] mask pulse "M1" fall pixel count
Register C6h Mask pulse 1 fall MSB
REGISTER
ADDRESS
R199 (C7h)
Mask pulse 2 rise LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
M2_RISE[7:0] 0000_0000 LSBs of M2_RISE[14:0] mask pulse "M2" rise pixel count
Register C7h Mask pulse 2 rise LSB
REGISTER
ADDRESS
R200 (C8h)
Mask pulse 2 rise MSB
BIT
6:0
LABEL DEFAULT DESCRIPTION
M2_RISE[14:8] 000_0000 MSBs of M2_RISE[14:0] mask pulse "M2" rise pixel count
Register C8h Mask pulse 2 rise MSB
REGISTER
ADDRESS
R201 (C9h)
Mask pulse 2 fall LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
M2_FALL[7:0] 0000_0000 LSBs of M2_FALL[14:0] mask pulse "M2" fall pixel count
Register C9h Mask pulse 2 fall LSB
REGISTER
ADDRESS
R202 (CAh)
Mask pulse 2 fall MSB
BIT
6:0
LABEL DEFAULT DESCRIPTION
M2_FALL[14:8] 000_0000
MSBs of M2_FALL[14:0] mask pulse "M2" fall pixel count
Register CAh Mask pulse 2 fall MSB
REGISTER
ADDRESS
R203 (CBh)
Mask pulse 3 rise LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
M3_RISE[7:0] 0000_0000 LSBs of M3_RISE mask pulse "M3" rise pixel count
Register CBh Mask pulse 3 rise LSB
Rev 4.5
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
113
REGISTER
ADDRESS
R204 (CCh)
Mask pulse 3 rise MSB
BIT
6:0
LABEL
M3_RISE[14:8]
Register CCh Mask pulse 3 rise MSB
DEFAULT
000_0000
MSBs of M3_RISE
DESCRIPTION
mask pulse "M3" rise pixel count
REGISTER
ADDRESS
R205 (CDh)
Mask pulse 3 fall LSB
BIT
7:0
LABEL DEFAULT DESCRIPTION
M3_FALL[7:0] 0000_0000 LSBs of M3_FALL mask pulse "M3" fall pixel count
Register CDh Mask pulse 3 fall LSB
REGISTER
ADDRESS
R206 (CEh)
Mask pulse 3 fall MSB
BIT
6:0
LABEL DEFAULT DESCRIPTION
M3_FALL[14:8] 000_0000 MSBs of M3_FALL mask pulse "M3" fall pixel count
Register CEh Mask pulse 3 fall MSB
REGISTER
ADDRESS
R207 (CFh)
Toggle point
0 LSB
BIT
7:0
LABEL
TP0[7:0]
Register CFh Toggle point 0 LSB
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP0"
REGISTER
ADDRESS
R208 (D0h)
Toggle point
0 MSB
BIT
7
LABEL
GEN_TP0
6:0 TP0[14:8]
Register D0h Toggle point 0 MSB
DEFAULT DESCRIPTION
0 global enable of toggle point
0 = disable all toggle point
1 = enable toggle point "TP0"
000_0000 pixel count of toggle point "TP0
REGISTER
ADDRESS
R209 (D1h)
Toggle point
1 LSB
BIT
7:0
LABEL
TP1[7:0]
Register D1h Toggle point 1 LSB
REGISTER
ADDRESS
R210 (D2h)
Toggle point
1 MSB
BIT
7
6:0
114
LABEL
EN_TP1
TP1[14:8]
DEFAULT
0000_0000 pixel count of toggle point "TP1"
DEFAULT
0 enable toggle point "TP1"
0 = disable "TP1" and all subsequent toggle point
1 = enable toggle point "TP1"
000_0000 pixel count of toggle point "TP1"
DESCRIPTION
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
Register D2h Toggle point 1 MSB
REGISTER
ADDRESS
R211 (D3h)
Toggle point
2 LSB
BIT
7:0
LABEL
TP2[7:0]
Register D3h Toggle point 2 LSB
REGISTER
ADDRESS
R212 (D4h)
Toggle point
2 MSB
BIT
7
LABEL
EN_TP2
6:0 TP2[14:8]
Register D4h Toggle point 2 MSB
REGISTER
ADDRESS
R213 (D5h)
Toggle point
3 LSB
BIT
7:0
LABEL
TP3[7:0]
Register D5h Toggle point 3 LSB
REGISTER
ADDRESS
R214 (D6h)
Toggle point
3 MSB
BIT
7
LABEL
EN_TP3
6:0 TP3[14:8]
Register D6h Toggle point 3 MSB
REGISTER
ADDRESS
R215 (D7h)
Toggle point
4 LSB
BIT
7:0
LABEL
TP4[7:0]
Register D7h Toggle point 4 LSB
REGISTER
ADDRESS
R216 (D8h)
Toggle point
4 MSB
BIT
7
LABEL
EN_TP4
6:0 TP4[14:8]
Register D8h Toggle point 4 MSB
Rev 4.5
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP2"
DEFAULT DESCRIPTION
0 enable toggle point "TP2"
0 = disable "TP2" and all subsequent toggle point
1 = enable toggle point "TP2"
000_0000 pixel count of toggle point "TP2"
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP3"
DEFAULT DESCRIPTION
0 enable toggle point "TP3"
0 = disable "TP3" and all subsequent toggle point
1 = enable toggle point "TP3"
000_0000 pixel count of toggle point "TP3"
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP4"
DEFAULT DESCRIPTION
0 enable toggle point "TP4"
0 = disable "TP4" and all subsequent toggle point
1 = enable toggle point "TP4"
000_0000 pixel count of toggle point "TP4"
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
115
REGISTER
ADDRESS
R217 (D9h)
Toggle point
5 LSB
BIT
7:0
LABEL
TP5[7:0]
Register D9h Toggle point 5 LSB
REGISTER
ADDRESS
R218 (DAh)
Toggle point
5 MSB
BIT
7
LABEL
EN_TP5
6:0 TP5[14:8]
Register DAh Toggle point 5 MSB
REGISTER
ADDRESS
R219 (DBh)
Toggle point
6 LSB
BIT
7:0
LABEL
TP6[7:0]
Register DBh Toggle point 6 LSB
REGISTER
ADDRESS
R220 (DCh)
Toggle point
6 MSB
BIT
7
LABEL
EN_TP6
6:0 TP6[14:8]
Register DCh Toggle point 6 MSB
REGISTER
ADDRESS
R221 (DDh)
Toggle point
7 LSB
BIT
7:0
LABEL
TP7[7:0]
Register DDh Toggle point 7 LSB
REGISTER
ADDRESS
R222 (DEh)
Toggle point
7 MSB
BIT
7
LABEL
EN_TP7
6:0 TP7[14:8]
Register DEh Toggle point 7 MSB
REGISTER
ADDRESS
R223 (DFh)
116
BIT
7:0
LABEL
TP8[7:0]
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP5"
DEFAULT DESCRIPTION
0 enable toggle point "TP5"
0 = disable "TP5" and all subsequent toggle point
1 = enable toggle point "TP5"
000_0000 pixel count of toggle point "TP5"
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP1"
DEFAULT DESCRIPTION
0 enable toggle point "TP6"
0 = disable "TP6" and all subsequent toggle point
1 = enable toggle point "TP6"
000_0000 pixel count of toggle point "TP6"
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP7"
DEFAULT DESCRIPTION
0 enable toggle point "TP7"
0 = disable "TP7" and all subsequent toggle point
1 = enable toggle point "TP7"
000_0000 pixel count of toggle point "TP7"
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP8"
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
Toggle point
8 LSB
BIT LABEL
Register DFh Toggle point 8 LSB
REGISTER
ADDRESS
R224 (E0h)
Toggle point
8 MSB
BIT
7
LABEL
EN_TP8
6:0 TP8[14:8]
Register E0h Toggle point 8 MSB
REGISTER
ADDRESS
R225 (E1h)
Toggle point
9 LSB
BIT
7:0
LABEL
TP9[7:0]
Register E1h Toggle point 9 LSB
REGISTER
ADDRESS
R226 (E2h)
Toggle point
9 MSB
BIT
7
LABEL
EN_TP9
6:0 TP9[14:8]
Register E2h Toggle point 9 MSB
REGISTER
ADDRESS
R227 (E3h)
Toggle point
10 LSB
BIT
7:0
LABEL
TP10[7:0]
Register E3h Toggle point 10 LSB
REGISTER
ADDRESS
R228 (E4h)
Toggle point
10 MSB
BIT
7
LABEL
EN_TP10
6:0 TP10[14:8]
Register E4h Toggle point 10 MSB
REGISTER
ADDRESS
R229 (E5h)
Toggle point
11 LSB
Rev 4.5
BIT
7:0
LABEL
TP11[7:0]
DEFAULT
DEFAULT
0 enable toggle point "TP8"
0 = disable "TP8" and all subsequent toggle point
1 = enable toggle point "TP8"
000_0000 pixel count of toggle point "TP8"
DEFAULT
0000_0000 pixel count of toggle point "TP9"
DEFAULT
DEFAULT
DEFAULT
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
0 enable toggle point "TP9"
0 = disable "TP9" and all subsequent toggle point
1 = enable toggle point "TP9"
000_0000 pixel count of toggle point "TP9"
DESCRIPTION
0000_0000 pixel count of toggle point "TP10"
0 enable toggle point "TP10"
0 = disable "TP10" and all subsequent toggle point
1 = enable toggle point "TP10"
000_0000 pixel count of toggle point "TP10"
DEFAULT
DESCRIPTION
DESCRIPTION
0000_0000 pixel count of toggle point "TP11"
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
117
Register E5h Toggle point 11 LSB
REGISTER
ADDRESS
R230 (E6h)
Toggle point
11 MSB
BIT
7
LABEL
EN_TP11
6:0 TP11[14:8]
Register E6h Toggle point 11 MSB
REGISTER
ADDRESS
R231 (E7h)
Toggle point
12 LSB
BIT
7:0
LABEL
TP12[7:0]
Register E7h Toggle point 12 LSB
REGISTER
ADDRESS
R232 (E8h)
Toggle point
12 MSB
BIT
7
LABEL
EN_TP12
6:0 TP12[14:8]
Register E8h Toggle point 12 MSB
REGISTER
ADDRESS
R233 (E9h)
Toggle point
13 LSB
BIT
7:0
LABEL
TP13[7:0]
Register E9h Toggle point 13 LSB
REGISTER
ADDRESS
R234 (EAh)
Toggle point
13 MSB
BIT
7
LABEL
EN_TP13
6:0 TP13[14:8]
Register EAh Toggle point 13 MSB
REGISTER
ADDRESS
R235 (EBh)
Toggle point
14 LSB
BIT
7:0
LABEL
TP14[7:0]
Register EBh Toggle point 14 LSB
118
DEFAULT
0 enable toggle point "TP11"
0 = disable "TP11" and all subsequent toggle point
1 = enable toggle point "TP11"
000_0000 pixel count of toggle point "TP11"
DEFAULT
0000_0000 pixel count of toggle point "TP12"
DEFAULT
DEFAULT
DEFAULT
DESCRIPTION
DESCRIPTION
DESCRIPTION
0 enable toggle point "TP12"
0 = disable "TP12" and all subsequent toggle point
1 = enable toggle point "TP12"
000_0000 pixel count of toggle point "TP12"
DESCRIPTION
0000_0000 pixel count of toggle point "TP13"
0 enable toggle point "TP13"
0 = disable "TP13" and all subsequent toggle point
1 = enable toggle point "TP13"
000_0000 pixel count of toggle point "TP13"
DEFAULT
DESCRIPTION
DESCRIPTION
0000_0000 pixel count of toggle point "TP14"
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R236 (ECh)
Toggle point
14 MSB
BIT
7
LABEL
EN_TP14
6:0 TP14[14:8]
Register ECh Toggle point 14 MSB
REGISTER
ADDRESS
R237 (EDh)
Toggle point
15 LSB
BIT
7:0
LABEL
TP15[7:0]
Register EDh Toggle point 15 LSB
REGISTER
ADDRESS
R238 (EEh)
Toggle point
15 MSB
BIT
7
LABEL
EN_TP15
6:0 TP15[14:8]
Register EEh Toggle point 15 MSB
REGISTER
ADDRESS
R239 (EFh)
Toggle point
16 LSB
BIT
7:0
LABEL
TP16[7:0]
Register EFh Toggle point 16 LSB
REGISTER
ADDRESS
R240 (F0h)
Toggle point
16 MSB
BIT
7
LABEL
EN_TP16
6:0 TP16[14:8]
Register F0h Toggle point 16 MSB
REGISTER
ADDRESS
R241 (F1h)
Toggle point
17 LSB
BIT
7:0
LABEL
TP17[7:0]
Register F1h Toggle point 17 LSB
REGISTER
ADDRESS
R242 (F2h)
Rev 4.5
BIT
7
LABEL
EN_TP17
DEFAULT
0 enable toggle point "TP14"
0 = disable "TP14" and all subsequent toggle point
1 = enable toggle point "TP14"
000_0000 pixel count of toggle point "TP14"
DEFAULT
0000_0000 pixel count of toggle point "TP15"
DEFAULT
0 enable toggle point "TP15"
0 = disable "TP15" and all subsequent toggle point
1 = enable toggle point "TP15"
000_0000 pixel count of toggle point "TP15"
DEFAULT
0000_0000 pixel count of toggle point "TP16"
DEFAULT
0 enable toggle point "TP16"
0 = disable "TP16" and all subsequent toggle point
1 = enable toggle point "TP16"
000_0000 pixel count of toggle point "TP16"
DEFAULT
0000_0000 pixel count of toggle point "TP17"
DEFAULT
0 enable toggle point "TP17"
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
119
REGISTER
ADDRESS
Toggle point
17 MSB
BIT LABEL
6:0 TP17[14:8]
Register F2h Toggle point 17 MSB
REGISTER
ADDRESS
R243 (F3h)
Toggle point
18 LSB
BIT
7:0
LABEL
TP18[7:0]
Register F3h Toggle point 18 LSB
REGISTER
ADDRESS
R244 (F4h)
Toggle point
18 MSB
BIT
7
LABEL
EN_TP18
6:0 TP18[14:8]
Register F4h Toggle point 18 MSB
REGISTER
ADDRESS
R245 (F5h)
Toggle point
19 LSB
BIT
7:0
LABEL
TP19[7:0]
Register F5h Toggle point 19 LSB
REGISTER
ADDRESS
R246 (F6h)
Toggle point
19 MSB
BIT
7
LABEL
EN_TP19
6:0 TP19[14:8]
Register F6h Toggle point 19 MSB
REGISTER
ADDRESS
R247 (F7h)
Toggle point
20 LSB
BIT
7:0
LABEL
TP20[7:0]
Register F7h Toggle point 20 LSB
REGISTER
ADDRESS
R248 (F8h)
Toggle point
BIT
7
LABEL
EN_TP20
120
DEFAULT
0 = disable "TP17" and all subsequent toggle point
1 = enable toggle point "TP17"
000_0000 pixel count of toggle point "TP17"
DEFAULT
0000_0000 pixel count of toggle point "TP18"
DEFAULT
0 enable toggle point "TP18"
0 = disable "TP18" and all subsequent toggle point
1 = enable toggle point "TP18"
000_0000 pixel count of toggle point "TP18"
DEFAULT
0000_0000 pixel count of toggle point "TP19"
DEFAULT
0 enable toggle point "TP19"
0 = disable "TP19" and all subsequent toggle point
1 = enable toggle point "TP19"
000_0000 pixel count of toggle point "TP19"
DEFAULT
0000_0000 pixel count of toggle point "TP20"
DEFAULT
0 enable toggle point "TP20"
0 = disable "TP20" and all subsequent toggle point
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
20 MSB
BIT LABEL
6:0 TP20[14:8]
Register F8h Toggle point 20 MSB
REGISTER
ADDRESS
R249 (F9h)
Toggle point
21 LSB
BIT
7:0
LABEL
TP21[7:0]
Register F9h Toggle point 21 LSB
REGISTER
ADDRESS
R250 (FAh)
Toggle point
21 MSB
BIT
7
LABEL
EN_TP21
6:0 TP21[14:8]
Register FAh Toggle point 21 MSB
REGISTER
ADDRESS
R251 (FBh)
Toggle point
22 LSB
BIT
7:0
LABEL
TP22[7:0]
Register FBh Toggle point 22 LSB
REGISTER
ADDRESS
R252 (FCh)
Toggle point
22 MSB
BIT
7
LABEL
EN_TP22
6:0 TP22[14:8]
Register FCh Toggle point 22 MSB
REGISTER
ADDRESS
R253 (FDh)
Toggle point
23 LSB
BIT
7:0
LABEL
TP23[7:0]
Register FDh Toggle point 23 LSB
REGISTER
ADDRESS
R254 (FEh)
Toggle point
23 MSB
BIT
7
LABEL
EN_TP23
Rev 4.5
DEFAULT
1 = enable toggle point "TP20"
000_0000 pixel count of toggle point "TP20"
DEFAULT
0000_0000 pixel count of toggle point "TP21"
DEFAULT
0 enable toggle point "TP21"
0 = disable "TP21" and all subsequent toggle point
1 = enable toggle point "TP21"
000_0000 pixel count of toggle point "TP21"
DEFAULT
0000_0000 pixel count of toggle point "TP22"
DEFAULT
0 enable toggle point "TP22"
0 = disable "TP22" and all subsequent toggle point
1 = enable toggle point "TP22"
000_0000 pixel count of toggle point "TP22"
DEFAULT
0000_0000 pixel count of toggle point "TP23"
DEFAULT
0 enable toggle point "TP23"
0 = disable "TP23" and all subsequent toggle point
1 = enable toggle point "TP23"
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
121
REGISTER
ADDRESS
BIT LABEL
6:0 TP23[14:8]
Register FEh Toggle point 23 MSB
REGISTER
ADDRESS
R255 (FFh)
Toggle point
24 LSB
BIT
7:0
LABEL
TP24[7:0]
Register FFh Toggle point 24 LSB
REGISTER
ADDRESS
R256 (0100h)
Toggle point
24 MSB
BIT
7
LABEL
EN_TP24
6:0 TP24[14:8]
Register 0100h Toggle point 24 MSB
REGISTER
ADDRESS
R257 (0101h)
Toggle point
25 LSB
BIT
7:0
LABEL
TP25[7:0]
Register 0101h Toggle point 25 LSB
REGISTER
ADDRESS
R258 (0102h)
Toggle point
25 MSB
BIT
7
LABEL
EN_TP25
6:0 TP25[14:8]
Register 0102h Toggle point 25 MSB
REGISTER
ADDRESS
R259 (0103h)
Toggle point
26 LSB
BIT
7:0
LABEL
TP26[7:0]
Register 0103h Toggle point 26 LSB
REGISTER
ADDRESS
R260 (0104h)
Toggle point
26 MSB
BIT
7
6:0
122
LABEL
EN_TP26
TP26[14:8]
DEFAULT
DEFAULT
DEFAULT
0 enable toggle point "TP24"
0 = disable "TP24" and all subsequent toggle point
1 = enable toggle point "TP24"
000_0000 pixel count of toggle point "TP24"
DEFAULT
DEFAULT
0 enable toggle point "TP26"
0 = disable "TP26" and all subsequent toggle point
1 = enable toggle point "TP26"
000_0000 pixel count of toggle point "TP26"
DESCRIPTION
000_0000 pixel count of toggle point "TP23"
0000_0000 pixel count of toggle point "TP24"
0000_0000 pixel count of toggle point "TP25"
0 enable toggle point "TP25"
0 = disable "TP25" and all subsequent toggle point
1 = enable toggle point "TP25"
000_0000 pixel count of toggle point "TP25"
DEFAULT
0000_0000 pixel count of toggle point "TP26"
DEFAULT
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
Register 0104h Toggle point 26 MSB
REGISTER
ADDRESS
R261 (0105h)
Toggle point
27 LSB
BIT
7:0
LABEL
TP27[7:0]
Register 0105h Toggle point 27 LSB
REGISTER
ADDRESS
R262 (0106h)
Toggle point
27 MSB
BIT
7
LABEL
EN_TP27
6:0 TP27[14:8]
Register 0106h Toggle point 27 MSB
REGISTER
ADDRESS
R263 (0107h)
Toggle point
28 LSB
BIT
7:0
LABEL
TP28[7:0]
Register 0107h Toggle point 28 LSB
REGISTER
ADDRESS
R264 (0108h)
Toggle point
28 MSB
BIT
7
LABEL
EN_TP28
6:0 TP28[14:8]
Register 0108h Toggle point 28 MSB
REGISTER
ADDRESS
R265 (0109h)
Toggle point
29 LSB
BIT
7:0
LABEL
TP29[7:0]
Register 0109h Toggle point 29 LSB
REGISTER
ADDRESS
R266
(010Ah)
Toggle point
29 MSB
BIT
7
LABEL
EN_TP29
6:0 TP29[14:8]
Register 010Ah Toggle point 29 MSB
Rev 4.5
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP27"
DEFAULT DESCRIPTION
0 enable toggle point "TP27"
0 = disable "TP27" and all subsequent toggle point
1 = enable toggle point "TP27"
000_0000 pixel count of toggle point "TP27"
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP28"
DEFAULT DESCRIPTION
0 enable toggle point "TP28"
0 = disable "TP28" and all subsequent toggle point
1 = enable toggle point "TP28"
000_0000 pixel count of toggle point "TP28"
DEFAULT DESCRIPTION
0000_0000 pixel count of toggle point "TP29"
DEFAULT DESCRIPTION
0 enable toggle point "TP29"
0 = disable "TP29" and all subsequent toggle point
1 = enable toggle point "TP29"
000_0000 pixel count of toggle point "TP29"
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
123
REGISTER
ADDRESS
R267
(010Bh)
Toggle point
30 LSB
BIT
7:0
LABEL
TP30[7:0]
Register 010Bh Toggle point 30 LSB
REGISTER
ADDRESS
R268
(010Ch)
Toggle point
30 MSB
BIT
7
LABEL
EN_TP30
6:0 TP30[14:8]
Register 010Ch Toggle point 30 MSB
REGISTER
ADDRESS
R269
(010Dh)
Toggle point
31 LSB
BIT
7:0
LABEL
TP31[7:0]
Register 010Dh Toggle point 31 LSB
REGISTER
ADDRESS
R270
(010Eh)
Toggle point
31 MSB
BIT
7
LABEL
EN_TP31
6:0 TP31[14:8]
Register 010Eh Toggle point 31 MSB
REGISTER
ADDRESS
R271
(010Fh)
Polarity setting of
T1 1
BIT
7
6
LABEL
POL7_T1
POL6_T1
DEFAULT
0 enable toggle point "TP30"
0 = disable "TP30" and all subsequent toggle point
1 = enable toggle point "TP30"
000_0000 pixel count of toggle point "TP30"
0 enable toggle point "TP31"
0 = disable "TP31"
1 = enable toggle point "TP31"
000_0000 pixel count of toggle point "TP31"
1
1
DESCRIPTION
0000_0000 pixel count of toggle point "TP30"
DEFAULT
DEFAULT
DESCRIPTION
DESCRIPTION
0000_0000 pixel count of toggle point "TP31"
DEFAULT
DEFAULT
DESCRIPTION
DESCRIPTION
124
5
4
3
2
POL5_T1
POL4_T1
POL3_T1
POL2_T1
1
1
1
1 logic level of T1 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of T1 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of T1 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of T1 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of T1 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of T1 pulse at toggle point TP2
0 = low at TP2
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT
Rev 4.5
1
0
5
4
LABEL
POL1_T1
POL0_T1
POL21_T1
POL20_T1
DEFAULT
1
1
DESCRIPTION
1 = high at TP2 logic level of T1 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of T1 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 010Fh Polarity setting of T1 1
REGISTER
ADDRESS
R272 (0110h)
Polarity setting of
T1 2
BIT
7
6
LABEL
POL15_T1
POL14_T1
DEFAULT
1
1
5
4
3
2
1
0
POL13_T1
POL12_T1
POL11_T1
POL10_T1
POL9_T1
POL8_T1
1
1
1
1
1
1
DESCRIPTION
logic level of T1 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of T1 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of T1 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of T1 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of T1 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of T1 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of T1 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of T1 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0110h Polarity setting of T1 2
REGISTER
ADDRESS
R273 (0111h)
Polarity setting of
T1 3
BIT
7
6
LABEL
POL23_T1
POL22_T1
DEFAULT
1
1
1
1
DESCRIPTION
logic level of T1 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of T1 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of T1 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of T1 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
WM8235
REFER TO
REFER TO
REFER TO
125
REGISTER
ADDRESS
BIT
3
2
1
0
LABEL
POL19_T1
POL18_T1
POL17_T1
POL16_T1
DEFAULT
1
1
1
1
DESCRIPTION
logic level of T1 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of T1 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of T1 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of T1 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0111h Polarity setting of T1 3
REGISTER
ADDRESS
R274 (0112h)
Polarity setting of
T1 4
BIT
7
6
LABEL
POL31_T1
POL30_T1
5
4
3
2
1
0
POL29_T1
POL28_T1
POL27_T1
POL26_T1
POL25_T1
POL24_T1
DEFAULT
1
1
1
1
1
1
1
1
DESCRIPTION
logic level of T1 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of T1 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of T1 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of T1 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of T1 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of T1 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of T1 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of T1 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0112h Polarity setting of T1 4
REGISTER
ADDRESS
R275 (0113h)
Polarity setting of
T2 1
BIT
7
6
LABEL
POL7_T2
POL6_T2
126
5 POL5_T2
DEFAULT
1
1
1
DESCRIPTION
logic level of T2 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of T2 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of T2 pulse at toggle point TP5
WM8235
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT
4
3
2
1
0
LABEL
POL4_T2
POL3_T2
POL2_T2
POL1_T2
POL0_T2
DEFAULT
1
1
1
1
1
DESCRIPTION
0 = low at TP5
1 = high at TP5 logic level of T2 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of T2 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of T2 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of T2 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of T2 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 0113h Polarity setting of T2 1
REGISTER
ADDRESS
R276 (0114h)
Polarity setting of
T2 2
BIT
7
6
5
4
3
2
1
0
LABEL
POL15_T2
POL14_T2
POL13_T2
POL12_T2
POL11_T2
POL10_T2
POL9_T2
POL8_T2
DEFAULT
1
1
1
1
1
1
1
1
DESCRIPTION
logic level of T2 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of T2 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of T2 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of T2 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of T2 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of T2 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of T2 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of T2 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0114h Polarity setting of T2 2
REGISTER
ADDRESS
R277 (0115h)
Polarity
Rev 4.5
BIT
7
LABEL
POL23_T2
DEFAULT
1 logic level of T2 pulse at toggle point TP23
0 = low at TP23
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
127
REGISTER
ADDRESS
setting of
T2 3
BIT
6
5
4
3
2
1
0
LABEL
POL22_T2
POL21_T2
POL20_T2
POL19_T2
POL18_T2
POL17_T2
POL16_T2
DEFAULT
1
1
1
1
1
1
1
DESCRIPTION
1 = high at TP23 logic level of T2 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of T2 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of T2 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20 logic level of T2 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of T2 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of T2 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of T2 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0115h Polarity setting of T2 3
REGISTER
ADDRESS
R278 (0116h)
Polarity setting of
T2 4
BIT
7
6
LABEL
POL31_T2
POL30_T2
5
4
3
2
1
0
POL29_T2
POL28_T2
POL27_T2
POL26_T2
POL25_T2
POL24_T2
DEFAULT
1
1
1
1
1
1
1
1
DESCRIPTION
logic level of T2 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of T2 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of T2 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of T2 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of T2 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of T2 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of T2 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of T2 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0116h Polarity setting of T2 4
128
WM8235
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R279 (0117h)
Polarity setting of
P0 1
BIT
7
6
5
4
3
2
1
0
LABEL
POL7_PO0
POL6_PO0
POL5_PO0
POL4_PO0
POL3_PO0
POL2_PO0
POL1_PO0
POL0_PO0
DEFAULT
0
0
0
0
0
0
0
0
DESCRIPTION
logic level of PO0 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of PO0 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of PO0 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of PO0 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of PO0 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of PO0 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of PO0 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of PO0 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 0117h Polarity setting of P0 1
REGISTER
ADDRESS
R280 (0118h)
Polarity setting of
P0 2
BIT
7
6
LABEL
POL15_PO0
POL14_PO0
DEFAULT
0
0
Rev 4.5
5
4
3
2
1
0
POL13_PO0
POL12_PO0
POL11_PO0
POL10_PO0
POL9_PO0
POL8_PO0
0
0
0
0
0
0
DESCRIPTION
logic level of PO0 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of PO0 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of PO0 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of PO0 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of PO0 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of PO0 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of PO0 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of PO0 pulse at toggle point TP8
0 = low at TP8
WM8235
REFER TO
REFER TO
129
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
1 = high at TP8
Register 0118h Polarity setting of P0 2
REGISTER
ADDRESS
R281 (0119h)
Polarity setting of
P0 3
BIT
7
6
LABEL
POL23_PO0
POL22_PO0
DEFAULT
0
0
5
4
3
2
1
0
POL21_PO0
POL20_PO0
POL19_PO0
POL18_PO0
POL17_PO0
POL16_PO0
0
0
0
0
0
0
DESCRIPTION
logic level of PO0 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of PO0 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of PO0 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of PO0 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20 logic level of PO0 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of PO0 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of PO0 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of PO0 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0119h Polarity setting of P0 3
REGISTER
ADDRESS
R282
(011Ah)
Polarity setting of
P0 4
BIT
7
6
LABEL
POL31_PO0
POL30_PO0
DEFAULT
0
0
DESCRIPTION
130
5
4
3
2
POL29_PO0
POL28_PO0
POL27_PO0
POL26_PO0
0
0
0
0 logic level of PO0 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of PO0 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of PO0 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of PO0 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of PO0 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of PO0 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
WM8235
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
1
0
POL25_PO0
POL24_PO0
0
0 logic level of PO0 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of PO0 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 011Ah Polarity setting of P0 4
REGISTER
ADDRESS
R283
(011Bh)
Polarity setting of
P1 1
BIT
7
6
5
4
3
2
1
0
LABEL
POL7_PO1
POL6_PO1
POL5_PO1
POL4_PO1
POL3_PO1
POL2_PO1
POL1_PO1
POL0_PO1
DEFAULT
0
0
0
0
0
0
0
0
DESCRIPTION
logic level of PO1 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of PO1 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of PO1 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of PO1 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of PO1 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of PO1 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of PO1 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of PO1 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 011Bh Polarity setting of P1 1
REGISTER
ADDRESS
R284
(011Ch)
Polarity setting of
P1 2
BIT
7
6
LABEL
POL15_PO1
POL14_PO1
DEFAULT
0
0
Rev 4.5
5
4
3
POL13_PO1
POL12_PO1
POL11_PO1
0
0
0
DESCRIPTION
logic level of PO1 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of PO1 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of PO1 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of PO1 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of PO1 pulse at toggle point TP11
WM8235
REFER TO
REFER TO
REFER TO
131
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
2
1
0
POL10_PO1
POL9_PO1
POL8_PO1
0
0
0
0 = low at TP11
1 = high at TP11 logic level of PO1 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of PO1 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of PO1 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 011Ch Polarity setting of P1 2
REGISTER
ADDRESS
R285
(011Dh)
Polarity setting of
P1 3
BIT
7
6
5
4
3
2
1
0
LABEL
POL23_PO1
POL22_PO1
POL21_PO1
POL20_PO1
POL19_PO1
POL18_PO1
POL17_PO1
POL16_PO1
DEFAULT
0
0
0
0
0
0
0
0
DESCRIPTION
logic level of PO1 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of PO1 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of PO1 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of PO1 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20 logic level of PO1 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of PO1 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of PO1 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of PO1 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 011Dh Polarity setting of P1 3
REGISTER
ADDRESS
R286
(011Eh)
Polarity setting of
P1 4
BIT
7
6
LABEL
POL31_PO1
POL30_PO1
DEFAULT
0
0
132
5 POL29_PO1 0
DESCRIPTION
logic level of PO1 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of PO1 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of PO1 pulse at toggle point TP29
0 = low at TP29
WM8235
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
4
3
2
1
0
POL28_PO1
POL27_PO1
POL26_PO1
POL25_PO1
POL24_PO1
0
0
0
0
0
1 = high at TP29 logic level of PO1 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of PO1 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of PO1 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of PO1 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of PO1 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 011Eh Polarity setting of P1 4
REGISTER
ADDRESS
R287
(011Fh)
Polarity setting of
P2 1
BIT
7
6
5
4
3
2
1
0
LABEL
POL7_PO2
POL6_PO2
POL5_PO2
POL4_PO2
POL3_PO2
POL2_PO2
POL1_PO2
POL0_PO2
DEFAULT
0
0
0
0
0
0
0
0
DESCRIPTION
logic level of PO2 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of PO2 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of PO2 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of PO2 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of PO2 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of PO2 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of PO2 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of PO2 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 011Fh Polarity setting of P2 1
REGISTER
ADDRESS
R288 (0120h)
Polarity setting of
Rev 4.5
BIT
7
LABEL
POL15_PO2
DEFAULT
0
DESCRIPTION
logic level of PO2 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15
WM8235
REFER TO
REFER TO
REFER TO
133
REGISTER
ADDRESS
P2 2
BIT LABEL DEFAULT DESCRIPTION
6
5
4
3
2
1
0
POL14_PO2
POL13_PO2
POL12_PO2
POL11_PO2
POL10_PO2
POL9_PO2
POL8_PO2
0
0
0
0
0
0
0 logic level of PO2 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of PO2 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of PO2 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of PO2 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of PO2 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of PO2 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of PO2 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0120h Polarity setting of P2 2
REGISTER
ADDRESS
R289 (0121h)
Polarity setting of
P2 3
BIT
7
6
LABEL
POL23_PO2
POL22_PO2
DEFAULT
0
0
5
4
3
2
1
0
POL21_PO2
POL20_PO2
POL19_PO2
POL18_PO2
POL17_PO2
POL16_PO2
0
0
0
0
0
0
DESCRIPTION
logic level of PO2 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of PO2 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of PO2 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of PO2 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20 logic level of PO2 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of PO2 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of PO2 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of PO2 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0121h Polarity setting of P2 3
134
WM8235
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R290 (0122h)
Polarity setting of
P2 4
BIT
7
6
5
4
3
2
1
0
LABEL
POL31_PO2
POL30_PO2
POL29_PO2
POL28_PO2
POL27_PO2
POL26_PO2
POL25_PO2
POL24_PO2
DEFAULT
0
0
0
0
0
0
0
0
DESCRIPTION
logic level of PO2 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of PO2 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of PO2 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of PO2 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of PO2 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of PO2 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of PO2 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of PO2 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0122h Polarity setting of P2 4
REGISTER
ADDRESS
R291 (0123h)
Polarity setting of
P3 1
BIT
7
6
LABEL
POL7_PO3
POL6_PO3
DEFAULT
0
0
5
4
3
2
1
0
POL5_PO3
POL4_PO3
POL3_PO3
POL2_PO3
POL1_PO3
POL0_PO3
0
0
0
0
0
0
DESCRIPTION
logic level of PO3 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of PO3 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of PO3 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of PO3 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of PO3 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of PO3 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of PO3 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of PO3 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Rev 4.5
WM8235
REFER TO
REFER TO
135
Register 0123h Polarity setting of P3 1
REGISTER
ADDRESS
R292 (0124h)
Polarity setting of
P3 2
BIT
7
6
LABEL
POL15_PO3
POL14_PO3
DEFAULT
0
0
5
4
3
2
1
0
POL13_PO3
POL12_PO3
POL11_PO3
POL10_PO3
POL9_PO3
POL8_PO3
0
0
0
0
0
0
DESCRIPTION
logic level of PO3 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of PO3 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of PO3 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of PO3 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of PO3 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of PO3 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of PO3 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of PO3 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0124h Polarity setting of P3 2
REGISTER
ADDRESS
R293 (0125h)
Polarity setting of
P3 3
BIT
7
6
136
5
4
3
2
1
LABEL
POL23_PO3
DEFAULT
0
POL22_PO3
POL21_PO3
POL20_PO3
POL19_PO3
POL18_PO3
POL17_PO3
0
0
0
0
0
0
DESCRIPTION
logic level of PO3 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of PO3 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of PO3 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of PO3 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20 logic level of PO3 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of PO3 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of PO3 pulse at toggle point TP17
0 = low at TP17
WM8235
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
0 POL16_PO3 0
1 = high at TP17 logic level of PO3 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0125h Polarity setting of P3 3
REGISTER
ADDRESS
R294 (0126h)
Polarity setting of
P3 4
BIT
7
6
LABEL
POL31_PO3
POL30_PO3
DEFAULT
0
0
5
4
3
2
1
0
POL29_PO3
POL28_PO3
POL27_PO3
POL26_PO3
POL25_PO3
POL24_PO3
0
0
0
0
0
0
DESCRIPTION
logic level of PO3 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of PO3 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of PO3 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of PO3 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of PO3 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of PO3 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of PO3 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of PO3 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0126h Polarity setting of P3 4
REGISTER
ADDRESS
R295 (0127h)
Polarity setting of
P4 1
BIT
7
6
LABEL
POL7_PO4
POL6_PO4
DEFAULT
0
0
DESCRIPTION
Rev 4.5
5
4
3
POL5_PO4
POL4_PO4
POL3_PO4
0
0
0 logic level of PO4 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of PO4 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of PO4 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of PO4 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of PO4 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
WM8235
REFER TO
REFER TO
REFER TO
137
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
2
1
0
POL2_PO4
POL1_PO4
POL0_PO4
0
0
0 logic level of PO4 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of PO4 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of PO4 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 0127h Polarity setting of P4 1
REGISTER
ADDRESS
R296 (0128h)
Polarity setting of
P4 2
BIT
7
6
LABEL
POL15_PO4
POL14_PO4
DEFAULT
0
0
5
4
3
2
1
0
POL13_PO4
POL12_PO4
POL11_PO4
POL10_PO4
POL9_PO4
POL8_PO4
0
0
0
0
0
0
DESCRIPTION
logic level of PO4 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of PO4 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of PO4 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of PO4 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of PO4 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of PO4 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of PO4 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of PO4 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0128h Polarity setting of P4 2
REGISTER
ADDRESS
R297 (0129h)
Polarity setting of
P4 3
BIT
7
6
138
5
4
LABEL
POL23_PO4
POL22_PO4
POL21_PO4
POL20_PO4
DEFAULT
0
0
0
0 logic level of PO4 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of PO4 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of PO4 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of PO4 pulse at toggle point TP20
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
3
2
1
0
POL19_PO4
POL18_PO4
POL17_PO4
POL16_PO4
0
0
0
0
Register 0129h Polarity setting of P4 3
REGISTER
ADDRESS
R298
(012Ah)
Polarity setting of
P4 4
BIT
7
6
LABEL
POL31_PO4
POL30_PO4
DEFAULT
0
0
5
4
3
2
1
0
POL29_PO4
POL28_PO4
POL27_PO4
POL26_PO4
POL25_PO4
POL24_PO4
0
0
0
0
0
0
DESCRIPTION
logic level of PO4 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of PO4 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of PO4 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of PO4 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of PO4 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of PO4 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of PO4 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of PO4 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 012Ah Polarity setting of P4 4
0 = low at TP20
1 = high at TP20 logic level of PO4 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of PO4 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of PO4 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of PO4 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
REGISTER
ADDRESS
R299
(012Bh)
Polarity setting of
P5 1
Rev 4.5
BIT
7
6
LABEL
POL7_PO5
POL6_PO5
DEFAULT
0
0 logic level of PO5 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of PO5 pulse at toggle point TP6
0 = low at TP6
DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
139
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
5
4
3
2
1
0
POL5_PO5
POL4_PO5
POL3_PO5
POL2_PO5
POL1_PO5
POL0_PO5
0
0
0
0
0
0
1 = high at TP6 logic level of PO5 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of PO5 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of PO5 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of PO5 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of PO5 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of PO5 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 012Bh Polarity setting of P5 1
REGISTER
ADDRESS
R300
(012Ch)
Polarity setting of
P5 2
BIT
7
6
LABEL
POL15_PO5
POL14_PO5
DEFAULT
0
0
5
4
3
2
1
0
POL13_PO5
POL12_PO5
POL11_PO5
POL10_PO5
POL9_PO5
POL8_PO5
0
0
0
0
0
0
DESCRIPTION
logic level of PO5 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of PO5 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of PO5 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of PO5 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of PO5 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of PO5 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of PO5 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of PO5 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 012Ch Polarity setting of P5 2
REGISTER
ADDRESS
140
BIT LABEL DEFAULT DESCRIPTION
WM8235
REFER TO
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
R301
(012Dh)
Polarity setting of
P5 3
BIT
7
6
5
4
3
2
1
0
LABEL
POL23_PO5
POL22_PO5
POL21_PO5
POL20_PO5
POL19_PO5
POL18_PO5
POL17_PO5
POL16_PO5
DEFAULT
0
0
0
0
0
0
0
0
DESCRIPTION
logic level of PO5 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of PO5 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of PO5 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of PO5 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20 logic level of PO5 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of PO5 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of PO5 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of PO5 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 012Dh Polarity setting of P5 3
REGISTER
ADDRESS
R302
(012Eh)
Polarity setting of
P5 4
BIT
7
6
Rev 4.5
5
4
3
2
1
0
LABEL
POL31_PO5
DEFAULT
0
POL30_PO5
POL29_PO5
POL28_PO5
POL27_PO5
POL26_PO5
POL25_PO5
POL24_PO5
0
0
0
0
0
0
0
DESCRIPTION
logic level of PO5 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of PO5 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of PO5 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of PO5 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of PO5 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of PO5 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of PO5 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of PO5 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
WM8235
REFER TO
REFER TO
141
Register 012Eh Polarity setting of P5 4
REGISTER
ADDRESS
R303
(012Fh)
Polarity setting of
P6 1
BIT
7
6
LABEL
POL7_PO6
POL6_PO6
DEFAULT
0
0
5
4
3
2
1
0
POL5_PO6
POL4_PO6
POL3_PO6
POL2_PO6
POL1_PO6
POL0_PO6
0
0
0
0
0
0
DESCRIPTION
logic level of PO6 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of PO6 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of PO6 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of PO6 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of PO6 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of PO6 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of PO6 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of PO6 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 012Fh Polarity setting of P6 1
REGISTER
ADDRESS
R304 (0130h)
Polarity setting of
P6 2
BIT
7
6
142
5
4
3
2
1
LABEL
POL15_PO6
DEFAULT
0
POL14_PO6
POL13_PO6
POL12_PO6
POL11_PO6
POL10_PO6
POL9_PO6
0
0
0
0
0
0
DESCRIPTION
logic level of PO6 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of PO6 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of PO6 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13 logic level of PO6 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of PO6 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of PO6 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of PO6 pulse at toggle point TP9
0 = low at TP9
WM8235
REFER TO
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
0 POL8_PO6 0
1 = high at TP9 logic level of PO6 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0130h Polarity setting of P6 2
REGISTER
ADDRESS
R305 (0131h)
Polarity setting of
P6 3
BIT
7
LABEL
POL23_PO6
6 POL22_PO6
DEFAULT
0
0
5
4
3
2
1
0
POL21_PO6
POL20_PO6
POL19_PO6
POL18_PO6
POL17_PO6
POL16_PO6
0
0
0
0
0
0
DESCRIPTION
logic level of PO6 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of PO6 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of PO6 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of PO6 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20 logic level of PO6 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of PO6 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of PO6 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of PO6 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0131h Polarity setting of P6 3
REGISTER
ADDRESS
R306 (0132h)
Polarity setting of
P6 4
BIT
7
6
Rev 4.5
5
4
3
LABEL
POL31_PO6
POL30_PO6
POL29_PO6
POL28_PO6
POL27_PO6
DEFAULT
0
0
0
0
0
DESCRIPTION
logic level of PO6 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of PO6 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30 logic level of PO6 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of PO6 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of PO6 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
WM8235
REFER TO
REFER TO
REFER TO
143
REGISTER
ADDRESS
BIT
2
LABEL DEFAULT DESCRIPTION
1
0
POL26_PO6
POL25_PO6
POL24_PO6
0
0
0 logic level of PO6 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of PO6 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of PO6 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0132h Polarity setting of P6 4
REGISTER
ADDRESS
R307 (0133h)
Polarity setting of
P7 1
BIT
7
6
LABEL
POL7_PO7
POL6_PO7
DEFAULT
0
0
5
4
3
2
1
0
POL5_PO7
POL4_PO7
POL3_PO7
POL2_PO7
POL1_PO7
POL0_PO7
0
0
0
0
0
0
DESCRIPTION
logic level of PO7 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7 logic level of PO7 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6 logic level of PO7 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5 logic level of PO7 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4 logic level of PO7 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3 logic level of PO7 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2 logic level of PO7 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1 logic level of PO7 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 0133h Polarity setting of P7 1
WM8235
REFER TO
REFER TO
REGISTER
ADDRESS
R308 (0134h)
Polarity setting of
P7 2
BIT
7
6
144
5
LABEL
POL15_PO7
DEFAULT
0
POL14_PO7
POL13_PO7
0
0
DESCRIPTION
logic level of PO7 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15 logic level of PO7 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14 logic level of PO7 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
REFER TO
Rev 4.5
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
4
3
2
1
0
POL12_PO7
POL11_PO7
POL10_PO7
POL9_PO7
POL8_PO7
0
0
0
0
0
Register 0134h Polarity setting of P7 2
REGISTER
ADDRESS
R309 (0135h)
Polarity setting of
P7 3
BIT
7
6
LABEL
POL23_PO7
POL22_PO7
DEFAULT
0
0
5
4
3
2
1
0
POL21_PO7
POL20_PO7
POL19_PO7
POL18_PO7
POL17_PO7
POL16_PO7
0
0
0
0
0
0
DESCRIPTION
logic level of PO7 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23 logic level of PO7 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22 logic level of PO7 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21 logic level of PO7 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20 logic level of PO7 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19 logic level of PO7 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18 logic level of PO7 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17 logic level of PO7 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0135h Polarity setting of P7 3 logic level of PO7 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12 logic level of PO7 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11 logic level of PO7 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10 logic level of PO7 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9 logic level of PO7 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
WM8235
REFER TO
REFER TO
REGISTER
ADDRESS
R310 (0136h)
Polarity setting of
P7 4
BIT
7
6
Rev 4.5
LABEL
POL31_PO7
DEFAULT
0
POL30_PO7 0
DESCRIPTION
logic level of PO7 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31 logic level of PO7 pulse at toggle point TP30
REFER TO
145
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
5
4
3
2
1
0
POL29_PO7
POL28_PO7
POL27_PO7
POL26_PO7
POL25_PO7
POL24_PO7
0
0
0
0
0
0
0 = low at TP30
1 = high at TP30 logic level of PO7 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29 logic level of PO7 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28 logic level of PO7 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27 logic level of PO7 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26 logic level of PO7 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25 logic level of PO7 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0136h Polarity setting of P7 4
REGISTER
ADDRESS
R432 (1B0h)
User access control
BIT
0
LABEL
USER_KEY
Register 01B0h User access control
DEFAULT
0
DESCRIPTION
0 = User access disabled
1 = User access enabled
REGISTER
ADDRESS
R436 (1B4h)
LDO2 control
BIT
4:0 LDO2 VSEL
Register 01B4h LDO2 control
LABEL DEFAULT
1_0000
1_0000 = 1.8V
1_0010 = 2.0V
REGISTER
ADDRESS
R448 (1C0h)
User access control2
BIT
0
LABEL
User_KEY2
Register 1C0h User access control2
REGISTER
ADDRESS
R459 (1CBh)
Comp control
BIT
1:0
LABEL
PT_COMP
DEFAULT
0
DEFAULT
01
DESCRIPTION
DESCRIPTION
0 = User access2 disabled
1 = User access2 enabled
DESCRIPTION
01 = Standard operation
11 = High performance operation
Other = Inhibit.
Register 1CBh Comp control
146
WM8235
REFER TO
REFER TO
REFER TO
REFER TO
REFER TO
Rev 4.5
WM8235
Rev 4.5
147
WM8235
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
AVDD1 AVDD2
DBVDD
C1
C2
LDO1VDD
LDO2VDD
55
C3
AVDD1
48
AVDD2
22
DBVDD
33
LDO1VDD
C4
9
LDO2VDD
C5
AGND1
56
AGND2
47
AGND3
43
VREF1C
VREF2C
4
VREF3C
1
3
AGND
C8 C7 C6
AGND
Video
Inputs
Timing
Signals
Interface
Controls
C9 C10
C11
2
VRLC/VBIAS
LDO1VOUT
31
LDO2VOUT
11
C12 C13
AGND
AGND
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
44
45
46
49
50
51
52
53
54
13
34
MCLK
TGSYNC
8
SDI
7
SCK
5
SEN
14
DSLCT1
12
DSLCT2
WM8235
D1P/OP[0]
D1N/OP[1]
D2P/OP[2]
D2N/OP[3]
D3P/OP[4]
D3N/OP[5]
DCLKP/OC[1]
DCLKN/OP[2]
D4P/OP[6]
D4N/OP[7]
D5P/OP[8]
D5N/OP[9]
23
20
19
18
17
16
28
27
26
25
24
15
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
35
36
37
38
39
40
41
42
AGND
Output
Data
Bus
AVDD1 AVDD2 DBVDDLDO1VDD LDO2VDD
C14 C15 C16 C17 C18
Timing generator
Outputs
LDO1VOUT
AGND
LDO2VOUT
C19 C20
AGND
NOTES: 1.
C1-20 should be fitted as close to device as possible.
2.
AGND should be connected as close to device as possible.
Figure 53 External Components Diagram
148 Rev 4.5
RECOMMENDED EXTERNAL COMPONENT VALUES
COMPONENT
REFERENCE
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
SUGGESTED
VALUE
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.01uF
10uF
1uF
1uF
1uF
10uF
10uF
10uF
10uF
10uF
10uF
10uF
DESCRIPTION
Table 16 External Components Descriptions
De-coupling for AVDD1
De-coupling for AVDD2
De-coupling for DBVDD
De-coupling for LDO1VDD
De-coupling for LDO2VDD
De-coupling for VREF1C
De-coupling for VREF2C
De-coupling for VREF3C
High frequency decoupling between VREF1C and VREF3C
Low frequency decoupling between VREF1C and VREF3C
De-coupling for VRLC/VBIAS
De-coupling for LDO1VOUT
De-coupling for LDO2VOUT
Reservoir capacitor for AVDD1
Reservoir capacitor for AVDD2
Reservoir capacitor for DBVDD
Reservoir capacitor for LDO1VDD
Reservoir capacitor for LDO2VDD
Reservoir capacitor for LDOOUT
Reservoir capacitor for LDOOUT
WM8235
Rev 4.5
149
PACKAGE DIMENSIONS
FL: 56 PIN QFN PLASTIC PACKAGE 7
X
7
X
0.85 mm BODY, 0.40 mm LEAD PITCH eee
D2
C B A
A
D2/2
PIN 1
43 56
L
36
1
INDEX AREA
(D/2 X E/2)
EXPOSED
GND
PADDLE
6
E2/2
E2
eee C B A
D
WM8235
DM092.B
B
E
29
28 e
C
SEATING PLANE
M
b
15
ddd
M
C A B
14
2 X
2 X aaa C aaa C
A1
(A3)
A2
A bbb C
M b
D
D2
E
E2 e
L
A
A1
A2
A3
Symbols
MIN
0.8
-
0
0.15
5.10
5.10
0.35
Dimensions (mm)
NOM
0.85
MAX
0.035
0.65
0.9
0.05
0.67
0.203 REF
0.2
7.00 BSC
0.25
5.20
7.00 BSC
5.20
0.4 BSC
5.30
5.30
0.4
0.45
NOTE
1
aaa bbb ccc ddd eee
REF
Tolerances of Form and Position
0.10
0.10
0.08
0.10
0.10
JEDEC, MO-220, VARIATION VKKE
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. ALL DIMENSIONS ARE IN MILLIMETRES
3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002.
4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION.
150
TOP VIEW
Rev 4.5
IMPORTANT NOTICE
WM8235
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another.
Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL
INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC
PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED
INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR
OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS,
STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE
CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS,
EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND
COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of
Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners.
Copyright © 2010
–2015 Cirrus Logic, Inc. All rights reserved.
Rev 4.5
151
WM8235
REVISION HISTORY
DATE
16/11/10
08/12/11
11/12/11
REV
1.0
3.0
3.0
ORIGINATOR
AA/NB
JMacD
AA
01/02/12
20/02/12
20/02/12
14/12/12
17/02/14
3.1
3.2
3.2
4.0
4.1
JMacD
AA/JMacD
AA/JMacD
AA
AA
CHANGES
First Release
Product status updated to Pre-Production
Corrected DAC description 4-bit to 8bit
Corrected temperature range to -40
Corrected PGAFS characteristics
Corrected Supply currents
Added test conditions for TG output
Corrected Clamp timing diagram
Corrected Signal flow summary (removed INVOP description)
Corrected Channel ID description INP to IN
Corrected TG MASK description
Corrected Register Map (PGAFS)
Update to Recommended External Component Values
– (C9)
0.1uF changed to 0.01uF
Corrected Parameter name and Register name for RLCDAC
Corrected RLCDAC resolution
Added channel to channel offset matching specifcation
Corrected offset DAC INL DNL spec
Corrected supply current for full power down mode
Updated timing specificationCorrected figure for ADC INPUT
BLACK LEVEL ADJUST
Corrected figure for overall signal flow
Added description for ADC, PGA Bias Current Control.
Added description for PLL DLL setup
Added description for 3pair LVDS format
Added LVDS output order
Corrected TG timing diagram
Added EXTENDED REGISTERES
Corrected description for R28
Corrected description for R128,R129
Corrected description of conversion rate
Corrected description of reference DAC resolution
Updated test condition for output noise specification
Corrected device ID descriptions (Table 2 and Table 3)
Corrected MCLK High/Low period
Corrected RESET CLAMPING description
Corrected CDS/Non-CDS PROCESSING description
Updated PLL and DLL setting table
Corrected TG-master/slave mode timing chart
Added TGSYNC low period specification
Added description for LINE BY LINE operation
Added description for TEST PATTERN GENERATOR
Added description for Register setting procedure
PAGE
1
5,8
9,10
11
11
24
27
30
34
41,48
124
10,41
10
9
10
11
15,17,36-38
21
22
22
23
29-33
34
36,37
54,131
65
83
1
1
9
13,14
15
18,19
20
23
39,40
40
51,52,62,79
53,54,76
55~61
152 Rev 4.5
DATE
22/05/14
19/08/2014
20/10/2015
REV
4.2
4.3
4.4
ORIGINATOR
AA
AA
PH
PH
CHANGES
Added data latency specification
Updated tPER, tMCLKH and tMCLKL description
Added LVDS synchronous output description
Removed tPER and tMCLKD description
Removed tTRGD and tPCKD description
Updated Data trigger timing delay specification
Corrected Trigger data description
Corrected TG MASK TIMING description
Added description of Data Output Configuration
Removed register description of SEL_PCK9,10,11
Corrected register description of SEL_PCK7,8
Corrected pin name (PO0~PO9)
Test limit (min/max) conditions added in Elec Chars
Signal timing limits added
Amendment to LVDS_AMP description
Electrical characteristics updated
27/11/2015 4.5
WM8235
15
PAGE
15
35
37,39
40
41
42
46
64,65
69,110,111
110
5,66,78~80
8-10
15, 39
64, 74
8-10
Rev 4.5
153
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