Datasheet RL78/G14

Datasheet RL78/G14
Datasheet
RL78/G14
R01DS0053EJ0100
Rev. 1.00
Feb 21, 2012
RENESAS MCU
True Low Power Platform (as low as 66 A/MHz, and 0.60 A for RTC + LVD), 1.6 V to 5.5 V
operation, 16 to 256 Kbyte Flash, 44 DMIPS at 32 MHz, for General Purpose Applications
1. OUTLINE
1.1
Features
Ultra-Low Power Technology
• 1.6 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.24 A, (LVD enabled): 0.32 A
• Halt (RTC + LVD): 0.60 A
• Snooze: T.B.D
• Operating: 66 A/MHz
16-bit RL78 CPU Core
• Delivers 44 DMIPS at maximum operating frequency of
32 MHz
• Instruction execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC architecture (Harvard) with 3-stage pipeline
• Multiply signed & unsigned: 16 x 16 to 32-bit result in 1
clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Code Flash Memory
• Density: 16 KB to 256 KB
• Block size: 1KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with secure boot swap function and
flash shield window function
Data Flash Memory
• Data flash with background operation
• Data flash size: 4 KB to 8 KB size options
• Erase cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
RAM
• 2.5 KB to 24 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 32 MHz with +/- 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (-20°C to 85°C)
• Pre-configured settings: 64 MHz,48 MHz,32 MHz,
24 MHz, 16 MHz, 12 MHz, 8 MHz, 4 MHz & 1 MHz
• 64 MHz, 48 MHz for timer RD
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
General Purpose I/O
• 5 V tolerant, high-current (up to 20 mA per pin)
• Open-drain, on-chip pull-up resistor
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Data Transfer Controller (DTC)
• 39 sources & 24 different settings
• Transfer data: 8 bits/16 bits
• Normal mode and repeat mode
Event Link Controller (ELC)
• Reduce interrupt intervention
• Link 26 events to specified peripheral function
Multiple Communication Interfaces
• Up to 8 x I2C master
• Up to 2 x I2C multi-master
• Up to 8 x CSI/SPI (7-, 8-bit)
• Up to 4 x UART (7-, 8-, 9-bit)
• Up to 1 x LIN
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Motor control timer (3 ph - complementary mode)
• Timer with encoder function: 16-bit, 1 channel
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval timer: 12-bit, 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Rich Analog
• ADC: Up to 20 channels, 10-bit resolution, 2.1 s
•
•
•
•
•
conversion time
Supports 1.6 V
2 x window comparators, with ELC connection
D/A converter: 2 channels, 8-bit resolution
Internal voltage reference (1.45 V)
On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock stop/frequency detection
• ADC self-test
• I/O port read back function (echo)
Operating Ambient Temperature
• Standard: -40°C to + 85°C
• Extended: -40°C to + 105°C <under planning>
Package Type and Pin Count
From 4 mm x 4 mm to 14 mm x 20 mm
QFP: 32, 44, 48, 52, 64, 80,100
QFN: 32, 40, 48
SSOP: 30
LGA: 36, 64
Page 1 of 97
RL78/G14
1. OUTLINE
ROM, RAM capacities
RL78/G14
Flash ROM
192 KB
Data flash
RAM
30 pins
32 pins
36 pins
40 pins
8 KB
20 KB
—
—
—
R5F104EH
128 KB
8 KB
16 KB
R5F104AG
R5F104BG
R5F104CG
R5F104EG
96 KB
8 KB
12 KB
R5F104AF
R5F104BF
R5F104CF
R5F104EF
64 KB
4 KB
5.5 KB Note 1
R5F104AE
R5F104BE
R5F104CE
R5F104EE
48 KB
4 KB
5.5 KB Note 1
R5F104AD
R5F104BD
R5F104CD
R5F104ED
32 KB
4 KB
4 KB
R5F104AC
R5F104BC
R5F104CC
R5F104EC
16 KB
4 KB
2.5 KB
R5F104AA
R5F104BA
R5F104CA
R5F104EA
Flash ROM
Data flash
RAM
RL78/G14
256 KB
8 KB
24 KB
Note 2
44 pins
48 pins
52 pins
64 pins
R5F104FJ
R5F104GJ
R5F104JJ
R5F104LJ
192 KB
8 KB
20 KB
R5F104FH
R5F104GH
R5F104JH
R5F104LH
128 KB
8 KB
16 KB
R5F104FG
R5F104GG
R5F104JG
R5F104LG
96 KB
8 KB
12 KB
R5F104FF
R5F104GF
R5F104JF
R5F104LF
64 KB
4 KB
5.5 KB Note 1
R5F104FE
R5F104GE
R5F104JE
R5F104LE
48 KB
4 KB
5.5 KB Note 1
R5F104FD
R5F104GD
R5F104JD
R5F104LD
32 KB
4 KB
4 KB
R5F104FC
R5F104GC
R5F104JC
R5F104LC
16 KB
4 KB
2.5 KB
R5F104FA
R5F104GA
—
—
Flash ROM
Data flash
RAM
RL78/G14
Note 2
80 pins
100 pins
R5F104MJ
R5F104PJ
256 KB
8 KB
192 KB
8 KB
20 KB
R5F104MH
R5F104PH
128 KB
8 KB
16 KB
R5F104MG
R5F104PG
96 KB
8 KB
12 KB
R5F104MF
R5F104PF
24 KB
Note 1.
This is about 4.5 KB when the self-programming function and data flash function are used.
Note 2.
This is about 23 KB when the self-programming function and data flash function are used.
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Feb 21, 2012
Page 2 of 97
RL78/G14
1.2
1. OUTLINE
Ordering Information
(1/2)
Pin count
30 pins
Package
30-pin plastic SSOP (7.62 mm (300))
Part Number
R5F104AAASP, R5F104ACASP, R5F104ADASP, R5F104AEASP,
R5F104AFASP, R5F104AGASP
R5F104AADSP, R5F104ACDSP, R5F104ADDSP, R5F104AEDSP,
R5F104AFDSP, R5F104AGDSP
32 pins
32-pin plastic WQFN (fine pitch) (5 × 5)
R5F104BAANA, R5F104BCANA, R5F104BDANA, R5F104BEANA,
R5F104BFANA, R5F104BGANA
R5F104BADNA, R5F104BCDNA, R5F104BDDNA, R5F104BEDNA,
R5F104BFDNA, R5F104BGDNA
32-pin plastic LQFP (7 × 7)
R5F104BAAFP, R5F104BCAFP, R5F104BDAFP, R5F104BEAFP,
R5F104BFAFP, R5F104BGAFP
R5F104BADFP, R5F104BCDFP, R5F104BDDFP, R5F104BEDFP,
R5F104BFDFP, R5F104BGDFP
36 pins
36-pin plastic FLGA (4 × 4)
R5F104CAALA, R5F104CCALA, R5F104CDALA, R5F104CEALA,
R5F104CFALA, R5F104CGALA
R5F104CADLA, R5F104CCDLA, R5F104CDDLA, R5F104CEDLA,
R5F104CFDLA, R5F104CGDLA
40 pins
40-pin plastic WQFN (fine pitch) (6 × 6)
R5F104EAANA, R5F104ECANA, R5F104EDANA, R5F104EEANA,
R5F104EFANA, R5F104EGANA, R5F104EHANA
R5F104EADNA, R5F104ECDNA, R5F104EDDNA, R5F104EEDNA,
R5F104EFDNA, R5F104EGDNA, R5F104EHDNA
44 pins
44-pin plastic LQFP (10 × 10)
R5F104FAAFP, R5F104FCAFP, R5F104FDAFP, R5F104FEAFP,
R5F104FFAFP, R5F104FGAFP, R5F104FHAFP, R5F104FJAFP
R5F104FADFP, R5F104FCDFP, R5F104FDDFP, R5F104FEDFP,
R5F104FFDFP, R5F104FGDFP, R5F104FHDFP, R5F104FJDFP
48 pins
48-pin plastic LQFP (fine pitch) (7 × 7)
R5F104GAAFB, R5F104GCAFB, R5F104GDAFB, R5F104GEAFB,
R5F104GFAFB, R5F104GGAFB, R5F104GHAFB, R5F104GJAFB
R5F104GADFB, R5F104GCDFB, R5F104GDDFB, R5F104GEDFB,
R5F104GFDFB, R5F104GGDFB, R5F104GHDFB, R5F104GJDFB
48-pin plastic WQFN (7 × 7)
R5F104GAANA, R5F104GCANA, R5F104GDANA, R5F104GEANA,
R5F104GFANA, R5F104GGANA, R5F104GHANA, R5F104GJANA
R5F104GADNA, R5F104GCDNA, R5F104GDDNA, R5F104GEDNA,
R5F104GFDNA, R5F104GGDNA, R5F104GHDNA, R5F104GJDNA
52 pins
52-pin plastic LQFP (10 × 10)
R5F104JCAFA, R5F104JDAFA, R5F104JEAFA, R5F104JFAFA,
R5F104JGAFA, R5F104JHAFA, R5F104JJAFA
R5F104JCDFA, R5F104JDDFA, R5F104JEDFA, R5F104JFDFA,
R5F104JGDFA, R5F104JHDFA, R5F104JJDFA
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 3 of 97
RL78/G14
1. OUTLINE
(2/2)
Pin count
64 pins
Package
64-pin plastic LQFP (12 × 12)
Part Number
R5F104LCAFA, R5F104LDAFA, R5F104LEAFA, R5F104LFAFA,
R5F104LGAFA, R5F104LHAFA, R5F104LJAFA
R5F104LCDFA, R5F104LDDFA, R5F104LEDFA, R5F104LFDFA,
R5F104LGDFA, R5F104LHDFA, R5F104LJDFA
64-pin plastic LQFP (fine pitch) (10 × 10)
R5F104LCAFB, R5F104LDAFB, R5F104LEAFB, R5F104LFAFB,
R5F104LGAFB, R5F104LHAFB, R5F104LJAFB
R5F104LCDFB, R5F104LDDFB, R5F104LEDFB, R5F104LFDFB,
R5F104LGDFB, R5F104LHDFB, R5F104LJDFB
64-pin plastic FLGA (5 × 5)
R5F104LCALA, R5F104LDALA, R5F104LEALA, R5F104LFALA,
R5F104LGALA, R5F104LHALA, R5F104LJALA
R5F104LCDLA, R5F104LDDLA, R5F104LEDLA, R5F104LFDLA,
R5F104LGDLA, R5F104LHDLA, R5F104LJDLA
64-pin plastic LQFP (14 × 14)
R5F104LCAFP, R5F104LDAFP, R5F104LEAFP, R5F104LFAFP,
R5F104LGAFP, R5F104LHAFP, R5F104LJAFP
R5F104LCDFP, R5F104LDDFP, R5F104LEDFP, R5F104LFDFP,
R5F104LGDFP, R5F104LHDFP, R5F104LJDFP
80 pins
80-pin plastic LQFP (fine pitch) (12 × 12)
R5F104MFAFB, R5F104MGAFB, R5F104MHAFB, R5F104MJAFB
R5F104MFDFB, R5F104MGDFB, R5F104MHDFB, R5F104MJDFB
80-pin plastic LQFP (14 × 14)
R5F104MFAFA, R5F104MGAFA, R5F104MHAFA, R5F104MJAFA
R5F104MFDFA, R5F104MGDFA, R5F104MHDFA, R5F104MJDFA
100 pins
100-pin plastic LQFP (fine pitch) (14 × 14) R5F104PFAFB, R5F104PGAFB, R5F104PHAFB, R5F104PJAFB
R5F104PFDFB, R5F104PGDFB, R5F104PHDFB, R5F104PJDFB
100-pin plastic LQFP (14 × 20)
R5F104PFAFA, R5F104PGAFA, R5F104PHAFA, R5F104PJAFA
R5F104PFDFA, R5F104PGDFA, R5F104PHDFA, R5F104PJDFA
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 4 of 97
RL78/G14
1. OUTLINE
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14
Part No. R 5 F 1 0 4 L E A x x x F B
Package type:
SP: SSOP, 0.65 mm pitch
FP: LQFP, 0.80 mm pitch
FA: LQFP, 0.65 mm pitch
FB: LQFP, 0.50 mm pitch
NA: WQFN, 0.50 mm pitch
LA: LGA, 0.50 mm pitch
ROM number (Omitted with blank products)
Classification:
A: Consumer applications, operating ambient temperature: -40°C to 85°C
D: Industrial applications, operating ambient temperature: -40°C to 85°C
ROM capacity:
A: 16 KB
C: 32 KB
D: 48 KB
E: 64 KB
F: 96 KB
G: 128 KB
H: 192 KB
J: 256 KB
Pin count:
A: 30-pin
B: 32-pin
C: 36-pin
E: 40-pin
F: 44-pin
G: 48-pin
J: 52-pin
L: 64-pin
M: 80-pin
P: 100-pin
RL78/G14
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 5 of 97
RL78/G14
1.3
1. OUTLINE
Pin Configuration (Top View)
1.3.1
30-pin products
• 30-pin plastic SSOP (7.62 mm (300))
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0
P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P60/SCLA0
P61/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Note
Mounted on the 96 KB or more code flash memory products.
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
P21/ANI1/AVREFM
P22/ANI2/ANO0 Note
P23/ANI3
P147/ANI18/VCOUT1 Note
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/SCK00/SCL00/TRJO0
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 6 of 97
RL78/G14
1.3.2
1. OUTLINE
32-pin products
• 32-pin plastic WQFN (fine pitch) (5 × 5)
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
• 32-pin plastic LQFP (7 × 7)
exposed die pad
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
1 2 3 4 5 6 7 8
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/SCK00/SCL00/TRJO0
P70
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P62/SSI00
P61/SDAA0
P60/SCLA0
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P147/ANI18/VCOUT1 Note
P23/ANI3/ANO1 Note
P22/ANI2/ANO0 Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0
P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
Note
Mounted on the 96 KB or more code flash memory products.
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
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RL78/G14
1.3.3
1. OUTLINE
36-pin products
• 36-pin plastic FLGA (4 × 4)
Top View
Bottom View
6
5
4
3
2
1
A
B
C
D
E
F
F
E
D
C
B
A
INDEX MARK
A
P60/SCLA0
B
C
P121/X1
VDD
D
P122/X2/EXCLK
E
P137/INTP0
F
P40/TOOL0
6
6
5
P62/SSI00
VSS
REGC
P120/ANI19/
RESET
VCOUT0 Note
P72/SO21
4
3
P61/SDAA0
P71/SI21/
P14/RxD2/SI20/
SDA21
SDA20/TRDIOD0/ INTP4/PCLBUZ0/ TRGCLKA/
P31/TI03/TO03/
P00/TI00/TxD1/
RxD1/TRGCLKB/
(SCLA0)
(TRJIO0)
(TRJO0)
TRJIO0
P01/TO00/
P50/INTP1/
P70/SCK21/
P15/PCLBUZ1/
P22/ANI2/
P20/ANI0/
P21/ANI1/
SI00/RxD0/
SCL21
SCK20/SCL20/
ANO0 Note
AVREFP
AVREFM
TOOLRxD/
TRDIOB0/
SDA00/TRGIOA/
(SDAA0)
5
4
3
(TRJO0)
2
P30/INTP3/
P16/TI01/TO01/
P12/SO11/
P11/SI11/
SCK00/SCL00/
INTP5/TRDIOC0/
TRDIOB1/
SDA11/
TRJO0
IVREF0 Note/
IVREF1 Note
TRDIOC1
P24/ANI4
P23/ANI3/
ANO1 Note
2
(RXD0)
1
P51/INTP2/
P17/TI02/TO02/
P13/TxD2/
P10/SCK11/
P147/ANI18/
SO00/TxD0/
TRDIOA0/
SO20/TRDIOA1/
SCL11/
VCOUT1 Note
TOOLTxD/
TRDCLK0/
IVCMP1 Note
TRDIOD1
TRGIOB
IVCMP0 Note/
P25/ANI5
1
(TXD0)
A
B
C
D
Note
Mounted on the 96 KB or more code flash memory products.
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
E
F
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
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RL78/G14
1.3.4
1. OUTLINE
40-pin products
P147/ANI18/VCOUT1 Note
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
• 40-pin plastic WQFN (fine pitch) (6 × 6)
30 29 28 27 26 25 24 23 22 21
20
31
exposed die pad 19
32
18
33
17
34
16
35
15
36
14
37
13
38
12
39
11
40
1 2 3 4 5 6 7 8 9 10
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P62/SSI00
P61/SDAA0
P60/SCLA0
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1 Note
P22/ANI2/ANO0 Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1/TRGCLKB/TRJIO0
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
Note
Mounted on the 96 KB or more code flash memory products.
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
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RL78/G14
1.3.5
1. OUTLINE
44-pin products
P147/ANI18/VCOUT1 Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
• 44-pin plastic LQFP (10 × 10)
34
35
36
37
38
39
40
41
42
43
44
33 32 31 30 29 28 27 26 25 24 23
22
21
20
19
18
17
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P63
P62/SSI00
P61/SDAA0
P60/SCLA0
P41
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1 Note
P22/ANI2/ANO0 Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1/TRGCLKB/TRJIO0
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
Note
Mounted on the 96 KB or more code flash memory products.
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 10 of 97
RL78/G14
1.3.6
1. OUTLINE
48-pin products
P24/ANI4
P25/ANI5
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0 Note
P23/ANI3/ANO1 Note
P26/ANI6
P27/ANI7
P147/ANI18/VCOUT1 Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P60/SCLA0
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P61/SDAA0
P62/SSI00
P63
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P120/ANI19/VCOUT0 Note
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P01/TO00/RxD1/TRGCLKB/TRJIO0
P130
P140/PCLBUZ0/INTP6
• 48-pin plastic LQFP (fine pitch) (7 × 7)
Note
Mounted on the 96 KB or more code flash memory products.
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 11 of 97
RL78/G14
1. OUTLINE
P24/ANI4
P25/ANI5
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0 Note
P23/ANI3/ANO1 Note
P26/ANI6
P27/ANI7
P147/ANI18/VCOUT1 Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P60/SCLA0
36 35 34 33 32 31 30 29 28 27 26 25
24
37
exposed die pad 23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P61/SDAA0
P62/SSI00
P63
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P120/ANI19/VCOUT0 Note
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P01/TO00/RxD1/TRGCLKB/TRJIO0
P130
P140/PCLBUZ0/INTP6
• 48-pin plastic WQFN (7 × 7)
Note
Mounted on the 96 KB or more code flash memory products.
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 12 of 97
RL78/G14
1.3.7
1. OUTLINE
52-pin products
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P12/SO11/TRDIOB1/IVREF1 Note
P11/SI11/SDA11/TRDIOC1
P146
P10/SCK11/SCL11/TRDIOD1
P147/ANI18/VCOUT1 Note
• 52-pin plastic LQFP (10 × 10)
39 38 37 36 35 34 33 32 31 30 29 28 27
P25/ANI5
42
24
P72/KR2/SO21
P24/ANI4
43
23
P73/KR3/SO01
P23/ANI3/ANO1 Note
44
22
P74/KR4/INTP8/SI01/SDA01
P22/ANI2/ANO0 Note
45
21
P75/KR5/INTP9/SCK01/SCL01
P21/ANI1/AVREFM
46
20
P76/KR6/INTP10/(RXD2)
P20/ANI0/AVREFP
47
19
P77/KR7/INTP11/(TXD2)
P130
48
18
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P03/ANI16/RxD1
49
17
P63
P02/ANI17/TxD1
50
16
P62/SSI00
P01/TO00/TRGCLKB/TRJIO0
51
15
P61/SDAA0
P00/TI00/TRGCLKA/(TRJO0)
52
14
P60/SCLA0
9 10 11 12 13
VDD
8
VSS
7
REGC
6
5
P121/X1
3 4
P40/TOOL0
2
P41/(TRJIO0)
1
P122/X2/EXCLK
P71/KR1/SI21/SDA21
P137/INTP0
25
P123/XT1
P70/KR0/SCK21/SCL21
41
RESET
P124/XT2/EXCLKS
26
P26/ANI6
P140/PCLBUZ0/INTP6
40
P120/ANI19/VCOUT0 Note
P27/ANI7
Note
Mounted on the 96 KB or more code flash memory products.
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 13 of 97
RL78/G14
1.3.8
1. OUTLINE
64-pin products
• 64-pin plastic LQFP (14 × 14)
• 64-pin plastic LQFP (12 × 12)
P147/ANI18/VCOUT1 Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(SI00)/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(SO00)/(TXD0)
P55/(PCLBUZ1)/(SCK00)/(INTP4)
P54/(INTP3)
P53/(INTP2)
P52/(INTP1)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
• 64-pin plastic LQFP (fine pitch) (10 × 10)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
60
61
62
63
64
22
21
20
19
18
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P05/(INTP10)
P06/(INTP11)/(TRJIO0)
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3/SO01
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63
P62/SSI00
P61/SDAA0
P60/SCLA0
P120/ANI19/VCOUT0 Note
P43/(INTP9)
P42/(INTP8)
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1 Note
P22/ANI2/ANO0 Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
Note
Mounted on the 96 KB or more code flash memory products.
Caution 1. Make EVSS0 pin the same potential as VSS pin.
Caution 2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the V DD and EVDD0 pins and connect the V SS and EV SS0 pins to
separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 14 of 97
RL78/G14
1. OUTLINE
• 64-pin plastic FLGA (5 × 5)
Top View
Bottom View
8
7
6
5
4
3
2
1
A B C D E F G H
H G F E D C B A
INDEX MARK
A
8
B
EVSS0
EVDD0
C
P121/X1
D
P122/X2/
E
P137/INTP0
F
P123/XT1
P60/SCLA0
VDD
VSS
REGC
RESET
P61/SDAA0
P62/SSI00
P63
P40/TOOL0
P41/(TRJIO0)
H
P120/ANI19/
EXCLKS
VCOUT0 Note
P01/TO00/
P00/TI00/
P140/
TRGCLKB/
TRGCLKA/
PCLBUZ0/
TRJIO0
(TRJO0)
INTP6
P02/ANI17/
P141/
SO10/TxD1
PCLBUZ1/
EXCLK
7
G
P124/XT2/
P43/(INTP9)
6
8
7
6
INTP7
P77/KR7/
5
P31/TI03/
P53/(INTP2)
P42/(INTP8)
INTP11/(TXD2) TO03/INTP4/
(PCLBUZ0)/
P03/ANI16/
P04/SCK10/
SI10/RxD1/
SCL10
P130
P20/ANI0/
AVREFP
SDA10
5
(TRJIO0)
4
P75/KR5/
P76/KR6/
P16/TI01/
P21/ANI1/
P22/ANI2/
P23/ANI3/
INTP9/
INTP10/
TO01/INTP5/
AVREFM
ANO0 Note
ANO1 Note
SCK01/
(RXD2)
TRDIOC0/
P52/(INTP1)
P54/(INTP3)
SCL01
4
IVREF0 Note/
(SI00)/(RXD0)
3
P70/KR0/
P73/KR3/
P74/KR4/
SO01
INTP8/SI01/
P17/TI02/TO02/ P15/SCK20/
TRDIOA0/
SCL20/
P12/SO11/
SCK21/
SDA01
TRDCLK0/
TRDIOB0/
IVREF1 Note/
IVCMP0 Note/
(SDAA0)
(INTP5)
SCL21
P24/ANI4
P26/ANI6
TRDIOB1/
3
(SO00)/(TXD0)
2
P30/INTP3/
P72/KR2/
P71/KR1/
P06/(INTP11)/
P14/RxD2/
P11/SI11/
RTC1HZ/
SO21
SI21/SDA21
(TRJIO0)
SI20/SDA20/
SDA11/
TRDIOD0/
TRDIOC1
SCK00/
SCL00/TRJO0
P05/(INTP10)
1
P25/ANI5
P27/ANI7
2
(SCLA0)
P50/INTP1/
P51/INTP2/
P55/
P13/TxD2/
P10/SCK11/
SI00/RxD0/
SO00/TxD0/
(PCLBUZ1)/
SO20/
SCL11/
TOOLRxD/
TOOLTxD/
(SCK00)/
TRDIOA1/
TRDIOD1
SDA00/
TRGIOB
(INTP4)
IVCMP1 Note
C
D
P146
P147/ANI18/
VCOUT1 Note
1
TRGIOA/
(TRJO0)
A
Note
B
E
F
G
H
Mounted on the 96 KB or more code flash memory products.
Caution 1. Make EVSS0 pin the same potential as VSS pin.
Caution 2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
(Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 15 of 97
RL78/G14
1. OUTLINE
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the V DD and EVDD0 pins and connect the V SS and EV SS0 pins to
separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 16 of 97
RL78/G14
1.3.9
1. OUTLINE
80-pin products
• 80-pin plastic LQFP (14 × 14)
P153/ANI11
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
P146
P111
P110/(INTP11)
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0)
P55/(PCLBUZ1)/(SCK00)/(INTP4)
P54/SCK31/SCL31/(INTP3)
P53/SI31/SDA31/(INTP2)
P52/SO31/(INTP1)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
• 80-pin plastic LQFP (fine pitch) (12 × 12)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1
P22/ANI2/ANO0
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
P142/SCK30/SCL30
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P05
P06/(TRJIO0)
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63/SDAA1
P62/SSI00/SCLA1
P61/SDAA0
P60/SCLA0
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19/VCOUT0
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01/(INTP9)
P42/(INTP8)
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Caution
Make EVSS0 pin the same potential as VSS pin.
Caution 1. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
Caution 2. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the V DD and EVDD0 pins and connect the V SS and EV SS0 pins to
separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 17 of 97
RL78/G14
1.3.10
1. OUTLINE
100-pin products
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P87/(INTP9)
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
P146/(INTP4)
P111
P110/(INTP11)
P101
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/SO00/TxD0/TOOLTxD/TRGIOB
P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
EVDD1
• 100-pin plastic LQFP (fine pitch) (14 × 14)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TXD1)
P81/(SI10)/(RXD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVSS1
P05
P06/(TRJIO0)
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63/SDAA1
P62/SSI00/SCLA1
P142/SCK30/SCL30
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19/VCOUT0
P47/INTP2
P46/INTP1
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
P60/SCLA0
P61/SDAA0
P156/ANI14
P155/ANI13
P154/ANI12
P153/ANI11
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1
P22/ANI2/ANO0
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P145
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
Caution
Make EVSS0, EVSS1 pins the same potential as VSS pin.
Caution 1. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
Make EVDD1 pin the same potential as EVDD0 pin.
Caution 2. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1
pins to separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 18 of 97
RL78/G14
1. OUTLINE
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
P142/SCK30/SCL30
P143/SI30/RxD3/SDA30
P144/SO30/TxD3
P145
P00/TI00/TRGCLKA/(TRJO0)
P01/TO00/TRGCLKB/TRJIO0
P02/ANI17/SO10/TxD1
P03/ANI16/SI10/RxD1/SDA10
P04/SCK10/SCL10
P102
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0
P23/ANI3/ANO1
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
• 100-pin plastic LQFP (fine pitch) (14 × 20)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P146/(INTP4)
P111
P110/(INTP11)
P101
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/SO00/TxD0/TOOLTxD/TRGIOB
P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P60/SCLA0
P61/SDAA0
P62/SSI00/SCLA1
P63/SDAA1
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P64/TI10/TO10
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P77/KR7/INTP11/(TXD2)
P76/KR6/INTP10/(RXD2)
P75/KR5/INTP9
P74/KR4/INTP8
P73/KR3
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P06/(TRJIO0)
P05
EVSS1
P80/(SCK10)/(SCL10)
P81/(SI10)/(RXD1)/(SDA10)
P82/(SO10)/(TXD1)
P83
P84/(INTP7)
P85/(INTP7)
P86/(INTP8)
P87/(INTP9)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
EVDD1
P120/ANI19/VCOUT0
P47/INTP2
P46/INTP1
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
Caution
Make EVSS0, EVSS1 pins the same potential as VSS pin.
Caution 1. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
Make EVDD1 pin the same potential as EVDD0 pin
Caution 2. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1
pins to separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1
(PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 19 of 97
RL78/G14
1.4
1. OUTLINE
Pin Identification
ANI0 to ANI14,:
Analog input
RxD0 to RxD3:
Receive data
SCK00, SCK01, SCK10,: Serial clock input/output
ANI16 to ANI20
ANO0, ANO1:
Analog output
SCK11, SCK20, SCK21,
AVREFM:
A/D converter reference
SCK30, SCK31
potential ( side) input
SCLA0, SCLA1, SCL00,: Serial clock input/output
AVREFP:
A/D converter reference
SCL01, SCL10, SCL11,
potential (+ side) input
SCL20, SCL21, SCL30,
EVDD0, EVDD1:
Power supply for port
SCL31
EVSS0, EVSS1:
Ground for port
SDAA0, SDAA1, SDA00,: Serial data input/output
EXCLK:
External clock input
SDA01, SDA10, SDA11,
(main system clock)
SDA20, SDA21, SDA30,
EXCLKS:
External clock input
SDA31
(sub system clock)
SI00, SI01, SI10, SI11,:
External interrupt input
SI20, SI21, SI30, SI31
IVCMP0, IVCMP1:
Comparator input
SO00, SO01, SO10,:
IVREF0, IVREF1:
Comparator reference input
SO11, SO20, SO21,
KR0 to KR7:
Key return
SO30, SO31
P00 to P06:
Port 0
SSI00:
Serial interface chip select input
P10 to P17:
Port 1
TI00 to TI03,:
Timer input
P20 to P27:
Port 2
TI10 to TI13
P30, P31:
Port 3
TO00 to TO03,:
P40 to P47:
Port 4
TO10 to TO13, TRJO0
P50 to P57:
Port 5
TOOL0:
Data input/output for tool
P60 to P67:
Port 6
TOOLRxD, TOOLTxD:
Data input/output for external device
P70 to P77:
Port 7
TRDCLK0, TRGCLKA,:
Timer external input clock
P80 to P87:
Port 8
TRGCLKB
P100 to P102:
Port 10
TRDIOA0, TRDIOB0,:
P110, P111:
Port 11
TRDIOC0, TRDIOD0,
P120 to P124:
Port 12
TRDIOA1, TRDIOB1,
P130, P137:
Port 13
TRDIOC1, TRDIOD1,
P140 to P147:
Port 14
TRGIOA, TRGIOB, TRJIO0
P150 to P156:
Port 15
TxD0 to TxD3:
Transmit data
PCLBUZ0, PCLBUZ1:
Programmable clock
VCOUT0, VCOUT1:
Comparator output
output/buzzer output
VDD:
Power supply
REGC:
Regulator capacitance
VSS:
Ground
RESET:
Reset
X1, X2:
Crystal oscillator (main system clock)
RTC1HZ:
Real-time clock correction clock
XT1, XT2:
Crystal oscillator (subsystem clock)
INTP0 to INTP11:
Serial data input
Serial data output
Timer output
Timer input/output
(1 Hz) output
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 20 of 97
RL78/G14
1.5
1.5.1
1. OUTLINE
Block Diagram
30-pin products
TIMER ARRAY
UNIT (4ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
PORT 0
2
P00, P01
PORT 1
8
P10 to P17
PORT 2
4
P20 to P23
PORT 3
2
P30, P31
PORT 4
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
P40
PORT 5
2
P50, P51
PORT 6
2
P60, P61
2
P120
P121, P122
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
PORT 12
INTERVAL
TIMER
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 14
REAL-TIME
CLOCK
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P31
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
P137
P147
4
ANI0/P20 to
ANI3/P23
4
ANI16/P01, ANI17/P00
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
ON-CHIP DEBUG
VDD
VSS
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
UART2
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCL20/P15
SDA20/P14
IIC20
TOOLRxD/P50,
TOOLTxD/P51
TOOL0/P40
RESET
X1/P121
X2/EXCLK/P122
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
2
PCLBUZ0/P31,
PCLBUZ1/P15
RxD0/P50 (LINSEL)
INTP0/P137
2
DATA TRANSFER
CONTROL
INTERRUPT
CONTROL
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
2
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
D/A CONVERTERNote
ANO0/P22
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 21 of 97
RL78/G14
1.5.2
1. OUTLINE
32-pin products
TIMER ARRAY
UNIT (4ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
PORT 0
2
P00, P01
PORT 1
8
P10 to P17
PORT 2
4
P20 to P23
PORT 3
2
P30, P31
PORT 4
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
PORT 5
2
P50, P51
PORT 6
3
P60 to P62
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
P40
PORT 7
PORT 12
INTERVAL
TIMER
P70
2
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
P137
PORT 14
REAL-TIME
CLOCK
P147
4
ANI0/P20 to
ANI3/P23
4
ANI16/P01, ANI17/P00
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
P120
P121, P122
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
VSS
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
UART2
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCL20/P15
SDA20/P14
IIC20
TOOLRxD/P50,
TOOLTxD/P51
RESET
X1/P121
X2/EXCLK/P122
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P31,
PCLBUZ1/P15
RxD0/P50 (LINSEL)
INTP0/P137
2
DATA TRANSFER
CONTROL
INTERRUPT
CONTROL
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
2
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 22 of 97
RL78/G14
1.5.3
1. OUTLINE
36-pin products
TIMER ARRAY
UNIT (4ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
PORT 0
2
P00, P01
PORT 1
8
P10 to P17
PORT 2
6
P20 to P25
PORT 3
2
P30, P31
PORT 4
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
PORT 5
2
P50, P51
PORT 6
3
P60 to P62
PORT 7
3
P70 to P72
2
P120
P121, P122
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
P40
PORT 12
INTERVAL
TIMER
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 14
REAL-TIME
CLOCK
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
P137
P147
6
ANI0/P20 to
ANI5/P25
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
VSS
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
UART2
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCK21/P70
SI21/P71
SO21/P72
CSI21
CLOCK OUTPUT
CONTROL
SCL20/P15
SDA20/P14
IIC20
DATA TRANSFER
CONTROL
SCL21/P70
SDA21/P71
IIC21
TOOLRxD/P50,
TOOLTxD/P51
RESET
X1/P121
X2/EXCLK/P122
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
2
PCLBUZ0/P31,
PCLBUZ1/P15
RxD0/P50 (LINSEL)
INTP0/P137
2
INTERRUPT
CONTROL
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
2
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 23 of 97
RL78/G14
1.5.4
1. OUTLINE
40-pin products
TIMER ARRAY
UNIT (4ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
PORT 0
2
P00, P01
PORT 1
8
P10 to P17
PORT 2
7
P20 to P26
PORT 3
2
P30, P31
PORT 4
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
PORT 5
2
P50, P51
PORT 6
3
P60 to P62
PORT 7
4
P70 to P73
4
P120
P121 to P124
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
P40
PORT 12
INTERVAL
TIMER
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 14
REAL-TIME
CLOCK
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
P137
P147
7
ANI0/P20 to
ANI6/P26
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
KEY RETURN
4
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR3/P73
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
VSS
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
UART2
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCK21/P70
SI21/P71
SO21/P72
CSI21
CLOCK OUTPUT
CONTROL
SCL20/P15
SDA20/P14
IIC20
DATA TRANSFER
CONTROL
SCL21/P70
SDA21/P71
IIC21
TOOLRxD/P50,
TOOLTxD/P51
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
2
PCLBUZ0/P31,
PCLBUZ1/P15
RxD0/P50 (LINSEL)
INTP0/P137
2
INTERRUPT
CONTROL
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
2
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 24 of 97
RL78/G14
1.5.5
1. OUTLINE
44-pin products
TIMER ARRAY
UNIT (4ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
2
P00, P01
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
4
P70 to P73
4
P120
P121 to P124
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
PORT 0
PORT 12
INTERVAL
TIMER
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 14
REAL-TIME
CLOCK
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
P137
2
P146, P147
8
ANI0/P20 to
ANI7/P27
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
KEY RETURN
4
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR3/P73
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
VSS
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
UART2
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCK21/P70
SI21/P71
SO21/P72
CSI21
CLOCK OUTPUT
CONTROL
SCL20/P15
SDA20/P14
IIC20
DATA TRANSFER
CONTROL
SCL21/P70
SDA21/P71
IIC21
TOOLRxD/P50,
TOOLTxD/P51
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
2
PCLBUZ0/P31,
PCLBUZ1/P15
RxD0/P50 (LINSEL)
INTP0/P137
2
INTERRUPT
CONTROL
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
2
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 25 of 97
RL78/G14
1.5.6
1. OUTLINE
48-pin products
TIMER ARRAY
UNIT (4ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
2
P00, P01
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
6
P70 to P75
4
P120
P121 to P124
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
PORT 0
PORT 12
INTERVAL
TIMER
P130
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 14
REAL-TIME
CLOCK
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P75
SI01/P74
SO01/P73
CSI01
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
3
P140,
P146, P147
8
ANI0/P20 to
ANI7/P27
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
KEY RETURN
6
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR5/P75
POR/LVD
CONTROL
RAM
RESET CONTROL
IIC01
SCL11/P10
SDA11/P11
IIC11
VSS
SCK21/P70
SI21/P71
SO21/P72
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
SCLA0/P60
2
CLOCK OUTPUT
CONTROL
CSI20
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD0/P50 (LINSEL)
INTP0/P137
BUZZER OUTPUT
UART2
SCK20/P15
SI20/P14
SO20/P13
TOOLRxD/P50,
TOOLTxD/P51
SDAA0/P61
SERIAL
INTERFACE IICA0
SERIAL ARRAY
UNIT1 (2ch)
TOOL0/P40
ON-CHIP DEBUG
VDD
SCL01/P75
SDA01/P74
RxD2/P14
TxD2/P13
P137
PCLBUZ0/P140,
PCLBUZ1/P15
DATA TRANSFER
CONTROL
2
INTERRUPT
CONTROL
2
INTP5/P16
INTP6/P140
EVENT LINK
CONTROLLER
2
BCD
ADJUSTMENT
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
D/A CONVERTERNote
INTP8/P74,
INTP9/P75
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 26 of 97
RL78/G14
1.5.7
1. OUTLINE
52-pin products
TIMER ARRAY
UNIT (4ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
4
P00 to P03
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
8
P70 to P77
4
P120
P121 to P124
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
PORT 0
PORT 12
INTERVAL
TIMER
P130
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 14
REAL-TIME
CLOCK
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P03
TxD1/P02
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P75
SI01/P74
SO01/P73
CSI01
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
3
8
ANI0/P20 to
ANI7/P27
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
P140,
P146, P147
KEY RETURN
8
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR7/P77
POR/LVD
CONTROL
RAM
RESET CONTROL
IIC01
SCL11/P10
SDA11/P11
IIC11
VSS
SCK21/P70
SI21/P71
SO21/P72
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
SCLA0/P60
2
CLOCK OUTPUT
CONTROL
CSI20
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD0/P50 (LINSEL)
INTP0/P137
BUZZER OUTPUT
UART2
SCK20/P15
SI20/P14
SO20/P13
TOOLRxD/P50,
TOOLTxD/P51
SDAA0/P61
SERIAL
INTERFACE IICA0
SERIAL ARRAY
UNIT1 (2ch)
TOOL0/P40
ON-CHIP DEBUG
VDD
SCL01/P75
SDA01/P74
RxD2/P14
TxD2/P13
P137
PCLBUZ0/P140,
PCLBUZ1/P15
DATA TRANSFER
CONTROL
2
INTERRUPT
CONTROL
2
INTP5/P16
INTP6/P140
EVENT LINK
CONTROLLER
4
BCD
ADJUSTMENT
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
D/A CONVERTERNote
INTP8/P74 to
INTP11/P77
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 27 of 97
RL78/G14
1.5.8
1. OUTLINE
64-pin products
TIMER ARRAY
UNIT (4ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
7
P00 to P06
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
4
P40 to P43
PORT 5
6
P50 to P55
PORT 6
4
P60 to P63
PORT 7
8
P70 to P77
4
P120
P121 to P124
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
PORT 0
PORT 12
INTERVAL
TIMER
P130
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 14
REAL-TIME
CLOCK
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P03
TxD1/P02
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P75
SI01/P74
SO01/P73
CSI01
SCK10/P04
SI10/P03
SO10/P02
CSI10
SCK11/P10
SI11/P11
SO11/P12
CSI11
IIC00
IIC01
SCL10/P04
SDA10/P03
IIC10
IIC11
4
AVREFP/P20
AVREFM/P21
CODE FLASH MEMORY
KEY RETURN
8
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR7/P77
POR/LVD
CONTROL
RAM
VDD,
VSS, TOOLRxD/P50,
EVDD0 EVSS0 TOOLTxD/P51
TOOL0/P40
SDAA0/P61
SERIAL
INTERFACE IICA0
SYSTEM
CONTROL
XT1/P123
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
SCLA0/P60
RxD0/P50 (LINSEL)
INTP0/P137
2
CLOCK OUTPUT
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
BUZZER OUTPUT
SERIAL ARRAY
UNIT1 (2ch)
Note
ANI0/P20 to
ANI7/P27
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
RL78 CPU CORE
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
P140, P141,
P146, P147
8
ON-CHIP DEBUG
SCL01/P75
SDA01/P74
RxD2/P14
TxD2/P13
4
RESET CONTROL
SCL00/P30
SDA00/P50
SCL11/P10
SDA11/P11
P137
2
PCLBUZ0/P140,
PCLBUZ1/P141
UART2
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
INTP5/P16
DATA TRANSFER
CONTROL
2
INTP6/P140,
INTP7/P141
4
INTP8/P74 to
INTP11/P77
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCK21/P70
SI21/P71
SO21/P72
CSI21
SCL20/P15
SDA20/P14
IIC20
COMPARATORNote
(2ch)
SCL21/P70
SDA21/P71
IIC21
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
EVENT LINK
CONTROLLER
D/A CONVERTERNote
BCD
ADJUSTMENT
ANO0/P22
ANO1/P23
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 28 of 97
RL78/G14
1.5.9
1. OUTLINE
80-pin products
TIMER ARRAY
UNIT0 (4ch)
TI00/P00
TO00/P01
TIMER ARRAY
UNIT1 (4ch)
ch0
TI10/TO10/P64
ch1
TI11/TO11/P65
ch2
TI12/TO12/P66
ch3
TI13/TO13/P67
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
7
P00 to P06
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
6
P40 to P45
PORT 5
6
P50 to P55
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
PORT 0
PORT 10
INTERVAL
TIMER
PORT 11
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P03
TxD1/P02
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P43
SI01/P44
SO01/P45
CSI01
SCK10/P04
SI10/P03
SO10/P02
CSI10
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL01/P43
SDA01/P44
IIC01
SCL10/P04
SDA10/P03
IIC10
SCL11/P10
SDA11/P11
IIC11
A/D CONVERTER
P100
2
P110, P111
4
P120
P121 to P124
8
ANI0/P20 to ANI7/P27
4
ANI8/P150 to ANI11/P153
PORT 12
5
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
PORT 13
AVREFP/P20
AVREFM/P21
PORT 14
7
P140 to P144,
P146, P147
PORT 15
4
P150 to P153
KEY RETURN
8
KR0/P70 to
KR7/P77
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
DATA FLASH MEMORY
P130
P137
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
RAM
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
VDD,
VSS, TOOLRxD/P50,
EVDD0 EVSS0 TOOLTxD/P51
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
SERIAL
INTERFACE IICA0
SDAA0/P61
SERIAL
INTERFACE IICA1
SDAA1/P63
REGC
RxD0/P50 (LINSEL)
INTP0/P137
SCLA0/P60
2
SERIAL ARRAY
UNIT1 (4ch)
RxD2/P14
TxD2/P13
SCLA1/P62
INTERRUPT
CONTROL
INTP5/P16
UART2
BUZZER OUTPUT
RxD3/P143
TxD3/P144
UART3
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCK21/P70
SI21/P71
SO21/P72
CSI21
SCK30/P142
SI30/P143
SO30/P144
CSI30
SCK31/P54
SI31/P53
SO31/P52
CSI31
SCL20/P15
SDA20/P14
IIC20
2
CLOCK OUTPUT
CONTROL
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
PCLBUZ0/P140,
PCLBUZ1/P141
D/A CONVERTER
SCL21/P70
SDA21/P71
IIC21
IIC30
SCL31/P54
SDA31/P53
IIC31
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
2
INTP6/P140,
INTP7/P141
4
INTP8/P74 to
INTP11/P77
ANO0/P22
ANO1/P23
COMPARATOR
(2ch)
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
BCD
ADJUSTMENT
SCL30/P142
SDA30/P143
2
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
Page 29 of 97
RL78/G14
1.5.10
1. OUTLINE
100-pin products
TIMER ARRAY
UNIT0 (4ch)
TI00/P00
TO00/P01
TIMER ARRAY
UNIT1 (4ch)
ch0
TI10/TO10/P64
ch1
TI11/TO11/P65
ch2
TI12/TO12/P66
ch3
TI13/TO13/P67
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
ch0
TRDIOA1/P13 toTRDIOD1/P10
4
ch1
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
INTERVAL
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P03
TxD1/P02
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P43
SI01/P44
SO01/P45
CSI01
SCK10/P04
SI10/P03
SO10/P02
CSI10
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL01/P43
SDA01/P44
IIC01
SCL10/P04
SDA10/P03
IIC10
SCL11/P10
SDA11/P11
IIC11
RxD3/P143
TxD3/P144
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
8
P40 to P47
PORT 5
8
P50 to P57
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
PORT 8
8
P80 to P87
8
PORT 10
3
P100 to P102
A/D CONVERTER
2
P110, P111
4
P120
P121 to P124
ANI0/P20 to ANI7/P27
7
ANI8/P150 to ANI14/P156
PORT 11
5
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
PORT 12
AVREFP/P20
AVREFM/P21
PORT 13
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
DATA FLASH MEMORY
P130
P137
PORT 14
8
PORT 15
7
P150 to P156
8
KR0/P70 to
KR7/P77
POWER ON RESET/
VOLTAGE
DETECTOR
P140 to P147
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD,
VSS, TOOLRxD/P50,
EVDD0, EVSS0, TOOLTxD/P51
EVDD1 EVSS1
SERIAL
INTERFACE IICA0
SDAA0/P61
SERIAL
INTERFACE IICA1
SDAA1/P63
SCLA0/P60
BUZZER OUTPUT
UART3
CSI20
SCK21/P70
SI21/P71
SO21/P72
CSI21
2
CLOCK OUTPUT
CONTROL
SYSTEM
CONTROL
PCLBUZ0/P140,
PCLBUZ1/P141
2
INTERRUPT
CONTROL
SCL21/P70
SDA21/P71
IIC21
SCL30/P142
SDA30/P143
IIC30
SCL31/P54
SDA31/P53
IIC31
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
2
INTP6/P140,
INTP7/P141
4
INTP8/P74 to
INTP11/P77
ANO0/P22
ANO1/P23
COMPARATOR
(2ch)
BCD
ADJUSTMENT
IIC20
2
INTP1/P47,
INTP2/P46
INTP3/P30,
INTP4/P31
INTP5/P16
D/A CONVERTER
CSI30
SCL20/P15
SDA20/P14
REGC
RxD0/P50 (LINSEL)
INTP0/P137
EVENT LINK
CONTROLLER
CSI31
XT1/P123
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
DATA TRANSFER
CONTROL
SCK31/P54
SI31/P53
SO31/P52
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
SCLA1/P62
UART2
SCK20/P15
SI20/P14
SO20/P13
SCK30/P142
SI30/P143
SO30/P144
P00 to P06
KEY RETURN
SERIAL ARRAY
UNIT1 (4ch)
RxD2/P14
TxD2/P13
7
TRJIO0/P01
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
PORT 0
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Page 30 of 97
RL78/G14
1.6
1. OUTLINE
Outline of Functions
[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 16 KB to 64 KB)]
Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H.
(1/2)
30-pin
32-pin
36-pin
40-pin
R5F104Ax
(x = A, C to E)
R5F104Bx
(x = A, C to E)
R5F104Cx
(x = A, C to E)
R5F104Ex
(x = A, C to E)
Code flash memory (KB)
16 to 64
16 to 64
16 to 64
16 to 64
Data flash memory (KB)
4
4
4
4
2.5 to 5.5 Note
2.5 to 5.5 Note
2.5 to 5.5 Note
2.5 to 5.5 Note
Item
RAM (KB)
Memory space
1 MB
Main system
High-speed system
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
clock
clock
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to
oscillator clock (fIH)
5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD =
1.6 to 5.5 V)
Subsystem clock
—
XT1 (crystal) oscillation
32.768 kHz (TYP.):
VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem
—
clock: fSUB = 32.768 kHz
operation)
Instruction set
I/O port
•
•
•
•
•
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
26
28
32
36
CMOS I/O
21
22
26
28
CMOS input
3
3
3
5
CMOS output
—
—
—
—
N-ch open-drain I/O (6
2
3
3
3
V tolerance)
Timer
16-bit timer
8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
1 channel
Timer output
16
(TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
—
1
• 1 Hz
(subsystem clock: fSUB
= 32.768 kHz)
Note
In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 31 of 97
RL78/G14
1. OUTLINE
(2/2)
Item
30-pin
32-pin
36-pin
40-pin
R5F104Ax
(x = A, C to E)
R5F104Bx
(x = A, C to E)
R5F104Cx
(x = A, C to E)
R5F104Ex
(x = A, C to E)
2
2
2
2
Clock output/buzzer output
[30-pin, 32-pin, 36-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
[40-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
Serial interface
8 channels
8 channels
8 channels
9 channels
[30-pin, 32-pin products]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
[36-pin, 40-pin products]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
I2C
bus
Data transfer controller (DTC)
Event link controller (ELC)
1 channel
1 channel
1 channel
1 channel
28 sources
29 sources
Event input: 20
Event trigger output: 7
Vectored interrupt
sources
Internal
24
24
24
24
External
6
6
6
7
—
—
—
4
Key interrupt
Reset
•
•
•
•
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = 40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 32 of 97
RL78/G14
1. OUTLINE
[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 96 KB to 256 KB)]
Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H.
(1/2)
30-pin
32-pin
36-pin
40-pin
R5F104Ax
(x = F, G)
R5F104Bx
(x = F, G)
R5F104Cx
(x = F, G)
R5F104Ex
(x = F to H)
Code flash memory (KB)
96 to 128
96 to 128
96 to 128
96 to 192
Data flash memory (KB)
8
8
8
8
12 to 16
12 to 16
12 to 16
12 to 20
Item
RAM (KB)
Memory space
1 MB
Main system
High-speed system
clock
clock
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to
oscillator clock (fIH)
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD =
1.6 to 5.5 V)
Subsystem clock
—
XT1 (crystal) oscillation
32.768 kHz (TYP.):
VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem
—
clock: fSUB = 32.768 kHz
operation)
Instruction set
I/O port
•
•
•
•
•
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
26
28
32
36
CMOS I/O
21
22
26
28
CMOS input
3
3
3
5
CMOS output
—
—
—
—
N-ch open-drain I/O (6
2
3
3
3
V tolerance)
Timer
16-bit timer
8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
1 channel
Timer output
16
(TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
—
1
• 1 Hz
(subsystem clock: fSUB
= 32.768 kHz)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 33 of 97
RL78/G14
1. OUTLINE
(2/2)
Item
30-pin
32-pin
36-pin
40-pin
R5F104Ax
(x = F, G)
R5F104Bx
(x = F, G)
R5F104Cx
(x = F, G)
R5F104Ex
(x = F to H)
2
2
2
2
Clock output/buzzer output
[30-pin, 32-pin, 36-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
[40-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
8 channels
8 channels
D/A converter
1 channel
2 channels
Comparator
2 channels
Serial interface
8 channels
9 channels
[30-pin, 32-pin products]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
[36-pin, 40-pin products]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
I2C bus
1 channel
1 channel
Data transfer controller (DTC)
28 sources
Event link controller (ELC)
Event input: 20
1 channel
1 channel
29 sources
Event trigger output: 7
Vectored interrupt
sources
Internal
24
24
24
24
External
6
6
6
7
—
—
—
4
Key interrupt
Reset
•
•
•
•
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = 40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 34 of 97
RL78/G14
1. OUTLINE
[44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 16 KB to 64 KB)]
Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H.
(1/2)
44-pin
48-pin
52-pin
64-pin
R5F104Fx
R5F104Gx
R5F104Jx
R5F104Lx
(x = A, C to E)
(x = A, C to E)
(x = C to E)
(x = C to E)
Code flash memory (KB)
16 to 64
16 to 64
32 to 64
32 to 64
Data flash memory (KB)
4
4
4
4
Item
RAM (KB)
2.5 to 5.5
Memory space
Note
2.5 to 5.5
Note
4 to 5.5
Note
4 to 5.5 Note
1 MB
Main system
High-speed system
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
clock
clock
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz
oscillator clock (fIH)
(VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage
operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
• Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port
Total
40
44
48
58
CMOS I/O
31
34
38
48
CMOS input
5
5
5
5
CMOS output
—
1
1
1
N-ch open-drain I/O
4
4
4
4
(6 V tolerance)
Timer
16-bit timer
8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock
1 channel
(RTC)
12-bit interval timer
1 channel
Timer output
16
(TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
Note
In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 35 of 97
RL78/G14
1. OUTLINE
(2/2)
44-pin
Item
48-pin
52-pin
64-pin
R5F104Fx
R5F104Gx
R5F104Jx
R5F104Lx
(x = A, C to E)
(x = A, C to E)
(x = C to E)
(x = C to E)
2
2
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
Serial interface
10 channels
10 channels
12 channels
12 channels
[44-pin products]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[48-pin, 52-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[64-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
1 channel
1 channel
Data transfer controller (DTC)
29 sources
30 sources
Event link controller (ELC)
Event input: 20
I2C bus
1 channel
1 channel
31 sources
Event trigger output: 7
Vectored
Internal
24
24
24
24
interrupt sources
External
7
10
12
13
4
6
8
8
Key interrupt
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset:
1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = 40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 36 of 97
RL78/G14
1. OUTLINE
[44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 96 KB to 256 KB)]
Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H.
(1/2)
44-pin
48-pin
52-pin
64-pin
R5F104Fx
R5F104Gx
R5F104Jx
R5F104Lx
(x = F to H, J)
(x = F to H, J)
(x = F to H, J)
(x = F to H, J)
Code flash memory (KB)
96 to 256
96 to 256
96 to 256
96 to 256
Data flash memory (KB)
8
8
8
8
Item
RAM (KB)
12 to 24
Memory space
Note
12 to 24
Note
12 to 24
Note
12 to 24 Note
1 MB
Main system
High-speed system
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
clock
clock
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz
oscillator clock (fIH)
(VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage
operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
• Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port
Total
40
44
48
58
CMOS I/O
31
34
38
48
CMOS input
5
5
5
5
CMOS output
—
1
1
1
N-ch open-drain I/O
4
4
4
4
(6 V tolerance)
Timer
16-bit timer
8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock
1 channel
(RTC)
12-bit interval timer
1 channel
Timer output
16
(TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
Note
In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used.
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Feb 21, 2012
Page 37 of 97
RL78/G14
1. OUTLINE
(2/2)
44-pin
Item
48-pin
52-pin
64-pin
R5F104Fx
R5F104Gx
R5F104Jx
R5F104Lx
(x = F to H, J)
(x = F to H, J)
(x = F to H, J)
(x = F to H, J)
2
2
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
10 channels
D/A converter
2 channels
Comparator
2 channels
Serial interface
[44-pin products]
10 channels
12 channels
12 channels
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[48-pin, 52-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[64-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
1 channel
1 channel
Data transfer controller (DTC)
29 sources
30 sources
Event link controller (ELC)
Event input: 20
I2C bus
1 channel
1 channel
31 sources
Event trigger output: 7
Vectored
Internal
24
24
24
24
interrupt sources
External
7
10
12
13
4
6
8
8
Key interrupt
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset:
1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = 40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 38 of 97
RL78/G14
1. OUTLINE
[80-pin, 100-pin products (code flash memory 96 KB to 256 KB)]
Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H.
(1/2)
80-pin
100-pin
R5F104Mx
R5F104Px
(x = F to H, J)
(x = F to H, J)
Code flash memory (KB)
96 to 256
96 to 256
Data flash memory (KB)
8
8
Item
RAM (KB)
12 to 24
Memory space
Note
12 to 24 Note
1 MB
Main system
High-speed system
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
clock
clock
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz
oscillator clock (fIH)
(VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage
operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
• Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port
Total
74
92
CMOS I/O
64
82
CMOS input
5
5
CMOS output
1
1
N-ch open-drain I/O
4
4
(6 V tolerance)
Timer
16-bit timer
12 channels
(TAU: 8 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock
1 channel
(RTC)
12-bit interval timer
1 channel
Timer output
20
(TAU: 8, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 13 (TAU: 6, Timer RD: 6, Timer RG: 1)
RTC output
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
Note
In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 39 of 97
RL78/G14
1. OUTLINE
(2/2)
80-pin
Item
100-pin
R5F104Mx
R5F104Px
(x = F to H, J)
(x = F to H, J)
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
17 channels
20 channels
D/A converter
2 channels
2 channels
Comparator
2 channels
2 channels
Serial interface
[80-pin, 100-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
2 channels
2 channels
Data transfer controller (DTC)
39 sources
39 sources
Event link controller (ELC)
Event input: 26
I2C bus
Event trigger output: 9
Vectored
Internal
32
32
interrupt sources
External
13
13
8
8
Key interrupt
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset:
1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = 40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 40 of 97
RL78/G14
2. ELECTRICAL SPECIFICATIONS
2. ELECTRICAL SPECIFICATIONS
Caution 1. The RL78/G14 has an on-chip debug function, which is provided for development and evaluation. Do
not use the on-chip debug function in products designated for mass production, because the
guaranteed number of rewritable times of the flash memory may be exceeded when this function is
used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
Caution 2. The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 41 of 97
RL78/G14
Caution
2.1
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25 C) (1/2)
Parameter
Supply voltage
REGC pin input voltage
Symbols
(1/2)
Conditions
Ratings
Unit
VDD
-0.5 to +6.5
V
EVDD0, EVDD1 EVDD0 = EVDD1
-0.5 to +6.5
V
VSS
-0.5 to +0.3
V
-0.5 to +0.3
V
-0.3 to +2.8
V
EVSS0, EVSS1
EVSS0 = EVSS1
VIREGC
REGC
and -0.3 to VDD +0.3 Note 1
Input voltage
VI1
P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P64 to P67,
-0.3 to EVDD0 +0.3
V
and -0.3 to VDD +0.3 Note 2
P70 to P77, P80 to P87, P100 to P102,
P110, P111, P120, P140 to P147
VI2
P60 to P63 (N-ch open-drain)
VI3
P20 to P27, P121 to P124, P137,
-0.3 to +6.5
-0.3 to VDD +0.3
V
V
Note 2
P150 to P156, EXCLK, EXCLKS, RESET
Output voltage
VO1
P00 to P06, P10 to P17, P30, P31,
-0.3 to EVDD0 +0.3 Note 2
V
-0.3 to VDD +0.3
V
P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P100 to P102,
P110, P111, P120, P130, P140 to P147
Analog input voltage
Note 1.
VO2
P20 to P27, P150 to P156
VAI1
ANI16 to ANI20
VAI2
ANI0 to ANI14
-0.3 to EVDD0 +0.3
-0.3 to VDD +0.3
Note 2
V
Note 2
V
Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Note 2.
Caution
Must be 6.5 V or lower.
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 42 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Absolute Maximum Ratings (TA = 25 C) (2/2)
Parameter
Output current, high
Symbols
IOH1
(2/2)
Conditions
Per pin
P00 to P06, P10 to P17, P30, P31, P40 to P47,
Ratings
Unit
-40
mA
-70
mA
-100
mA
-0.5
mA
-2
mA
40
mA
70
mA
100
mA
1
mA
5
mA
-40 to +85
C
-65 to +150
C
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120, P130,
P140 to P147
Total of all P00 to P04, P40 to P47, P102, P120, P130,
pins
P140 to P145
-170 mA
P05, P06, P10 to P17, P30, P31, P50 to P57,
P64 to P67, P70 to P77, P80 to P87, P100, P101,
P110, P111, P146, P147
IOH2
Per pin
P20 to P27, P150 to P156
Total of all
pins
Output current, low
IOL1
Per pin
P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120, P130,
P140 to P147
Total of all P00 to P04, P40 to P47, P102, P120, P130,
pins
P140 to P145
170 mA
P05, P06, P10 to P17, P30, P31, P50 to P57,
P60 to P67, P70 to P77, P80 to P87, P100, P101,
P110, P111, P146, P147
IOL2
Per pin
P20 to P27, P150 to P156
Total of all
pins
Operating ambient
TA
temperature
Storage temperature
Caution
In normal operation mode
In flash memory programming mode
Tstg
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 43 of 97
RL78/G14
2. ELECTRICAL SPECIFICATIONS
Caution
2.2
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Oscillator Characteristics
2.2.1
Main system clock oscillator characteristics
(TA = -40 to +85 °C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
Ceramic
X1 clock oscillation frequency
2.7 V VDD 5.5 V
resonator
(fX) Note
VSS X1
X2
MAX.
Unit
1.0
20.0
MHz
1.8 V VDD < 2.7 V
1.0
8.0
1.6 V VDD < 1.8 V
1.0
4.0
X1 clock oscillation frequency
2.7 V VDD 5.5 V
1.0
20.0
(fX) Note
1.8 V VDD < 2.7 V
1.0
8.0
1.6 V VDD < 1.8 V
1.0
4.0
Rd
C1
C2
Crystal resonator
VSS X1
X2
Rd
C1
Note
TYP.
MHz
C2
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to
avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Caution 2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 44 of 97
RL78/G14
Caution
2.2.2
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
On-chip oscillator characteristics
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Oscillators
Parameters
High-speed on-chip oscillator
Conditions
MAX.
Unit
1
32
MHz
1.8 V  VDD  5.5 V
-1
+1
%
1.6 V  VDD  1.8 V
-5
+5
%
1.8 V  VDD < 5.5 V
-1.5
+1.5
%
1.6 V  VDD  1.8 V
-5.5
+5.5
%
fIH
MIN.
TYP.
clock frequency Note 1
-20 to +85 C
High-speed on-chip oscillator
clock frequency accuracy
Note 2
-40 to -20 C
Low-speed on-chip oscillator
15
fIL
kHz
clock frequency
Low-speed on-chip oscillator
-15
+15
%
clock frequency accuracy
Note 1.
High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/010C2H) and bits 0 to 2 of
the HOCODIV register.
Note 2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
When SSOP (30-pin), WQFN (32-, 40-, 48-pin), FLGA (36-pin), LQFP (7 × 7) (48-pin), LQFP (10 × 10) (52-pin), LQFP
(12 × 12) (64-, 80-pin), LQFP (14 × 14) (80-, 100-pin), LQFP (14 × 20) (100-pin) products, these specifications show
target values, which may change after device evaluation.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 45 of 97
RL78/G14
2. ELECTRICAL SPECIFICATIONS
2.2.3
Subsystem clock oscillator characteristics
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Resonator
Recommended Circuit
Items
Crystal
XT1 clock oscillation frequency
resonator
(fXT) Note
VSS XT2
XT1
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
Rd
C4
Note
C3
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to
avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Caution 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to
malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method
when the XT1 clock is used.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves
or apply to the resonator manufacturer for evaluation.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 46 of 97
RL78/G14
Caution
2.3
2.3.1
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
DC Characteristics
Pin characteristics
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Symbol
Output current, high Note 1
IOH1
Conditions
Per pin for P00 to P06,
MIN.
TYP.
1.6 V  EVDD0  5.5 V
P10 to P17, P30, P31,
MAX.
Unit
-10.0
mA
Note 2
P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P130, P140 to P147
4.0 V  EVDD0  5.5 V
-55.0
P102, P120, P130, P140 to P145
2.7 V  EVDD0 < 4.0 V
-10.0
mA
(When duty = 70% Note 3)
1.8 V  EVDD0 < 2.7 V
-5.0
mA
1.6 V  EVDD0 < 1.8 V
-2.5
mA
Total of P00 to P04, P40 to P47,
mA
4.0 V  EVDD0  5.5 V
-80.0
mA
P30, P31, P50 to P57,
2.7 V  EVDD0 < 4.0 V
-19.0
mA
P64 to P67, P70 to P77,
1.8 V  EVDD0 < 2.7 V
-10.0
mA
1.6 V  EVDD0 < 1.8 V
-5.0
mA
Total of P05, P06, P10 to P17,
P80 to P87, P100, P101, P110,
P111, P146, P147
(When duty = 70% Note 3)
Total of all pins
(When duty = 70% Note 3)
IOH2
Per pin for P20 to P27,
1.6 V  EVDD0  5.5 V
1.6 V  VDD  5.5 V
P150 to P156
Total of all pins
-135.0
Note 4
-0.1
mA
mA
Note 2
1.6 V  VDD  5.5 V
-1.5
mA
(When duty = 70% Note 3)
Note 1.
Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to
an output pin.
Note 2.
However, do not exceed the total current value.
Note 3.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following expression (when changing
the duty factor from 70 % to n %).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example>
Where n = 50 % and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(50 × 0.01) = -14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Note 4.
Caution
The applied current for the products of industrial application (R5F104xxDxx) is -100 mA.
P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144
do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 47 of 97
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Output current, low
Symbol
Note 1
IOL1
MAX.
Unit
Per pin for P00 to P06,
Conditions
MIN.
TYP.
20.0
mA
P10 to P17, P30, P31,
Note 2
P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P130, P140 to P147
Per pin for P60 to P63
15.0
mA
Note 2
Total of P00 to P04, P40 to P47,
4.0 V  EVDD0  5.5 V
70.0
mA
P102, P120, P130, P140 to P145
2.7 V  EVDD0 < 4.0 V
15.0
mA
(When duty = 70% Note 3)
1.8 V  EVDD0 < 2.7 V
9.0
mA
1.6 V  EVDD0 < 1.8 V
4.5
mA
Total of P05, P06, P10 to P17,
4.0 V  EVDD0  5.5 V
80.0
mA
P30, P31, P50 to P57,
2.7 V  EVDD0 < 4.0 V
35.0
mA
P60 to P67, P70 to P77,
1.8 V  EVDD0 < 2.7 V
20.0
mA
1.6 V  EVDD0 < 1.8 V
10.0
mA
150.0
mA
0.4
mA
P80 to P87, P100, P101, P110,
P111, P146, P147
(When duty = 70% Note 3)
Total of all pins
(When duty = 70% Note 3)
IOL2
Per pin for P20 to P27,
P150 to P156
Total of all pins
Note 2
1.6 V  VDD  5.5 V
5.0
mA
(When duty = 70% Note 3)
Note 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0,
EVSS1, and VSS pins.
Note 2.
However, do not exceed the total current value.
Note 3.
Specification under conditions where the duty factor is 70 %.
The output current value that has changed the duty ratio can be calculated with the following expression
(when changing the duty factor from 70 % to n %).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example>
Where n = 50 % and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 48 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Input voltage, high
Symbol
VIH1
Conditions
P00 to P06, P10 to P17, P30,
MIN.
Normal input buffer
MAX.
Unit
0.8 EVDD0
TYP.
EVDD0
V
2.2
EVDD0
V
2.0
EVDD0
V
1.50
EVDD0
V
0.7 VDD
VDD
V
0.7 EVDD0
6.0
V
0.8 VDD
VDD
V
0
0.2 EVDD0
V
0
0.8
V
0
0.5
V
0
0.32
V
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
VIH2
P01, P03, P04, P10, P14 to P17, TTL input buffer
P30, P31, P43, P44, P50,
4.0 V  EVDD0  5.5 V
P53 to P55, P80, P81, P142,
TTL input buffer
P143
3.3 V  EVDD0 < 4.0 V
TTL input buffer
1.6 V  EVDD0 < 3.3 V
Input voltage, low
VIH3
P20 to P27, P150 to P156
VIH4
P60 to P63
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
VIL1
P00 to P06, P10 to P17, P30,
Normal input buffer
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
VIL2
P01, P03, P04, P10, P14 to P17, TTL input buffer
P30, P31, P43, P44, P50,
4.0 V  EVDD0  5.5 V
P53 to P55, P80, P81, P142,
TTL input buffer
P143
2.7 V  EVDD0 < 4.0 V
TTL input buffer
1.6 V  EVDD0 < 2.7 V
Caution
VIL3
P20 to P27, P150 to P156
0
0.3 VDD
V
VIL4
P60 to P63
0
0.3 EVDD0
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2 VDD
V
The maximum value of VIH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71,
P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Output voltage, high
Symbol
VOH1
Conditions
P00 to P06, P10 to P17, P30,
4.0 V  EVDD0  5.5 V,
P31, P40 to P47, P50 to P57,
IOH1 = -10.0 mA
P64 to P67, P70 to P77,
4.0 V  EVDD0  5.5 V,
P80 to P87, P100 to P102, P110, IOH1 = -3.0 mA
P111, P120, P130, P140 to P147
1.8 V  EVDD0  5.5 V,
MIN.
TYP.
MAX.
Unit
EVDD0 - 1.5
V
EVDD0 - 0.7
V
EVDD0 - 0.5
V
EVDD0 - 0.5
V
VDD - 0.5
V
IOH1 = -1.5 mA
1.6 V  EVDD0 < 1.8 V,
IOH1 = -1.0 mA
VOH2
P20 to P27, P150 to P156
1.6 V  VDD  5.5 V,
IOH2 = -100 A
Output voltage, low
VOL1
P00 to P06, P10 to P17, P30,
4.0 V  EVDD0  5.5 V,
P31, P40 to P47, P50 to P57,
IOL1 = 20.0 mA
1.3
V
4.0 V  EVDD0  5.5 V,
P80 to P87, P100 to P102, P110, IOL1 = 8.5 mA
P111, P120, P130,
4.0 V  EVDD0  5.5 V,
P140 to P147
IOL1 = 4.0 mA
0.7
V
0.4
V
2.7 V  EVDD0  5.5 V,
0.4
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
0.4
V
P64 to P67, P70 to P77,
IOL1 = 1.5 mA
1.8 V  EVDD0  5.5 V,
IOL1 = 0.6 mA
1.6 V  EVDD0 < 1.8 V,
IOL1 = 0.3 mA
VOL2
P20 to P27, P150 to P156
1.6 V  VDD  5.5 V,
IOL2 = 400 A
VOL3
P60 to P63
4.0 V  EVDD0  5.5 V,
IOL3 = 15.0 mA
4.0 V  EVDD0  5.5 V,
IOL3 = 5.0 mA
2.7 V  EVDD0  5.5 V,
IOL3 = 3.0 mA
1.8 V  EVDD0  5.5 V,
IOL3 = 2.0 mA
1.6 V  EVDD0  5.5 V,
IOL3 = 1.0 mA
Caution
P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, P142 to P144 do not
output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Feb 21, 2012
Page 50 of 97
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2. ELECTRICAL SPECIFICATIONS
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Input leakage
Symbol
ILIH1
Conditions
P00 to P06, P10 to P17, P30,
MAX.
Unit
VI = EVDD0
MIN.
TYP.
1
A
VI = VDD
1
A
1
A
10
A
VI = EVSS0
-1
A
VI = VSS
-1
A
-1
A
-10
A
100
k
P31, P40 to P47, P50 to P57,
current, high
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
ILIH2
P20 to P27, P137, P150 to P156,
RESET
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, EXCLK, XT1, XT2,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
current, low
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
ILIL2
P20 to P27, P137, P150 to P156,
RESET
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, EXCLK, XT1, XT2,
external clock
EXCLKS)
input
In resonator
connection
On-chip pll-up
RU
P00 to P06, P10 to P17, P30,
VI = EVSS0, In input port
10
20
P31, P40 to P47, P50 to P57,
resistance
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0053EJ0100 Rev. 1.00
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Caution
2.3.2
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Supply current characteristics
(1) Flash ROM: 16 to 64 KB of 30- to 64-pin products
(TA = -40 to +85 C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter Symbol
Supply
current
IDD1
(1/2)
Conditions
Operating High-speed
mode
VDD = 5.0 V
2.4
operation VDD = 3.0 V
2.4
fHOCO = 32 MHz,
Basic
VDD = 5.0 V
2.1
fIH = 32 MHz
operation VDD = 3.0 V
2.1
fHOCO = 64 MHz,
Normal
fHOCO = 64 MHz,
operation Notes 3, 5 fIH = 32 MHz
Note 1
High-speed
5.2
8.7
5.2
8.7
fHOCO = 32 MHz,
Normal
VDD = 5.0 V
4.8
8.1
fIH = 32 MHz
operation VDD = 3.0 V
4.8
8.1
fHOCO = 48 MHz,
Normal
VDD = 5.0 V
4.1
6.9
fIH = 24 MHz
operation VDD = 3.0 V
4.1
6.9
fHOCO = 24 MHz,
Normal
VDD = 5.0 V
3.8
6.3
fIH = 24 MHz
operation VDD = 3.0 V
3.8
6.3
fHOCO = 16 MHz,
Normal
VDD = 5.0 V
2.8
4.6
fIH = 16 MHz
operation VDD = 3.0 V
2.8
4.6
fHOCO = 8 MHz,
Normal
operation
Notes 2, 5
Low-speed
operation
Notes 2, 5
Subsystem clock
operation
Note 4
VDD = 3.0 V
1.3
2.0
operation VDD = 2.0 V
1.3
2.0
Normal
VDD = 3.0 V
1.3
1.8
operation VDD = 2.0 V
1.3
1.8
fMX = 20 MHz,
Normal
3.3
5.3
VDD = 5.0 V
operation Resonator connection
3.5
5.5
fMX = 20 MHz,
Normal
3.3
5.3
VDD = 3.0 V
operation Resonator connection
3.5
5.5
fMX = 10 MHz,
Normal
2.0
3.1
VDD = 5.0 V
operation Resonator connection
2.1
3.2
fMX = 10 MHz,
Normal
2.0
3.1
VDD = 3.0 V
operation Resonator connection
2.1
3.2
fMX = 8 MHz,
Normal
1.2
1.9
VDD = 3.0 V
operation Resonator connection
1.2
2.0
fMX = 8 MHz,
Normal
1.2
1.9
VDD = 2.0 V
operation Resonator connection
1.2
2.0
fHOCO = 4 MHz,
operation Notes 3, 5 fIH = 4 MHz
High-speed
mA
VDD = 5.0 V
operation Notes 3, 5 fIH = 8 MHz
Low-voltage
Basic
operation VDD = 3.0 V
operation Notes 3, 5 fIH = 32 MHz
Low-speed
MIN. TYP. MAX. Unit
fSUB = 32.768 kHz Normal
TA = -40 C
Square wave input
Square wave input
Square wave input
Square wave input
Square wave input
Square wave input
operation Resonator connection
fSUB = 32.768 kHz Normal
TA = +85 C
Square wave input
operation Resonator connection
fSUB = 32.768 kHz Normal
TA = +70 C
Square wave input
operation Resonator connection
fSUB = 32.768 kHz Normal
TA = +50 C
Square wave input
operation Resonator connection
fSUB = 32.768 kHz Normal
TA = +25 C
Square wave input
Square wave input
operation Resonator connection
mA
mA
mA
mA
mA
A
4.7
4.7
4.7
6.1
4.7
6.1
4.8
6.7
4.8
6.7
4.8
7.5
4.8
7.5
5.4
8.9
5.4
8.9
(Notes and Remarks are listed on the next page.)
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Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except
for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port,
and on-chip pull-up/pull-down resistors.
Note 2.
When high-speed on-chip oscillator and subsystem clock are stopped.
Note 3.
When high-speed system clock and subsystem clock are stopped.
Note 4.
When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog
timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation).
Note 5.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
High speed operation: VDD = 2.7 V to 5.5 [email protected] MHz to 32 MHz
VDD = 2.4 V to 5.5 [email protected] MHz to 16 MHz
Low speed operation: VDD = 1.8 V to 5.5 [email protected] MHz to 8 MHz
Low voltage operation: VDD = 1.6 V to 5.5 [email protected] MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
Note
fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the
same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set
fCLK to fIH.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 53 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(1) Flash ROM: 16 to 64 KB of 30- to 64-pin products
(TA = -40 to +85 C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Supply
IDD2
current
Note 2
Conditions
Unit
mA
3.09
0.80
3.09
fHOCO = 32 MHz,
VDD = 5.0 V
0.54
2.40
fIH = 32 MHz
VDD = 3.0 V
0.54
2.40
fHOCO = 48 MHz,
VDD = 5.0 V
0.62
2.40
fIH = 24 MHz
VDD = 3.0 V
0.62
2.40
fHOCO = 24 MHz,
VDD = 5.0 V
0.44
1.83
fIH = 24 MHz
VDD = 3.0 V
0.44
1.83
fHOCO = 16 MHz,
VDD = 5.0 V
0.40
1.38
fIH = 16 MHz
VDD = 3.0 V
0.40
1.38
fHOCO = 8 MHz,
VDD = 3.0 V
260
710
fIH = 8 MHz
VDD = 2.0 V
260
710
fHOCO = 4 MHz,
VDD = 3.0 V
420
700
fIH = 4 MHz
VDD = 2.0 V
420
700
High-speed
fMX = 20 MHz,
Square wave input
0.28
1.55
operation Notes 3, 7
VDD = 5.0 V
Resonator connection
0.53
1.74
fMX = 20 MHz,
Square wave input
0.28
1.55
VDD = 3.0 V
Resonator connection
0.49
1.74
fMX = 10 MHz,
Square wave input
0.19
0.86
VDD = 5.0 V
Resonator connection
0.30
0.93
fMX = 10 MHz,
Square wave input
0.19
0.86
VDD = 3.0 V
Resonator connection
0.30
0.93
Low-speed
fMX = 7 MHz,
Square wave input
95
550
operation Notes 3, 7
VDD = 3.0 V
Resonator connection
145
590
fMX = 8 MHz,
Square wave input
95
550
VDD = 2.0 V
Resonator connection
145
590
fSUB = 32.768 kHz,
Square wave input
0.25
TA = -40 C
Resonator connection
0.44
fSUB = 32.768 kHz,
Square wave input
0.30
0.57
TA = +25 C
Resonator connection
0.49
0.76
fSUB = 32.768 kHz,
Square wave input
0.33
1.17
TA = +50 C
Resonator connection
0.52
1.36
fSUB = 32.768 kHz,
Square wave input
0.36
1.97
TA = +70 C
Resonator connection
0.55
2.16
fSUB = 32.768 kHz,
Square wave input
0.97
3.37
TA = +85 C
Resonator connection
0.16
3.56
operation
Notes 4, 7
Low-voltage
operation
Notes 4, 7
Subsystem clock
operation
mode
MAX.
0.80
Low-speed
Note 6
TYP.
VDD = 5.0 V
fHOCO = 64 MHz,
operation Notes 4, 7 fIH = 32 MHz
STOP
MIN.
VDD = 3.0 V
HALT mode High-speed
Note 1
IDD3
(2/2)
Note 5
TA = -40 C
0.18
A
A
mA
A
A
A
TA = +25 C
0.24
0.51
TA = +50 C
0.26
1.10
TA = +70 C
0.29
1.90
TA = +85 C
0.90
3.30
(Notes and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 54 of 97
RL78/G14
Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD , EV DD0 or V SS , EVSS0 . The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors.
Note 2.
During HALT instruction execution by flash memory.
Note 3.
When high-speed on-chip oscillator and subsystem clock are stopped.
Note 4.
When high-speed system clock and subsystem clock are stopped.
Note 5.
When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When high-speed onchip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX.
column include the leakage current.
Note 6.
When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer
is stopped. The values below the MAX. column include the leakage current.
Note 7.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
High speed operation: VDD = 2.7 V to 5.5 [email protected] MHz to 32 MHz
VDD = 2.4 V to 5.5 [email protected] MHz to 16 MHz
Low speed operation: VDD = 1.8 V to 5.5 [email protected] MHz to 8 MHz
Low voltage operation: VDD = 1.6 V to 5.5 [email protected] MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C
Note
fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the
same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set
fCLK to fIH.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 55 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol
Supply
current
IDD1
Conditions
Operating High-speed
mode
fHOCO = 64 MHz,
operation Notes 3, 5 fIH = 32 MHz
Note 1
(1/2)
MIN. TYP. MAX. Unit
Basic
VDD = 5.0 V
2.6
operation VDD = 3.0 V
2.6
2.3
mA
fHOCO = 32 MHz,
Basic
fIH = 32 MHz
operation VDD = 3.0 V
2.3
fHOCO = 64 MHz,
Normal
VDD = 5.0 V
5.8
10.2
operation VDD = 3.0 V
5.8
10.2
fHOCO = 32 MHz,
Normal
VDD = 5.0 V
5.4
9.6
fIH = 32 MHz
operation VDD = 3.0 V
5.4
9.6
fHOCO = 48 MHz,
Normal
VDD = 5.0 V
4.5
7.8
fIH = 24 MHz
operation VDD = 3.0 V
4.5
7.8
fHOCO = 24 MHz,
Normal
VDD = 5.0 V
4.2
7.4
fIH = 24 MHz
operation VDD = 3.0 V
4.2
7.4
fHOCO = 16 MHz,
Normal
VDD = 5.0 V
3.1
5.3
fIH = 16 MHz
operation VDD = 3.0 V
3.1
5.3
Low-speed
fHOCO = 8 MHz,
Normal
VDD = 3.0 V
1.4
2.3
operation Notes 3, 5
fIH = 8 MHz
operation VDD = 2.0 V
1.4
2.3
Low-voltage
fHOCO = 4 MHz,
Normal
VDD = 3.0 V
1.4
1.9
operation Notes 3, 5
fIH = 4 MHz
operation VDD = 2.0 V
1.4
1.9
High-speed
fMX = 20 MHz,
Normal
3.7
6.2
VDD = 5.0 V
operation Resonator connection
3.9
6.4
fMX = 20 MHz,
Normal
3.7
6.2
VDD = 3.0 V
operation Resonator connection
3.9
6.4
fMX = 10 MHz,
Normal
2.2
3.6
VDD = 5.0 V
operation Resonator connection
2.3
3.7
fMX = 10 MHz,
Normal
2.2
3.6
VDD = 3.0 V
operation Resonator connection
2.3
3.7
fMX = 8 MHz,
Normal
1.3
2.2
VDD = 3.0 V
operation Resonator connection
1.3
2.3
fMX = 8 MHz,
Normal
1.3
2.2
VDD = 2.0 V
operation Resonator connection
1.3
2.3
High-speed
operation Notes 3, 5 fIH = 32 MHz
operation
Notes 2, 5
Low-speed
operation
Notes 2, 5
Subsystem clock
fSUB = 32.768 kHz Normal
operation Note 4
TA = -40 C
Square wave input
Square wave input
Square wave input
Square wave input
Square wave input
Square wave input
Square wave input
operation Resonator connection
fSUB = 32.768 kHz Normal
TA = +85 C
Square wave input
operation Resonator connection
fSUB = 32.768 kHz Normal
TA = +70 C
Square wave input
operation Resonator connection
fSUB = 32.768 kHz Normal
TA = +50 C
Square wave input
operation Resonator connection
fSUB = 32.768 kHz Normal
TA = +25 C
VDD = 5.0 V
Square wave input
operation Resonator connection
mA
mA
mA
mA
mA
A
5.0
5.0
5.0
7.1
5.0
7.1
5.1
8.8
5.1
8.8
5.5
10.5
5.5
10.5
6.5
14.5
6.5
14.5
(Notes and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 56 of 97
RL78/G14
Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input
pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current
(except for background operation (BGO)). However, not including the current flowing into the A/D converter, D/A
converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
Note 2.
When high-speed on-chip oscillator and subsystem clock are stopped.
Note 3.
When high-speed system clock and subsystem clock are stopped.
Note 4.
When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog
timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation).
Note 5.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
High speed operation: VDD = 2.7 V to 5.5 [email protected] MHz to 32 MHz
VDD = 2.4 V to 5.5 [email protected] MHz to 16 MHz
Low speed operation: VDD = 1.8 V to 5.5 [email protected] MHz to 8 MHz
Low voltage operation: VDD = 1.6 V to 5.5 [email protected] MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25 °C
Note
fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the
same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set
fCLK to fIH.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 57 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol
Supply
IDD2
current
Conditions
TYP.
MAX.
Unit
mA
VDD = 5.0 V
0.88
3.32
0.88
3.32
fHOCO = 32 MHz,
VDD = 5.0 V
0.62
2.63
fIH = 32 MHz
VDD = 3.0 V
0.62
2.63
fHOCO = 48 MHz,
VDD = 5.0 V
0.68
2.57
fIH = 24 MHz
VDD = 3.0 V
0.68
2.57
fHOCO = 24 MHz,
VDD = 5.0 V
0.50
2.00
fIH = 24 MHz
VDD = 3.0 V
0.50
2.00
fHOCO = 16 MHz,
VDD = 5.0 V
0.44
1.49
fIH = 16 MHz
VDD = 3.0 V
0.44
1.49
fHOCO = 8 MHz,
VDD = 3.0 V
290
800
fIH = 8 MHz
VDD = 2.0 V
290
800
fHOCO = 4 MHz,
VDD = 3.0 V
440
755
fIH = 4 MHz
VDD = 2.0 V
440
755
High-speed
fMX = 20 MHz,
Square wave input
0.31
1.63
operation Notes 3, 7
VDD = 5.0 V
Resonator connection
0.50
1.85
fMX = 20 MHz,
Square wave input
0.31
1.63
VDD = 3.0 V
Resonator connection
0.50
1.85
fMX = 10 MHz,
Square wave input
0.21
0.89
VDD = 5.0 V
Resonator connection
0.30
0.97
fMX = 10 MHz,
fHOCO = 64 MHz,
operation Notes 4, 7 fIH = 32 MHz
Note 1
Low-speed
operation
Notes 4, 7
Low-voltage
operation
Notes 4, 7
Square wave input
0.21
0.89
VDD = 3.0 V
Resonator connection
0.30
0.97
Low-speed
fMX = 8 MHz,
Square wave input
110
580
operation Notes 3, 7
VDD = 3.0 V
Resonator connection
160
630
fMX = 8 MHz,
Square wave input
110
580
VDD = 2.0 V
Resonator connection
160
630
fSUB = 32.768 kHz,
Square wave input
0.28
TA = -40 C
Resonator connection
0.47
fSUB = 32.768 kHz,
Square wave input
0.34
TA = +25 C
Resonator connection
0.53
0.85
fSUB = 32.768 kHz,
Square wave input
0.37
2.35
TA = +50 C
Resonator connection
0.56
2.54
fSUB = 32.768 kHz,
Square wave input
0.61
4.08
TA = +70 C
Resonator connection
0.80
4.27
fSUB = 32.768 kHz,
Square wave input
1.55
8.09
TA = +85 C
Resonator connection
1.74
8.28
Subsystem clock
operation
IDD3
MIN.
VDD = 3.0 V
HALT mode High-speed
Note 2
(2/2)
Note 5
A
mA
A
A
0.66
TA = -40 C
0.19
mode Note 6 TA = +25 C
0.25
0.57
TA = +50 C
0.28
2.26
TA = +70 C
0.52
3.99
TA = +85 C
1.46
8.00
STOP
A
A
(Notes and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 58 of 97
RL78/G14
Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input
pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD
circuit, I/O port, and on-chip pull-up/pull-down resistors.
Note 2.
During HALT instruction execution by flash memory.
Note 3.
When high-speed on-chip oscillator and subsystem clock are stopped.
Note 4.
When high-speed system clock and subsystem clock are stopped.
Note 5.
When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When high-speed onchip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX.
column include the leakage current.
Note 6.
When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer
is stopped. The values below the MAX. column include the leakage current.
Note 7.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
High speed operation: VDD = 2.7 V to 5.5 [email protected] MHz to 32 MHz
VDD = 2.4 V to 5.5 [email protected] MHz to 16 MHz
Low speed operation: VDD = 1.8 V to 5.5 [email protected] MHz to 8 MHz
Low voltage operation: VDD = 1.6 V to 5.5 [email protected] MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C
Note
fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the
same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set
fCLK to fIH.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 59 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(3) Common to RL78/G14 all products
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
RTC operating current IRTC
Conditions
fSUB = 32.768 kHz
Notes 1, 2
MIN.
TYP.
Real-time clock operation
0.02
12-bit interval timer operation
0.02
fIL = 15 kHz
MAX.
A
A
0.22
Watchdog timer
IWDT
operating current
Notes 2, 3
A/D converter
IADC
When conversion
operating current
Note 4
at maximum speed Low voltage mode, AVREFP = VDD = 3.0 V
A/D converter
IADREF
Normal mode, AVREFP = VDD = 5.0 V
Unit
1.3
1.7
mA
0.5
0.7
mA
A
75
reference voltage
current
D/A converter
IDAC Notes
operating current
5, 9
Comparator operating ICMP Notes
6, 9
current
Per D/A converter channel
VDD = 5.0 V,
Regulator output
mA
12.5
A
High-speed comparator mode
6.5
A
Low-speed comparator mode
1.7
A
VDD = 5.0 V,
Window comparator mode
8.0
A
Regulator output
High-speed comparator mode
4.0
A
Low-speed comparator mode
1.3
A
75
A
A
voltage = 2.1 V
voltage = 1.8 V
Temperature sensor
Window comparator mode
1.5
ITMPS
operating current
LVD operating current
ILVI Note 7
0.08
BGO operating
IBGO Note 8
2.50
12.20
mA
current
Note 1.
Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The TYP. value of the
current value of the RL78/G14 is the sum of the TYP. values of either IDD1 or IDD2, and IRTC, when the real-time clock
operates in operation mode or HALT mode. The IDD1 and IDD2 MAX. values also include the real-time clock operating
current. However, IDD2 subsystem clock operation includes the operational current of the real-time clock.
Note 2.
When high speed on-chip oscillator and high-speed system clock are stopped.
Note 3.
Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The current value of the RL78/G14 is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates in STOP
mode.
Note 4.
Current flowing only to the A/D converter. The current value of the RL78/G14 is the sum of IDD1 or IDD2 and IADC when the
A/D converter operates in an operation mode or the HALT mode.
Note 5.
Current flowing only to the D/A converter. The current value of the RL78/G14 is the sum of IDD1 or IDD2 and IADC when the
D/A converter operates in an operation mode or the HALT mode.
Note 6.
Current flowing only to the comparator circuit. The current value of the RL78/G14 is the sum of IDD1, IDD2 or IDD3 and ICMP
when the comparator circuit operates in the Operating, HALT or STOP mode.
Note 7.
Current flowing only to the LVD circuit. The current value of the RL78/G14 is the sum of IDD1, IDD2 or IDD3 and ILVI when
the LVD circuit operates in the Operating, HALT or STOP mode.
Note 8.
Current flowing only to the BGO. The current value of the RL78/G14 is the sum of IDD1 or IDD2 and IBGO when the BGO
operates in an operation mode.
Note 9.
A comparator and D/A converter are provided in products with 96 KB or more code flash memory.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK: CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25 °C
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 60 of 97
RL78/G14
Caution
2.4
2.4.1
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
AC Characteristics
Basic operation
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
MAX.
Unit
Main system
High-speed
2.7 V  VDD  5.5 V
0.03125
1
s
(minimum instruction
clock (fMAIN)
main mode
2.4 V  VDD < 2.7 V
0.0625
1
s
execution time)
operation
Low voltage
1.6 V  VDD  5.5 V
0.25
1
s
1.8 V  VDD  5.5 V
0.125
1
s
Subsystem clock (fSUB) operation
1.8 V  VDD  5.5 V
28.5
31.3
s
In the self
High-speed
2.7 V  VDD  5.5 V
0.03125
1
s
programming
main mode
2.4 V  VDD < 2.7 V
0.0625
1
s
Low voltage
1.8 V  VDD  5.5 V
0.25
1
s
1.8 V  VDD  5.5 V
0.125
1
s
2.7 V  VDD  5.5 V
1.0
20.0
MHz
1.8 V  VDD < 2.7 V
1.0
8.0
MHz
1.6 V  VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
Instruction cycle
Symbol
TCY
Conditions
(1/2)
MIN.
TYP.
main mode
Low-speed
main mode
mode
30.5
main mode
Low-speed
main mode
External main system
fEX
clock frequency
fEXS
External main system
tEXH,
2.7 V  VDD  5.5 V
24
ns
clock input high-level
tEXL
1.8 V  VDD < 2.7 V
60
ns
1.6 V  VDD < 1.8 V
120
ns
13.7
s
1/fMCK + 10
ns
width, low-level width
tEXHS,
tEXLS
TI00 to TI03, TI10 to
tTIH, tTIL
TI13 input high-level
Note
width, low-level width
Timer RJ input cycle
fC
TRJIO
2.7 V  EVDD0  5.5 V
100
ns
1.8 V  EVDD0 < 2.7 V
300
ns
1.6 V  EVDD0 < 1.8 V
500
ns
2.7 V  EVDD0  5.5 V
40
ns
level width, low-level
1.8 V  EVDD0 < 2.7 V
120
ns
width
1.6 V  EVDD0 < 1.8 V
200
ns
Timer RJ input high-
Note
fWH, fWL
TRJIO
The following conditions are required for low voltage interface when EVDD0 < VDD
1.8 V  EVDD0 < 2.7 V : MIN. 125 ns
1.6 V  EVDD0 < 1.8 V : MIN. 250 ns
Remark
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel
number (n = 0 to 3))
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 61 of 97
RL78/G14
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
TO00 to TO03, TO10 to T13
Symbol
fTO
Conditions
High-speed main mode
output frequency
PCLBUZ0, PCLBUZ1 output
fPCL
(2/2)
MIN.
TYP.
MAX.
Unit
4.0 V  EVDD0  5.5 V
16
MHz
2.7 V  EVDD0 < 4.0 V
8
MHz
1.8 V  EVDD0 < 2.7 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
Low voltage main mode
1.6 V  EVDD0  5.5 V
2
MHz
Low-speed main mode
1.8 V  EVDD0  5.5 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
4.0 V  EVDD0  5.5 V
16
MHz
2.7 V  EVDD0 < 4.0 V
8
MHz
1.8 V  EVDD0 < 2.7 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
1.8 V  EVDD0  5.5 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
1.8 V  EVDD0  5.5 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
High-speed main mode
frequency
Low voltage main mode
Low-speed main mode
Interrupt input high-level width,
tINTH,
INTP0
1.6 V  VDD  5.5 V
1
s
low-level width
tINTL
INTP1 to INTP11
1.6 V  EVDD0  5.5 V
1
s
Key interrupt input low-level
tKR
1.8 V  EVDD0  5.5 V
250
ns
1.6 V  EVDD0 < 1.8 V
1
s
10
s
width
RESET low-level width
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
tRSL
Page 62 of 97
RL78/G14
Caution
2.5
2.5.1
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Peripheral Functions Characteristics
Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
Note 1
MAX.
fMCK/6
Theoretical value of the maximum transfer
Note 2
5.3
Unit
bps
Mbps
rate fCLK = 32 MHz, fMCK = fCLK
UART mode connection diagram (during communication at same potential)
TxDq
Rx
User’s device
RL78/G14
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Note 1.
Transfer rate in the SNOOZE mode is MAX. 9600 bps and MIN. 4800 bps.
Note 2.
The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V  EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V  EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V  EVDD0 < 1.8 V : MAX. 0.6 Mbps
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 63 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(2) During communication at same potential (CSI mode) (master mode (fMCK/2), SCKp... internal clock output)
(TA = -40 to +85 C, 2.7 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCKp cycle time
tKCY1
2.7 V  EVDD0  5.5 V
62.5 Note 1
ns
SCKp high-/low-level width
tKH1,
4.0 V  EVDD0  5.5 V
tKCY1/2 - 7
ns
tKL1
2.7 V  EVDD0  5.5 V
tKCY1/2 - 10
ns
tSIK1
4.0 V  EVDD0  5.5 V
23
ns
2.7 V  EVDD0  5.5 V
Note 5
ns
10
ns
SIp setup time (to SCKp↑) Note 2
SIp hold time (from SCKp↑) Note 3
tKSI1
2.7 V  EVDD0  5.5 V
Delay time from SCKp↓ to SOp output
tKSO1
C = 20 pF Note 6
33
10
ns
Note 4
Note 1.
The value must also be 2/fCLK or more.
Note 2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 5.
Using the fMCK within 24 MHz.
Note 6.
C is the load capacitance of the SCKp and SOp output lines.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 64 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(3) During communication at same potential (CSI mode) (master mode (fMCK/4), SCKp... internal clock output)
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time
SCKp high-/low-level width
SIp setup time (to SCKp↑) Note 2
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
2.7 V  EVDD0  5.5 V
125 Note 1
ns
2.4 V  EVDD0  5.5 V
250 Note 1
ns
1.8 V  EVDD0  5.5 V
500 Note 1
ns
1.6 V  EVDD0  5.5 V
1000 Note 1
ns
tKH1,
4.0 V  EVDD0  5.5 V
tKCY1/2 - 12
ns
tKL1
2.7 V  EVDD0  5.5 V
tKCY1/2 - 18
ns
2.4 V  EVDD0  5.5 V
tKCY1/2 - 38
ns
1.8 V  EVDD0  5.5 V
tKCY1/2 - 50
ns
1.6 V  EVDD0  5.5 V
tKCY1/2 - 100
ns
4.0 V  EVDD0  5.5 V
44
ns
2.7 V  EVDD0  5.5 V
44
ns
2.4 V  EVDD0  5.5 V
75
ns
1.8 V  EVDD0  5.5 V
110
ns
1.6 V  EVDD0  5.5 V
220
ns
19
ns
tKCY1
tSIK1
SIp hold time (from SCKp↑) Note 3
tKSI1
Delay time from SCKp↓ to SOp output
tKSO1
C = 30 pF Note 5
Note 4
25
ns
Note 1.
The value must also be 4/fCLK or more.
Note 2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 5.
C is the load capacitance of the SCKp and SOp output lines.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 65 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time Note 5
Symbol
tKCY2
Conditions
MIN.
(1/2)
TYP.
MAX.
Unit
4.0 V  EVDD0  5.5 V 20 MHz < fMCK
8/fMCK
ns
fMCK  20 MHz
6/fMCK
ns
2.7 V  EVDD0 < 4.0 V 16 MHz < fMCK
8/fMCK
ns
fMCK  16 MHz
6/fMCK
ns
1.8 V  EVDD0 < 2.7 V 16 MHz < fMCK
8/fMCK
ns
fMCK  16 MHz
6/fMCK
ns
6/fMCK
ns
tKCY2/2
ns
1.6 V  EVDD0 < 1.8 V
SCKp high-/low-level width tKH2,
tKL2
1.6 V  EVDD0  5.5 V
tSIK2
2.7 V  EVDD0  5.5 V
1/fMCK + 20
ns
1.8 V  EVDD0 < 2.7 V
1/fMCK + 30
ns
1.6 V  EVDD0 < 1.8 V
1/fMCK + 40
ns
2.7 V  EVDD0  5.5 V
1/fMCK + 31
ns
2.4 V  EVDD0 < 2.7 V
1/fMCK + 31
ns
SIp setup time
Note 1
(to SCKp↑)
tKSI2
SIp hold time
(from SCKp↑)
Note 2
Delay time from SCKp↓ to
SOp output
tKSO2
1.8 V  EVDD0 < 2.4 V
1/fMCK + 31
ns
1.6 V  EVDD0 < 1.8 V
1/fMCK + 250
ns
C = 30 pF Note 4
Note 3
4.0 V  EVDD0  5.5 V
2/fMCK + 44
ns
2.7 V  EVDD0 < 4.0 V
2/fMCK + 44
ns
2.4 V  EVDD0 < 2.7 V
2/fMCK + 75
ns
1.8 V  EVDD0 < 2.4 V
2/fMCK + 110
ns
1.6 V  EVDD0 < 1.8 V
2/fMCK + 220
ns
Note 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
Note 2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4.
C is the load capacitance of the SOp output lines.
Note 5.
The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution
Select the TTL input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 66 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SSI00 setup time
Symbol
tSSIK
Conditions
DAPmn = 0
DAPmn = 1
SSI00 hold time
tKSSI
DAPmn = 0
DAPmn = 1
Caution
MIN.
(2/2)
TYP.
MAX.
Unit
2.7 V  EVDD0  5.5 V
120
ns
1.8 V  EVDD0 < 2.7 V
200
ns
1.6 V  EVDD0 < 1.8 V
400
ns
2.7 V  EVDD0  5.5 V
1/fMCK + 120
ns
1.8 V  EVDD0 < 2.7 V
1/fMCK + 200
ns
1.6 V  EVDD0 < 1.8 V
1/fMCK + 400
ns
2.7 V  EVDD0  5.5 V
1/fMCK + 120
ns
1.8 V  EVDD0 < 2.7 V
1/fMCK + 200
ns
1.6 V  EVDD0 < 1.8 V
1/fMCK + 400
ns
2.7 V  EVDD0  5.5 V
120
ns
1.8 V  EVDD0 < 2.7 V
200
ns
1.6 V  EVDD0 < 1.8 V
400
ns
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5)
CSI mode connection diagram (during communication at same potential)
SCKp
RL78/G14
SCK
SIp
SO
SOp
SI
User's device
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
SCK00
SCK
SI00
SO
SO00
SI
SSI00
SS0
RL78/G14
User's device
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 67 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
tKSSI
tSSIK
SSI00
(CSI00 only)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
tSSIK
tKSSI
SSI00
(CSI00 only)
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 68 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(5) During communication at same potential (simplified I2C mode)
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
MIN.
2.7 V  EVDD0  5.5 V,
MAX.
Unit
1000
kHz
400
kHz
300
kHz
250
kHz
Cb = 50 pF, Rb = 2.7 k
1.8 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
1.8 V  EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
1.6 V  EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
Hold time when SCLr = “L”
tLOW
2.7 V  EVDD0  5.5 V,
475
ns
1150
ns
1550
ns
1850
ns
475
ns
1150
ns
1550
ns
1850
ns
1/fMCK + 85
ns
Cb = 50 pF, Rb = 2.7 k
1.8 V  VDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
1.8 V  EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
1.6 V  EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
Hold time when SCLr = “H”
tHIGH
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
1.8 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
1.8 V  EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
1.6 V  EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
Data setup time (reception)
tSU:DAT
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
Data hold time (transmission)
tHD:DAT
Note
1.8 V  EVDD0  5.5 V,
1/fMCK + 145
Cb = 100 pF, Rb = 3 k
Note
1.8 V  EVDD0 < 2.7 V,
1/fMCK + 230
Cb = 100 pF, Rb = 5 k
Note
ns
ns
1.6 V  EVDD0 < 1.8 V,
1/fMCK + 290
Cb = 100 pF, Rb = 5 k
Note
2.7 V  EVDD0  5.5 V,
0
305
ns
0
355
ns
0
405
ns
0
405
ns
ns
Cb = 50 pF, Rb = 2.7 k
1.8 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
1.8 V  EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
1.6 V  EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
Note
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
(Caution and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 69 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Simplified I2C mode mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
RL78/G14
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
Caution
tSU: DAT
Select the TTL input buffer and the N-ch open drain output (EVDD0 tolerance) mode for the SDAr pin and the N-ch
open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register h (POMh).
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 3 to 5, 14),
h: POM number (h = 0, 1, 3 to 5, 7, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 00 to 03, 10 to 13)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 70 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(6) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output)
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Transfer rate
Symbol
Conditions
reception
TYP.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V
Notes 1, 2
MIN.
(1/2)
MAX.
Unit
fMCK/6 Note 1
bps
5.3
Mbps
fMCK/6 Note 1
bps
5.3
Mbps
fMCK/6
bps
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
1.8 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V
Note 1 to Note 3
Theoretical value of the
1.3
Mbps
maximum transfer rate
fCLK = 8 MHz, fMCK = fCLK
Note 1.
Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
Note 2.
Use it with EVDD0  Vb.
Note 3.
The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V  EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V  EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V  EVDD0 < 1.8 V : MAX. 0.6 Mbps
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD0 tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in UART mode.
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 5. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 71 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(6) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output)
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
(2/2)
MIN. TYP.
transmission 4.0 V  EVDD0  5.5 V,
Transfer
2.7 V  Vb  4.0 V
rate
Theoretical value of the maximum
transfer rate
MAX.
Unit
Notes 1, 2
bps
2.8
Mbps
Note 3
Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V
Theoretical value of the maximum
transfer rate
Notes 2, 4
bps
1.2
Mbps
Note 5
Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V
1.8 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V
Notes 2, 6, 7
bps
Theoretical value of the maximum
0.40
Mbps
transfer rate
Note 8
Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V
Note 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 4.0 V  EVDD0  5.5 V and 2.7 V  Vb  4.0 V
1
[bps]
Maximum transfer rate =
{-Cb  Rb  In (1 -
2.2
Vb
)}  3
1
Transfer rate  2
- {-Cb  Rb  In (1 -
2.2
Vb
)}
 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
)  Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 2.
Transfer rate in the SNOOZE mode: MAX. 9600 bps, MIN. 4800 bps
Note 3.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Note 4.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 2.7 V  EVDD0 < 4.0 V and 2.3 V  Vb  2.7 V
1
Maximum transfer rate =
[bps]
{-Cb  Rb  In (1 -
2.0
Vb
)}  3
1
Transfer rate  2
- {-Cb  Rb  In (1 -
2.0
Vb
)}
 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
)  Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 5.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
Note 6.
Use it with EVDD0  Vb.
R01DS0053EJ0100 Rev. 1.00
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RL78/G14
Note 7.
2. ELECTRICAL SPECIFICATIONS
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 1.8 V  EVDD0 < 3.3 V and 1.6 V  Vb  2.0 V
1
Maximum transfer rate =
[bps]
{-Cb  Rb  In (1 -
1.5
Vb
)}  3
1
Transfer rate  2
- {-Cb  Rb  In (1 -
1.5
Vb
)}
 100 [%]
Baud rate error (theoretical value) =
(
1
)  Number of transferred bits
Transfer rate
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 8.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD0 tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in UART mode.
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 5. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78/G14
User’s device
RxDq
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Tx
Page 73 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD0 tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
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RL78/G14
2. ELECTRICAL SPECIFICATIONS
Caution
(7)
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +85 C, 2.7 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY1
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
200 Note 1
ns
300 Note 1
ns
tKCY1/2 - 50
ns
tKCY1/2 - 120
ns
tKCY1/2 - 7
ns
tKCY1/2 - 10
ns
58
ns
121
ns
10
ns
10
ns
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SCKp high-level width
tKH1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SCKp low-level width
tKL1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp setup time
tSIK1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
(to SCKp↑) Note 2
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKSI1
SIp hold time
(from SCKp↑)
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
Note 2
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
Delay time from SCKp↓ to SOp
tKSO1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
60
ns
130
ns
Cb = 20 pF, Rb = 1.4 k
output Note 2
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp setup time
(to SCKp↓)
tSIK1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
23
ns
33
ns
10
ns
10
ns
Cb = 20 pF, Rb = 1.4 k
Note 3
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp hold time
tKSI1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
(from SCKp↓) Note 3
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
Delay time from SCKp↑ to SOp
output
Note 3
tKSO1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
10
ns
10
ns
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
(Notes, Caution and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
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RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Vb
Rb
SCKp
RL78/G14
Rb
SCK
SIp
SO
SOp
SI
User’s device
Note 1.
The value must also be 2/fCLK or more.
Note 2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Note 3.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in CSI mode.
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V
Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Remark 5. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(8) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY1
(1/2)
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
300 Note
ns
500 Note
ns
1150 Note
ns
tKCY1/2 - 75
ns
tKCY1/2 - 170
ns
tKCY1/2 - 458
ns
tKCY1/2 - 12
ns
tKCY1/2 - 18
ns
tKCY1/2 - 50
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
SCKp high-level width
tKH1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
SCKp low-level width
tKL1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
Note 1.
The value must also be 4/fCLK or more.
Caution 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Caution 2. Use it with EVDD0  Vb.
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in CSI mode.
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 4. 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 77 of 97
RL78/G14
2. ELECTRICAL SPECIFICATIONS
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(8) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SIp setup time
Symbol
tSIK1
Conditions
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
(2/2)
MIN.
TYP.
MAX.
Unit
81
ns
177
ns
479
ns
19
ns
19
ns
19
ns
Cb = 30 pF, Rb = 1.4 k
(to SCKp↑) Note 1
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
(from SCKp↑) Note 1
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp↓ to SOp
output
tKSO1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
100
ns
195
ns
483
ns
Cb = 30 pF, Rb = 1.4 k
Note 1
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
SIp setup time
(to SCKp↓)
tSIK1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
44
ns
44
ns
110
ns
19
ns
19
ns
19
ns
Cb = 30 pF, Rb = 1.4 k
Note 2
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
(from SCKp↓) Note 2
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp↑ to SOp
output Note 2
tKSO1
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
25
ns
25
ns
25
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
(Notes, Caution and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 78 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
CSI mode connection diagram (during communication at different potential
<Master>
Vb
Vb
Rb
SCKp
RL78/G14
Rb
SCK
SIp
SO
SOp
SI
Note 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Note 2.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
User’s device
Caution 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Caution 2. Use it with EVDD0  Vb.
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in CSI mode.
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 79 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
tKSI1
Input data
SIp
tKSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKH1
tKL1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Caution
Output data
Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 80 of 97
RL78/G14
2. ELECTRICAL SPECIFICATIONS
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(9) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time Note 1
Symbol
tKCY2
Conditions
4.0 V  EVDD0  5.5 V,
24 MHz  fMCK
2.7 V  Vb  4.0 V
MIN.
TYP.
MAX.
Unit
14/fMCK
ns
20 MHz < fMCK  24 MHz
12/fMCK
ns
8 MHz < fMCK  20 MHz
10/fMCK
ns
4 MHz < fMCK  8 MHz
8/fMCK
ns
fMCK  4 MHz
6/fMCK
ns
2.7 V  EVDD0 < 4.0 V,
24 MHz < fMCK
20/fMCK
ns
2.3 V  Vb  2.7 V
20 MHz < fMCK  24 MHz
16/fMCK
ns
16 MHz < fMCK  20 MHz
14/fMCK
ns
8 MHz < fMCK  16 MHz
12/fMCK
ns
4 MHz < fMCK  8 MHz
8/fMCK
ns
fMCK  4 MHz
6/fMCK
ns
24 MHz  fMCK
48/fMCK
ns
36/fMCK
ns
16 MHz < fMCK  20 MHz
32/fMCK
ns
8 MHz < fMCK  16 MHz
26/fMCK
ns
4 MHz < fMCK  8 MHz
16/fMCK
ns
fMCK  4 MHz
10/fMCK
ns
1.8 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V Note 2 20 MHz < fMCK  24 MHz
SCKp high-/low-level
tKH2,
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V
tKCY2/2 - 12
ns
width
tKL2
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V
tKCY2/2 - 18
ns
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 2
tKCY2/2 - 50
ns
2.7 V  EVDD0 < 5.5 V
1/fMCK + 20
ns
1.8 V  EVDD0 < 3.3 V
1/fMCK + 30
ns
1/fMCK + 31
ns
SIp setup time
tSIK2
(to SCKp↑) Note 3
SIp hold time
tKSI2
(from SCKp↑) Note 4
Delay time from SCKp↓
tKSO2
to SOp output Note 5
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
1/fMCK + 250
2/fMCK + 120
ns
2/fMCK + 214
ns
2/fMCK + 573
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
(Notes, Caution and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 81 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
Rb
SCKp
RL78/G14
SIp
SO
SOp
SI
Note 1.
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Note 2.
Use it with EVDD0  Vb.
Note 3.
SCK
User’s device
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD0 tolerance) mode
for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 02, 10))
Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in CSI mode.
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 5. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 82 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2
tKL2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Caution
Output data
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD0 tolerance) mode
for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 83 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
(1/2)
MIN.
4.0 V  EVDD0  5.5 V,
MAX.
Unit
1000
kHz
1000
kHz
400
kHz
400
kHz
300
kHz
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 k
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V Note 1,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr = “L”
tLOW
4.0 V  EVDD0  5.5 V,
475
ns
475
ns
1150
ns
1150
ns
1550
ns
245
ns
200
ns
675
ns
600
ns
610
ns
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 k
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V Note 1,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr = “H”
tHIGH
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 k
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V Note 1,
Cb = 100 pF, Rb = 5.5 k
(Notes, Caution and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 84 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Data setup time (reception)
Symbol
tSU:DAT
Conditions
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
(2/2)
MIN.
MAX.
1/fMCK + 135
Unit
ns
Note 2
Cb = 50 pF, Rb = 2.7 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
1/fMCK + 135
ns
Note 2
Cb = 50 pF, Rb = 2.7 k
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
1/fMCK + 190
ns
Note 2
Cb = 100 pF, Rb = 2.8 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
1/fMCK + 190
ns
Note 2
Cb = 100 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V Note 1,
1/fMCK + 190
ns
Note 2
Cb = 100 pF, Rb = 5.5 k
Data hold time (transmission)
tHD:DAT
4.0 V  EVDD0  5.5 V,
0
305
ns
0
305
ns
0
355
ns
0
355
ns
0
405
ns
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 k
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1.8 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V Note 1,
Cb = 100 pF, Rb = 5.5 k
Note 1.
Use it with EVDD0  Vb.
Note 2.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the TTL input buffer and the N-ch open drain output (EVDD0 tolerance) mode for the SDAr pin and the N-ch
open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
(Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 85 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78/G14
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
Caution
tSU: DAT
Select the TTL input buffer and the N-ch open drain output (EVDD0 tolerance) mode for the SDAr pin and the N-ch
open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 30, 31), g: PIM, POM number (g = 0, 1, 3 to 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0, 3), mn = 00 to 03, 10, 12, 13)
Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in simplified I2C mode.
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 86 of 97
RL78/G14
2. ELECTRICAL SPECIFICATIONS
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.5.2
Serial interface IICA
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Standard
Parameter
Symbol
Mode
Conditions
Fast Mode
Fast Mode
Plus
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock frequency
fSCL
Fast mode plus:
2.7 V  EVDD0  5.5 V
0
1000
kHz
fCLK  10 MHz
1.8 V  EVDD0  5.5 V
Fast mode:
0
400
kHz
fCLK  3.5 MHz
Normal mode:
1.6 V  EVDD0  5.5 V
0
100
kHz
fCLK  1 MHz
tSU:STA
4.7
0.6
0.26
s
Hold time
tHD:STA
4.0
0.6
0.26
s
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
0.5
s
Hold time when SCLA0 = “H” tHIGH
4.0
0.6
0.26
s
Data setup time (reception)
250
100
50
ns
0
s
Setup time of restart
condition Note 1
tSU:DAT
Data hold time (transmission) tHD:DAT
0
Note 2
3.45
0
0.9
Setup time of stop condition
tSU:STO
4.0
0.6
0.26
s
Bus-free time
tBUF
4.7
1.3
0.5
s
Note 1.
Note 2.
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
Fast mode: Cb = 320 pF, Rb = 1.1 k
Fast mode plus: Cb = 120 pF, Rb = 1.1 k
IICA serial transfer timing
tLOW
SCL0
tHD: DAT
tHD: STA
tHIGH
tSU: STA
tHD: STA
tSU: STO
tSU: DAT
SDA0
tLOW
Stop
condition
Start
condition
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Restart
condition
Stop
condition
Page 87 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.5.3
On-chip debug (UART)
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
Transfer rate
2.6
MIN.
TYP.
115.2 k
MAX.
Unit
1M
bps
Analog Characteristics
2.6.1
A/D converter characteristics
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1),
target ANI pin: ANI2 to ANI14 (supply ANI pin to VDD)
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) =
AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall error Notes 1, 2
AINL
Conversion time
Zero-scale error
tCONV
Notes 1, 2
Full-scale error Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
EZS
EFS
ILE
DLE
Note 1
Reference voltage (+)
AVREFP
Analog input voltage
VAIN
VBGR
Conditions
MIN.
TYP.
MAX.
Unit
10
bit
1.2
3.5
LSB
1.2
8
10-bit resolution
1.8 V  VDD  5.5 V
AVREFP = VDD
1.6 V  VDD  5.5 V
7.0
LSB
10-bit resolution
3.6 V  VDD  5.5 V
2.125
39
s
AVREFP = VDD
2.7 V  VDD  5.5 V
3.1875
39
s
1.8 V  VDD  5.5 V
17
39
s
1.6 V  VDD  5.5 V
57
95
s
10-bit resolution
1.8 V  VDD  5.5 V
0.25
% FSR
AVREFP = VDD
1.6 V  VDD < 5.5 V
0.50
% FSR
10-bit resolution
1.8 V  VDD  5.5 V
0.25
% FSR
AVREFP = VDD
1.6 V  VDD  5.5 V
0.50
% FSR
10-bit resolution
1.8 V  VDD  5.5 V
2.5
LSB
AVREFP = VDD
1.6 V  VDD  5.5 V
5.0
LSB
10-bit resolution
1.8 V  VDD  5.5 V
1.5
LSB
AVREFP = VDD
1.6 V  VDD  5.5V
2.4 V  VDD < 5.5 V,
2.0
LSB
1.6
VDD
V
0
AVREFP
V
1.5
V
1.38
1.45
HS (high-speed main) mode
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
This value is indicated as a ratio (% FSR) to the full-scale value.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 88 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(2) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1),
target ANI pin: ANI16 to ANI20 (supply ANI pin to EVDD0)
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) =
AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall error Notes 1, 2
AINL
Conversion time
Zero-scale error
tCONV
Notes 1, 2
Full-scale error Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
EZS
EFS
ILE
DLE
Note 1
Reference voltage (+)
AVREFP
Analog input voltage
VAIN
Conditions
MIN.
TYP.
8
MAX.
Unit
10
bit
10-bit resolution
1.8 V  VDD  5.5 V
1.2
5.0
LSB
AVREFP = VDD
1.6 V  VDD  5.5 V
1.2
8.5
LSB
10-bit resolution
3.6 V  VDD  5.5 V
2.125
39
s
AVREFP = VDD
2.7 V  VDD  5.5 V
3.1875
39
s
1.8 V  VDD  5.5 V
17
39
s
1.6 V  VDD  5.5 V
57
95
s
10-bit resolution
1.8 V  VDD  5.5 V
0.35
% FSR
AVREFP = VDD
1.6 V  VDD  5.5 V
0.60
% FSR
10-bit resolution
1.8 V  VDD  5.5 V
0.35
% FSR
AVREFP = VDD
1.6 V  VDD  5.5 V
0.60
% FSR
10-bit resolution
1.8 V  VDD  5.5 V
3.5
LSB
AVREFP = VDD
1.6 V  VDD  5.5 V
6.0
LSB
10-bit resolution
1.8 V  VDD  5.5 V
2.0
LSB
AVREFP = VDD
1.6 V  VDD  5.5 V
2.5
LSB
VDD
V
1.6
AVREFP
0
and
V
EVDD0
VBGR
2.4 V  VDD  5.5 V,
1.38
1.45
1.5
V
HS (high-speed main) mode
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
This value is indicated as a ratio (% FSR) to the full-scale value.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 89 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(3) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (-) = VSS (ADREFM = 0), target ANI pin: ANI0 to
ANI14, ANI16 to ANI20
(TA = -40 to +85 °C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD,
Reference voltage (-) = VSS)
Parameter
Symbol
Resolution
RES
Overall error Notes 1, 2
AINL
Conversion time
Zero-scale error
tCONV
Notes 1, 2
Full-scale error Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
EZS
EFS
ILE
DLE
Conditions
VAIN
VBGR
TYP.
8
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
Note 1
Analog input voltage
MIN.
MAX.
Unit
10
bit
1.8 V  VDD  5.5 V
1.2
7.0
LSB
1.6 V  VDD  5.5 V
1.2
10.5
LSB
3.6 V  VDD  5.5 V
2.125
39
s
2.7 V  VDD  5.5 V
3.1875
39
s
1.8 V  VDD  5.5 V
17
39
s
1.6 V  VDD  5.5 V
57
95
s
1.8 V  VDD  5.5 V
0.60
% FSR
1.6 V  VDD  5.5 V
0.85
% FSR
1.8 V  VDD  5.5 V
0.60
% FSR
1.6 V  VDD  5.5 V
0.85
% FSR
1.8 V  VDD  5.5 V
4.0
LSB
1.6 V  VDD  5.5 V
6.5
LSB
1.8 V  VDD  5.5 V
2.0
LSB
1.6 V  VDD  5.5 V
2.5
LSB
ANI0 to ANI14
0
VDD
V
ANI16 to ANI20
0
EVDD0
V
1.5
V
2.4 V  VDD  5.5 V,
1.38
1.45
HS (high-speed main) mode
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
This value is indicated as a ratio (% FSR) to the full-scale value.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 90 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(4) When AVREF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF (-) = AVREFM/ANI1
(ADREFM = 1), target ANI pin: ANI0 to ANI14, ANI16 to ANI20
(TA = -40 to +85 °C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR,
Reference voltage (-) = AVREFM = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
Resolution
RES
Conversion time
tCONV
8-bit resolution
2.4 V  VDD  5.5 V
Zero-scale error Notes 1, 2
EZS
8-bit resolution
Integral linearity error Note 1
ILE
Differential linearity error Note 1 DLE
Reference voltage (+)
VBGR
Reference voltage (-)
AVREFM
Analog input voltage
VAIN
TYP.
MAX.
8
Unit
bit
39
s
2.4 V  VDD  5.5 V
0.60
% FSR
8-bit resolution
2.4 V  VDD  5.5 V
2.0
LSB
8-bit resolution
2.4 V  VDD  5.5 V
1.0
LSB
1.5
V
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
This value is indicated as a ratio (% FSR) to the full-scale value.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
MIN.
17
1.38
1.45
VSS
0
V
VBGR
V
Page 91 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.6.2
Temperature sensor characteristics
(TA = -40 to +85 °C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
Temperature sensor output voltage VTMPS25
Setting ADS register = 80H, TA = +25 C
Reference output voltage
VCONST
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
MIN.
TYP.
1.38
1.45
1.05
temperature
Operation stabilization wait time
2.6.3
MAX.
Unit
V
1.5
-3.6
V
mV/C
5
s
MAX.
Unit
8
bit
tAMP
D/A converter characteristics
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Resolution
RES
Overall error
AINL
Settling time
tSET
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Conditions
MIN.
TYP.
Rload = 4 M
1.8 V  VDD  5.5 V
2.5
LSB
Rload = 8 M
1.8 V  VDD  5.5 V
2.5
LSB
Cload = 20 pF
2.7 V  VDD  5.5 V
3
s
1.6 V  VDD < 2.7 V
6
s
Page 92 of 97
RL78/G14
2.6.4
2. ELECTRICAL SPECIFICATIONS
Comparator
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Input voltage range
Symbol
Conditions
MIN.
Ivref
MAX.
EVDD0 +
V
0.3
High-speed comparator
VDD = 3.0 V
V
1.4
-0.3
td
Unit
EVDD0 -
0
Ivcmp
Output delay
TYP.
1.2
s
2.0
s
Input slew rate > 50 mV/s mode, standard mode
High-speed comparator
mode, window mode
3
s
High-speed comparator mode, window mode
0.76 VDD
V
High-speed comparator mode, window mode
0.24 VDD
V
Low-speed comparator mode,
standard mode
High-electric-potential VTW+
judgment voltage
Low-electric-potential
VTW-
judgment voltage
2.6.5
POR circuit characteristics
(TA = -40 to +85 C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width
TYP.
MAX.
Unit
VPOR
Symbol
Power supply rise time
1.51
1.54
V
VPDR
Power supply fall time
1.50
1.53
V
TPW
Detection delay time
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Conditions
MIN.
s
300
350
s
Page 93 of 97
RL78/G14
Caution
2.6.6
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
LVD circuit characteristics
(TA = -40 to +85 C, VPDR  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Detection
Supply voltage level
Symbol
VLVI0
voltage
VLVI1
VLVI2
VLVI3
VLVI4
VLVI5
VLVI6
VLVI7
VLVI8
VLVI9
VLVI10
VLVI11
VLVI12
VLVI13
Minimum pulse width
tLW
Detection delay time
tLD
Caution
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.98
4.06
4.14
V
Power supply fall time
3.90
3.98
4.06
V
Power supply rise time
3.68
3.75
3.82
V
Power supply fall time
3.60
3.67
3.74
V
Power supply rise time
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
Power supply rise time
2.66
2.71
2.76
V
Power supply fall time
2.60
2.65
2.70
V
Power supply rise time
2.56
2.61
2.66
V
Power supply fall time
2.50
2.55
2.60
V
Power supply rise time
2.45
2.50
2.55
V
Power supply fall time
2.40
2.45
2.50
V
Power supply rise time
2.05
2.09
2.13
V
Power supply fall time
2.00
2.04
2.08
V
Power supply rise time
1.94
1.98
2.02
V
Power supply fall time
1.90
1.94
1.98
V
Power supply rise time
1.84
1.88
1.91
V
Power supply fall time
1.80
1.84
1.87
V
Power supply rise time
1.74
1.77
1.81
V
Power supply fall time
1.70
1.73
1.77
V
Power supply rise time
1.64
1.67
1.70
V
Power supply fall time
1.60
1.63
1.66
V
s
300
s
300
Set the detection voltage (VLVI) to be within the operating voltage range. The operating voltage range depends on
the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range.
HS (high-speed main) mode:
VDD = 2.7 to 5.5 [email protected] MHz to 32 MHz
VDD = 2.4 to 5.5 [email protected] MHz to 16 MHz
Remark
LS (low-speed main) mode:
VDD = 1.8 to 5.5 [email protected] MHz to 8 MHz
LV (low voltage main) mode:
VDD = 1.6 to 5.5 [email protected] MHz to 4 MHz
VLVI (n - 1) > VLVIn: n = 1 to 13
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 94 of 97
RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
LVD Detection Voltage of Interrupt & Reset Mode
(TA = -40 to +85 C, VPDR  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Interrupt and reset
VLVI13
mode
VLVI12
VLVI11
VLVI4
VLVI11
VLVI10
VLVI9
VLVI2
VLVI8
VLVI7
VLVI6
VLVI1
VLVI5
VLVI4
VLVI3
VLVI0
Caution
Conditions
VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage: 1.6 V
MIN.
TYP.
MAX.
Unit
1.60
1.63
1.66
V
LVIS0, LVIS1 = 1, 0
Rising release reset voltage
1.74
1.77
1.81
V
(+0.1 V)
Falling interrupt voltage
1.70
1.73
1.77
V
LVIS0, LVIS1 = 0, 1
Rising release reset voltage
1.84
1.88
1.91
V
(+0.2 V)
Falling interrupt voltage
1.80
1.84
1.87
V
LVIS0, LVIS1 = 0, 0
Rising release reset voltage
2.86
2.92
2.97
V
(+1.2 V)
Falling interrupt voltage
2.80
2.86
2.91
V
1.80
1.84
1.87
V
1.94
1.98
2.02
V
VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage: 1.8 V
LVIS0, LVIS1 = 1, 0
Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
1.90
1.94
1.98
V
LVIS0, LVIS1 = 0, 1
Rising release reset voltage
2.05
2.09
2.13
V
(+0.2 V)
Falling interrupt voltage
2.00
2.04
2.08
V
LVIS0, LVIS1 = 0, 0
Rising release reset voltage
3.07
3.13
3.19
V
(+1.2 V)
Falling interrupt voltage
3.00
3.06
3.12
V
2.40
2.45
2.50
V
VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage: 2.4 V
LVIS0, LVIS1 = 1, 0
Rising release reset voltage
2.56
2.61
2.66
V
(+0.1 V)
Falling interrupt voltage
2.50
2.55
2.60
V
LVIS0, LVIS1 = 0, 1
Rising release reset voltage
2.66
2.71
2.76
V
(+0.2 V)
Falling interrupt voltage
2.60
2.65
2.70
V
LVIS0, LVIS1 = 0, 0
Rising release reset voltage
3.68
3.75
3.82
V
(+1.2 V)
Falling interrupt voltage
3.60
3.67
3.74
V
VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V
2.70
2.75
2.81
V
LVIS0, LVIS1 = 1, 0
Rising release reset voltage
2.86
2.92
2.97
V
(+0.1 V)
Falling interrupt voltage
2.80
2.86
2.91
V
LVIS0, LVIS1 = 0, 1
Rising release reset voltage
2.96
3.02
3.08
V
(+0.2 V)
Falling interrupt voltage
2.90
2.96
3.02
V
LVIS0, LVIS1 = 0, 0
Rising release reset voltage
3.98
4.06
4.14
V
(+1.2 V)
Falling interrupt voltage
3.90
3.98
4.06
V
Set the detection voltage (VLVI) to be within the operating voltage range. The operating voltage range depends on
the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range.
HS (high-speed main) mode:
VDD = 2.7 to 5.5 [email protected] MHz to 32 MHz
VDD = 2.4 to 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
VDD = 1.8 to 5.5 [email protected] MHz to 8 MHz
LV (low voltage main) mode:
VDD = 1.6 to 5.5 [email protected] MHz to 4 MHz
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 95 of 97
RL78/G14
2. ELECTRICAL SPECIFICATIONS
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.7
Power Supply Rise Time
(TA = -40 to +85 C, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
VDD rise inclination
2.8
Conditions
MIN.
TYP.
TPUP
MAX.
Unit
53.0
V/ms
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = -40 to +85 C)
Parameter
Data retention supply
voltage
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
5.5
V
1.5 Note
VDDDR
The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is
Note
effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.9
Flash Memory Programming Characteristics
(TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
CPU/peripheral hardware
Symbol
fCLK
Conditions
MIN.
1.8 V  VDD  5.5 V
1
clock frequency
Number of code flash rewrites Cerwr
Number of data flash rewrites
1 erase + 1 write after
Retained for 20 years
the erase is regarded as
(Self/serial
1 rewrite.
programming) Note
The retaining years are
Retained for 1 years
until next rewrite after
(Self/serial
the rewrite.
TYP.
programming)
MAX.
Unit
32
MHz
Times
1,000
1,000,000
Note
Retained for 5 years
100,000
(Self/serial
programming) Note
Note
When using flash memory programmer and Renesas Electronics self programming library.
Remark
When updating data multiple times, use the flash memory as one for updating data.
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 96 of 97
RL78/G14
Caution
2.10
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Timing Specs for Switching Modes
Parameter
Symbol
How long from when a pin reset ends until the initial
tSUINIT
communication settings are specified
Conditions
MIN.
TYP.
POR and LVD reset must end
MAX.
Unit
100
ms
before the pin reset ends.
How long from when the TOOL0 pin is placed at the
tSU
low level until a pin reset ends
POR and LVD reset must end
10
s
1
ms
before the pin reset ends.
How long the TOOL0 pin must be kept at the low
tHD
level after a reset ends
POR and LVD reset must end
before the pin reset ends.
<1>
<2>
<3>
<4>
RESET
tHD+
software
processing
time
TOOL0
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The pins reset ends (POR and LVD reset must end before the pin reset ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the external and internal resets end.
tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end
R01DS0053EJ0100 Rev. 1.00
Feb 21, 2012
Page 97 of 97
REVISION HISTORY
Rev.
Date
Description
Page
0.01
Feb 10, 2011
—
0.02
May 01, 2011
1 to 2
3
4 to 13
14
0.03
Jul 28, 2011
1.00
Feb 21, 2012
RL78/G14 Datasheet
Summary
First Edition issued
1.1 Features revised
1.2 Ordering Information revised
1.3 Pin Configuration (Top View) revised
1.4 Pin Identification revised
15 to 17
1.5.1 30-pin products to 1.5.3 36-pin products revised
23 to 26
1.6 Outline of Functions revised
1
1.1 Features revised
1 to 40
1. OUTLINE revised
41 to 97
2. ELECTRICAL SPECIFICATIONS added
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries
including the United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
C-1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
7.
Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
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