Altera IP Release Notes

Altera IP Release Notes
Altera IP
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2015.11.02
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TOC-2
Altera IP Release Notes
Contents
Altera IP Release Notes....................................................................................... 1-1
Errata............................................................................................................................................................. 1-1
1G/10GbE and Backplane Ethernet 10GBASE-KR PHY Revision History....... 2-1
1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP Core v14.0 Revision History................2-1
1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP Core v13.1 Revision History................2-1
10-Gbps Ethernet (10GbE) MAC Revision History............................................3-1
10-Gbps Ethernet (10GbE) MAC v15.1....................................................................................................3-1
10-Gbps Ethernet (10GbE) MAC v15.0....................................................................................................3-1
10-Gbps Ethernet (10GbE) MAC v14.0....................................................................................................3-2
10-Gbps Ethernet (10GbE) MAC v13.1....................................................................................................3-2
1G/2.5G/10G Multi-rate Ethernet PHY Revision History................................. 4-1
1G/2.5G/10G Multi-rate Ethernet PHY v15.1......................................................................................... 4-1
10GBASE-R PHY IP Core Revision History...................................................... 5-1
10GBASE-R PHY IP Core v14.1 Revision History................................................................................. 5-1
10GBASE-R PHY IP Core v14.0 Revision History................................................................................. 5-1
10GBASE-R PHY IP Core v13.1 Revision History................................................................................. 5-2
40- and 100-Gbps Ethernet MAC and PHY IP Core Revision History..............6-1
40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1....................................................................6-1
40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Update 2.................................................. 6-1
40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0....................................................................6-2
40- and 100-Gbps Ethernet MAC and PHY IP Core v13.1....................................................................6-2
40- and 100-Gbps Ethernet MAC and PHY IP Core v13.0....................................................................6-3
40- and 100-Gbps Ethernet MAC and PHY IP Core v12.1....................................................................6-3
50G Interlaken IP Core Revision History...........................................................7-1
50G Interlaken IP Core v15.1.....................................................................................................................7-1
50G Interlaken IP Core v15.0.....................................................................................................................7-2
50G Interlaken IP Core v14.1.....................................................................................................................7-2
50G Interlaken IP Core v14.0 Arria 10 Edition....................................................................................... 7-3
50G Interlaken IP Core v14.0.....................................................................................................................7-3
50G Interlaken IP Core v13.1 Arria 10 Edition....................................................................................... 7-3
50G Interlaken IP Core v13.1.....................................................................................................................7-4
50G Interlaken IP Core v13.0.....................................................................................................................7-5
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Altera IP Release Notes
TOC-3
100G Interlaken IP Core Revision History.........................................................8-1
100G Interlaken IP Core v15.1...................................................................................................................8-1
100G Interlaken IP Core v15.0...................................................................................................................8-2
100G Interlaken IP Core v14.1...................................................................................................................8-3
100G Interlaken IP Core v14.0 Arria 10 Edition..................................................................................... 8-3
100G Interlaken IP Core v14.0...................................................................................................................8-3
100G Interlaken IP Core v13.1 Arria 10 Edition..................................................................................... 8-4
100G Interlaken IP Core v13.1...................................................................................................................8-5
100G Interlaken IP Core v13.0...................................................................................................................8-5
Arria V GZ Hard IP for PCI Express IP Core Revision History........................ 9-1
Arria V GZ Hard IP for PCI Express IP Core v15.0............................................................................... 9-1
Arria V GZ Hard IP for PCI Express IP Core v14.1............................................................................... 9-2
Arria V GZ Hard IP for PCI Express IP Core v14.0............................................................................... 9-2
Arria V GZ Hard IP for PCI Express IP Core v13.1............................................................................... 9-3
Arria V Hard IP for PCI Express IP Core Revision History............................ 10-1
Arria V Hard IP for PCI Express IP Core v15.0.................................................................................... 10-1
Arria V Hard IP for PCI Express IP Core v14.1.................................................................................... 10-2
Arria V Hard IP for PCI Express IP Core v14.0.................................................................................... 10-2
Arria V Hard IP for PCI Express IP Core v13.1.................................................................................... 10-3
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Revision History.......... 11-1
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.1 Revision History................................. 11-1
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0.1 Revision History.............................. 11-2
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0 Revision History................................. 11-4
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.1 Revision History................................. 11-5
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.0 Revision History................................. 11-5
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v13.1 Revision History................................. 11-6
Arria 10 External Memory Interface IP Revision History............................... 12-1
Arria 10 External Memory Interface IP 15.1..........................................................................................12-1
Arria 10 External Memory Interface IP 15.0..........................................................................................12-1
Arria 10 External Memory Interface IP 14.1 .........................................................................................12-2
Arria 10 External Memory Interface IP 14.0 Arria 10 Edition ........................................................... 12-3
Arria 10 External Memory Interface IP 13.0 Arria 10 Edition ........................................................... 12-3
Arria 10 FPLL IP Core Revision History.......................................................... 13-1
Arria 10 FPLL IP Core Revision History v15.1 Revision History....................................................... 13-1
Arria 10 FPLL IP Core Revision History v15.0 Revision History....................................................... 13-2
Arria 10 FPLL IP Core Revision History v14.1 Revision History....................................................... 13-3
Arria 10 FPLL IP Core Revision History v14.0 Revision History....................................................... 13-3
Arria 10 FPLL IP Core Revision History v13.1 Revision History....................................................... 13-5
Altera Corporation
TOC-4
Altera IP Release Notes
Arria 10 Hard IP for PCI Express IP Core Revision History........................... 14-1
Arria 10 Hard IP for PCI Express IP Core v15.1................................................................................... 14-1
Arria 10 Hard IP for PCI Express IP Core v15.0 .................................................................................. 14-3
Arria 10 Hard IP for PCI Express IP Core v14.1 .................................................................................. 14-4
Arria 10 Hard IP for PCI Express IP Core v14.0 Arria 10 Edition..................................................... 14-5
Arria 10 Hard IP for PCI Express IP Core v13.1 Arria 10 Edition..................................................... 14-6
Arria 10 Transceiver ATX PLL IP Core Revision History............................... 15-1
Arria 10 Transceiver ATX PLL IP Core v15.1 Revision History.........................................................15-1
Arria 10 Transceiver ATX PLL IP Core v15.0 Revision History.........................................................15-2
Arria 10 Transceiver ATX PLL IP Core v14.1 Revision History.........................................................15-3
Arria 10 Transceiver ATX PLL IP Core v14.0 Revision History.........................................................15-3
Arria 10 Transceiver ATX PLL IP Core v13.1 Revision History.........................................................15-4
Arria 10 Transceiver CMU PLL IP Core Revision History.............................. 16-1
Arria 10 Transceiver CMU PLL IP Core v15.1 Revision History....................................................... 16-2
Arria 10 Transceiver CMU PLL IP Core v15.0 Revision History....................................................... 16-2
Arria 10 Transceiver CMU PLL IP Core v14.1 Revision History....................................................... 16-3
Arria 10 Transceiver CMU PLL IP Core v14.0 Revision History....................................................... 16-3
Arria 10 Transceiver CMU PLL IP Core v13.1 Revision History....................................................... 16-4
Arria 10 Transceiver Native PHY IP Core Revision History........................... 17-1
Arria 10 Transceiver Native PHY IP Core v15.1 Revision History.................................................... 17-2
Arria 10 Transceiver Native PHY IP Core v15.0 Revision History.................................................... 17-3
Arria 10 Transceiver Native PHY IP Core v14.1 Revision History.................................................... 17-6
Arria 10 Transceiver Native PHY IP Core v14.0 Revision History.................................................... 17-7
Arria 10 Transceiver Native PHY IP Core v13.1 Revision History.................................................... 17-8
BCH IP Core Revision History......................................................................... 18-1
BCH IP Core v15.1.................................................................................................................................... 18-1
CIC IP Core Revision History........................................................................... 19-1
CIC IP Core v15.0...................................................................................................................................... 19-1
CIC IP Core v14.1...................................................................................................................................... 19-1
CPRI IP Core Revision History.........................................................................20-1
CPRI IP Core v14.1....................................................................................................................................20-1
CPRI IP Core v14.0....................................................................................................................................20-1
CPRI IP Core v13.1....................................................................................................................................20-2
CPRI IP Core v13.0....................................................................................................................................20-2
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Altera IP Release Notes
TOC-5
Cyclone V Hard IP for PCI Express IP Core Revision History........................21-1
Cyclone V Hard IP for PCI Express IP Core v15.0............................................................................... 21-1
Cyclone V Hard IP for PCI Express IP Core v14.1............................................................................... 21-2
Cyclone V Hard IP for PCI Express IP Core v14.0............................................................................... 21-2
Cyclone V Hard IP for PCI Express IP Core v13.0 SP1....................................................................... 21-3
DDR2 and DDR3 SDRAM Controller with UniPHY Revision History.......... 22-1
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v15.1................................................. 22-1
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v15.0................................................. 22-1
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v14.1................................................. 22-2
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v14.0................................................. 22-2
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v13.1................................................. 22-2
DisplayPort IP Core Revision History..............................................................23-1
DisplayPort IP Core v15.1........................................................................................................................ 23-1
DisplayPort IP Core v15.0........................................................................................................................ 23-1
DisplayPort IP Core v14.1........................................................................................................................ 23-3
FIR II IP Core Revision History........................................................................24-1
FIR II IP Core v15.1...................................................................................................................................24-1
FIR II IP Core v15.0...................................................................................................................................24-1
FIR II IP Core v14.1 ..................................................................................................................................24-2
FFT IP Core Revision History...........................................................................25-1
FFT IP Core v15.1...................................................................................................................................... 25-1
FFT IP Core v15.0...................................................................................................................................... 25-1
FFT IP Core v14.1...................................................................................................................................... 25-2
HDMI IP Core Revision History.......................................................................26-1
HDMI IP Core v15.1................................................................................................................................. 26-1
HDMI IP Core v15.0 Update 1................................................................................................................ 26-2
HDMI IP Core v15.0................................................................................................................................. 26-2
HDMI IP Core v14.1................................................................................................................................. 26-3
High-speed Reed-Solomon IP Core Revision History......................................27-1
High-speed Reed-Solomon IP Core v15.1..............................................................................................27-1
Hybrid Memory Cube Controller IP Core Revision History........................... 28-1
Hybrid Memory Cube Controller IP Core v15.1...................................................................................28-1
Hybrid Memory Cube Controller IP Core v15.0...................................................................................28-2
Altera Corporation
TOC-6
Altera IP Release Notes
Interlaken PHY IP Core Revision History........................................................29-1
Interlaken PHY IP Core v14.1 Revision History................................................................................... 29-1
Interlaken PHY IP Core v14.0 Revision History................................................................................... 29-1
Interlaken PHY IP Core v13.1 Revision History................................................................................... 29-2
IP Compiler for PCI Express Revision History................................................ 30-1
IP Compiler for PCI Express v14.1..........................................................................................................30-1
IP Compiler for PCI Express v14.0..........................................................................................................30-1
IP Compiler for PCI Express v13.1..........................................................................................................30-2
IP Compiler for PCI Express v13.0..........................................................................................................30-2
JESD204B IP Core Revision History.................................................................31-1
JESD204B IP Core v15.1........................................................................................................................... 31-1
JESD204B IP Core v15.0........................................................................................................................... 31-2
JESD204B IP Core v14.1 .......................................................................................................................... 31-3
JESD204B IP Core v14.0 Arria 10 Edition Update 1 ........................................................................... 31-5
JESD204B IP Core v14.0 Arria 10 Edition ............................................................................................ 31-5
JESD204B IP Core v14.0 .......................................................................................................................... 31-6
LDPC IP Core Revision History........................................................................32-1
LDPC IP Core v15.1.................................................................................................................................. 32-1
LDPC IP Core v15.0.................................................................................................................................. 32-1
LDPC IP Core v14.1 ................................................................................................................................. 32-2
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Revision
History........................................................................................................... 33-1
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.1.......................................... 33-1
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.0.......................................... 33-5
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1.......................................... 33-8
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Arria 10 Edition.......... 33-12
Low Latency Ethernet 10G MAC IP Core Revision History............................ 34-1
Low Latency Ethernet 10G MAC IP Core v15.1....................................................................................34-1
Low Latency Ethernet 10G MAC IP Core v15.0....................................................................................34-2
Low Latency Ethernet 10G MAC IP Core v14.1....................................................................................34-2
Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition......................................................34-3
Low Latency Ethernet 10G MAC IP Core v14.0 ...................................................................................34-3
Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition......................................................34-4
Low Latency Ethernet 10G MAC IP Core v13.1 ...................................................................................34-4
Nios II Processor Revision History................................................................... 35-1
What's New in v15.1.................................................................................................................................. 35-2
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Altera IP Release Notes
TOC-7
What's New in v15.0.................................................................................................................................. 35-2
What's New in v14.1.................................................................................................................................. 35-3
NCO IP Core Revision History......................................................................... 36-1
NCO IP Core v15.0....................................................................................................................................36-1
NCO IP Core v14.1....................................................................................................................................36-1
QDR II and QDR II+ SRAM Controller with UniPHY Revision History....... 37-1
QDR II and QDR II+ SRAM Controller with UniPHY v15.1.............................................................37-1
QDR II and QDR II+ SRAM Controller with UniPHY v15.0.............................................................37-1
QDR II and QDR II+ SRAM Controller with UniPHY v14.1.............................................................37-2
QDR II and QDR II+ SRAM Controller with UniPHY v14.0.............................................................37-2
QDR II and QDR II+ SRAM Controller with UniPHY v13.1.............................................................37-2
RapidIO IP Core Revision History................................................................... 38-1
RapidIO IP Core v15.1.............................................................................................................................. 38-1
RapidIO IP Core v15.0.............................................................................................................................. 38-2
RapidIO IP Core v14.1.............................................................................................................................. 38-2
RapidIO IP Core v14.0 Arria 10 Edition................................................................................................ 38-3
RapidIO IP Core v14.0.............................................................................................................................. 38-8
RapidIO IP Core v13.1.............................................................................................................................. 38-9
RapidIO IP Core v13.0.............................................................................................................................. 38-9
RapidIO II IP Core Revision History............................................................... 39-1
RapidIO II IP Core v15.1.......................................................................................................................... 39-1
RapidIO II IP Core v14.1.......................................................................................................................... 39-2
RapidIO II IP Core v14.0 Arria 10 Edition............................................................................................ 39-3
RapidIO II IP Core v14.0.......................................................................................................................... 39-6
RapidIO II IP Core v13.1.......................................................................................................................... 39-6
RapidIO II IP Core v13.0.......................................................................................................................... 39-7
Reed-Solomon II IP Core Revision History......................................................40-1
Reed-Solomon II IP Core v15.1............................................................................................................... 40-1
Reed-Solomon II IP Core v15.0............................................................................................................... 40-1
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core
Revision History............................................................................................ 41-1
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core v15.1......................... 41-1
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core v15.0......................... 41-1
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core v14.1......................... 41-2
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core v14.0......................... 41-2
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core v13.1......................... 41-3
Altera Corporation
TOC-8
Altera IP Release Notes
SDI Revision History.........................................................................................42-1
SDI v15.1..................................................................................................................................................... 42-1
SDI v15.0..................................................................................................................................................... 42-1
SDI v14.0..................................................................................................................................................... 42-2
SDI II IP Core Revision History....................................................................... 43-1
SDI II IP Core v15.1...................................................................................................................................43-1
SDI II IP Core v15.0...................................................................................................................................43-2
SDI II IP Core v14.1...................................................................................................................................43-2
SDI Audio IP Cores Revision History...............................................................44-1
SDI Audio IP Cores v15.1.........................................................................................................................44-1
SDI Audio IP Cores v15.0.........................................................................................................................44-1
SDI Audio IP Cores v14.0.........................................................................................................................44-2
SerialLite II Revision History............................................................................45-1
SerialLite II v14.0....................................................................................................................................... 45-1
SerialLite II v13.1....................................................................................................................................... 45-1
SerialLite III Streaming IP Core Revision History...........................................46-1
SerialLite III Streaming IP Core v15.1.................................................................................................... 46-1
SerialLite III Streaming IP Core v15.0.................................................................................................... 46-2
SerialLite III Streaming IP Core v14.1.................................................................................................... 46-2
SerialLite III Streaming IP Core v14.0 Arria 10 Edition.......................................................................46-3
SerialLite III Streaming IP Core v14.0.................................................................................................... 46-6
SerialLite III Streaming IP Core v13.1.................................................................................................... 46-6
SerialLite III Streaming IP Core v13.0.................................................................................................... 46-6
SmartVID Controller IP Core Revision History.............................................. 47-1
SmartVID Controller v15.1...................................................................................................................... 47-1
SmartVID Controller v15.0...................................................................................................................... 47-1
SmartVID Controller v14.1...................................................................................................................... 47-2
Stratix V Hard IP for PCI Express IP Core Revision History.......................... 48-1
Stratix V Hard IP for PCI Express IP Core v15.0..................................................................................48-1
Stratix V Hard IP for PCI Express IP Core v14.1..................................................................................48-2
Stratix V Hard IP for PCI Express IP Core v14.0..................................................................................48-2
Stratix V Hard IP for PCI Express IP Core v13.1..................................................................................48-3
Triple Speed Ethernet IP Core Revision History..............................................49-1
Triple Speed Ethernet IP Core v15.1.......................................................................................................49-1
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Altera IP Release Notes
TOC-9
Triple Speed Ethernet IP Core v15.0.......................................................................................................49-2
Triple Speed Ethernet IP Core v14.0 Arria 10 Edition......................................................................... 49-2
Triple Speed Ethernet IP Core v14.0.......................................................................................................49-2
Triple Speed Ethernet IP Core v13.1 Arria 10 Edition......................................................................... 49-3
Triple Speed Ethernet IP Core v13.1 ......................................................................................................49-3
Turbo IP Core Revision History....................................................................... 50-1
Turbo IP Core v15.1.................................................................................................................................. 50-1
Video and Image Processing Suite Revision History....................................... 51-1
Video and Image Processing Suite v15.1................................................................................................ 51-1
Video and Image Processing Suite v15.0................................................................................................ 51-2
Video and Image Processing Suite v14.1................................................................................................ 51-3
Viterbi IP Core Revision History......................................................................52-1
Viterbi IP Core v15.0.................................................................................................................................52-1
Viterbi IP Core v14.1.................................................................................................................................52-1
V-Series Avalon-MM DMA for PCI Express IP Core Revision History.......... 53-1
V-Series Avalon-MM DMA PCI Express IP Core v15.1......................................................................53-1
V-Series Avalon-MM DMA PCI Express IP Core v14.1......................................................................53-1
V-Series Avalon-MM DMA PCI Express IP Core v14.0......................................................................53-2
V-Series Avalon-MM DMA PCI Express IP Core v15.0......................................................................53-2
XAUI PHY Revision History.............................................................................54-1
XAUI PHY IP Core v14.1 Revision History...........................................................................................54-1
XAUI PHY IP Core v14.0 Arria 10 Revision History...........................................................................54-2
XAUI PHY IP Core v14.0 Revision History...........................................................................................54-2
XAUI PHY IP Core v13.1 Revision History...........................................................................................54-3
Other IP Cores Product Revision History........................................................ 55-1
Altera Advanced SEU Detection IP Core v14.1.....................................................................................55-1
Altera Dual Configuration v14.0 Update 2............................................................................................ 55-1
Altera EMR Unloader IP Core v14.1.......................................................................................................55-2
ALTERA_FP_FUNCTIONS v15.0..........................................................................................................55-2
ALTERA_FP_MATRIX_MULT v14.1................................................................................................... 55-3
Altera OCT IP Core v14.0 Arria 10 Edition...........................................................................................55-3
Altera GPIO IP Core v14.0 Arria 10 Edition......................................................................................... 55-4
Altera GPIO Lite IP Core v14.0 Update 2.............................................................................................. 55-5
Altera Modular ADC IP Core v14.0 Update 2.......................................................................................55-5
Altera LVDS SERDES IP Core v14.1.......................................................................................................55-5
Altera LVDS SERDES IP Core v14.0 Arria 10 Edition.........................................................................55-6
Altera PHYLite for Parallel Interfaces IP Core v15.1............................................................................55-6
Altera PHYLite for Memory IP Core v14.1............................................................................................55-7
Altera Corporation
TOC-10
Altera IP Release Notes
Altera PHYLite for Memory IP Core v14.0 Arria 10 Edition.............................................................. 55-7
Altera On-Chip Flash IP Core v15.1....................................................................................................... 55-7
Altera On-Chip Flash IP Core v14.1....................................................................................................... 55-8
Altera On-Chip Flash IP Core v14.0 Update 2...................................................................................... 55-8
Altera Soft LVDS IP Core v14.0 Update 2..............................................................................................55-8
Altera Voltage Sensor IP Core v15.0....................................................................................................... 55-9
Arria 10 Native Fixed Point DSP IP Core v14.1.................................................................................... 55-9
Internal Oscillator IP Core v14.0 Update 2............................................................................................55-9
RAM: 1-port and RAM: 2-port v14.0 Arria 10 Edition......................................................................55-10
SCFIFO and DCFIFO IP Cores v15.1................................................................................................... 55-10
SLD Hub Controller System v14.1........................................................................................................ 55-10
Other Transceiver IP Cores Product Revision History.................................... 56-1
Transceiver PHY Reset Controller IP Core v15.1 Revision History...................................................56-1
Transceiver PHY Reset Controller IP Core v14.1 Revision History...................................................56-2
Transceiver PHY Reset Controller IP Core v14.0 Arria 10 Revision History................................... 56-2
Transceiver PHY Reset Controller IP Core v13.0 Arria 10 Revision History................................... 56-2
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Altera IP Release Notes
2015.11.02
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These release notes include versions 15.1, 15.0, and 14.1 of Altera® IP cores, including the Altera IP
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Errata
Errata are functional defects or errors, which may cause the product to deviate from published specifica‐
tions. Documentation issues include errors, unclear descriptions, or omissions from current published
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For full information on errata and the versions affected by errata, refer to the Knowledge Base page of the
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© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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1G/10GbE and Backplane Ethernet 10GBASEKR PHY Revision History
2
2015.11.02
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP Core v14.0
Revision History
Table 2-1: v14.0 July 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Impact
-
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP core in the Knowledge Base
• Introduction to Altera IP Cores
1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP Core v13.1
Revision History
Table 2-2: v13.1 November 2013
Description
Verified in the Quartus II software v13.1
Impact
-
Related Information
• Altera Transceiver PHY IP Core User Guide
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
2-2
1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP Core v13.1 Revision...
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• Errata for 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP core in the Knowledge Base
• Introduction to Altera IP Cores
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1G/10GbE and Backplane Ethernet 10GBASE-KR PHY Revision History
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10-Gbps Ethernet (10GbE) MAC Revision
History
2015.11.02
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
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Altera Complete Design Suite Update Release Notes
10-Gbps Ethernet (10GbE) MAC v15.1
Table 3-1: v15.1 November 2015
Description
Impact
Enhanced unidirectional feature to support user-triggered remote fault —
notification through the register bit.
Related Information
• Introduction to Altera IP Cores
• 10-Gbps Ethernet (10GbE) MAC MegaCore Function User Guide
• Errata for 10-Gbps Ethernet (10GbE) MAC MegaCore Function in the Knowledge Base
10-Gbps Ethernet (10GbE) MAC v15.0
Table 3-2: v15.0 May 2015
Description
Added new TX and RX registers, vlandet_dis, in the frame decoder
for the option to disable VLAN or stacked VLAN tag detection. To
disable the detection of VLAN/SVLAN type frame (length type field =
0x8100), set the register to 1.
Impact
This new register is available
when you upgrade the IP core to
v15.0
Related Information
• Introduction to Altera IP Cores
• 10-Gbps Ethernet (10GbE) MAC MegaCore Function User Guide
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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10-Gbps Ethernet (10GbE) MAC v14.0
• Errata for 10-Gbps Ethernet (10GbE) MAC MegaCore Function in the Knowledge Base
10-Gbps Ethernet (10GbE) MAC v14.0
Table 3-3: v14.0 June 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Added support for clause 66 of IEEE 802.3—synthesis option.
This change is optional. If you
do not upgrade your IP core, it
does not have this new feature.
Related Information
• Introduction to Altera IP Cores
• 10-Gbps Ethernet (10GbE) MAC MegaCore Function User Guide
• Errata for 10-Gbps Ethernet (10GbE) MAC MegaCore Function in the Knowledge Base
10-Gbps Ethernet (10GbE) MAC v13.1
Table 3-4: v13.1 November 2013
Description
Impact
Removed support for the following devices:
-
• Arria GX
• HardCopy IV GX
• Stratix II GX
Removed 1G/10GbE MAC and 10M-10GbE MAC with IEEE 1588v2
design examples from the directory.
-
The 10GbE MAC with 10GBASE-R PHY and IEEE 1588v2 configura‐
tion supports only Arria V GT device with speed grade 3_H3.
-
Increased the width for path delay interface signals such as tx_path_
delay_10g_data (16 bits), tx_path_delay_1g_data (22 bits), rx_
path_delay_10g_data (16 bits), and rx_path_delay_1g_data (22
bits)
-
Related Information
• Introduction to Altera IP Cores
• 10-Gbps Ethernet (10GbE) MAC MegaCore Function User Guide
• Errata for 10-Gbps Ethernet (10GbE) MAC MegaCore Function in the Knowledge Base
Altera Corporation
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1G/2.5G/10G Multi-rate Ethernet PHY v15.1
Table 4-1: v15.1 November 2015
Description
Initial release.
Impact
—
• 2.5G, 1G/2.5G, and 1G/2.5/10G operating modes.
• Supports auto-negotiation.
• Provides required latencies for the IEEE 1588v2 feature.
Related Information
• Introduction to Altera IP Cores
• 1G/2.5G/10G Multi-rate Ethernet PHY User Guide
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
10GBASE-R PHY IP Core v14.1 Revision History
Table 5-1: v14.1 December 2014
Description
Verified in Quartus II software v14.1
Impact
-
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for 10GBASE-R PHY in the Knowledge Base
• Introduction to Altera IP Cores
10GBASE-R PHY IP Core v14.0 Revision History
Table 5-2: v14.0 July 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Added OpenCore Plus evaluation feature support for IEEE 1588
Precision Time Protocol.
-
Related Information
• Altera Transceiver PHY IP Core User Guide
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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10GBASE-R PHY IP Core v13.1 Revision History
• Errata for 10GBASE-R PHY in the Knowledge Base
• Introduction to Altera IP Cores
10GBASE-R PHY IP Core v13.1 Revision History
Table 5-3: v13.1 November 2013
Description
Verified in the Quartus II software v13.1
Impact
-
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for 10GBASE-R PHY in the Knowledge Base
• Introduction to Altera IP Cores
Altera Corporation
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1
Table 6-1: Version 14.1 December 2014
Description
Impact
Notes
Verified in the Quartus II
software v14.1
Related Information
• 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Update 2
Table 6-2: Version 14.0 Update 2 September 2014
Description
Fixed an issue in which incoming
runt Ethernet packets of size one
byte to eight bytes caused the
40GbE IP core to hang instead of
handling the error.
Impact
Notes
If you upgrade to version 14.0 Update 2 of the Quartus
II software, you must upgrade your 40-100GbE IP core
to incorporate this fix. The fix has no effect on 100GbE
IP cores, which did not have the issue. However, the
previous versions of the 40-100GbE IP core require
upgrade with the Quartus II software.
Related Information
• 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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• Errata for 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0
Table 6-3: Version 14.0 June 2014
Description
Impact
Notes
Upgraded to support the new IP Catalog. For more informa‐
tion about the IP Catalog, refer to IP Catalog and Parameter
Editor in Introduction to Altera IP Cores.
Upgrading your IP
core for this change is
optional.
Added OpenCore Plus support for 40GBASE-KR4 variations.
Upgrading your IP
core for this change is
optional.
Related Information
• Introduction to Altera IP Cores
• 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
40- and 100-Gbps Ethernet MAC and PHY IP Core v13.1
Table 6-4: Version 13.1 November 2013
Description
Impact
Notes
Added 40GBASE-KR4 option with FEC and with auto-negotiation and link
training mode options.
Added Synchronous Ethernet clock support option in Stratix V devices. The
option separates the TX PLL and RX CDR input reference clocks (tx_ref_
clk and rx_ref_clk signals replace ref_clk for these variations) and
exposes the RX recovered clock.
Exposed link fault signals remote_fault_status and local_fault_status
in duplex variations.
Exposed PHY status signals tx_lanes_stable and lanes_deskewed in
MAC&PHY variations.
Updated and simplified the example design and testbench. The testbench
stimulus is simpler and the user no longer needs to configure the DUT with a
specific name and clock rate.
Related Information
• 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
Altera Corporation
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40- and 100-Gbps Ethernet MAC and PHY IP Core v13.0
Table 6-5: Version 13.0 May 2013
Description
Impact
Notes
Added preamble pass-through option.
Added transmitter average inter-packet gap (IPG) adjustment option.
Related Information
• 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
40- and 100-Gbps Ethernet MAC and PHY IP Core v12.1
Table 6-6: Version 12.1 November 2012
Description
Impact
Notes
Verified with the Quartus II software v12.1.
Related Information
• 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
40- and 100-Gbps Ethernet MAC and PHY IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
50G Interlaken IP Core v15.1
Table 7-1: Version 15.1 November 2015
Description
Impact
Notes
Added new Enable Native XCVR PHY
ADME parameter for Arria 10 variations..
Upgrading the IP core to incorporate this This
feature is optional. This change does not parameter
affect the top-level signals of the IP core. exposes
control of
transceiver
configuration
features.
Added hardware design example for Arria 10
variations.
A hardware design example is now
available with Arria 10 variations of the
50G Interlaken IP core.
Modified instructions to generate legacy
testbench.
Related Information
• 50G Interlaken MegaCore Function User Guide
• Errata for 50G Interlaken IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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50G Interlaken IP Core v15.0
Table 7-2: Version 15.0 May 2015
Description
Impact
Notes
Added new TX scrambler seed parameter.
This feature adds support for
modification of the TX scrambler
seed for Arria 10 variations. If your
design includes multiple IP cores,
you should ensure they have
different TX scrambler seed values.
Previously this functionality was not
available for Arria 10 variations.
In addition, starting in the IP core
version 15.0, you must refrain from
modifying the RTL parameter
SCRAM_CONST in Stratix V and Arria
V GZ variations, and use the new
parameter in the Parameter Editor
instead.
Related Information
• 50G Interlaken MegaCore Function User Guide
• Errata for 50G Interlaken IP core in the Knowledge Base
50G Interlaken IP Core v14.1
Table 7-3: Version 14.1 December 2014
Description
The Quartus II software v14.1 requires that
you specify a device if your IP core targets the
Arria 10 device family. If you do not specify
your target Arria 10 device, the IP Upgrade
tool insists that your IP core requires upgrade,
but does not clarify the reason.
Impact
Notes
IYou must ensure that you specify a
device for your v13.1 Arria 10
Edition or v14.0 Arria 10 Edition IP
core variation and regenerate it in
the Quartus II software v14.1.
Related Information
• 50G Interlaken MegaCore Function User Guide
• Errata for 50G Interlaken IP core in the Knowledge Base
Altera Corporation
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50G Interlaken IP Core v14.0 Arria 10 Edition
Table 7-4: Version 14.0 Arria 10 Edition August 2014
Description
Impact
Notes
Verified in the Quartus II software v14.0 Arria 10 Edition.
Related Information
• 50G Interlaken MegaCore Function User Guide
• Errata for 50G Interlaken IP core in the Knowledge Base
50G Interlaken IP Core v14.0
Table 7-5: Version 14.0 June 2014
Description
Impact
Notes
New required frequency for input clock signals tx_usr_clk and rx_usr_
clk is 250 MHz, and the two clocks must be driven at the same frequency. If
you provide a clock with a different frequency, it must be in the range of 200
MHz to 300 MHz, and you must modify the new hidden (RTL) parameter
TX_USR_CLK_MHZ to the new value in the files <instance_name>/ilk_core_50g.sv
for synthesis and <instance_name>_sim/ilk_core_50g.sv for simulation.
Upgraded to support the new IP Catalog. For more information about the
IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to
Altera IP Cores.
Improved resource utilization by 20% and latency by 55%.
Related Information
• Introduction to Altera IP Cores
• 50G Interlaken MegaCore Function User Guide
• Errata for 50G Interlaken IP core in the Knowledge Base
50G Interlaken IP Core v13.1 Arria 10 Edition
Table 7-6: Version 13.1 Arria 10 Edition December 2013
Description
Impact
Notes
Added support for Arria 10 devices. IP core variations that target an Arria
10 device have additional interfaces and design requirements.
50G Interlaken IP Core Revision History
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Table 7-7: 50G Interlaken IP Core Signal Changes
Signals added or modified in version 13.1 Arria 10 Edition.
Old Signal Name
New Signal Name
—
tx_serial_clk
—
tx_pll_locked
—
tx_pll_powerdown
—
tx_cal_busy
—
reconfig_clk
—
reconfig_reset
—
reconfig_read
—
reconfig_write
—
reconfig_
address[12:0]
—
reconfig_
readdata[31:0]
—
reconfig_
waitrequest
—
reconfig_
writedata[31:0]
reconfig_to_xcvr
Not present in Arria
10 variations.
reconfig_from_xcvr
Not present in
Arria 10
variations.
Notes
New interface to external TX PLL. Relevant for
Arria 10 variations only.
New Arria 10 transceiver reconfiguration
interface. Relevant for Arria 10 variations only.
Transceiver reconfiguration interface for Arria V
and Stratix V variations. This interface is present
only in Arria V and Stratix V variations (as
supported in past and future versions of the
Quartus II software). It is not present in Arria 10
variations.
Related Information
• 50G Interlaken MegaCore Function User Guide
• Errata for 50G Interlaken IP core in the Knowledge Base
50G Interlaken IP Core v13.1
Table 7-8: Version 13.1 November 2013
Description
Impact
Notes
Verified in the Quartus II software v13.1.
Altera Corporation
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Related Information
• 50G Interlaken MegaCore Function User Guide
• Errata for 50G Interlaken IP core in the Knowledge Base
50G Interlaken IP Core v13.0
Table 7-9: Version 13.0 May 2013
Description
Impact
Notes
Initial release.
Related Information
• 50G Interlaken MegaCore Function User Guide
• Errata for 50G Interlaken IP core in the Knowledge Base
50G Interlaken IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
100G Interlaken IP Core v15.1
Table 8-1: Version 15.1 November 2015
Description
Impact
Notes
Added new Enable Native XCVR PHY
ADME parameter for Arria 10 variations..
Upgrading the IP core to incorporate this This
feature is optional. This change does not parameter
affect the top-level signals of the IP core. exposes
control of
transceiver
configuration
features.
Changed behavior of irx_err signal.
Previously, if the IP core could not determine
the burst in which the error occurred, it
asserted the irx_err signal anyway, and the
client could also not determine the associated
burst. Now, if the IP core cannot determine
the burst in which an error occurred, it does
not assert the irx_err signal. If it can
determine the burst in which an error
occurred, it asserts the irx_err signal during
the end of burst cycle (when it also asserts
irx_eob).
This change ensures that apparent errors Refer to 100G
that occur during Idle cycles do not cause Interlaken IP
the irx_err signal to assert.
Core Signal
Changes
Upgrading the IP core to incorporate this
v15.1 table.
feature is optional. If you upgrade your
IP core you should be aware of the
change in signal behavior.
Added hardware design example for Arria 10
variations.
A hardware design example is now
available with tArria 10 variations of the
100G Interlaken IP core.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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100G Interlaken IP Core v15.0
Description
Impact
Notes
Modified instructions to generate legacy
testbench.
Table 8-2: 100G Interlaken IP Core Signal Changes v15.1
Signals added or modified in version 15.1.
Old Signal Name
irx_err
New Signal Name
irx_err
Notes
Changed behavior of irx_err signal. The IP core
asserts the signal in a subset of the cases in which it
asserted this signal in the previous release, and always
asserts this signal synchronously with the irx_eob
signal of the burst in which the error occurred.
Related Information
• 100G Interlaken MegaCore Function User Guide
• Errata for 100G Interlaken IP core in the Knowledge Base
100G Interlaken IP Core v15.0
Table 8-3: Version 15.0 May 2015
Description
Added new TX scrambler seed parameter.
Impact
Notes
This feature adds support for
modification of the TX scrambler seed
for Arria 10 variations. If your design
includes multiple IP cores, you should
ensure they have different TX scrambler
seed values. Previously this functionality
was not available for Arria 10 variations.
In addition, starting in the IP core
version 15.0, you must refrain from
modifying the RTL parameter SCRAM_
CONST in Stratix V and Arria V GZ
variations, and use the new parameter in
the Parameter Editor instead.
Related Information
• 100G Interlaken MegaCore Function User Guide
• Errata for 100G Interlaken IP core in the Knowledge Base
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100G Interlaken IP Core v14.1
100G Interlaken IP Core v14.1
Table 8-4: Version 14.1 December 2014
Description
Impact
The Quartus II software v14.1 requires that
you specify a device if your IP core targets the
Arria 10 device family. If you do not specify
your target Arria 10 device, the IP Upgrade
tool insists that your IP core requires upgrade,
but does not clarify the reason.
Notes
You must ensure that you specify a device
for your v13.1 Arria 10 Edition or v14.0
Arria 10 Edition IP core variation and
regenerate it in the Quartus II software
v14.1.
Related Information
• 100G Interlaken MegaCore Function User Guide
• Errata for 100G Interlaken IP core in the Knowledge Base
100G Interlaken IP Core v14.0 Arria 10 Edition
Table 8-5: Version 14.0 Arria 10 Edition August 2014
Description
Impact
Notes
Impact
Notes
Verified in the Quartus II software v14.0 Arria 10 Edition.
Related Information
• 100G Interlaken MegaCore Function User Guide
• Errata for 100G Interlaken IP core in the Knowledge Base
100G Interlaken IP Core v14.0
Table 8-6: Version 14.0 June 2014
Description
Removed mm_clk_locked input signal.
Port
change.
Removed hidden parameter CNTR_BITS from top level RTL files.
Upgraded to support the new IP Catalog. For more information about the IP
Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP
Cores.
Related Information
• Introduction to Altera IP Cores
100G Interlaken IP Core Revision History
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100G Interlaken IP Core v13.1 Arria 10 Edition
• 100G Interlaken MegaCore Function User Guide
• Errata for 100G Interlaken IP core in the Knowledge Base
100G Interlaken IP Core v13.1 Arria 10 Edition
Table 8-7: Version 13.1 Arria 10 Edition December 2013
Description
Impact
Notes
Added support for Arria 10 devices. IP core variations that target an Arria
10 device have additional interfaces and design requirements.
Table 8-8: 100G Interlaken IP Core Signal Changes
Signals added or modified in version 13.1 Arria 10 Edition.
Old Signal Name
New Signal Name
—
tx_serial_clk
—
tx_pll_locked
—
tx_pll_powerdown
—
tx_cal_busy
—
reconfig_clk
—
reconfig_reset
—
reconfig_read
—
reconfig_write
—
reconfig_
address[13:0] or
reconfig_
address[14:0]
—
reconfig_
readdata[31:0]
—
reconfig_
waitrequest
—
reconfig_
writedata[31:0]
reconfig_to_xcvr
Not present in Arria
10 variations.
reconfig_from_xcvr
Not present in
Arria 10
variations.
Altera Corporation
Notes
New interface to external TX PLL. Relevant for
Arria 10 variations only.
New Arria 10 transceiver reconfiguration
interface. Relevant for Arria 10 variations only.
Transceiver reconfiguration interface for Arria V
and Stratix V variations. This interface is present
only in Arria V and Stratix V variations (as
supported in past and future versions of the
Quartus II software). It is not present in Arria 10
variations.
100G Interlaken IP Core Revision History
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Related Information
• 100G Interlaken MegaCore Function User Guide
• Errata for 100G Interlaken IP core in the Knowledge Base
100G Interlaken IP Core v13.1
Table 8-9: Version 13.1 November 2013
Description
Impact
Notes
Impact
Notes
Added optional ECC feature on M20K blocks in Stratix V devices.
Added bit error injection testing feature to check CRC24 error detection.
Changed implementation of single segment mode:
• Changed parameter name from Received data format to Data format.
• If you select Single segment mode, the IP core can no longer handle incoming
dual segment traffic on the TX client data interface.
Added four new parameters to optionally include advanced error reporting and
handling, Stratix V M20K block ECC feature, diagnostic features, and in-band flow
control functionality. Excluding the features improves resource utilization.
Changed the behavior of the management interface during read operations. The IP
core asserts the mm_rddata_valid signal two mm_clk cycles after the mm_read
signal is asserted, instead of one mm_clk cycle as in previous versions of the IP core.
Related Information
• 100G Interlaken MegaCore Function User Guide
• Errata for 100G Interlaken IP core in the Knowledge Base
100G Interlaken IP Core v13.0
Table 8-10: Version 13.0 May 2013
Description
Added dual segment mode.
Added packet mode option in parameter editor.
Improved error handling.
Added PRBS capability.
Added CRC-32 error injection capability.
Related Information
• 100G Interlaken MegaCore Function User Guide
100G Interlaken IP Core Revision History
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Arria V GZ Hard IP for PCI Express IP Core
Revision History
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Arria V GZ Hard IP for PCI Express IP Core v15.0
Table 9-1: v15.0 May 2015
Description
Impact
In IP core variations with the Avalon-MM DMA interface, added
support for downstream burst read request for a payload of size up to 4
KBytes, if Enable burst capability for RXM BAR2 port is turned on in
the Parameter Editor. Previous maximum downstream read request
payload size was 512 bytes.
If you choose the Avalon-MM
DMA interface, the IP core can
receive and process a burst read
request for a payload of any size
supported by the PCI Express
specification (up to 4 KBytes), if
it receives such a burst read
request on the PCI Express link.
In IP core variations with the Avalon-MM interface, added support to
send message TLPs with data payload of any length from a Root Port.
If you choose the Avalon-MM
interface, a Root Port IP core can
send messages with payload
greater than 1 dword.
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Arria V GZ Hard IP for PCI Express in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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Arria V GZ Hard IP for PCI Express IP Core v14.1
Arria V GZ Hard IP for PCI Express IP Core v14.1
Table 9-2: v14.1 December 2014
Description
Impact
Reduced Quartus II compilation warnings by 50%.
Reduces time required to vet
compilation warnings.
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Arria V GZ Hard IP for PCI Express in the Knowledge Base
Arria V GZ Hard IP for PCI Express IP Core v14.0
Table 9-3: v14.0 June 2014
Description
Impact
Made the following changes for the V-Series PCIe with Avalon-MM
DMA Interface (previously called the Avalon-MM 256-bit Hard IP for
PCI Express IP Core):
•
•
•
•
•
•
•
•
The Descriptor Controller IP
core included in the 14.0 release
is significantly different from the
one included in 13.1. Altera
Revised programming model and optimized the performance of the
recommends that you update to
Descriptor Controller.
the 14.0 version. Altera will no
Added support for either 128- or 256-bit interface to the Applica‐
longer support the 13.1 version
tion Layer.
Added support for 64-bit addressing, making address translation
unnecessary.
Added support for optional bursting RX Master for BAR2.
Added access to selected Configuration Space registers and link
status registers through the optional Control Register Access (CRA)
Avalon-MM slave port.
Added parameters to enable 256 completion tags with completion
tag checking performed in Application Layer.
Simulation support for Phase 2 and Phase 3 equalization when
requested by third-party BFM for Gen3 variants.
Due to the many changes, the support level has reverted to prelimi‐
nary.
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Arria V GZ Hard IP for PCI Express IP Core v13.1
Description
9-3
Impact
Made the following changes to the Avalon-MM Arria V GZ Hard IP
for PCI Express IP core :
•
•
•
•
•
•
•
All of these new features are
optional. If you choose to
include an optional feature that
Added access to selected Configuration Space registers and link
changes the port signature of
status registers through the optional Control Register Access (CRA)
your IP core, you must
Avalon-MM slave port.
regenerate your design and
Added optional hard IP status bus that includes signals necessary to connect the signals.
connect the Transceiver Reconfiguration Controller IP Core.
Added optional hard IP status extension bus which includes signals
that are useful for debugging, including: link training, status, error,
and Configuration Space signals.
Added support for 64-bit addressing, making address translation
unnecessary.
Added parameters to enable 256 completion tags with completion
tag checking performed in Application Layer.
Simulation support for Phase 2 and Phase 3 equalization when
requested by third-party BFM.
Increased CRA address to 14 bits from 12 bits.
Upgraded the Avalon-ST version to support the new IP Catalog. For
more information about the IP Catalog, refer to IP Catalog and
Parameter Editor in Introduction to Altera IP Cores
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Arria V GZ Hard IP for PCI Express in the Knowledge Base
Arria V GZ Hard IP for PCI Express IP Core v13.1
Table 9-4: v13.1 November 2013
Description
Support for Avalon-MM 256-Bit Hard IP for PCI Express Gen3 ×8
with DMA is final.
Impact
-
Support for Gen2 CvP is removed.
Related Information
• Introduction to Altera IP Cores
• Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
• Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide
Arria V GZ Hard IP for PCI Express IP Core Revision History
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• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
• Errata for Arria V GZ Hard IP for PCI Express in the Knowledge Base
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Arria V Hard IP for PCI Express IP Core v15.0
Table 10-1: v15.0 May 2015
Description
Impact
In IP core variations with the Avalon-MM DMA interface, added
support for downstream burst read request for a payload of size up to 4
KBytes, if Enable burst capability for RXM BAR2 port is turned on in
the Parameter Editor. Previous maximum downstream read request
payload size was 512 bytes.
If you choose the Avalon-MM
DMA interface, the IP core can
receive and process a burst read
request for a payload of any size
supported by the PCI Express
specification (up to 4 KBytes), if
it receives such a burst read
request on the PCI Express link.
In IP core variations with the Avalon-MM interface, added support to
send message TLPs with data payload of any length from a Root Port.
If you choose the Avalon-MM
interface, a Root Port IP core can
send messages with payload
greater than 1 dword.
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Arria V Avalon-ST Interface for PCIe Solutions User Guide
Arria V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Arria V Hard IP for PCI Express in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
10-2
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Arria V Hard IP for PCI Express IP Core v14.1
Arria V Hard IP for PCI Express IP Core v14.1
Table 10-2: v14.1 December 2014
Description
Impact
Reduced Quartus II compilation warnings by 50%.
Reduces time required to vet
compilation warnings.
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Arria V Avalon-ST Interface for PCIe Solutions User Guide
Arria V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Arria V Hard IP for PCI Express in the Knowledge Base
Arria V Hard IP for PCI Express IP Core v14.0
Table 10-3: v14.0 June 2014
Description
Impact
Upgraded the Avalon-ST version to support the new IP Catalog. For
more information about the IP Catalog, refer to IP Catalog and
Parameter Editor in Introduction to Altera IP Cores.
-
Upgraded Arria V Hard IP for PCI Express IP core to support the new
IP Catalog.
-
Added support for new, V-Series PCIe with Avalon-MM DMA
Interface IP Core.
-
Arria V Avalon-MM Hard IP for PCI Express IP core. :
All of these new features are
optional. If you include either
• Added access to selected Configuration Space and link status
the hard IP status bus or status
registers through the optional Control Register Access (CRA)
extension bus in you design, you
Avalon-MM slave port.
must regenerate your design and
• Added optional hard IP status bus that includes signals necessary to connect the new bus
connect the Transceiver Reconfiguration Controller IP Core.
• Added optional hard IP status extension bus which includes signals
that are useful for debugging, including: link training, status, error,
and Configuration Space signals.
Related Information
• Introduction to Altera IP Cores
• Arria V Avalon-ST Interface for PCIe Solutions User Guide
• Arria V Avalon-MM Interface for PCIe Solutions User Guide
Altera Corporation
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10-3
• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
• Errata for Arria V Hard IP for PCI Express in the Knowledge Base
Arria V Hard IP for PCI Express IP Core v13.1
Table 10-4: v13.1 November 2013
Description
Added support for Gen2 Configuration via Protocol (CvP) using
an .ini file. Contact your sales representative for more information.
Impact
-
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Arria V Avalon-ST Interface for PCIe Solutions User Guide
Arria V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Arria V Hard IP for PCI Express in the Knowledge Base
Arria V Hard IP for PCI Express IP Core Revision History
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Arria 10 1G/10GbE and 10GBASE-KR PHY IP
Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.1 Revision History
Table 11-1: v15.1 November 2015
Description
Impact
Verified in Quartus Prime software v15.1
-
Made the following changes:
-
• Changed the descriptions for tx_serial_clk_1g and rx_cdr_
refclk_1g.
• Added bit 12 to the 0x4B0 word address.
Table 11-2: 10GBASE-KR IP Core Register Definition Changes v15.1
Register definitions added or modified in version 15.1 for word address 0x4B0.
Bit
12
RW
Old Register Name
New Register Name
RW
N/A
LT failure response
Description
When set to 1, LT failure causes the
PHY to go into data mode. When
set to 0, LT failure restarts autonegotiation (if enabled). If autonegotiation is not enabled, the PHY
will restart LT.
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for 10GBASE-R PHY in the Knowledge Base
• Introduction to Altera IP Cores
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0.1 Revision History
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0.1 Revision History
Table 11-3: v15.0.1 June 2015
Description
Impact
Verified in Quartus II software v15.0.1
-
Made the following improvements to the link training (LT) algorithm:
-
• Support for manual VGA tuning
• Added option to skip link partner VOD (main tap) adjustment
during LT
• Added option to enable decision feedback equalization (DFE) at the
end of LT
• General algorithm improvements for stability
Table 11-4: 10GBASE-KR IP Core Register Definition Changes v15.0.1
Register definitions added or modified in version 15.0.1 for word address 0x4D0.
Bit
RW
Old Register Name
New Register Name
Description
2
RW
quick_mode
Reserved
Reserved
3
RW
pass_one
Reserved
Reserved
18
RW
Ctle_depth
VOD Training Enable
Defines whether or not to skip
adjustment of the link partner’s
VOD (main tap) during link
training. The following values are
defined:
• 1 = Exercise VOD (main tap)
adjustment during link training
• 0 = Skip VOD (main tap)
adjustment during link training
The default value is 0.
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Bit
19
RW
Old Register Name
New Register Name
RW
Ctle_depth
Bypass DFE
11-3
Description
Defines whether or not Decision
Feedback Equalization (DFE) is
enabled at the end of link training.
The following values are defined:
• 1 = Bypass continuous adaptive
DFE at the end of link training
• 0 = Enable continuous adaptive
DFE at the end of link training
The default value for simulation is
1. The default value for hardware is
0.
21:20
RW
rx_ctle_mode
rx_ctle_vga_mode
Defines the point at which to
enable the RX CTLE in the
adaptation algorithm. The
following values are defined:
• 00 = never, the RX CTLE isn’t
enabled or adjusted
• 01 = trigger CTLE/VGA before
starting TX-EQ
• 10 = trigger CTLE/VGA after
finishing TX-EQ
• 11 = trigger CTLE/VGA, both
before starting, and after
finishing TX-EQ
The default value is 00.
Note: These bits are only
effective when
0x4D0[22] is set to 0.
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Revision History
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Bit
22
RW
Old Register Name
New Register Name
RW
Reserved
adp_ctle_vga_mode
Description
Defines whether or not CTLE/VGA
adaptation is in adaptive or manual
mode. The following values are
defined:
• 1 = Manual CTLE/VGA mode.
Link training algorithm sets
fixed CTLE and VGA values as
specified in bits 0x4D0[28:24]
and 0x4D0[31:29], respectively.
• 0 = adaptive CTLE mode. Bits
in 0x4D0[21:20] are effective
only when this bit is set to 0.
The default value is 1.
28:24
RW
Reserved
Manual CTLE
Defines the CTLE value used by the
link training algorithm when in
manual CTLE mode. These bits are
only effective when 0x4D0[22] is
set to 1.
The default value is 1.
31:29
RW
max_post_
step[2:0]
Manual VGA
Defines the VGA value used by the
link training algorithm when in
manual VGA mode. These bits are
only effective when 0x4D0[22] is
set to 1.
The default value is 4.
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for 10GBASE-R PHY in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0 Revision History
Table 11-5: v15.0 May 2015
Description
Impact
When adaptation is enabled, the 10GBASE-KR link training may not
finish in the required 500 ms. This results in a Link Training Failure.
When this occurs, equalization may not be trained optimally for the
link.
Altera Corporation
You can disable adaptation and
use a fixed CTLE value during
link training. This is done by
setting 0x4D0[22:20] to 4, and
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Revision History
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Description
11-5
Impact
0x4D0[28:24] to the desired
CTLE value.
The 10GBASE-KR register, 0x4d2[0] Link Trained – Receiver status, is read incorrectly as 0 when testing on HW. It will be read back correctly
during simulation.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for the Arria 10 1G/10GbE and 10GBASE-KR PHY MegaCore Function in the Knowledge
Base
• Introduction to Altera IP Cores
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.1 Revision History
Table 11-6: v14.1 December 2014
Description
Impact
Verified in Quartus II software v14.1
-
The Quartus II software v14.1 requires that you specify a device if your
IP core targets the Arria 10 device family. If you do not specify your
target Arria 10 device, the IP Upgrade tool insists that your IP core
requires upgrade but does not clarify the reason.
You must ensure that you
specify a device for your v13.1
Arria 10 Edition or v14.0 Arria
10 Edition IP core variation and
regenerate it in the Quartus II
software v14.1.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for the Arria 10 1G/10GbE and 10GBASE-KR PHY MegaCore Function in the Knowledge
Base
• Introduction to Altera IP Cores
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.0 Revision History
Table 11-7: v14.0 August 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Revision History
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-
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Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v13.1 Revision History
Description
Impact
Removed the following parameters from the Link Training tab:
-
• Enable daisy chain mode.
• Enable microprocessor interface.
Changed the default values of the following PMA parameters under the Link Training tab:
•
•
•
•
•
•
•
•
•
VMAXRULE
VMINRULE
VODMINRULE
VPOSTRULE
VPRERULE
PREMAINVAL
INITMAINVAL
INITPOSTVAL
INITPREVAL
Changed Avalon Memory-Mapped (AVMM) clock frequency from
125 MHz to 161 MHz to support NIOS II. The AVMM slave interface
provides access to the IP core registers.
-
IEEE 1588 Precision Time Protocols are not supported in backplane
applications.
-
Link Training takes more time in simulation as NIOS command
processing is slower.
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for the Arria 10 1G/10GbE and 10GBASE-KR PHY MegaCore Function in the Knowledge
Base
• Introduction to Altera IP Cores
Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v13.1 Revision History
Table 11-8: v13.1 December 2013
Description
Initial release
Impact
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for the Arria 10 1G/10GbE and 10GBASE-KR PHY MegaCore Function in the Knowledge
Base
• Introduction to Altera IP Cores
Altera Corporation
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History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
Arria 10 External Memory Interface IP 15.1
Table 12-1: v15.1 November 2015
Description
Several new features are added in v15.1:
Impact
-
•
•
•
•
Arria 10 EMIF IP support for LPDDR3 external memory protocol.
EMIF Configurable Traffic Generator 2.0 for Arria 10 EMIF IP.
Abstract PHY support for faster simulation.
New example design presets that map directly to Arria 10 device
kits.
• Ping Pong PHY now exposes two user clocks.
• EMIF Debug Toolkit includes several new features: 2D eye diagram
for DDR4 and QDR-IV, improved C-based API for On-Chip Debug
Toolkit, automated memory ODT sweep, driver margining.
Related Information
• External Memory Interface Handbook
• Errata for Arria 10 External Memory Interface IP in the Knowledge Base
Arria 10 External Memory Interface IP 15.0
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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9001:2008
Registered
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Arria 10 External Memory Interface IP 14.1
Table 12-2: v15.0 May 2015
Description
Impact
Verified in the Quartus II software v15.0
-
Related Information
• External Memory Interface Handbook
• Errata for Arria 10 External Memory Interface IP in the Knowledge Base
Arria 10 External Memory Interface IP 14.1
Table 12-3: v14.1 December 2014
Description
Impact
Several new features are added in v14.1:
-
•
•
•
•
Support for the QDR-IV memory protocol.
Ping Pong PHY support for DDR3 and DDR4.
Compact pin placement for x4 groups for DDR3 and DDR4.
Simulation, compilation, and timing closure support for DDR4
RDIMMs.
• Compilation and timing closure support for DDR3 RDIMMs, and
LRDIMMs, and DDR4 LRDIMMs.
• Half-rate controller and PHY support for quarter-rate DDR3 and
DDR4 interfaces.
DDR3 and DDR4 interfaces with x4 groups are now generated with
two DQS groups per I/O lane. In previous releases, interfaces with x4
groups required one I/O lane per DQS group, causing inefficient I/O
pin usage.
v14.1 allows more compact pin
placement.
(For devices with a name prefixed with 10AX090, 10AX115, 10AT090,
or 10AT115, x4 support is available only for ES2 and newer silicon
revisions. For other devices, x4 support is available for all silicon
revisions including ES.)
For quarter-rate DDR3 and DDR4 interfaces using hard memory
controller, the hard memory controller and the PHY can now run at
half-rate (that is, at 2x the frequency of user clock domain). This
feature is enabled automatically for interfaces and FPGA devices that
can support it. In previous releases, the hard memory controller and
the PHY always ran at quarter-rate for quarter-rate interfaces.
Running at half-rate allows
better efficiency and improved
latency.
In PHY-only mode for multi-rank interfaces, new signals afi_rrank
and afi_wrank have been introduced for shadow register selection.
Shadow registers now are
supported for Arria 10.
DDR4 3DS / ChipID is not supported by Arria 10. The option to use it
has been removed.
Option is no longer available.
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12-3
Related Information
External Memory Interface Handbook
Arria 10 External Memory Interface IP 14.0 Arria 10 Edition
Table 12-4: v14.0 Arria 10 Edition August 2014
Description
Impact
Added support for QDR II/II+/II+ Xtreme and RLDRAM 3.
-
Added I/O and Diagnostics Settings tab to the parameter editor for
DDR3 and DDR4.
-
Added optional signal mem_alert_n , which is enabled by default for
DDR4. This port is used to enable address and command deskew for
calibration.
-
Added support for PHY-only mode for DDR3 and DDR4.
-
Added error correction code (ECC) and memory-mapped configura‐
tion and status register (MMR) support for DDR3 and DDR4.
-
Related Information
External Memory Interface Handbook
Arria 10 External Memory Interface IP 13.0 Arria 10 Edition
Table 12-5: v13.0 Arria 10 Edition December 2013
Description
Initial release.
Impact
-
Related Information
External Memory Interface Handbook
Arria 10 External Memory Interface IP Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
Arria 10 FPLL IP Core Revision History v15.1 Revision History
Table 13-1: v15.1 Novembver 2015
Description
Changed the "Enable cascade clock input port" parameter name to
"Enable ATX to FPLL cascade clock input port."
Impact
—
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
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Registered
13-2
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Arria 10 FPLL IP Core Revision History v15.0 Revision History
Description
Issue: ACDS 15.1 introduces a necessary fix for Arria 10 transceiver
designs. This fix introduces a change that affects post-fit simulation for
designs containing Arria 10 Transceiver Native PHY, Arria 10
Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Arria 10
fPLL IP cores.
pll_powerdown is not connected for HSSI PLL IPs.
Workaround: Users requiring post-fit simulation of the transceiver
PLLs in ACDS 15.1 need to disable the "Transceiver Reset Sequencer"
for their design to produce a post-fit simulation netlist. However, this
cannot and should not be used to produce the final bitstream for
hardware. Hardware requires the "Transceiver Reset Sequencer" to be
enabled.
Impact
pll_powerdown inputs to the
Arria 10 Transceiver ATX PLL,
Arria 10 Transceiver CMU PLL,
and Arria 10 fPLL IP cores for
Quartus Prime synthesis. As a
result, the resulting generated
post-fit simulation will not have
a reset input connection for the
PLL and post-fit simulation will
likely fail.
To disable the "Transceiver Reset Sequencer" in the Quartus Prime
software, add the following QSF to the Quartus Settings File for the
project:
set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_
A10_ENABLE_ANALOG_RESETS=1"
This will completely disable the reset sequencer in the design and
restore the old behavior. This method does not allow post-fit
simulation of the "Transceiver Reset Sequencer" logic.
Resolution: A modification to the PLL simulation models is planned
for a subsequent release of ACDS 15.1 to remove the reset requirement.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 FPLL IP Core Revision History v15.0 Revision History
Table 13-2: v15.0 May 2015
Description
Impact
Changed the following GUI warning: Warning (10858): Verilog HDL warning at altera_xcvr_fpll_a10.sv(487): object pll_extfb_wire used but
never assigned.
This compile warning resulted from a dangling net left behind when
the CGB master was not generated (enabled). Tied off the pll_extfb_
wire signal when the CGB master is not generated to drive it.
Altera Corporation
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Description
13-3
Impact
Added an Advanced Parameters tab that displays the following values: •
•
•
•
C counters (0 to 3)
L, M and N counters
K fractional division
VCO frequency
Truncated the return vco frequency (MHz) to six digits after the
decimal point.
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 FPLL IP Core Revision History v14.1 Revision History
Table 13-3: v14.1 December 2014
Description
Changed the default FPLL Mode to Transceiver TX PLL.
Impact
-
FPLL does not allow the bandwidth setting of "high" in fractional
mode.
The Quartus II software v14.1 requires that you specify a device if your
IP core targets the Arria 10 device family. If you do not specify your
target Arria 10 device, the IP Upgrade tool insists that your IP core
requires upgrade but does not clarify the reason.
You must ensure that you
specify a device for your v13.1
Arria 10 Edition or v14.0 Arria
10 Edition IP core variation and
regenerate it in the Quartus II
software v14.1.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 FPLL IP Core Revision History v14.0 Revision History
Arria 10 FPLL IP Core Revision History
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Table 13-4: v14.0 Arria 10 Edition August 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Added support for Embedded debug feature. This feature enables you
to write to the PLL control registers and read from status registers for
the PLL instances in the design. This feature is available under the
Dynamic Reconfiguration tab.
-
Changed the FPLL Parameter Editor graphic user interface (GUI) to
show the available FPLL modes. You can use the FPLL in the following
three modes:
• Core
• Cascade Source
• Transceiver
Removed the option for automatic bandwidth setting. The following
bandwidth settings are available:
-
• Low
• Medium
• High
Enhanced user warnings and information messages.
-
The fPLL IP in 13.1 Arria 10 edition, allowed simultaneous selection of FPLL to be used in core and transceiver PLL modes. However, in the
FPLL IP in 14.0 Arria 10 edition, only one mode (transceiver PLL or
core PLL) can be selected at a time. If you have selected both
(transceiver PLL and core PLL) modes in 13.1 Arria 10 edition, then
FPLL IP will fail automatic upgrade for 14.0 Arria 10 edition. In this
case, you will have to manually upgrade the FPLL IP after selecting one
legal FPLL usage mode.
The Master Clock Generation Block tab in IP Parameter Editor is not
visible when "Core" is selected as the FPLL mode. The Master Clock
Generation Block tab appears only when "Transceiver" is selected as
the FPLL mode.
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Altera Corporation
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13-5
Arria 10 FPLL IP Core Revision History v13.1 Revision History
Table 13-5: v13.1 Arria 10 Edition
Description
Initial release for Arria 10 devices.
Impact
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 FPLL IP Core Revision History
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Arria 10 Hard IP for PCI Express IP Core v15.1
Table 14-1: 15.1 November 2015
Description
Impact
Added Example Designs tab that automatically generates both
simulation and hardware example designs with the parameters you
specify.
You can now download an
example design to the Altera
Arria 10 GX FPGA Development
Kit using only the automatically
generated files.
Revised the component GUI. For example, is a new single parameter,
HIP mode combines all supported data rates, interface widths and
frequencies as a single parameter.
Improves useability of the
component GUI.
Added support for optional Avalon-ST clr_st reset output port which This signal eliminates Avalon
has the same functionality as the reset_status in the hip_rst
Streaming reset warnings.
conduit interface.
Increased the number of tags supported to 256 from 64 for the Avalon- Enhances DMA throughput for
MM with DMA interface.
high latency systems.
Added support for RX Completion buffer overflow monitoring.
Improves system visibility,
resulting in better optimization
of RX buffer.
Added preliminary support for Gen3 x4, Gen3 x8, and Gen2 x8 Root
Port when you select the 256-bit Avalon-MM interface.
Extends Avalon-MM Root Port
support to include 64-, 128-, and
256-bit interfaces.
Replaced the SR-IOV DMA example design with a target example
design that includes 1 physical function and 3 virtual functions.
This design provides a simpler
introduction to the SR-IOV
functionality.
Added support for immediate writes when you select the Avalon-MM
with DMA interface.
Provides an efficient mechanism
for writing a single dword of
data.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
14-2
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Arria 10 Hard IP for PCI Express IP Core v15.1
Table 14-2: Arria 10 HIP for PCI Express Signal Changes v15.0
Signals added or modified in version 15.0.
Signal Name
New Behavior
derr_cor_ext_rcv
derr_cor_ext_rpl
derr_rpl
dlup
dlup_exit
ev128ns
ev1us
hotrst_exit
int_status[3:0]
l2_exit
The presence or absence of these signals is now controlled by the new
Enable Hard IP Status Bus when using the AVMM interface parameter.
If the parameter is turned on, the signals are included. If the parameter is
turned off, the signals are not available.
lane_act[3:0]
ltssmstate[4:0]
rx_par_err
tx_par_err[1:0]
cfg_par_err
ko_cpl_spc_header[7:0]
ko_cpl_spc_data[11:0]
currentspeed[1:0]
Related Information
•
•
•
•
Altera Corporation
Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped DMA Interface
Errata for the Arria 10 Hard IP for PCI Express MegaCore Function in the Knowledge Base
Arria 10 Hard IP for PCI Express IP Core Revision History
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14-3
Arria 10 Hard IP for PCI Express IP Core v15.0
Table 14-3: 15.0 May 2015
Description
Impact
Added Enable Altera Debug Master Endpoint (ADME) parameter to
support optional Native PHY register programming with the Altera
System Console.
If you turn on this option, you
can use the Altera System
Console for enhanced
debugging.
In IP core variations with the Avalon-MM DMA interface, added
support for downstream burst read request for a payload of size up to 4
KBytes, if Enable burst capability for RXM BAR2 port is turned on in
the Parameter Editor. Previous maximum downstream read request
payload size was 512 bytes.
If you choose the Avalon-MM
DMA interface, the IP core can
receive and process a burst read
request for a payload of any size
supported by the PCI Express
specification (up to 4 KBytes), if
it receives such a burst read
request on the PCI Express link.
In IP core variations with the Avalon-MM interface, added support to
send message TLPs with data payload of any length from a Root Port.
If you choose the Avalon-MM
interface, a Root Port IP core can
send messages with payload
greater than 1 dword.
In IP core variations with the Avalon-MM interface, added support for
dynamically generated Qsys example designs that reflect the
parameters that you selected in the Parameter Editor. This feature was
new in the IP core v14.1 with the Avalon-ST interface, and is now
provided also with the Avalon-MM interface.
If you choose the Avalon-MM
interface and click the Example
Design button, the Quartus II
software generates an example
design that matches the current
parameter settings, for most IP
core variations,
In IP core variations with the Avalon-MM or Avalon-MM DMA
interface, added Enable Hard IP Status Bus when using the AVMM
interface parameter. This parameter makes visible or hides the link
status signals, ECC error signals, TX and RX parity error signals,
completion header and data signals, and currentspeed signal.
Refer to the Arria 10 HIP for PCI
Express Signal Changes v15.0
table.
The IP core no longer generates with a Synopsys Design Constraints
file (.sdc) that includes a derive_pll_clocks constraint. Instead, in
compliance with Arria 10 design requirements, the user must add the
timing constraint macro derive_pll_clocks -create_base_clocks
to a top-level .sdc file.
User must add this constraint in
a top-level Synopsys Design
Constraints file. This constraint
was previously included in the IP
core SDC file.
Arria 10 Hard IP for PCI Express IP Core Revision History
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Arria 10 Hard IP for PCI Express IP Core v14.1
Table 14-4: Arria 10 HIP for PCI Express Signal Changes v15.0
Signals added or modified in version 15.0.
Signal Name
New Behavior
derr_cor_ext_rcv
derr_cor_ext_rpl
derr_rpl
dlup
dlup_exit
ev128ns
ev1us
hotrst_exit
The presence or absence of these signals is now controlled by the new
Enable Hard IP Status Bus when using the AVMM interface parameter.
If the parameter is turned on, the signals are included. If the parameter is
turned off, the signals are not available.
int_status[3:0]
l2_exit
lane_act[3:0]
ltssmstate[4:0]
rx_par_err
tx_par_err[1:0]
cfg_par_err
ko_cpl_spc_header[7:0]
ko_cpl_spc_data[11:0]
currentspeed[1:0]
Related Information
•
•
•
•
Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped DMA Interface
Errata for the Arria 10 Hard IP for PCI Express MegaCore Function in the Knowledge Base
Arria 10 Hard IP for PCI Express IP Core v14.1
Table 14-5: 14.1 December 2014
Description
Reduced Quartus II compilation warnings by 50%.
Altera Corporation
Impact
Reduces time required to vet
compilation warnings.
Arria 10 Hard IP for PCI Express IP Core Revision History
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Arria 10 Hard IP for PCI Express IP Core v14.0 Arria 10 Edition
Description
14-5
Impact
Added support for Single-Root I/O Virtualization (SR-IOV) interface.
If you choose to use the SR-IOV
interface, you will need to
redesign your Application Layer.
Added support for dynamically generated Qsys example designs that
reflects the parameters that you selected in the Parameter Editor.
If you choose the Avalon-ST
interface, the automatically
generated testbench has the
parameters that you specified.
Added support for Configuration Space Bypass Mode when using the
Avalon-ST interface.
If you choose to use Configura‐
tion Space Bypass Mode, you will
need to redesign your Applica‐
tion Layer.
Added Quartus II compilation support for the Avalon-MM with DMA You can now compile for the
interface.
Avalon-MM with DMA interface
and download the Programmer
Object File .pof to a development
board.
The Quartus II software v14.1 requires that you specify a device if your
IP core targets the Arria 10 device family. If you do not specify your
target Arria 10 device, the IP Upgrade tool insists that your IP core
requires upgrade but does not clarify the reason.
If you generate your IP core
outside a Quartus II project, you
must ensure that you specify a
device for your Arria 10 IP core
variation and regenerate it in the
Quartus II software v14.1.
Related Information
•
•
•
•
Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped DMA Interface
Errata for the Arria 10 Hard IP for PCI Express MegaCore Function in the Knowledge Base
Arria 10 Hard IP for PCI Express IP Core v14.0 Arria 10 Edition
Table 14-6: v14.0 Arria 10 Edition August 2014
Description
Impact
Changed the PIPE interface to 32 bits for all data rates.
Added simulation log file, altpcie_monitor_<dev>_dlhip_tlp_file_log.log in This change requires you to
your simulation directory. Generation of the log file requires the
recompile your v13.1 variant in
following simulation file, <install_dir>altera/altera_pcie/altera_pcie_a10_ 14.0a10 release
hip/altpcie_monitor_a10_dlhip_sim.sv, that was not present in earlier
releases of the Quartus II software.
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Description
Impact
Added option to enable 62.5 MHz application clock for Gen1 x1 data
rate.
Added third interface option, Avalon-MM with DMA, that includes a
high performance DMA. If you choose this option, you must
regenerate your IP core.
Added option to integrate the Descriptor Controller in the variant for
the Avalon-MM with DMA interface.
If you choose this option, you
must regenerate your IP core.
-
Related Information
•
•
•
•
Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped DMA Interface
Errata for the Arria 10 Hard IP for PCI Express MegaCore Function in the Knowledge Base
Arria 10 Hard IP for PCI Express IP Core v13.1 Arria 10 Edition
Table 14-7: v13.1 Arria 10 Edition December 2013
Description
Initial release.
Impact
-
Related Information
•
•
•
•
Altera Corporation
Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface
Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped DMA Interface
Errata for the Arria 10 Hard IP for PCI Express MegaCore Function in the Knowledge Base
Arria 10 Hard IP for PCI Express IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
Arria 10 Transceiver ATX PLL IP Core v15.1 Revision History
Table 15-1: v15.1 November 2015
Description
The ATX PLL IP core only supports integer mode. It does not support
fractional mode (unless in cascade mode).
Impact
—
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
15-2
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Arria 10 Transceiver ATX PLL IP Core v15.0 Revision History
Description
Impact
Issue: ACDS 15.1 introduces a necessary fix for Arria 10 transceiver
designs. This fix introduces a change that affects post-fit simulation for
designs containing Arria 10 Transceiver Native PHY, Arria 10
Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Arria 10
fPLL IP cores.
pll_powerdown is not connected for HSSI PLL IPs.
Workaround: Users requiring post-fit simulation of the transceiver
PLLs in ACDS 15.1 need to disable the "Transceiver Reset Sequencer"
for their design to produce a post-fit simulation netlist. However, this
cannot and should not be used to produce the final bitstream for
hardware. Hardware requires the "Transceiver Reset Sequencer" to be
enabled.
pll_powerdown inputs to the
Arria 10 Transceiver ATX PLL,
Arria 10 Transceiver CMU PLL,
and Arria 10 fPLL IP cores for
Quartus Prime synthesis. As a
result, the resulting generated
post-fit simulation will not have
a reset input connection for the
PLL and post-fit simulation will
likely fail.
To disable the "Transceiver Reset Sequencer" in the Quartus Prime
software, add the following QSF to the Quartus Settings File for the
project:
set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_
A10_ENABLE_ANALOG_RESETS=1"
This will completely disable the reset sequencer in the design and
restore the old behavior. This method does not allow post-fit
simulation of the "Transceiver Reset Sequencer" logic.
Resolution: A modification to the PLL simulation models is planned
for a subsequent release of ACDS 15.1 to remove the reset requirement.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver ATX PLL IP Core v15.0 Revision History
Table 15-2: v15.0 May 2015
Description
Impact
Added an Advanced Parameters tab that displays the following values: •
•
•
•
C counters (0 to 3)
L, M and N counters
K fractional division
VCO frequency
Related Information
• Arria 10 Transceiver PHY User Guide
Altera Corporation
Arria 10 Transceiver ATX PLL IP Core Revision History
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Arria 10 Transceiver ATX PLL IP Core v14.1 Revision History
15-3
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver ATX PLL IP Core v14.1 Revision History
Table 15-3: v14.1 December 2014
Description
Impact
Verified in Quartus II software v14.1.
-
The Quartus II software v14.1 requires that you specify a device if your
IP core targets the Arria 10 device family. If you do not specify your
target Arria 10 device, the IP Upgrade tool insists that your IP core
requires upgrade but does not clarify the reason.
You must ensure that you
specify a device for your v13.1
Arria 10 Edition or v14.0 Arria
10 Edition IP core variation and
regenerate it in the Quartus II
software v14.1.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver ATX PLL IP Core v14.0 Revision History
Table 15-4: v14.0 Arria 10 Edition August 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Impact
-
Added support for fractional mode. Fractional mode provides support for a wider range of output frequencies than integer mode. This feature
is available under the Output Frequency tab.
Added support for Embedded Debug feature. This feature enables you
to write to the PLL control registers and read from status registers for
the PLL instances in the design. This feature is available under the
Dynamic Reconfiguration tab.
-
Added the following presets for GT and GX modes:
-
•
•
•
•
GT 25781.25 Mbps Single Channel
GX 2500 Mbps Bonded
GX 2500 Mbps Single Channel
GX 2500 Mbps xN Non-Bonded
Arria 10 Transceiver ATX PLL IP Core Revision History
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Arria 10 Transceiver ATX PLL IP Core v13.1 Revision History
Description
Impact
Changed the documentation link in IP Parameter Editor to refer to the Arria 10 Transceiver PHY User Guide.
Enhanced user warnings and information messages.
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver ATX PLL IP Core v13.1 Revision History
Table 15-5: v13.1 Arria 10 Edition December 2014
Description
Impact
Initial release for Arria 10 devices.
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Altera Corporation
Arria 10 Transceiver ATX PLL IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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Arria 10 Transceiver CMU PLL IP Core v15.1 Revision History
Arria 10 Transceiver CMU PLL IP Core v15.1 Revision History
Table 16-1: v15.1 November 2015
Description
Impact
Issue: ACDS 15.1 introduces a necessary fix for Arria 10 transceiver
designs. This fix introduces a change that affects post-fit simulation for
designs containing Arria 10 Transceiver Native PHY, Arria 10
Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Arria 10
fPLL IP cores.
pll_powerdown is not connected for HSSI PLL IPs.
Workaround: Users requiring post-fit simulation of the transceiver
PLLs in ACDS 15.1 need to disable the "Transceiver Reset Sequencer"
for their design to produce a post-fit simulation netlist. However, this
cannot and should not be used to produce the final bitstream for
hardware. Hardware requires the "Transceiver Reset Sequencer" to be
enabled.
pll_powerdown inputs to the
Arria 10 Transceiver ATX PLL,
Arria 10 Transceiver CMU PLL,
and Arria 10 fPLL IP cores for
Quartus Prime synthesis. As a
result, the resulting generated
post-fit simulation will not have
a reset input connection for the
PLL and post-fit simulation will
likely fail.
To disable the "Transceiver Reset Sequencer" in the Quartus Prime
software, add the following QSF to the Quartus Settings File for the
project:
set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_
A10_ENABLE_ANALOG_RESETS=1"
This will completely disable the reset sequencer in the design and
restore the old behavior. This method does not allow post-fit
simulation of the "Transceiver Reset Sequencer" logic.
Resolution: A modification to the PLL simulation models is planned
for a subsequent release of ACDS 15.1 to remove the reset requirement.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver CMU PLL IP Core v15.0 Revision History
Table 16-2: v15.0 May 2015
Description
Impact
Removed the hip_cal_done port to avoid a fitter failure. Previously,
this port was available when dynamic reconfiguration was enabled.
-
Related Information
• Arria 10 Transceiver PHY User Guide
Altera Corporation
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Arria 10 Transceiver CMU PLL IP Core v14.1 Revision History
16-3
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver CMU PLL IP Core v14.1 Revision History
Table 16-3: v14.1 December 2014
Description
Impact
Verified in the Quartus II software v14.1
-
The Quartus II software v14.1 requires that you specify a device if your
IP core targets the Arria 10 device family. If you do not specify your
target Arria 10 device, the IP Upgrade tool insists that your IP core
requires upgrade but does not clarify the reason.
You must ensure that you
specify a device for your v13.1
Arria 10 Edition or v14.0 Arria
10 Edition IP core variation and
regenerate it in the Quartus II
software v14.1.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver CMU PLL IP Core v14.0 Revision History
Table 16-4: v14.0 Arria 10 Edition August 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Added support for Embedded debug feature. This feature enables you
to write to the PLL control registers and read from status registers for
the PLL instances in the design. This feature is available under the
Dynamic Reconfiguration tab.
-
Added preset GX 2500 Mbps Single Channel for GX mode.
-
Changed the IP core to expose the pll_cal_busy port to the top level.
-
Changed the documentation link in IP Parameter Editor to refer to the Arria 10 Transceiver PHY User Guide.
Enhanced user warnings and information messages.
-
Related Information
• Arria 10 Transceiver PHY User Guide
Arria 10 Transceiver CMU PLL IP Core Revision History
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Arria 10 Transceiver CMU PLL IP Core v13.1 Revision History
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver CMU PLL IP Core v13.1 Revision History
Table 16-5: v13.1 Arria 10 Edition December 2014
Description
Impact
Initial release for Arria 10 devices.
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Altera Corporation
Arria 10 Transceiver CMU PLL IP Core Revision History
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Arria 10 Transceiver Native PHY IP Core
Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
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Registered
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Arria 10 Transceiver Native PHY IP Core v15.1 Revision History
Arria 10 Transceiver Native PHY IP Core v15.1 Revision History
Table 17-1: v15.1 November 2015
Description
Impact
Issue: ACDS 15.1 introduces a necessary fix for Arria 10 transceiver
designs. This fix introduces a change that affects post-fit simulation for
designs containing Arria 10 Transceiver Native PHY, Arria 10
Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Arria 10
fPLL IP cores.
pll_powerdown is not connected for HSSI PLL IPs.
Workaround: Users requiring post-fit simulation of the transceiver
PLLs in ACDS 15.1 need to disable the "Transceiver Reset Sequencer"
for their design to produce a post-fit simulation netlist. However, this
cannot and should not be used to produce the final bitstream for
hardware. Hardware requires the "Transceiver Reset Sequencer" to be
enabled.
pll_powerdown inputs to the
Arria 10 Transceiver ATX PLL,
Arria 10 Transceiver CMU PLL,
and Arria 10 fPLL IP cores for
Quartus Prime synthesis. As a
result, the resulting generated
post-fit simulation will not have
a reset input connection for the
PLL and post-fit simulation will
likely fail.
To disable the "Transceiver Reset Sequencer" in the Quartus Prime
software, add the following QSF to the Quartus Settings File for the
project:
set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_
A10_ENABLE_ANALOG_RESETS=1"
This will completely disable the reset sequencer in the design and
restore the old behavior. This method does not allow post-fit
simulation of the "Transceiver Reset Sequencer" logic.
Resolution: A modification to the PLL simulation models is planned
for a subsequent release of ACDS 15.1 to remove the reset requirement.
In Arria 10 devices, you may observe marginal core-to-periphery and
periphery-to-core setup and hold violations (range: 80 ps - 100 ps) in
transceiver based designs. You can ignore these violations in the 15.1
release.
These setup and hold violations
have no impact on hardware
designs.
The Arria 10 Transceiver Native PHY IP core adds logic that controls
and sequences the assertion and deassertion of the rx_analogreset
and tx_analogreset signals internal to the core. The logic that
performs this sequencing is inserted by the Quartus Prime software
during synthesis.
This change requires you to
make one of two changes to
your reset control logic that
drives the rx_analogreset, tx_
analogreset, and tx_digitalreset signals. Refer to the
Resetting Transceiver Channels
chapter of the Arria 10
Transceiver PHY User Guide for
details about the new reset
sequence requirements.
Altera Corporation
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Arria 10 Transceiver Native PHY IP Core v15.0 Revision History
Description
A new option in the Native PHY IP core called "Include PMA analog
settings in configuration files" allows you to select whether you want
analog settings and their dependent parameters to be part of your
configuration files (MIF, SV, or H) for dynamic reconfiguration. If you
select this option, a new tab opens up for you to select various analog
settings.
17-3
Impact
You must still use Quartus II
Settings File (.qsf) assignments
to specify the analog settings for
their current configuration in
the Quartus Prime software.
This new GUI option does not
remove the requirement to
specify .qsf assignments for their
analog settings. This option only
allows you to include analog
settings as part of the configura‐
tion files for reconfiguration.
Arria 10 Transceiver Native PHY IP Core v15.0 Revision History
Table 17-2: 15.0 May 2015
Description
Impact
Changed bit settings.
You must upgrade any IPs
generated prior to Quartus II
software v15.0.
Added the following warning message to the GUI: "Enable dynamic
reconfiguration should be enabled when Enable datapath and
interface reconfiguration is enabled".
-
This message appears when dynamic reconfiguration is disabled while
datapath reconfiguration is enabled.
Arria 10 Transceiver Native PHY IP Core Revision History
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Arria 10 Transceiver Native PHY IP Core v15.0 Revision History
Description
Impact
Updated tooltips and added information messages for the parameters
in the table below
-
Note: Information messages are displayed only if the parameter is
enabled.
Table 17-3: Tool Tip and Information Message Updates
Parameter
tx_pma_clkout
rx_pma_clkout
tx_pma_div_
clkout
rx_pma_div_
clkout
Altera Corporation
Tool Tip Update
Information Message
Enables the
The tx_pma_clkout port
optional tx_pma_ is not to be used to clock
clkout output
the data interface.
clock. This is the
parallel clock from
the TX PMA. This
port is not to be
used to clock the
data interface.
Enables the
optional rx_pma_
clkout output
clock. This is the
recovered parallel
clock from the RX
CDR. This port is
not to be used to
clock the data
interface.
The rx_pma_clkout port
is not to be used to clock
the data interface.
Enables the
optional tx_pma_
div_clkout output
clock. This port
should not be used
for register mode
data transfers.
The tx_pma_div_clkout
port should not be used
for register mode data
transfers.
Enables the
optional rx_pma_
div_clkout output
clock. This port
should not be used
for register mode
data transfers.
The rx_pma_div_clkout
port should not be used
for register mode data
transfers.
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Arria 10 Transceiver Native PHY IP Core v15.0 Revision History
Description
Added the following information message to the GUI for tx_std_
bitslipboundarysel: "The tx_std_bitslipboundarysel port must
be enabled if Standard PCS TX bitslip capability is desired."
17-5
Impact
-
This message is displayed if TX bitslip is enabled and Std PCS is used.
Added warning messages for merging simplex IPs. The messages are
displayed conditionally. For example, when embedded debug is enabled
in a simplex design.
The following are example messages:
• If this TX Simplex Native PHY instance needs to be merged with an
RX Simplex Native PHY instance or a CDR PLL IP instance, ensure
that reconfiguration inputs of both the PHY instances are driven by
the same source.
• If this RX Simplex Native PHY instance needs to be merged with an
TX Simplex Native PHY instance, ensure that reconfiguration
inputs of both the PHY instances are driven by the same source.
• This TX Simplex Native PHY instance cannot be merged with an
RX Simplex Native PHY instance or a CDR PLL IP instance.
• This RX Simplex Native PHY instance cannot be merged with a TX
Simplex Native PHY instance.
Removed the triggered option from the DFE adaptation mode
parameter. If an IP core is generated before 15.0 with the triggered
option selected for DFE adaptation mode, automatic upgrade maps
triggered to continuous.
-
Also updated the tool tip for DFE adaptation mode accordingly.
Added options to enable/disable the tx_pma_iqtxrx_clkout and rx_
pma_iqtxrx_clkout ports. The ports are targeted for cascading the
RX/TX PMA output clocks to the input of a PLL.
-
Fixed the issue where the following parameter values were not setting
properly if using Riveria:
-
•
•
•
•
•
•
hssi_10g_tx_pcs_pseudo_seed_a
hssi_10g_tx_pcs_pseudo_seed_b
hssi_8g_rx_pcs_wa_pd_data
pma_tx_buf_xtx_path_pma_tx_divclk_hz
pma_rx_buf_xrx_path_pma_rx_divclk_hz
pma_tx_buf_xtx_path_tx_pll_clk_hz
Arria 10 Transceiver Native PHY IP Core Revision History
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Arria 10 Transceiver Native PHY IP Core v14.1 Revision History
Description
Impact
When generating configuration files for RX-only configurations, the
PHY incorrectly includes registers related to the TX CGB block.
When generating configuration files for TX-only configurations, the
PHY incorrectly includes registers related to the RX PMA adaptation
blocks.
The RX/TX configuration file
inadvertently contains configu‐
ration data for the complimen‐
tary simplex direction. This
causes an issue when a TX and
RX PHY are merged to the same
location because streaming the
configuration data to one side
affects the other.
Embedded streamer configura‐
tions are not affected as such
and are not permitted in simplex
configurations.
Arria 10 Transceiver Native PHY IP Core v14.1 Revision History
Table 17-4: 14.1 December 2014
Description
Impact
Added support for multiple silicon revisions supported for ACDS 14.1
version of the Quartus II software.
-
Added a new parameter for Interlaken protocol implementation called
Enable Interlaken TX random disparity bit. When enabled, a random
number is used as a disparity bit.
Changed the option "Manual (PLD controlled)" to "Manual (FPGA
fabric controlled)" for the RX word aligner mode parameter.
-
Changed the option "SATA" to "SATA/SAS" for PMA configuration
rules parameter.
-
Changed the descriptions of parameters CTLE adaptation mode and
DFE adaptation mode.
-
The Quartus II software v14.1 requires that you specify a device if your
IP core targets the Arria 10 device family. If you do not specify your
target Arria 10 device, the IP Upgrade tool insists that your IP core
requires upgrade but does not clarify the reason.
You must ensure that you
specify a device for your v13.1
Arria 10 Edition or v14.0 Arria
10 Edition IP core variation and
regenerate it in the Quartus II
software v14.1.
Altera Corporation
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Arria 10 Transceiver Native PHY IP Core v14.0 Revision History
17-7
Arria 10 Transceiver Native PHY IP Core v14.0 Revision History
Table 17-5: v14.0 Arria 10 Edition August 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Added support for PCS-Direct mode. The PCS-Direct mode enables
you to bypass all the internal PCS blocks.
-
Changed the maximum data rate supported by GT channels to 28300
Mbps.
-
Added support for Embedded debug feature. This feature enables you
to write to the PLL control registers and read from status registers for
the PLL instances in the design. This feature is available under the
Dynamic Reconfiguration tab.
-
Changed Enable embedded JTAG AVMM Master parameter to
Enable Altera Debug Master Endpoint parameter.
-
Added the following parameters:
-
• PMA Configuration Rules.
• Enable fast sync status reporting for deterministic latency SM
under the Word Aligner and Bitslip tab. Use this parameter for
implementing CPRI (Auto) protocol.
Added Faster Register mode for PCS TX and RX FIFO.
-
Changed the parameter Enable Reconfiguration between Standard
and Enhanced PCS to Enable Datapath and Interface Reconfigura‐
tion.
-
Changed the one-time option for CTLE and DFE adaptation mode to
Triggered mode.
-
Removed Enable tx_enh_fifo_cnt port and Enable rx_enh_fifo_cnt
port parameters from the IP Parameter Editor.
-
Removed the parameter Device Speed Gradeselection.
-
Removed 62.5, 125, 200, and 250 values for PPM detector threshold.
-
Enhanced user warnings and information messages.
-
Arria 10 Transceiver Native PHY IP Core Revision History
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Arria 10 Transceiver Native PHY IP Core v13.1 Revision History
Description
Impact
Added the following presets:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
-
3G SDI NTSC
3G SDI PAL
HD SDI NTSC
HD SDI PAL
Low Latency GT
SAS Gen1
SAS Gen1.1
SAS Gen2
SATA Gen1
SATA Gen2
SATA Gen3
SFI-S 64:64 4x11.3Gbps
SONET/SDH OC-12
SONET/SDH OC-48
SONET/SDH OC-96
Serial Rapid IO 1.25Gbps
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Arria 10 Transceiver Native PHY IP Core v13.1 Revision History
Table 17-6: v13.1 Arria 10 Edition
Description
Impact
Initial release for Arria 10 devices.
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Altera Corporation
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BCH IP Core v15.1
Table 18-1: v15.1 November 2015
Description
First release.
Impact
-
Related Information
• BCH IP Core User Guide
• Introduction to Altera IP Cores
• Errata for BCH IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
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CIC IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
CIC IP Core v15.0
Table 19-1: v15.0 May 2015
Description
Verified in the Quartus II software v15.0.
Impact
-
Related Information
• CIC MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for CIC IP core in the Knowledge Base
CIC IP Core v14.1
Table 19-2: v14.1 December 2014
Description
Added final support for Arria 10 devices
Impact
-
Related Information
• CIC MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for CIC IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
CPRI IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
CPRI IP Core v14.1
Table 20-1: Version 14.1 December 2014
Description
Impact
Notes
Impact
Notes
Verified in the Quartus II software v14.1.
Related Information
• CPRI MegaCore Function User Guide
• Errata for CPRI IP core in the Knowledge Base
CPRI IP Core v14.0
Table 20-2: Version 14.0 June 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction
to Altera IP Cores.
Renamed Include Vendor Specific Space (VSS) access through CPU
interface parameter to Include all control word access through CPU
interface to better explain the function of the parameter. The parameter
functionality remains as it was in the 13.1 and 13.0 releases.
Renamed Receiver buffer depth parameter to Receiver FIFO depth. The
parameter functionality remains as it was in the 13.1 and 13.0 releases.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
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CPRI IP Core v13.1
Related Information
• Introduction to Altera IP Cores
• CPRI MegaCore Function User Guide
• Errata for CPRI IP core in the Knowledge Base
CPRI IP Core v13.1
Table 20-3: Version 13.1 November 2013
Description
Impact
Notes
Removed support for HardCopy IV GX device family.
Improved the demonstration testbench.
Improved resource utilization.
Related Information
• CPRI MegaCore Function User Guide
• Errata for CPRI IP core in the Knowledge Base
CPRI IP Core v13.0
Table 20-4: Version 13.0 May 2013
Description
Impact
Notes
Added new parameter for user control of inclusion or exclusion of
software interface to full control words.
Added new parameter for user control of inclusion or exclusion of roundtrip delay calibration feature.
Reduced resource utilization in 28-nm devices.
Related Information
• CPRI MegaCore Function User Guide
• Errata for CPRI IP core in the Knowledge Base
Altera Corporation
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Cyclone V Hard IP for PCI Express IP Core
Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Cyclone V Hard IP for PCI Express IP Core v15.0
Table 21-1: v15.0 May 2015
Description
Impact
In IP core variations with the Avalon-MM DMA interface, added
support for downstream burst read request for a payload of size up to 4
KBytes, if Enable burst capability for RXM BAR2 port is turned on in
the Parameter Editor. Previous maximum downstream read request
payload size was 512 bytes.
If you choose the Avalon-MM
DMA interface, the IP core can
receive and process a burst read
request for a payload of any size
supported by the PCI Express
specification (up to 4 KBytes), if
it receives such a burst read
request on the PCI Express link.
In IP core variations with the Avalon-MM interface, added support to
send message TLPs with data payload of any length from a Root Port.
If you choose the Avalon-MM
interface, a Root Port IP core can
send messages with payload
greater than 1 dword.
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Cyclone V Avalon-ST Interface for PCIe Solutions User Guide
Cyclone V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Cyclone V Hard IP for PCI Express in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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Cyclone V Hard IP for PCI Express IP Core v14.1
Cyclone V Hard IP for PCI Express IP Core v14.1
Table 21-2: v14.1 December 2014
Description
Impact
Reduced Quartus II compilation warnings by 50%.
Reduces time required to vet
compilation warnings.
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Cyclone V Avalon-ST Interface for PCIe Solutions User Guide
Cyclone V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Cyclone V Hard IP for PCI Express in the Knowledge Base
Cyclone V Hard IP for PCI Express IP Core v14.0
Table 21-3: v14.0 June 2014
Description
Impact
Upgraded the Avalon-ST version to support the new IP Catalog. For
more information about the IP Catalog, refer to IP Catalog and
Parameter Editor in Introduction to Altera IP Cores.
-
Added support for new V-Series PCIe with Avalon-MM DMA
Interface IP Core.
-
Added the following features to the Cyclone V Avalon-MM Hard IP
for PCI Express IP core:
All of these new features are
optional. If you include either
the hard IP status bus or status
• Added access to selected Configuration Space registers and link
extension bus in you design, you
status registers through the optional Control Register Access (CRA)
must regenerate your design and
Avalon-MM slave port.
connect the new bus.
• Added optional hard IP status bus that includes signals necessary to
connect the Transceiver Reconfiguration Controller IP Core.
• Added optional hard IP status extension bus which includes signals
that are useful for debugging, including: link training, status, error,
and Configuration Space signals.
Related Information
•
•
•
•
•
Altera Corporation
Introduction to Altera IP Cores
Cyclone V Avalon-ST Interface for PCIe Solutions User Guide
Cyclone V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Cyclone V Hard IP for PCI Express in the Knowledge Base
Cyclone V Hard IP for PCI Express IP Core Revision History
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Cyclone V Hard IP for PCI Express IP Core v13.0 SP1
21-3
Cyclone V Hard IP for PCI Express IP Core v13.0 SP1
Table 21-4: v13.0 SP1 July 2013
Description
Verified in the Quartus II software v13.0 SP1.
Impact
-
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Cyclone V Avalon-ST Interface for PCIe Solutions User Guide
Cyclone V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Cyclone V Hard IP for PCI Express in the Knowledge Base
Cyclone V Hard IP for PCI Express IP Core Revision History
Send Feedback
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DDR2 and DDR3 SDRAM Controller with
UniPHY Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v15.1
Table 22-1: v15.1 November 2015
Description
Verified in the Quartus Prime software v15.1
Impact
-
Related Information
• External Memory Interface Handbook
• Errata for DDR3 SDRAM Controller with UniPHY IP core in the Knowledge Base
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v15.0
Table 22-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0
Impact
-
Related Information
• External Memory Interface Handbook
• Errata for DDR3 SDRAM Controller with UniPHY IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v14.1
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v14.1
Table 22-3: v14.1 December 2014
Description
Impact
Verified in the Quartus II software v14.1
-
Related Information
• External Memory Interface Handbook
• Errata for DDR3 SDRAM Controller with UniPHY IP core in the Knowledge Base
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v14.0
Table 22-4: v14.0 June 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Removed support for Cyclone III, Cyclone III LS, and Stratix III
devices
-
Related Information
• External Memory Interface Handbook
• Errata for DDR3 SDRAM Controller with UniPHY IP core in the Knowledge Base
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core v13.1
Table 22-5: v13.1 November 2013
Description
Impact
Verified in the Quartus II software v13.1
-
Removed support for HardCopy III and HardCopy IV devices
-
Related Information
• External Memory Interface Handbook
• Errata for DDR3 SDRAM Controller with UniPHY IP core in the Knowledge Base
Altera Corporation
DDR2 and DDR3 SDRAM Controller with UniPHY Revision History
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DisplayPort IP Core v15.1
Table 23-1: v15.1 November 2015
Description
The txN_vid_f pin is removed from the DisplayPort IP core. The IP
core handles the interface internally.
Updated multi-stream support:
• 1, 2, 3, or 4 streams for Arria 10 and Stratix V devices
• 1 or 2 streams for Arria V devices
Impact
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
Related Information
• Introduction to Altera IP Cores
• DisplayPort IP Core User Guide
• Errata for DisplayPort IP Core in the Knowledge Base
DisplayPort IP Core v15.0
Table 23-2: v15.0 May 2015
Description
Impact
Added preliminary support for Arria 10 devices.
Updated color support.
• RGB—18, 24, 30, 36, or 48 bpp
• YCbCr 4:4:4—24, 30, 36, or 48 bpp
• YCbCr 4:2:2—16, 20, 24, or 32 bpp
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
Added source-supported DPCD locations.
Added new bits for DPTX_TEST_80BIT_PATTERN bits.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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DisplayPort IP Core v15.0
Description
Impact
Removed the Link Quality Generation register bits and combined these
bits into the DPTX_TX_CONTROL register.
•
•
•
•
•
•
•
•
•
•
0000 = Normal video
0001 = Training pattern 1
0010 = Training pattern 2
0011 = Training pattern 3
0111 = Video idle pattern
1001 = D10.2 test pattern (same as training pattern 1)
1010 = Symbol error rate measurement pattern
1011 = PRBS7
1100 = 80-bit custom pattern
1101 = HBR2 compliance test pattern (CP2520 pattern 1)
Added new sink-supported DPCD location bits: TEST_REQUEST, TEST_
LINK_RATE, TEST_LANE_COUNT, PHY_TEST_PATTERN, and TEST_80BIT_
CUSTOM_PATTERN.
Added simulation testbench for Arria 10 devices.
Related Information
• Introduction to Altera IP Cores
• DisplayPort IP Core User Guide
• Errata for DisplayPort IP Core in the Knowledge Base
Altera Corporation
DisplayPort IP Core Revision History
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DisplayPort IP Core v14.1
23-3
DisplayPort IP Core v14.1
Table 23-3: v14.1 December 2014
Description
Impact
Added multi-stream support (MST, 1 to 4 source and sink streams).
You can access this feature using these parameters:
• Support MST
• Max stream count
Added support for 4Kp60 resolution.
Removed support for double reference clocks—162MHz and 270MHz
—for transceiver clocking.
Updated the design example with pixel clock recovery feature and
4Kp60 support.
Added new signals.
Added new source registers:
•
•
•
•
•
•
•
•
•
•
•
0×00a0 (DPTX_MST_CONTROL1)
0×00a2 (DPTX _MST_VCPTAB0)
0×00a3 (DPTX _MST_VCPTAB
0×00a3 (DPTX _MST_VCPTAB1)
0×00a4 (DPTX _MST_VCPTAB2)
0×00a5 (DPTX _MST_VCPTAB3)
0×00a6 (DPTX _MST_VCPTAB4)
0×00a7 (DPTX _MST_VCPTAB5)
0×00a8 (DPTX _MST_VCPTAB6)
0×00a9 (DPTX _MST_VCPTAB7)
0×00aa (DPTX _MST_TAVG_TS)
Added new sink registers:
•
•
•
•
•
•
•
•
•
•
•
•
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
0×0006 (DPRX_BER_CNTI0)
0×0007 (DPRX_BER_CNTI1)
0×00a0 (DPRX_MST_CONTROL1)
0×00a1 (DPRX_MST_STATUS1)
0×00a2 (DPRX _MST_VCPTAB0)
0×00a3 (DPRX _MST_VCPTAB1)
0×00a4 (DPRX _MST_VCPTAB2)
0×00a5 (DPRX _MST_VCPTAB3)
0×00a6 (DPRX _MST_VCPTAB4)
0×00a7 (DPRX _MST_VCPTAB5)
0×00a8 (DPRX _MST_VCPTAB6)
0×00a9 (DPRX _MST_VCPTAB7)
Changed
the value
of the following register bits:
DisplayPort
IP Core Revision
History
• Source register
Send Feedback
• 0×0000 - Bits RX_LINK_RATE
• 0×0001 - Bits RX_LINK_RATE
• 0×0002 - Bits RSTI3, RSTI2, RSTI1, RSTI0
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DisplayPort IP Core v14.1
Table 23-4: DisplayPort IP Core Signal Changes
Signals added or modified in version 14.1.
Old Signal Name
New Signal Name
Notes
—
clk_cal
Calibration clock for transceiver
management interface
—
tx_link_rate_8bits
—
rx_link_rate_8bits
Main link rate expressed in multiples of
270Mbps
—
txN_video_in (N=1,2,3)
—
txN_vid_clk (N=1,2,3)
—
txN_audio (N=1,2,3)
—
txN_audio_clk (N=1,2,3)
—
txN_ss (N=1,2,3)
—
txN_msa_conduit
(N=1,2,3)
—
rxN_video_out (N=1,2,3)
—
rxN_vid_clk (N=1,2,3)
—
rxN_audio (N=1,2,3)
—
rxN_ss (N=1,2,3)
—
rxN_msa_conduit
(N=1,2,3)
—
rxN_stream (N=1,2,3)
TX signals for Stream 1, 2 and 3
RX signals for Stream 1, 2 and 3
tx_xcvr_clkout
tx_ss_clk
—
rx_xcvr_clkout
rx_ss_clk
—
Related Information
• Introduction to Altera IP Cores
• DisplayPort IP Core User Guide
• Errata for DisplayPort IP Core in the Knowledge Base
Altera Corporation
DisplayPort IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
FIR II IP Core v15.1
Table 24-1: v15.1 November 2015
Description
Added reconfigurable FIR filters.
Impact
-
Related Information
• FIR II IP Core User Guide
• Introduction to Altera IP Cores
• Errata for FIR II IP core in the Knowledge Base
FIR II IP Core v15.0
Table 24-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0.
Impact
-
Related Information
• FIR II IP Core User Guide
• Introduction to Altera IP Cores
• Errata for FIR II IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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FIR II IP Core v14.1
FIR II IP Core v14.1
Table 24-3: v14.1 December 2014
Description
Added final support for Arria 10 and MAX 10 devices
Impact
-
Related Information
• FIR II IP Core User Guide
• Introduction to Altera IP Cores
• Errata for FIR II IP core in the Knowledge Base
Altera Corporation
FIR II IP Core Revision History
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FFT IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
FFT IP Core v15.1
Table 25-1: v15.1 November 2015
Description
Verified in the Quartus Prime software v15.1.
Impact
-
Related Information
• FFT MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for FFT IP core in the Knowledge Base
FFT IP Core v15.0
Table 25-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0.
Impact
-
Related Information
• FFT MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for FFT IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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FFT IP Core v14.1
FFT IP Core v14.1
Table 25-3: v14.1 December 2014
Description
Added hard-ffloating point option for Arria 10 devices.
Impact
-
Related Information
• FFT MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for FFT IP core in the Knowledge Base
Altera Corporation
FFT IP Core Revision History
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HDMI IP Core v15.1
Table 26-1: v15.1 November 2015
Description
Impact
Added the following new GUI parameters:
• HDMI source
• Support for 8-channel audio
• Support for deep color
• HDMI sink
•
•
•
•
•
Support for 8-channel audio
Support for deep color
Manufacturer OUI
Device ID String
Hardware Revision
Updated the following interface ports:
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
• HDMI source
• Added ctrl
• Removed gcp_Set_AVMute and gcp_Clear_AVMute
• HDMI sink
• Added ctrl, mode, in_5v_power, and in_hpd
• Removed gcp_Set_AVMute and gcp_Clear_AVMute
Related Information
• Introduction to Altera IP Cores
• Altera High-Definition Multimedia Interface User Guide
• Errata for HDMI IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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HDMI IP Core v15.0 Update 1
HDMI IP Core v15.0 Update 1
Table 26-2: v15.0 Update 1 June 2015
Description
Fixed the timing violation on the oversampling block in the Arria V
HDMI 2.0 design.
Impact
Upgrade if you are using the
Arria V HDMI 2.0 design.
Related Information
• Introduction to Altera IP Cores
• Altera High-Definition Multimedia Interface User Guide
• Errata for HDMI IP core in the Knowledge Base
HDMI IP Core v15.0
Table 26-3: v15.0 May 2015
Description
Impact
Upgraded support for HDMI specification compliance from version
1.4b to 2.0.
Added 4 symbols per clock.
Added Status and Control Data Channel (SCDC) for HDMI specifica‐
tion version 2.0.
Added the following interface ports:
• HDMI source
• TMDS_Bit_clock_Ratio
• Scrambler_Enable
• HDMI sink
• TMDS_Bit_clock_Ratio
• Avalon-MM SCDC Management
•
•
•
•
•
•
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
scdc_i2c_clk
scdc_i2c_addr[7:0]
scdc_i2c_r
scdc_i2c_rdata[31:0]
scdc_i2c_w
scdc_i2c_wdata[31:0]
Related Information
• Introduction to Altera IP Cores
• Altera High-Definition Multimedia Interface User Guide
Altera Corporation
HDMI IP Core Revision History
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HDMI IP Core v14.1
26-3
• Errata for HDMI IP core in the Knowledge Base
HDMI IP Core v14.1
Table 26-4: v14.1 December 2014
Description
Initial release.
Impact
-
Related Information
• Introduction to Altera IP Cores
• Altera High-Definition Multimedia Interface User Guide
• Errata for HDMI IP core in the Knowledge Base
HDMI IP Core Revision History
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High-speed Reed-Solomon IP Core Revision
History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
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High-speed Reed-Solomon IP Core v15.1
Table 27-1: v15.1 September 2015
Description
First release.
Impact
-
Related Information
• High-speed Reed-Solomon IP Core User Guide
• Introduction to Altera IP Cores
• Errata for High-speed Reed-Solomon IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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Hybrid Memory Cube Controller IP Core
Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
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Hybrid Memory Cube Controller IP Core v15.1
Table 28-1: Version 15.1 November 2015
Description
Enhanced ADME feature. When you turn on
the Enable Altera Debug Master Endpoint
(ADME) parameter the IP core enables an
additional Arria 10 Transceiver PHY IP core
feature. In the 15.0 release, turning on the
parameter turned on these Arria 10 PHY
features:
Impact
This feature does not affect the top-level
signals of the IP core.
• Enable capability registers
• Enable control and status registers
• Enable prbs soft accumulators
Notes
You must
upgrade to
the 15.1
version of the
IP core if you
use the
Quartus
Prime
software
v15.1.
In the 15.1 release, the parameter also turns on
this Arria 10 PHY feature:
• Enable odi acceleration logic
Related Information
• Hybrid Memory Cube Controller IP Core User Guide
• Errata for Hybrid Memory Cube Controller IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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Hybrid Memory Cube Controller IP Core v15.0
Hybrid Memory Cube Controller IP Core v15.0
Table 28-2: Version 15.0 May 2015
Description
Impact
Notes
Initial public release.
Related Information
• Hybrid Memory Cube Controller IP Core User Guide
• Errata for Hybrid Memory Cube Controller IP core in the Knowledge Base
Altera Corporation
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Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
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Interlaken PHY IP Core v14.1 Revision History
Table 29-1: v14.1 December 2014
Description
Verified in Quartus II software v14.1
Impact
-
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for Interlaken PHY IP Core in the Knowledge Base
• Introduction to Altera IP Cores
Interlaken PHY IP Core v14.0 Revision History
Table 29-2: v14.0 July 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Impact
-
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for Interlaken PHY IP Core in the Knowledge Base
• Introduction to Altera IP Cores
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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Interlaken PHY IP Core v13.1 Revision History
Table 29-3: v13.1 November 2013
Description
Verified in the Quartus II software v13.1
Impact
-
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for Interlaken PHY IP Core in the Knowledge Base
• Introduction to Altera IP Cores
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Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
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IP Compiler for PCI Express v14.1
Table 30-1: Version 14.1 December 2014
Description
Impact
Notes
Impact
Notes
Verified in the Quartus II software v14.1.
Related Information
• IP Compiler for PCI Express User Guide
• Errata for IP Compiler for PCI Express in the Knowledge Base
IP Compiler for PCI Express v14.0
Table 30-2: Version 14.0 June 2014
Description
Removed support for Cyclone III, Cyclone III LS, and
Stratix III device families.
If your IP core variation targets
one of these device families, and
you choose to upgrade it to
version 14.0, this change
requires that you revise your IP
core variation and regenerate it.
Upgraded to support the new IP Catalog. For more
information about the IP Catalog, refer to IP Catalog and
Parameter Editor in Introduction to Altera IP Cores.
Upgrading your IP core for this
change is optional.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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IP Compiler for PCI Express v13.1
Related Information
• Introduction to Altera IP Cores
• IP Compiler for PCI Express User Guide
• Errata for IP Compiler for PCI Express in the Knowledge Base
IP Compiler for PCI Express v13.1
Table 30-3: Version 13.1 November 2013
Description
Impact
Notes
Removed support for the Arria GX, Cyclone II, HardCopy If your IP core variation targets
II, HardCopy III, HardCopy IV, Stratix II, and Stratix II GX one of these device families, and
you choose to upgrade it to
device families.
version 14.0, this change
requires that you revise your IP
core variation and regenerate it.
Related Information
• Introduction to Altera IP Cores
• IP Compiler for PCI Express User Guide
• Errata for IP Compiler for PCI Express in the Knowledge Base
IP Compiler for PCI Express v13.0
Table 30-4: Version 13.0 May 2013
Description
Impact
Notes
Removed support for the SOPC Builder design flow.
Related Information
• Introduction to Altera IP Cores
• IP Compiler for PCI Express User Guide
• Errata for IP Compiler for PCI Express in the Knowledge Base
Altera Corporation
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
JESD204B IP Core v15.1
Table 31-1: v15.1 November 2015
Description
Impact
Added data rate support of up to 13.5 Gbps for Arria 10 and 7.5 Gbps
for Arria V GT/ST devices.
—
Added a new selection for PCS Option parameter—Enabled PMA
Direct.
—
Changed the default value for RX Phase Compensation FIFO empty
error enable (csr_pcfifo_empty_err_en) CSR to 0 (refer to the RX
register map).
Disables the interrupt when PC
FIFO empty condition occurs.
Added Example Designs tab in the parameter editor that automatically —
generates both simulation and hardware example designs with the
parameters you specify.
Added a new design example—Nios II Control. The Altera JESD204B
IP core now includes two design examples:
• RTL State Machine Control (supports Arria V, Cyclone V, Stratix
V, and Arria 10 devices only)
• Nios II Control (supports Arria 10 devices only)
The RTL State Machine Control
is a legacy design example and is
renamed in this release.
Related Information
• JESD204B IP Core User Guide
• Errata for JESD204B IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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JESD204B IP Core v15.0
JESD204B IP Core v15.0
Table 31-2: v15.0 May 2015
Description
Impact
Added support for Cyclone V FPGA device family (up to 5 Gbps).
–
Added new parameters:
–
•
•
•
•
•
Enable Capability Registers
Set user-defined IP identifier
Enable Control and Status Registers
Enable Prbs Soft Accumulators
Enable manual F configuration
Added new register bits to support error detection (refer to Table
31-3).
These new register bits are
available when you upgrade the
IP core to v15.0.
Table 31-3: New Register Bits
Register
Bit
csr_pll_locked_err
csr_pcfifo_full_err
tx_err (0x60)
csr_pcfifo_empty_err
csr_pll_locked_err_en
tx_err_enable
(0x64)
csr_pcfifo_full_err_en
csr_pcfifo_empty_err_en
Altera Corporation
Description
Detects and flags an error when one or more lanes
of PLL locked loses lock while the JESD204B link
is running.
Detects and flags an error when one or more lanes
of the Phase Compensation FIFO is unexpectedly
full while the JESD204B link is running.
Detects and flags an error when one or more lanes
of the Phase Compensation FIFO is unexpectedly
empty while the JESD204B link is running.
Enable interrupt for PLL lose lock error.
Enable interrupt for Phase Compensation FIFO
full error.
Enable interrupt for Phase Compensation FIFO
empty error.
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Register
Bit
csr_rx_locked_to_data_err
csr_pcfifo_full_err
rx_err0 (0x60)
csr_pcfifo_empty_err
csr_rx_locked_to_data_err_en
rx_err_enable
(0x74)
csr_pcfifo_full_err_en
csr_pcfifo_empty_err_en
rx_err_link_
reinit (0x78)
31-3
Description
Detects and flags an error when one or more lanes
is not locked to data while the JESD204B link is
running.
Detects and flags an error when one or more lanes
of the Phase Compensation FIFO is unexpectedly
full while the JESD204B link is running.
Detects and flags an error when when one or
more lanes of the Phase Compensation FIFO is
unexpectedly empty while the JESD204B link is
running.
Enable interrupt for RX not locked to data error.
Enable interrupt for Phase Compensation FIFO
full error.
Enable interrupt for Phase Compensation FIFO
empty error.
csr_rx_locked_to_data_err_
link_reinit
Enable link reinitialization for RX not locked to
data error.
csr_pcfifo_full_err_link_
reinit
Enable link reinitialization for Phase Compensa‐
tion FIFO full error.
csr_pcfifo_empty_err_link_
reinit
Enable link reinitialization for Phase Compensa‐
tion FIFO empty error.
Related Information
• JESD204B IP Core User Guide
• Errata for JESD204B IP core in the Knowledge Base
JESD204B IP Core v14.1
Table 31-4: 14.1 December 2014
Description
Revised the parameter name of Enable PLL/CDR Dynamic Reconfi‐
guration to Enable Transceiver Dynamic Reconfiguration.
Impact
–
Added a new parameter—Altera Debug Master Endpoint. Enable this This feature is available only for
feature to access the reconfiguration space of the Transceiver Native
Arria 10 device family.
PHY IP Core.
Added new register bits:
JESD204B IP Core Revision History
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The new register bits are
available when you upgrade the
IP core in your design to v14.1.
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JESD204B IP Core v14.1
Description
Impact
• TX core:
• Bit: csr_reinit_w_rxsyncn_rise in the dll_ctrl register
(offset 0x50).
• Description: This bit controls the Code Group Synchronization
(CGS) state exit behavior during link re-initialization.
• RX core:
• Bit: csr_syncn_delay in the syncn_sysref_ctrl register
(offset 0x54).
• Description: This bit extends the SYNC_N assertion (low state)
by delaying the deassertion.
Updated the test_ilas_loop bit behavior in the dll_ctrl register (offset Upgrade the IP core in your
0x50).
design to v14.1 to implement
this new behavior.
Changed the JESD204B Avalon-MM slave interface readLatency value
from 0 to 1.
Upgrade the IP core in your
design to v14.1 to implement
this new behavior.
If you upgrade your IP core in
your design, you have to
reconnect the IP core in your
design due to port change.
Changed the interface type of the jesd204_rx_int and jesd204_tx_
int signals from conduit to interrupt.
–
Changed signal type of pll_locked, tx_cal_busy, rx_cal_busy, and
rx_is_lockedtodata.
–
New simulation flow for the IP core design example testbench.
Regenerate the design example
Changed the link bring up sequence by powering up the JESD204B TX from the IP Parameter Editor to
link and JESD204B RX link independently.
obtain this change.
Changed the default value of the 8B/10B encoder to /K28.5/ control
word during reset assertion to resolve the CDR lock issue in the
receiver. This change only affects design that select Enabled Soft PCS
for the PCS Option parameter.
If you use Enabled Soft PCS for
the PCS Option parameter, you
must upgrade the IP core in your
design to v14.1.
Related Information
• JESD204B IP Core User Guide
• Errata for JESD204B IP core in the Knowledge Base
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31-5
JESD204B IP Core v14.0 Arria 10 Edition Update 1
Table 31-5: 14.0 Arria 10 Edition Update 1 September 2014
Description
An optional upgrade is available for the JESD204B IP core in this
release of the Altera Complete Design Suite. However, neither the IP
Components window in the Project Navigator nor the IP Upgrade
dialog box indicate that the upgrade is available.
For information on features included in this optional upgrade, refer to
the Altera Complete Design Suite Version 14.0 Arria 10 Edition
Update Release Notes.
Impact
To upgrade your IP core, use the
IP Parameter Editor for the
JESD204B IP core to regenerate
the core. Automatic upgrade is
not available.
Related Information
• JESD204B IP Core User Guide
• Errata for JESD204B IP core in the Knowledge Base
JESD204B IP Core v14.0 Arria 10 Edition
Table 31-6: 14.0 Arria 10 Edition August 2014
Description
Added support for Arria 10 devices.
JESD204B IP Core Revision History
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Impact
Upgrading your existing IP core
from a previous release of the
Quartus II software requires
migrating it to the Arria 10
device family. To migrate your
IP core to the Arria 10 device
family, you must regenerate the
IP core manually in the Quartus
II v14.0 Arria 10 Edition
software and reconnect it in your
design.
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JESD204B IP Core v14.0
Description
Impact
New pll_locked signal behavior:
• Changed the signal direction from output to input.
• Changed the signal width to follow the number of lanes selected
instead of fixed at 1 bit.
Added the following signals for JESD204B IP core variations that target
an Arria 10 device:
• tx_bonding_clocks signal on the transmitter path if you select
bonded for the Bonded Mode option
• tx_serial_clk0 signal on the transmitter path if you select nonbonded for the Bonded Mode option.
• reconfig_clk, reconfig_reset, reconfig_avmm_address,
reconfig_read, reconfig_readdata, reconfig_avmm_
waitrequest, reconfig_write, and reconfig_writedata if you
turn on Enable PLL/CDR Dynamic Reconfiguration.
If you upgrade your IP core to
the Quartus II software v14.0
Arria 10 Edition, this change
requires that you regenerate the
IP core manually and reconnect
it in your design.
Removed the following signals for JESD204B IP core variations that
target an Arria 10 device:
•
•
•
•
reconfig_to_xcvr
reconfig_from_xcvr
pll_ref_clk on the transmitter path
pll_powerdown on the transmitter path
Related Information
• JESD204B IP Core User Guide
• Errata for JESD204B IP core in the Knowledge Base
JESD204B IP Core v14.0
Table 31-7: 14.0 June 2014
Description
Initial release.
Impact
-
Related Information
• JESD204B IP Core User Guide
• Errata for JESD204B IP core in the Knowledge Base
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Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
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LDPC IP Core v15.1
Table 32-1: v15.1 September 2015
Description
Verified in the Quartus Prime software v15.1.
Impact
-
Related Information
• LDPC IP Core User Guide
• Introduction to Altera IP Cores
• Errata for LDPC IP core in the Knowledge Base
LDPC IP Core v15.0
Table 32-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0.
Impact
-
Related Information
• LDPC IP Core User Guide
• Introduction to Altera IP Cores
• Errata for LDPC IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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LDPC IP Core v14.1
LDPC IP Core v14.1
Table 32-3: v14.1 December 2014
Description
Initial release
Impact
-
Related Information
• LDPC IP Core User Guide
• Introduction to Altera IP Cores
• Errata for LDPC IP core in the Knowledge Base
Altera Corporation
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and PHY IP Core Revision History
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Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
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Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.1
Table 33-1: Version 15.1 November 2015
Arria 10 support for this IP core is available in the Altera MegaCore IP Library. Stratix V support is available only
through the Self-Service Licensing center.
Description
Impact
Notes
In Arria 10 variations. added new
parameters Enable Altera Debug
Master Endpoint and Enable ODI
acceleration logic.
Upgrading the IP core to incorporate These parameters expose
these features is optional. This
control of transceiver
change does not affect the top-level configuration features.
signals of the IP core.
Made comprehensive changes to 1588
PTP interfaces.
Upgrading the IP core to incorporate Refer to LL 40-100GbE IP
this feature is optional. In variations Core Signal Changes
that include the 1588 PTP support
v15.1 table.
feature, the interface changes modify
and add top-level output signals to
the IP core. Therefore, to utilize the
1588 PTP support feature after you
upgrade, you must reconnect the IP
core in your design.
Added new 1588 PTP parameters
Enable 96b Time of Day Format,
Enable 64b Time of Day Format, and
Timestamp fingerprint width.
Upgrading the IP core to incorporate
this feature is optional. These
parameters are available only if you
turn on the Enable 1588 PTP
parameter.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.1
Description
Impact
Removed TX_PTP_STATUS register.
Upgrading the IP core to incorporate
this feature is optional. If you
upgrade your IP core to the v15.1
version, you must be aware of this
change in variations that include the
1588 PTP support feature.
Added new 1588 PTP registers TX_
PTP_ASYM_DELAY, TX_PTP_PMA_
LATENCY, and RX_PTP_PMA_LATENCY.
Upgrading the IP core to incorporate
this feature is optional. If you
upgrade your IP core to the v15.1
version, you must be aware of these
changes in variations that include the
1588 PTP support feature.
Added dedicated Example Design tab
in parameter editor for Arria 10
variations.
Upgrading the IP core to incorporate
this feature is optional. If you
upgrade your IP core, you should use
the Example Design tab to generate
a testbench and design example that
work correctly with the upgraded IP
core.
Added hardware test you can run on
the hardware design example.
Upgrading the IP core and
regenerating the example design to
incorporate this feature is optional. If
you upgrade the IP core but do not
regenerate the example design, this
feature is not available.
Minor changes to LL 40GBASE-KR4
feature register default values.
If you upgrade your IP core to the
v15.1 version, you must be aware of
these changes in LL 40GBASE-KR4
variations.
Altera Corporation
Notes
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33-3
Table 33-2: LL 40-100GbE IP Core Signal Changes v15.1
All signal changes are associated with the PTP module. Signals added or modified in version 15.1 are due to a
comprehensive change in the 1588 PTP interface. All correspondences between old and new signal names are
approximate: many of the new signals indicate a combination of old signal values or incorporate information
previously available in the TX_PTP_STATUS register. Other signals are added for the new 64-bit timestamp option.
Notes specify the expected usage of the new signal. In most cases the output signals are in fact available in the
other processing modes and your design can use them in other processing modes. For full information about the
sets of mutually exclusive input signals, refer to the LL 40-100GbE IP core user guide.
Old Signal Name
New Signal Name
rx_time_of_day_
96b_data[95:0]
tod_rxmac_in[95:0]
rx_time_of_day_
64b_data[63:0]
tx_time_of_day_
96b_data[95:0]
tod_txmac_in[95:0]
tx_time_of_day_
64b_data[63:0]
rx_ingress_
timestamp_96b_
data[95:0]
rx_tod[95:0]
rx_ingress_
timestamp_64b_
data[63:0]
—
—
rx_ingress_
timestamp_96b_
valid
rx_ingress_
timestamp_64b_
valid
tx_egress_
timestamp_request_
valid
tx_in_ptp
tx_etstamp_ins_
ctrl_timestamp_
insert
Notes
RX PTP interface to TOD module: Two distinct
signals to support the Enable 96b Time of Day
Format and Enable 64b Time of Day Format
parameters.
TX PTP interface to TOD module: Two distinct
signals to support the Enable 96b Time of Day
Format and Enable 64b Time of Day Format
parameters.
RX PTP interface to TOD module: Two distinct
signals to support the Enable 96b Time of Day
Format and Enable 64b Time of Day Format
parameters.
RX PTP interface: Valid signal for rx_ingress_
timestamp_96b_data.
RX PTP interface: Valid signal for rx_ingress_
timestamp_64b_data.
Incorporates functionality of old tx_in_ptp
signal (tells the IP core the current incoming
packet on the TX client interface is a PTP packet)
and also tells the IP core to process this packet in
two-step processing mode.
Incorporates functionality of old tx_in_ptp
signal (tells the IP core the current incoming
packet on the TX client interface is a PTP packet)
and also tells the IP core to process this packet in
one-step processing insertion mode.
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Old Signal Name
New Signal Name
tx_etstamp_ins_
ctrl_residence_
time_update
tx_egress_
timestamp_96b_
data[95:0]
tod_tx_clk_st2[95:0]
tx_egress_
timestamp_64b_
data[63:0]
tx_egress_
timestamp_96b_
valid
ptp_pkt_out
tx_egress_
timestamp_64b_
valid
—
—
—
tx_in_ptp_overwrite[1:0]
—
—
tx_egress_
timestamp_request_
fingerprint
tx_egress_
timestamp_96b_
fingerprint
tx_egress_
timestamp_64b_
fingerprint
Altera Corporation
Incorporates functionality of old tx_in_ptp
signal (tells the IP core the current incoming
packet on the TX client interface is a PTP packet)
and also tells the IP core to process this packet in
tone-step processing correction mode.
TX PTP two-step processing: Two distinct
signals to support the Enable 96b Time of Day
Format and Enable 64b Time of Day Format
parameters.
TX PTP two-step processing: Two distinct
signals to support the Enable 96b Time of Day
Format and Enable 64b Time of Day Format
parameters.
TX PTP fingerprint: Fingerprint in.
TX PTP fingerprint: Fingerprint out (96-bit
timestamp interface).
TX PTP fingerprint: Fingerprint out (64-bit
timestamp interface).
—
tx_etstamp_ins_
ctrl_timestamp_
format
tx_etstamp_ins_
ctrl_residence_
time_calc_format
tx_etstamp_ins_
ctrl_offset_
timestamp[15:0]
tx_in_ptp_offset[15:0]
Notes
tx_etstamp_ins_
ctrl_offset_
correction_
field[15:0]
TX PTP one-step processing insertion mode:
timestamp format (96-bit or 64-bit).
TX PTP one-step processing correction mode:
latency format (96-bit or 64-bit).
TX PTP one-step processing insertion mode:
timestamp offset.
TX PTP one-step processing correction mode:
correction field offset. Also the location for two
bytes of inserted 96-bit timestamp (in insertion
mode).
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Old Signal Name
—
—
New Signal Name
tx_etstamp_ins_
ctrl_ingress_
timestamp_
96b[95:0]
tx_etstamp_ins_
ctrl_ingress_
timestamp_
64b[63:0]
tx_etstamp_ins_
ctrl_checksum_zero
tx_in_zero_tcp
tx_etstamp_ins_
ctrl_checksum_
correct
tx_etstamp_ins_
ctrl_offset_
checksum_
field[15:0]
tx_in_tcp_offset[15:0]
tx_etstamp_ins_
ctrl_offset_
checksum_
correction[15:0]
—
tx_egress_
asymmetry_update
33-5
Notes
TX PTP one-step processing: 96-bit entry
timestamp.
TX PTP one-step processing: 64-bit entry
timestamp.
TX PTP one-step processing: Set checksum to
the value of zero.
TX PTP one-step processing: Update the
checksum following the timestamp update.
TX PTP one-step processing, offset to zero the
checksum (required if you assert tx_etstamp_
ins_ctrl_checksum_zero).
TX PTP one-step processing, offset to update
(correct) the checksum (required if you assert
tx_etstamp_ins_ctrl_checksum_correct).
Tells the IP core to use the value in the new TX_
PTP_ASYM_DELAY register.
Related Information
• Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.0
Table 33-3: Version 15.0 May 2015
Arria 10 support for this IP core is available in the Altera MegaCore IP Library. Stratix V support is available only
through the Self-Service Licensing center.
Description
Impact
If you upgrade the LL 40-100GbE IP
core to the IP core v15.0, the example
design no longer functions correctly.
You must regenerate the example
design after you upgrade.
After you upgrade your IP core, you
must regenerate the example design.
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Description
Impact
Notes
Added optional Synchronous Ethernet
support for Arria 10 variations.
Turning on the new Enable SyncE
parameter adds a new RX recovered
clock output signal.
Upgrading the IP core to incorporate Refer to LL 40-100GbE IP
this feature is optional. This feature Core Signal Changes
does not affect the top-level signals
v15.0 table.
of the IP core unless you turn on the
Enable SyncE parameter. If you
upgrade, turn on this parameter, and
intend to implement a Synchronous
Ethernet system, you must reconnect
the IP core in your design.
Changed handling of received
malformed packets:
If you upgrade your IP core to the
v15.0 version, you must be aware of
this behavior change.
• The IP core asserts the l<n>_rx_
error[0] or rx_error[0] signal in
the case of an unexpected control
character that is not an Error
character.
• Both the LL 40GbE IP core and the
LL 100GbE IP core handle received
malformed packets the same way.
New output signals explain the control
frames that the IP core passes to the RX
client interface. The output flags
indicate whether the control frame is a
standard flow-control frame, a
priority-based flow-control frame, or a
non-flow control frame.
Upgrading the IP core to incorporate Refer to LL 40-100GbE IP
this feature is optional. This feature Core Signal Changes
adds top-level output signals to the
v15.0 table.
IP core. Therefore, to utilize this
feature after you upgrade, you must
reconnect the IP core in your design.
Priority-based flow control is now
available for both LL 40GbE IP core
variations and LL 100GbE IP core
variations. Previously it was available
only in LL 100GbE variations.
Upgrading the IP core to incorporate
this feature is optional. This feature
does not affect the top-level signals
of the IP core.
New output status flag indicates when
TX lanes are fully aligned and ready to
transmit data.
Upgrading the IP core to incorporate Refer to LL 40-100GbE IP
this feature is optional. This feature Core Signal Changes
adds top-level output signals to the
v15.0 table.
IP core. Therefore, to utilize this
feature after you upgrade, you must
reconnect the IP core in your design.
New option to direct the IP core to
insert an error in a transmitted
Ethernet frame.
Upgrading the IP core to incorporate Refer to LL 40-100GbE IP
this feature is optional. This feature Core Signal Changes
adds top-level input signals to the IP v15.0 table.
core. Therefore, if you upgrade, you
must reconnect the IP core in your
design.
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Description
Impact
The IP core now generates an example
project that you can configure on a
device, for most variations. The older
type of example projects, which you
cannot configure on a device, are also
generated.
33-7
Notes
Upgrading the IP core to incorporate
this feature is optional.
Minor changes to LL 40GBASE-KR4
feature parameters and registers:
If you upgrade your IP core to the
v15.0 version, you must be aware of
these changes, and set the parameter
• Changed default value of link
and access the register accordingly,
training INITPOSTVAL parameter
in LL 40GBASE-KR4 variations..
from 22 to 13.
• Changed rx_ctle_mode LL
40GBASE-KR4 register field. The IP
core uses only the two least signifi‐
cant bits of the 10GBASE-KR
register field.
Table 33-4: LL 40-100GbE IP Core Signal Changes v15.0
Signals added or modified in version 15.0.
Old Signal Name
—
—
New Signal Name
clk_rx_recover
New three-bit control frame type flag.
rx_status[2:0]
(custom client
interface)
—
tx_lanes_stable
—
l<n>_tx_error
—
Output RX recovered clock intended to drive the
input reference clock of another Ethernet
component in a Synchronous Ethernet design.
This signal is available if you turn on Enable
SyncE in the LL 40-100GbE parameter editor.
l<n>_rx_
status[2:0]
(Avalon-ST client
interface)
—
Notes
(Avalon-ST client
interface)
tx_error[1:0] or
tx_error[3:0]
New output status flag.
New TX error insertion signal. User logic asserts
a bit to direct the IP core to insert an error in the
corresponding frame on the Ethernet link.
(custom client
interface)
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Related Information
• Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1
Table 33-5: Version 14.1 December 2014
Arria 10 support for this IP core is available in the Altera MegaCore IP Library. Stratix V support is available only
through the Self-Service Licensing center.
Description
Impact
Notes
The Quartus II software v14.1 requires
that you specify a device if your IP core
targets the Arria 10 device family. If
you do not specify your target Arria 10
device, the IP Upgrade tool insists that
your IP core requires upgrade, but does
not clarify the reason.
You must ensure that you specify a
device for your v14.0 Arria 10
Edition IP core variation and
regenerate it in the Quartus II
software v14.1.
Added optional 40GBASE-KR4
support in LL 40GbE IP core
variations. Turning on the Enable KR4
parameter makes many additional
40GBASE-KR4 specific parameters
available. 40GBASE-KR4 variations
have many additional registers but no
additional signals.
Upgrading the IP core to incorporate
this feature is optional. This feature
does not affect the top-level signals
of the IP core.
All statistics increment vectors are now
available and functional whether or not
you include the relevant statistics
counters in your IP core variations.
Previously, the statistics increment
vectors were functional only in IP core
variations that included the relevant
statistics module.
Upgrading the IP core to incorporate
this feature is optional. This feature
does not affect the top-level signals
of the IP core.
Added option to move the TX MAC
PLL outside the IP core. Turning on
the Use external TX MAC PLL
parameter adds an input clock that
drives the clk_txmac internal clock.
This option adds no additional
registers or register fields.
Upgrading the IP core to incorporate Refer to LL 40-100GbE IP
this feature is optional. This feature Core Signal Changes
does not affect the top-level signals
table.
of the IP core unless you turn on the
Use external TX MAC PLL
parameter.
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Description
Added two new 64-bit statistics
counters RXOctets_OK at offset 0x960
and TXOctets_OK at offset 0x860 to
count the payload bytes (octets) in
received and transmitted frames with
no FCS errors, undersized, oversized,
or payload length errors. The two
registers each have two associated new
signals.
Impact
33-9
Notes
Upgrading the IP core to incorporate Refer to LL 40-100GbE IP
this feature is optional. If you
Core Signal Changes
upgrade the IP core to the v14.1
table.
version, this feature adds top-level
signals and therefore requires that
you reconnect the IP core in your
design.
Added new CFG_PLEN_CHECK register at If you upgrade your IP core to the
offset 0x50A to support bit[4] of the
v14.1 version and wish to use the
new six-bit RX error signal.
new length checking status flag, you
must ensure that user logic turns on
the enable bit in this new register. In
addition, the register supports a new
RX error status flag signal that
requires that you reconnect the IP
core in your design.
Changed handling of received
If you upgrade your IP core to the
malformed packet. If the IP core
v14.1 version, you must be aware of
detects an incoming unexpected
this behavior change.
control character, it generates an EOP
for the packet. Previously the IP core
did not terminate (generate an EOP
for) an incoming packet if it received
an unexpected control character. In
addition the IP core signals an error on
the new six-bit RX error status signal
when appropriate.
Newly generated IP cores do not have
top-level signals that interface to
modules that the IP core does not
include. This change applies to the TX
MAC input clock, link fault signals,
pause signals, and PTP signals.
Because of the backward
compatibility feature described in the
Notes column, if you upgrade your
IP core to the v14.1 version, this
feature has no effect on the top-level
signals and does not require any
additional actions. Note that this
feature applies only to IP core
variations that do not instantiate the
relevant module or modules.
Updated PTP module behavior and
modified parameter name. If you turn
on Enable 1588 PTP, the PTP module
has the following new features and
requirements:
Upgrading the IP core to incorporate
this feature is optional. If you
upgrade the IP core to the v14.1
version, and the PTP module is
included in your original IP core
variation, this feature adds top-level
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For backward compati‐
bility, if you upgrade an
IP core variation, link
fault signals, pause toplevel signals, and PTP
signals in the earlier
release of the IP core
variation remain available
in the 14.1 version after
upgrade.
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Description
Impact
Notes
• You must instantiate a time-of-day signals and therefore requires that
(TOD) module and connect it to the you reconnect the IP core in your
design.
IP core.
• Added new PTP signals to receive
the timestamps the TOD module
generates in the two clock domains.
Refer to LL 40-100GbE IP Core
Signal Changes table.
• Removed TX PTP module TOD
calculation registers at offsets 0xB06
through 0xB08. The TOD module
now provides the functionality the
registers supported in previous
versions of the IP core.
• Added support for resetting the
TCP checksum to zero of the
application does not recalculate it.
Added two new signals with which
the application communicates such
a request to the IP core. Refer to LL
40-100GbE IP Core Signal Changes
table.
Improved RX skew tolerance to 1900
bits for LL 40GbE IP core variations
and to 1000 bits for LL 100GbE IP core
variations. Altera LL 40-100GbE IP
cores exceed the IEEE 802.3-2012
Ethernet Standard Clause 82.2.12
requirements of 1856 bits skew
tolerance for 40GbE IP cores and 928
bits skew tolerance for 100GbE IP
cores.
Table 33-6: LL 40-100GbE IP Core Signal Changes
Signals added or modified in version 14.1.
Old Signal Name
—
Altera Corporation
New Signal Name
clk_txmac_in
Notes
Input clock to drive the clk_txmac internal
clock. This signal is available if you turn on Use
external TX MAC PLL in the LL 40-100GbE
parameter editor.
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Old Signal Name
l<n>_rx_error (1 bit)
—
—
—
—
—
—
—
—
—
—
—
New Signal Name
33-11
Notes
l<n>_rx_error[5:0]
(Avalon-ST client
interface)
New six-bit RX error status signal.
rx_error[5:0]
(custom client
interface)
unidirectional_en
link_fault_gen_
en
tx_inc_
octetsOK[15:0]
tx_inc_
octetsOK_valid
rx_inc_
octetsOK[15:0]
Signals that provide status from the LINK_
FAULT_CONFIG register.
Signals that provide per-frame information
associated with the new RxOctets_OK and
TXOctets_OK registers. These signals are present
and functional whether or not you turn on
Enable TX statistics or Enable RX statistics in
the parameter editor.
rx_inc_
octetsOK_valid
tx_in_zero_tcp
tx_in_tcp_
offset[15:0]
tod_txmac_in[95:0]
tod_rxmac_
in[95:0]
Signals for application to direct the IP core to
reset the TCP checksum field.
Signals to receive TOD values from new external
TOD module.
Link fault signals are present in new IP core variations you generate in the Quartus II v14.1 IP Catalog
only if you turn on Enable link fault generation in the parameter editor. For backward compatibility, the
signals remain if you upgrade from a pre-14.1 IP core variation that has those signals.
Pause signals are present in new IP core variations that you generate in the Quartus II v14.1 IP Catalog
only if you set Flow control mode to standard flow control or priority-based flow control in the
parameter editor. For backward compatibility, the signals remain if you upgrade from a pre-14.1 IP core
variation that has those signals.
PTP interface signals are present in new IP core variations that you generate in the Quartus II v14.1 IP
Catalog only if you turn on Enable 1588 PTP in the parameter editor. For backward compatibility, the
signals remain if you upgrade from a pre-14.1 IP core variation that has those signals.
Related Information
• Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
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Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Arria...
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Arria
10 Edition
Table 33-7: Version 14.0 Arria 10 Edition August 2014
Description
Impact
Notes
Initial release in the Altera MegaCore IP Library.
Related Information
• Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Errata for Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP core in the Knowledge Base
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Low Latency Ethernet 10G MAC IP Core v15.1
Table 34-1: v15.1 November 2015
Description
• Support for 1G/2.5 and 1G/2.5G/10G operating modes.
• Generation of the following design examples:
Impact
—
• 10GBase-R Register Mode
• 1G/10G Ethernet
• 1G/10G Ethernet with 1588
• 10M/100M/1G/10G Ethernet
• 10M/100M/1G/10G Ethernet with 1588
• Enhanced unidirectional feature to support user-triggered remote
fault notification through the register bit.
Related Information
• Introduction to Altera IP Cores
• Low Latency Ethernet 10G MAC MegaCore Function User Guide
• Errata for Low Latency Ethernet 10G MAC IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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Low Latency Ethernet 10G MAC IP Core v15.0
Low Latency Ethernet 10G MAC IP Core v15.0
Table 34-2: v15.0 May 2015
Description
Impact
Added new registers:
•
•
•
•
Software reset register for TX and RX datapaths.
Transfer status registers for TX and RX datapaths.
VLAN and stacked VLAN detection disable.
Programmable IPG registers for 10G and 10M/100M/1G operating
speeds.
If you do not upgrade your IP
core, it does not have this new
feature.
Related Information
• Introduction to Altera IP Cores
• Low Latency Ethernet 10G MAC MegaCore Function User Guide
• Errata for Low Latency Ethernet 10G MAC IP core in the Knowledge Base
Low Latency Ethernet 10G MAC IP Core v14.1
Table 34-3: v14.1 December 2014
Description
Impact
Added new parameter options:
• Enable 10GBASE-R register mode
• Time of Day Format.
Added new signals to support 10GBASE-R register mode:
•
•
•
•
tx_xcvr_clk
If you do not upgrade your IP
core, it does not have this new
feature.
rx_xcvr_clk
xgmii_tx_valid
xgmii_rx_valid
Related Information
• Introduction to Altera IP Cores
• Low Latency Ethernet 10G MAC MegaCore Function User Guide
• Errata for Low Latency Ethernet 10G MAC IP core in the Knowledge Base
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Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition
34-3
Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition
Table 34-4: v14.0 Arria 10 Edition August 2014
Description
Verified in the Quartus II software v14.0 Arria 10 Edition. (Added
support for Arria 10 devices).
Impact
If you upgrade your IP core to
the Quartus II software v14.0
Arria 10 Edition, all of the
changes require that you
regenerate the IP core manually
and reconnect it in your design.
Related Information
• Introduction to Altera IP Cores
• Low Latency Ethernet 10G MAC MegaCore Function User Guide
• Errata for Low Latency Ethernet 10G MAC IP core in the Knowledge Base
Low Latency Ethernet 10G MAC IP Core v14.0
Table 34-5: v14.0 June 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Added support for unidirectional feature.
Modified the reset behavior—TX and RX reset signals changed from
asynchronous reset to synchronous reset.
Resource improvement with no impact to performance.
Impact
-
The following changes are
optional. If you do not upgrade
your IP core, it does not have
these new features.
Related Information
• Introduction to Altera IP Cores
• Low Latency Ethernet 10G MAC MegaCore Function User Guide
• Errata for Low Latency Ethernet 10G MAC IP core in the Knowledge Base
Low Latency Ethernet 10G MAC IP Core Revision History
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Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition
Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition
Table 34-6: v13.1 Arria 10 Edition December 2013
Description
Impact
-
Added support for Arria 10 devices.
Related Information
• Introduction to Altera IP Cores
• Low Latency Ethernet 10G MAC MegaCore Function User Guide
• Errata for Low Latency Ethernet 10G MAC IP core in the Knowledge Base
Low Latency Ethernet 10G MAC IP Core v13.1
Table 34-7: v13.1 November 2013
Description
Impact
Initial release.
-
• Lowest latency 10-Gbps Ethernet MAC with 32-bit user interface
mode.
• Final support for Arria V GZ and Stratix V devices.
Related Information
• Introduction to Altera IP Cores
• Low Latency Ethernet 10G MAC MegaCore Function User Guide
• Errata for Low Latency Ethernet 10G MAC IP core in the Knowledge Base
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Note: Unless otherwise noted, the Nios II processor supports new device families as they are supported
by the Quartus Prime software.
Table 35-1: Product Revision History
Version
Date
Description
15.1
November
2015
• GCC updated to 4.9.2
• Enhanced device and IP support
• Nios II Gen2 processor now known as Nios II processor
15.0
June 2015
Enhanced device and IP support
14.1
December
2014
• The Nios II Gen2 processor is fully supported.
• Enhanced device and IP support
Related Information
• IP Catalog and Parameter Editor
For more information about the IP Catalog, refer to "IP Catalog and Parameter Editor" in the Introduc‐
tion to Altera IP Cores.
• Nios II Embedded Design Suite Release Notes
• Altera Knowledge Base
You can search for Nios II processor errata in the Altera Knowledge Base.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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What's New in v15.1
What's New in v15.1
Enhancements
• The floating point hardware 2 (FPH2) has been enhanced to support optional exclusion of the sqrt()
custom instruction.(1)
• The name of the Nios II Gen2 core is now simply Nios II. The register transfer level (RTL) name
remains Nios II Gen2.
• The parameter editor for the Nios II vectored interrupt controller (VIC) now allows selection of the
number of pipeline stages used in the core. The default value is five stages, which results in five cycles
of latency.
Note: The new option allows you to reduce latency. However, the penalty for this reduction is a lower
fMAX in the VIC.
• A descriptor prefetcher is added to the modular Scatter-Gather Direct Memory Access (mSGDMA) IP
core to automatically fetch descriptors from memory.
• GNU Compiler Collections (GCC) has been upgraded to v4.9.2
Bug Fixes
• The known issue with the Floating Point Hardware 2 square root custom instruction, reported in the
15.0 release notes, has been fixed.
Related Information
Square Root Error in Floating Point Custom Instruction 2
What's New in v15.0
New Nios II processor and related embedded IP features:
• VHDL simulation issue resolved.
• Improved support for the MAX 10 analog-to-digital converter (ADC) through the enhanced MAX 10
ADC interface IP core.
• Support for MAX 10 dual ADC simultaneous sampling.
• Support for new generic Quad SPI (QSPI) Controller IP core.
• Support for MAX 10 Remote Update IP core.
• Nios II Flash Accelerator, available in the Nios II component editor, for increased performance when
running from user flash memory (beta release).
There is a known issue with the Floating Point Hardware 2 square root custom instruction. To download
a patch, refer to the Square Root Error in Floating Point Custom Instruction 2 topic in the Knowledge Base.
Related Information
Square Root Error in Floating Point Custom Instruction 2
(1)
The sqrt() instruction is a look-up table based implementation and relies on a pre-populated FPGA
memory. However, for some MAX® 10 device configurations, FPGA memory block initialization is not
supported, which means that this instruction does not function correctly for these configurations.
Note: In these cases, the instruction can be manually omitted from the FPH2 module and the sqrt()
operation can be performed correctly in software.
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What's New in v14.1
35-3
What's New in v14.1
The Nios II Gen2 processor is fully supported.
Other new Nios II processor and related embedded IP features:
• The original Nios II processor is referred to as the Nios II Classic processor.
• The electrically programmable configuration quad-serial (EPCQ) controller IP core is upgraded to
support x4 mode and EPCQ low-voltage (EPCQ-L) devices.
• Both Nios II processor cores support the generic QSPI Controller IP core as a beta release.
• The Nios II Gen2 processor supports the MAX 10 Altera Flash Controller IP core, which interfaces
MAX 10 flash memory to FPGA logic.
Related Information
• Nios II Classic Processor Reference Handbook
• Nios II Gen2 Processor Reference Handbook
• Nios II Gen2 Migration Guide
Nios II Processor Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
NCO IP Core v15.0
Table 36-1: v15.0 May 2015
Description
Verified in the Quartus II software v15.0.
Impact
-
Related Information
• NCO MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for NCO IP Core in the Knowledge Base
NCO IP Core v14.1
Table 36-2: v14.1 December 2014
Description
Added final support for Arria 10 and MAX 10 devices
Impact
-
Related Information
• NCO MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for NCO IP Core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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UniPHY Revision History
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Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
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QDR II and QDR II+ SRAM Controller with UniPHY v15.1
Table 37-1: v15.1 November 2015
Description
Verified in the Quartus Prime software v15.1
Impact
-
Related Information
• External Memory Interfaces Handbook
• Errata for QDR II and QDR II+ SRAM Controller with UniPHY in the Knowledge Base
QDR II and QDR II+ SRAM Controller with UniPHY v15.0
Table 37-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0
Impact
-
Related Information
• External Memory Interfaces Handbook
• Errata for QDR II and QDR II+ SRAM Controller with UniPHY in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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QDR II and QDR II+ SRAM Controller with UniPHY v14.1
QDR II and QDR II+ SRAM Controller with UniPHY v14.1
Table 37-3: v14.1 December 2014
Description
Impact
Verified in the Quartus II software v14.1
-
Related Information
• External Memory Interfaces Handbook
• Errata for QDR II and QDR II+ SRAM Controller with UniPHY in the Knowledge Base
QDR II and QDR II+ SRAM Controller with UniPHY v14.0
Table 37-4: v14.0 June 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Removed support for Cyclone III, Cyclone III LS, and Stratix III
devices
-
Related Information
• External Memory Interfaces Handbook
• Errata for QDR II and QDR II+ SRAM Controller with UniPHY in the Knowledge Base
QDR II and QDR II+ SRAM Controller with UniPHY v13.1
Table 37-5: v13.1 November 2013
Description
Impact
Verified in the Quartus II software v13.1
-
Removed support for HardCopy III and HardCopy IV devices
-
Related Information
• External Memory Interfaces Handbook
• Errata for QDR II and QDR II+ SRAM Controller with UniPHY in the Knowledge Base
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Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
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RapidIO IP Core v15.1
Table 38-1: Version 15.1 November 2015
Description
Added new parameter PacketNot-Accepted to Link Request
timeout. This parameter specifies
whether or not the IP core enters
a Fatal Error state if it sends a
packet-not-accepted control
symbol and then does not receive
any link-request control
symbol from the RapidIO link
partner within the period of time
indicated in the VALUE field of the
PLTCTRL register at offset 0x120.
By default, for backward
compatibility, this parameter is
turned on.
Impact
Notes
The default value of this parameter
turns on the feature, which is
always on in the previous version of
the IP core. Turning off this
parameter changes the IP core
behavior.
Related Information
• RapidIO MegaCore Function User Guide
• Errata for RapidIO IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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RapidIO IP Core v15.0
RapidIO IP Core v15.0
Table 38-2: Version 15.0 May 2015
Description
Impact
Notes
The IP core loses lane synchronization when Lane synchronization is
a lane receives three errored characters.
slightly more robust.
Previously the IP core lost lane synchroniza‐
tion after receiving two errored characters
on a lane.
Table 38-3: RapidIO IP Core Signal Changes
Signals added or modified in version 15.0.
Old Signal Name
—
New Signal Name
no_sync_indicator
Notes
When this new output signal is low, it indicates at least
one lane is not synchronized.
Related Information
• RapidIO MegaCore Function User Guide
• Errata for RapidIO IP core in the Knowledge Base
RapidIO IP Core v14.1
Table 38-4: Version 14.1 December 2014
Description
The Quartus II software v14.1 requires that
you specify a device if your IP core targets
the Arria 10 device family. If you do not
specify your target Arria 10 device, the IP
Upgrade tool insists that your IP core
requires upgrade, but does not clarify the
reason.
Impact
Notes
You must ensure that you
specify a device for your v14.0
Arria 10 Edition IP core
variation and regenerate it in
the Quartus II software v14.1.
Related Information
• RapidIO MegaCore Function User Guide
• Errata for RapidIO IP core in the Knowledge Base
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RapidIO IP Core v14.0 Arria 10 Edition
38-3
RapidIO IP Core v14.0 Arria 10 Edition
Table 38-5: Version 14.0 Arria 10 Edition August 2014
Description
Verified in the Quartus II software v14.0
Arria 10 Edition. (Added support for Arria
10 devices).
RapidIO IP core variations that target an
Arria 10 device have the following
differences from the variations that target
earlier device families.
Impact
Notes
Upgrading your existing IP
core from a previous release of
the Quartus II software
requires migrating it to the
Arria 10 device family. To
migrate your IP core to the
Arria 10 device family, you
must regenerate the IP core
manually in the Quartus II
v14.0 Arria 10 Edition
software and reconnect it in
your design.
Arria 10 variations require that you
instantiate and connect a TX transceiver
PLL IP core and a reset controller in your
design.
Upgrading your existing IP
core from a previous release of
the Quartus II software
requires migrating it to the
Arria 10 device family. To
migrate your IP core to the
Arria 10 device family, you
must regenerate the IP core
manually in the Quartus II
v14.0 Arria 10 Edition
software and reconnect it in
your design.
The new interface signals
are listed in the RapidIO
IP Core Signal Changes
table.
Arria 10 variations do not require that you
instantiate and connect a dynamic reconfi‐
guration controller. Instead, if you turn on
the new parameter Enable transceiver
dynamic reconfiguration, these variations
have an internal reconfiguration controller
that the user accesses through an AvalonMM interface.
Upgrading your existing IP
core from a previous release of
the Quartus II software
requires migrating it to the
Arria 10 device family. To
migrate your IP core to the
Arria 10 device family, you
must regenerate the IP core
manually in the Quartus II
v14.0 Arria 10 Edition
software and reconnect it in
your design.
The new interface signals
are listed in the RapidIO
IP Core Signal Changes
table.
RapidIO IP Core Revision History
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RapidIO IP Core v14.0 Arria 10 Edition
Description
If a RapidIO IP core that targets an Arria 10
device includes an I/O Logical layer AvalonMM slave interface or an I/O Logical layer
Avalon-MM master interface, the following
conditions apply:
• The IP core must include both an I/O
Logical layer slave interface and an I/O
Logical layer master interface. It cannot
include one but not the other.
• The I/O Logical layer slave module
preserves transaction ordering between
read and write operations.
• The number of RX address translation
windows is 16.
• The number of TX address translation
windows is 16.
Impact
Notes
Unsupported parameters and
parameter values are not
available in the parameter
editor or cause error messages
that block IP core generation.
If your IP core is already in
this subset of variations, you
can recreate the precise
variation. However, you must
still regenerate the IP core
manually and reconnect it in
your design, because of other
changes.
If a RapidIO IP core that targets an Arria 10
device includes an I/O Maintenance Logical
layer module, the following conditions
apply:
Unsupported parameters and
parameter values are not
available in the parameter
editor or cause error messages
that block IP core generation.
• The module has both master and slave
If your IP core is already in
ports.
this subset of variations, you
• The number of Maintenance transmit
can recreate the precise
address translation windows is 16.
variation. However, you must
• The module supports both reception and still regenerate the IP core
transmission of port-write requests, or manually and reconnect it in
supports neither.
your design, because of other
changes.
A RapidIO IP core that targets an Arria 10
Unsupported parameters and
device supports both outbound and inbound parameter values are not
DOORBELL messages, or it supports neither.
available in the parameter
editor or cause error messages
that block IP core generation.
If your IP core is already in
this subset of variations, you
can recreate the precise
variation. However, you must
still regenerate the IP core
manually and reconnect it in
your design, because of other
changes.
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RapidIO IP Core v14.0 Arria 10 Edition
Description
Impact
If a RapidIO IP core that targets an Arria 10
device supports DOORBELL messages, it
preserves transaction order between
DOORBELL messages and I/O write request
transactions.
Unsupported parameters and
parameter values are not
available in the parameter
editor or cause error messages
that block IP core generation.
If your IP core is already in
this subset of variations, you
can recreate the precise
variation. However, you must
still regenerate the IP core
manually and reconnect it in
your design, because of other
changes.
A RapidIO IP core that targets an Arria 10
device automatically synchronizes
transmitted ackIDs.
Unsupported parameters and
parameter values are not
available in the parameter
editor or cause error messages
that block IP core generation.
If your IP core is already in
this subset of variations, you
can recreate the precise
variation. However, you must
still regenerate the IP core
manually and reconnect it in
your design, because of other
changes.
In a RapidIO IP core that targets an Arria 10
device, the number of link-request
attempts before declaring a fatal error is tied
to 7.
Unsupported parameters and
parameter values are not
available in the parameter
editor or cause error messages
that block IP core generation.
If your IP core is already in
this subset of variations, you
can recreate the precise
variation. However, you must
still regenerate the IP core
manually and reconnect it in
your design, because of other
changes.
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RapidIO IP Core v14.0 Arria 10 Edition
Description
Impact
Notes
In a RapidIO IP core that targets an Arria 10 Unsupported parameters and
device, the Physical layer receive and
parameter values are not
transmit buffers are 32 Kbytes each.
available in the parameter
editor or cause error messages
that block IP core generation.
If your IP core is already in
this subset of variations, you
can recreate the precise
variation. However, you must
still regenerate the IP core
manually and reconnect it in
your design, because of other
changes.
In the parameter editor for RapidIO IP core
variations that target an Arria 10 device, the
Disable Destination ID checking by
default parameter is not available. Arria 10
variations do not check destination IDs, by
default. However, support for controlling
this feature through the IP core registers is
available in all RapidIO IP core variations, as
it was in the previous release.
Unsupported parameters and
parameter values are not
available in the parameter
editor or cause error messages
that block IP core generation.
If your IP core is already in
this subset of variations, you
can recreate the precise
variation. However, you must
still regenerate the IP core
manually and reconnect it in
your design, because of other
changes.
Table 38-6: RapidIO IP Core Signal Changes
Signals added or modified in version 14.0 Arria 10 Edition.
Old Signal Name
—
New Signal Name
tx_bonded_clocks_
ch<n>[5:0]
Notes
New interface to external TX PLL. Relevant for
Arria 10 variations only.
Individual transceiver channel clock signals. One
signal (_ch<n>) for each RapidIO lane <n>.
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RapidIO IP Core v14.0 Arria 10 Edition
Old Signal Name
New Signal Name
—
reconfig_clk_ch<n>
—
reconfig_reset_
ch<n>
—
reconfig_read_
ch<n>
—
reconfig_write_
ch<n>
—
reconfig_address_
ch<n>[9:0]
—
reconfig_
readdata_ch<n>
[31:0]
—
reconfig_
waitrequest_
ch<n>
—
reconfig_
writedata_ch<n>
[31:0]
—
tx_analogreset[N-1:0]
—
rx_analogreset[N1:0]
—
tx_digitalreset[N1:0]
—
rx_digitalreset[N1:0]
reconfig_togxb
Not present in Arria
10 variations.
reconfig_fromgxb
Not present in
Arria 10
variations.
38-7
Notes
New Arria 10 transceiver reconfiguration
interface. This interface is available if you turn
on Enable transceiver dynamic reconfiguration
in the RapidIO parameter editor. Relevant for
Arria 10 variations only.
One signal (_ch<n>) for each RapidIO lane <n>.
New interface to external reset controller.
Relevant for Arria 10 variations only.
N is the number of RapidIO lanes.
Transceiver reconfiguration interface for Arria
V, Cyclone V, and Stratix V variations. This
interface is present only in Arria V, Cyclone V,
and Stratix V variations (as supported in past
and future versions of the Quartus II software).
These signals are not present in Arria 10
variations.
Related Information
• RapidIO MegaCore Function User Guide
• Errata for RapidIO IP core in the Knowledge Base
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RapidIO IP Core v14.0
RapidIO IP Core v14.0
Table 38-7: Version 14.0 June 2014
Description
Impact
Notes
Removed support for Cyclone III, Cyclone III LS, and Stratix
III device families. The Quartus II software v14.0 does not
support these device families.
If your IP core variation targets
one of these device families, this
change requires that you revise
your IP core variation and
regenerate it.
Removed support for Physical-layer only variations.
If your IP core variation is no
longer supported, and you choose
to upgrade the IP core, this
change requires that you revise
your IP core variation and
regenerate it.
Removed support for external transceivers. All supported
variations include configuration of the high-speed
transceivers on the target device.
If your IP core variation is no
longer supported, and you choose
to upgrade the IP core, this
change requires that you revise
your IP core variation and
regenerate it.
Removed naming differences between Qsys-generated and
non-Qsys-generated IP core variations. New variations
generated in the 14.0 software, whether in Qsys or outside
Qsys, use the port names previously identified with the Qsys
variations.
If your IP core was generated in
the MegaWizard Plug-In Manager
flow, and you choose to upgrade
the IP core, this change requires
that you revise your IP core
variation, upgrade it, and
reconnect your IP core in your
design.
Upgraded to support the new IP Catalog. For more informa‐
tion about the IP Catalog, refer to IP Catalog and Parameter
Editor in Introduction to Altera IP Cores.
This change is optional for v13.1
IP cores. However, IP upgrade is
required for IP cores v13.0 and
earlier.
Related Information
• Introduction to Altera IP Cores
• RapidIO MegaCore Function User Guide
• Errata for RapidIO IP core in the Knowledge Base
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RapidIO IP Core v13.1
38-9
RapidIO IP Core v13.1
Table 38-8: Version 13.1 November 2013
Description
Impact
Notes
Removed support for the Arria GX, Cyclone II, HardCopy II,
HardCopy III, HardCopy IV E, HardCopy IV GX, Stratix II,
and Stratix II GX device families.
Related Information
• RapidIO MegaCore Function User Guide
• Errata for RapidIO IP core in the Knowledge Base
RapidIO IP Core v13.0
Table 38-9: Version 13.0 May 2013
Description
Impact
Notes
Added 2x mode for Arria V, Cyclone V, and Stratix V devices.
Removed support for SOPC Builder design flow.
Related Information
• RapidIO MegaCore Function User Guide
• Errata for RapidIO IP core in the Knowledge Base
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Related Information
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RapidIO II IP Core v15.1
Table 39-1: Version 15.1 November 2015
Description
The RapidIO II IP core no longer supports
6.25 Gbaud, Avalon-ST pass-through
variations that target the Arria V family on
any -5 speed grade device.
Impact
Note
You must target a different
Arria V device for these
variations.
If you connect your RapidIO II IP core to an
Altera Transceiver PHY Reset Controller,
added the requirement to set the RX_PER_
CHANNEL parameter of the reset controller
to the value of 1.
Related Information
• RapidIO II MegaCore Function User Guide
• Errata for RapidIO II IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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ISO
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Registered
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RapidIO II IP Core v14.1
RapidIO II IP Core v14.1
Table 39-2: Version 14.1 December 2014
Description
Impact
The Quartus II software v14.1 requires that
you specify a device if your IP core targets
the Arria 10 device family. If you do not
specify your target Arria 10 device, the IP
Upgrade tool insists that your IP core
requires upgrade, but does not clarify the
reason.
You must ensure that you
specify a device for your v14.0
Arria 10 Edition IP core
variation and regenerate it in
the Quartus II software v14.1.
Added io_error_response_set input port.
The IP core sets the IO_ERROR_RSP field in
bit [31] of the Logical/Transport Layer
Error Detect CSR at offset 0x308 when this
signal changes value from 0 to 1.
If you upgrade the RapidIO II
IP core in your design to the IP
core v14.1, you must reconnect
the IP core in your design so
the new input signal does not
float.
Changed behavior of individual baud rate _
ENABLE and _SUPPORT fields of Port 0
Control 2 CSR at offset 0x154. Instead of all
being set to the value of 1, now the _SUPPORT
fields for baud rates less than or equal to the
value of the Maximum baud rate parameter
have the value of 1, and the _SUPPORT fields
for baud rates greater than the value of the
Maximum baud rate parameter have the
value of 0. Instead of all being set to the value
of 1, now the _ENABLE field for the baud rate
at which the IP core is operating has the
value of 1, and the _ENABLE fields for all
other baud rates have the value of 0.
If you upgrade the RapidIO II
IP core in your design to the IP
core v14.1, the Port 0 Control 2
CSR fields are set as expected
to indicate the supported and
enabled baud rates.
Altera Corporation
Note
To modify the IP core to
run at a different baud
rate than the Maximum
baud rate value, you must
turn on Enable
transceiver dynamic
reconfiguration in the
parameter editor, and
user logic must
reconfigure the
transceiver to the new
baud rate. As indicated by
the values of the Port 0
Control 2 CSR fields, you
can only reconfigure the
IP core to a baud rate
equal or slower than the
Maximum baud rate
value.
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RapidIO II IP Core v14.0 Arria 10 Edition
Description
Impact
Made changes to Port 0 Control CSR at
offset 0x15C:
If you upgrade the RapidIO II
IP core in your design to the IP
core v14.1, your IP core
implements the new behavior.
You can use the new register
field to force an interrupt in
this case.
• Added new field PORT_ERR_IRQ_EN that
controls whether an interrupt is
generated when an error is flagged in the
Port 0 Error Detect register at offset
0x340. The new field is in bit [6] of the
Port 0 Control CSR.
• Moved DIS_DEST_ID_CHK field from bit
[7] to bit [8].
• Moved LOG_TRANS_ERR_IRQ_EN field
from bit [6] to bit [7].
39-3
Note
Related Information
• RapidIO II MegaCore Function User Guide
• Errata for RapidIO II IP core in the Knowledge Base
RapidIO II IP Core v14.0 Arria 10 Edition
Table 39-3: Version 14.0 Arria 10 Edition August 2014
Description
Impact
Verified in the Quartus II software v14.0
Arria 10 Edition. (Added support for Arria
10 devices).
Upgrading your existing IP
core from a previous release of
the Quartus II software
requires migrating it to the
Arria 10 device family. To
migrate your IP core to the
Arria 10 device family, you
must regenerate the IP core
manually in the Quartus II
v14.0 Arria 10 Edition software
and reconnect it in your
design.
RapidIO II IP Core Revision History
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Note
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RapidIO II IP Core v14.0 Arria 10 Edition
Description
Impact
Note
Arria 10 variations require that you
Upgrading your existing IP
instantiate and connect a TX transceiver PLL core from a previous release of
IP core in your design.
the Quartus II software
requires migrating it to the
Arria 10 device family. To
migrate your IP core to the
Arria 10 device family, you
must regenerate the IP core
manually in the Quartus II
v14.0 Arria 10 Edition software
and reconnect it in your
design.
The new interface signals
are listed in the RapidIO
II IP Core Signal
Changes table.
Arria 10 variations do not require that you
instantiate and connect a dynamic reconfi‐
guration controller. Instead, if you turn on
the new parameter Enable transceiver
dynamic reconfiguration, these variations
have an internal reconfiguration controller
that the user accesses through an AvalonMM interface.
The new interface signals
are listed in the RapidIO
II IP Core Signal
Changes table.
Upgrading your existing IP
core from a previous release of
the Quartus II software
requires migrating it to the
Arria 10 device family. To
migrate your IP core to the
Arria 10 device family, you
must regenerate the IP core
manually in the Quartus II
v14.0 Arria 10 Edition software
and reconnect it in your
design.
Table 39-4: RapidIO II IP Core Signal Changes
Signals added or modified in version 14.0 Arria 10 Edition.
Old Signal Name
—
New Signal Name
tx_bonded_clocks_
ch<n>[5:0]
Notes
New interface to external TX PLL. Relevant for
Arria 10 variations only.
Individual transceiver channel clock signals. One
signal (_ch<n>) for each RapidIO lane <n>.
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RapidIO II IP Core v14.0 Arria 10 Edition
Old Signal Name
New Signal Name
—
reconfig_clk_ch<n>
—
reconfig_reset_
ch<n>
—
reconfig_read_
ch<n>
—
reconfig_write_
ch<n>
—
reconfig_address_
ch<n>[9:0]
—
reconfig_
readdata_ch<n>
[31:0]
—
reconfig_
waitrequest_
ch<n>
—
reconfig_
writedata_ch<n>
[31:0]
reconfig_to_xcvr
Not present in Arria
10 variations.
reconfig_from_xcvr
Not present in
Arria 10
variations.
pll_locked
Not present in
Arria 10
variations.
pll_powerdown
Not present in
Arria 10
variations.
39-5
Notes
New Arria 10 transceiver reconfiguration
interface. This interface is available if you turn
on Enable transceiver dynamic reconfiguration
in the RapidIO II parameter editor. Relevant for
Arria 10 variations only.
One signal (_ch<n>) for each RapidIO lane <n>.
Transceiver reconfiguration interface signals for
specific non-Arria 10 device families (as
supported in past and future versions of the
Quartus II software). These signals are not
present in Arria 10 variations.
Related Information
• RapidIO II MegaCore Function User Guide
• Errata for RapidIO II IP core in the Knowledge Base
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RapidIO II IP Core v14.0
RapidIO II IP Core v14.0
Table 39-5: Version 14.0 June 2014
Description
Impact
Note
Upgraded to support the new IP Catalog. For more
information about the IP Catalog, refer to IP Catalog and
Parameter Editor in Introduction to Altera IP Cores.
This change is optional
for v13.1 IP cores.
However, IP upgrade is
required for IP cores
v13.0 and earlier.
In case of MAINTENANCE Response with Error status, the
ADDRESS field of the Logical/Transport Layer Address
Capture CSR captures the config_offset value from the
original request.
None. This change is
optional. If you do not
upgrade your IP core, it
does not have this new
feature.
Added new allowed value IMPLEMENTATION SPECIFIC
for INFO_TYPE field of Port 0 Attributes Capture CSR.
None. This change is
optional. If you do not
upgrade your IP core, it
does not have this new
feature.
Related Information
• Introduction to Altera IP Cores
• RapidIO II MegaCore Function User Guide
• Errata for RapidIO II IP core in the Knowledge Base
RapidIO II IP Core v13.1
Table 39-6: Version 13.1 November 2013
Description
Impact
Note
Verified in the Quartus II software v13.1.
Related Information
• RapidIO II MegaCore Function User Guide
• Errata for RapidIO II IP core in the Knowledge Base
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39-7
RapidIO II IP Core v13.0
Table 39-7: Version 13.0 May 2013
Description
Impact
Note
Verified in the Quartus II software v13.0.
Related Information
• RapidIO II MegaCore Function User Guide
• Errata for RapidIO II IP core in the Knowledge Base
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
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Reed-Solomon II IP Core v15.1
Table 40-1: v15.1 November 2015
Description
Added Optimize latency and Optimize resource parameters
Impact
-
Related Information
• Reed-Solomon II MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for Reed-Solomon II IP core in the Knowledge Base
Reed-Solomon II IP Core v15.0
Table 40-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0.
Impact
-
Related Information
• Reed-Solomon II MegaCore Function User Guide
• Introduction to Altera IP Cores
• Errata for Reed-Solomon II IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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RLDRAM 3 PHY-Only IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
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RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core
v15.1
Table 41-1: v15.1 November 2015
Description
Verified in the Quartus Prime software v15.1
Impact
-
Related Information
• External Memory Interface Handbook
• Errata for RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP in the Knowledge
Base
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core
v15.0
Table 41-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0
Impact
-
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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Related Information
• External Memory Interface Handbook
• Errata for RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP in the Knowledge
Base
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core
v14.1
Table 41-3: v14.1 December 2014
Description
Verified in the Quartus II software v14.1
Impact
-
Related Information
• External Memory Interface Handbook
• Errata for RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP in the Knowledge
Base
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core
v14.0
Table 41-4: v14.0 June 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Removed support for Cyclone III, Cyclone III LS, and Stratix III
devices
-
Related Information
• External Memory Interface Handbook
• Errata for RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP in the Knowledge
Base
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41-3
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core
v13.1
Table 41-5: v13.1 November 2013
Description
Impact
Verified in the Quartus II software v13.1
-
Removed support for HardCopy III and HardCopy IV devices
-
Related Information
• External Memory Interface Handbook
• Errata for RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP in the Knowledge
Base
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core Revision History
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SDI v15.1
Table 42-1: v15.1 November 2015
Description
Verified in the Quartus Prime software v15.1
Impact
-
Related Information
• Introduction to Altera IP Cores
• SDI IP Core User Guide
• Errata for SDI IP Core in the Knowledge Base
SDI v15.0
Table 42-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0
Impact
-
Related Information
• Introduction to Altera IP Cores
• SDI IP Core User Guide
• Errata for SDI IP Core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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SDI v14.0
SDI v14.0
Table 42-3: v14.0 June 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Impact
-
Removed support for Cyclone III and Stratix III devices.
Related Information
• Introduction to Altera IP Cores
• SDI IP Core User Guide
• Errata for SDI IP Core in the Knowledge Base
Altera Corporation
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SDI II IP Core v15.1
Table 43-1: v15.1 November 2015
Description
Impact
Redefined the rx_format signal. Each stream of 6G-SDI and 12G-SDI
interfaces reports its own detected rx format. For example, when
receiving 2160p60 in 12G-SDI, all 4 streams are expected to report
1080p60.
Added new interface signals for Arria V, Cyclone V, and Stratix V
devices:
• rx_trs_in
• pll_powerdown_in
• pll_ powerdown_out
Added new reconfiguration management parameters for Arria 10
devices:
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
• VIDEO_STANDARD
• ED_TXPLL_SWITCH
• XCVR_RCFG_IF_TYPE
Fixed jitter tolerance reduction issue when receiving SD-SDI video
standards.
Updated the sdc constraint for the dual-clock FIFO (DCFIFO)
component instantiated in the core.
Related Information
• Introduction to Altera IP Cores
• SDI II IP Core User Guide
• Errata for SDI II IP Core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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SDI II IP Core v15.0
SDI II IP Core v15.0
Table 43-2: v15.0 May 2015
Description
Impact
Added the following parameters:
• Added new video standard Multi rate (up to 12G) for Arria 10
devices.
• Added TX PLL reference clock switching option for Dynamic Tx
clock switching parameter.
Included design example for TX PLL reference clock switching.
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
Note: Tx PLL reference clock switching is not supported for ATX PLL
in Arria V GZ and Stratix V devices.
Related Information
• Introduction to Altera IP Cores
• SDI II IP Core User Guide
• Errata for SDI II IP Core in the Knowledge Base
SDI II IP Core v14.1
Table 43-3: v14.1 December 2014
Description
Impact
The run_sim script for each simulator is now located in its respective
folder.
-
rx_format signal now reports video transport format instead of
If you update to the Quartus II
software version 14.1, you must
update your SDI II IP core to
incorporate this fix.
picture format. The signal reports 3G Level A RGB or YCbCr 4:4:4
format.
Changed the names of the following parameters:
• Convert Level A to Level B (SMPTE 372M) changed to Convert
HD-SDI dual link to 3G-SDI (level B)
• Convert Level B to Level A (SMPTE 372M) changed to Convert
3G-SDI (level B) to HD-SDI dual link
-
Related Information
• Introduction to Altera IP Cores
• SDI II IP Core User Guide
• Errata for SDI II IP Core in the Knowledge Base
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SDI Audio IP Cores v15.1
Table 44-1: v15.1 November 2015
Description
Verified in the Quartus Prime software v15.1.
Impact
-
Related Information
• Introduction to Altera IP Cores
• SDI Audio IP Cores User Guide
• Errata for SDI IP Core in the Knowledge Base
SDI Audio IP Cores v15.0
Table 44-2: v15.0 May 2015
Description
Verified in the Quartus II software v15.0
Impact
-
Related Information
• Introduction to Altera IP Cores
• SDI Audio IP Cores User Guide
• Errata for SDI IP Core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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SDI Audio IP Cores v14.0
SDI Audio IP Cores v14.0
Table 44-3: v14.0 June 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
-
Removed support for Cyclone III and Stratix III devices.
-
Related Information
• Introduction to Altera IP Cores
• SDI Audio IP Cores User Guide
• Errata for SDI IP Core in the Knowledge Base
Altera Corporation
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
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SerialLite II v14.0
Table 45-1: v14.0 June 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Impact
-
Related Information
• Introduction to Altera IP Cores
• SerialLite II IP Core User Guide
• Errata for SerialLite II IP Core in the Knowledge Base
SerialLite II v13.1
Table 45-2: v13.1 November 2013
Description
Removed support for the following devices:
Impact
-
• Arria GX
• HardCopy IV
• Stratix GX and Stratix II GX
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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SerialLite II v13.1
Description
OpenCore Plus feature will not be supported for Arria V, Arria V GX,
Cyclone V, and Stratix V devices.
Impact
-
Related Information
• Introduction to Altera IP Cores
• SerialLite II IP Core User Guide
• Errata for SerialLite II IP Core in the Knowledge Base
Altera Corporation
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
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SerialLite III Streaming IP Core v15.1
Table 46-1: v15.1 November 2015
Description
Added a new parameter—Burst Gap.
Impact
—
For Arria 10 devices, the PMA width for Interlaken mode is changed to IP Upgrade is compulsory if you
64 bits.
are using Arria 10 devices.
For Arria 10 devices, the I/O PLL replaces the fractional PLL (fPLL) in
generating the core clock and user clock signals.
Updated the bit function in the error_tx signal.
Updated the design example to support Arria 10 devices.
For Arria 10 devices, automatic
upgrade will fail for IP core that
uses Standard Clocking mode
and was generated in a prior
version of the Quartus II
software. You must uncheck the
Auto Upgrade option and click
Upgrade in Editor to select a
valid Transceiver Reference
Clock frequency if the existing
selection is invalid.
For Stratix V and Arria V GZ
devices, these changes are
optional. If you do not upgrade
your IP core, it does not have
these new features.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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SerialLite III Streaming IP Core v15.0
Related Information
• SerialLite III Streaming IP Core User Guide
• Errata for SerialLite III Streaming IP core in the Knowledge Base
SerialLite III Streaming IP Core v15.0
Table 46-2: v15.0 May 2015
Description
Impact
Updated sync_tx and sync_rx signal bus width to 8-bits.
–
Design example now supports simulation testbench based on user
configurations in the Seriallite III Streaming IP core parameter editor.
–
Related Information
• SerialLite III Streaming MegaCore Function User Guide
• Errata for SerialLite III Streaming IP core in the Knowledge Base
SerialLite III Streaming IP Core v14.1
Table 46-3: Version 14.1 December 2014
Description
The Quartus II software v14.1 requires that you
specify a device if your IP core targets the Arria
10 device family. If you do not specify your
target Arria 10 device, the IP Upgrade tool
insists that your IP core requires upgrade, but
does not clarify the reason.
Impact
Notes
You must ensure that you specify a
device for your v14.0 Arria 10 Edition
IP core variation and regenerate it in
the Quartus II software v14.1.
Added support for 17.4 Gbps data rate in
variations that target an Arria 10 device. In the
parameter editor, added support for the value
of 17.4 Gbps for the Transceiver data rate per
lane parameter in variations that target an
Arria 10 device.
Related Information
• SerialLite III Streaming MegaCore Function User Guide
• Errata for SerialLite III Streaming IP core in the Knowledge Base
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SerialLite III Streaming IP Core v14.0 Arria 10 Edition
46-3
SerialLite III Streaming IP Core v14.0 Arria 10 Edition
Table 46-4: Version 14.0 Arria 10 Edition August 2014
Description
Impact
Notes
This IP core requires manual regeneration
Verified in the Quartus II software
v14.0 Arria 10 Edition. (Added support and reconnection in your design. You
cannot use the standard process in the
for Arria 10 devices).
Quartus II IP Upgrade tool to upgrade this
SerialLite III IP core variations that
IP core. Upgrading your existing IP core
target an Arria 10 device have the
from a previous release of the Quartus II
following differences from the
software requires migrating it to the Arria
variations that target earlier device
10 device family. To migrate your SerialLite
families.
III IP core to the Arria 10 device family, you
must regenerate the IP core manually in the
Quartus II v14.0 Arria 10 Edition software
and reconnect it in your design.
Arria 10 variations have a new IP core When you begin the regeneration process
name in the IP Catalog. Instead of
by selecting the IP core, note the change in
SerialLite III Streaming, the Arria 10 IP core name in the IP Catalog.
IP core name is Arria 10 SerialLite III
Streaming.
Arria 10 variations require that you
Upgrading your existing IP core from a
instantiate and connect a TX
previous release of the Quartus II software
transceiver PLL IP core in your design. requires migrating it to the Arria 10 device
family. To migrate your IP core to the Arria
10 device family, you must regenerate the
IP core manually in the Quartus II v14.0
Arria 10 Edition software and reconnect it
in your design.
The new interface
signals are listed in
the SerialLite III
Streaming IP Core
Signal Changes
table.
Arria 10 variations do not require that
you instantiate and connect a dynamic
reconfiguration controller. Instead,
these variations have an internal
reconfiguration controller that you
access through an Avalon-MM
interface.
The new interface
signals are listed in
the SerialLite III
Streaming IP Core
Signal Changes
table.
You must select the value for the
Transceiver reference clock frequency
parameter from a drop-down menu.
The SerialLite III Streaming parameter
editor does not automatically set the
value for Arria 10 variations.
SerialLite III Streaming IP Core Revision History
Send Feedback
Upgrading your existing IP core from a
previous release of the Quartus II software
requires migrating it to the Arria 10 device
family. To migrate your IP core to the Arria
10 device family, you must regenerate the
IP core manually in the Quartus II v14.0
Arria 10 Edition software and reconnect it
in your design.
Parameter editor
change.
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SerialLite III Streaming IP Core v14.0 Arria 10 Edition
Description
Impact
Notes
The Device speed grade parameter is
not available in the SerialLite III
parameter editor for variations that
target an Arria 10 device.
Parameter editor
change.
If you specify the Source direction, you
must set the value of the Transceiver
reference clock frequency parameter
to none. Arria 10 Source variations do
not receive the transceiver TX
reference clock as an input signal, and
therefore this parameter does not
modify the SerialLite III IP core.
Parameter editor
change.
Currently, Arria 10 variations do not
provide support for Transceiver data
rate per lane greater than 15.625 Gbps.
Currently, Altera does not provide a
hardware design example for Arria 10
variations.
The testbench you can generate from
the SerialLite III parameter editor for
Arria 10 variations is only available for
Sink and Duplex directions. If your IP
core has the value of the Direction
parameter set to Source, the testbench
does not simulate correctly with the IP
core.
Testbench
availability change.
The testbench you can generate from
the SerialLite III parameter editor for
Arria 10 variations automatically forces
the DUT meta frame length to 200
words. If you specify a different value
for the Meta frame length parameter,
your IP core retains the value you
specify, but when the testbench runs it
simulates with the IP core meta frame
length set to 200 words.
Testbench
behavior change.
Altera Corporation
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SerialLite III Streaming IP Core v14.0 Arria 10 Edition
46-5
Table 46-5: SerialLite III Streaming IP Core Signal Changes
Signals added or modified in version 14.0 Arria 10 Edition.
Old Signal Name
New Signal Name
—
tx_serial_clk[N-1:0]
—
tx_pll_locked
phy_mgmt_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_clk_
reset
phy_mgmt_read
phy_mgmt_read
phy_mgmt_write
phy_mgmt_write
phy_mgmt_addr[8:0]
phy_mgmt_
addr[M:0]
Notes
New interface to external TX PLL. Relevant for
Arria 10 variations only.
N is the number of IP core lanes.
In Arria 10 variations, this interface provides
access to control Arria 10 transceiver reconfigu‐
ration, by connecting directly to the reconfigura‐
tion interface of the included Arria 10 Native
PHY IP core.
In Arria 10 variations, the width of phy_mgmt_
addr is a value in the range of 11 to 16,
phy_mgmt_readdata[31:0]
phy_mgmt_
readdata[31:0]
phy_mgmt_waitrequest
phy_mgmt_
waitrequest
phy_mgmt_writedata[31:0]
phy_mgmt_
writedata[31:0]
reconfig_busy
reconfig_busy
Arria 10 variations of the IP core ignore this
input signal.
xcvr_pll_ref_clk
xcvr_pll_ref_clk
Arria 10 Source-only variations of the iP core
ignore this input signal.
reconfig_to_xcvr
Not present in Arria
10 variations.
reconfig_from_xcvr
Not present in
Arria 10
variations.
Transceiver reconfiguration interface for Arria V
GZ and Stratix V variations. This interface is
present only in Arria V GZ and Stratix V
variations (as supported in past and future
versions of the Quartus II software). It is not
present in Arria 10 variations.
depending on the number of lanes. (M is 10 to
15).
Related Information
• SerialLite III Streaming MegaCore Function User Guide
• Errata for SerialLite III Streaming IP core in the Knowledge Base
SerialLite III Streaming IP Core Revision History
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SerialLite III Streaming IP Core v14.0
SerialLite III Streaming IP Core v14.0
Table 46-6: Version 14.0 June 2014
Description
Impact
Notes
Impact
Notes
Impact
Notes
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Changed component subfolder name from seriallite_iii to seriallite_iii_
sv.
Related Information
• Introduction to Altera IP Cores
• SerialLite III Streaming MegaCore Function User Guide
• Errata for SerialLite III Streaming IP core in the Knowledge Base
SerialLite III Streaming IP Core v13.1
Table 46-7: Version 13.1 November 2013
Description
Added support for CRC-32 error injection.
Added support for FIFO ECC protection.
Related Information
• SerialLite III Streaming MegaCore Function User Guide
• Errata for SerialLite III Streaming IP core in the Knowledge Base
SerialLite III Streaming IP Core v13.0
Table 46-8: Version 13.0 May 2013
Description
Initial release.
Related Information
• SerialLite III Streaming MegaCore Function User Guide
• Errata for SerialLite III Streaming IP core in the Knowledge Base
Altera Corporation
SerialLite III Streaming IP Core Revision History
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SmartVID Controller v15.1
Table 47-1: v15.1 November 2015
Description
Verified in the Quartus Prime software v15.1.
Impact
-
Related Information
• Introduction to Altera IP Cores
• SmartVID Controller User Guide
• Errata for SmartVID Controller IP core in the Knowledge Base
SmartVID Controller v15.0
Table 47-2: v15.0 May 2015
Description
Updated the legal range for the VID Computation Delay (VID_
COMPUTE_DELAY) register from 1 ms–1 second to 10 ms–1 second.
Impact
-
Related Information
• Introduction to Altera IP Cores
• SmartVID Controller User Guide
• Errata for SmartVID Controller IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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SmartVID Controller v14.1
SmartVID Controller v14.1
Table 47-3: v14.1 December 2014
Description
Impact
Initial release for Arria 10 devices.
-
Related Information
• Introduction to Altera IP Cores
• SmartVID Controller User Guide
• Errata for SmartVID Controller IP core in the Knowledge Base
Altera Corporation
SmartVID Controller IP Core Revision History
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Stratix V Hard IP for PCI Express IP Core
Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Stratix V Hard IP for PCI Express IP Core v15.0
Table 48-1: v15.0 May 2015
Description
Impact
In IP core variations with the Avalon-MM DMA interface, added
support for downstream burst read request for a payload of size up to 4
KBytes, if Enable burst capability for RXM BAR2 port is turned on in
the Parameter Editor. Previous maximum downstream read request
payload size was 512 bytes.
If you choose the Avalon-MM
DMA interface, the IP core can
receive and process a burst read
request for a payload of any size
supported by the PCI Express
specification (up to 4 KBytes), if
it receives such a burst read
request on the PCI Express link.
In IP core variations with the Avalon-MM interface, added support to
send message TLPs with data payload of any length from a Root Port.
If you choose the Avalon-MM
interface, a Root Port IP core can
send messages with payload
greater than 1 dword.
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Stratix V Avalon-ST Interface for PCIe Solutions User Guide
Stratix V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Stratix V Hard IP for PCI Express in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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Stratix V Hard IP for PCI Express IP Core v14.1
Stratix V Hard IP for PCI Express IP Core v14.1
Table 48-2: v14.1 December 2014
Description
Impact
Reduced Quartus II compilation warnings by 50%.
Reduces time required to vet
compilation warnings.
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Stratix V Avalon-ST Interface for PCIe Solutions User Guide
Stratix V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Stratix V Hard IP for PCI Express in the Knowledge Base
Stratix V Hard IP for PCI Express IP Core v14.0
Table 48-3: v14.0 June 2014
Description
Impact
Added preliminary support for Stratix V Hard IP for PCI Express with SR-IOV (Single Root I/O Virtualization).
Made the following changes for the V-Series PCIe with Avalon-MM
DMA Interface (previously called the Avalon-MM 256-bit Hard IP for
PCI Express IP Core).
•
•
•
•
•
•
•
•
The Descriptor Controller IP
core included in the 14.0 release
is significantly different from the
one included in 13.1. Altera
Revised programming model and optimized the performance of the
recommends that you update to
Descriptor Controller.
v14.0. Altera no longer support
Added support for either 128- or 256-bit interface to the Applica‐
v13.1.
tion Layer.
Added support for 64-bit addressing, making address translation
unnecessary.
Added support for optional bursting RX Master for BAR2.
Added access to selected Configuration Space registers and link
status registers through the optional Control Register Access (CRA)
Avalon-MM slave port.
Added parameters to enable 256 completion tags with completion
tag checking performed in Application Layer.
Simulation support for Phase 2 and Phase 3 equalization when
requested by third-party BFM for Gen3 variants.
Due to the many changes, the support level has reverted to prelimi‐
nary.
Altera Corporation
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Stratix V Hard IP for PCI Express IP Core v13.1
Description
48-3
Impact
Made the following changes to the Avalon-MM Stratix V Hard IP for
PCI Express IP core:
•
•
•
•
•
•
•
All of these new features are
optional. If you include an
optional feature that changes the
Added access to selected Configuration Space registers and link
port signature of your IP core,
status registers through the optional Control Register Access (CRA)
you must regenerate your design
Avalon-MM slave port.
and connect the signals
Added optional hard IP status bus that includes signals necessary to
connect the Transceiver Reconfiguration Controller IP Core.
Added optional hard IP status extension bus which includes signals
that are useful for debugging, including: link training, status, error,
and Configuration Space signals.
Added support for 64-bit addressing, making address translation
unnecessary.
Added parameters to enable 256 completion tags with completion
tag checking performed in Application Layer.
Simulation support for Phase 2 and Phase 3 equalization when
requested by third-party BFM.
Increased CRA address to 14 bits from 12 bits.
Upgraded the Avalon-ST version to support the new IP Catalog. For
more information about the IP Catalog, refer to IP Catalog and
Parameter Editor in Introduction to Altera IP Cores.
-
Related Information
•
•
•
•
•
Introduction to Altera IP Cores
Stratix V Avalon-ST Interface for PCIe Solutions User Guide
Stratix V Avalon-MM Interface for PCIe Solutions User Guide
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Errata for Stratix V Hard IP for PCI Express in the Knowledge Base
Stratix V Hard IP for PCI Express IP Core v13.1
Table 48-4: v13.1 November 2013
Description
Impact
Support for a Avalon-MM 256-Bit Hard IP for PCI Express Gen3 ×8
with DMA is final.
-
Support for Gen2 CvP is removed.
-
Related Information
• Introduction to Altera IP Cores
• Stratix V Avalon-ST Interface for PCIe Solutions User Guide
• Stratix V Avalon-MM Interface for PCIe Solutions User Guide
Stratix V Hard IP for PCI Express IP Core Revision History
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Stratix V Hard IP for PCI Express IP Core v13.1
• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
• Errata for Stratix V Hard IP for PCI Express in the Knowledge Base
Altera Corporation
Stratix V Hard IP for PCI Express IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
Triple Speed Ethernet IP Core v15.1
Table 49-1: v15.1 November 2015
Description
Impact
Updated the ToD Clock module:
• Added a new parameter—PERIOD_CLOCK_FREQUENCY.
Updated the ToD Synchronizer module:
• Added a new parameter—SAMPLE SIZE.
• Changed the parameter value of SYNC_MODE to "Between 0 to
15".
• Changed the frequency range to 390.625 MHz.
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
Related Information
• Triple Speed Ethernet IP Core User Guide
• Errata for Triple Speed Ethernet IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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Triple Speed Ethernet IP Core v15.0
Triple Speed Ethernet IP Core v15.0
Table 49-2: v15.0 May 2015
Description
Impact
You may observe hold time violation in designs targeting the Stratix®
V, Arria® V, Cyclone® V, and Arria 10 (10AS066ES) devices in this
release.
Refer to the following errata for
more information and the
workaround: Hold Time
Violation in Triple Speed
Ethernet IP Core.
Related Information
• Introduction to Altera IP Cores
• Triple Speed Ethernet MegaCore Function User Guide
• Errata for Triple Speed Ethernet IP core in the Knowledge Base
Triple Speed Ethernet IP Core v14.0 Arria 10 Edition
Table 49-3: v14.0 Arria 10 Edition August 2014
Description
Impact
Verified in the Quartus II software v14.0 Arria 10 Edition. (Added
support for Arria 10 devices).
If you upgrade your IP core to
the Quartus II software v14.0
Arria 10 Edition , all of the
changes require that you
regenerate the IP core manually
and reconnect it in your design.
Related Information
• Introduction to Altera IP Cores
• Triple Speed Ethernet MegaCore Function User Guide
• Errata for Triple Speed Ethernet IP core in the Knowledge Base
Triple Speed Ethernet IP Core v14.0
Table 49-4: v14.0 June 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Altera Corporation
-
Triple Speed Ethernet IP Core Revision History
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Triple Speed Ethernet IP Core v13.1 Arria 10 Edition
Description
Added ECC support for M20K blocks.
Added 1588v2 support for LVDS variant.
49-3
Impact
Optional changes. If you do not
upgrade your IP core, it does not
have these new features:
Related Information
• Introduction to Altera IP Cores
• Triple Speed Ethernet MegaCore Function User Guide
• Errata for Triple Speed Ethernet IP core in the Knowledge Base
Triple Speed Ethernet IP Core v13.1 Arria 10 Edition
Table 49-5: v13.1 Arria 10 Edition December 2014
Description
Added support for Arria 10 devices.
impact
-
Related Information
• Introduction to Altera IP Cores
• Triple Speed Ethernet MegaCore Function User Guide
• Errata for Triple Speed Ethernet IP core in the Knowledge Base
Triple Speed Ethernet IP Core v13.1
Table 49-6: v13.1 November 2013
Description
Removed support for the following devices:
•
•
•
•
Impact
-
Arria GX
Cyclone II
HardCopy II, HardCopy III, and HardCopy IV
Stratix II and Stratix II GX
Added 1588v2 support for Arria V, Arria V SoC, Cyclone V, Cyclone V SoC and Stratix V devices.
Added 1588v2 support for MAC-only variants
-
Added ATX and CMU Tx PLL options for variations that include the
PCS block targeting Arria V GZ and Stratix V devices.
-
Added SyncE support by separating Tx PLL and Rx PLL reference
clock.
-
Triple Speed Ethernet IP Core Revision History
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Triple Speed Ethernet IP Core v13.1
Description
Impact
The period in nanosecond for csr registers: tx_period, rx_period,
Period, and AdjustPeriod, was changed from bit 16 to 19 to bit 16 to
24.
-
Related Information
• Introduction to Altera IP Cores
• Triple Speed Ethernet MegaCore Function User Guide
• Errata for Triple Speed Ethernet IP core in the Knowledge Base
Altera Corporation
Triple Speed Ethernet IP Core Revision History
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Turbo IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
Turbo IP Core v15.1
Table 50-1: v15.1 November 2015
Description
First release.
Impact
-
Related Information
• Turbo IP Core User Guide
• Introduction to Altera IP Cores
• Errata for Turbo IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
Video and Image Processing Suite Revision
History
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Caution: Altera removed Clipper and Test Pattern Generator IP cores from the Video and Image
Processing Suite and discontinued their support. Use Clipper II and Test Pattern Generator II
IP cores instead. For more information about Altera's current IP offering, refer to Altera's
Intellectual Property website.
Video and Image Processing Suite v15.1
Table 51-1: v15.1 November 2015
Description
Impact
Removed Clipper and Test Pattern Generator IP cores. Use Clipper II
and Test Pattern Generators II IP cores instead.
If you are using the obsoleted IP
cores, you will not get any
support from Altera.
Supports Quartus Prime Standard edition only.
–
Related Information
• Introduction to Altera IP Cores
• Video and Image Processing Suite User Guide
• Errata for the Video and Image Processing Suite in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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Video and Image Processing Suite v15.0
Video and Image Processing Suite v15.0
Table 51-2: v15.0 May 2015
Description
Impact
Updated the Input (0-3) Enable registers for the Mixer II IP core.
The 1-bit registers are changed to 2-bit registers:
• Set to bit 0 of the registers to display input 0.
• Set to bit 1 of the registers to enable consume mode.
Updated the parameter settings for the Mixer II IP core.
• Added a new parameter Pattern which enables you to select the
pattern for the background layer.
• Removed Color planes transmitted in parallel . This feature is now
default and internally handled through the hardware TCL file.
Updated the parameter settings for the Frame Buffer II IP core.
• Added support for the following parameters (these were not
supported in the previous version): Maximum ancillary packets
per frame, Interlace support, Locked rate support, Run-time
writer control, andRun-time reader control
• Removed Ready latency and Delay length (frames). These features
are fixed to 1 and internally handled through the hardware TCL file.
These changes are optional. If
you do not upgrade your IP core,
it does not have these new
features.
Updated the parameter settings for the Avalon-ST Video Monitor IP
core.
• Added new parameters: Color planes transmitted in parallel and
Pixels in parallel.
• Removed Number of color planes in sequence. You can specify
whether to transmit the planes in parallel or in series using the
Color planes transmitted in parallel parameter.
Related Information
• Introduction to Altera IP Cores
• Video and Image Processing Suite User Guide
• Errata for the Video and Image Processing Suite in the Knowledge Base
Altera Corporation
Video and Image Processing Suite Revision History
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51-3
Video and Image Processing Suite v14.1
Table 51-3: v14.1 December 2014
Description
Impact
Updated the parameters for Clocked Video Input II and Clocked Video Output II IP cores.
• Edited the function of the Use control port parameter. The control
ports will now only appear when you turn on this parameter.
• Removed the Generate Display Port output parameter.
Related Information
• Introduction to Altera IP Cores
• Video and Image Processing Suite User Guide
• Errata for the Video and Image Processing Suite in the Knowledge Base
Video and Image Processing Suite Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
Viterbi IP Core v15.0
Table 52-1: v15.0 May 2015
Description
Verified in the Quartus II software v15.0.
Impact
-
Related Information
• Viterbi IP Core User Guide
• Introduction to Altera IP Cores
• Errata for Viterbi IP core in the Knowledge Base
Viterbi IP Core v14.1
Table 52-2: v14.1 December 2014
Description
Impact
Added support for multiple codesets for Arria 10 devices.
-
Added final support for Arria 10 and MAX 10 devices
-
Related Information
• Viterbi IP Core User Guide
• Introduction to Altera IP Cores
• Errata for Viterbi IP core in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
V-Series Avalon-MM DMA for PCI Express IP
Core Revision History
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V-Series Avalon-MM DMA PCI Express IP Core v15.1
Table 53-1: v15.1 November 2015
Description
Impact
Verified in the Quartus® Prime 15.1 software release.
Related Information
• Introduction to Altera IP Cores
• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
• Errata for V-Series Avalon-MM DMA Interface for PCI Express in the Knowledge Base
V-Series Avalon-MM DMA PCI Express IP Core v14.1
Table 53-2: v14.1 December 2014
Description
Impact
Reduced Quartus II compilation warnings by 50%.
Reduces time required to vet
compilation warnings.
Added support for 128-Bit Avalon-MM RX master.
If you add this Avalon-MM RX
master to your design, you must
regenerate your IP core.
Related Information
• Introduction to Altera IP Cores
• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
• Errata for V-Series Avalon-MM DMA Interface for PCI Express in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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V-Series Avalon-MM DMA PCI Express IP Core v14.0
V-Series Avalon-MM DMA PCI Express IP Core v14.0
Table 53-3: v14.0 December 2014
Description
Impact
Made the following changes for the V-Series PCIe with Avalon-MM
DMA Interface (previously called the Avalon-MM 256-bit Hard IP for
PCI Express IP Core).
The Descriptor Controller IP
core included in the 14.0 release
is significantly different from the
• Revised programming model and optimized the performance of the one included in 13.1. Altera
recommends that you update to
Descriptor Controller.
v14.0. Altera no longer support
• Added support for either 128- or 256-bit interface to the Applica‐
v13.1.
tion Layer.
• Added support for 64-bit addressing, making address translation
unnecessary.
• Added support for optional bursting RX Master for BAR2.
• Added access to selected Configuration Space registers and link
status registers through the optional Control Register Access (CRA)
Avalon-MM slave port.
• Added parameters to enable 256 completion tags with completion
tag checking performed in Application Layer.
• Simulation support for Phase 2 and Phase 3 equalization when
requested by third-party BFM for Gen3 variants.
• Due to the many changes, the support level has reverted to prelimi‐
nary.
Related Information
• Introduction to Altera IP Cores
• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
• Errata for V-Series Avalon-MM DMA Interface for PCI Express in the Knowledge Base
V-Series Avalon-MM DMA PCI Express IP Core v15.0
Table 53-4: v15.0 May 2015
Description
Impact
Added support for downstream burst read request for a payload of size
up to 4 KBytes, if Enable burst capability for RXM BAR2 port is
turned on in the Parameter Editor. Previous maximum downstream
read request payload size was 512 bytes.
Altera Corporation
The IP core can receive and
process a burst read request for a
payload of any size supported by
the PCI Express specification (up
to 4 KBytes), if it receives such a
burst read request on the PCI
Express link.
V-Series Avalon-MM DMA for PCI Express IP Core Revision History
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V-Series Avalon-MM DMA PCI Express IP Core v15.0
53-3
Related Information
• Introduction to Altera IP Cores
• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
• Errata for V-Series Avalon-MM DMA Interface for PCI Express in the Knowledge Base
V-Series Avalon-MM DMA for PCI Express IP Core Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
XAUI PHY IP Core v14.1 Revision History
Table 54-1: v14.1 December 2014
Description
Impact
The Quartus II software v14.1 requires that you
specify a device if your IP core targets the Arria
10 device family. If you do not specify your
target Arria 10 device, the IP Upgrade tool
insists that your IP core requires upgrade, but
does not clarify the reason.
You must ensure that you specify a device for your
v13.1 Arria 10 Edition or v14.0 Arria 10 Edition IP core
variation and regenerate it in the Quartus II software
v14.1.
Added the Enable phase compensation FIFO
parameter.
-
Added the xgmii_rx_inclk port, which is
available when Enable phase compensation
FIFO is enabled.
-
Added the pll_cal_busy_i port, which
connects to the pll_cal_busy output port of
the external PLL.
-
Added a new Arria 10 SDC constraint require‐ ment. Refer to the "XAUI PHY TimeQuest SDC
Constraint" section of the Arria 10 Transceiver
PHY User Guide.
Related Information
• Altera Transceiver PHY IP Core User Guide
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
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Registered
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XAUI PHY IP Core v14.0 Arria 10 Revision History
• Arria 10 Transceiver PHY User Guide
• Errata for XAUI PHY IP Core in the Knowledge Base
• Introduction to Altera IP Cores
XAUI PHY IP Core v14.0 Arria 10 Revision History
Table 54-2: v14.0 Arria 10 Edition August 2014
Description
Impact
Added support for Arria 10 devices. To use the XAUI PHY IP core for
Arria 10 devices, you must instantiate an external transmit PLL. You
can only use the ATX PLL IP core with the XAUI PHY IP core for
Arria 10 devices.
-
Added Enable dynamic reconfiguration parameter.
-
Removed the following parameters:
-
• PLL type.
• External PMA control and configuration.
Added new port to enable connectivity with an external transmit PLL
and with the dynamic reconfiguration interface. Refer to the Arria 10
Transceiver PHY User Guide parameter and port descriptions.
-
The XAUI PHY IP core does not support NCSIM simulator. You will
see an error message during elaboration.
-
The XAUI PHY IP core does not support VHDL. You will get a
compilation error when you simulate the XAUI PHY IP core generated
in VHDL. You must generate this IP core in Verilog.
Related Information
•
•
•
•
Altera Transceiver PHY IP Core User Guide
Arria 10 Transceiver PHY User Guide
Errata for XAUI PHY IP Core in the Knowledge Base
Introduction to Altera IP Cores
XAUI PHY IP Core v14.0 Revision History
Table 54-3: v14.0 July 2014
Description
Upgraded to support the new IP Catalog. For more information about
the IP Catalog, refer to IP Catalog and Parameter Editor in Introduc‐
tion to Altera IP Cores.
Altera Corporation
Impact
-
XAUI PHY Revision History
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XAUI PHY IP Core v13.1 Revision History
54-3
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for XAUI PHY IP Core in the Knowledge Base
• Introduction to Altera IP Cores
XAUI PHY IP Core v13.1 Revision History
Table 54-4: v13.1 November 2013
Description
Verified in the Quartus II software v13.1
Impact
-
Related Information
• Altera Transceiver PHY IP Core User Guide
• Errata for XAUI PHY IP Core in the Knowledge Base
• Introduction to Altera IP Cores
XAUI PHY Revision History
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Altera Advanced SEU Detection IP Core v14.1
Table 55-1: v14.1 December 2014
Description
Impact
Added support for double-adjacent SEU sensitivity processing.
Initiates an .smh lookup for
correctable double-adjacent
EDCRC errors instead of
identifying such SEU as critical.
Added critical_clear signal to errors interface
-
Added busy signal to errors interface
For on-chip processing configu‐
ration only.
Related Information
• Advanced SEU Detection IP Core User Guide
• Errata for other IP cores in the Knowledge Base
Altera Dual Configuration v14.0 Update 2
Table 55-2: v14.0 Update 2 September 2014
Description
Initial release.
Impact
-
Related Information
• MAX 10 FPGA Configuration User Guide
• Errata for other IP cores in the Knowledge Base
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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Altera EMR Unloader IP Core v14.1
Altera EMR Unloader IP Core v14.1
Table 55-3: v14.1 December 2014
Description
Fixed an issue with synchronization the of CRCERROR signal, which
comes from the EDCRC circuitry that the internal oscillator drives.
Impact
-
Related Information
• Advanced SEU Detection IP Core User Guide
• Errata for other IP cores in the Knowledge Base
ALTERA_FP_FUNCTIONS v15.0
Table 55-4: v15.0 May 2015
Description
Impact
Added new functions: Multiply Add, Multiply Accumulate,
Accumulate, and Scalar Product..
-
Added support for range reduction option for appropriate trigono‐
metric functions.
-
Added Manually Specify DSP Registers option on the Performance
tab that shows a GUI and allows you to target specific registers on
Arria 10 devices. applies to Add, Subtract, Multiply Add functions
-
Added target option on the Performance tab to allow you to constrain both latency and frequency
Related Information
• Floating-Point Megafunctions User Guide
• Errata for other IP cores in the Knowledge Base
Altera Corporation
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ALTERA_FP_MATRIX_MULT v14.1
55-3
ALTERA_FP_MATRIX_MULT v14.1
Table 55-5: v14.1 December 2014
Description
Impact
Added support for Arria 10 device hard floating-point blocks.
Changed reset port. It is no longer optional and is always present
Only for new IP cores.
Removed option to add an enable port
Changed performance. Specify twice the number of memory blocks
compared to previous version for the equivalent performance
Only for new IP cores. Any
existing IP cores continue to
have the same signals even when
you edit and regenerate the IP
core.
Changed the signals to use Avalon-ST interfaces.
Changed reset to active low
Related Information
• Floating-Point Megafunctions User Guide
• Errata for other IP cores in the Knowledge Base
Altera OCT IP Core v14.0 Arria 10 Edition
Table 55-6: v14.0 Arria 10 Edition August 2014
Description
Impact
• Changed signal names
• Added user mode OCT
Table 55-7: Signal Name Changes
Old Name
New Name
Notes
core_rzqin_export
rzqin
-
core_series_termination_
control_expor
oct_#_series_termination_control
-
core_parallel_termination_
control_export
oct_#_parallel_termination_
control
-
Related Information
• Altera OCT Megafunction User Guide
• Errata for other IP cores in the Knowledge Base
Other IP Cores Product Revision History
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Altera GPIO IP Core v14.0 Arria 10 Edition
Altera GPIO IP Core v14.0 Arria 10 Edition
Table 55-8: v14.0 Arria 10 Edition August 2014
Description
Impact
Changed signal names
-
Table 55-9: Signal Name Changes
Old Name
New Name
core_ck_fr_in_export
ck_fr_in
core_ck_fr_out_export
ch_fr_out
core_ck_hr_in_export
ch_hr_in
core_ck_hr_out_export
ch_hr_out
core_dout_export
dout
core_din_export
din
core_oe_export
oe
core_pad_io_export
pad_io
core_pad_io_b_export
pad_io_b
core_aclr_export
aclr
core_sclr_export
sclr
core_cke_export
cke
core_ck_export
ck
core_ck_in_export
ck_in
core_ck_out_export
ck_out
core_ck_fr_export
ck_fr
core_ck_hr_export
ck_hr
core_pad_in_export
pad_in
core_pad_in_b_export
pad_in_b
core_pad_out_export
pad_out
core_pad_out_b_export
pad_out_b
core_aset_export
aset
core_sset_export
sset
Altera Corporation
Notes
Other IP Cores Product Revision History
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Altera GPIO Lite IP Core v14.0 Update 2
55-5
Related Information
• Altera GPIO Megafunction User Guide
• Errata for other IP cores in the Knowledge Base
Altera GPIO Lite IP Core v14.0 Update 2
Table 55-10: v14.0 Update 2 September 2014
Description
Impact
Initial release.
Related Information
• MAX 10 General Purpose I/O User Guide
• Errata for other IP cores in the Knowledge Base
Altera Modular ADC IP Core v14.0 Update 2
Table 55-11: v14.0 Update 2 September 2014
Description
Initial release.
Impact
-
Related Information
• MAX 10 Analog to Digital Converter User Guide
• Errata for other IP cores in the Knowledge Base
Altera LVDS SERDES IP Core v14.1
Table 55-12: v14.1 December 2014
Description
Added internal PLL additional clock export parameter
Impact
-
Related Information
• Altera LVDS SERDES Megafunction User Guide
• Errata for other IP cores in the Knowledge Base
Other IP Cores Product Revision History
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Altera LVDS SERDES IP Core v14.0 Arria 10 Edition
Altera LVDS SERDES IP Core v14.0 Arria 10 Edition
Table 55-13: v14.0 Arria 10 Edition August 2014
Description
Impact
Added feature that creates .sdc file for generated designs (previously
only for example designs)
-
Added support for external PLL mode
-
Added option to clock TX core registers using reference clock
-
Related Information
• Altera LVDS SERDES Megafunction User Guide
• Errata for other IP cores in the Knowledge Base
Altera PHYLite for Parallel Interfaces IP Core v15.1
Table 55-14: v15.1 November 2015
Description
Impact
Added new debug kit example design using Nios II for dynamic reconfigu‐
rations.
-
Added parameter, Copy parameters from another group, to allow
copying parameters from one DQ group to another DQ group.
-
Added new parameters group, Group <x> Dynamic Reconfiguration
Timing Settings, for users to select dynamic reconfiguration algorithm for
timing analysis.
-
Added parameter, OCT enable size, for users to specify the interpolator
clock cycle delay required to ensure OCT is turned on before sampling any
input data.
-
Added parameters, Inter Symbol Interference of the Read Channel and
Inter Symbol Interference of the Write Channel, for users to specify the
Inter Symbol Interference values for read and write channels for timing
analysis.
-
Related Information
• Introduction to Altera IP Cores
• Altera PHYLite for Parallel Interfaces IP Core User Guide
• Errata for other IP cores in the Knowledge Base
Altera Corporation
Other IP Cores Product Revision History
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Altera PHYLite for Memory IP Core v14.1
55-7
Altera PHYLite for Memory IP Core v14.1
Table 55-15: v14.1 December 2014
Description
Impact
Added internal PLL additional clock export parameter
-
Added setup delay constraint timing parameters in the Group tabs in
the parameter editor
-
Related Information
• Altera PHYLite for Memory Megafunction User Guide
• Errata for other IP cores in the Knowledge Base
Altera PHYLite for Memory IP Core v14.0 Arria 10 Edition
Table 55-16: v14.0 Arria 10 Edition August 2014
Description
Impact
Added dynamic reconfiguration
-
Added I/O standard and OCT settings
-
Added complementary strobe type
-
Changed pll_locked port name to interface_locked
-
Related Information
• Altera PHYLite for Memory Megafunction User Guide
• Errata for other IP cores in the Knowledge Base
Altera On-Chip Flash IP Core v15.1
Table 55-17: v15.1 November 2015
Description
Impact
Added parallel data interface support for 10M02 devices; the maximum –
frequency is 7.25 MHz.
Related Information
• Introduction to Altera IP Cores
• MAX 10 User Flash Memory User Guide
• Errata for other IP cores in the Knowledge Base
Other IP Cores Product Revision History
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Altera On-Chip Flash IP Core v14.1
Altera On-Chip Flash IP Core v14.1
Table 55-18: v14.1 December 2014
Description
Added new parameters:
Impact
-
• Data interface parameter.
• Read burst count parameter. Adjusts the maximum burst count for
Incrementing read mode. Also autoadjusts burstcount bus width.
• Serial data interfaces
• Flash Memory. Indicates the address mapping for each sector and
adjusts the Access Mode for each sector individually
Replaced Dual Images parameter with Configuration Scheme and
Configuration Mode parameters which includes all supported
configuration modes. Use CFM as UFM during single image configu‐
ration mode without memory initialization.
Fixed a bug, which allows you to adjust the Read burst count from 1 to
2 or 4 while using WrappingRead burst mode.
Related Information
• MAX 10 User Flash Memory User Guide
• Errata for other IP cores in the Knowledge Base
Altera On-Chip Flash IP Core v14.0 Update 2
Table 55-19: v14.0 Update 2 September 2014
Description
Initial release.
Impact
-
Related Information
• MAX 10 User Flash Memory User Guide
• Errata for other IP cores in the Knowledge Base
Altera Soft LVDS IP Core v14.0 Update 2
Table 55-20: v14.0 Update 2 September 2014
Description
Initial release.
Altera Corporation
Impact
-
Other IP Cores Product Revision History
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Altera Voltage Sensor IP Core v15.0
55-9
Related Information
• MAX 10 High-Speed LVDS I/O User Guide
• Errata for other IP cores in the Knowledge Base
Altera Voltage Sensor IP Core v15.0
Table 55-21: v15.0 May 2015
Description
Initial release.
Impact
-
Related Information
• Altera Voltage Sensor IP Core User Guide
• Errata for other IP cores in the Knowledge Base
Arria 10 Native Fixed Point DSP IP Core v14.1
Table 55-22: v14.1 December 2014
Description
Initial release. Only supports Arria 10 device family.
Impact
-
Related Information
• Arria 10 Native Fixed Point DSP IP Core User Guide
• Errata for other IP cores in the Knowledge Base
Internal Oscillator IP Core v14.0 Update 2
Table 55-23: v14.0 Update 2 September 2014
Description
Initial release.
Impact
-
Related Information
• MAX 10 Clocking and PLL User Guide
• Errata for other IP cores in the Knowledge Base
Other IP Cores Product Revision History
Send Feedback
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RAM: 1-port and RAM: 2-port v14.0 Arria 10 Edition
RAM: 1-port and RAM: 2-port v14.0 Arria 10 Edition
Table 55-24: v14.0 Arria 10 Edition August 2014
Description
Impact
Changed GUI. When upgrading, you lose any value in Memory Initial Mode > File name. For the work around, refer to the Knowledge Base.
Related Information
• Internal Memory (ROM and RAM) User Guide
• Errata for other IP cores in the Knowledge Base
SCFIFO and DCFIFO IP Cores v15.1
Table 55-25: v15.1 November 2015
Description
Added a new GUI parameter, enable_ecc, for Arria 10 devices. The
enable_ecc parameter specifies whether to enable the error correction
code (ECC) feature that corrects single-bit errors and double-adjacent
bit errors, and detects triple-adjacent bit errors at the output of the
memory.
Impact
This change is optional. If you
do not upgrade your IP core, it
does not have this new feature.
Added a new signal, eccstatus that indicates the ECC status of the
data.
Related Information
• Introduction to Altera IP Cores
• SCFIFO and DCFIFO IP Cores User Guide
• Errata for other IP cores in the Knowledge Base
SLD Hub Controller System v14.1
Table 55-26: v14.1 December 2014
Description
Enhanced the register map
Impact
The pre-v14.1 and v14.1 register
maps are similar. Pre v14.1
register maps work unchanged
with v14.1 hardware.
Related Information
Errata for other IP cores in the Knowledge Base
Altera Corporation
Other IP Cores Product Revision History
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If a release note is not available for a specific IP core version, the IP core has no changes in that version.
Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
Related Information
Altera Complete Design Suite Update Release Notes
Transceiver PHY Reset Controller IP Core v15.1 Revision History
Table 56-1: v15.1 November 2015
Description
In ACDS 15.1, the Quartus Prime software includes a modification to Arria 10 designs using
transceivers that controls and sequences rx_analogreset and tx_analogreset to transceiver
channels. This new sequencing logic is inserted into the design during Quartus Prime compila‐
tion.
Impact
—
The Transceiver PHY Reset Controller IP core adds a new parameter (T_TX_ANALOGRESET)
for Arria 10 devices. This change requires a modification to all instances of the Transceiver PHY
Reset Controller IP core.
Configure the Transceiver PHY Reset Controller IP core with the following parameters for most
designs:
T_TX_ANALOGRESET (tx_analogreset duration) : 70000
R_RX_ANALOGRESET (rx_analogreset duration) : 70000
T_TX_DIGITALRESET (tx_digitalreset duration) : 70000
These settings ensure that the new underlying reset sequencer logic has sufficient time to accept
the reset inputs from the Transceiver PHY Reset Controller IP core.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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Transceiver PHY Reset Controller IP Core v14.1 Revision History
Transceiver PHY Reset Controller IP Core v14.1 Revision History
Table 56-2: v14.1 December 2014
Description
Impact
Added an optional port pll_cal_busy. To enable pll_cal_busy select Enable pll_cal_busy
input port parameter under the TX Channel option in the Reset Controller IP Core parameter
editor. If not enabled, then by default, this port is connected to 1'b0.
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Transceiver PHY Reset Controller IP Core v14.0 Arria 10 Revision History
Table 56-3: v14.0 Arria 10 August 2014
Description
Impact
Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores.
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Transceiver PHY Reset Controller IP Core v13.0 Arria 10 Revision History
Table 56-4: v13.0 Arria 10 December 2013
Description
Initial release for Arria 10 devices.
Impact
-
Related Information
• Arria 10 Transceiver PHY User Guide
• Errata for Transceiver IP Cores in the Knowledge Base
• Introduction to Altera IP Cores
Altera Corporation
Other Transceiver IP Cores Product Revision History
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