RL78/L12 Datasheet

RL78/L12 Datasheet
Datasheet
RL78/L12
R01DS0157EJ0100
Rev.1.00
2013.01.31
RENESAS MCU
Integrated LCD controller/driver, True Low Power Platform (as low as 62.5 µA/MHz, and 0.64 µA for RTC +
LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
1.
1.1
OUTLINE
Features
Ultra-Low Power Technology
• 1.6 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
µA
• Halt (RTC + LVD): 0.64 µA
• Supports snooze
• Operating: 62.5 µA/MHz
• LCD operating current (Capacitor split method): 0.12
µA
• LCD operating current (Internal voltage boost
method): 0.63 µA (VDD = 3.0 V)
16-bit RL78 CPU Core
• Delivers 31 DMIPS at maximum operating frequency
of 24 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
LCD Controller/Driver
• Up to 35 seg x 8 com or 39 seg x 4 com
• Supports capacitor split method, internal voltage
boost method and resistance division method
• Supports waveform types A and B
• Supports LCD contrast adjustment (16 steps)
• Supports LCD blinking
Data Memory Access (DMA) Controller
• Up to 2 fully programmable channels
• Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
2
• Up to 1 × I C multi-master
• Up to 2 × CSI/SPI (7-, 8-bit)
• Up to 1 × UART (7-, 8-, 9-bit)
• Up to 1 × LIN
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval Timer: 12-bit, 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Code Flash Memory
• Density: 8 KB to 32 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with flash shield window function
Rich Analog
• ADC: Up to 10 channels, 10-bit resolution, 2.1 µs
conversion time
• Supports 1.6 V
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Data Flash Memory
• Data flash with background operation
• Data flash size: 2 KB size
• Erase cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock frequency detection
• ADC self-test
RAM
• 1 KB and 1.5 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 24 MHz with +/− 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (−20°C to 85°C)
• Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, 8
MHz, 4 MHz & 1 MHz
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
R01DS0157EJ0100 Rev.1.00
2013.01.31
General Purpose I/O
• 5V tolerant, high-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• Standard: −40 °C to +85 °C
Package Type and Pin Count
From 7mm x 7mm to 12mm x 12mm
QFP: 32, 44, 48, 52, 64
QFN: 64
Page 1 of 77
RL78/L12
1. OUTLINE
{ ROM, RAM capacities
Flash
Data
ROM
flash
32 KB
2 KB
RAM
1.5
RL78/L12
32 pins
44 pins
48 pins
52 pins
64 pins
R5F10RBC
R5F10RFC
R5F10RGC
R5F10RJC
R5F10RLC
R5F10RBA
R5F10RFA
R5F10RGA
R5F10RJA
R5F10RLA
R5F10RB8
R5F10RF8
R5F10RG8
R5F10RJ8
−
Note
KB
16 KB
2 KB
1
KB
8KB
2 KB
1
KB
Note
Note
Note
In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash
function is used.
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 2 of 77
RL78/L12
1.2
1. OUTLINE
Ordering Information
• Flash memory version (lead-free product)
Pin count
Package
Part Number
32 pins
32-pin plastic LQFP (7 × 7)
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
44 pins
44-pin plastic LQFP (10 × 10)
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
48 pins
48-pin plastic LQFP
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
(fine pitch) (7 × 7)
52 pins
52-pin plastic LQFP (10 × 10)
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
64 pins
64-pin plastic WQFN (8 × 8)
R5F10RLAANB, R5F10RLCANB
64-pin plastic LQFP (fine pitch)
R5F10RLAAFB, R5F10RLCAFB
(10 × 10)
64-pin plastic LQFP (12 × 12)
R01DS0157EJ0100 Rev.1.00
2013.01.31
R5F10RLAAFA, R5F10RLCAFA
Page 3 of 77
RL78/L12
1.3
1.3.1
1. OUTLINE
Pin Configuration (Top View)
32-pin products
COM0
COM1
COM2
COM3
COMEXP/SEG0
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
• 32-pin plastic LQFP (7 × 7)
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3 4 5 6 7 8
P30/TI01/TO01/SEG19
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P14/ANI19/SEG32
P13/ANI18/TI00/SEG31
P12/SO00/TXD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RXD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 4 of 77
RL78/L12
1.3.2
1. OUTLINE
44-pin products
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
• 44-pin plastic LQFP (10 × 10)
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P120/ANI17/SEG25
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
P141/TI00/PCLBUZ1/SEG26
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 5 of 77
RL78/L12
1.3.3
1. OUTLINE
48-pin products
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
• 48-pin plastic LQFP (fine pitch) (7 × 7)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P70/KR0/SEG16
P32/TI03/TO03/INTP4/KR1/SEG17
P31/INTP3/RTC1HZ/KR2/SEG18
P30/TI01/TO01/KR3/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
P10/SCK00/TI07/TO07/SEG28/(INTP1)
P140/TO00/PCLBUZ0/SEG27
P141/TI00/PCLBUZ1/SEG26
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 6 of 77
RL78/L12
1.3.4
1. OUTLINE
52-pin products
P51/TI06/TO06/SEG8
P50/INTP5/SEG7/(PCLBUZ0)
P17/SO01/TI02/TO02/SEG6
P16/SI01/INTP2/SEG5
P15/SCK01/INTP1/SEG4
COM7/SEG3
COM6/SEG2
COM5/SEG1
COM4/COMEXP/SEG0
COM3
COM2
COM1
COM0
• 52-pin plastic LQFP (10 × 10)
39 38 37 36 35 34 33 32 31 30 29 28 27
24
P32/TI03/TO03/INTP4/SEG17
P144/ANI22/SEG35
43
23
P31/INTP3/RTC1HZ/KR2/SEG18
P143/ANI21/SEG34
44
22
P30/TI01/TO01/KR3/SEG19
P142/ANI20/SEG33
45
21
P125/VL3
P14/ANI19/SEG32
46
20
VL4
P13/ANI18/SEG31
47
19
VL2
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
48
18
VL1
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
49
17
P126/CAPL
P10/SCK00/TI07/TO07/SEG28/(INTP1)
50
16
P127/CAPH
P140/TO00/PCLBUZ0/SEG27
51
15
P61/SDAA0/SEG20
P141/TI00/PCLBUZ1/SEG26
52
14
P60/SCLA0/SEG21
VDD
VSS
8 9 10 11 12 13
REGC
6 7
P121/X1
5
P122/X2/EXCLK
3 4
P123/XT1
2
P40/TOOL0
1
P137/INTP0
42
P124/XT2/EXCLKS
P70/KR0/SEG16
P145/ANI23/SEG36
RESET
25
P42/TI05/TO05/SEG23
P71/KR1/SEG15
41
P120/ANI17/SEG25
26
P20/ANI0/AVREFP
P41/ANI16/TI04/TO04/SEG24
P21/ANI1/AVREFM
40
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 7 of 77
RL78/L12
1.3.5
1. OUTLINE
64-pin products
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
P51/TI06/TO06/SEG8
P52/INTP6/SEG9
P53/TI07/TO07/SEG10/(INTP1)
P54/SEG11/(TI02)/(TO02)/(INTP2)
• 64-pin plastic WQFN (8 × 8)
exposed die pad
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P147/SEG38
P146/SEG37
P145/ANI23/SEG36
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6 7 8 9 10 11 12 13 14 15 16
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P42/TI05/TO05/SEG23
P43/INTP7/SEG22
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS
VDD
EVDD
1 2 3 4 5
P74/SEG12
P73/KR3/SEG13
P72/KR2/SEG14
P71/KR1/SEG15
P70/KR0/SEG16
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
Cautions 1. Make EVSS pin the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD pins and connect the VSS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 8 of 77
RL78/L12
1. OUTLINE
• 64-pin plastic LQFP (fine pitch) (10 × 10)
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
P51/TI06/TO06/SEG8
P52/INTP6/SEG9
P53/TI07/TO07/SEG10/(INTP1)
P54/SEG11/(TI02)/(TO02)/(INTP2)
• 64-pin plastic LQFP (12 × 12)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P147/SEG38
P146/SEG37
P145/ANI23/SEG36
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6 7 8 9 10 11 12 13 14 15 16
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P42/TI05/TO05/SEG23
P43/INTP7/SEG22
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS
VDD
EVDD
1 2 3 4 5
P74/SEG12
P73/KR3/SEG13
P72/KR2/SEG14
P71/KR1/SEG15
P70/KR0/SEG16
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
Cautions 1. Make EVSS pin the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD pins and connect the VSS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 9 of 77
RL78/L12
1.4
1. OUTLINE
Pin Identification
ANI0, ANI1,
P120 to P127:
Port 12
ANI16 to ANI23:
Analog Input
P130, P137:
Port 13
AVREFM:
Analog Reference
P140 to P147:
Port 14
Voltage Minus
PCLBUZ0, PCLBUZ1:
Programmable Clock
AVREFP:
CAPH, CAPL:
Analog Reference
Output/Buzzer Output
Voltage Plus
REGC:
Regulator Capacitance
Capacitor for LCD
RESET:
Reset
RTC1HZ:
Real-time Clock Correction Clock
COM0 to COM7,
COMEXP:
LCD Common Output
EVDD:
Power Supply for Port
RxD0:
Receive Data
EVSS:
Ground for Port
SCK00, SCK01:
Serial Clock Input/Output
EXCLK:
External Clock Input
SCLA0:
Serial Clock Input/Output
(Main System Clock)
SDAA0:
Serial Data Input/Output
External Clock Input
SEG0 to SEG38:
LCD Segment Output
(Subsystem Clock)
SI00, SI01:
Serial Data Input
Interrupt Request From
SO00, SO01:
Serial Data Output
Peripheral
TI00 to TI07:
Timer Input
KR0 to KR3:
Key Return
TO00 to TO07:
Timer Output
P10 to P17:
Port 1
TOOL0:
Data Input/Output for Tool
P20, P21:
Port 2
TOOLRxD, TOOLTxD:
Data Input/Output for External Device
P30 to P32:
Port 3
TxD0:
Transmit Data
P40 to P43:
Port 4
VDD:
Power Supply
P50 to P54:
Port 5
VL1 to VL4:
LCD Power Supply
P60, P61:
Port 6
VSS:
Ground
P70 to P74:
Port 7
X1, X2:
Crystal Oscillator (Main System Clock)
XT1, XT2:
Crystal Oscillator (Subsystem Clock)
EXCLKS:
INTP0 to INTP7:
R01DS0157EJ0100 Rev.1.00
2013.01.31
(1 Hz) Output
Page 10 of 77
RL78/L12
1.5
1. OUTLINE
Block Diagram
1.5.1
32-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P13
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
ch3
ch4
2
ANI0/P20, ANI1/P21
2
ANI18/P13, ANI19/P14
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
P30
PORT 4
P40
A/D CONVERTER
ch5
AVREFP/P20
AVREFM/P21
ch6
PORT 6
REAL-TIME
CLOCK
<R>
2
P60, P61
ch7
TI07/TO07/P10
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
PORT 12
RL78
CPU
CORE
2
P126, P127
2
P121, P122
CODE FLASH MEMORY
PORT 13
P137
PORT 14
P140
DATA FLASH MEMORY
WINDOW
WATCHDOG
TIMER
BUZZER OUTPUT
PCLBUZ0/P140
SEG0, SEG4 to SEG6,
SEG19 to SEG21,
SEG27 to SEG32
COM0 to COM3, COMEXP
VL1, VL2, VL4
CAPH
CAPL
13
5
LCD
CONTROLLER/
DRIVER
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
SERIAL ARRAY
UNIT0 (2ch)
VDD
RxD0/P11
TxD0/P12
UART0
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
SDAA0/P61
SCLA0/P60
3
KR0/P12 to KR2/P10
KR3/P140
RAM SPACE
FOR LCD DATA
VSS
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
DIRECT MEMORY
ACCESS CONTROL
SYSTEM
CONTROL
HIGH-SPEED
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
RESET
X1/P121
X2/EXCLK/P122
ON-CHIP
OSCILLATOR
CRC
VOLTAGE
REGULATOR
REGC
INTP0/P137
2
BCD
ADJUSTMENT
Remark
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
INTERRUPT
CONTROL
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 11 of 77
RL78/L12
1.5.2
1. OUTLINE
44-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
2
ch4
ANI0/P20, ANI1/P21
ANI17/P120, ANI18/P13,
ANI19/P14
ANI20/P142, ANI21/P143
3
A/D CONVERTER
ch5
2
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
AVREFP/P20
AVREFM/P21
ch6
PORT 6
REAL-TIME
CLOCK
RTC1HZ/P31
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
PORT 12
RL78
CPU
CORE
COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
22
9
LCD
CONTROLLER/
DRIVER
P121 to P124
PORT 13
PORT 14
P137
4
P140 to P143
2
PCLBUZ0/P140,
PCLBUZ1/P141
3
KR0/P12 to KR2/P10
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
UART0
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCLA0/P60
P120, P125 to P127
4
KR3/P140
RAM SPACE
FOR LCD DATA
RxD0/P11
TxD0/P12
SDAA0/P61
4
DATA FLASH MEMORY
SERIAL ARRAY
UNIT0 (2ch)
SCK01/P15
SI01/P16
SO01/P17
P60, P61
CODE FLASH MEMORY
WINDOW
WATCHDOG
TIMER
SEG0 to SEG6,
SEG17 to SEG21,
SEG25 to SEG34
2
ch7
TI07/TO07/P10
<R>
P40
VSS
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
CSI01
TOOL0/P40
ON-CHIP DEBUG
DIRECT MEMORY
ACCESS CONTROL
SYSTEM
CONTROL
HIGH-SPEED
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
RESET
X1/P121
X2/EXCLK/P122
XT1/P123
ON-CHIP
CRC
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
INTP0/P137
BCD
ADJUSTMENT
Remark
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 12 of 77
RL78/L12
1.5.3
1. OUTLINE
48-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
2
ch4
TI04/TO04/P41
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI22/P144
4
A/D CONVERTER
ch5
3
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
2
P40, P41
PORT 5
P50
AVREFP/P20
AVREFM/P21
ch6
PORT 6
2
P60, P61
ch7
TI07/TO07/P10
PORT 7
RTC1HZ/P31
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
<R>
12- BIT INTERVAL
TIMER
PORT 12
RL78
CPU
CORE
COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
26
9
LCD
CONTROLLER/
DRIVER
4
P120, P125 to P127
4
P121 to P124
CODE FLASH MEMORY
PORT 13
P137
DATA FLASH MEMORY
PORT 14
WINDOW
WATCHDOG
TIMER
SEG0 to SEG7,
SEG16 to SEG21,
SEG24 to SEG35
P70
5
P140 to P144
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
3
KR1/P32 to KR3/P30
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
KR0/P70
RAM SPACE
FOR LCD DATA
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P11
TxD0/P12
UART0
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
VSS
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
SDAA0/P61
SCLA0/P60
TOOL0/P40
ON-CHIP DEBUG
DIRECT MEMORY
ACCESS CONTROL
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
CRC
INTP0/P137
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
INTP5/P50
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 13 of 77
RL78/L12
1.5.4
1. OUTLINE
52-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
2
ch4
TI04/TO04/P41
4
A/D CONVERTER
TI05/TO05/P42
ch5
TI06/TO06/P51
ch6
TI07/TO07/P10
ch7
RTC1HZ/P31
<R>
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI23/P145
4
12- BIT INTERVAL
TIMER
COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
30
9
LCD
CONTROLLER/
DRIVER
RL78
CPU
CORE
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
3
P40 to P42
PORT 5
2
P50, P51
PORT 6
2
P60, P61
PORT 7
2
P70, P71
4
P120, P125 to P127
4
P121 to P124
CODE FLASH MEMORY
PORT 13
P137
DATA FLASH MEMORY
PORT 14
6
P140 to P145
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
2
KR0/P70, KR1/P71
2
KR2/P31, KR3/P30
RAM SPACE
FOR LCD DATA
POWER ON RESET/
VOLTAGE
DETECTOR
SERIAL ARRAY
UNIT0 (2ch)
VDD
RxD0/P11
TxD0/P12
UART0
SCK00/P10
SO10/P17
SI00/P11
SO00/P12
CSI00
SCK10/P15
SI10/P16
P10 to P17
PORT 12
WINDOW
WATCHDOG
TIMER
SEG0 to SEG8,
SEG15 to SEG21,
SEG23 to SEG36
8
AVREFP/P20
AVREFM/P21
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 1
VSS
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
CSI01
DIRECT MEMORY
ACCESS CONTROL
TOOL0/P40
ON-CHIP DEBUG
CRC
SYSTEM
CONTROL
SDAA0/P61
SCLA0/P60
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
INTP0/P137
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
INTP5/P50
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 14 of 77
RL78/L12
1.5.5
1. OUTLINE
64-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P54)
ch2
TI03/TO03/P32
ch3
2
TI04/TO04/P41
ch4
TI05/TO05/P42
ch5
4
A/D CONVERTER
TI06/TO06/P51
ch6
TI07/TO07/P53
ch7
RTC1HZ/P31
<R>
4
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI23/P145
12- BIT INTERVAL
TIMER
39
COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
9
LCD
CONTROLLER/
DRIVER
RL78
CPU
CORE
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
SDAA0/P61
SCLA0/P60
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
4
P40 to P43
PORT 5
5
P50 to P54
PORT 6
2
P60, P61
PORT 7
5
P70 to P74
4
P120, P125 to P127
4
P121 to P124
P130
P137
PORT 13
DATA FLASH MEMORY
PORT 14
8
P140 to P147
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
SERIAL ARRAY
UNIT0 (2ch)
UART0
PORT 2
CODE FLASH MEMORY
RAM SPACE
FOR LCD DATA
RxD0/P11
TxD0/P12
P10 to P17
PORT 12
WINDOW
WATCHDOG
TIMER
SEG0 to SEG38
8
AVREFP/P20
AVREFM/P21
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 1
VDD,
EVDD
KR0/P70 to
KR3/P73
4
POR/LVD
CONTROL
VSS, TOOLRxD/P11,
EVSS TOOLTxD/P12
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
DIRECT MEMORY
ACCESS CONTROL
SYSTEM
CONTROL
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
CRC
INTP0/P137
2
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P53),
INTP2/P16(INTP2/P54)
INTP3/P31,
INTP4/P32
INTP5/P50
INTP6/P52(INTP6/P140)
INTP7/P43(INTP7/P141)
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 15 of 77
RL78/L12
1.6
1. OUTLINE
Outline of Functions
Caution
This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H.
(1/2)
Item
Code flash memory (KB)
32-pin
44-pin
48-pin
52-pin
64-pin
R5F10RBx
R5F10RFx
R5F10RGx
R5F10RJx
R5F10RLx
8 to 32
8 to 32
8 to 32
8 to 32
16, 32
Data flash memory (KB)
RAM (KB)
2
1, 1.5
Memory space
Main system
clock
2
Note 1
1, 1.5
2
Note 1
1, 1.5
2
Note 1
1, 1.5
2
Note 1
Note 1
1, 1.5
1 MB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD =
1.6 to 1.8 V
High-speed on-chip
oscillator clock
HS (high-speed main) operation: 1 to 24 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-voltage main) operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
−
XT1 (crystal) oscillation , external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
Internal oscillation
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.04167 μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
• Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean
operation), etc.
Instruction set
I/O port
Timer
Total
20
29
33
37
47
CMOS I/O
15
22
26
30
39
CMOS input
3
5
5
5
5
CMOS output
−
−
−
−
1
N-ch open-drain I/O
(EVDD tolerance)
2
2
2
2
2
16-bit timer
8 channels
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer (IT)
1 channel
Timer output
RTC output
Notes 1.
8 channels (with 1 channel remote control output function)
4 channels
5 channels
6 channels
8 channels (PWM outputs: 7
(PWM outputs: (PWM outputs: (PWM outputs:
Note 2
Note 2
Note 2
3
)
4
)
5
)
−
Note 2
)
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz or )
In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data
flash function is used.
<R>
2.
The number of PWM outputs varies depending on the setting of channels in use (the number of
masters and slaves).
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 16 of 77
RL78/L12
1. OUTLINE
(2/2)
Item
Clock output/buzzer output
32-pin
44-pin
48-pin
52-pin
64-pin
R5F10RBx
R5F10RFx
R5F10RGx
R5F10RJx
R5F10RLx
1
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz,
32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
4 channels
Serial interface
•
2
I C bus
9 channels
10 channels
10 channels
CSI: 2 channel/UART (LIN-bus supported): 1 channel
1 channel
LCD controller/driver
7 channels
1 channel
1 channel
1 channel
1 channel
Internal voltage boosting method, capacitor split method, and external resistance
division
method are switchable.
Segment signal output
13
Common signal output
4
Note 1
22 (18)
26 (22)
Note 1
30 (26)
4 (8)
Multiplier and
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
divider/multiply-accumulator
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
Note 1
39 (35)
Note 1
Note 1
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored interrupt Internal
23
23
23
23
23
sources
4
6
7
7
9
External
Key interrupt
•
Reset
<R>
4
Power-on-reset circuit
Reset by RESET pin
•
Internal reset by watchdog timer
•
Internal reset by power-on-reset
•
Internal reset by voltage detector
•
Internal reset by illegal instruction execution
•
Internal reset by RAM parity error
•
Internal reset by illegal-memory access
• Power-on-reset:
Note 2
1.51 ±0.04 V
• Power-down-reset: 1.50 ±0.04 V
Voltage detector
• Rising edge : 1.67 V to 4.06 V (14 stages)
• Falling edge : 1.63 V to 3.98 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Notes 1.
2.
The values in parentheses are the number of signal outputs when 8 com is used.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or
on-chip debug emulator.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 17 of 77
RL78/L12
<R>
2.
2. ELECTRICAL SPECIFICATIONS
ELECTRICAL
SPECIFICATIONS
Cautions 1. The RL78/L12 microcontrollers have an on-chip debug function, which is provided for
development and evaluation.
Do not use the on-chip debug function in products
designated for mass production, because the guaranteed number of rewritable times of the
flash memory may be exceeded when this function is used, and product reliability therefore
cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the
on-chip debug function is used.
<R>
2. With products not provided with an EVDD, or EVSS pin, replace EVDD with VDD, or replace EVSS
with VSS.
3. The pins mounted depend on the product. Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 18 of 77
RL78/L12
2.1
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/3)
Parameter
Symbols
Supply voltage
Conditions
Ratings
Unit
VDD
VDD = EVDD
−0.5 to +6.5
V
EVDD
VDD = EVDD
−0.5 to +6.5
V
VSS
−0.5 to +0.3
V
EVSS
−0.5 to +0.3
V
REGC pin input voltage VIREGC
−0.3 to +2.8
REGC
V
and −0.3 to VDD +0.3
Input voltage
VI1
VI2
−0.3 to EVDD +0.3
P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127, P140 to P147
Note 1
and −0.3 to VDD +0.3
V
Note 2
−0.3 to EVDD +0.3
P60, P61 (N-ch open-drain)
and −0.3 to VDD +0.3
VI3
P20, P21, P121 to P124, P137, EXCLK,
VO1
P10 to P17, P30 to P32, P40 to P43,
−0.3 to VDD +0.3
V
Note 2
Note 2
V
EXCLKS, RESET
Output voltage
P50 to P54, P60, P61, P70 to P74, P120,
−0.3 to EVDD +0.3
and −0.3 to VDD +0.3
V
Note 2
P125 to P127, P130, P140 to P147
Analog input voltage
VO2
P20, P21
VAI1
ANI16 to ANI23
−0.3 to VDD +0.3
−0.3 to AVREF(+) +0.3
VAI2
−0.3 to AVREF(+) +0.3
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μ F).
absolute maximum rating of the REGC pin.
V
Notes 2, 3
−0.3 to VDD +0.3 and
ANI0, ANI1
<R>
Notes 1.
V
−0.3 to EVDD +0.3 and
<R>
<R>
Note 2
V
Notes 2, 3
This value regulates the
Do not use this pin with voltage applied to it.
2.
Must be 6.5 V or lower.
3.
Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
the port pins.
<R>
2.
AVREF(+) : + side reference voltage of the A/D converter.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 19 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C) (2/3)
Parameter
<R>
LCD voltage
Symbols
Ratings
Unit
VL1 voltage
Note
−0.3 to +2.8
V
VL2
VL2 voltage
Note
−0.3 to +6.5
V
VL3
VL3 voltage
Note
−0.3 to +6.5
V
VL4 voltage
Note
−0.3 to +6.5
V
−0.3 to +6.5
V
−0.3 to +6.5
V
VL1
VL4
Conditions
Note
VL5
CAPL, CAPH voltage
VL6
COM0 to COM7, SEG0 to SEG38, COMEXP output
voltage
<R>
Note
This value only indicates the absolute maximum ratings when applying voltage to the V L1 , V L2 , V L3 ,
and V L4 pins; it does not mean that applying voltage to these pins is recommended.
When using the
internal voltage boosting method or capacitance split method, connect these pins to V SS via a
capacitor (0.47 μ F ± 30%) and connect a capacitor (0.47 μ F ± 30%) between the CAPL and CAPH
pins.
<R>
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 20 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C) (3/3)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
P10 to P17, P30 to P32,
Ratings
Unit
−40
mA
−70
mA
−100
mA
P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127,
P130, P140 to P147
Total of all pins
P10 to P14, P40 to P43, P120,
−170 mA
P130, P140 to P147
P15 to P17, P30 to P32,
P50 to P54, P70 to P74,
P125 to P127
IOH2
Per pin
P20, P21
Total of all pins
Output current, low
IOL1
Per pin
P10 to P17, P30 to P32,
−0.5
mA
−1
mA
40
mA
70
mA
100
mA
1
mA
2
mA
−40 to +85
°C
−65 to +150
°C
P40 to P43, P50 to P54, P60,
P61, P70 to P74, P120,
P125 to P127, P130,
P140 to P147
Total of all pins
P10 to P14, P40 to P43, P120,
170 mA
P130, P140 to P147
P15 to P17, P30 to P32,
P50 to P54, P60, P61,
P70 to P74, P125 to P127
IOL2
Per pin
P20, P21
Total of all pins
Operating ambient
TA
temperature
In normal operation mode
In flash memory programming mode
Storage temperature
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 21 of 77
RL78/L12
<R>
2.2
2. ELECTRICAL SPECIFICATIONS
Oscillator Characteristics
2.2.1
X1, XT1 oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Resonator
Recommended
Conditions
MIN.
TYP.
MAX.
Unit
Circuit
X1 clock
Ceramic
oscillation
resonator/
Note
frequency (fX)
VSS X1
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
1.6 V ≤ VDD <1.8 V
1.0
4.0
MHz
35
kHz
X2
Rd
crystal resonator
C2
C1
Crystal resonator
XT1 clock
32
VSS XT2
oscillation
Note
frequency (fXT)
32.768
XT1
Rd
C4
C3
Note Indicates only oscillator characteristics.
Refer to 2.4 AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, XT1 oscillator,wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
•
Keep the wiring length as short as possible.
•
Do not cross the wiring with the other signal lines.
•
Do not route the wiring near a signal line through which a high fluctuating current flows.
•
Always make the ground point of the oscillator capacitor the same potential as VSS.
•
Do not ground the capacitor to a ground pattern through which a high current flows.
•
Do not fetch signals from the oscillator.
2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release,
check the X1 clock oscillation stabilization time using the oscillation stabilization time
counter status register (OSTC) by the user. Determine the oscillation stabilization time of the
OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently
evaluating the oscillation stabilization time with the resonator to be used.
3. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption,
and is more prone to malfunction due to noise than the X1 oscillator. Particular care is
therefore required with the wiring method when the XT1 clock is used.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 22 of 77
RL78/L12
2.2.2
2. ELECTRICAL SPECIFICATIONS
On-chip oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Oscillators
Parameters
High-speed on-chip oscillator
clock frequency
Conditions
MAX.
Unit
1
24
MHz
1.8 V≤VDD≤5.5 V
−1
+1
%
1.6 V≤VDD≤1.8 V
−5
+5
%
1.8 V≤VDD≤5.5 V
−1.5
+1.5
%
1.6 V≤VDD≤1.8 V
−5.5
+5.5
%
fIH
MIN.
TYP.
Note 1
−20 to +85 °C
High-speed on-chip oscillator
clock frequency accuracy
Note 2
−40 to −20 °C
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
Low-speed on-chip oscillator
−15
+15
%
clock frequency accuracy
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to
2 of HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to 2.4 AC Characteristics for instruction
execution time.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 23 of 77
RL78/L12
2.3
2. ELECTRICAL SPECIFICATIONS
DC Characteristics
2.3.1
Pin characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output current,
Note 1
high
IOH1
Conditions
MIN.
TYP.
Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127, P130, P140 to P147
Total of P10 to P14, P40 to P43, P120,
P130, P140 to P147
Note 2
(When duty = 70%
)
IOH2
MAX.
Unit
−10.0
mA
Note 3
4.0 V ≤ EVDD ≤ 5.5 V
−40.0
mA
2.7 V ≤ EVDD < 4.0 V
−8.0
mA
1.8 V ≤ EVDD < 2.7 V
−4.0
mA
1.6 V ≤ EVDD < 1.8 V
−2.0
mA
4.0 V ≤ EVDD ≤ 5.5 V
−60.0
mA
2.7 V ≤ EVDD < 4.0 V
−15.0
mA
1.8 V ≤ EVDD < 2.7 V
−8.0
mA
1.6 V ≤ EVDD < 1.8 V
−4.0
mA
Total of all pins
Note 2
(When duty = 70%
)
−100.0
mA
P20, P21
−0.1
mA
Total of P15 to P17, P30 to P32,
P50 to P54, P70 to P74, P125 to P127
Note 2
(When duty = 70%
)
Per pin
Total of all pins
Note 2
)
(When duty = 70%
Notes 1.
(1/5)
1.6 V ≤ VDD ≤ 5.5 V
Note 3
−1.5
mA
Value of current at which the device operation is guaranteed even if the current flows from the VDD,
EVDD pins to an output pin.
2.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(50 × 0.01) = −14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
3.
Do not exceed the total current value.
Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 24 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output current,
Note 1
low
IOL1
Conditions
(2/5)
MIN.
TYP.
Per pin for P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P70 to P74, P120, P125 to P127, P130,
P140 to P147
Per pin for P60, P61
Total of P10 to P14, P40 to P43,
P120, P130, P140 to P147
Note 2
(When duty = 70%
)
Total of P15 to P17, P30 to P32,
P50 to P54, P60, P61, P70 to P74,
P125 to P127
Note 2
)
(When duty = 70%
mA
Note 3
Note 3
mA
4.0 V ≤ EVDD ≤ 5.5 V
70.0
2.7 V ≤ EVDD < 4.0 V
15.0
mA
1.8 V ≤ EVDD < 2.7 V
9.0
mA
1.6 V ≤ EVDD < 1.8 V
4.5
mA
4.0 V ≤ EVDD ≤ 5.5 V
80.0
mA
2.7 V ≤ EVDD < 4.0 V
35.0
mA
1.8 V ≤ EVDD < 2.7 V
20.0
mA
mA
10.0
mA
Total of all pins
Note 2
(When duty = 70%
)
150.0
mA
P20, P21
0.4
Per pin for
Total of all pins
Note 2
)
(When duty = 70%
Notes 1.
Unit
20.0
15.0
1.6 V ≤ EVDD < 1.8 V
IOL2
MAX.
1.6 V ≤ VDD ≤ 5.5 V
Note 3
5.0
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the EVSS and VSS pin.
2.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
3.
Remark
Do not exceed the total current value.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
the port pins.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 25 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
P10 to P17, P30 to P32, P40 to P43,
(3/5)
MIN.
TYP.
MAX.
Unit
Normal input buffer 0.8EVDD
EVDD
V
TTL input buffer
2.2
EVDD
V
2.0
EVDD
V
1.50
EVDD
V
P50 to P54, P70 to P74, P120,
high
P125 to P127, P140 to P147
VIH2
P10, P11, P15, P16
4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer
3.3 V ≤ EVDD < 4.0 V
TTL input buffer
1.6 V ≤ EVDD < 3.3 V
Input voltage,
VIH3
P20, P21
0.7VDD
VDD
V
VIH4
P60, P61
0.7EVDD
EVDD
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8VDD
VDD
V
VIL1
P10 to P17, P30 to P32, P40 to P43,
Normal input buffer
0
0.2EVDD
V
TTL input buffer
0
0.8
V
0
0.5
V
0
0.32
V
P50 to P54, P70 to P74, P120,
low
P125 to P127, P140 to P147
VIL2
P10, P11, P15, P16
4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer
3.3 V ≤ EVDD < 4.0 V
TTL input buffer
1.6 V ≤ EVDD < 3.3 V
Caution
Remark
VIL3
P20, P21
0
0.3VDD
V
VIL4
P60, P61
0
0.3EVDD
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
The maximum value of VIH of P10, P12, P15, P17 is EVDD, even in the N-ch open-drain mode.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 26 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output voltage,
VOH1
high
Conditions
(4/5)
MIN.
P10 to P17, P30 to P32, P40 to P43,
4.0 V ≤ EVDD ≤ 5.5 V, EVDD−1.5
P50 to P54, P70 to P74, P120,
IOH1 = −10 mA
P125 to P127, P130, P140 to P147
4.0 V ≤ EVDD ≤ 5.5 V, EVDD−0.7
TYP.
MAX.
Unit
V
V
IOH1 = −3.0 mA
2.7 V ≤ EVDD ≤ 5.5 V, EVDD−0.6
V
IOH1 = −2.0 mA
1.8 V ≤ EVDD ≤ 5.5 V, EVDD−0.5
IOH1 = −1.5 mA
V
1.6 V ≤ EVDD < 5.5 V, EVDD−0.5
V
IOH1 = −1.0 mA
VOH2
P20, P21
1.6 V ≤ VDD ≤ 5.5 V,
VDD−0.5
V
IOH2 = −100 μ A
Output voltage,
VOL1
low
P10 to P17, P30 to P32, P40 to P43,
4.0 V ≤ EVDD ≤ 5.5 V,
P50 to P54, P70 to P74, P120,
IOL1 = 20 mA
P125 to P127, P130, P140 to P147
4.0 V ≤ EVDD ≤ 5.5 V,
1.3
V
0.7
V
0.6
V
0.4
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
0.4
V
IOL1 = 8.5 mA
2.7 V ≤ EVDD ≤ 5.5 V,
IOL1 = 3.0 mA
2.7 V ≤ EVDD ≤ 5.5 V,
IOL1 = 1.5 mA
1.8 V ≤ EVDD ≤ 5.5 V,
IOL1 = 0.6 mA
1.6 V ≤ EVDD < 5.5 V,
IOL1 = 0.3 mA
VOL2
P20, P21
1.6 V ≤ VDD ≤ 5.5 V,
IOL2 = 400 μ A
VOL3
P60, P61
4.0 V ≤ EVDD ≤ 5.5 V,
IOL3 = 15.0 mA
4.0 V ≤ EVDD ≤ 5.5 V,
IOL3 = 5.0 mA
2.7 V ≤ EVDD ≤ 5.5 V,
IOL3 = 3.0 mA
1.8 V ≤ EVDD ≤ 5.5 V,
IOL3 = 2.0 mA
1.6 V ≤ EVDD < 5.5 V,
IOL3 = 1.0 mA
Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 27 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Input leakage
Symbol
ILIH1
Conditions
P10 to P17, P30 to P32,
(5/5)
MIN.
TYP.
MAX.
Unit
VI = EVDD
1
μA
1
μA
1
μA
10
μA
VI = EVSS
−1
μA
−1
μA
−1
μA
−10
μA
P40 to P43, P50 to P54, P60,
current, high
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIH2
P20, P21, P137, RESET
VI = VDD
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
P10 to P17, P30 to P32,
P40 to P43, P50 to P54, P60,
current, low
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIL2
P20, P21, P137, RESET
VI = VSS
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pll-up
RU1
VI = EVSS
resistance
RU2
SEGxx port
2.4 V ≤ EVDD = VDD ≤ 5.5 V
10
20
100
kΩ
1.6 V ≤ EVDD = VDD < 2.4 V
10
30
100
kΩ
10
20
100
kΩ
Ports other than above
(Except for P60, P61,
and P130)
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 28 of 77
RL78/L12
2.3.2
2. ELECTRICAL SPECIFICATIONS
Supply current characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Supply
current
Symbol
Note 1
IDD1
Conditions
Operating
mode
HS
(high-speed
main) mode
fIH = 24 MHz
Note 3
Basic
VDD = 5.0 V
operation VDD = 3.0 V
Normal
VDD = 5.0 V
operation VDD = 3.0 V
Note 5
fIH = 16 MHz
LS
(low-speed
main) mode
fIH = 8 MHz
Note 3
(1/3)
MIN.
Normal
VDD = 5.0 V
operation VDD = 3.0 V
TYP.
MAX.
Unit
1.5
mA
1.5
mA
3.3
5.0
3.3
5.0
mA
mA
2.5
3.7
mA
2.5
3.7
mA
Normal
VDD = 3.0 V
operation VDD = 2.0 V
1.2
1.8
mA
1.2
1.8
mA
Normal
VDD = 3.0 V
operation VDD = 2.0 V
1.2
1.7
mA
1.2
1.7
mA
Normal
Square wave input
operation Resonator connection
2.8
4.4
mA
3.0
4.6
mA
Normal
Square wave input
operation Resonator connection
2.8
4.4
mA
3.0
4.6
mA
Note 2
Normal
Square wave input
operation Resonator connection
1.8
2.6
mA
1.8
2.6
mA
Note 2
Normal
Square wave input
operation Resonator connection
1.8
2.6
mA
1.8
2.6
mA
Normal
Square wave input
operation Resonator connection
1.1
1.7
mA
1.1
1.7
mA
Normal
Square wave input
operation Resonator connection
1.1
1.7
mA
1.1
1.7
mA
Note 4
Normal
Square wave input
operation Resonator connection
3.5
4.9
μA
3.6
5.0
μA
Note 4
Normal
Square wave input
operation Resonator connection
3.6
4.9
μA
3.7
5.0
μA
Note 4
Normal
Square wave input
operation Resonator connection
3.7
5.5
μA
3.8
5.6
μA
Normal
Square wave input
operation Resonator connection
3.8
6.3
μA
3.9
6.4
μA
Normal
Square wave input
operation Resonator connection
4.1
7.7
μA
4.2
7.8
μA
Note 3
Note 5
fIH = 4 MHz
LV
(low-voltage
Note
main) mode
Note 3
5
HS
(high-speed
main) mode
Note 5
Note 2
fMX = 20 MHz
,
VDD = 5.0 V
Note 2
fMX = 20 MHz
,
VDD = 3.0 V
fMX = 10 MHz
,
VDD = 5.0 V
fMX = 10 MHz
,
VDD = 3.0 V
LS
(low-speed
main) mode
Note 5
Note 2
fMX = 8 MHz
,
VDD = 3.0 V
Note 2
fMX = 8 MHz
,
VDD = 2.0 V
Subsystem
clock
operation
fSUB = 32.768 kHz
TA = −40°C
fSUB = 32.768 kHz
TA = +25°C
fSUB = 32.768 kHz
TA = +50°C
fSUB = 32.768 kHz
Note 4
TA = +70°C
fSUB = 32.768 kHz
TA = +85°C
Note 4
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 29 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral
operation current (except for back ground operation (BGO)). However, not including the current flowing
<R>
into the watchdog timer, 12-bit interval timer, A/D converter, LVD circuit, I/O port, on-chip
pull-up/pull-down resistors, and LCD controller driver.
<R>
2. When high-speed on-chip oscillator and subsystem clock are stopped.
When real-time clock is
stopped.
<R>
3. When high-speed system clock and subsystem clock are stopped. When real-time clock is stopped.
<R>
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time clock,
serial interface IICA, multiplier and divider/multiply-accumulator, and DMA contoroller are stopped.
When AMPHS1 = 1 (Ultra-low power consumption oscillation).
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 [email protected] MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 [email protected] MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 30 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Supply
current
Symbol
IDD2
Note 2
Conditions
HALT
mode
Note 1
HS
(high-speed
main) mode
fIH = 24 MHz
Note 7
fIH = 16 MHz
LS
(low-speed
main) mode
fIH = 8 MHz
(2/3)
MIN.
Note 4
Note 4
Note 4
TYP.
MAX.
Unit
mA
VDD = 5.0 V
0.44
1.28
VDD = 3.0 V
0.44
1.28
mA
VDD = 5.0 V
0.40
1.00
mA
VDD = 3.0 V
0.40
1.00
mA
VDD = 3.0 V
260
530
μA
VDD = 2.0 V
260
530
μA
VDD = 3.0 V
420
640
μA
VDD = 2.0 V
420
640
μA
Note 7
LV
(low-voltage
main) mode
fIH = 4 MHz
Note 4
Note 7
HS
(high-speed
main) mode
Note 7
Note 3
fMX = 20 MHz
,
VDD = 5.0 V
Note 3
fMX = 20 MHz
,
VDD = 3.0 V
Note 3
fMX = 10 MHz
,
VDD = 5.0 V
Note 3
fMX = 10 MHz
,
VDD = 3.0 V
LS
(low-speed
main) mode
Note 7
Note 3
fMX = 8 MHz
,
VDD = 3.0 V
fSUB = 32.768 kHz
STOP
Note 8
mode
1.00
mA
1.17
mA
Square wave input
0.19
0.60
mA
Resonator connection
0.26
0.67
mA
Square wave input
0.19
0.60
mA
Resonator connection
0.26
0.67
mA
Square wave input
95
330
μA
Resonator connection
145
380
μA
μA
μA
Note 5
Square wave input
0.31
0.57
μA
Resonator connection
0.50
0.76
μA
Note 5
Square wave input
0.37
0.57
μA
Resonator connection
0.56
0.76
μA
Square wave input
0.46
1.17
μA
Resonator connection
0.65
1.36
μA
Note 5
Note 5
Note 5
Square wave input
0.57
1.97
μA
Resonator connection
0.76
2.16
μA
Square wave input
0.85
3.37
μA
Resonator connection
1.04
3.56
μA
TA = −40°C
0.17
0.50
μA
TA = +25°C
0.23
0.50
μA
TA = +50°C
0.32
1.10
μA
TA = +70°C
0.43
1.90
μA
TA = +85°C
0.71
3.30
μA
TA = +85°C
Note 6
IDD3
0.28
0.45
330
TA = +70°C
fSUB = 32.768 kHz
Square wave input
Resonator connection
380
TA = +50°C
fSUB = 32.768 kHz
mA
95
TA = +25°C
fSUB = 32.768 kHz
mA
1.17
145
TA = −40C
fSUB = 32.768 kHz
1.00
0.45
Square wave input
,
VDD = 2.0 V
Subsystem
clock
operation
0.28
Resonator connection
Resonator connection
Note 3
fMX = 8 MHz
Square wave input
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 31 of 77
RL78/L12
Notes 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral
<R>
operation current (except for back ground operation (BGO)). However, not including the current flowing
into the watchdog timer, 12-bit interval timer, A/D converter, LVD circuit, I/O port, on-chip
pull-up/pull-down resistors, and LCD controller driver.
2.
During HALT instruction execution by flash memory.
<R>
3.
When high-speed on-chip oscillator and subsystem clock are stopped.
<R>
4.
When real-time clock and
multiplier and divider/multiply-accumulator are stopped.
When high-speed system clock and subsystem clock are stopped. When real-time clock and multiplier
and divider/multiply-accumulator are stopped.
5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When
<R>
high-speed on-chip oscillator and high-speed system clock are stopped.
When real-time clock, serial
interface IICA, multiplier and divider/multiply-accumulator, and DMA contoroller are stopped.
The
values below the MAX. column include the leakage current.
<R>
6.
When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped.
When real-time clock, serial interface IIC, multiplier and divider/multiply-accumulator, and DMA
contoroller are stopped. The values below the MAX. column include the leakage current.
7.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode:
2.7 V ≤ VDD ≤ 5.5 [email protected] MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 [email protected] MHz to 16 MHz
<R>
8.
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 [email protected] MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V ≤ VDD ≤ 5.5 [email protected] MHz to 4 MHz
Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25°C
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 32 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
RTC operating
Symbol
Notes 1, 2
IRTC
Conditions
(3/3)
MIN.
TYP.
fMAIN is stopped
0.08
Note 12
fMAIN is stopped
0.08
Note 12
MAX.
Unit
μA
μA
current
12-bit inteval
IIT
Notes 1, 2
timer current
μA
IWDT
Notes 2, 3
fIL = 15 kHz, fMAIN is stopped
0.24
A/D converter
operating
current
IADC
Note 4
When conversion
at maximum speed
Normal mode, AVREFP = VDD = 5.0 V
1.3
1.7
mA
Low voltage mode, AVREFP = VDD = 3.0 V
0.5
0.7
mA
A/D converter
reference
voltage current
IADREF
75.0
μA
Temperature
sensor
operating
current
ITMPS
75.0
μA
LVD operating
ILVD
0.08
μA
Watchdog timer
operating
current
Note 5
current
BGO operating
IBGO
Notes 6, 7
2.00
12.20
mA
2.00
12.20
mA
0.04
0.2
μA
1.12
3.7
μA
0.63
2.2
μA
0.12
0.5
μA
0.50
0.60
mA
1.20
1.44
mA
0.70
0.84
mA
current
Flash
IFSP
Note 8
self-programming
operating current
LCD operating
ILCD1
current
Notes 9, 10
External resistance division method
VDD = EDD = 5.0 V
VL4 = 5.0 V
ILCD2
Note 9
Internal voltage boosting method
VDD = EDD = 5.0 V
VL4 = 5.1 V (VLCD = 12H)
VDD = EDD = 3.0 V
VL4 = 3.0 V (VLCD = 04H)
ILCD3
Note 9
Capacitor split method
VDD = EDD = 3.0 V
VL4 = 3.0 V
SNOOZE
ISNOZ
ADC operation
The mode is performed
Note 11
operating
The A/D conversion operations are
current
performed, Low voltage mode, AVREFP = VDD
= 3.0 V
CSI/UART operation
(Note, Caution and Remark are lisited on the next page)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 33 of 77
RL78/L12
<R>
<R>
<R>
<R>
<R>
2. ELECTRICAL SPECIFICATIONS
Notes 1. Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The
TYP. value of the current value of the RL78/L12 is the sum of the TYP. values of either IDD1 or IDD2, and
IRTC, when the real-time clock operates in operation mode or HALT mode. The IDD1 and IDD2 MAX.
values also include the real-time clock operating current. However, IDD2 subsystem clock operation
includes the operational current of the real-time clock.
2. When high-speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the watchdog timer (including the operating current of the 15 kHz low-speed
on-chip oscillator). The supply current value of the RL78/L12 is the sum of IDD1, IDD2 or IDD3 and IWDT
when the watchdog timer operates.
4. Current flowing only to the A/D converter. The supply current value of the RL78/L12 is the sum of IDD1
or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
5. Current flowing only to the LVD circuit. The supply current value of the RL78/L12 is the sum of IDD1,
IDD2 or IDD3 and ILVD when the LVD circuit operates.
6. Current flowing only when the BGO operates. The supply current value of the RL78/L12 is the sum of
IDD1 or IDD2 and IBGO when the BGO operates in an operation mode.
7. Current flowing during data flash programming (not including the CPU operating current). The TYP.
value indicates the averaged current for repeated writing and erasing of contiguous 1 KB on the flash
memory. The MAX. value indicates the inrush current that flows during flash programming.
8. Current flowing during code flash programming (not including the CPU operating current). The TYP.
value indicates the averaged current for repeated writing and erasing of contiguous 1 KB on the flash
memory. The MAX. value indicates the inrush current that flows during flash programming.
9. Current flowing only to the LCD controller/driver (VDD pin). The supply current value of the RL78/L12
microcontrollers is the sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1,
or IDD2) when the LCD controller/driver operates in an operation mode or HALT mode. Not including the
current that flows through the LCD panel.
The TYP. value and MAX. value are following conditions.
• Set 20 pins as a segment function, all lighting
• When fSUB is selected for system clock, LCD clock = 128 Hz (LCDC0 = 07H)
• 4-Time-Slice, 1/3 Bias Method
10. Not including the current that flows through the external divider resistor when the external resistance
division method is used.
11. For shift time to the SNOOZE mode, see 19.3.3 SNOOZE mode in the RL78/L12 User’s Manual:
Hardware (R01UH0330E).
12. Add 200 nA when using fIL.
Remarks 1.
2.
3.
4.
fIL: Low-speed on-chip oscillator clock frequency
fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
fCLK: CPU/peripheral hardware clock frequency
Temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 34 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
2.4
AC Characteristics
2.4.1
Basic operation
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
MIN.
LS (low-speed
main) mode
Subsystem clock (fSUB)
operation
1.8 V ≤ VDD ≤ 5.5 V
0.125
1.8 V ≤ VDD ≤ 5.5 V
28.5
In the self
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167
programming main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
mode
External main system clock
frequency
fEX
tEXH, tEXL
TO00 to TO07 output frequency
fTO
PCLBUZ0, PCLBUZ1 output
frequency
Interrupt input high-level width,
low-level width
fPCL
tINTH,
tINTL
Key interrupt input low-level width tKR
RESET low-level width
Remark
μs
1
μs
1
μs
1
μs
31.3
μs
1
1
μs
μs
0.25
1
μs
LS (low-speed
main) mode
1.8 V ≤ VDD ≤ 5.5 V
0.125
1
μs
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
2.7 V ≤ VDD ≤ 5.5 V
24
ns
1.8 V ≤ VDD < 2.7 V
60
ns
1.6 V ≤ VDD < 1.8 V
tTIH,
tTIL
Unit
1
1.8 V ≤ VDD ≤ 5.5 V
tEXHS,
tEXLS
TI00 to TI07 input high-level
width, low-level width
30.5
MAX.
LV (low voltage
main) mode
fEXS
External main system clock input
high-level width, low-level width
TYP.
Main system HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167
clock (fMAIN) main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
operation
LV (low voltage 1.6 V ≤ VDD ≤ 5.5 V 0.25
main) mode
HS (high-speed main)
mode
120
ns
13.7
μs
1/fMCK+10
ns
4.0 V ≤ EVDD ≤ 5.5 V
12
MHz
2.7 V ≤ EVDD < 4.0 V
8
MHz
2.4 V ≤ EVDD < 2.7 V
4
MHz
LV (low voltage main)
mode
1.6 V ≤ EVDD ≤ 5.5 V
2
MHz
LS (low-speed main)
mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
HS (high-speed main)
mode
4.0 V ≤ EVDD ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD < 4.0 V
8
MHz
MHz
2.4 V ≤ EVDD < 2.7 V
4
LV (low voltage main)
mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD < 1.8 V
2
MHz
LS (high-speed main)
mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
μs
μs
INTP0
1.6 V ≤ VDD ≤ 5.5 V
1
INTP1 to INTP7
1.6 V ≤ EVDD ≤ 5.5 V
1
1.8 V ≤ EVDD ≤ 5.5 V
250
ns
1.6 V ≤ EVDD < 1.8 V
1
μs
μs
KR0 to KR3
tRSL
10
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n =
0 to 7))
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 35 of 77
RL78/L12
<R>
2. ELECTRICAL SPECIFICATIONS
AC Timing Test Points
VIH
VIH
Test points
VIL
VIL
External System Clock Timing
1/fEX
tEXL
tEXH
0.7VDD (MIN.)
EXCLK
0.3VDD (MAX.)
TI/TO Timing
tTIH
tTIL
TI00 to TI07
1/fTO
TO00 to TO07
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP7
Key Interrupt Input Timing
tKR
KR0 to KR3
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 36 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
RESET Input Timing
tRSL
RESET
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 37 of 77
RL78/L12
2.5
2.5.1
2. ELECTRICAL SPECIFICATIONS
Peripheral Functions Characteristics
Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
Note 1
MIN.
2.4 V ≤ EVDD = VDD ≤ 5.5 V
Transfer rate
Theoretical value of the
MAX.
LS
MIN.
Note 2
MAX.
LV
MIN.
Note 3
Unit
MAX.
fMCK/6
fMCK/6
fMCK/6
Note 4
Note 4
Note 4
4.0
1.3
0.7
Mbps
fMCK/6
fMCK/6
bps
Note 4
Note 4
1.3
0.7
Mbps
fMCK/6
bps
bps
maximum transfer rate
fMCK = fCLK
Note 5
1.8 V ≤ EVDD = VDD ≤ 5.5 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK
Note 5
1.6 V ≤ EVDD = VDD ≤ 5.5 V
Note 4
Theoretical value of the
0.7
Mbps
maximum transfer rate
fMCK = fCLK
Note 5
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User's device
RL78/L12
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
<R>
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode is max. 9600 bps, min. 4800 bps.
<R>
5. fCLK in each operating mode is as below.
HS (high-speed main) mode: fCLK = 24 MHz
LS (low-speed main) mode:
fCLK = 8 MHz
LV (low-voltage main) mode: fCLK = 4 MHz
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 38 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
q: UART number (q = 0), g: PIM and POM number (g = 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 39 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(2) During communication at same potential (CSI mode) (master mode (fMCK/2, fMCK/4), SCKp... internal
clock output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
tKCY1
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
167
Note 4
250
Note 4
Note 1
MAX.
1.8 V ≤ EVDD ≤ 5.5 V
LS
Note 2
MIN.
500
Note 4
500
Note 4
500
Note 4
MAX.
1.6 V ≤ EVDD ≤ 5.5 V
SCKp high-/low-level width
tKH1,
4.0 V ≤ EVDD ≤ 5.5 V
tKL1
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
LV
MIN.
MAX.
1000
ns
1000
Note 4
ns
1000
Note 4
ns
1000
Note 4
ns
tKCY1/2
tKCY1/2
−12
−50
−100
tKCY1/2
tKCY1/2
tKCY1/2
−18
−50
−100
tKCY1/2
tKCY1/2
tKCY1/2
−38
−50
−100
tKCY1/2
tKCY1/2
−50
−100
1.6 V ≤ EVDD ≤ 5.5 V
Unit
Note 4
tKCY1/2
1.8 V ≤ EVDD ≤ 5.5 V
Note 3
ns
ns
ns
ns
tKCY1/2
ns
−100
SIp setup time (to SCKp↑)
tSIK1
Note 5
4.0 V ≤ EVDD ≤ 5.5 V
44
110
220
ns
2.7 V ≤ EVDD ≤ 5.5 V
44
110
220
ns
2.4 V ≤ EVDD ≤ 5.5 V
75
110
220
ns
110
220
ns
220
ns
19
19
ns
19
19
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
SIp hold time (from SCKp↑) tKSI1
Note 6
2.4 V ≤ EVDD ≤ 5.5 V
19
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
Delay time from SCKp↓ to
SOp output
tKSO1
Note 7
C = 30 pF 2.4 V ≤ EVDD ≤ 5.5 V
Note 8
19
25
1.8 V ≤ EVDD ≤ 5.5 V
25
25
25
25
1.6 V ≤ EVDD ≤ 5.5 V
<R>
ns
25
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. For CSI00, set a cycle of 2/fMCK or longer. For CSI01, set a cycle of 4/fMCK or longer.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
7. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
8. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 40 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
Note 4
tKCY2
4.0 V ≤ EVDD ≤ 5.5 V 20 MHz < fMCK
8/fMCK
fMCK ≤ 20 MHz
6/fMCK
2.7 V ≤ EVDD < 4.0 V 16 MHz < fMCK
8/fMCK
fMCK ≤ 16 MHz
6/fMCK
2.4 V ≤ EVDD < 2.7 V 12 MHz < fMCK
8/fMCK
fMCK ≤ 12 MHz
6/fMCK
Note 1
MAX.
LS
MIN.
Note 2
MAX.
6/fMCK
tKH2,
tKL2
4..0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD < 4.0 V
2.4 V ≤ EVDD < 2.7 V
Unit
MAX.
6/fMCK
ns
ns
6/fMCK
6/fMCK
ns
ns
6/fMCK
1.8 V ≤ EVDD < 2.4 V
width
MIN.
Note 3
ns
6/fMCK
1.6 V ≤ EVDD < 1.8 V
SCKp high-/low-level
LV
6/fMCK
ns
6/fMCK
ns
6/fMCK
ns
ns
tKCY2/2
tKCY2/2
tKCY2/2
−7
−7
−7
tKCY2/2
tKCY2/
tKCY2/2
−8
−-8
−8
tKCY2/2
tKCY2/2
tKCY2/2
−18
−18
−18
tKCY2/2
tKCY2/2
−18
−18
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
ns
ns
ns
tKCY2/2
ns
−66
SIp setup time
(to SCKp↑)
tSIK2
2.7 V ≤ EVDD ≤ 5.5 V
Note 5
2.4 V ≤ EVDD < 2.7 V
1/fMCK
1/fMCK
1/fMCK
+20
+30
+30
1/fMCK
1/fMCK
1/fMCK
+30
+30
+30
1/fMCK
1/fMCK
+30
+30
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
ns
ns
1/fMCK
ns
+40
SIp hold time
(from SCKp↑)
tKSI2
2.4 V ≤ EVDD ≤ 5.5 V
Note 6
1/fMCK
1/fMCK
1/fMCK
+31
+31
+31
1/fMCK
1/fMCK
+31
+31
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
ns
ns
1/fMCK+
ns
250
Delay time from SCKp↓
to SOp output
tKSO2
Note 7
C = 30 pF
4.0 V ≤ EVDD ≤ 5.5 V
Note 8
2.7 V ≤ EVDD < 4.0 V
2.4 V ≤ EVDD < 2.7 V
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
2/fMCK
2/fMCK
2/fMCK
+44
+110
+110
2/fMCK
2/fMCK
2/fMCK
+44
+110
+110
2/fMCK
2/fMCK
2/fMCK
+75
+110
+110
2/fMCK
2/fMCK
+110
+110
2/fMCK+
ns
ns
ns
ns
ns
220
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 41 of 77
RL78/L12
<R>
2. ELECTRICAL SPECIFICATIONS
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
7. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
8. C is the load capacitance of the SOp output lines.
<R>
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0),
n: Channel number (n = 0, 1), g: PIM number (g = 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 42 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78/L12
SIp
SO
SOp
SI
User's device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01)
m: Unit number, n: Channel number (mn = 00, 01)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 43 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (dedicated baud rate generator
output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
Note 1
LS
Note 2
LV
Note 3
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate
reception
4.0 V ≤ EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Theoretical value of the
fMCK/6
fMCK/6
fMCK/6
Note 4
Notes 4, 5
Notes 4, 5
4.0
1.3
0.7
Mbps
fMCK/6
fMCK/6
fMCK/6
bps
Note 4
Notes 4, 5
Notes 4, 5
4.0
1.3
0.7
Mbps
fMCK/6
fMCK/6
fMCK/6
bps
Note 4
Notes 4, 5
Notes 4, 5
4.0
1.3
0.7
Mbps
fMCK/6
fMCK/6
bps
Notes 4, 5
Notes 4, 5
1.3
0.7
bps
maximum transfer rate
fMCK = fCLK
Note 6
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK
Note 6
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK
Note 6
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
Mbps
maximum transfer rate
fMCK = fCLK
<R>
Note 6
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
5. Use it with EVDD≥Vb.
<R>
6. fCLK in each operating mode is as below.
HS (high-speed main) mode: fCLK = 24 MHz
LS (low-speed main) mode:
fCLK = 8 MHz
LV (low-voltage main) mode: fCLK = 4 MHz
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32-pin
to 52-pin products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
3.
Vb[V]: Communication line voltage
q: UART number (q = 0), g: PIM and POM number (g = 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 44 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (dedicated baud rate generator
output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
Note 1
LS
Note 2
LV
Note 3
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate
transmission 4.0 V ≤ EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Notes
Notes
4, 5
4, 5
Notes bps
4, 5
Theoretical value of the
2.8
2.8
2.8
maximum transfer rate
Note 6
Note 6
Note 6
Notes
Notes
5, 7
5, 7
Theoretical value of the
1.2
1.2
1.2
maximum transfer rate
Note 8
Note 8
Note 8
Notes
Notes
5, 9,
5, 9,
5, 9,
10
10
10
Theoretical value of the
0.43
0.43
0.43 Mbps
maximum transfer rate
Note 11
Note 11
Note 11
Mbps
Cb = 50 pF, Rb = 1.4 kΩ,
Vb = 2.7 V
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Notes bps
5, 7
Mbps
Cb = 50 pF, Rb = 2.7 kΩ
Vb = 2.3 V
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Notes bps
Cb = 50 pF, Rb = 5.5 kΩ
Vb = 1.6 V
1.8 V ≤ EVDD < 3.3 V,
Notes
1.6 V ≤ Vb ≤ 2.0 V
Notes bps
5, 9,
5, 9,
10
10
Theoretical value of the
0.43
0.43 Mbps
maximum transfer rate
Note 11
Note 11
Cb = 50 pF, Rb = 5.5 kΩ,
Vb = 1.6 V
<R>
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.2
Vb )} × 3
[bps]
1
− {−Cb × Rb × ln (1 −
Transfer rate × 2
2.2
Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
5. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
6. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 45 of 77
RL78/L12
Notes 7.
2. ELECTRICAL SPECIFICATIONS
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.0
Vb )} × 3
[bps]
1
− {−Cb × Rb × ln
Transfer rate × 2
2.0
(1 − Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
8.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
9.
Use it with EVDD ≥ Vb.
10. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ EVDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1.5
Vb )} × 3
[bps]
1.5
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
11. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 10 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32-pin
to 52-pin products)/EDD tolerance (64-pin products)) mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
Rb[Ω]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
<R>
m: Unit number, n: Channel number (mn = 00, 01))
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
User's device
RL78/L12
RxDq
R01DS0157EJ0100 Rev.1.00
2013.01.31
Tx
Page 46 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32-pin
to 52-pin products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
Rb[Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
q: UART number (q = 0), g: PIM and POM number (g = 1)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 47 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(5) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock
output, corresponding CSI00 only)
(TA = −40 to +85°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
tKCY1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 1
MAX.
LS
MIN.
Note 2
MAX.
LV
MIN.
200
1150
1150
Note 4
Note 4
Note 4
300
1150
1150
Note 4
Note 4
Note 4
tKCY1/2
tKCY1/2
− 50
− 50
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2
tKCY1/2
tKCY1/2
− 120
− 120
− 120
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2
−7
Cb = 20 pF, Rb = 1.4 kΩ
tKCY1/2
tKCY1/2
− 50
− 50
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2
Note 3
Unit
MAX.
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
ns
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2
Cb = 20 pF, Rb = 1.4 kΩ
Cb = 20 pF, Rb = 2.7 kΩ
SCKp low-level width
tKL1
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↑)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
− 50
ns
ns
ns
tKCY1/2
tKCY1/2
− 10
− 50
− 50
58
479
479
ns
121
479
479
ns
10
10
10
ns
10
10
10
ns
ns
Note 5
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↑)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 5
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↓ to
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
60
60
60
ns
130
130
130
ns
Note 5
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↓)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
23
110
110
ns
33
110
110
ns
10
10
10
ns
10
10
10
ns
Note 6
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↓)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 6
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↑ to
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
10
10
10
ns
10
10
10
ns
Note 6
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 48 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Vb
Rb
Rb
SCKp
RL78/L12
<R>
SCK
SIp
SO
SOp
SI
User's device
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. The value must also be 2/fMCK or more.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
6. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to
52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
<R>
n: Channel number (mn = 00, 01)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 49 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
tKCY1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
SCKp low-level width
tKL1
MAX.
LV
MIN.
1150
1150
Note 4
Note 4
500
1150
1150
Note 4
Note 4
Note 4
1150
1150
1150
Note 4
Note 4
Note 4
1150
1150
Note 4
Note 4
tKCY1/2
tKCY1/2
tKCY1/2
− 75
− 75
− 75
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
tKCY1/2
tKCY1/2
tKCY1/2
Cb = 30 pF, Rb = 2.7 kΩ
− 170
− 170
− 170
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
tKCY1/2
tKCY1/2
tKCY1/2
Cb = 30 pF, Rb = 5.5 kΩ
− 458
− 458
− 458
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
tKCY1/2
tKCY1/2
Cb = 30 pF, Rb = 5.5 kΩ
− 458
− 458
tKCY1/2
tKCY1/2
tKCY1/2
− 12
− 50
− 50
tKCY1/2
tKCY1/2
tKCY1/2
− 18
− 50
− 50
tKCY1/2
tKCY1/2
tKCY1/2
− 50
− 50
− 50
tKCY1/2
tKCY1/2
− 50
− 50
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
<R>
MIN.
Note 2
Note 4
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
tKH1
MAX.
LS
300
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
Note 1
Note 3
Unit
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. The value must also be 4/fMCK or more.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance
(32-pin to 52-pin products)/EDD tolerance (64-pin products)) mode for the SOp pin and SCKp
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
2. Use it with EVDD ≥ Vb.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM
<R>
number (g = 1)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 50 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
Note 1
LS
Note 2
LV
Note 3
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
Note 4
(to SCKp↑)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
81
479
479
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
177
479
479
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
479
479
479
ns
479
479
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 4
(from SCKp↑)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
19
19
19
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
19
19
19
ns
19
19
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↓ to
Note 4
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
100
100
100
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
195
195
195
ns
2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
483
483
483
ns
483
483
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp setup time
Note 5
(to SCKp↓)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
44
110
110
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
44
110
110
ns
2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
110
110
110
ns
110
110
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 5
(from SCKp↓)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
19
19
19
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
ns
2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
ns
19
19
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑ to
Note 5
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
25
25
25
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
25
25
25
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
25
25
25
ns
25
25
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 51 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Rb
Vb
Rb
SCKp
RL78/L12
<R>
SCK
SIp
SO
SOp
SI
User's device
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
5. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance
(32-pin to 52-pin products)/EDD tolerance (64-pin products)) mode for the SOp pin and SCKp
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
2. Use it with EVDD ≥ Vb.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 52 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to
52-pin products)/EVDD tolerance (64-pin products)) mode for
the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 53 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
Note 4
tKCY2
4.0 V ≤ EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ EVDD < 3.3 V,
Note 5
1.6 V ≤ Vb ≤ 2.0 V
1.8 V ≤ EVDD < 3.3 V,
Note 5
1.6 V ≤ Vb ≤ 2.0 V
SCKp high-/low-level
Note 5
width
tKH2,
tKL2
Note 1
MAX.
tSIK2
tKSI2
tKSO2
MIN.
Note 3
Unit
MAX.
ns
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
ns
10/fMCK
ns
20 MHz < fMCK ≤ 24 MHz 16/fMCK
ns
16 MHz < fMCK ≤ 20 MHz 14/fMCK
ns
8 MHz < fMCK ≤ 16 MHz 12/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
ns
10/fMCK
ns
20 MHz < fMCK ≤ 24 MHz 36/fMCK
ns
16 MHz < fMCK ≤ 20 MHz 32/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
16/fMCK
fMCK ≤ 4 MHz
10/fMCK
10/fMCK
ns
10/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
fMCK ≤ 4 MHz
10/fMCK
10/fMCK
ns
ns
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
tKCY2/2
− 12
tKCY2/2
− 50
tKCY2/2
− 50
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2
− 18
tKCY2/2
− 50
tKCY2/2
− 50
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY2/2
− 50
tKCY2/2
− 50
tKCY2/2
− 50
ns
tKCY2/2
− 50
tKCY2/2
− 50
ns
2.7 V ≤ EVDD < 5.5 V, 2.3 V ≤ Vb ≤ 4.0 V
1/fMCK +
20
1/fMCK +
30
1/fMCK +
30
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1/fMCK +
30
1/fMCK +
30
1/fMCK +
30
ns
1/fMCK +
30
1/fMCK +
30
ns
2.7 V ≤ EVDD < 5.5 V, 2.3 V ≤ Vb ≤ 4.0 V
1/fMCK +
31
1/fMCK +
31
1/fMCK +
31
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1/fMCK +
31
1/fMCK +
31
1/fMCK +
31
ns
1/fMCK +
31
1/fMCK +
31
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Delay time from SCKp↓
Notes 5, 8
to SOp output
MAX.
LV
8 MHz < fMCK ≤ 20 MHz 10/fMCK
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
SIp hold time
Note 7
(from SCKp↑)
MIN.
Note 2
20 MHz < fMCK ≤ 24 MHz 12/fMCK
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
SIp setup time
Note 6
(to SCKp↑)
LS
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK
+ 120
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.4 V ≤ EVDD < 4.0 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
2/fMCK
+ 573
2/fMCK
+ 573
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 54 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
Rb
SCKp
RL78/L12
<R>
SCK
SIp
SO
SOp
SI
User's device
Notes 1. HS is condition of HS (high-speed main) mode.
<R>
2. LS is condition of LS (low-speed main) mode.
<R>
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
5. Use it with EVDD ≥ Vb.
6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
7. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
8. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance (32-pin to 52-pin products)/EDD tolerance (64-pin products)) mode for the SOp pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01))
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 55 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Output data
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance (32-pin to 52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 56 of 77
RL78/L12
2.5.2
2. ELECTRICAL SPECIFICATIONS
Serial interface IICA
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
(1/2)
Conditions
Standard Mode
HS
SCLA0 clock frequency
fSCL
Note 2
LS
Note 3
tSU:STA
MIN.
MIN.
MAX.
MIN.
2.7 V ≤ EVDD ≤ 5.5 V
0
100
0
100
0
100
2.4 V ≤ EVDD ≤ 5.5 V
0
100
0
100
0
100
0
100
0
100
0
100
2.7 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
2.4 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
4.7
4.7
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
Hold time
tHD:STA
2.7 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
2.4 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
4.0
4.0
1.6 V ≤ EVDD ≤ 5.5 V
tLOW
4.7
4.7
4.7
2.4 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
4.7
4.7
1.6 V ≤ EVDD ≤ 5.5 V
tHIGH
2.7 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
2.4 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
4.0
4.0
1.6 V ≤ EVDD ≤ 5.5 V
tSU:DAT
250
250
250
2.4 V ≤ EVDD ≤ 5.5 V
250
250
250
250
250
1.6 V ≤ EVDD ≤ 5.5 V
Data hold time (transmission)
tHD:DAT
0
3.45
0
3.45
0
3.45
2.4 V ≤ EVDD ≤ 5.5 V
0
3.45
0
3.45
0
3.45
0
3.45
0
3.45
0
3.45
2.7 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
2.4 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
4.0
4.0
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
Bus-free time
tBUF
ns
2.7 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
tSU:STO
μs
250
1.8 V ≤ EVDD ≤ 5.5 V
Setup time of stop condition
μs
4.0
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
Note 6
μs
4.7
1.8 V ≤ EVDD ≤ 5.5 V
Data setup time (reception)
μs
4.0
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
Hold time when SCLA0 = “H”
4.7
4.7
4.7
2.4 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
4.7
4.7
1.6 V ≤ EVDD ≤ 5.5 V
μs
μs
4.0
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
kHz
4.7
1.8 V ≤ EVDD ≤ 5.5 V
Hold time when SCLA0 = “L”
LV
MAX.
1.6 V ≤ EVDD ≤ 5.5 V
Note 5
Unit
Note 4
MIN.
1.8 V ≤ EVDD ≤ 5.5 V
Setup time of restart condition
Note 1
μs
4.7
(Note and Remark are listed on the next page.)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 57 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
<R>
Parameter
Symbol
(2/2)
Conditions
Fast Mode
Note 7
Fast Mode Plus Unit
Note 8
HS
SCLA0 clock frequency
fSCL
Note 2
LS
condition
tSU:STA
Note 5
tHD:STA
tLOW
= “L”
tHIGH
= “H”
MAX.
MIN.
MAX.
MIN.
2.7 V ≤ EVDD ≤ 5.5 V
0
400
0
400
0
400
0
1000
2.4 V ≤ EVDD ≤ 5.5 V
0
400
tSU:DAT
(reception)
tHD:DAT
Note 6
(transmission)
tSU:STO
condition
tBUF
400
400
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
0.6
0.6
2.7 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
0.6
0.6
2.7 V ≤ EVDD ≤ 5.5 V
1.3
1.3
1.3
2.4 V ≤ EVDD ≤ 5.5 V
1.3
1.3
1.3
1.3
1.3
2.7 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
0.6
0.6
2.7 V ≤ EVDD ≤ 5.5 V
100
100
100
2.4 V ≤ EVDD ≤ 5.5 V
100
100
100
100
0
0.9
0
0.9
0
0.9
2.4 V ≤ EVDD ≤ 5.5 V
0
0.9
0
0.9
0
0.9
0
0.9
0
0.9
2.7 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
0.6
0.6
1.3
1.3
2.7 V ≤ EVDD ≤ 5.5 V
1.3
2.4 V ≤ EVDD ≤ 5.5 V
1.3
1.8 V ≤ EVDD ≤ 5.5 V
kHz
0.26
μs
0.26
μs
0.5
μs
0.26
μs
50
ns
100
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
Bus-free time
0
0
0.6
1.8 V ≤ EVDD ≤ 5.5 V
Setup time of stop
400
400
0.6
1.8 V ≤ EVDD ≤ 5.5 V
Data hold time
0
0
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
Data setup time
Note 2
MIN.
1.8 V ≤ EVDD ≤ 5.5 V
Hold time when SCLA0
HS
MIN.
1.8 V ≤ EVDD ≤ 5.5 V
Hold time when SCLA0
Note 4
MAX.
1.8 V ≤ EVDD ≤ 5.5 V
Hold time
LV
MIN.
1.8 V ≤ EVDD ≤ 5.5 V
Setup time of restart
Note 3
1.3
1.3
1.3
1.3
0
450
μs
0.26
μs
0.5
μs
In normal mode, use it with fCLK ≥ 1 MHz, 1.6 V ≤ EVDD ≤ 5.5 V.
<R>
Notes 1.
<R>
2.
HS is condition of HS (high-speed main) mode.
<R>
3.
LS is condition of LS (low-speed main) mode.
<R>
4.
LV is condition of LV (low-voltage main) mode.
5.
The first clock pulse is generated after this period when the start/restart condition is detected.
6.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
<R>
7.
In fast mode, use it with fCLK ≥ 3.5 MHz, 1.8 V ≤ EVDD ≤ 5.5 V.
<R>
8.
In fast mode plus, use it with fCLK ≥ 10 MHz, 2.7 V ≤ EVDD ≤ 5.5 V.
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode:
Cb = 320 pF, Rb = 1.1 kΩ
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 58 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
IICA serial transfer timing
tLOW
SCLA0
tHD:DAT
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
tHD:STA
SDAA0
tLOW
Stop
condition
2.5.3
Start
condition
Restart
condition
Stop
condition
On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Transfer rate
R01DS0157EJ0100 Rev.1.00
2013.01.31
Symbol
Conditions
MIN.
115.2 k
TYP.
MAX.
Unit
1M
bps
Page 59 of 77
RL78/L12
2.6
2.6.1
2. ELECTRICAL SPECIFICATIONS
Analog Characteristics
A/D converter characteristics
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), target
ANI pin : ANI16 to ANI23 (supply ANI pin to EVDD)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage (−) = AVREFM)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
EZS
Notes 1, 2
Integral linearity error
EFS
Note 1
Differential linearity error
ILE
Note 1
DLE
Reference voltage (+)
AVREFP
Analog input voltage
VAIN
MIN.
TYP.
8
MAX.
Unit
10
bit
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
1.2
±5.0
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
1.2
±8.5
LSB
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
AVREFP = VDD
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
1.8 V ≤ VDD ≤ 5.5 V
±0.35
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±0.35
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±3.5
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
±6.0
LSB
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±2.0
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
VDD
V
AVREFP
V
10-bit resolution
AVREFP = VDD
10-bit resolution
AVREFP = VDD
1.6
0
and EVDD
VBGR
Select internal reference voltage output,
1.38
1.45
1.5
V
2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode only
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 60 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(2) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (−) = VSS (ADREFM = 0), target ANI pin : ANI0,
ANI1, ANI16 to ANI23
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference
voltage (−) = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
EZS
Notes 1, 2
Integral linearity error
EFS
Note 1
Differential linearity error
ILE
Note 1
Analog input voltage
DLE
VAIN
VBGR
MIN.
TYP.
8
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
MAX.
Unit
10
bit
1.8 V ≤ VDD ≤ 5.5 V
1.2
±7.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
1.2
±10.5
LSB
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
1.8 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±4.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±6.5
LSB
1.8 V ≤ VDD ≤ 5.5 V
±2.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
ANI0, ANI1
0
VDD
V
ANI16 to ANI23
0
EVDD
V
1.5
V
Select internal reference voltage output,
1.38
1.45
2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode only
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 61 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(3) When AVREF
(+)
= Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF
(−)
= AVREFM/ANI1
(ADREFM = 1), target ANI pin : ANI0, ANI16 to ANI23
(TA = −40 to +85°C, 2.4 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR, Reference
voltage (−) = AVREFM = 0 V) (HS (high-speed main) mode only)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Integral linearity error
Note 1
Differential linearity error
Note 1
TYP.
MAX.
8
Unit
bit
39
μs
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±1.0
LSB
1.5
V
VBGR
V
tCONV
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
EZS
8-bit resolution
ILE
DLE
17
Reference voltage (+)
VBGR
1.38
Analog input voltage
VAIN
0
1.45
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
2.6.2
Temperature sensor/internal reference voltage characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) (HS (high-speed main) mode only)
Parameter
Symbol
Temperature sensor output voltage VTMPS25
Conditions
MIN.
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VCONST
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
TYP.
MAX.
1.05
1.38
1.45
Unit
V
1.5
−3.6
V
mV/°C
temperature
<R>
Operation stabilization wait time
2.6.3
tAMP
μs
5
POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width
Detection delay time
R01DS0157EJ0100 Rev.1.00
2013.01.31
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.47
1.51
1.55
V
VPDR
Power supply fall time
1.46
1.50
1.54
V
TPW
μs
300
350
μs
Page 62 of 77
RL78/L12
2.6.4
2. ELECTRICAL SPECIFICATIONS
LVD circuit characteristics
(TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Detection
Supply voltage level
Symbol
VLVD0
voltage
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
Minimum pulse width
tLW
Detection delay time
tLD
R01DS0157EJ0100 Rev.1.00
2013.01.31
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.98
4.06
4.14
V
Power supply fall time
3.90
3.98
4.06
V
Power supply rise time
3.68
3.75
3.82
V
Power supply fall time
3.60
3.67
3.74
V
Power supply rise time
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
Power supply rise time
2.66
2.71
2.76
V
Power supply fall time
2.60
2.65
2.70
V
Power supply rise time
2.56
2.61
2.66
V
Power supply fall time
2.50
2.55
2.60
V
Power supply rise time
2.45
2.50
2.55
V
Power supply fall time
2.40
2.45
2.50
V
Power supply rise time
2.05
2.09
2.13
V
Power supply fall time
2.00
2.04
2.08
V
Power supply rise time
1.94
1.98
2.02
V
Power supply fall time
1.90
1.94
1.98
V
Power supply rise time
1.84
1.88
1.91
V
Power supply fall time
1.80
1.84
1.87
V
Power supply rise time
1.74
1.77
1.81
V
Power supply fall time
1.70
1.73
1.77
V
Power supply rise time
1.64
1.67
1.70
V
Power supply fall time
1.60
1.63
1.66
V
μs
300
300
μs
Page 63 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Interrupt and reset VLVD13
mode
Conditions
VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage
VLVD12
VLVD11
VLVD4
VLVD11
VLVD9
VLVD2
VLVD8
VLVD6
VLVD5
VLVD3
VLVD0
2.6.5
V
1.81
V
1.70
1.73
1.77
V
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
1.84
1.88
1.91
V
(+0.2 V)
1.80
1.84
1.87
V
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
2.86
2.92
2.97
V
(+1.2 V)
2.80
2.86
2.91
V
Falling interrupt voltage
Falling interrupt voltage
1.80
1.84
1.87
V
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
1.94
1.98
2.02
V
(+0.1 V)
1.90
1.94
1.98
V
Falling interrupt voltage
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
(+0.2 V)
Falling interrupt voltage
2.05
2.09
2.13
V
2.00
2.04
2.08
V
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
3.07
3.13
3.19
V
(+1.2 V)
3.00
3.06
3.12
V
2.40
2.45
2.50
V
Falling interrupt voltage
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
2.56
2.61
2.66
V
(+0.1 V)
2.50
2.55
2.60
V
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
2.66
2.71
2.76
V
(+0.2 V)
2.60
2.65
2.70
V
3.68
3.75
3.82
V
3.60
3.67
3.74
V
2.70
2.75
2.81
V
Falling interrupt voltage
Falling interrupt voltage
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
VLVD4
Unit
1.66
1.77
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
(+1.2 V)
Falling interrupt voltage
VLVD1
MAX.
1.63
1.74
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage
VLVD7
TYP.
1.60
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage
VLVD10
MIN.
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
2.86
2.92
2.97
V
2.80
2.86
2.91
V
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
2.96
3.02
3.08
V
(+0.2 V)
2.90
2.96
3.02
V
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
3.98
4.06
4.14
V
(+1.2 V)
3.90
3.98
4.06
V
MIN.
TYP.
MAX.
Unit
54
V/ms
Falling interrupt voltage
Falling interrupt voltage
Supply voltage rise time
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
VDD rise slope
(VDD : 0 V to VDD (MIN.)
<R>
Conditions
SVDD
Note
)
Note VDD (MIN.) in each operating mode is as below.
HS (high-speed main) mode: 2.7 [email protected] MHz to 24 MHz
2.4 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: 1.6 [email protected] MHz to 4 MHz
<R>
Caution
When LVD off, be sure to use external RESET pin.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 64 of 77
RL78/L12
2.7
2.7.1
2. ELECTRICAL SPECIFICATIONS
LCD Characteristics
Resistance division method
(1) Static display mode
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.0
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
MAX.
Unit
(2) 1/2 bias method, 1/4 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.7
(3) 1/3 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Note
Symbol
VL4
Conditions
MIN.
2.5
TYP.
VDD
Note
V
5.5 V (MAX) when driving a memory-type liquid crystal (the MLCDEN bit of the MLCD register = 1).
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 65 of 77
RL78/L12
2.7.2
2. ELECTRICAL SPECIFICATIONS
Internal voltage boosting method
(1) 1/3 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Conditions
Note 1
C1 to C4
Note 2
= 0.47 μF
MIN.
TYP.
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
VLCD = 0BH
1.25
1.35
1.43
V
VLCD = 0CH
1.30
1.40
1.48
V
VLCD = 0DH
1.35
1.45
1.53
V
VLCD = 0EH
1.40
1.50
1.58
V
VLCD = 0FH
1.45
1.55
1.63
V
VLCD = 10H
1.50
1.60
1.68
V
VLCD = 11H
1.55
1.65
1.73
V
VLCD = 12H
1.60
1.70
1.78
V
VLCD = 13H
1.65
1.75
1.83
V
= 0.47 μF
2 VL1
−0.1
2 VL1
2 VL1
V
3 VL1
3 VL1
V
Doubler output voltage
VL2
C1 to C4
Note 1
Tripler output voltage
VL4
C1 to C4
Note 1
= 0.47 μF
3 VL1
−0.15
5
ms
C1 to C4
Note 1
= 0.47 μF
500
ms
Reference voltage setup time
Voltage boost wait time
Note 2
Note 3
tVWAIT1
tVWAIT2
Notes 1.
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register
(or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of
the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts
(VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON
= 1).
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 66 of 77
RL78/L12
2. ELECTRICAL SPECIFICATIONS
(2) 1/4 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
Doubler output voltage
VL1
VL2
Conditions
Note 1
C1 to C5
Note 2
= 0.47 μF
MIN.
TYP.
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
VLCD = 0BH
1.25
1.35
1.43
V
VLCD = 0CH
1.30
1.40
1.48
V
VLCD = 0DH
1.35
1.45
1.53
V
VLCD = 0EH
1.40
1.50
1.58
V
VLCD = 0FH
1.45
1.55
1.63
V
VLCD = 10H
1.50
1.60
1.68
V
VLCD = 11H
1.55
1.65
1.73
V
VLCD = 12H
1.60
1.70
1.78
V
VLCD = 13H
1.65
1.75
1.83
V
C1 to C5
Note 1
= 0.47 μF
2 VL1−0.08
2 VL1
2 VL1
V
Tripler output voltage
VL3
C1 to C5
Note 1
= 0.47 μF
3 VL1−0.12
3 VL1
3 VL1
V
Quadruply output voltage
VL4
C1 to C5
Note 1
= 0.47 μF
4 VL1−0.16
4 VL1
4 VL1
V
5
ms
C1 to C5
Note 1
= 0.47 μF
500
ms
Reference voltage setup time
Voltage boost wait time
Note 2
Note 3
tVWAIT1
tVWAIT2
Notes 1.
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = C5 = 0.47 pF±30 %
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register
(or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of
the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts
(VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON
= 1).
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 67 of 77
RL78/L12
2.7.3
2. ELECTRICAL SPECIFICATIONS
Capacitor split method
(1) 1/3 bias method
(TA = −40 to +85°C, 2.2 V ≤ VDD = EVDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VL4
C1 to C4 = 0.47 μ F
VL2 voltage
VL2
C1 to C4 = 0.47 μ F
2/3 VL4
−0.1
2/3 VL4
2/3 VL4
+0.1
V
VL1 voltage
VL1
C1 to C4 = 0.47 μ F
1/3 VL4
−0.1
1/3 VL4
1/3 VL4
+0.1
V
VL4 voltage
Capacitor split wait time
Notes 1.
Note 1
Note 2
Note 2
Note 2
tVWAIT
VDD
100
V
ms
This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON
= 1).
2.
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 68 of 77
RL78/L12
2.8
2. ELECTRICAL SPECIFICATIONS
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C)
Parameter
<R>
Data retention supply voltage
Symbol
Conditions
MIN.
VDDDR
1.46
TYP.
Note
MAX.
Unit
5.5
V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a
POR reset is effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
<R>
2.9
Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
System clock frequency
Number of code flash rewrites
Symbol
fCLK
Cerwr
Conditions
MIN.
1.8 V ≤ VDD ≤ 5.5 V
TYP.
1
Retained for 20 years TA = 85°C
Note 3
Retained for 1 year
TA = 25°C
Note 3
Retained for 5 years
TA = 85°C
Note 3
100,000
Retained for 20 years TA = 85°C
Note 3
10,000
1,000
MAX.
Unit
24
MHz
Times
Note 1, 2, 3
Number of data flash rewrites
1,000,000
Note 1, 2, 3
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability
test.
Remark
When updating data multiple times, use the flash memory as one for updating data.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 69 of 77
RL78/L12
2.10
2. ELECTRICAL SPECIFICATIONS
Timing Specifications for Switching Flash Memory Programming Modes
Parameter
Symbol
How long from when a pin reset
tSUINIT
Conditions
MIN.
POR and LVD reset must end before the pin
TYP.
MAX.
Unit
100
ms
reset ends.
ends until the initial communication
settings are specified
How long from when the TOOL0
tSU
POR and LVD reset must end before the pin
10
μs
1
ms
reset ends.
pin is placed at the low level until a
pin reset ends
How long the TOOL0 pin must be
tHD
POR and LVD reset must end before the pin
reset ends.
kept at the low level after a reset
ends (except soft processing time)
<1>
<2>
<R>
<4>
<3>
RESET
tHD+
soft processing
time
00H reception
(TOOLRxD, TOOLTxD mode)
TOOL0
tSU
tSUINIT
<1>
The low level is input to the TOOL0 pin.
<2>
The pins reset ends. (POR and LVD reset must end before the pin reset ends.)
<3>
The TOOL0 pin is set to the high level.
<4>
Setting of the flash memory programming mode by UART reception and completion
of the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings
within 100 ms from when the reset ends.
tSU:
How long from when the TOOL0 pin is placed at the low level until a pin reset ends (MIN. 10 μs)
tHD:
How long to keep the TOOL0 pin at the low level from when the external or internal resets ends
(except software processing time)
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 70 of 77
RL78/L12
3. PACKAGE DRAWINGS
3. PACKAGE
3.1
DRAWINGS
32-pin products
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP32-7x7-0.80
PLQP0032GB-A
P32GA-80-GBT-1
0.2
HD
2
D
17
16
24
25
detail of lead end
1
E
c
HE
θ
32
8
1
L
9
e
(UNIT:mm)
3
b
x
M
A
A2
ITEM
D
DIMENSIONS
7.00±0.10
E
7.00±0.10
HD
9.00±0.20
HE
9.00±0.20
A
1.70 MAX.
A1
0.10±0.10
A2
y
A1
1.40
b
0.37±0.05
c
0.145 ±0.055
L
0.50±0.20
θ
0° to 8°
e
0.80
1.Dimensions “ 1” and “ 2” do not include mold flash.
x
0.20
2.Dimension “ 3” does not include trim offset.
y
0.10
NOTE
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 71 of 77
RL78/L12
3.2
3. PACKAGE DRAWINGS
44-pin products
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP44-10x10-0.80
PLQP0044GC-A
P44GB-80-UES-2
0.36
HD
D
detail of lead end
A3
23
22
33
34
c
L
E
Lp
HE
L1
(UNIT:mm)
12
11
44
1
ZE
e
ZD
b
x
M
S
A
S
S
NOTE
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
A1
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
A2
y
ITEM
D
0.25
b
0.37 +0.08
0.07
c
0.145 +0.055
0.045
L
0.50
Lp
0.60±0.15
L1
1.00±0.20
3° +5°
3°
e
0.80
x
0.20
y
0.10
ZD
1.00
ZE
1.00
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 72 of 77
RL78/L12
3.3
3. PACKAGE DRAWINGS
48-pin products
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP48-7x7-0.50
PLQP0048KF-A
P48GA-50-8EU-1
0.16
HD
D
detail of lead end
36
25
37
A3
24
c
L
E
Lp
HE
L1
(UNIT:mm)
13
48
12
1
ZE
e
ZD
b
x
M
S
A
ITEM
D
DIMENSIONS
7.00±0.20
E
7.00±0.20
HD
9.00±0.20
HE
9.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A2
c
L
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
0.25
0.22±0.05
0.145 +0.055
0.045
0.50
Lp
0.60±0.15
L1
1.00±0.20
3° +5°
3°
e
0.50
x
0.08
y
0.08
ZD
0.75
ZE
0.75
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 73 of 77
RL78/L12
3.4
3. PACKAGE DRAWINGS
52-pin products
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
52-PIN PLASTIC LQFP (10x10)
HD
D
2
27
39
40
detail of lead end
26
c
1
E
HE
L
52
14
1
13
e
(UNIT:mm)
3
b
x
M
A
A2
y
NOTE
ITEM
D
DIMENSIONS
10.00±0.10
E
10.00±0.10
HD
12.00±0.20
HE
12.00±0.20
A
1.70 MAX.
A1
0.10±0.05
A2
A1
0.32±0.05
c
0.145 ±0.055
L
0.50±0.15
e
0.65
x
0.13
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
1.40
b
0° to 8°
y
0.10
P52GB-65-GBS
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 74 of 77
RL78/L12
3.5
3. PACKAGE DRAWINGS
64-pin products
R5F10RLAAFA, R5F10RLCAFA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP64-12x12-0.65
PLQP0064JA-A
P64GK-65-UET-2
0.51
HD
D
detail of lead end
48
33
49
32
A3
c
L
E
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
A2
S
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
DIMENSIONS
12.00±0.20
E
12.00±0.20
HD
14.00±0.20
HE
14.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
A
y
ITEM
D
A1
0.25
b
0.32 +0.08
0.07
c
0.145 +0.055
0.045
L
0.50
Lp
0.60±0.15
L1
1.00±0.20
3° +5°
3°
e
0.65
x
0.13
y
0.10
ZD
1.125
ZE
1.125
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 75 of 77
RL78/L12
3. PACKAGE DRAWINGS
R5F10RLAAFB, R5F10RLCAFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP64-10x10-0.50
PLQP0064KF-A
P64GB-50-UEU-2
0.35
HD
D
detail of lead end
48
33
49
A3
32
c
L
E
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
ITEM
D
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A
A2
c
L
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
0.25
0.22±0.05
0.145 +0.055
0.045
0.50
Lp
0.60±0.15
L1
1.00±0.20
3° +5°
3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 76 of 77
RL78/L12
3. PACKAGE DRAWINGS
R5F10RLAANB, R5F10RLCANB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-HWQFN64-8x8-0.40
PWQN0064LA-A
P64K8-40-9B5-1
0.16
D
DETAIL OF A
E
PART
A
S
A
S
y
S
(UNIT:mm)
ITEM
D2
A
1
EXPOSED DIE PAD
16
64
17
D
8.00 ± 0.05
E
8.00 ± 0.05
A
0.75 ± 0.05
b
0.20 ± 0.05
e
0.40
Lp
B
DIMENSIONS
0.40 ± 0.10
x
0.05
y
0.05
E2
ITEM
32
49
EXPOSED
DIE PAD
VARIATIONS
33
48
Lp
D2
E2
MIN NOM MAX MIN NOM MAX
A 6.45 6.50 6.55 6.45 6.50 6.55
e
b
x
M
S A
B
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0100 Rev.1.00
2013.01.31
Page 77 of 77
Revision History
Rev.
Date
0.01
0.02
Feb 20, 2012
Sep 26, 2012
1.00
Jan 31, 2013
RL78/L12 Data Sheet
Description
Summary
Page
7, 8
15
11 to 15
16
17
18
19
20
First Edition issued
Modification of caution 2 in 1.3.5 64-pin products
Modification of I/O port in 1.6 Outline of Functions
Modification of 2. ELECTRICAL SPECIFICATIONS (TARGET)
Update of package drawings in 3. PACKAGE DRAWINGS
Modification of 1.5 Block Diagram
Modification of Note 2 in 1.6 Outline of Functions
Modification of 1.6 Outline of Functions
Deletion of target in 2. ELECTRICAL SPECIFICATIONS
Addition of caution 2 to 2. ELECTRICAL SPECIFICATIONS
Addition of description, note 3, and remark 2 to 2.1 Absolute Maximum
Ratings
22, 23
Modification of description and addition of note to 2.1 Absolute Maximum
Ratings
Modification of 2.2 Oscillator Characteristics
30
32
Modification of notes 1 to 4 in 2.3.2 Supply current characteristics
Modification of notes 1, 3 to 6, 8 in 2.3.2 Supply current characteristics
34
Modification of notes 7, 9, 11, and addition of notes 8, 12 to 2.3.2 Supply
current characteristics
Addition of description to 2.4 AC Characteristics
Modification of 2.5.1 Serial array unit
36
38, 40
to 42,
44 to
46, 48
to 52,
54, 55
57, 58
62
64
69
Modification of 2.5.2 Serial interface IICA
Modification of 2.6.2 Temperature sensor/internal reference voltage
characteristics
Addition of note and caution in 2.6.5 Supply voltage rise time
Modification of 2.8 Data Memory STOP Mode Low Supply Voltage Data
Retention Characteristics
69
Modification of conditions in 2.9 Timing Specs for Switching Flash Memory
Programming Modes
70
Modification of 2.10 Timing Specifications for Switching Flash Memory
Programming Modes
The mark “<R>” shows major revised points. The revised points can be easily searched by copying an “<R>” in the
PDF file and specifying it in the “Find what:” field.
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2013 Renesas Electronics Corporation. All rights reserved.
Colophon 2.2
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement