SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs ADAU1702

SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs ADAU1702
SigmaDSP 28-/56-Bit Audio Processor
with Two ADCs and Four DACs
ADAU1702
FEATURES
GENERAL DESCRIPTION
28-/56-bit, 25 MIPS digital audio processor
2 ADCs: SNR of 100 dB, THD + N of −83 dB
4 DACs: SNR of 104 dB, THD + N of −90 dB
Complete standalone operation
Self-boot from serial EEPROM
Auxiliary ADC with 4-input mux for analog control
GPIOs for digital controls and outputs
Fully programmable with SigmaStudio graphical tool
28-bit × 28-bit multiplier with 56-bit accumulator for full
double precision processing
Clock oscillator for generating master clock from crystal
PLL for generating a master clock from 64 × fS, 256 × fS,
384 × fS, or 512 × fS clocks
Flexible serial data input/output ports with I2S-compatible,
left-justified, right-justified, and TDM modes
Sampling rates of up to 192 kHz are supported
On-chip voltage regulator for compatibility with 3.3 V systems
48-lead, plastic LQFP
The ADAU1702 is a complete single-chip audio system with a
28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like
control interfaces. Signal processing includes equalization, crossover, bass enhancement, multiband dynamics processing, delay
compensation, speaker compensation, and stereo image widening.
This processing can be used to compensate for real-world
limitations of speakers, amplifiers, and listening environments,
providing dramatic improvements in perceived audio quality.
APPLICATIONS
Multimedia speaker systems
MP3 player speaker docks
Automotive head units
Minicomponent stereos
Digital televisions
Studio monitors
Speaker crossovers
Musical instrument effects processors
In-seat sound systems (aircraft/motor coaches)
Its signal processing is comparable to that found in high end
studio equipment. Most processing is done in full 56-bit, double
precision mode, resulting in very good low level signal performance. The ADAU1702 is a fully programmable DSP. The easy to
use SigmaStudio™ software allows the user to graphically configure
a custom signal processing flow using blocks such as biquad filters,
dynamics processors, level controls, and GPIO interface controls.
ADAU1702 programs can be loaded on power-up either from a
serial EEPROM through its own self-boot mechanism or from
an external microcontroller. On power-down, the current state
of the parameters can be written back to the EEPROM from the
ADAU1702 to be recalled the next time the program is run.
Two Σ-Δ ADCs and four Σ-Δ DACs provide a 98.5 dB analog
input to analog output dynamic. Each ADC has a THD + N of
−83 dB, and each DAC has a THD + N of −90 dB. Digital input
and output ports allow a glueless connection to additional
ADCs and DACs. The ADAU1702 communicates through an
I2C bus or a 4-wire SPI port.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.
ADAU1702
TABLE OF CONTENTS
Features .............................................................................................. 1
Parameter RAM.......................................................................... 30
Applications....................................................................................... 1
Data RAM ................................................................................... 30
General Description ......................................................................... 1
Read/Write Data Formats ......................................................... 30
Revision History ............................................................................... 3
Control Register Map..................................................................... 32
Functional Block Diagram .............................................................. 4
Control Register Details ................................................................ 34
Specifications..................................................................................... 5
Analog Performance .................................................................... 5
Address 2048 to Address 2055 (0x0800 to 0x0807)—Interface
Registers....................................................................................... 34
Digital Input/Output.................................................................... 6
Address 2056 (0x0808)—GPIO Pin Setting Register ............ 35
Power.............................................................................................. 6
Address 2057 to Address 2060 (0x0809 to 0x080C)—
Auxiliary ADC Data Registers.................................................. 36
PLL and Oscillator........................................................................ 6
Regulator........................................................................................ 6
Digital Timing Specifications ..................................................... 7
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
Address 2064 to Address 2068 (0x0810 to 0x0814)—Safeload
Data Registers ............................................................................. 37
Address 2069 to Address 2073 (0x0815 to 0x0819)—Safeload
Address Registers ....................................................................... 37
ESD Caution................................................................................ 10
Address 2074 to Address 2075 (0x081A to 0x081B)—Data
Capture Registers........................................................................ 38
Pin Configuration and Function Descriptions........................... 11
Address 2076 (0x081C)—DSP Core Control Register .......... 39
Typical Performance Characteristics ........................................... 14
Address 2078 (0x081E)—Serial Output Control Register .... 40
System Block Diagram ................................................................... 15
Address 2079 (0x081F)—Serial Input Control Register ....... 41
Theory of Operation ...................................................................... 16
Address 2080 to Address 2081 (0x0820 to 0x0821)—
Multipurpose Pin Configuration Registers............................. 42
Initialization .................................................................................... 17
Power-Up Sequence ................................................................... 17
Address 2082 (0x0822)—Auxiliary ADC and Power Control
Register ........................................................................................ 43
Control Registers Setup ............................................................. 17
Address 2084 (0x0824)—Auxiliary ADC Enable Register ... 43
Recommended Program/Parameter Loading Procedure ..... 17
Address 2086 (0x0826)—Oscillator Power-Down Register . 43
Power Reduction Modes............................................................ 18
Address 2087 (0x0827)—DAC Setup ...................................... 44
Using the Oscillator.................................................................... 18
Multipurpose Pins .......................................................................... 45
Setting Master Clock/PLL Mode .............................................. 18
Auxiliary ADC............................................................................ 45
Voltage Regulator ....................................................................... 19
General-Purpose Input/Output Pins....................................... 45
Audio ADCs .................................................................................... 20
Serial Data Input/Output Ports ................................................ 45
Audio DACs .................................................................................... 21
Layout Recommendations............................................................. 48
Control Ports................................................................................... 22
Parts Placement .......................................................................... 48
I2C Port ........................................................................................ 23
Grounding ................................................................................... 48
SPI Port ........................................................................................ 26
Typical Application Schematics.................................................... 49
Self-Boot ...................................................................................... 27
Self-Boot Mode........................................................................... 49
Signal Processing ............................................................................ 29
I2C Control .................................................................................. 50
Numeric Formats........................................................................ 29
SPI Control.................................................................................. 51
Programming .............................................................................. 29
Outline Dimensions ....................................................................... 52
RAMs and Registers ....................................................................... 30
Ordering Guide .......................................................................... 52
Address Maps.............................................................................. 30
Rev. C | Page 2 of 52
ADAU1702
REVISION HISTORY
6/11—Rev. B to Rev. C
Deleted Table 2 ..................................................................................6
2/11—Rev. A to Rev. B
Changes to Test Conditions/Comments Column, Table 3 ..........8
Changes to Table 10 ........................................................................12
Changes to Figure 20, Figure 21 ....................................................25
Changes to Figure 27 ......................................................................27
9/10—Rev. 0 to Rev. A
Deleted Temperature Range Section and Table 4, Renumbered
Sequentially ........................................................................................4
Moved and Changes to Functional Block Diagram Section and
Figure 1 ...............................................................................................4
Changes to Table 1 ............................................................................5
Added Table 2; Renumbered Sequentially .....................................6
Changes to Table 3 and Table 5 .......................................................7
Changes to Table 7 ............................................................................8
Reorganized Digital Timing Diagrams Section ............................9
Changes to Figure 2...........................................................................9
Changes to Figure 5.........................................................................10
Changes to Table 8 ..........................................................................11
Changes to Table 10 ........................................................................12
Changes to Figure 8 to Figure 11 ..................................................15
Renamed Theory of Operation Section ......................................17
Changes to Initialization Section ..................................................18
Changes to Setting the Master Clock/PLL Mode Section .........19
Changes to Voltage Regulator Section .........................................20
Changes to Figure 19 ......................................................................22
Changes to Table 14 ........................................................................23
Changes to Figure 22 through Figure 25......................................26
Deleted Table 20 ..............................................................................27
Changes to Self-Boot Section and EEPROM Format Section ..28
Added Figure 28, Renumbered Sequentially...............................29
Changes to Address 2057 to Address 2060 (0x809 to 0x80C)—
Auxiliary ADC Data Registers Section ........................................37
Changes to Multipurpose Pins Section and Auxiliary ADC
Section ..............................................................................................46
Changes to Ordering Guide...........................................................56
7/07—Revision 0: Initial Version
Rev. C | Page 3 of 52
ADAU1702
FUNCTIONAL BLOCK DIAGRAM
DIGITAL DIGITAL ANALOG ANALOG PLL PLL LOOP
VDD
GROUND VDD GROUND MODE FILTER
3
3
3
2
2
CRYSTAL
3.3V
1.8V
REGULATOR
ADAU1702
2
CLOCK
OSCILLATOR
PLL
2
FILTA/
ADC_RES
DAC
STEREO
ADC
28-/56-BIT, 25MIPS
AUDIO PROCESSOR CORE
10ms DELAY MEMORY
2
RESET/
MODE
SELECT
CONTROL
INTERFACE
AND
SELFBOOT
8-BIT
AUX
ADC
8-CH
DIGITAL
INPUT
DAC
4-CHANNEL
ANALOG
OUTPUT
8-CH
DIGITAL
OUTPUT
GPIO
INPUT/OUTPUT MATRIX
5
3
RESET SELFBOOT
I2C/SPI
DIGITAL IN
AND WRITEBACK OR GPIO
3
3
AUX ADC DIGITAL OUT
OR GPIO
OR GPIO
Figure 1.
Rev. C | Page 4 of 52
05798-001
2-CHANNEL
ANALOG
INPUT
FILTD/CM
ADAU1702
SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted.
ANALOG PERFORMANCE
Specifications are guaranteed at 25°C (ambient).
Table 1.
Parameter
ADC INPUTS
Number of Channels
Resolution
Full-Scale Input
Signal-to-Noise Ratio
A-Weighted
Dynamic Range
A-Weighted
Total Harmonic Distortion + Noise
Interchannel Gain Mismatch
Crosstalk
DC Bias
Gain Error
Group Delay
DAC OUTPUTS
Number of Channels
Resolution
Full-Scale Analog Output
Signal-to-Noise Ratio
A-Weighted
Dynamic Range
A-Weighted
Total Harmonic Distortion + Noise
Crosstalk
Interchannel Gain Mismatch
Gain Error
DC Bias
Group Delay
VOLTAGE REFERENCE
Absolute Voltage (CM)
AUXILIARY ADC
Full-Scale Analog Input
INL
DNL
Offset
Input Impedance
Min
Typ
Max
Unit
2
24
100 (283)
Bits
μA rms (μA p-p)
100
dB
100
−83
25
−82
1.5
dB
dB
mdB
dB
V
%
μs
Test Conditions/Comments
Stereo input
2 V rms input with 20 kΩ (18 kΩ external + 2 kΩ
internal) series resistor
−60 dB with respect to full-scale analog input
95
1.4
−11
250
1.6
+11
480
4
24
0.9 (2.5)
Bits
V rms (V p-p)
104
dB
104
−90
−100
25
dB
dB
dB
mdB
%
V
μs
−3 dB with respect to full-scale analog input
Analog channel-to-channel crosstalk
Delay is the same across all frequencies
Two stereo output channels
−60 dB with respect to full-scale analog output
99
−10
1.4
1.5
400
250
+10
1.6
1.4
1.5
1.6
V
2.8
3.0
0.5
1.0
15
30
3.1
V
LSB
LSB
mV
kΩ
17.8
42
Rev. C | Page 5 of 52
−1 dB with respect to full-scale analog output
Analog channel-to-channel crosstalk
Delay is the same across all frequencies
ADAU1702
DIGITAL INPUT/OUTPUT
Table 2.
Parameter
Input Voltage, High
Input Voltage, Low
Input Leakage, High
Input Leakage, Low
Bidirectional Pin Pull-Up Current, Low
MCLKI Input Leakage, High
MCLKI Input Leakage, Low
High Level Output Voltage
Low Level Output Voltage
Input Capacitance
GPIO Output Drive
1
Symbol
VIH
VIL
IIH
IIL
IIH
IIL
VOH
VOL
Min
2.0
Typ
Max 1
IOVDD
0.8
1
1
150
3
3
2.0
0.8
5
2
Unit
V
V
μA
μA
μA
μA
μA
V
V
pF
mA
Test Conditions/Comments
Excluding MCLKI
Excluding MCLKI and bidirectional pins
IOH = 2 mA
IOL = 2 mA
Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
POWER
Table 3.
Parameter
SUPPLY VOLTAGE
Analog Voltage
Digital Voltage
PLL Voltage
IOVDD Voltage
SUPPLY CURRENT
Analog Current (AVDD and PVDD)
Digital Current (DVDD)
Analog Current, Reset
Digital Current, Reset
DISSIPATION
Operation (AVDD, DVDD, PVDD) 2
Reset, All Supplies
POWER SUPPLY REJECTION RATIO (PSRR)
1 kHz, 200 mV p-p Signal at AVDD
1
2
Min
Typ
Max 1
3.3
1.8
3.3
3.3
50
40
35
1.5
Unit
V
V
V
V
85
60
55
4.5
mA
mA
mA
mA
286.5
118
mW
mW
50
dB
Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.
PLL AND OSCILLATOR
Table 4. PLL and Oscillator
Parameter
PLL Operating Range
PLL Lock Time
Crystal Oscillator Transconductance (gm)
1
Min
MCLK_Nom − 20%
Typ
Max 1
MCLK_Nom + 20%
20
78
Unit
MHz
ms
mmho
Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
REGULATOR
Table 5. Regulator
Parameter
DVDD Voltage
1
Min 1
1.7
Typ1
1.8
Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.
Rev. C | Page 6 of 52
Max1
1.84
Unit
V
ADAU1702
DIGITAL TIMING SPECIFICATIONS
All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 64).
Table 6. Digital Timing
Parameter
MASTER CLOCK
tMP
tMP
tMP
tMP
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
tSIS
tMIN
Limit
tMAX
Unit
Description
ns
ns
ns
ns
MCLKI period, 512 × fS mode
MCLKI period, 384 × fS mode
MCLKI period, 256 × fS mode
MCLKI period, 64 × fS mode
40
40
10
10
10
ns
ns
ns
ns
ns
tSIH
10
ns
tLOS
tLOH
tTS
tSODS
10
10
5
40
ns
ns
ns
ns
40
ns
INPUT_BCLK (Pin 9) low pulse width
INPUT_BCLK (Pin 9) high pulse width
INPUT_LRCLK (Pin 8) setup; time to INPUT_BCLK rising
INPUT_LRCLK (Pin 8) hold; time from INPUT_BCLK rising
SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) setup; time to
INPUT_BCLK (Pin 9) rising
SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) hold; time from
INPUT_BCLK (Pin 9) rising
OUTPUT_LRCLK (Pin 16) setup in slave mode
OUTPUT_LRCLK (Pin 16) hold in slave mode
OUTPUT_BCLK (Pin 19) falling to OUTPUT_LRCLK (Pin 16) timing skew
SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in slave mode; time
from OUTPUT_BCLK (Pin 19) falling
SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in master mode;
time from OUTPUT_BCLK (Pin 19) falling
6.25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
CCLK (Pin 23) frequency
CCLK (Pin 23) pulse width low
CCLK (Pin 23) pulse width high
CLATCH (Pin 21) setup; time to CCLK (Pin 23) rising
CLATCH (Pin 21) hold; time from CCLK (Pin 23) rising
CLATCH (Pin 21) pulse width high
CDATA (Pin 20) setup; time to CCLK (Pin 23) rising
CDATA (Pin 20) hold; time from CCLK (Pin 23) rising
COUT (Pin 22) delay; time from CCLK (Pin 23) falling
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
SCL (Pin 23) frequency
SCL (Pin 23) high
SCL (Pin 23) low
Setup time, relevant for repeated start condition
Hold time; after this period, the first clock is generated
Data setup time
SCL (Pin 23) rise time
SCL (Pin 23) fall time
SDA (Pin 22) rise time
SDA (Pin 22) fall time
Bus-free time; time between stop and start
ns
ns
μs
ns
GPIO (MPx pins) rise time
GPIO (MPx pins) fall time
GPIO (MPx pins) input latency; time until high/low value is read by core
RESET low pulse width
36
48
73
291
tSODM
SPI PORT
fCCLK
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCDS
tCDH
tCOD
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tBFT
MULTIPURPOSE PINS AND RESET
tGRT
tGFT
tGIL
tRLPW
244
366
488
1953
80
80
0
100
80
0
80
101
400
0.6
1.3
0.6
0.6
100
300
300
300
300
0.6
50
50
1.5 × 1/fS
20
Rev. C | Page 7 of 52
ADAU1702
Digital Timing Diagrams
tLIH
tBIH
INPUT_BCLK
tBIL
tLIS
INPUT_LRCLK
tSIS
SDATA_INx
LEFT-JUSTIFIED
MODE
MSB
MSB–1
tSIH
tSIS
SDATA_INx
I2S MODE
MSB
tSIH
tSIS
tSIS
SDATA_INx
RIGHT-JUSTIFIED
MODE
LSB
MSB
tSIH
tSIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
05798-002
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Input Port Timing
tCLS
tCLH
tCLPH
tCCPL
tCCPH
CLATCH
CCLK
CDATA
tCDH
tCDS
COUT
05798-004
tCOD
Figure 3. SPI Port Timing
tDS
tSCH
tSCH
SDA
tSCLH
SCL
tSCLL
tSCS
tSCF
2
Figure 4. I C Port Timing
Rev. C | Page 8 of 52
tBFT
05798-005
tSCR
ADAU1702
tLCH
tBIH
tTS
OUTPUT_BCLK
tBIL
tLOS
OUTPUT_LRCLK
SDATA_OUTx
LEFT-JUSTIFIED
MODE
tSODS
tSODM
MSB
MSB–1
tSODS
tSODM
SDATA_OUTx
I2S MODE
MSB
tSODS
tSODM
SDATA_OUTx
RIGHT-JUSTIFIED
MODE
MSB
LSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
05798-003
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 5. Serial Output Port Timing
tMP
RESET
tRLPW
Figure 6. Master Clock and RESET Timing
Rev. C | Page 9 of 52
05798-006
MCLKI
ADAU1702
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter
DVDD to Ground
AVDD to Ground
IOVDD to Ground
Digital Inputs
Temperature Range
Storage
Operating (Ambient),
Functionally Guaranteed
Maximum Junction Temperature
Soldering (10 sec)
Rating
0 V to 2.2 V
0 V to 4.0 V
0 V to 4.0 V
DGND − 0.3 V, IOVDD + 0.3 V
−65°C to +150°C
0°C to +70°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 8. Thermal Resistance
Package Type
48-Lead LQFP
ESD CAUTION
135°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 10 of 52
θJA
72
θJC
19.5
Unit
°C/W
ADAU1702
AGND
PLL_MODE0
PLL_MODE1
CM
FILTD
AGND
VOUT3
VOUT2
VOUT1
VOUT0
FILTA
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
AGND
1
ADC0
2
ADC_RES
36
AVDD
35
PLL_LF
3
34
PVDD
ADC1
4
33
PGND
RESET
5
32
MCLKI
31
OSCO
30
RSVD
PIN 1
INDICATOR
ADAU1702
TOP VIEW
(Not to Scale)
SELFBOOT 6
ADDR0 7
MP4
8
29
MP2
MP5
9
28
MP3
MP1 10
MP0 11
27
MP8
26
MP9
DGND 12
25
DGND
05798-007
DVDD
SCL/CCLK
SDA/COUT
CLATCH/WP
ADDR1/CDATA/WB
MP11
IOVDD
VDRIVE
MP10
MP6
MP7
DVDD
13 14 15 16 17 18 19 20 21 22 23 24
Figure 7. 48-Lead LQFP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1, 37, 42
Mnemonic
AGND
Type 1
PWR
2
ADC0
A_IN
3
ADC_RES
A_IN
4
ADC1
A_IN
5
RESET
D_IN
6
SELFBOOT
D_IN
7
ADDR0
D_IN
8
MP4
D_IO
9
MP5
D_IO
10
MP1
D_IO
11
MP0
D_IO
12, 25
DGND
PWR
13, 24
DVDD
PWR
Description
Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple AGND to an AVDD pin with a 100 nF capacitor.
Analog Audio Input 0. Full-scale 100 μA rms input. Current input allows the input voltage
level to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale
input. See the Audio ADCs section for details.
ADC Reference Current. Set the full-scale current of the ADCs with an external 18 kΩ resistor
connected between this pin and ground. See the Audio ADCs section for details.
Analog Audio Input 1. Full-scale 100 μA rms input. Current input allows the input voltage
level to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input.
Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1702 exits
reset on a low-to-high edge. For more information about initialization, see the Power-Up
Sequence section for details.
Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting
this pin high initiates a self-boot operation when the ADAU1702 is brought out of a reset. This
pin can be tied directly to the control voltage or pulled up/down with a resistor. See the
Self-Boot section for details.
I2C and SPI Address 0. In combination with the ADDR1 function on Pin 20, this pin allows
up to four ADAU1702 devices to be used on the same I2C bus and up to two ICs to be used
with a common SPI CLATCH signal. See the I2C Port section for details.
Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK). See the Multipurpose Pins
section for more details.
Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK). See the Multipurpose Pins
section for more details.
Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN1). See the Multipurpose Pins
section for more details.
Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN0). See the Multipurpose Pins
section for more details.
Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple DGND to a DVDD pin with a 100 nF capacitor.
1.8 V Digital Supply. This can be supplied either externally or generated from a 3.3 V
supply with the on-board 1.8 V regulator. Decouple DVDD to DGND with a 100 nF
capacitor.
Rev. C | Page 11 of 52
ADAU1702
Pin No.
14
Mnemonic
MP7
Type 1
D_IO
15
MP6
D_IO
16
MP10
D_IO
17
VDRIVE
A_OUT
18
IOVDD
PWR
19
MP11
D_IO
20
ADDR1/CDATA/WB
D_IN
21
CLATCH/WP
D_IO
22
SDA/COUT
D_IO
23
SCL/CCLK
D_IO
26
MP9
D_IO/A_IO
27
MP8
D_IO/A_IO
28
MP3
D_IO/A_IO
29
MP2
D_IO/A_IO
30
31
RSVD
OSCO
N/A
D_OUT
32
MCLKI
D_IN
Description
Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1). See the Multipurpose Pins
section for more details.
Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output (SDATA_OUT0). See the
Multipurpose Pins section for more details.
Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK). See the Multipurpose
Pins section for more details.
Drive for 1.8 V Regulator. The base of the voltage regulator external PNP transistor is
driven from VDRIVE. See the Voltage Regulator section for details.
Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage
that should be seen on the digital input pins. This pin is also the supply for the digital
output signals on the control port and MP pins. Always set IOVDD to 3.3 V. The current
draw of this pin is variable because it is dependent on the loads of the digital outputs.
Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). See the Multipurpose Pins
section for more details.
I2C Address 1/SPI Data Input/EEPROM Write Back Trigger. This is a multifunction pin as
follows:
ADDR1: In combination with ADDR0, this sets the I2C address of the IC so that four
ADAU1702s can be used on the same I2C bus. See the I2C Port section for details.
CDATA: See the SPI Port section for details.
WB: A rising (default) or falling (if set in the EEPROM messages) edge on this pin triggers a
writeback of the interface registers to the external EEPROM. This function can be used to
save parameter data on power-down. See the Self-Boot section for details.
SPI Latch Signal/ Self-Boot EEPROM Write Protect. This is a multifunction pin as follows:
CLATCH: must go low at the beginning of an SPI transaction and high at the end of a
transaction. Each SPI transaction can take a different number of cycles on the CCLK pin to
complete, depending on the address and read/write bit that are sent at the beginning of
the SPI transaction. See the SPI Port section for details.
WP: an open-collector output pin when in self-boot mode. The ADAU1702 pulls this low to
enable writes to an external EEPROM. This pin should be pulled high to 3.3 V. See the SelfBoot section for details.
I2C Data/ SPI Data Output. This is a multifunction pin, as follows:
SDA: this is for I2C data and is a bidirectional open-collector pin. The line connected to this
pin should have a 2.2 kΩ pull-up resistor. See the I2C Port section for details.
COUT: this SPI data output is used for reading back registers and memory locations. It is
three-stated when an SPI read is not active. See the SPI Port section for details.
I2C Clock/SPI Clock. This is a multifunction pin, as follows:
SCL: this pin function is for the I2C clock and is always an open-collector input when in I2C
control mode. In self-boot mode, this pin is an open-collector output (I2C master). The line
connected to this pin should have a 2.2 kΩ pull-up resistor. See the I2C Port section for
details.
CCLK: this pin function is for the SPI Clock and it either runs continuously or is gated off
between SPI transactions. See the SPI Port section for details.
Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary ADC Input 0. See
the Multipurpose Pins section for more details.
Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary ADC Input 3. See
the Multipurpose Pins section for more details.
Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary ADC Input 2. See the
Multipurpose Pins section for more details.
Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary ADC Input 1. See the
Multipurpose Pins section for more details.
Reserved. Tie to ground, either directly or through a pull-down resistor.
Crystal Oscillator Circuit Output. Connect a 100 Ω damping resistor between this pin and
the crystal. Do not use this output to directly drive a clock to another IC. If the crystal
oscillator is not used, this pin can be left disconnected. See the Using the Oscillator
section for details.
Master Clock Input. MCLKI can either be connected to a 3.3 V clock signal or be the input
from the crystal oscillator circuit. See the Setting Master Clock/PLL Mode section for details.
Rev. C | Page 12 of 52
ADAU1702
Pin No.
33
Mnemonic
PGND
Type 1
PWR
34
PVDD
PWR
35
PLL_LF
A_OUT
36, 48
38, 39
PWR
D_IN
40
AVDD
PLL_MODE0,
PLL_MODE1
CM
41
FILTD
A_OUT
43
VOUT3
A_OUT
44
VOUT2
A_OUT
45
VOUT1
A_OUT
46
VOUT0
A_OUT
47
FILTA
A_OUT
1
A_OUT
Description
PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple PGND to PVDD with a 100 nF capacitor.
3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. Decouple this pin
should to PGND with a 100 nF capacitor.
PLL Loop Filter Connection. Two capacitors and a resistor need to be connected to this pin, as
shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details.
3.3 V Analog Supply. Decouple this pin to AGND with a 100 nF capacitor.
PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency of the master
clock PLL. See the Setting Master Clock/PLL Mode section for more details.
1.5 V Common-Mode Reference. Connect a 47 μF decoupling capacitor between this pin
and ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is
not critical. This pin can be used to bias external analog circuits, as long as those circuits are
not drawing current from the pin (such as when CM is connected to the noninverting
input of an op amp).
DAC Filter Decoupling Pin. Connect a 10 μF capacitor between this pin and ground. The
capacitor material is not critical. The voltage on this pin is 1.5 V.
VOUT3 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used
with either an active or passive output reconstruction filter. See the Audio DACs section
for details.
VOUT2 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used
with either an active or passive output reconstruction filter. See the Audio DACs section
for details.
VOUT1 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used
with either an active or passive output reconstruction filter. See the Audio DACs section
for details.
VOUT0 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used
with either an active or passive output reconstruction filter. See the Audio DACs section
for details.
ADC Filter Decoupling Pin. Connect a 10 μF capacitor between this pin and ground. The
capacitor material is not critical. The voltage on this pin is 1.5 V.
PWR is power/ground, A_IN is analog input, D_IN is digital input, A_OUT is analog output, D_IO is digital input/output, D_IO is digital input/output, A_IO is analog
input/output, and N/A is not applicable.
Rev. C | Page 13 of 52
ADAU1702
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.20
fS = 48kHz
0.15
fS = 48kHz
0.08
0.06
0.10
0.04
GAIN (dB)
GAIN (dB)
0.05
0
–0.05
0.02
0
–0.02
–0.04
–0.10
–0.06
–0.15
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
22
–0.10
0
5
20
Figure 10. DAC Pass-Band Filter Response
10
10
–10
–20
–20
–30
–30
GAIN (dB)
–10
–40
–50
–40
–50
–60
–70
–70
–80
–80
–90
–90
5
10
15
20
25
30
35
40
FREQUENCY (kHz)
45
05798-009
–60
0
fS = 48kHz
0
fS = 48kHz
Figure 9. ADC Stop-Band Filter Response
–100
0
2
4
6
8
10
12
14
16
FREQUENCY (kHz)
Figure 11. DAC Stop-Band Filter Response
Rev. C | Page 14 of 52
18
20
05798-011
0
GAIN (dB)
15
FREQUENCY (kHz)
Figure 8. ADC Pass-Band Filter Response
–100
10
05798-010
0
05798-008
–0.20
–0.08
ADAU1702
SYSTEM BLOCK DIAGRAM
3.3V
100nF
100nF
3.3V TO 1.8V
REGULATOR
CIRCUIT
100nF
100nF
10µF
+
10µF
+
IOVDD
PVDD
AVDD
DVDD
VDRIVE
18kΩ
ADC0
AUDIO ADC
INPUT SIGNALS
18kΩ
18kΩ
VOUT0
ADC1
VOUT1
DAC OUTPUT FILTERS
(ACTIVE OR PASSIVE)
ADC_RES
VOUT2
+
10µF
FILTA
VOUT3
100nF
FILTD
ADCs
10µF
MP0
MULTIPURPOSE
PIN INTERFACES
+
100nF
MP1
ADAU1702
MP2
DACs
MP3
CM
MP4
10µF
MP5
+
100nF
MP6
MP7
MP8
MP9
MP10
ADDR0
MP11
ADDR1/CDATA/WB
CLATCH/WP
3.3V
SDA/COUT
475Ω
3.3nF
56nF
SCL/CCLK
PLL_LF
PLL_MODE0
PLL
SETTINGS
EEPROM,
MICROCONTROLLER,
AND/OR SELFBOOT
LOGIC
SELFBOOT
PLL_MODE1
MCLKI
RESET
RESET LOGIC
3MHz TO 25MHz
22pF
100Ω
OSCO
AGND
DGND
PGND
05798-012
22pF
RSVD
Figure 12. System Block Diagram
Rev. C | Page 15 of 52
ADAU1702
THEORY OF OPERATION
The core of the ADAU1702 is a 28-bit DSP (56-bit with double
precision processing) optimized for audio processing. The
program and parameter RAMs can be loaded with a custom
audio processing signal flow built by using SigmaStudio graphical
programming software from Analog Devices, Inc. The values
stored in the parameter RAM control individual signal processing
blocks, such as equalization filters, dynamics processors, audio
delays, and mixer levels. A safeload feature allows for transparent
parameter updates and prevents clicks in the output signals.
The program RAM, parameter RAM, and register contents can
be saved in an external EEPROM, from which the ADAU1702
can self-boot on startup. In this standalone mode, parameters
can be controlled through the on-board multipurpose pins. The
ADAU1702 can accept controls from switches, potentiometers,
rotary encoders, and IR receivers. Parameters such as volume
and tone settings can be saved to the EEPROM on power-down
and recalled on power-up.
The ADAU1702 can operate with digital or analog inputs and
outputs, or a mix of both. The stereo ADC and four DACs each
have an SNR of at least +100 dB and a THD + N of at least
−83 dB. The 8-channel, flexible serial data input/output ports
allow glueless interconnection to a variety of ADCs, DACs,
general-purpose DSPs, S/PDIF receivers and transmitters, and
sample rate converters. The serial ports of the ADAU1702 can
be configured in I2S, left justified, right justified, or TDM serial
port compatible modes.
Twelve multipurpose (MP) pins allow the ADAU1702 to receive
external control signals as input and to output flags or controls
to other devices in the system. The MP pins can be configured
as digital I/Os, inputs to the 4-channel auxiliary ADC, or serial data
I/O ports. As inputs, they can be connected to buttons, switches,
rotary encoders, potentiometers, IR receivers, or other external
circuitry to control the internal signal processing program. When
configured as outputs, these pins can drive LEDs, control other
ICs, or connect to other external circuitry in an application.
The ADAU1702 has a sophisticated control port that supports
complete read/write capability of all memory locations. Control
registers are provided to offer complete control of the configuration and serial modes of the chip. The ADAU1702 can be
configured for either SPI or I2C control, or can self-boot from
an external EEPROM.
An on-board oscillator can be connected to an external crystal
to generate the master clock. In addition, a master clock phaselocked loop (PLL) allows the ADAU1702 to be clocked from
various clock speeds. The PLL can accept inputs of 64 × fS, 256
× fS, 384 × fS, or 512 × fS to generate the internal master clock of
the core.
The SigmaStudio software is used to program and control the
SigmaDSP® through the control port. Along with designing and
tuning a signal flow, the tools can be used to configure all of the
DSP registers and burn a new program into the external EEPROM.
The SigmaStudio graphical interface allows anyone with digital
or analog audio processing knowledge to easily design a DSP
signal flow and port it to a target application. At the same time,
it provides enough flexibility and programmability for an experienced DSP programmer to have in-depth control of the design.
In SigmaStudio, the user can connect graphical blocks (such as
biquad filters, dynamics processors, mixers, and delays), compile
the design, and load the program and parameter files into the
ADAU1702 memory through the control port. Signal processing
blocks available in the provided libraries include
•
•
•
•
•
•
•
•
•
•
•
•
•
Single- and double-precision biquad filters
Processors with peak or rms detection for monochannel
and multichannel dynamics
Mixers and splitters
Tone and noise generators
Fixed and variable gain
Loudness
Delay
Stereo enhancement
Dynamic bass boost
Noise and tone sources
FIR filters
Level detectors
GPIO control and conditioning
Additional processing blocks are always being developed.
Analog Devices also provides proprietary and third-party
algorithms for applications such as matrix decoding, bass
enhancement, and surround virtualizers. Contact Analog
Devices for information about licensing these algorithms.
The ADAU1702 operates from a 1.8 V digital power supply
and a 3.3 V analog supply. An on-board voltage regulator can
be used to operate the chip from a single 3.3 V supply. It is
fabricated on a single monolithic, integrated circuit and is
packaged in a 48-lead LQFP for operation over the 0°C to
+70°C temperature range.
Rev. C | Page 16 of 52
ADAU1702
INITIALIZATION
1.
2.
3.
4.
5.
Apply power to ADAU1702.
Wait for PLL to lock.
Load the SigmaDSP program and parameters.
Set up the registers (including multipurpose pins and
digital interfaces).
Turn off the default muting of the converters, clear the
data registers, and initialize the DAC setup register (see
the Control Registers Setup section for specific settings).
POWER-UP SEQUENCE
Table 10 lists typical times to boot the ADAU1702 into an
operational state of an application, assuming a 400 kHz I2C
clock loading a full program, parameter set, and all registers
(about 6.5 kB). In reality, most applications do not fill the RAMs
and therefore boot time (Column 3 of Table 10) is less.
CONTROL REGISTERS SETUP
The following registers must be set as described in this section
to initialize the ADAU1702. These settings are the basic minimum
settings needed to operate the IC with an analog input/output of
48 kHz. More registers may need to be set, depending on the
application. See the RAMs and Registers section for additional
settings.
The ADAU1702 has a built-in power-up sequence that
initializes the contents of all internal RAMs on power-up or
when the device is brought out of a reset. On the positive edge
of RESET, the contents of the Internal Program Boot ROM are
copied to the Internal Program RAM memory, the parameter,
RAM, is filled with values (all 0s) from its associated Boot
ROM, and all registers are initialized to 0s. The default Boot
ROM program copies audio from the inputs to the outputs
without processing it (see Figure 13). In this program, serial
digital Input 0 and Input 1 are output on DAC0 and DAC1 and
serial digital Output 0 and Output 1. ADC0 and ADC1 are
output on DAC2 and DAC3. The data memories are also zeroed
at power-up. Do not write new values to the control port until
the initialization is complete.
DSP Core Control Register (Address 2076)
Table 10. Power-Up Time
2.
MCLKI Input
3.072 MHz (64 × fS)
11.289 MHz (256 × fS)
12.288 MHz (256 × fS)
18.432 MHz (384 × fS)
24.576 MHz (512 × fS)
Init.
Time
85 ms
23 ms
21 ms
16 ms
11 ms
Max Program/
Parameter/Register
Boot Time (I2C)
133 ms
133 ms
133 ms
133 ms
133 ms
Total
218 ms
156 ms
154 ms
149 ms
144 ms
Set Bits[4:2] (ADM, DAM, and CR) each to 1.
DAC Setup Register (Address 2087)
Set Bits[0:1] (DS[1:0]) to 01.
RECOMMENDED PROGRAM/PARAMETER
LOADING PROCEDURE
When writing large amounts of data to the program or parameter RAM in direct write mode, the processor core should
be disabled to prevent unpleasant noises from appearing in
the audio output.
1.
3.
4.
5.
The PLL start-up time lasts for 218 cycles of the clock on the
MCLKI pin. This time ranges from 10.7 ms for a 24.576 MHz
(512 × fS) input clock to 85.3 ms for a 3.072 MHz (64 × fS) input
clock and is measured from the rising edge of RESET. Following
the PLL startup, the duration of the ADAU1702 boot cycle is about
42 μs for a fS of 48 kHz. The user should avoid writing to or reading
from the ADAU1702 during this start-up time.
For an MCLK input of 12.288 MHz, the full initialization
sequence (PLL startup plus boot cycle) is approximately 21 ms.
As the device comes out of a reset, the clock mode is
immediately set by the PLL_MODE0 and PLL_MODE1 pins.
The reset is synchronized to the falling edge of the internal clock.
Rev. C | Page 17 of 52
Set Bit 3 and Bit 4 (active low) of the core control register
to 1 to mute the ADCs and DACs. This begins a volume
ramp-down.
Set Bit 2 (active low) of the core control register to 1. This
zeroes the SigmaDSP accumulators, the data output registers,
and the data input registers.
Fill the program RAM using burst mode writes.
Fill the parameter RAM using burst mode writes.
Deassert Bit 2 to Bit 4 of the core control register.
DAC0
SDATA_OUT0
SDATA_IN0
DAC1
ADC0
DAC2
ADC1
DAC3
Figure 13. Default Program Signal Flow
05798-013
This section details the procedure for properly setting up the
ADAU1702. The following five-step sequence provides an
overview of how to initialize the IC:
ADAU1702
POWER REDUCTION MODES
Sections of the ADAU1702 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
DACs, and voltage reference.
The individual analog sections can be turned off by writing to
the auxiliary ADC and power control register. By default, the
ADCs, DACs, and reference are enabled (all bits set to 0). Each
of these can be turned off by writing a 1 to the appropriate bits
in this register. The ADC power-down mode powers down both
ADCs, and each DAC can be powered down individually. The
current savings is about 15 mA when the ADCs are powered
down and about 4 mA for each DAC that is powered down.
The voltage reference, which is supplied to both the ADCs
and DACs, should only be powered down if all ADCs and
DACs are powered down. The reference is powered down by
setting both Bit 6 and Bit 7 of the control register.
USING THE OSCILLATOR
The ADAU1702 can use an on-board oscillator to generate
its master clock. The oscillator is designed to work with a
256 × fS master clock, which is 12.288 MHz for a fS of 48 kHz
and 11.2896 MHz for a fS of 44.1 kHz. The crystal in the oscillator circuit should be an AT-cut, parallel resonator operating
at its fundamental frequency. Figure 14 shows the external
circuit recommended for proper operation.
ADAU1702
OSCO
C2
MCLKI
SETTING MASTER CLOCK/PLL MODE
The MCLKI input of the ADAU1702 feeds a PLL, which generates
the 25 MIPS SigmaDSP core clock. In normal operation, the
input to MCLKI must be one of the following: 64 × fS, 256 × fS,
384 × fS, or 512 × fS, where fS is the input sampling rate. The
mode is set on PLL_MODE0 and PLL_MODE1 as described in
Table 11. If the ADAU1702 is set to receive double-rate signals
(by reducing the number of program steps per sample by a factor
of 2 using the core control register), the master clock frequency
must be 32 × fS, 128 × fS, 192 × fS, or 256 × fS. If the ADAU1702
is set to receive quad-rate signals (by reducing the number of
program steps per sample by a factor of 4 using the core control
register), the master clock frequency must be 16 × fS, 64 × fS, 96 × fS,
or 128 × fS. On power-up, a clock signal must be present on the
MCLKI pin so that the ADAU1702 can complete its
initialization routine.
Table 11. PLL Modes
Figure 14. Crystal Oscillator Circuit
The 100 Ω damping resistor on OSCO gives the oscillator a
voltage swing of approximately 2.2 V. The crystal shunt capacitance should be 7 pF. Its load capacitance should be about 18 pF,
although the circuit supports values of up to 25 pF. The necessary
values of the C1 and C2 load capacitors can be calculated from
the crystal load capacitance as follows:
CL =
If the oscillator is not used in the design, it can be powered
down to save power. This can be done if a system master clock
is already available in the system. By default, the oscillator is
powered on. The oscillator powers down when a 1 is written to
the OPD bit of the oscillator power-down register (see Table 58).
C1 × C2
+ C stray
C1 + C2
where Cstray is the stray capacitance in the circuit and is usually
assumed to be approximately 2 pF to 5 pF.
MCLKI Input
64 × fS
256 × fS
384 × fS
512 × fS
PLL_MODE0
0
0
1
1
PLL_MODE1
0
1
0
1
Do not change the clock mode without also resetting the
ADAU1702. If the mode is changed during operation, a click or
pop can result in the output signals. Change the state of the
PLL_MODEx pins while holding RESET low.
Connect the PLL loop filter to the PLL_LF pin. This filter, shown
in Figure 15, includes three passive components—two capacitors
and a resistor. The values of these components do not need to
be exact; the tolerance can be up to 10% for the resistor and up
to 20% for the capacitors. The 3.3 V signal shown in Figure 15 can
be connected to the AVDD supply of the chip.
OSCO should not be used to drive the crystal signal directly to
another IC. This signal is an analog sine wave, and it is not appropriate to use it to drive a digital input. There are two options for
using the ADAU1702 to provide a master clock to other ICs in
the system. The first, and less recommended, method is to use a
high impedance input digital buffer on the OSCO signal. If this
approach is used, minimize the trace length to the buffer input.
The second method is to use a clock from the serial output port.
Pin MP11 can be set as an output (master) clock divided down
from the internal core clock. If this pin is set to serial output port
(OUTPUT_BCLK) mode in the multipurpose pin configuration
Rev. C | Page 18 of 52
3.3V
475Ω
3.3nF
56nF
ADAU1702
PLL_LF
05798-015
100Ω
05798-014
C1
register (Address 2081) and the port is set to master in the serial
output control register (Address 2078), the desired output
frequency can also be set in the serial output control register
with the OBF[1:0] bits (see Table 47).
Figure 15. PLL Loop Filter
ADAU1702
The digital voltage of the ADAU1702 must be set to 1.8 V. The
chip includes an on-board voltage regulator that allows the
device to be used in systems without an available 1.8 V supply
but with an available 3.3 V supply. The only external components
needed in such instances are a PNP transistor, a resistor, and a
few bypass capacitors. Only one pin, VDRIVE, is necessary to
support the regulator.
The recommended design for the voltage regulator is shown
in Figure 16. The 10 μF and 100 nF capacitors shown in this
configuration are recommended for bypassing, but are not
necessary for operation. Each DVDD pin should have its own
100 nF bypass capacitor, but only one bulk capacitor (10 μF to
47 μF) is needed for both DVDD pins. With this configuration,
3.3 V is the main system voltage; 1.8 V is generated at the
transistor’s collector, which is connected to the DVDD pins.
VDRIVE is connected to the base of the PNP transistor. If the
regulator is not used in the design, VDRIVE can be tied to ground.
Two specifications must be considered when choosing a
regulator transistor: The transistor’s current amplification factor
(hFE or beta) should be at least 100, and the transistor’s collector
must be able to dissipate the heat generated when regulating
from 3.3 V to 1.8 V. The maximum digital current drawn from
the ADAU1702 is 60 mA. The equation to determine the
minimum power dissipation of the transistor is as follows:
(3.3 V − 1.8 V) × 60 mA = 90 mW
There are many transistors with these specifications available in
small SOT-23 or SOT-223 packages.
Rev. C | Page 19 of 52
3.3V
10µF
+
1kΩ
100nF
ADAU1702
DVDD
VDRIVE
05798-016
VOLTAGE REGULATOR
Figure 16. Voltage Regulator Configuration
ADAU1702
AUDIO ADCs
The stereo audio ADCs are current input; therefore, a voltageto-current resistor is required on the inputs. This means that
the voltage level of the input signals to the system can be set to
any level; only the input resistors need to be scaled to provide
the proper full-scale current input. The ADC0 and ADC1 input
pins, as well as ADC_RES, have an internal 2 kΩ resistor for
ESD protection. The voltage seen directly on the ADC input
pins is the 1.5 V common mode.
The external resistor connected to ADC_RES sets the full-scale
current input of the ADCs. The full range of the ADC inputs is
100 μA rms with an external 18 kΩ resistor on ADC_RES (20 kΩ
total, because it is in series with the internal 2 kΩ). The only
reason to change the ADC_RES resistor is if a sampling rate
other than 48 kHz is used.
The voltage-to-current resistors connected to ADC0/ADC1 set
the full-scale voltage input of the ADCs. With a full-scale current
input of 100 μA rms, a 2.0 V rms signal with an external 18 kΩ
resistor (in series with the 2 kΩ internal resistor) results in an
input using the full range of the ADC. The matching of these
resistors to the ADC_RES resistor is important to the operation
of the ADCs. For these three resistors, a 1% tolerance is
recommended.
The values of the resistors (internal plus external) in series with
the ADC0 and ADC1 pins can be calculated as follows:
R INPUT TOTAL = (rms Input Voltage) × 10 kΩ ×
Table 12. ADC Input Resistor Values
Full-Scale
RMS Input
Voltage (V)
0.9
1.0
2.0
ADC_RES
Value (kΩ)
18
18
18
ADC0/ADC1
Resistor
Value (kΩ)
7
8
18
Total ADC0/ADC1
Input Resistance
(External +
Internal) (kΩ)
9
10
20
Figure 17 shows a typical configuration of the ADC inputs for
a 2.0 V rms input signal for a fS of 48 kHz. The 47 μF capacitors are
used to ac-couple the signals so that the inputs are biased at 1.5 V.
Either the ADC0 and/or ADC1 input pins can be left unconnected if that channel of the ADC is unused.
These calculations of resistor values assume a 48 kHz sample
rate. The recommended input and current setting resistors
scale linearly with the sample rate because the ADCs have a
switched-capacitor input. The total value (2 kΩ internal plus
external resistor) of the ADC_RES resistor with sample rate
fS_NEW can be calculated as follows:
RTOTAL = 20 kΩ ×
48,000
f S _ NEW
Table 12 lists the external and total resistor values for common
signal input levels at a 48 kHz sampling rate. A full-scale rms
input voltage of 0.9 V is shown in the table because a full-scale
signal at this input level is equal to a full-scale output on the DACs.
48,000
f S _ NEW
Rev. C | Page 20 of 52
ADAU1702
47µF
18kΩ
ADC0
47µF
18kΩ
ADC1
18kΩ
ADC_RES
05798-017
The ADAU1702 has two Σ-Δ ADCs. The signal-to-noise ratio
(SNR) of the ADCs is 100 dB, and the THD + N is −83 dB.
Figure 17. Audio ADC Input Configuration
ADAU1702
AUDIO DACs
To properly initialize the DACs, the DS[1:0] bits in the DAC
setup register (Address 2087) should be set to 01.
47µF
DAC_OUT
The DAC outputs can be filtered with either an active or a
passive reconstruction filter. A single-pole, passive, low-pass
filter with a 50 kHz corner frequency, as shown in Figure 18,
is sufficient to filter the DAC out-of-band noise, although an
active filter may provide better audio performance. Figure 19
560Ω
FILTER_OUT
5.6nF
+
Figure 18. Passive DAC Output Filter
470pF
47µF
150pF
604Ω
AD8606
3.3nF
FILTER_OUT
Figure 19. Active DAC Output Filter
Rev. C | Page 21 of 52
49.9kΩ
05798-019
4.75kΩ 4.75kΩ
+
DAC_OUT
05798-018
The DACs are in an inverting configuration. If a signal inversion
from input to output is undesirable, it can be reversed either by
using an inverting configuration for the output filter or by simply
inverting the signal in the SigmaDSP program flow.
shows a triple-pole, active, low-pass filter that provides a steeper
roll-off and better stop-band attenuation than the passive filter.
In this configuration, the V+ and V− pins of the AD8606 op
amp are set to VDD and ground, respectively.
+
The ADAU1702 includes four Σ-Δ DACs. The SNR of the DAC
is 104 dB, and the THD + N is −90 dB. A full-scale output on
the DACs is 0.9 V rms (2.5 V p-p).
ADAU1702
CONTROL PORTS
exceed the range of single byte addressing. All subsequent bytes
(starting with Byte 3) contain the data, such as control port data,
program data, or parameter data. The number of bytes per word
depends on the type of data that is being written. The exact formats
for specific types of writes are shown in Table 20 to Table 29.
The ADAU1702 can operate in one of three control modes:
•
•
•
I2C control
SPI control
Self-boot (no external controller)
The ADAU1702 has both a 4-wire SPI control port and a
2-wire I2C bus control port. Each can be used to set the RAMs
and registers. When the SELFBOOT pin is low at power-up, the
part defaults to I2C mode but can be put into SPI control mode
by pulling the CLATCH/WP pin low three times. When the
SELFBOOT pin is set high at power-up, the ADAU1702 loads
its program, parameters, and register settings from an external
EEPROM on startup.
The control port is capable of full read/write operation for all
addressable memory and registers. Most signal processing
parameters are controlled by writing new values to the parameter
RAM using the control port. Other functions, such as mute and
input/output mode control, are programmed by writing to the
registers.
All addresses can be accessed in a single address mode or a
burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
memory or register location within the ADAU1702. This
subaddress must be two bytes because the memory locations
within the ADAU1702 are directly addressable and their sizes
The ADAU1702 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. If large blocks of data need to be downloaded, the output
of the DSP core can be halted (using the CR bit in the DSP core
control register (Address 2076)), new data can be loaded, and
then the device can be restarted. This is typically done during
the booting sequence at startup or when loading a new program
into RAM. In cases where only a few parameters need to be
changed, they can be loaded without halting the program. To
avoid unwanted side effects while loading parameters on the fly, the
SigmaDSP provides safeload registers. The safeload registers can
be used to buffer a full set of parameters (for example, the five
coefficients of a biquad) and then transfer these parameters into
the active program within one audio frame. The safeload mode
uses internal logic to prevent contention between the DSP core
and the control port.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 13 details these
multiple functions.
Table 13. Control Port Pins and SELFBOOT Pin Functions
Pin
SCL/CCLK
SDA/COUT
ADDR1/CDATA/WB
CLATCH/WP
ADDR0
I2C Mode
SCL—input
SDA—open-collector output
ADDR1—input
Unused input—tie to ground or IOVDD
ADDR0—input
SPI Mode
CCLK—input
COUT—output
CDATA—input
CLATCH—input
ADDR0—input
Rev. C | Page 22 of 52
Self-Boot
SCL—output
SDA—open-collector output
WB—writeback trigger
WP—EEPROM write protect, open-collector output
Unused input—tie to ground or IOVDD
ADAU1702
I2C PORT
Addressing
The ADAU1702 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1702 and the system I2C master controller.
In I2C mode, the ADAU1702 is always a slave on the bus,
meaning it cannot initiate a data transfer. Each slave device is
recognized by a unique address. The address byte format is
shown in Table 14. The ADAU1702 slave addresses are set with
the ADDR0 and ADDR1 pins. The address resides in the first
seven bits of the I2C write. The LSB of this byte sets either a read
or write operation. Logic Level 1 corresponds to a read operation,
and Logic Level 0 corresponds to a write operation. Bit 5 and
Bit 6 of the address are set by tying the ADDRx pins of the
ADAU1702 to Logic Level 0 or Logic Level 1. The full byte
addresses, including the pin settings and read/write (R/W) bit,
are shown in Table 15.
Initially, each device on the I2C bus is in an idle state monitoring
the SDA and SCL lines for a start condition and the proper address.
The I2C master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA while SCL
remains high. This indicates that an address or an address and a
data stream follow. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
R/W bit) MSB first. The device that recognizes the transmitted
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition. The R/W bit determines the direction of the
data. A Logic 0 on the LSB of the first byte means the master
writes information to the peripheral, whereas a Logic 1 means
the master reads infor-mation from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop condition
occurs when SDA transitions from low to high while SCL is held
high. Figure 20 shows the timing of an I2C write, and Figure 21
shows an I2C read.
Burst mode addressing, where the subaddresses are automatically incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single-word write unless a
stop condition is encountered. The registers and RAMs in the
ADAU1702 range in width from one to five bytes, so the autoincrement feature knows the mapping between subaddresses and
the word length of the destination register (or memory location). A
data transfer is always terminated by a stop condition.
Both SDA and SCL should have 2.2 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines should
not be more than IOVDD (3.3 V).
Table 14. ADAU1702 I2C Address Byte Format
Bit 0
0
Bit 1
1
Bit 2
1
Bit 3
0
Bit 4
1
Bit 5
ADDR1
Bit 6
ADDR0
Table 15. ADAU1702 I2C Addresses
ADDR1
0
0
0
0
1
1
1
1
ADDR0
0
0
1
1
0
0
1
1
R/W
0
1
0
1
0
1
0
1
Slave Address
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
Bit 7
R/W
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1702 immediately
jumps to the idle condition. During a given SCL high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1702 does
not issue an acknowledge and returns to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the ADAU1702
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no-acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. On the other hand, if the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register,
a no acknowledge is issued by the ADAU1702, and the part returns
to the idle condition.
Rev. C | Page 23 of 52
ADAU1702
SCL
1
0
SDA
1
START BY
MASTER
0
1
0
ADDR R/W
SEL
ACK BY
ADAU1702
ACK BY
ADAU1702
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK BY
ADAU1702
FRAME 4
DATA BYTE 1
STOP BY
MASTER
05798-020
ACK BY
ADAU1702
FRAME 3
SUBADDRESS BYTE 2
Figure 20. I2C Write to ADAU1702 Clocking
SCL
SDA
START BY
MASTER
0
1
1
0
1
ADDR
SEL R/W
0
ACK BY
ADAU1702
ACK BY
ADAU1702
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
SCL
(CONTINUED)
SDA
(CONTINUED)
ADR
SEL
FRAME 3
SUBADDRESS BYTE 2
ACK BY
ADAU1702
R/W
ACK BY
ADAU1702
REPEATED
START BY MASTER
FRAME 4
CHIP ADDRESS BYTE
SCL
(CONTINUED)
ACK BY
MASTER
FRAME 5
READ DATA BYTE 1
ACK BY
MASTER
FRAME 6
READ DATA BYTE 2
Figure 21. I2C Read from ADAU1702 Clocking
Rev. C | Page 24 of 52
STOP BY
MASTER
05798-021
SDA
(CONTINUED)
ADAU1702
I2C Read and Write Operations
master then responds every ninth pulse with an acknowledge
pulse to the ADAU1702.
Figure 22 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1702 issues an acknowledge by
pulling SDA low.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1702 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other addresses
may have word lengths ranging from one to five bytes. The
ADAU1702 always decodes the subaddress and sets the autoincrement circuit so that the address increments after the
appropriate number of bytes.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1702 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
two-byte word length.
The timing of a single-word read operation is shown in
Figure 24. Note that the first R/W bit is 0, indicating a write
operation. This is because the subaddress still needs to be
written to set up the internal address. After the ADAU1702
acknowledges the receipt of the subaddress, the master must
issue a repeated start command followed by the chip address
byte with the R/W set to 1 (read). This causes the ADAU1702
SDA to reverse and begin driving data back to the master. The
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS
HIGH
AS
SUBADDRESS
LOW
AS
DATA BYTE 1
AS
DATA BYTE 2
AS
DATA BYTE N
P
05798-022
S
Figure 22 to Figure 25 use the following abbreviations:
S is the start bit.
P is the stop bit.
AM means acknowledge by master.
AS means acknowledge by slave.
S
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS
HIGH
SUBADDRESS
LOW
AS
DATAWORD 1,
BYTE 1
AS
AS
DATAWORD 1,
BYTE 2
DATAWORD 2,
BYTE 1
AS
AS
DATAWORD 2,
BYTE 2
AS
P
05798-023
Figure 22. Single Word I2C Write Format
S
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS
HIGH
AS
SUBADDRESS
LOW
AS
S
CHIP ADDRESS,
R/W = 1
AS
DATA
BYTE 1
AM
DATA
BYTE 2
AM
DATA
BYTE N
P
05798-024
Figure 23. Burst Mode I2C Write Format
S
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS
HIGH
AS
SUBADDRESS
LOW
AS
S
CHIP ADDRESS,
R/W = 1
Figure 25. Burst Mode I2C Read Format
Rev. C | Page 25 of 52
AS
DATAWORD 1,
BYTE 1
AM
DATAWORD 1,
BYTE 2
AM
P
05798-025
Figure 24. Single-Word I2C Read Format
ADAU1702
SPI PORT
Table 16. ADAU1702 SPI Address Byte Format
2
By default, the ADAU1702 is in I C mode, but it can be put into
SPI control mode by pulling CLATCH/WP low three times. The
SPI port uses a 4-wire interface, consisting of CLATCH, CCLK,
CDATA, and COUT signals, and is always a slave port. The
CLATCH signal should go low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
CDATA during a low-to-high transition. COUT data is shifted
out of the ADAU1702 on the falling edge of CCLK and should be
clocked into a receiving device, such as a microcontroller, on the
CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal is the serial output data. The COUT
signal remains three-stated until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in Table 17. A timing diagram is shown in Figure 3. Write
all data MSB first. The ADAU1702 cannot be taken out of SPI
mode without a full reset.
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip address
and a R/W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU1702s to share a CLATCH signal, yet continue to
operate independently. When ADDR0 is low, the chip address is
0000000; when it is high, the address is 0000001 (see Table 16).
The LSB of this first byte determines whether the SPI transaction is a read (Logic Level 1) or a write (Logic Level 0).
Bit 0
0
Bit 1
0
Bit 2
0
Bit 3
0
Bit 4
0
Bit 5
0
Bit 6
ADDR0
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the memorie areas or registers. This subaddress is the location
of the appropriate RAM location or register. The MSBs of the
subaddress are zero padded to bring the word to a full two-byte
length.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
format for continuous mode operation is shown in Table 21 and
Table 23 in the Read/Write Data Formats section.
A sample timing diagram for a single-write SPI operation to the
parameter RAM is shown in Figure 26. A sample timing diagram
of a single-read SPI operation is shown in Figure 27. The COUT
pin goes from three-state to being driven at the beginning of
Byte 3. In this example, Byte 0 to Byte 2 contain the addresses,
and the R/W bit and subsequent bytes carry the data.
Table 17. Generic Control Word Format
Byte 0
CHIP_ADR[6:0], R/W
Byte 2
SUBADR[7:0]
Byte 4 1
Data
Byte 3
Data
Continues to end of data.
CLATCH
CDATA
BYTE 0
BYTE 1
BYTE 2
05798-026
CCLK
BYTE 3
Figure 26. SPI Write to ADAU1702 Clocking (Single-Write Mode)
CLATCH
CCLK
CDATA
COUT
BYTE 1
BYTE 0
BYTE 2
HIGH-Z
DATA
Figure 27. SPI Read from ADAU1702 Clocking (Single-Read Mode)
Rev. C | Page 26 of 52
DATA
HIGH-Z
05798-027
1
Byte 1
0000, SUBADR[11:8]
Bit 7
R/W
ADAU1702
SELF-BOOT
EEPROM Format
On power-up, the ADAU1702 can load a program and a set
of parameters that have been saved in an external EEPROM.
Combined with the auxiliary ADC and the multipurpose pins,
this eliminates the need for a microcontroller in the system. The
self-booting is accomplished by the ADAU1702 acting as a master
on the I2C bus on startup, which occurs when the SELFBOOT
pin is set high. The ADAU1702 cannot self-boot in SPI mode.
The EEPROM data contains a sequence of messages. Each
discrete message is one of the seven types defined in Table 18
and consists of a sequence of one or more bytes. The first byte
identifies the message type. Bytes are written MSB first. Most
messages are block write (0x01) types, which are used for writing
to the ADAU1702 program RAM, parameter RAM, and control
registers.
The maximum necessary EEPROM size for program and parameters is 6688 bytes, or just over 6.5 kB. This does not include
register settings or overhead bytes, but such factors do not add a
significant number of bytes. This much memory is only needed
if the program RAM (512 × five bytes), parameter RAM (1024 ×
four bytes), and interface registers (8 × four bytes) are completely
full. Most applications do not use the full program and parameter
RAMs, thus, an 8 kB EEPROM should be sufficient.
The body of the message following the message type should
start with a 0x00 byte; this is the chip address. As with all other
control port transactions, following the chip address is a two-byte
register/memory address field.
A self-boot operation is triggered on the rising edge of RESET
when the SELFBOOT and WP pins are set high. The ADAU1702
reads the program, parameters, and register settings from the
EEPROM. After the ADAU1702 finishes self-booting, additional
messages can be sent to the ADAU1702 on the I2C bus, although
this typically is not necessary in a self-booting application. In
self-boot mode, the I2C device address is 0x68 for a write and
0x69 for a read. The ADDRx pins have different functions
when the chip is in this mode, so the settings on them can be
ignored.
The ADAU1702 does not self-boot if WP is set low. Holding
this pin low allows the EEPROM to be programmed in-circuit.
The WP pin is pulled low (it typically has a resistor pull-up) to
enable writes to the EEPROM, but this in turn disables the selfboot function until the WP pin is returned high.
The ADAU1702 is a master on the I2C bus during self-boot and
writeback. Although it is uncommon for an application using
self-boot to also have a microcontroller connected to the control
lines, care should be taken that no other device tries to write to the
I2C bus during self-boot or writeback. The ADAU1702 generates
SCL at 8 × fS; therefore, for a fS of 48 kHz, SCL runs at 384 kHz.
SCL has a duty cycle of 3/8 in accordance with the I2C specification.
The ADAU1702 reads from EEPROM Chip Address 0xA1. The
LSBs of the addresses of some EEPROMs are pin configurable;
in most cases, these pins should be tied low to set this address.
Figure 28 shows an example of what should be stored in the
EEPROM, starting with EEPROM Address 0. In this example,
the interface registers are first set to control port write mode
(Line 1), which is followed by 18 no operation (no op) bytes
(Line 2 to Line 4) so that the interface register data appears on
Page 2 of the EEPROM. Next, follows the write header (Line 4)
and then 32 bytes of interface register data (Line 5 to Line 8).
Finally, the program RAM data, starting at Address 0x04, 0x00 is
written (Line 9 to Line 11). In this example, the program length
is 70 words, or 350 bytes; therefore, 332 additional bytes are
included in the EEPROM but are not shown in Figure 28.
Writeback
A writeback occurs when the WB pin is triggered and data is
written to the EEPROM from the ADAU1702. This function is
typically used to save the volume setting and other parameter
settings to the EEPROM immediately prior to power being
removed from the system. A rising edge on the WB pin triggers
a writeback when the device is in self-boot mode, unless a message
to set the WB to the falling edge sensitive (0x05) is contained in
the self-boot message sequence. Only one writeback takes place
unless a message to set multiple writebacks (0x04) is contained
in the self-boot message sequence. The WP pin is pulled low
when a writeback is triggered to allow writing to the EEPROM.
The ADAU1702 is only capable of writing back the contents of
the interface registers to the EEPROM. These registers are usually
set by the DSP program, but can also be written to directly after
setting Bit 6 of the core control register. The parameter settings
that the user wants to save are configured in SigmaStudio.
Rev. C | Page 27 of 52
ADAU1702
The writeback function writes data from the ADAU1702
interface registers to the second page of the self-boot EEPROM,
Address 32 to Address 63. Starting at EEPROM Address 26
(so that the interface register data begins at Address 32), the
EEPROM should be programmed with six bytes—the message
byte (0x01), two length bytes, the chip address (0x00), and the
two-byte subaddress for the interface registers (0x08 0x00).
There must be a message to the DSP core control register to
enable writing to the interface registers prior to the interface
register data in the EEPROM; store this in EEPROM Address 0.
No op messages (0x03) can be used in between messages to
ensure that these conditions are met.
The ADAU1702 writes to EEPROM Chip Address 0xA0. The
LSBs of the addresses of some EEPROMs are pin configurable; in
most cases, these pins should be tied low to set the address to 0xA0.
The maximum number of bytes that is written back from the
ADAU1702 is 35 (eight four-byte interface registers plus three
bytes of EEPROM-addressing overhead). With SCL running at
384 kHz, the writeback operation takes approximately 73 μs to
complete after being triggered. Ensure that sufficient power is
available to the system to allow enough time for a writeback to
complete, especially if the WB signal is triggered from a falling
decreasing power supply voltage.
Table 18. EEPROM Message Types
Message ID
0x00
0x01
Message Type
End
Write
0x02
0x03
0x04
0x05
0x06
Delay
No operation executed
Set multiple writeback
Set WB to falling edge sensitive
End and wait for writeback
0x01
0x00
WRITE
0x03
0x05
LENGTH
0x03
0x00
0x08
DEVICE
ADDRESS
0x03
Following Bytes
None
Two bytes indicating message length followed by appropriate
number of data bytes
Two bytes for delay
None
None
None
None
0x03
0x1C
CORE CONTROL REGISTER
ADDRESS
0x03
0x00
0x40
CORE CONTROL REGISTER
DATA
0x03
0x03
0x03
0x03
0x03
0x03
0x08
0x00
NO-OP BYTES
0x03
0x03
0x03
0x03
0x03
NO-OP BYTES
0x03
0x03
NO-OP BYTES
0x00
0x01
0x00
WRITE
0x00
0x00
0x23
LENGTH
0x00
0x00
DEVICE
ADDRESS
0x00
INTERFACE REGISTER
ADDRESS
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
INTERFACE REGISTER DATA
0x00
0x00
0x00
0x00
0x00
INTERFACE REGISTER DATA
0x00
0x00
0x00
0x00
0x00
INTERFACE REGISTER DATA
0x00
0x00
0x00
0x00
0x00
INTERFACE REGISTER DATA
0x01
0x001
WRITE
0x00
0x61
LENGTH
0x00
0x00
DEVICE
ADDRESS
0x01
0x00
0x04
PROGRAM RAM ADDRESS
0x00
PROGRAM RAM DATA
0x00
0xE8
0x01
0x00
0x08
0x00
0x00
0x00
0x00
0x00
0x01
PROGRAM RAM DATA (CONTINUES FOR 332 MORE BYTES)
Figure 28. EEPROM Data Example
Rev. C | Page 28 of 52
05798-039
PROGRAM RAM DATA
ADAU1702
SIGNAL PROCESSING
Many of the signal processing functions are coded using full,
56-bit, double precision arithmetic data. The input and output
word lengths of the DSP core are 24 bits. Four extra headroom
bits are used in the processor to allow internal gains of up to
24 dB without clipping. Additional gains can be achieved by
initially scaling down the input signal in the DSP signal flow.
NUMERIC FORMATS
DSP systems commonly use a standard numeric format.
Fractional number systems are specified by an A.B format,
where A is the number of bits to the left of the decimal point
and B is the number of bits to the right of the decimal point.
The ADAU1702 uses the same numeric format for both the
parameter and data values. The format follows in the Numerical
Format: 5.23 section.
Numerical Format: 5.23
clips the top four bits of the signal to produce a 24-bit output
with a range of 1.0 (minus 1 LSB) to −1.0. Figure 29 shows the
maximum signal levels at each point in the data flow in both
binary and decibel levels.
4-BIT SIGN EXTENSION
DATA IN
1.23
(0dB)
SERIAL
PORT
1.23
(0dB)
SIGNAL
PROCESSING
(5.23 FORMAT)
5.23
(24dB)
DIGITAL
CLIPPER
5.23
(24dB)
1.23
(0dB)
05798-028
The ADAU1702 is designed to provide all audio signal processing
functions commonly used in stereo or multichannel playback
systems. The signal processing flow is designed using the
SigmaStudio software, which allows graphical entry and realtime control of all signal processing functions.
Figure 29. Numeric Precision and Clipping Structure
PROGRAMMING
On power-up, the ADAU1702 default program passes the
unprocessed input signals to the outputs (shown in Figure 13),
but the outputs are muted by default (see the Power-Up Sequence
section). There are 512 instruction cycles per audio sample,
resulting in about 25 MIPS available. The SigmaDSP runs in a
stream-oriented manner, meaning that all 512 instructions are
executed each sample period. The ADAU1702 can also be set up to
accept double- or quad-speed inputs by reducing the number of
instructions per sample that are set in the core control register.
The part can be easily programmed using SigmaStudio (Figure 30),
a graphical tool provided by Analog Devices. No knowledge of
writing line-level DSP code is required. More information about
SigmaStudio can be found at www.analog.com.
Linear range: −16.0 to (+16.0 − 1 LSB)
Examples:
1000 0000 0000 0000 0000 0000 0000 = −16.0
1110 0000 0000 0000 0000 0000 0000 = −4.0
1111 1000 0000 0000 0000 0000 0000 = −1.0
1111 1110 0000 0000 0000 0000 0000 = −0.25
1111 1111 0011 0011 0011 0011 0011 = −0.1
1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0)
0000 0000 0000 0000 0000 0000 0000 = 0.0
0000 0000 1100 1100 1100 1100 1101 = 0.1
0000 0010 0000 0000 0000 0000 0000 = 0.25
0000 1000 0000 0000 0000 0000 0000 = 1.0
0010 0000 0000 0000 0000 0000 0000 = 4.0
0111 1111 1111 1111 1111 1111 1111 = (16.0 − 1 LSB).
A digital clipper circuit is used between the output of the DSP
core and the DACs or serial port outputs (see Figure 29). This
Rev. C | Page 29 of 52
05798-029
The serial port accepts up to 24 bits on the input and is signextended to the full 28 bits of the DSP core. This allows internal
gains of up to 24 dB without internal clipping.
Figure 30. SigmaStudio Screen Shot
ADAU1702
RAMS AND REGISTERS
Table 19. RAM Map and Read/Write Modes
Memory
Parameter RAM
Program RAM
Reserved
1
2
Size
1024 × 32
512 × 40
Not applicable
Address Range
0 to 1023 (0x0000 to 0x03FF)
1024 to 1535 (0x0400 to 0x05FF)
1536 to 2047 (0x0600 to 0x07FF) 2
Read
Yes
Yes
No
Write
Yes
Yes
No
Write Modes
Direct write 1 safeload write
Direct write1
Not applicable
Internal registers should be cleared first to avoid clicks/pops.
Addresses 1536 to 2047 (0x0600 to 0x07FF) are reserved RAM locations and data cannot be written to them.
ADDRESS MAPS
DATA RAM
Table 19 shows the RAM map whereas Table 30 shows the
ADAU1702 register map. The address space encompasses a
set of registers and two RAMs: one holds signal processing
parameters and the other holds the program instructions. The
program RAM and parameter RAM are initialized on power-up
from on-board boot ROMs (see the Power-Up Sequence section).
The ADAU1702 data RAM is used to store audio data-words for
processing. For the most part, this process is transparent to the
user. The user cannot address this RAM space, which has a size
of 0.5k words, directly from the control port.
All RAMs and registers have a default value of all 0s, except for
the program RAM, which is loaded with the default program
(see the Initialization section).
PARAMETER RAM
The parameter RAM is 32 bits wide and occupies Address 0
to Address 1023. Each parameter is padded with four 0s before
the MSB to extend the 28-bit word to a full 4-byte width. The
parameter RAM is initialized to all 0s on power-up. The data
format of the parameter RAM is twos complement, 5.23.
This means that the coefficients can range from +16.0 (minus
1 LSB) to −16.0, with 1.0 represented by the binary word,
0000 1000 0000 0000 0000 0000 0000, or by the hexadecimal
word, 0x00 0x80 0x00 0x00.
The parameter RAM can be written using one of the two
following methods: a direct read/write or a safeload write.
Direct Read/Write
The direct read/write method allows direct access to the program
RAM and parameter RAM. This mode of operation is typically
used when loading a new RAM using burst mode addressing. The
clear registers bit in the core control register should be set to 0
using this mode to prevent any clicks or pops in the outputs. Note
that this mode can be used during live program execution, but
because there is no handshaking between the core and the control
port, the parameter RAM is unavailable to the DSP core during
control writes, resulting in clicks and pops in the audio stream.
Safeload Write
Up to five safeload registers can be loaded with the parameter
RAM address and data. The data is then transferred to the
requested address when the RAM is not busy. This method can
be used for dynamic updates while live program material is
playing through the ADAU1702. For example, a complete
update of one biquad section can occur in one audio frame
while the RAM is not busy. This method is not available for
writing to the program RAM or control registers.
Data RAM utilization should be considered when implementing
blocks that require large amounts of data RAM space, such as
delays. The SigmaDSP core processes delay times in one sample
increments; therefore, the total pool of delay available to the user
equals 512 multiplied by the sample period. For a fS of 48 kHz,
the pool of available delay is a maximum of about 10 ms. In
practice, this much data memory is not available to the user
because every block in a design uses a few data memory locations
for its processing. In most DSP programs, this does not significantly impact the total delay time. The SigmaStudio compiler
manages the data RAM and indicates if the number of addresses
needed in the design exceeds the maximum available.
READ/WRITE DATA FORMATS
The read/write formats of the control port are designed to
be byte oriented. This allows easy programming of common
microcontroller chips. To fit into a byte oriented format, 0s are
appended to the data fields before the MSB to extend the dataword to eight bits. For example, 28-bit words written to the
parameter RAM are appended with four leading 0s to equal
32 bits (four bytes); 40-bit words written to the program RAM
are not appended with 0s because they are already a full five bytes.
These zero padded data fields are appended to a 3-byte field
consisting of a 7-bit chip address, a read/write bit, and an 11-bit
RAM/register address. The control port knows how many data
bytes to expect based on the address given in the first three bytes.
The total number of bytes for a single location write command
can vary from four bytes (for a control register write) to eight
bytes (for a program RAM write). Burst mode can be used to fill
contiguous register or RAM locations. A burst mode write begins
by writing the address and data of the first RAM or register location
to be written. Rather than ending the control port transaction
(by issuing a stop command in I2C mode or by bringing the
CLATCH signal high in SPI mode after the data-word), as is
done in a single address write, the next data-word can be
immediately written without specifying its address. The
ADAU1702 control port auto-increments the address of each write
even across the boundaries of the different RAMs and registers.
Table 21 and Table 23 show examples of burst mode writes.
Rev. C | Page 30 of 52
ADAU1702
Table 20. Parameter RAM Read/Write Format (Single Address)
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
000000, PARAM_ADR[9:8]
Byte 2
PARAM_ADR[7:0]
Byte 3
0000, PARAM[27:24]
Bytes[4:6]
PARAM[23:0]
Table 21. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
000000, PARAM_ADR[9:8]
Byte 2
PARAM_ADR[7:0]
Byte 3
0000, PARAM[27:24]
Bytes[4:6]
PARAM[23:0]
<—PARAM_ADR—>
Bytes[7:10]
Bytes[11:14]
PARAM_ADR + 1
PARAM_ADR + 2
Table 22. Program RAM Read/Write Format (Single Address)
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
00000, PROG_ADR[10:8]
Byte 2
PROG_ADR[7:0]
Bytes[3:7]
PROG[39:0]
Table 23. Program RAM Block Read/Write Format (Burst Mode)
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
00000, PROG_ADR[10:8]
Byte 2
PROG_ADR[7:0]
Bytes[3:7]
PROG[39:0]
<—PROG_ADR—>
Bytes[8:12]
Bytes[13:17]
PROG_ADR + 1
PROG_ADR + 2
Table 24. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1)
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
0000, REG_ADR[11:8]
Byte 2
REG_ADR[7:0]
Byte 3
Data[15:8]
Byte 4
Data[7:0]
Table 25. Control Register Read/Write Format (RAM Configuration, Serial Input)
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
0000, REG_ADR[11:8]
Byte 2
REG_ADR[7:0]
Byte 3
Data[7:0]
Table 26. Data Capture Register Write Format
Byte 0
CHIP_ADR[6:0], W/R
1
2
Byte 1
0000,
DATA_CAPTURE_ADR[11:8]
Byte 2
DATA_CAPTURE_ADR[7:0]
Byte 3
000,
PROGCOUNT[10:6] 1
Byte 4
PROGCOUNT[5:0]1,
REGSEL[1:0] 2
PROGCOUNT[10:0] is the value of the program counter when the data capture occurs (the table of values is generated by the SigmaStudio compiler).
REGSEL[1:0] selects one of four registers (see the 2074 to 2075 (0x081A to 0x081B)—Data Capture Registers section).
Table 27. Data Capture (Control Port Readback) Register Read Format
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
0000, DATA_CAPTURE_ADR[11:8]
Byte 2
DATA_CAPTURE_ADR[7:0]
Bytes[3:5]
Data[23:0]
Table 28. Safeload Address Register Write Format
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
0000, SAFELOAD_ADR[11:8]
Byte 2
SAFELOAD_ADR[7:0]
Byte 3
000000, PARAM_ADR[9:8]
Byte 4
PARAM_ADR[7:0]
Table 29. Safeload Data Register Write Format
Byte 0
CHIP_ADR[6:0], W/R
Byte 1
0000, SAFELOAD_ADR[11:8]
Byte 2
SAFELOAD_ADR[7:0]
Rev. C | Page 31 of 52
Byte 3
00000000
Byte 4
0000, Data[27:24]
Bytes[5:7]
Data[23:0]
ADAU1702
CONTROL REGISTER MAP
Table 30. Register Map 1
1F
MSB
Register
Address
No.
of
Hex
Dec Bytes Name
0x0800 2048 4
Interface 0[31:16]
Interface 0[15:0]
0x0801 2049 4
Interface 0[31:16]
Interface 0[15:0]
0x0802 2050 4
Interface 0[31:16]
Interface 0[15:0]
0x0803 2051 4
Interface 0[31:16]
Interface 0[15:0]
0x0804 2052 4
Interface 0[31:16]
Interface 0[15:0]
0x0805 2053 4
Interface 0[31:16]
Interface 0[15:0]
0x0806 2054 4
Interface 0[31:16]
Interface 0[15:0]
0x0807 2055 4
Interface 0[31:16]
Interface 0[15:0]
0x0808 2056 2
GPIO pin setting
0x0809 2057 2
Auxiliary ADC Data 0
0x080A 2058 2
Auxiliary ADC Data 1
0x080B 2059 2
Auxiliary ADC Data 2
0x080C 2060 2
Auxiliary ADC Data 3
0x080D 2061 5
Reserved[39:32]
Reserved[31:16]
Reserved[15:0]
0x080E 2062 5
Reserved[39:32]
Reserved[31:16]
Reserved[15:0]
0x080F 2063 5
Reserved[39:32]
Reserved[31:16]
Reserved[15:0]
0x0810 2064 5
Safeload Data 0[39:32]
Safeload Data 0[31:16]
Safeload Data 0[15:0]
0x0811 2065 5
Safeload Data 1[39:32]
Safeload Data 1[31:16]
Safeload Data 1[15:0]
0x0812 2066 5
Safeload Data 2[39:32]
Safeload Data 2[31:16]
Safeload Data 2[15:0]
0x0813 2067 5
Safeload Data 3[39:32]
Safeload Data 3[31:16]
Safeload Data 3[15:0]
0x0814 2068 5
Safeload Data 4[39:32]
Safeload Data 4[31:16]
Safeload Data 4[15:0]
0x0815 2069 2
Safeload Address 0
0x0816 2070 2
Safeload Address 1
0x0817 2071 2
Safeload Address 2
0x0818 2072 2
Safeload Address 3
0x0819 2073 2
Safeload Address 4
0x081A 2074 2
Data Capture 0
0x081B 2075 2
Data Capture 1
0x081C 2076 2
DSP core control
0x081D 2077 1
Reserved
0x081E 2078 2
Serial output control
0x081F 2079 1
Serial input control
D31
D30
D29
D28
D27
D26
D25
D24
D15
0
IF15
0
IF15
0
IF15
0
IF15
0
IF15
0
IF15
0
IF15
0
IF15
0
0
0
0
0
D14
0
IF14
0
IF14
0
IF14
0
IF14
0
IF14
0
IF14
0
IF14
0
IF14
0
0
0
0
0
D13
0
IF13
0
IF13
0
IF13
0
IF13
0
IF13
0
IF13
0
IF13
0
IF13
0
0
0
0
0
D12
0
IF12
0
IF12
0
IF12
0
IF12
0
IF12
0
IF12
0
IF12
0
IF12
0
0
0
0
0
D11
IF27
IF11
IF27
IF11
IF27
IF11
IF27
IF11
IF27
IF11
IF27
IF11
IF27
IF11
IF27
IF11
MP11
AA11
AA11
AA11
AA11
D10
IF26
IF10
IF26
IF10
IF26
IF10
IF26
IF10
IF26
IF10
IF26
IF10
IF26
IF10
IF26
IF10
MP10
AA10
AA10
AA10
AA10
D9
IF25
IF09
IF25
IF09
IF25
IF09
IF25
IF09
IF25
IF09
IF25
IF09
IF25
IF09
IF25
IF09
MP09
AA09
AA09
AA09
AA09
D8
IF24
IF08
IF24
IF08
IF24
IF08
IF24
IF08
IF24
IF08
IF24
IF08
IF24
IF08
IF24
IF08
MP08
AA08
AA08
AA08
AA08
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24
SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08
SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24
SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08
SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24
SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08
SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24
SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08
SD31
SD15
0
0
0
0
0
0
0
RSVD
SD30
SD14
0
0
0
0
0
0
0
RSVD
SD29
SD13
0
0
0
0
0
0
0
GD1
SD28
SD12
0
0
0
0
0
0
0
GD0
0
0
OLRP OBP
SD27
SD11
SA11
SA11
SA11
SA11
SA11
PC09
PC09
RSVD
SD26
SD10
SA10
SA10
SA10
SA10
SA10
PC08
PC08
RSVD
SD25
SD09
SA09
SA09
SA09
SA09
SA09
PC07
PC07
RSVD
SD24
SD08
SA08
SA08
SA08
SA08
SA08
PC06
PC06
AACW
M/S
OBF1 OBF0 OLF1
Rev. C | Page 32 of 52
D39
D23
D38
D22
D37
D21
D36
D20
D7
IF23
IF07
IF23
IF07
IF23
IF07
IF23
IF07
IF23
IF07
IF23
IF07
IF23
IF07
IF23
IF07
MP07
AA07
AA07
AA07
AA07
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SD39
SD23
SD07
SD39
SD23
SD07
SD39
SD23
SD07
SD39
SD23
SD07
SD39
SD23
SD07
SA07
SA07
SA07
SA07
SA07
PC05
PC05
GPCW
RSVD
OLF0
0
D6
IF22
IF06
IF22
IF06
IF22
IF06
IF22
IF06
IF22
IF06
IF22
IF06
IF22
IF06
IF22
IF06
MP06
AA06
AA06
AA06
AA06
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SD38
SD22
SD06
SD38
SD22
SD06
SD38
SD22
SD06
SD38
SD22
SD06
SD38
SD22
SD06
SA06
SA06
SA06
SA06
SA06
PC04
PC04
IFCW
RSVD
FST
0
D5
D4
IF21
IF20
IF05
IF04
IF21
IF20
IF05
IF04
IF21
IF20
IF05
IF04
IF21
IF20
IF05
IF04
IF21
IF20
IF05
IF04
IF21
IF20
IF05
IF04
IF21
IF20
IF05
IF04
IF21
IF20
IF05
IF04
MP05 MP04
AA05 AA04
AA05 AA04
AA05 AA04
AA05 AA04
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
SD37 SD36
SD21 SD20
SD05 SD04
SD37 SD36
SD21 SD20
SD05 SD04
SD37 SD36
SD21 SD20
SD05 SD04
SD37 SD36
SD21 SD20
SD05 SD04
SD37 SD36
SD21 SD20
SD05 SD04
SA05 SA04
SA05 SA04
SA05 SA04
SA05 SA04
SA05 SA04
PC03 PC02
PC03 PC02
IST
ADM
RSVD RSVD
TDM MSB2
0
ILP
D35
D19
D34
D18
D33
D17
D3
IF19
IF03
IF19
IF03
IF19
IF03
IF19
IF03
IF19
IF03
IF19
IF03
IF19
IF03
IF19
IF03
MP03
AA03
AA03
AA03
AA03
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SD35
SD19
SD03
SD35
SD19
SD03
SD35
SD19
SD03
SD35
SD19
SD03
SD35
SD19
SD03
SA03
SA03
SA03
SA03
SA03
PC01
PC01
DAM
RSVD
MSB1
IBP
D2
D1
IF18
IF17
IF02
IF01
IF18
IF17
IF02
IF01
IF18
IF17
IF02
IF01
IF18
IF17
IF02
IF01
IF18
IF17
IF02
IF01
IF18
IF17
IF02
IF01
IF18
IF17
IF02
IF01
IF18
IF17
IF02
IF01
MP02 MP01
AA02 AA01
AA02 AA01
AA02 AA01
AA02 AA01
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD RSVD
SD34 SD33
SD18 SD17
SD02 SD01
SD34 SD33
SD18 SD17
SD02 SD01
SD34 SD33
SD18 SD17
SD02 SD01
SD34 SD33
SD18 SD17
SD02 SD01
SD34 SD33
SD18 SD17
SD02 SD01
SA02 SA01
SA02 SA01
SA02 SA01
SA02 SA01
SA02 SA01
PC00 RS01
PC00 RS01
CR
SR1
RSVD RSVD
MSB0 OWL1
M2
M1
LSB
D32
D16
D0
IF16
IF00
IF16
IF00
IF16
IF00
IF16
IF00
IF16
IF00
IF16
IF00
IF16
IF00
IF16
IF00
MP00
AA00
AA00
AA00
AA00
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SD32
SD16
SD00
SD32
SD16
SD00
SD32
SD16
SD00
SD32
SD16
SD00
SD32
SD16
SD00
SA00
SA00
SA00
SA00
SA00
RS00
RS00
SR0
RSVD
OWL0
M0
Default
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00
0x0000
0x0000
0x00
0x0000
0x0000
0x00
0x0000
0x0000
0x00
0x0000
0x0000
0x00
0x0000
0x0000
0x00
0x0000
0x0000
0x00
0x0000
0x0000
0x00
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00
0x0000
0x00
ADAU1702
MSB
Register
Address
Hex
Dec
0x0820 2080
0x0821 2081
0x0822 2082
0x0823
0x0824
0x0825
0x0826
0x0827
1
2083
2084
2085
2086
2087
No.
of
Bytes Name
3
MP Pin Config. 0[23:16]
MP Pin Config. 0[15:0]
3
MP Pin Config. 1[23:16]
MP Pin Config. 1[15:0]
2
Auxiliary ADC and power
control
2
Reserved
2
Auxiliary ADC enable
2
Reserved
2
Oscillator power-down
2
DAC setup
D39
D31 D30 D29 D28 D27 D26 D25 D24 D23
D15 D14 D13 D12 D11 D10 D9
D8
D7
MP53
MP33 MP32 MP31 MP30 MP23 MP22 MP21 MP20 MP13
MP113
MP93 MP92 MP91 MP90 MP83 MP82 MP81 MP80 MP73
RSVD RSVD RSVD RSVD RSVD RSVD FIL1 FIL0 AAPD
D38
D22
D6
MP52
MP12
MP112
MP72
VBPD
D37
D21
D5
MP51
MP11
MP111
MP71
VRPD
D36
D20
D4
MP50
MP10
MP110
MP70
RSVD
D35
D19
D3
MP43
MP03
MP103
MP63
D0PD
D34
D18
D2
MP42
MP02
MP102
MP62
D1PD
D33
D17
D1
MP41
MP01
MP101
MP61
D2PD
LSB
D32
D16
D0
MP40
MP00
MP100
MP60
D3PD
Default
0x00
0x0000
0x00
0x0000
0x0000
RSVD
AAEN
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
OPD
RSVD
RSVD
RSVD
RSVD
RSVD
DS1
RSVD
RSVD
RSVD
RSVD
DS0
0x0000
0x0000
0x0000
0x0000
0x0000
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Shading indicates that registers do not fill these locations; therefore, control bits do not exist in these locations.
Rev. C | Page 33 of 52
ADAU1702
CONTROL REGISTER DETAILS
ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO
0x0807)—INTERFACE REGISTERS
The interface registers are used in self-boot mode to save
parameters that need to be written to the external EEPROM.
The ADAU1702 then recalls these parameters from the
EEPROM after the next reset or power-up. Therefore, system
parameters such as volume and EQ settings can be saved during
power-down and recalled the next time the system is turned on.
There are eight 32-bit interface registers, which allow eight 28-bit
(plus zero padding) parameters to be saved. The parameters to
be saved in these registers are selected in the graphical
programming tools. These registers are updated with their
corresponding parameter RAM data once per sample period.
An edge, which can be set to be either rising or falling, triggers
the ADAU1702 to write the current contents of the interface
registers to the EEPROM. See the Self-Boot section for details.
The user can write directly to the interface registers after the
interface registers control port write mode (IFCW) in the DSP core
control register has been set. In this mode, the data in the registers
is written from the control port, not from the DSP core.
Table 31. Interface Register Bit Map
D31
D15
0
IF15
D30
D14
0
IF14
D29
D13
0
IF13
D28
D12
0
IF12
D27
D11
IF27
IF11
D26
D10
IF26
IF10
D25
D9
IF25
IF09
D24
D8
IF24
IF08
D23
D7
IF23
IF07
D22
D6
IF22
IF06
Table 32.
Bit Name
IF[27:0]
Description
Interface register 28-bit parameter
Rev. C | Page 34 of 52
D21
D5
IF21
IF05
D20
D4
IF20
IF04
D19
D3
IF19
IF03
D18
D2
IF18
IF02
D17
D1
IF17
IF01
D16
D0
IF16
IF00
Default
0x0000
0x0000
ADAU1702
ADDRESS 2056 (0x0808)—GPIO PIN SETTING
REGISTER
This register allows the user to set the GPIO pins through the
control port. High or low settings can be directly written to or
read from this register after setting the GPIO pin to set the
register control port write (GPCW) mode in the core control
register. This register is updated once every LRCLK frame (1/fS).
Table 33. GPIO Pin Setting Register Bit Map
D15
0
D14
0
D13
0
D12
0
D11
MP11
D10
MP10
D9
MP09
D8
MP08
D7
MP07
D6
MP06
D5
MP05
D4
MP04
D3
MP03
Table 34.
Bit Name
MP[11:0]
Description
Setting of multipurpose pin when controlled through SPI or I2C
Rev. C | Page 35 of 52
D2
MP02
D1
MP01
D0
MP00
Default
0x0000
ADAU1702
ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO
0x080C)—AUXILIARY ADC DATA REGISTERS
These registers hold the data generated by the 4-channel
auxiliary ADC. The ADCs have eight bits of precision and can
be extended to 12 bits if filtering is selected via Bits FIL[1:0] of
the auxiliary ADC and power control register. The SigmaDSP
program reads this data as a 1.11 format data-word with a range
of 0 to 1.0. This data-word is mapped to the 5.23 format
parameter word with the four MSBs and 12 LSBs set to 0. A
full-scale code of 255 results in a value of 1.0 in 5.23 format.
These registers can be written to directly if the auxiliary ADC
data registers control port write (AACW) mode bit is set in the
DSP core control register.
Table 35. Auxiliary ADC Data Register Bit Map
D15
0
D14
0
D13
0
D12
0
D11
AA11
D10
AA10
D9
AA09
D8
AA08
D7
AA07
D6
AA06
Table 36.
Bit Name
AA[11:0]
Description
Auxiliary ADC output data, MSB first
Rev. C | Page 36 of 52
D5
AA05
D4
AA04
D3
AA03
D2
AA02
D1
AA01
D0
AA00
Default
0x0000
ADAU1702
After the address and data registers are loaded, set the initiate
safeload transfer bit in the core control register to initiate the
loading into RAM. Each of the five safeload registers takes one of
the 512 core instructions to load into the parameter RAM. The
total program lengths should, therefore, be limited to 507 cycles
(512 minus 5) to ensure that the SigmaDSP core always has at
least five cycles available. The safeload is guaranteed to occur
within one LRCLK period (21 μs for a fS of 48 kHz) of the initiate
safeload transfer bit being set.
ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO
0x0814)—SAFELOAD DATA REGISTERS
Many applications require real-time microcontroller control of
signal processing parameters, such as filter coefficients, mixer
gains, multichannel virtualizing parameters, or dynamics
processing curves. When controlling a biquad filter, for
example, all of the parameters must be updated at the same
time. Doing so prevents the filter from executing with a mix of
old and new coefficients for one or two audio frames, thus
avoiding temporary instability and transients that may take a
long time to decay. To accomplish this, the ADAU1702 uses
safeload data registers to simultaneously load a set of five 28-bit
values to the desired parameter RAM address. Five registers are
used because a biquad filter uses five coefficients and, as
previously mentioned, it is desirable to do a complete update in
one transaction.
The safeload logic automatically sends data to be loaded into
RAM from only those safeload registers that have been written
to since the last safeload operation. For example, if two parameters
are to be updated in the RAM, only two of the five safeload registers
must be written. When the initiate safeload transfer bit is asserted,
only data from those two registers are sent to the RAM; the other
three registers are not sent to the RAM and may hold old or
invalid data.
The first step in performing a safeload operation is writing the
parameter address to one of the safeload address registers
(Address 2069 to Address 2073). The 10-bit data-word to be
written is the address in parameter RAM to which the safeload
is being performed. After this address is written, the 28-bit
data-word can be written to the corresponding safeload data
register (Address 2064 to Address 2068).
Table 37. Safeload Address and Data Register Mapping
Safeload
Register
0
1
2
3
4
The data formats for these writes are detailed in Table 28 and
Table 29. Table 37 shows how each of the five address registers
maps to its corresponding data register.
Safeload
Address Register
2069
2070
2071
2072
2073
Safeload
Data Register
2064
2065
2066
2067
2068
Table 38. Safeload Registers Bit Map
D31
D15
D30
D14
D29
D13
D28
D12
D27
D11
D26
D10
D25
D9
D24
D8
SD31
SD15
SD30
SD14
SD29
SD13
SD28
SD12
SD27
SD11
SD26
SD10
SD25
SD09
SD24
SD08
D39
D23
D7
SD39
SD23
SD07
D38
D22
D6
SD38
SD22
SD06
D37
D21
D5
SD37
SD21
SD05
D36
D20
D4
SD36
SD20
SD04
D35
D19
D3
SD35
SD19
SD03
D34
D18
D2
SD34
SD18
SD02
D33
D17
D1
SD33
SD17
SD01
D32
D16
D0
SD32
SD16
SD00
Default
0x00
0x0000
0x0000
Table 39.
Bit Name
SD[39:0]
Description
Safeload data. Data (program, parameters, and register contents) to be loaded into the RAMs or
registers.
ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS
Table 40. Safeload Address Registers Bit Map
D15
0
D14
0
D13
0
D12
0
D11
SA11
D10
SA10
D9
SA09
D8
SA08
D7
SA07
D6
SA06
D5
SA05
D4
SA04
D3
SA03
D2
SA02
D1
SA01
D0
SA00
Table 41.
Bit Name
SA[11:0]
Description
Safeload address. Address of data that is to be loaded into the RAMs or registers.
Rev. C | Page 37 of 52
Default
0x0000
ADAU1702
The captured data is in 5.19, twos complement data format,
which comes from the internal 5.23 data-word with the four
LSBs truncated.
ADDRESS 2074 TO ADDRESS 2075 (0x081A TO
0x081B)—DATA CAPTURE REGISTERS
The ADAU1702 data capture feature allows the data at any node
in the signal processing flow to be sent to one of two readable
registers. This feature is useful for monitoring and displaying
information about internal signal levels or compressor/limiter
activity.
The data that must be written to set up the data capture is a
concatenation of the 10-bit program count index with the 2-bit
register select field. The capture count and register select values
that correspond to the desired point to be monitored in the
signal processing flow can be found in a file output from the
program compiler. The capture registers can be accessed by
reading from Location 2074 and Location 2075. The format for
writing and reading to the data capture registers is shown in
Table 26 and Table 27.
For each of the data capture registers, a capture count and a
register select must be set. The capture count is a number
between 0 and 1023 that corresponds to the program step
number where the capture is to occur. The register select field
programs one of four registers in the DSP core that transfers
this information to the data capture register when the program
counter reaches this step.
Table 42. Safeload Data Registers Bit Map
D15
0
D14
0
D13
0
D12
0
D11
PC09
D10
PC08
D9
PC07
D8
PC06
D7
PC05
D6
PC04
D5
PC03
Table 43.
Bit Name
PC[9:0]
RS[1:0]
Description
10-bit program counter address
Select the register to be transferred to the data capture output
Setting
Function
00
Multiplier X input (MULT_X_INPUT)
01
Multiplier Y input (MULT_Y_INPUT)
10
Multiplier accumulator output (MAC_OUT)
11
Accumulator feedback (ACCUM_FBACK)
Rev. C | Page 38 of 52
D4
PC02
D3
PC01
D2
PC00
D1
RS01
D0
RS00
Default
0x0000
ADAU1702
ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER
Table 44. DSP Core Control Register Bit Map
D15
RSVD
D14
RSVD
D13
GD1
D12
GD0
D11
RSVD
D10
RSVD
D9
RSVD
D8
AACW
D7
GPCW
D6
IFCW
D5
IST
D4
ADM
D3
DAM
D2
CR
D1
SR1
D0
SR0
Default
0x0000
Table 45. DSP Core Control Register
Bit Name
GD[1:0]
AACW
GPCW
IFCW
IST
ADM
DAM
CR
SR[1:0]
Description
GPIO debounce control. These bits set the debounce time of the multipurpose pins, which are set as GPIO inputs.
Setting
Time (ms)
00
20
01
40
10
10
11
5
Auxiliary ADC data registers control port write mode. Setting this bit allows data to be written directly to the
auxiliary ADC data registers (Address 2057 to Address 2060) from the control port. When this bit is set, the
auxiliary ADC data registers ignore the settings on the multipurpose pins.
GPIO pin setting register control port write mode. When this bit is set, the GPIO pin setting register (Address 2056)
can be written to directly from the control port and this register ignores the input settings on the multipurpose pins.
Interface registers control port write mode. When this bit is set, data can be written directly to the interface
registers (Address 2048 to Address 2055) from the control port. In that state, the interface registers are not
written from the SigmaDSP program.
Initiate safeload transfer. Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit is
automatically cleared when the operation is complete. There are five safeload register pairs (address/data);
only those registers that have been written since the last safeload event are transferred to the parameter RAM.
Mute ADCs. This bit mutes the output of the ADCs. The bit defaults to 0 and is active low; therefore, it must be
set to 1 to transmit audio signals from the ADCs.
Mute DACs. This bit mutes the output of the DACs. The bit defaults to 0 and is active low; therefore, it must be
set to 1 to transmit audio signals from the DACs.
Clear internal registers to 0. This bit defaults to 0 and is active low. It must be set to 1 for a signal to pass
through the SigmaDSP core.
Sample rate. These bits set the number of DSP instructions for every sample and the sample rate at which the
ADAU1702 operates. At the default setting of 1×, there are 512 instructions per audio sample. This setting
should be used with sample rates such as 48 kHz and 44.1 kHz.
At the 2× setting, the number of instructions per frame is halved to 256 and the ADCs and DACs nominally run
at a 96 kHz sample rate.
At the 4× setting, there are 128 instructions per cycle and the converters run at a 192 kHz sample rate.
Setting Function
00
1× (512 instructions)
01
2× (256 instructions)
10
4× (128 instructions)
11
Reserved
Rev. C | Page 39 of 52
ADAU1702
ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
Table 46. Serial Output Control Register Bit Map
D15
0
D14
0
D13
OLRP
D12
OBP
D11
M/S
D10
OBF1
D9
OBF0
D8
OLF1
D7
OLF0
D6
FST
D5
TDM
D4
MSB2
D3
MSB1
D2
MSB0
D1
OWL1
D0
OWL0
Default
0x0000
Table 47.
Bit Name
OLRP
OBP
M/S
OBF[1:0]
OLF[1:0]
FST
TDM
MSB[2:0]
OWL[1:0]
Description
OUTPUT_LRCLK polarity. When this bit is set to 0, the left channel data is clocked when OUTPUT_LRCLK is low
and the right channel data is clocked when OUTPUT_LRCLK is high. When this bit is set to 1, the right channel
data is clocked when OUTPUT_LRCLK is low and the left channel data is clocked when OUTPUT_LRCLK is high.
OUTPUT_BCLK polarity. This bit controls on which edge of the bit clock the output data is clocked. Data
changes on the falling edge of OUTPUT_BCLK when this bit is set to 0, and it changes on the rising edge
when this bit is set to 1.
Master/slave. This bit sets whether the output port is a clock master or slave. The default setting is slave; on
power-up, the OUTPUT_BCLK and OUTPUT_LRCLK pins are set as inputs until this bit is set to 1, at which time
they become clock outputs.
OUTPUT_BCLK frequency (master mode only). When the output port is being used as a clock master, these
bits set the frequency of the output bit clock, which is divided down from an internal 1024 × fS clock (49.152 MHz
for a fS of 48 kHz).
Setting
Function
00
Internal clock/16
01
Internal clock/8
10
Internal clock/4
11
Internal clock/2
OUTPUT_LRCLK frequency (master mode only). When the output port is used as a clock master, these bits set
the frequency of the output word clock on the OUTPUT_LRCLK pins, which is divided down from an internal
1024 × fS clock (49.152 MHz for a fS of 48 kHz).
Setting
Function
00
Internal clock/1024
01
Internal clock/512
10
Internal clock/256
11
Reserved
Frame sync type. This bit sets the type of signal on the OUTPUT_LRCLK pins. When this bit is set to 0, the
signal is a word clock with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of
one bit clock at the beginning of the data frame.
TDM enable. Setting this bit to 1 changes the output port from four serial stereo outputs to a single 8-channel TDM
output stream on the SDATA_OUT0 pin (MP6).
MSB position. These three bits set the position of the MSB of data with respect to the LRCLK edge. The data
output of the ADAU1702 is always MSB first.
Setting
Function
000
Delay by 1
001
Delay by 0
010
Delay by 8
011
Delay by 12
100
Delay by 16
101
Reserved
111
Reserved
Output word length. These bits set the word length of the output data-word. All bits following the LSB are set to 0.
OWL[1:0]
Setting
00
24 bits
01
20 bits
10
16 bits
11
Reserved
Rev. C | Page 40 of 52
ADAU1702
ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
Table 48. Serial Input Control Register Bit Map
D7
0
D6
0
D5
0
D4
ILP
D3
IBP
D2
M2
D1
M1
D0
M0
Default
0x00
Table 49. Serial Input Control Register Bit Descriptions
Bit Name
ILP
IBP
M[2:0]
Description
INPUT_LRCLK polarity. When this bit is set to 0, the left channel data on the SDATA_INx pins is clocked when
INPUT_LRCLK is low and the right channel data is clocked when INPUT_LRCLK is high. When this bit is set to 1,
the clocking of these channels is reversed. In TDM mode, when this bit is set to 0, data is clocked in starting with
the next appropriate BCLK edge (set in Bit 3 of this register) after a falling edge on the INPUT_LRCLK pin. When
this bit is set to 1 and the device is running in TDM mode, the input data is valid on the BCLK edge after a rising
edge on the word clock (INPUT_LRCLK). INPUT_LRCLK can also operate with a pulse input, rather than a clock;
in this case, the first edge of the pulse is used by the ADAU1702 to start the data frame. When this polarity bit is
set to 0, use a low pulse; when the bit it set to 1, use a high pulse.
INPUT_BCLK polarity. This bit controls on which edge of the bit clock the input data changes and on which
edge it is clocked. Data changes on the falling edge of INPUT_BCLK when this bit is set to 0 and on the rising edge
when this bit is set at 1.
Serial input mode. These two bits control the data format that the input port expects to receive. Bit 3 and Bit 4
of this control register override the settings of Bits[2:0]; therefore, all four bits must be changed together for
proper operation in some modes. The clock diagrams for these modes are shown in Figure 32, Figure 33, and
Figure 34. Note that for left-justified and right-justified modes, the LRCLK polarity is high and then low, which is
the opposite of the default setting for ILP.
When these bits are set to accept a TDM input, the ADAU1702 data starts after the edge defined by ILP. Input
the ADAU1702 TDM data stream on Pin SDATA_IN0. Figure 35 shows a TDM stream with a high-to-low triggered
LRCLK and data changing on the falling edge of the BCLK. The ADAU1702 expects the MSB of each data slot to
be delayed by one BCLK from the beginning of the slot, as it would in stereo I2S format. In TDM mode, Channel 0
to Channel 3 are in the first half of the frame, and Channel 4 to Channel 7 are in the second half. Figure 36 shows
an example of a TDM stream running with a pulse word clock, which is used to interface to ADI codecs in auxiliary
mode. To work in this mode with either the input or output serial ports, set the ADAU1702 to begin the frame
on the rising edge of LRCLK, to change data on the falling edge of BCLK, and to delay the MSB position from the
start of the word clock by one BCLK.
Setting
Function
000
I2S
001
Left justified
010
TDM
011
Right justified, 24 bits
100
Right justified, 20 bits
101
Right justified, 18 bits
110
Right justified, 16 bits
111
Reserved
Rev. C | Page 41 of 52
ADAU1702
different MP pin. Table 52 lists the function of each nibble
setting within the MP pin configuration registers. Each MP pin
has a 4-bit configuration, the MSB of which inverts the input to,
or the output from, the pin. The internal pull-up resistor (approximately 10 kΩ) of each MP pin is enabled when it is set as a
digital input (either a GPIO input or a serial data port input).
ADDRESS 2080 TO ADDRESS 2081 (0x0820 TO
0x0821)—MULTIPURPOSE PIN CONFIGURATION
REGISTERS
Each multipurpose pin can be set to different functions from
these registers (2080 to 2081). The two 3-byte registers are
broken up into 12 4-bit (nibble) sections that each control a
Table 50. Register 2080 Bit Map
D15
D14
D13
D12
D11
D10
D9
D8
MP33
MP32
MP31
MP30
MP23
MP22
MP21
MP20
D23
D7
MP53
MP13
D22
D6
MP52
MP12
D21
D5
MP51
MP11
D20
D4
MP50
MP10
D19
D3
MP43
MP03
D18
D2
MP42
MP02
D17
D1
MP41
MP01
D16
D0
MP40
MP00
Default
0x00
0x0000
D19
D3
MP103
MP63
D18
D2
MP102
MP62
D17
D1
MP101
MP61
D16
D0
MP100
MP60
Default
0x00
0x0000
Table 51. Register 2081 Bit Map
D15
D14
D13
D12
D11
D10
D9
D8
MP93
MP92
MP91
MP90
MP83
MP82
MP81
MP80
D23
D7
MP113
MP73
D22
D6
MP112
MP72
D21
D5
MP111
MP71
Table 52. Multipurpose Configuration Registers Bit Descriptions
Bit Name
MPx[3:0]
Description
These bits set the function of each multipurpose pin.
Setting
Function
1111
Auxiliary ADC input (see Table 61)
1110
Reserved
1101
Reserved
1100
Serial data port—inverted (see Table 63)
1011
Open-collector output—inverted
1010
GPIO output—inverted
1001
GPIO input, no debounce—inverted
1000
GPIO input, debounced—inverted
0111
Not applicable
0110
Reserved
0101
Reserved
0100
Serial data port (see Table 63)
0011
Open-collector output
0010
GPIO output
0001
GPIO input, no debounce
0000
GPIO input, debounced
Rev. C | Page 42 of 52
D20
D4
MP110
MP70
ADAU1702
ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER
Table 53. Auxiliary ADC and Power Control Register Bit Map
D15
RSVD
D14
RSVD
D13
RSVD
D12
RSVD
D11
RSVD
D10
RSVD
D9
FIL1
D8
FIL0
D7
AAPD
D6
VBPD
D5
VRPD
D4
RSVD
D3
D0PD
D2
D1PD
D1
D2PD
D0
D3PD
Default
0x0000
Table 54. Auxiliary ADC and Power Control Register Bit Descriptions
Bit Name
FIL[1:0]
AAPD
VBPD
VRPD
D0PD
D1PD
D2PD
D3PD
Description
Auxiliary ADC filtering
Setting
Function
00
4-bit hysteresis (12-bit level)
01
5-bit hysteresis (12-bit level)
10
Filter and hysteresis bypassed
11
Low-pass filter bypassed
ADC power-down (both ADCs)
Voltage reference buffer power-down
Voltage reference power-down
DAC0 power-down
DAC1 power-down
DAC2 power-down
DAC3 power-down
ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER
Table 55. Auxiliary ADC Enable Register Bit Map
D15
AAEN
D14
RSVD
D13
RSVD
D12
RSVD
D11
RSVD
D10
RSVD
D9
RSVD
D8
RSVD
D7
RSVD
D6
RSVD
D5
RSVD
D4
RSVD
D3
RSVD
D2
RSVD
D1
RSVD
D0
RSVD
Default
0x0000
D4
RSVD
D3
RSVD
D2
OPD
D1
RSVD
D0
RSVD
Default
0x0000
Table 56. Auxiliary ADC Enable Register Bit Descriptions
Bit Name
AAEN
Description
Enable the auxiliary ADC
ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER
Table 57. Oscillator Power-Down Register Bit Map
D15
RSVD
D14
RSVD
D13
RSVD
D12
RSVD
D11
RSVD
D10
RSVD
D9
RSVD
D8
RSVD
D7
RSVD
D6
RSVD
Table 58. Oscillator Power-Down Register Bit Descriptions
Bit Name
OPD
Description
Oscillator power-down. This bit powers down the oscillator.
Rev. C | Page 43 of 52
D5
RSVD
ADAU1702
ADDRESS 2087 (0x0827)—DAC SETUP
To properly initialize the DACs, set Bits DS[1:0] in this register to 01.
Table 59. DAC Setup Bit Map
D15
RSVD
D14
RSVD
D13
RSVD
D12
RSVD
D11
RSVD
D10
RSVD
D9
RSVD
D8
RSVD
D7
RSVD
D6
RSVD
Table 60.
Bit Name
DS[1:0]
Description
DAC setup
Setting
00
01
10
11
Function
Reserved
Initialize DACs
Reserved
Reserved
Rev. C | Page 44 of 52
D5
RSVD
D4
RSVD
D3
RSVD
D2
RSVD
D1
DS1
D0
DS0
Default
0x0000
ADAU1702
MULTIPURPOSE PINS
The ADAU1702 has 12 multipurpose (MP) pins that can be
individually programmed for use as serial data inputs, serial
data outputs, digital control inputs/outputs to and from the
SigmaDSP core, or inputs to the 4-channel auxiliary ADC. These
pins allow the ADAU1702 to be used with external ADCs and
DACs. They also use analog or digital inputs to control settings
such as volume control, or use output digital signals to drive
LED indicators. Every MP pin has an internal 15 kΩ pull-up
resistor.
AUXILIARY ADC
The ADAU1702 has a 4-channel, auxiliary, 8-bit ADC that can
be used in conjunction with a potentiometer to control volume,
tone, or other parameter settings in the DSP program. Each of
the four channels is sampled at the audio sampling frequency (fS).
Full-scale input on this ADC is 3.0 V, thus the step size is
approximately 12 mV (3.0 V/256 steps). The input resistance of
the ADC is approximately 30 kΩ. Table 61 indicates which four
MP pins are mapped to the four channels of the auxiliary ADC.
The auxiliary ADC is enabled for those pins by writing 1111 to the
appropriate portion of the multipurpose pin configuration
registers.
The auxiliary ADC is turned on by setting the AAEN bit of the
auxiliary ADC enable register (see Table 56).
Noise on the ADC input can cause the digital output to change
constantly by a few LSBs. If the auxiliary ADC is used to control
volume, this constant change causes small gain fluctuations. To
avoid this, add a low-pass filter or hysteresis to the auxiliary ADC
signal path by enabling either function in the auxiliary ADC and
power control register (Address 2082), as described in Table 54.
The filter is enabled by default when the auxiliary ADC is
enabled. When data is read from the auxiliary ADC registers,
two bytes (12 bits of data plus zero padded LSBs) are available
because of this filtering.
AUX ADC
INPUT PIN
20kΩ
S2
1.8pF
Table 61. Multipurpose Pin Auxiliary ADC Mapping
Multipurpose Pin
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
Function
Not applicable
Not applicable
ADC1
ADC2
Not applicable
Not applicable
Not applicable
Not applicable
ADC3
ADC0
Not applicable
Not applicable
GENERAL-PURPOSE INPUT/OUTPUT PINS
Use the general-purpose input/output (GPIO) pins as either
inputs or outputs. These pins are readable and are set either
through the control interface or directly by the SigmaDSP core.
When set as inputs, these pins can be used with push-button
switches or rotary encoders to control DSP program settings.
Use digital outputs to drive LEDs or external logic to indicate
the status of internal signals and to control other devices.
Examples of this use include indicating signal overload, signal
present, and button press confirmation.
When set as an output, each pin can typically drive 2 mA. This
is enough current to directly drive some high efficiency LEDs.
Standard LEDs require about 20 mA of current and can be driven
from a GPIO output with an external transistor or buffer. Because
of issues that can arise from simultaneously driving or sinking a
large current on many pins, take care in the application design to
avoid connecting high efficiency LEDs directly to many or all of
the MPx pins. If many LEDs are required, use an external driver.
When the GPIO pins are set as open-collector outputs, they
should be pulled up to a maximum voltage of 3.3 V (the voltage
on IOVDD).
05798-030
S1
10kΩ
PVDD supplies the 3.3 V power for the auxiliary ADC analog
input. The digital core of the auxiliary ADC is powered with the
1.8 V DVDD signal.
SERIAL DATA INPUT/OUTPUT PORTS
Figure 31. Auxiliary ADC Input Circuit
Figure 31 shows the input circuit for the auxiliary ADC. Switch S1
enables the auxiliary ADC and is set by Bit 15 of the auxiliary
ADC enable register. The sampling switch, S2, operates at the
audio sampling frequency.
The auxiliary ADC data registers can be written to directly after
AACW in the DSP core control register has been set. In this
mode, the voltages on the analog inputs are not written into the
registers, but rather the data in the registers is written from the
control port.
The flexible serial data input and output ports of the ADAU1702
can be set to accept or transmit data in 2-channel format or in an
8-channel TDM stream. Data is processed in twos complement,
MSB-first format. The left-channel data field always precedes
the right-channel data field in the 2-channel streams. In TDM
mode, Slot 0 to Slot 3 are in the first half of the audio frame, and
Slot 4 to Slot 7 are in the second half of the frame. TDM mode
allows fewer multipurpose pins to be used, freeing more pins
for other functions. The serial modes are set in the serial output
and serial input control registers.
Rev. C | Page 45 of 52
ADAU1702
The serial data clocks need to be synchronous with the
ADAU1702 master clock input.
The input control register allows control of clock polarity and
data input modes. The valid data formats are I2S, left-justified,
right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In all
modes, except for the right-justified modes, the serial port accepts
an arbitrary number of bits up to a limit of 24. Extra bits do not
cause an error, but they are truncated internally. Proper operation
of the right-justified modes requires that there be exactly 64 BCLKs
per audio frame. The TDM data is input on SDATA_IN0. The
LRCLK in TDM mode can be input to the ADAU1702 either as a
50/50 duty cycle clock or as a bit-wide pulse.
In TDM mode, the ADAU1702 can be a master for 48 kHz and
96 kHz data, but not for 192 kHz data. Table 62 lists the modes
in which the serial output port can function.
Table 62. Serial Output Port Master/Slave Mode Capabilities
fS
48 kHz
96 kHz
192 kHz
2-Channel Modes
(I2S, Left Justified,
Right Justified)
Master and slave
Master and slave
Master and slave
8-Channel TDM
Master and slave
Master and slave
Slave only
the configuration of the corresponding output port is controlled
with the serial output control register (Table 47). The clocks of
the input port function only as slaves, whereas the output port
clocks can be set to function as either masters or slaves. The
INPUT_LRCLK (MP4) and INPUT_BCLK (MP5) pins are
used to clock the SDATA_INx (MP0 to MP3) signals, and the
OUTPUT_LRCLK (MP10) and OUTPUT_BCLK (MP11) pins
are used to clock the SDATA_OUTx (MP6 to MP9) signals.
If an external ADC is connected as a slave to the ADAU1702,
use both the input and output port clocks. The OUTPUT_LRCLK
(MP10) and OUTPUT_BCLK (MP11) pins must be set to master
mode and connected externally to the INPUT_LRCLK (MP4)
and INPUT_BCLK (MP5) pins, as well as to the external ADC
clock input pins. The data is output from the external ADC into
the SigmaDSP on one of the four SDATA_INx pins (MP0 to MP3).
Connections to an external DAC are handled exclusively with the
output port pins. The OUTPUT_LRCLK and OUTPUT_BCLK
pins can be set to function as either masters or slaves, and the
SDATA_OUTx pins are used to output data from the SigmaDSP
to the external DAC.
Table 64 describes the proper configurations for standard audio
data formats.
The output control registers allow the user to control clock
polarities, clock frequencies, clock types, and data format. In
all modes except for the right-justified modes (MSB delayed by
8, 12, or 16 bits), the serial port accepts an arbitrary number of
bits up to a limit of 24. Extra bits do not cause an error, rather,
they are truncated internally. Proper operation of the right-justified
modes requires the LSB to align with the edge of the LRCLK.
The default settings of all serial port control registers correspond
to the 2-channel I2S mode. All register settings apply to both
master and slave modes, unless otherwise noted.
The function of each multipurpose pin in serial data port mode
is listed in Table 63. Pin MP0 to Pin MP5 support digital data
input to the ADAU1702, and Pin MP6 to Pin MP11 handle digital
data output from the DSP. The configuration of the serial data
input port is set in the serial input control register (Table 49), and
Table 63. Multipurpose Pin Serial Data Port Functions
Multipurpose Pin
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
Function
SDATA_IN0/TDM_IN
SDATA_IN1
SDATA_IN2
SDATA_IN3
INPUT_LRCLK (slave only)
INPUT_BCLK (slave only)
SDATA_OUT0/TDM_OUT
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
OUTPUT_LRCLK (master or slave)
OUTPUT_BCLK (master or slave)
Table 64. Data Format Configurations
Format
I2S (Figure 32)
LRCLK Polarity
Frame begins on falling edge
LRCLK
Type
Clock
BCLK Polarity
Data changes on falling edge
Left Justified (Figure 33)
Right Justified (Figure 34)
Frame begins on rising edge
Frame begins on rising edge
Clock
Clock
Data changes on falling edge
Data changes on falling edge
TDM with Clock (Figure 35)
Frame begins on falling edge
Clock
Data changes on falling edge
TDM with Pulse (Figure 36)
Frame begins on rising edge
Pulse
Data changes on falling edge
Rev. C | Page 46 of 52
MSB Position
Delayed from LRCLK edge
by 1 BCLK
Aligned with LRCLK edge
Delayed from LRCLK edge
by 8, 12, or 16 BCLKs
Delayed from start of word clock
by 1 BCLK
Delayed from start of word clock
by 1 BCLK
ADAU1702
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
LSB
MSB
LSB
MSB
05798-031
SDATA
1/FS
2
Figure 32. I S Mode—16 Bits to 24 Bits Per Channel
MSB
LSB
MSB
LSB
05798-032
SDATA
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
1/FS
Figure 33. Left-Justified Mode—16 Bits to 24 Bits Per Channel
RIGHT CHANNEL
SDATA
MSB
LSB
MSB
LSB
05798-033
LEFT CHANNEL
LRCLK
BCLK
1/FS
Figure 34. Right-Justified Mode—16 Bits to 24 Bits Per Channel
LRCLK
256 BCLKs
BCLK
DATA
32 BCLKs
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
MSB–1
MSB–2
05798-034
BCLK
MSB
DATA
Figure 35. TDM Mode
LRCLK
BCLK
MSB TDM
MSB TDM
CH
0
8TH
CH
SLOT 0
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
05798-035
SDATA
32
BCLKs
Figure 36. TDM Mode with Pulse Word Clock
Rev. C | Page 47 of 52
ADAU1702
LAYOUT RECOMMENDATIONS
To minimize stray capacitance, keep all traces in the crystal
oscillator circuit (Figure 14) as short as possible. In addition,
avoid long board traces connected to any of these components
because such traces can affect crystal startup and operation.
PARTS PLACEMENT
Place the ADC input voltage-to-current resistors and the ADC
current set resistor as close as possible to the two, three, and
four input pins.
All 100 nF bypass capacitors, which are recommended for every
analog, digital, and PLL power/ground pair, should be placed as
close as possible to the ADAU1702. Bypass each of the 3.3 V
and 1.8 V signals on the board with a single bulk capacitor
(10 μF to 47 μF).
GROUNDING
Use a single ground plane in the application layout. Place
components in an analog signal path away from digital signals.
Rev. C | Page 48 of 52
ADAU1702
TYPICAL APPLICATION SCHEMATICS
SELF-BOOT MODE
05798-036
U1
ADAU1702
Figure 37. Self-Boot Mode Schematic
Rev. C | Page 49 of 52
ADAU1702
I2C CONTROL
05798-037
U1
ADAU1702
Figure 38. I2C Control Schematic
Rev. C | Page 50 of 52
ADAU1702
SPI CONTROL
05798-038
U1
ADAU1702
Figure 39. SPI Control Schematic
Rev. C | Page 51 of 52
ADAU1702
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.75
0.60
0.45
Figure 40. 48-Lead Low-Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADAU1702JSTZ
ADAU1702JSTZ-RL
EVAL-ADAU1401EBZ
EVAL-ADAU1701MINIZ
1
2
Temperature Range
0°C to +70°C
0°C to +70°C
Package Description
48-Lead LQFP
48-Lead LQFP in 13” Tape and Reel
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
The EVAL-ADAU1401EBZ and the EVAL-ADAU1701MINIZ are used to evaluate the ADAU1702, ADAU1701, and the ADAU1401.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05798-0-6/11(C)
Rev. C | Page 52 of 52
Package Option
ST-48
ST-48
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