Cyclone V SoC开发板原理图

Cyclone V SoC开发板原理图
8
7
6
5
4
NOTES:
E
1. Project Drawing Numbers:
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic Drawing
PCB Film
Bill of Materials
Schematic Design Files
Functional Specification
PCB Layout Guidelines
Assembly Rework
3
REV
DATE
PAGES
E1
07/11/2014
All
2
1
DESCRIPTION
INITIAL REVISION RELEASE
100-0321003-E1
110-0321003-E1
120-0321003-E1
130-0321003-E1
140-0321003-E1
150-0321003-E1
160-0321003-E1
170-0321003-E1
180-0321003-E1
210-0321003-E1
220-0321003-E1
320-0321003-E1
E
Cyclone V SoC FPGA Development Kit Board
PAGE
1
D
C
B
DESCRIPTION
Title, Notes, Block Diag, Rev. History
DESCRIPTION
PAGE
30
Power 3 - 1.5V FPGA
D
2
FPGA Package Top
31
Power 3 - 2.5V FPGA
3
PCI Express Edge Connector
32
Power 3 - 2.5V HPS
4
Cyclone V GX SoC Bank 3,4
33
Power 3 - 1.5V & 1.5V HPS
5
Cyclone V GX SoC Bank 5,6
34
Power 3 - 3.3V HPS
6
Cyclone V GX SoC Bank 7
35
Power 1.1V_HPS , 5.0V , 1.8V
7
Cyclone V GX SoC Bank 8
36
Power 4 - Linear Regulators
8
Cyclone V GX SoC Transceiver Banks
37
Power 6 - Power & Temp Monitor
9
Cyclone V GX SoC Clocks
38
CycloneV GX SOC Power
10
PLL
39
CycloneV GX SOC Ground
11
Cyclone V GX SoC Configuration
40
Decoupling
12
JTAG
41
Changes History
13
1024MB DDR3 ( x32 ) - FPGA
14
1024MB DDR3 ( x32 + ECC ) - HPS
15
FLASH , EPCQ
16
5M2210 System Controller
17
HSMC PORT A
18
10/100/1000 Ethernet - HPS
19
10/100M Ethernet - FPGA
20
SDI Cable Driver , SMA & SMB
21
QSPI FLASH & RESET Circuit
22
USB2.0 & Micro SD Card
23
User I/O , RTC
24
UART , CAN
25
On - Board USB Blaster II
26
FPGA Power Monitor
27
HPS Power Monitor
28
Power 1 - DC I/P & 12V , 3.3V O/P
29
Power 2
A
C
B
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
1
of
1
41
E1
8
7
6
5
4
3
2
1
FPGA Package Top View
E
E
D
D
C
C
B
B
XCVR BANK QR2
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
2
of
1
41
E1
8
7
6
5
4
3
2
1
PCI Express Connector
3.3V
12V
E
E
R554
0_Ohms
12V_EXP
3.3V_EXP
R547
0_Ohms
12V_EXP
12V_EXP
3.3V_EXP
J25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
PCIE_SMBCLK
PCIE_SMBDAT
(9) PCIE_SMBCLK
(9) PCIE_SMBDAT
3.3V
R262
D
4.70K, 1%
PCIE_WAKEn (11)
+12V
+12V
+12V
GND
SMCLK
SMDAT
GND
+3_3V
JTAG_TRSTN
+3_3VAUX
WAKE_N
PRSNT1_N
+12V
+12V
GND
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
+3_3V
+3_3V
PERST_N
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
R271
4.7K
3.3V_EXP
D
(4,11) PCIE_PERSTn
R255
4.70K, 1%
KEY
PCIE_TX_P0(8)
PCIE_TX_N0 (8)
C673
0.1uF
C670
0.1uF
PCIE_TX_C_P0
PCIE_TX_C_N0
PCIE_PRSNT2_X1 (9)
C
PCIE_TX_P1(8)
PCIE_TX_N1 (8)
C662
0.1uF
C656
0.1uF
PCIE_TX_C_P1
PCIE_TX_C_N1
PCIE_TX_P2(8)
PCIE_TX_N2 (8)
C650
0.1uF
C649
0.1uF
PCIE_TX_C_P2
PCIE_TX_C_N2
PCIE_TX_P3(8)
PCIE_TX_N3 (8)
C638
0.1uF
C637
0.1uF
PCIE_TX_C_P3
PCIE_TX_C_N3
PCIE_PRSNT2_X4 (9)
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
RSVD1
GND
X1
GND
REFCLK+
PET0P
REFCLKPET0N
GND
GND
PER0P
PRSNT2_N_X1
PER0N
GND
GND
PET1P
X4
PET1N
GND
GND
PET2P
PET2N
GND
GND
PET3P
PET3N
GND
RSVD3
PRSNT2_N_X4
GND
RSVD2
GND
PER1P
PER1N
GND
GND
PER2P
PER2N
GND
GND
PER3P
PER3N
GND
RSVD4
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
(10) PCIE_REFCLK_SYN_P
(10) PCIE_REFCLK_SYN_N
(8) PCIE_RX_P0
(8) PCIE_RX_N0
(8) PCIE_RX_P1
(8) PCIE_RX_N1
(8) PCIE_RX_P2
(8) PCIE_RX_N2
C
(8) PCIE_RX_P3
(8) PCIE_RX_N3
PCIE-064-02-F-D-TH
B
B
12V_EXP
A
3.3V_EXP
C215
C232
220uF
16V
220uF
16V
C236
47uF
20V
C238
47uF
20V
C687
22uF
25V
C683
22uF
25V
C237
C231
220uF
16V
47uF
20V
C235
47uF
20V
C678
22uF
25V
C684
22uF
25V
Title
Size
B
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
3
of
1
41
E1
8
7
6
5
4
3
2
1
Cyclone V GX SoC Bank 3 & 4
(5,19) ENET2_TX_D[3..0]
(5,19) ENET2_RX_D[3..0]
U21B
E
E
(19,21) ENET_DUAL_RESETn
CYCLONE V GX SoC BANK 4
100, 1%
U21A
DDR3_FPGA_DQ2
CYCLONE V GX SoC BANK 3
HSMA_D0
HSMA_D1
HSMA_D2
HSMA_D3
HSMA_SDA
HSMA_SCL
SDI_CLK148_UP (8)
SDI_CLK148_DN (8)
PCIE_PERSTn
AF9
AF8
AG7
AG1
AH2
AA12
AB12
AF6
AG6
DIFFIO_TX_B8p,DQ1B
Bank 3A
2.5 Volt
DIFFIO_TX_B9p,DQ2B
DIFFIO_TX_B9n
DIFFIO_RX_B10p,DQ2B
DIFFIO_RX_B10n,DQ2B
DIFFIO_RX_B11p,DQS2B
DIFFIO_RX_B11n,DQSn2B
DIFFIO_TX_B12p
DIFFIO_TX_B12n,DQ2B
DIFFIO_TX_B13p,DQ2B
DIFFIO_TX_B13n,DQ2B
DIFFIO_RX_B14p,DQ2B
DIFFIO_RX_B14n,DQ2B
DIFFIO_RX_B15p
DIFFIO_RX_B15n
DIFFIO_TX_B16p,DQ2B
DIFFIO_TX_B16n,DQ2B
AG5(19) P0TXERR
AH5(19) P1TXERR
AJ1
AJ2 HSMA_CLK_OUT_P1
AC12 HSMA_CLK_OUT_N1
AD12 HSMA_PRSNTn
AG2 HSMA_CLK_IN_P1
AH3 HSMA_CLK_IN_N1
D
USER_DIPSW_FPGA0
USER_DIPSW_FPGA1
USER_DIPSW_FPGA2
USER_DIPSW_FPGA3
USER_PB_FPGA0
USER_PB_FPGA1
USER_LED_FPGA0
USB_FULL
USB_EMPTY
USB_SCL
USB_SDA
USB_B2_CLK
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
DDR3_FPGA_WEn
C
DDR3_FPGA_A14
AG10
AH9
AF11
AG11
AA13
AB13
AK2
AK3
AJ4
AK4
AE13
AF13
AD14
AE14
AJ5
AK6
AJ6
AJ7
AG12
AG13
DIFFIO_TX_B17p,DQ3B
DIFFIO_TX_B17n
DIFFIO_RX_B18p,DQ3B
DIFFIO_RX_B18n,DQ3B
DIFFIO_RX_B19p,DQS3B
DIFFIO_RX_B19n,DQSn3B
DIFFIO_TX_B20p
DIFFIO_TX_B20n,DQ3B
DIFFIO_TX_B21p,DQ3B
DIFFIO_TX_B21n,DQ3B
DIFFIO_RX_B22p,DQ3B
DIFFIO_RX_B22n,DQ3B
DIFFIO_RX_B23p
DIFFIO_RX_B23n
DIFFIO_TX_B24p,DQ3B
DIFFIO_TX_B24n,DQ3B
DIFFIO_TX_B25p,DQ4B,B_WE#
DIFFIO_TX_B25n,GND
DIFFIO_RX_B26p,DQ4B,B_A_14
DIFFIO_RX_B26n,DQ4B,B_A_15
Bank 3B
1.5 Volt DIFFIO_RX_B27p,DQS4B,B_CS#_0
DIFFIO_RX_B27n,DQSn4B,B_CS#_1
DIFFIO_TX_B28p,B_A_12
DIFFIO_TX_B28n,DQ4B,B_A_13
DIFFIO_TX_B29p,DQ4B,B_A_10
DIFFIO_TX_B29n,DQ4B,B_A_11
DIFFIO_RX_B30p,DQ4B,B_A_8
DIFFIO_RX_B30n,DQ4B,B_A_9
DIFFIO_TX_B32p,DQ4B,B_CAS#
DIFFIO_TX_B32n,DQ4B,B_RAS#
DIFFIO_TX_B33p,DQ5B,B_BA_0
DIFFIO_TX_B33n,GND
DIFFIO_RX_B34p,DQ5B,B_BA_1
DIFFIO_RX_B34n,DQ5B,B_BA_2
DIFFIO_RX_B35p,DQS5B,B_CK
DIFFIO_RX_B35n,DQSn5B,B_CK#
DIFFIO_TX_B36p,B_A_6
DIFFIO_TX_B36n,DQ5B,B_A_7
DIFFIO_RX_B38p,DQ5B,B_A_4
DIFFIO_RX_B38n,DQ5B,B_A_5
DIFFIO_TX_B40p,DQ5B,B_A_0
DIFFIO_TX_B40n,DQ5B,B_A_1
AB15 DDR3_FPGA_CSn
AC14
AK7 DDR3_FPGA_A12
AK8 DDR3_FPGA_A13
AJ9 DDR3_FPGA_A10
AK9 DDR3_FPGA_A11
AH13 DDR3_FPGA_A8
AH14 DDR3_FPGA_A9
AH7 DDR3_FPGA_CASn
AH8 DDR3_FPGA_RASn
AH10 DDR3_FPGA_BA0
AJ10
AJ11 DDR3_FPGA_BA1
AK11 DDR3_FPGA_BA2
AA14 DDR3_FPGA_CLK_P
AA15 DDR3_FPGA_CLK_N
AK12 DDR3_FPGA_A6
AK13 DDR3_FPGA_A7
AG15 DDR3_FPGA_A4
AH15 DDR3_FPGA_A5
AJ14 DDR3_FPGA_A0
AK14 DDR3_FPGA_A1
AG16
DDR3_FPGA_DQ1
DDR3_FPGA_DQ0
DDR3_FPGA_DQS_P0
DDR3_FPGA_DQS_N0
DDR3_FPGA_ODT
DDR3_FPGA_DQ3
DDR3_FPGA_DQ6
AE17
AF18
V16
W16
AE16
AF16
AJ16
AK16
DDR3_FPGA_DQ5
AG21
DDR3_FPGA_DQ4
AH20
DDR3_FPGA_DM0
AH17
DDR3_FPGA_DQ7
AH18
DDR3_FPGA_DQ10
AG18
AH19
DDR3_FPGA_DQ9
AJ17
DDR3_FPGA_DQ8
AK18
DDR3_FPGA_DQS_P1
V17
DDR3_FPGA_DQS_N1
W17
AJ19
DDR3_FPGA_DQ11
AK19
DDR3_FPGA_DQ14
AJ20
DDR3_FPGA_CKE
AJ21
DDR3_FPGA_DQ13
AF19
DDR3_FPGA_DQ12
AG20
DDR3_FPGA_DM1
AG23
DDR3_FPGA_DQ15
AH24
DDR3_FPGA_DQ18
AG22
AH22
DDR3_FPGA_DQ17
AE18
DDR3_FPGA_DQ16
AE19
DDR3_FPGA_DQS_P2
Y17
DDR3_FPGA_DQS_N2
AA18
DDR3_FPGA_RESETn AK21
DDR3_FPGA_DQ19
AK22
DDR3_FPGA_DQ22
AH23
AJ22
DIFFIO_TX_B41p,DQ6B,B_DQ_2
DIFFIO_RX_B42p,DQ6B,B_DQ_1
DIFFIO_RX_B42n,DQ6B,B_DQ_0
DIFFIO_RX_B43p,DQS6B,B_DQS_0
DIFFIO_RX_B43n,DQSn6B,B_DQS#_0
DIFFIO_TX_B44p,B_ODT_0
DIFFIO_TX_B44n,DQ6B,B_DQ_3
DIFFIO_TX_B45p,DQ6B,B_DQ_6
DIFFIO_TX_B45n,DQ6B,B_ODT_1
DIFFIO_RX_B46p,DQ6B,B_DQ_5
DIFFIO_RX_B46n,DQ6B,B_DQ_4
DIFFIO_TX_B48p,DQ6B,B_DM_0
DIFFIO_TX_B48n,DQ6B,B_DQ_7
DIFFIO_TX_B49p,DQ7B,B_DQ_10
DIFFIO_TX_B49n,GND
DIFFIO_RX_B50p,DQ7B,B_DQ_9
DIFFIO_RX_B50n,DQ7B,B_DQ_8
DIFFIO_RX_B51p,DQS7B,B_DQS_1
DIFFIO_RX_B51n,DQSn7B,B_DQS#_1
DIFFIO_TX_B52p,B_CKE_1
DIFFIO_TX_B52n,DQ7B,B_DQ_11
DIFFIO_TX_B53p,DQ7B,B_DQ_14
DIFFIO_TX_B53n,DQ7B,B_CKE_0
DIFFIO_RX_B54p,DQ7B,B_DQ_13
DIFFIO_RX_B54n,DQ7B,B_DQ_12
DIFFIO_TX_B56p,DQ7B,B_DM_1
DIFFIO_TX_B56n,DQ7B,B_DQ_15
DIFFIO_TX_B57p,DQ8B,B_DQ_18
DIFFIO_TX_B57n,GND
DIFFIO_RX_B58p,DQ8B,B_DQ_17
DIFFIO_RX_B58n,DQ8B,B_DQ_16
DIFFIO_RX_B59p,DQS8B,B_DQS_2
DIFFIO_RX_B59n,DQSn8B,B_DQS#_2
DIFFIO_TX_B60p,B_RESET#
DIFFIO_TX_B60n,DQ8B,B_DQ_19
DIFFIO_TX_B61p,DQ8B,B_DQ_22
DIFFIO_TX_B61n,DQ8B,GND
5CSXFC6D_F896
Bank 4A
1.5 Volt
RZQ_0,DIFFIO_TX_B41n
DIFFIO_RX_B62p,DQ8B,B_DQ_21
DIFFIO_RX_B62n,DQ8B,B_DQ_20
DIFFIO_RX_B63p,GND
DIFFIO_RX_B63n,GND
DIFFIO_TX_B64p,DQ8B,B_DM_2
DIFFIO_TX_B64n,DQ8B,B_DQ_23
DIFFIO_TX_B65p,DQ9B,B_DQ_26
DIFFIO_TX_B65n,GND
DIFFIO_RX_B66p,DQ9B,B_DQ_25
DIFFIO_RX_B66n,DQ9B,B_DQ_24
DIFFIO_RX_B67p,DQS9B,B_DQS_3
DIFFIO_RX_B67n,DQSn9B,B_DQS#_3
DIFFIO_TX_B68p,GND
DIFFIO_TX_B68n,DQ9B,B_DQ_27
DIFFIO_TX_B69p,DQ9B,B_DQ_30
DIFFIO_TX_B69n,DQ9B,GND
DIFFIO_RX_B70p,DQ9B,B_DQ_29
DIFFIO_RX_B70n,DQ9B,B_DQ_28
DIFFIO_RX_B71p,GND
DIFFIO_RX_B71n,GND
DIFFIO_TX_B72p,DQ9B,B_DM_3
DIFFIO_TX_B72n,DQ9B,B_DQ_31
DIFFIO_TX_B73p,DQ10B,B_DQ_34
DIFFIO_TX_B73n,GND
DIFFIO_RX_B74p,DQ10B,B_DQ_33
DIFFIO_RX_B74n,DQ10B,B_DQ_32
DIFFIO_RX_B75p,DQS10B,B_DQS_4
DIFFIO_RX_B75n,DQSn10B,B_DQS#_4
DIFFIO_TX_B76p,GND
DIFFIO_TX_B76n,DQ10B,B_DQ_35
DIFFIO_TX_B77p,DQ10B,B_DQ_38
DIFFIO_TX_B77n,DQ10B,GND
DIFFIO_RX_B78p,DQ10B,B_DQ_37
DIFFIO_RX_B78n,DQ10B,B_DQ_36
DIFFIO_RX_B79p,GND
DIFFIO_RX_B79n,GND
DIFFIO_TX_B80p,DQ10B,B_DM_4
DIFFIO_TX_B80n,DQ10B,B_DQ_39
AG17
RZQIN_1_5V
R449
AF20 DDR3_FPGA_DQ21
AF21 DDR3_FPGA_DQ20
Y18
AA19
AK23 DDR3_FPGA_DM2
AK24 DDR3_FPGA_DQ23
AJ24 DDR3_FPGA_DQ26
AJ25
AF23 DDR3_FPGA_DQ25
AF24 DDR3_FPGA_DQ24
AC20 DDR3_FPGA_DQS_P3
AD19 DDR3_FPGA_DQS_N3
AJ26
AK26 DDR3_FPGA_DQ27
AG25 DDR3_FPGA_DQ30
AH25
AE22 DDR3_FPGA_DQ29
AE23 DDR3_FPGA_DQ28
V18
W19
DDR3_FPGA_DM3
AJ27
AK27 DDR3_FPGA_DQ31
USB_B2_DATA0
AK28
AK29
USB_B2_DATA1
AD20
USB_B2_DATA2
AD21
USB_B2_DATA3
Y19
USB_B2_DATA4
AA20
AG26
USB_B2_DATA5
AH27
USB_B2_DATA6
AF25
AF26
USB_B2_DATA7
AC22
AC23
AA21
AB21
AD24
AE24
D
C
5CSXFC6D_F896
HSMC LVCMOS INTERFACE
(17) HSMA_CLK_OUT_P1
(17) HSMA_CLK_OUT_N1
USER_PB_FPGA[1:0] (23)
USB_B2_DATA[7:0]
LVCMOS Only
(13) DDR3_FPGA_DM0
(13) DDR3_FPGA_DM1
(13) DDR3_FPGA_DM2
(13) DDR3_FPGA_DM3
USB_B2_DATA[7:0] (25)
(17) HSMA_CLK_IN_P1
USER_LED_FPGA[3:0] (9,23)
B
DDR3_FPGA_CKE
DDR3_FPGA_CLK_P
DDR3_FPGA_CLK_N
(13) DDR3_FPGA_CKE
(13) DDR3_FPGA_CLK_P
(13) DDR3_FPGA_CLK_N
USER_DIPSW_FPGA[3:0] (23)
(17) HSMA_CLK_IN_N1
USB_FULL
USB_EMPTY
USB_SCL
USB_SDA
USB_B2_CLK
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
(16,17,23) HSMA_PRSNTn
(17) HSMA_D[3:0]
USB_FULL (25)
USB_EMPTY (25)
USB_SCL (25)
USB_SDA (25)
USB_B2_CLK (16,25)
USB_RESETn (25)
USB_OEn (25)
USB_RDn (25)
USB_WRn (25)
(17) HSMA_SDA
(17) HSMA_SCL
(13) DDR3_FPGA_CSn
(13) DDR3_FPGA_WEn
(13) DDR3_FPGA_RASn
(13) DDR3_FPGA_CASn
(13) DDR3_FPGA_BA0
(13) DDR3_FPGA_BA1
(13) DDR3_FPGA_BA2
(13) DDR3_FPGA_RESETn
(13) DDR3_FPGA_ODT
DDR3_FPGA_BA[2:0] (13)
DDR3_FPGA_DM0
DDR3_FPGA_DM1
DDR3_FPGA_DM2
DDR3_FPGA_DM3
DDR3_FPGA_DM[3:0] (13)
DDR3_FPGA_CSn
DDR3_FPGA_WEn
DDR3_FPGA_RASn
DDR3_FPGA_CASn
DDR3_FPGA_DQS_N[3:0] (13)
DDR3_FPGA_BA0
DDR3_FPGA_BA1
DDR3_FPGA_BA2
DDR3_FPGA_RESETn
DDR3_FPGA_ODT
DDR3_FPGA_A[14:0] (9,13)
DDR3_FPGA_DQS_P[3:0] (13)
B
DDR3_FPGA_DQ[31:0] (13)
PCIE INTERFACE
A
(3,11) PCIE_PERSTn
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
4
of
1
41
E1
8
7
6
5
4
3
2
1
Cyclone V GX SoC Bank 5 & 6
U21D
CYCLONE V GX SoC BANK 6
100, 1%
E
U21C
CYCLONE V GX SoC BANK 5
Bank 5A
2.5 Volt
ENET1_TX_D0
W20
ENET1_TX_D1
Y21
ENET1_TX_D2
AA25
ENET1_TX_D3
AB26
ENET1_TX_EN(19) AB22
ENET1_RX_D0
AB23
ENET1_RX_D1
AA24
ENET1_RX_D2
AB25
ENET1_RX_D3
AE27
ENET1_RX_ERROR (19) AE28
Y23
ENET1_RX_DV (19)
Y24
ENET1_RX_CLK (19)
D
ENET1_TX_CLK_FB (19) W25
V25
ENET2_RX_ERROR (19)
AC28
ENET2_RX_DV (19)
SDI_TX_SD_HDn (20)
AC29
AB30
SDI_RSTI (20)
AA30
SDI_TX_EN (16,20)
SDI_RX_BYPASS (16,20)AB28
AA28
SDI_RX_EN (16,20)
SDI_FAULT (20)
AD30
C
AC30
AG27
RZQ_1,DIFFIO_TX_R1p,DQ1R
DIFFIO_RX_R4p,DQ1R
DIFFIO_RX_R4n,DQ1R
DIFFIO_TX_R7p,DQ1R
DIFFIO_TX_R7n
DIFFIO_RX_R8p,DQ1R
DIFFIO_RX_R8n,DQ1R
DIFFIO_RX_R9p
DIFFIO_RX_R9n
DIFFIO_TX_R10p,DQ2R
DIFFIO_TX_R10n,DQ2R
DIFFIO_RX_R11p,DQ2R
DIFFIO_RX_R11n,DQ2R
DIFFIO_RX_R17p
DIFFIO_RX_R17n
DIFFIO_TX_R18p,DQ3R
DIFFIO_TX_R18n,DQ3R
DIFFIO_RX_R19p,DQ3R
DIFFIO_RX_R19n,DQ3R
DIFFIO_TX_R20p,DQ3R
DIFFIO_TX_R20n,DQ3R
DIFFIO_TX_R24p,DQ3R
DIFFIO_TX_R12p,DQ2R
DIFFIO_TX_R12n,DQ2R
DIFFIO_RX_R13p,DQS2R
DIFFIO_RX_R13n,DQSn2R
DIFFIO_TX_R14p
DIFFIO_TX_R14n,DQ2R
DIFFIO_RX_R15p,DQ2R
DIFFIO_RX_R15n,DQ2R
DIFFIO_TX_R16p,DQ2R
DIFFIO_TX_R16n
ENET2_TX_D0
ENET2_TX_D1
AG28
ENET2_TX_D2
AF28
ENET2_TX_D3
V23
W24(19) ENET2_TX_EN
ENET2_RX_D0
AF29
ENET2_RX_D1
AF30
ENET2_RX_D2
AD26
ENET2_RX_D3
AC27
AH30
(19) ENET2_RX_CLK
AG30(19) ENET2_TX_CLK_FB
D27
R410
DDR3_HPS_A0 F26
DDR3_HPS_A1 G30
DDR3_HPS_A2 F28
DDR3_HPS_A3 F30
DDR3_HPS_A4 J25
DDR3_HPS_A5 J27
DDR3_HPS_A6 F29
DDR3_HPS_A7 E28
DDR3_HPS_A8 H27
DDR3_HPS_A9 G26
DDR3_HPS_A10D29
DDR3_HPS_A11C30
DDR3_HPS_A12B30
DDR3_HPS_A13C29
DDR3_HPS_A14H25
G25
DDR3_HPS_CLK_P
M23
DDR3_HPS_CLK_N
L23
DDR3_HPS_CKE L29
L30
DDR3_HPS_BA0 E29
DDR3_HPS_BA1 J24
DDR3_HPS_BA2 J23
DDR3_HPS_RASnD30
DDR3_HPS_CASnE27
DDR3_HPS_WEn C28
DDR3_HPS_CSn H24
K21
DDR3_HPS_ODT H28
H29
Bank 5B
2.5 Volt
DDR3_HPS_DM2 R28
DDR3_HPS_DQS_P2R19
DDR3_HPS_DQS_N2R18
DDR3_HPS_DQ16U26
DDR3_HPS_DQ17T26
DDR3_HPS_DQ18N29
DDR3_HPS_DQ19N28
DDR3_HPS_DQ20P26
DDR3_HPS_DQ21P27
DDR3_HPS_DQ22N27
DDR3_HPS_DQ23R29
RZQ_2,DIFFIO_TX_R24n
5CSXFC6D_F896
DDR3_HPS_DM3 W30
DDR3_HPS_DQS_P3R22
DDR3_HPS_DQS_N3R21
DDR3_HPS_DQ24P24
DDR3_HPS_DQ25P25
DDR3_HPS_DQ26T29
DDR3_HPS_DQ27T28
DDR3_HPS_DQ28R27
DDR3_HPS_DQ29R26
DDR3_HPS_DQ30V30
DDR3_HPS_DQ31W29
HPS_RZQ_0
HPS_DDR,HPS_A_0
HPS_DDR,HPS_A_1
HPS_DDR,HPS_A_2
HPS_DDR,HPS_A_3
HPS_DDR,HPS_A_4
HPS_DDR,HPS_A_5
HPS_DDR,HPS_A_6
HPS_DDR,HPS_A_7
HPS_DDR,HPS_A_8
HPS_DDR,HPS_A_9
HPS_DDR,HPS_A_10
HPS_DDR,HPS_A_11
HPS_DDR,HPS_A_12
HPS_DDR,HPS_A_13
HPS_DDR,HPS_A_14
HPS_DDR,HPS_A_15
HPS_DDR,HPS_CK
HPS_DDR,HPS_CK#
HPS_DDR,HPS_CKE_0
HPS_DDR,HPS_CKE_1
HPS_DDR,HPS_BA_0
HPS_DDR,HPS_BA_1
HPS_DDR,HPS_BA_2
HPS_DDR,HPS_RAS#
HPS_DDR,HPS_CAS#
HPS_DDR,HPS_WE#
HPS_DDR,HPS_CS#_0
HPS_DDR,HPS_CS#_1
HPS_DDR,HPS_ODT_0
HPS_DDR,HPS_ODT_1
Bank 6A
1.5 Volt
HPS_DDR,HPS_DM_0
HPS_DDR,HPS_DQS_0
HPS_DDR,HPS_DQS#_0
HPS_DDR,HPS_DQ_0
HPS_DDR,HPS_DQ_1
HPS_DDR,HPS_DQ_2
HPS_DDR,HPS_DQ_3
HPS_DDR,HPS_DQ_4
HPS_DDR,HPS_DQ_5
HPS_DDR,HPS_DQ_6
HPS_DDR,HPS_DQ_7
HPS_DDR,HPS_DM_1
HPS_DDR,HPS_DQS_1
HPS_DDR,HPS_DQS#_1
HPS_DDR,HPS_DQ_8
HPS_DDR,HPS_DQ_9
HPS_DDR,HPS_DQ_10
HPS_DDR,HPS_DQ_11
HPS_DDR,HPS_DQ_12
HPS_DDR,HPS_DQ_13
HPS_DDR,HPS_DQ_14
HPS_DDR,HPS_DQ_15
HPS_GPI0
HPS_GPI1
HPS_GPI3
HPS_GPI2
HPS_DDR,HPS_DM_2
HPS_DDR,HPS_DQS_2
HPS_DDR,HPS_DQS#_2
HPS_DDR,HPS_DQ_16
HPS_DDR,HPS_DQ_17
HPS_DDR,HPS_DQ_18
HPS_DDR,HPS_DQ_19
HPS_DDR,HPS_DQ_20
HPS_DDR,HPS_DQ_21
HPS_DDR,HPS_DQ_22
HPS_DDR,HPS_DQ_23
HPS_DDR,HPS_DM_4
Bank 6B
1.5 Volt HPS_DDR,HPS_DQS_4
HPS_DDR,HPS_DM_3
HPS_DDR,HPS_DQS_3
HPS_DDR,HPS_DQS#_3
HPS_DDR,HPS_DQ_24
HPS_DDR,HPS_DQ_25
HPS_DDR,HPS_DQ_26
HPS_DDR,HPS_DQ_27
HPS_DDR,HPS_DQ_28
HPS_DDR,HPS_DQ_29
HPS_DDR,HPS_DQ_30
HPS_DDR,HPS_DQ_31
HPS_GPI4
HPS_GPI5
HPS_GPI6
HPS_GPI7
HPS_GPI8
HPS_GPI9
HPS_GPI10
HPS_GPI11
HPS_GPI12
HPS_GPI13
HPS_DDR,HPS_DQS#_4
HPS_DDR,HPS_DQ_32
HPS_DDR,HPS_DQ_33
HPS_DDR,HPS_DQ_34
HPS_DDR,HPS_DQ_35
HPS_DDR,HPS_DQ_36
HPS_DDR,HPS_DQ_37
HPS_DDR,HPS_DQ_38
HPS_DDR,HPS_DQ_39
HPS_DDR,HPS_RESET#
B
K28
N18
M19
K23
K22
H30
G28
L25
L24
J30
J29
DDR3_HPS_DM0
DDR3_HPS_DQS_P0
DDR3_HPS_DQS_N0
DDR3_HPS_DQ0
DDR3_HPS_DQ1
DDR3_HPS_DQ2
DDR3_HPS_DQ3
DDR3_HPS_DQ4
DDR3_HPS_DQ5
DDR3_HPS_DQ6
DDR3_HPS_DQ7
M28
N25
N24
K26
L26
K29
K27
M26
M27
L28
M30
DDR3_HPS_DM1
DDR3_HPS_DQS_P1
DDR3_HPS_DQS_N1
DDR3_HPS_DQ8
DDR3_HPS_DQ9
DDR3_HPS_DQ10
DDR3_HPS_DQ11
DDR3_HPS_DQ12
DDR3_HPS_DQ13
DDR3_HPS_DQ14
DDR3_HPS_DQ15
DDR3_HPS_DM4
DDR3_HPS_DQS_P4
DDR3_HPS_DQS_N4
DDR3_HPS_DQ32
DDR3_HPS_DQ33
DDR3_HPS_DQ34
DDR3_HPS_DQ35
DDR3_HPS_DQ36
DDR3_HPS_DQ37
DDR3_HPS_DQ38
DDR3_HPS_DQ39
W27
T24
T23
W26
R24
U27
V28
T25
U25
V27
Y29
USER_DIPSW_HPS0
USER_DIPSW_HPS1
USER_DIPSW_HPS2
USER_DIPSW_HPS3
USER_PB_HPS0
USER_PB_HPS1
USER_PB_HPS2
USER_PB_HPS3
N30
P29
P22
V20
T30
U28
T21
U20
V29
Y28
(14) DDR3_HPS_BA0
(14) DDR3_HPS_BA1
(14) DDR3_HPS_BA2
(14) DDR3_HPS_RASn
(14) DDR3_HPS_CASn
(14) DDR3_HPS_WEn
(14) DDR3_HPS_CSn
(14) DDR3_HPS_ODT
(14) DDR3_HPS_RESETn
A
C
(23) USER_DIPSW_HPS[3:0]
(23) USER_PB_HPS[3:0]
DDR3_HPS_RESETn
P30
(4,7,17) HSMA_CLK_OUT_P[2:1]
B
(4,7,17) HSMA_CLK_OUT_N[2:1]
(7,17) HSMA_TX_D_P[16:0]
DDR3_HPS_CLK_P
DDR3_HPS_CLK_N
DDR3_HPS_CKE
(14) DDR3_HPS_CLK_P
(14) DDR3_HPS_CLK_N
(14) DDR3_HPS_CKE
D
M25
J26
M22
N23
5CSXFC6D_F896
ENET1_TX_D[3..0] (19)
ENET1_RX_D[3..0] (19)
ENET2_TX_D[3..0] (19)
ENET2_RX_D[3..0] (19)
E
DDR3_HPS_BA[2:0] (14)
(7,17) HSMA_TX_D_N[16:0]
DDR3_HPS_BA0
DDR3_HPS_BA1
DDR3_HPS_BA2
DDR3_HPS_RASn
DDR3_HPS_CASn
DDR3_HPS_WEn
DDR3_HPS_CSn
DDR3_HPS_DM[4:0] (14)
(7,17) HSMA_RX_D_P[16:0]
DDR3_HPS_ODT
DDR3_HPS_DQ[39:0] (14)
DDR3_HPS_RESETn
DDR3_HPS_A[14:0] (14)
(7,17) HSMA_RX_D_N[16:0]
DDR3_HPS_DQS_P[4:0] (14)
DDR3_HPS_DQS_N[4:0] (14)
Si571 VCXO
(4,8) SDI_CLK148_DN
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
5
of
1
41
E1
8
7
6
5
4
3
2
Micro SD / USB INTERFACE
Cyclone V GX SoC Bank 7
2.5V_HPS
3.3V
1
USB_DATA[7..0]
USB_DATA[7..0] (22)
U21E
R393
R392
4.70K, 1%
2.5V_HPS
CSEL 00 by default
HEADER, 1x3-PIN
J26
1 10.0K R239
UART_TX
2
3
1.00k
MICTOR_RSTn
HPS_RESETn
JTAG_HPS_TDO (12)
HPS_EN_2.5V
JTAG_HPS_TMS (12)
JTAG_HPS_TCK (12)
JTAG_HPS_TRST
JTAG_HPS_TDI (12)
TRACE_CLK_MIC
TRACE_DATA0
TRACE_DATA1
TRACE_DATA2
3.3V
CLKSEL0 38.3
R240
D
22pF
CLKSEL1
R242
HEADER, 1x3-PIN
0
22
22
22
B26
B25
C25
A25
B20
G20
A20
K17
B21
E21
A21
F19
F21
J19
F20
SD_CD_DAT3
B16
SD_DAT2
D17
SD_CLK
A16
USER_LED_HPS0 E17
USER_LED_HPS1 E18
USER_LED_HPS2 G17
(22) SD_CD_DAT3
(22) SD_DAT2
(22) SD_CLK
USB_DATA6
USB_DATA5
USB_DATA7
USB_CLK
USB_NXT
USB_DIR
USB_STP
(22) USB_DATA6
(22) USB_DATA5
(22) USB_DATA7
C
R391
R375
R373
R374
ENET_HPS_RXD1
ENET_HPS_RX_CLK
ENET_HPS_TX_EN
ENET_HPS_RX_DV
ENET_HPS_MDC
ENET_HPS_MDIO
ENET_HPS_RXD0
ENET_HPS_TXD3
ENET_HPS_TXD2
ENET_HPS_TXD1
ENET_HPS_TXD0
3.3V
1 10.0K R241
CAN_0_TX
2
3
1.00k
C27
F23
B28
G23
A29
H22
A28
B27
F24
D25
F25
CLK_OSC1 (10)
CLK_OSC2 (10)
R693
C784
J27
ETHERNET INTERFACE
CYCLONE V GX SoC BANK 7
4.70K, 1%
E
(22) USB_CLK
(22) USB_NXT
(22) USB_DIR
(22) USB_STP
D15
C14
M17
N16
A14
E14
C15
ENET_HPS_TXD[3..0]
HPS_nRST
HPS_nPOR
HPS_TDO
VCCRSTCLK_HPS
HPS_TMS
HPS_TCK
HPS_TRST
HPS_TDI
HPS_PORSEL
HPS_CLK1
HPS_CLK2
Bank 7A
D24
(24) UART_TX
E24
(24) UART_RX
D22 (18,23,27) I2C_SCL_HPS
C23 (18,23,27) I2C_SDA_HPS
G22
(24) CAN_0_TX
B22
(24) CAN_0_RX
SPI_CSn
H20
SPI_MISO
B23
SPI_MOSI
C22
SPI_SCK
A23
E23
R377
22 TRACE_DATA7
C24
R376
22 TRACE_DATA6
R396
22 TRACE_DATA5
G21
A24
R395
22 TRACE_DATA4
H23
R394
22 TRACE_DATA3
CAN0_TX,UART0_TX,SPIM1_SS0,HPS_GPIO66
CAN0_RX,UART0_RX,SPIM1_MISO,HPS_GPIO65
I2C0_SCL,UART1_TX,SPIM1_MOSI,HPS_GPIO64
I2C0_SDA,UART1_RX,SPIM1_CLK,HPS_GPIO63
UART0_TX,CAN0_TX,SPIM1_SS1,HPS_GPIO62
UART0_RX,CAN0_RX,SPIM0_SS1,HPS_GPIO61
SPIM0_SS0,CAN1_TX,UART1_RTS,BOOTSEL0,HPS_GPIO60
SPIM0_MISO,CAN1_RX,UART1_CTS,HPS_GPIO59
SPIM0_MOSI,I2C1_SCL,UART0_RTS,HPS_GPIO58
SPIM0_CLK,I2C1_SDA,UART0_CTS,HPS_GPIO57
TRACE_D7,SPIS1_MISO,I2C0_SCL,HPS_GPIO56
TRACE_D6,SPIS1_SS0,I2C0_SDA,HPS_GPIO55
TRACE_D5,SPIS1_MOSI,CAN1_TX,HPS_GPIO54
TRACE_D4,SPIS1_CLK,CAN1_RX,HPS_GPIO53
TRACE_D3,SPIS0_SS0,I2C1_SCL,HPS_GPIO52
TRACE_CLK,HPS_GPIO48
TRACE_D0,SPIS0_CLK,UART0_RX,HPS_GPIO49
TRACE_D1,SPIS0_MOSI,UART0_TX,HPS_GPIO50
TRACE_D2,SPIS0_MISO,I2C1_SDA,HPS_GPIO51
NAND_DQ6,RGMII1_RXD1,USB1_D7,HPS_GPIO25
NAND_DQ5,RGMII1_RX_CLK,USB1_D6,HPS_GPIO24
NAND_DQ4,RGMII1_TX_CTL,USB1_D5,HPS_GPIO23
NAND_DQ3,RGMII1_RX_CTL,USB1_D4,HPS_GPIO22
NAND_DQ2,RGMII1_MDC,I2C3_SCL,HPS_GPIO21
NAND_DQ1,RGMII1_MDIO,I2C3_SDA,HPS_GPIO20
NAND_DQ0,RGMII1_RXD0,HPS_GPIO19
NAND_RB,RGMII1_TXD3,USB1_D3,HPS_GPIO18
NAND_RE,RGMII1_TXD2,USB1_D2,HPS_GPIO17
NAND_CLE,RGMII1_TXD1,USB1_D1,HPS_GPIO16
NAND_CE,RGMII1_TXD0,USB1_D0,HPS_GPIO15
Bank 7B NAND_ALE,RGMII1_TX_CLK,QSPI_SS3,HPS_GPIO14
SDMMC_D3,USB0_NXT,HPS_GPIO47
SDMMC_D2,USB0_DIR,HPS_GPIO46
SDMMC_CLK,USB0_STP,HPS_GPIO45
SDMMC_CLK_IN,USB0_CLK,HPS_GPIO44
SDMMC_D7,USB0_D7,HPS_GPIO43
SDMMC_D6,USB0_D6,HPS_GPIO42
Bank 7C
RGMII0_MDC ,USB1_D6,I2C2_SCL,HPS_GPIO7
RGMII0_MDIO,USB1_D5,I2C2_SDA,HPS_GPIO6
RGMII0_RX_CTL,USB1_D7,HPS_GPIO8
RGMII0_RX_CLK,USB1_CLK,HPS_GPIO10
RGMII0_RXD3,USB1_NXT,HPS_GPIO13
RGMII0_RXD2,USB1_DIR,HPS_GPIO12
RGMII0_RXD1,USB1_STP,HPS_GPIO11
Bank 7D
ENET_HPS_TXD[3..0] (18)
ENET_HPS_GTX_CLK
ENET_HPS_TX_EN
ENET_HPS_MDC
ENET_HPS_RESETn
ENET_HPS_RXD[3..0]
ENET_HPS_RXD[3..0] (18)
ENET_HPS_RX_CLK
ENET_HPS_RX_DV
ENET_HPS_MDIO
ENET_HPS_INTn
ENET_HPS_RX_CLK (18)
ENET_HPS_RX_DV (18)
ENET_HPS_MDIO (18)
ENET_HPS_INTn (18)
HPS_RESETn
H19
B18
D21
D20
C20
H18
A19
E19
A18
D19
C19
NAND_DQ7,RGMII1_RXD2,HPS_GPIO26
NAND_WP,RGMII1_RXD3,QSPI_SS2,HPS_GPIO27
NAND_WE,QSPI_SS1,BOOTSEL2,HPS_GPIO28
QSPI_IO0,USB1_CLK,HPS_GPIO29
QSPI_IO1,USB1_STP,HPS_GPIO30
QSPI_IO2,USB1_DIR,HPS_GPIO31
QSPI_IO3,USB1_NXT,HPS_GPIO32
QSPI_SS0,BOOTSEL1,HPS_GPIO33
QSPI_CLK,HPS_GPIO34
QSPI_SS1,HPS_GPIO35
F18
B17
G18
C17
H17
C18
SDMMC_CMD,USB0_D0,HPS_GPIO36
SDMMC_PWREN,USB0_D1,HPS_GPIO37
SDMMC_D0,USB0_D2,HPS_GPIO38
SDMMC_D1,USB0_D3,HPS_GPIO39
SDMMC_D4,USB0_D4,HPS_GPIO40
SDMMC_D5,USB0_D5,HPS_GPIO41
ENET_HPS_GTX_CLK
ENET_HPS_RXD2
ENET_HPS_RXD3
BOOTSEL2
(21) QSPI_IO0
(21) QSPI_IO1
(21) QSPI_IO2
(21) QSPI_IO3
(21) QSPI_SS0
(21) QSPI_CLK
ENET_HPS_INTn
USER_LED_HPS[3..0] (23)
R243 10.0K 1
SPI_CSn
2
3
1.00k
R244
SD_CMD (22)
SD_PWREN
SD_DAT0 (22)
SD_DAT1 (22)
3.3V
USER_LED_HPS3
USB_DATA4 (22)
USB_DATA3 (22)
USB_DATA2 (22)
USB_DATA1 (22)
USB_DATA0 (22)
BOOTSEL0
J29
1
R245 10.0K
QSPI_SS0
2
3
1.00k
R246
D
HEADER, 1x3-PIN
J28
3.3V
USB_DATA4
A15
USB_DATA3
D14
USB_DATA2
D16
USB_DATA1
G16
USB_DATA0
E16
F16 CODEC_SEL
B15 PM_CNTL0
RGMII0_RXD0,USB1_D4,HPS_GPIO5
RGMII0_TXD3,USB1_D3,HPS_GPIO4
RGMII0_TXD2,USB1_D2,HPS_GPIO3
RGMII0_TXD1,USB1_D1,HPS_GPIO2
RGMII0_TXD0,USB1_D0,HPS_GPIO1
RGMII0_TX_CLK,HPS_GPIO0
RGMII0_TX_CTL,HPS_GPIO9
HPS_RESETn (16,21)
USER_LED_HPS[3..0]
SD_CMD
SD_PWREN
SD_DAT0
SD_DAT1
E
ENET_HPS_GTX_CLK (18)
ENET_HPS_TX_EN (18)
ENET_HPS_MDC (18)
ENET_HPS_RESETn (18,21)
BOOTSEL1
HEADER, 1x3-PIN
3.3V
J30
1
2
3
R247 10.0K
BOOTSEL2
1.00k
R248
PM_CNTL0 (26,27)
C
BOOTSEL2
HEADER, 1x3-PIN
3.3V
5CSXFC6D_F896
U54
IDTQS3VH257
Manufacturer = IDT
PART_NUMBER = QS3VH257PAG
3.3V
16
VCC
SPI_MISO
2
I0A
YA
3
I1A
3.3V
R3
R4
4.70K, 1%
4.70K, 1%
JTAG_MICTOR_TMS
JTAG_MICTOR_TDI
9V_VPP
3.3V
J4
3.3V
(12,16,21) MICTOR_RSTn
J32
B
MISO
MOSI_SDA
I2C_SDA_HPS R260 0
I2C_SCL_HPS R259 0
1
3
5
7
9
11
13
1
3
5
7
9
11
13
2
4
6
8
10
12
14
(12) JTAG_MICTOR_TDI
2
4
6
8
10
12
14
SCK_SCL
CSn
R258
0
JTAG_MICTOR_TCK
JTAG_MICTOR_TMS
JTAG_MICTOR_TDO
MICTOR_TRST
(12) JTAG_MICTOR_TCK
(12) JTAG_MICTOR_TMS
(12) JTAG_MICTOR_TDO
XJ4
881545-2
J16
1
2
HDR 2X7, VT, THM, 2mm
JTAG_MIC_SEL
2.5V_REG_HPS
R125 4.70K, 1%
CON2
Logic 0 = pin 10 <--> pin 9 (TRST from JTAG)
Logic 1 = pin 10 <--> pin 2 (TRST from MICTOR)
U57
JTAG_MIC_SEL
1
MICTOR_TRST
A
R310 10.0K
MICTOR_RSTn
JTAG_MICTOR_TDI
2
3
Logic 0 = pin 6 <--> pin 7 (Bypass)
Logic 1 = pin 6 <--> pin 4 (Enable)
4
5
IN1
NO1
COM1
NC1
GND
V+
NO2
NC2
IN2
COM2
10
9
8
MICTR_TRST
0
R318
(12,16) JTAG_TRST
2.5V_REG_HPS
C244
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
XJ7
5VDC
GND
CLKE
D15E
D14E
D13E
D12E
D11E
D10E
D9E
D8E
D7E
D6E
D5E
D4E
D3E
D2E
D1E
D0E
JTAG_HPS_TRST
SCL
SDA
CLKO
D15O
D14O
D13O
D12O
D11O
D10O
D9O
D8O
D7O
D6O
D5O
D4O
D3O
D2O
D1O
D0O
GND1
GND2
GND3
GND4
GND5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
39
40
41
42
43
TRACE_CLK_MIC
R338 10.0K
R33
MICTOR_PWR1
MICTOR_PWR2
TRACE_DATA7
TRACE_DATA6
TRACE_DATA5
TRACE_DATA4
TRACE_DATA3
TRACE_DATA2
TRACE_DATA1
R327
R328
MIC_34
R330
MIC_36
R331
TRACE_DATA0
3.3V
881545-2
J39
0_Ohms
1
2
SPI_MOSI
I2C_SDA_HPS 6
I2C_SCL_HPS 10
3.3V
0.1uF
0.001uf
Mictor38P
MISO
YB
7
MOSI_SDA
9
SCK_SCL
B
I1B
SPI_CSn
14
3.3V
13
I0C
YC
3.3V
I1C
I0D
YD
I1D
GND
E
12
1
R266
10.0K
CSn
CODEC_SEL
J31
1
2
15
CON2
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
7
Title
MIC_34
MIC_36
6
R329
R332
DNI
DNI
B
Date:
6
4
0.1uF
Size
7
11
8
C24
0.1uF
XJ3
I0B
S
C25
C686
2.2uF
881545-2
SPI_SCK
10K
10K
10K
10K
3.3V
TS5A23157
Manufacturer = Texas Instruments
PART_NUMBER = TS5A23157DGSR
8
5
CON2
C685
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
6
of
1
41
E1
8
7
6
5
4
3
Cyclone V GX SoC Bank 8
2
1
(4,17) HSMA_D[3:0]
(17) HSMA_TX_D_P[16:0]
(17) HSMA_TX_D_N[16:0]
E
E
(17) HSMA_RX_D_P[16:0]
(17) HSMA_RX_D_N[16:0]
(4,17) HSMA_CLK_OUT_P[2:1]
U21F
(4,17) HSMA_CLK_OUT_N[2:1]
(4,9,17) HSMA_CLK_IN_P[2:1]
CYCLONE V GX SoC BANK 8
(4,9,17) HSMA_CLK_IN_N[2:1]
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_TX_D_P16
HSMA_TX_D_N16
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P11
HSMA_TX_D_N11
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMA_TX_D_P1
HSMA_TX_D_N1
ENET_FPGA_MDIO (19)
ENET_FPGA_MDC (19)
HSMA_TX_D_P9
HSMA_TX_D_N9
D
C
B13
A13
C13
B12
F15
F14
C12
B11
D11
D10
A9
A8
C7
B7
E9
D9
C8
B8
H14
G13
C10
C9
F13
E13
A6
A5
H8
G8
A4
A3
E12
D12
D6
C5
H13
H12
D5
C4
Bank 8A
2.5 Volt
DIFFIO_TX_T2p,DQ1T
DIFFIO_TX_T2n,DQ1T
DIFFIO_RX_T3p,DQ1T
DIFFIO_RX_T3n,DQ1T
DIFFIO_RX_T5p,DQS1T
DIFFIO_RX_T5n,DQSn1T
DIFFIO_TX_T6p
DIFFIO_TX_T6n,DQ1T
DIFFIO_RX_T7p,DQ1T
DIFFIO_RX_T7n,DQ1T
DIFFIO_TX_T8p,DQ1T
DIFFIO_TX_T8n
DIFFIO_TX_T10p,DQ2T
DIFFIO_TX_T10n,DQ2T
DIFFIO_RX_T11p,DQ2T
DIFFIO_RX_T11n,DQ2T
DIFFIO_TX_T12p,DQ2T
DIFFIO_TX_T12n,DQ2T
DIFFIO_RX_T13p,DQS2T
DIFFIO_RX_T13n,DQSn2T
DIFFIO_TX_T14p
DIFFIO_TX_T14n,DQ2T
DIFFIO_RX_T15p,DQ2T
DIFFIO_RX_T15n,DQ2T
DIFFIO_TX_T16p,DQ2T
DIFFIO_TX_T16n
DIFFIO_RX_T17p
DIFFIO_RX_T17n
DIFFIO_TX_T18p,DQ3T
DIFFIO_TX_T18n,DQ3T
DIFFIO_RX_T19p,DQ3T
DIFFIO_RX_T19n,DQ3T
DIFFIO_TX_T20p,DQ3T
DIFFIO_TX_T20n,DQ3T
DIFFIO_RX_T21p,DQS3T
DIFFIO_RX_T21n,DQSn3T
DIFFIO_TX_T22p
DIFFIO_TX_T22n,DQ3T
DIFFIO_RX_T23p,DQ3T
DIFFIO_RX_T23n,DQ3T
DIFFIO_TX_T24p,DQ3T
DIFFIO_TX_T24n
DIFFIO_RX_T25p
DIFFIO_RX_T25n
DIFFIO_TX_T26p,DQ4T
DIFFIO_TX_T26n,DQ4T
DIFFIO_RX_T27p,DQ4T
DIFFIO_RX_T27n,DQ4T
DIFFIO_TX_T28p,DQ4T
DIFFIO_TX_T28n,DQ4T
DIFFIO_RX_T29p,DQS4T
DIFFIO_RX_T29n,DQSn4T
DIFFIO_TX_T30p
DIFFIO_TX_T30n,DQ4T
DIFFIO_RX_T31p,DQ4T
DIFFIO_RX_T31n,DQ4T
DIFFIO_TX_T32p,DQ4T
DIFFIO_TX_T32n
DIFFIO_RX_T33p
DIFFIO_RX_T33n
DIFFIO_TX_T34p,DQ5T
DIFFIO_TX_T34n,DQ5T
DIFFIO_RX_T35p,DQ5T
DIFFIO_RX_T35n,DQ5T
DIFFIO_TX_T36p,DQ5T
DIFFIO_TX_T36n,DQ5T
DIFFIO_RX_T37p,DQS5T
DIFFIO_RX_T37n,DQSn5T
DIFFIO_TX_T38p
DIFFIO_TX_T38n,DQ5T
DIFFIO_RX_T39p,DQ5T
DIFFIO_RX_T39n,DQ5T
DIFFIO_TX_T40p,DQ5T
DIFFIO_TX_T40n
HSMA_RX_D_P9
F11
HSMA_RX_D_N9
E11
HSMA_TX_D_P0
E8
HSMA_TX_D_N0
D7
HSMA_RX_D_P5
J7
HSMA_RX_D_N5
H7
HSMA_TX_D_P6
B2
HSMA_TX_D_N6
B1
HSMA_RX_D_P10
B6
HSMA_RX_D_N10
B5
HSMA_TX_D_P7
C3
HSMA_TX_D_N7
B3
HSMA_RX_D_P1
K12
HSMA_RX_D_N1
J12
HSMA_TX_D_P5
D2
HSMA_TX_D_N5
C2
HSMA_RX_D_P4
G12
HSMA_RX_D_N4
G11
HSMA_TX_D_P2
E4
HSMA_TX_D_N2
D4
HSMA_RX_D_P3
K7
HSMA_RX_D_N3
K8
HSMA_TX_D_P3
E3
HSMA_TX_D_N3
E2
HSMA_RX_D_P7
G10
HSMA_RX_D_N7
F10
HSMA_TX_D_P4
E1
HSMA_TX_D_N4
D1
HSMA_RX_D_P2
J10
HSMA_RX_D_N2
J9
HSMA_CLK_OUT_P2
E7
HSMA_CLK_OUT_N2
E6
HSMA_RX_D_P8
F9
HSMA_RX_D_N8
F8
(16,20,26)
0
I2C_SCL
G7 I2C_SCL_FPGA
I2C_SDA_FPGA
F6
(16,20,26)
0
I2C_SDA
D
C
R427
R426
5CSXFC6D_F896
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
7
of
1
41
E1
8
7
6
5
4
3
2
1
Cyclone V GX SoC Transceivers and Power
E
E
U21M
Cyclone V GX SoC Transceiver
AE2
AE1
AC2
AC1
AA2
AA1
PCIE_RX_P0 (3)
PCIE_RX_N0 (3)
PCIE_RX_P1 (3)
PCIE_RX_N1 (3)
PCIE_RX_P2 (3)
PCIE_RX_N2 (3)
GXB_RX_L0p,GXB_REFCLK_L0p
GXB_RX_L0n,GXB_REFCLK_L0n
GXB_RX_L1p,GXB_REFCLK_L1p
GXB_RX_L1n,GXB_REFCLK_L1n
GXB_RX_L2p,GXB_REFCLK_L2p
GXB_RX_L2n,GXB_REFCLK_L2n
W8
PCIE_REFCLK_QL0_P (10)
W7
PCIE_REFCLK_QL0_N (10)
GXB_LO
GXB_TX_L0p
GXB_TX_L0n
GXB_TX_L1p
GXB_TX_L1n
GXB_TX_L2p
GXB_TX_L2n
AD4
AD3
AB4
AB3
Y4
Y3
(3) PCIE_TX_P0
(3) PCIE_TX_N0
(3) PCIE_TX_P1
(3) PCIE_TX_N1
(3) PCIE_TX_P2
(3) PCIE_TX_N2
REFCLK0Lp
REFCLK0Ln
CMU PLL (PCIe)
D
(20) SDI_RX_P
W2
PCIE_RX_P3 (3)
W1
PCIE_RX_N3 (3)
GXB_RX_L4_P
U2
GXB_RX_L4_N
U1
HSMA_RX_P0(17) R2
HSMA_RX_N0 (17) R1
R137
SDI_RX_P
SDI_RX_N
0
R135 0
(20) SDI_RX_N
CAD Note:
R138
Overlap R137 & R138 DNI
Overlap R135 & R136
GXB_RX_L3p,GXB_REFCLK_L3p
GXB_RX_L3n,GXB_REFCLK_L3n
GXB_RX_L4p,GXB_REFCLK_L4p
GXB_RX_L4n,GXB_REFCLK_L4n
GXB_RX_L5p,GXB_REFCLK_L5p
GXB_RX_L5n,GXB_REFCLK_L5n
R136
DNI
CLK_148_P
CLK_148_N
T9
T8
GXB_L1
GXB_TX_L3p
GXB_TX_L3n
GXB_TX_L4p
GXB_TX_L4n
GXB_TX_L5p
GXB_TX_L5n
V4
V3
T4
T3
P4
P3
D
(3) PCIE_TX_P3
(3) PCIE_TX_N3
GXB_TX_L4_P
GXB_TX_L4_N
(17) HSMA_TX_P0
(17) HSMA_TX_N0
R61
R63
R62
DNI
REFCLK1Lp
REFCLK1Ln
SDI_TX_P
SDI_TX_N
0
0
CAD Note:
Overlap R22 & R27
R60 Overlap R24 & R19
DNI
SMA Connector Interface
OPTION_SMA_XCVR_TX_P
SMA Connector Interface
J10
1
5
4
3
2
C
J18
1OPTION_SMA_XCVR_RX_N
HSMA_RX_P1(17)
HSMA_RX_N1 (17)
HSMA_RX_P2(17)
HSMA_RX_N2 (17)
HSMA_RX_P3(17)
HSMA_RX_N3 (17)
N2
N1
L2
L1
J2
J1
REFCLK_QL2_P (10)
REFCLK_QL2_N (10)
P9
P8
CAD Note:
Place resistors
& capacitors
near SMA
connectors
GXB_RX_L6p,GXB_REFCLK_L6p
GXB_RX_L6n,GXB_REFCLK_L6n
GXB_RX_L7p,GXB_REFCLK_L7p
GXB_RX_L7n,GXB_REFCLK_L7n
GXB_RX_L8p,GXB_REFCLK_L8p
GXB_RX_L8n,GXB_REFCLK_L8n
GXB_TX_L6p
GXB_TX_L6n
GXB_TX_L7p
GXB_TX_L7n
GXB_TX_L8p
GXB_TX_L8n
REFCLK2Lp
REFCLK2Ln
RREF_TL
M4
M3
K4
K3
H4
H3
G1
(17) HSMA_TX_P1
(17) HSMA_TX_N1
(17) HSMA_TX_P2
(17) HSMA_TX_N2
(17) HSMA_TX_P3
(17) HSMA_TX_N3
J11
OPTION_SMA_XCVR_TX_N1
C
CAD Note:
Place resistors & capacitors
near SMA connectors
2
3
4
5
1OPTION_SMA_XCVR_RX_P
2
3
4
5
GXB_L2
J19
5
4
3
2
(20) SDI_TX_P
(20) SDI_TX_N
XCVR_RREF_TL
5CSXFC6D_F896
R413
2.00K
1%
CAD Note:
Place resistor near
RREF_TL pins.
Route away frm aggressor
SDI Reference Clocks
2.5V_REG_HPS
DNI
R54
B
From MAXV
C62
C66
0.1uF
10uF
B
X3
SI571_EN (16)
2
I2C_SDA_MAX (10,16) 7
I2C_SCL_MAX (10,16)8
3
OE
VDD
SDA
CLK+
SCL
CLK-
GND
Si571
VC
6
LVDS
4
CLK_148_CP C64
0.1uF
CLK_148_P
5
CLK_148_CN C65
0.1uF
CLK_148_N
1
SI571_VCONTROL
SDI_CLK148_UP (4) R58
4.99K
From FPGA
SDI_CLK148_DN (4)R59
4.99K
1000pF
C53
R57
180K C50
0.1uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
8
of
1
41
E1
8
7
HSMA_CLK_IN_P2
R412
6
5
4
3
2
1
Cyclone V GX SoC Clocks
100, 1% HSMA_CLK_IN_N2
E
E
U21N
D
D
Cyclone V GX SoC Clocks
(10) CLK_BOT1
1.5 Volt
CLK_BOT1
R453
AF15
AF14
0
R456
DNI
USER_LED_FPGA[3:0] (4,23)
USER_LED_FPGA1
USER_LED_FPGA2
Y16
W15
Bank 3B
CLK0n,FPLL_BL_FBn,DIFFIO_RX_B31n
CLK0p,FPLL_BL_FBp,DIFFIO_RX_B31p
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB,DIFFIO_TX_B37p,DQ5B,B_A_2
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn,DIFFIO_TX_B37n,DQ5B,B_A_3
(4,13) DDR3_FPGA_A[14:0]
AH12 DDR3_FPGA_A2
AJ12 DDR3_FPGA_A3
CLK1n,DIFFIO_RX_B39n
CLK1p,DIFFIO_RX_B39p
1.5 Volt
USER_LED_FPGA3
CLK_ENET_FPGA_PHY
CLK_ENET_FPGA_PHY (10)
(10) CLK_50M_FPGA
CLK_50M_FPGA
AB17
AA16
AD17
AC18
Bank 4A
CLK2n,DIFFIO_RX_B47n
CLK2p,DIFFIO_RX_B47p
CLK3n,DIFFIO_RX_B55n
CLK3p,DIFFIO_RX_B55p
C
C
2.5 Volt
(10) CLK_TOP1
(10) CLK_100M_FPGA
CLK_TOP1
CLK_100M_FPGA
(10) CLK_ENET_FPGA_P
(10) CLK_ENET_FPGA_N
Bank 5B
AA26
AB27
CLK_ENET_FPGA_P
CLK_ENET_FPGA_N
Y26
Y27
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
H15
G15
HSMA_CLK_IN0
PCIE_SMBDAT
K14
J14
CLK5p,DIFFIO_RX_R21p,DQS3R
CLK5n,DIFFIO_RX_R21n,DQSn3R
FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB,DIFFIO_TX_R22p
CLK4p,FPLL_BR_FBp,DIFFIO_RX_R23p,DQ3R
CLK4n,FPLL_BR_FBn,DIFFIO_RX_R23n,DQ3R
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn,DIFFIO_TX_R22n,DQ3R
AE29 PCIE_SMBCLK
PCIE_SMBCLK
AD29
(3) PCIE_PRSNT2_X1
A10
HSMA_CLK_OUT0
PCIE_SMBCLK (3)
2.5 Volt
(17) HSMA_CLK_IN_P2
(17) HSMA_CLK_IN_N2
(17) HSMA_CLK_IN0
(3) PCIE_SMBDAT
Bank 8A
B
CLK7p,DIFFIO_RX_T1p
CLK7n,DIFFIO_RX_T1n
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn,DIFFIO_TX_T4n,DQ1T
CLK6p,FPLL_TL_FBp,DIFFIO_RX_T9p
CLK6n,FPLL_TL_FBn,DIFFIO_RX_T9n
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB,DIFFIO_TX_T4p,DQ1T
(17) HSMA_CLK_OUT0
A11 (3) PCIE_PRSNT2_X4
B
5CSXFC6D_F896
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
9
of
1
41
E1
8
7
6
5
4
3
2
1
PLL
3.3V
DNI
C214
C211
PCIE_REFCLK_QL0_P
0.1uF
2.2uF
PCIE_REFCLK_QL0_N
PCIE_REFCLK_SYN_P
2.5V_REG_HPS
R250
2.5V_REG_HPS
PCIE_REFCLK_SYN_N
R252
E
E
DNI
U49
1
10
3
SDA
CLK+
SCL
CLK-
GND
NC
DanP:Consider to remove ac couplingl
6
REFCLK_QL2_C_P C19
100, 1%
REFCLK_QL2_C_N C18
4
R18
5
C207
0.1uF
(8) REFCLK_QL2_P
4
Y4
25.00MHz
2
2
3
0.1uF
(8) REFCLK_QL2_N
DanP:Consider to DNI termination
1
DNI
C206
DNI
4
5
SI570
Si570 Programmable Oscillator
Use Clock Control GUI
(Default 100MHz)
I2C Address 66 HEX
C84
C95
C102
742792780
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C113 C83
Y2
25.00MHz
2
1
2
3
2.5V_PLL1
R110
R109
4
5
6
DNI
DNI
I2C_SDA_MAX (8,10,16)
19
C
CLKIN_P
CLKIN_N
CLKIN
I2C_LSB
FDBK_P
FDBK_N
SCL
VDD1
VDD2
VDDO3
VDDO2
VDDO1
VDDO0
INTR
CLK3B
CLK3A
SDA
CLK2B
CLK2A
CLK1B
CLK1A
CLK0B
CLK0A
RSVD_GND
EPAD
2.5V_REG_HPS
C155
C165
C169
C153
0.1uF
0.1uF
0.1uF
0.1uF
3
DNI
DNI
1
2
VDD
VDD
XA_CLKIN
XB_CLKINB
VDDO0
VDDO1
VDDO2
VDDO3
1
C134
Y3
25.00MHz
2
2.5V_REG_HPS
C142
C154
0.1uF
0.1uF
VSS
VSS2
DIFF2
12
19
3
5
6
8
7
24
11
15
16
20
CLK0A
CLK0B
P1
P2
P3
P5
P6
CLK1A
CLK1B
CLK2A
CLK2B
LOS
CLK3A
CLK3B
A
GND
RSVD_GND
EPAD
24
7
2.5V_REG_HPS
6
2.5V_PLL1
2.5V_REG_HPS
L27
1V8
C465
C464
0.1uF
10uF
2.5V_PLL1
C483
R111
C503
C504
7
0(3) PCIE_REFCLK_SYN_P
R249
0(3) PCIE_REFCLK_SYN_N
R251
D
EN
OUT
NC
OUTn
VCC
GND
4
(9) CLK_ENET_FPGA_P
5
(9) CLK_ENET_FPGA_N
3
0.1uF
0.1uF
OSC1_CLK_SEL = HIGH selects (OSC1_CLK_SMA) SMA input
2.5V_REG_HPS
OSC1_CLK_SEL = LOW selects (OSC1_CLK_SYN) Si5356A input
2.5V_CLK_MUX L29
742792780
0.1uF
0.1uF
C674
C679
0.1uF
0.1uF
742792780
25Mhz
U52
OSC1_CLK_SYN
17
18
(6) CLK_OSC2
21
22
(9) CLK_TOP1 156.25MHz
10
7
J36
25Mhz
OSC1_CLK_SMA
1
SMA
1
6
11
16
OSC1_CLK_SEL
23
25
R103
DNI
R263
DNI
2.5V_REG_HPS
9
CMOS
Clk_in0
Clk_in1
SEL3
SEL2
SEL1
SEL0
EN
ICS83054AGI-01
PART_NUMBER = ICS83054AGI-01LFx
Manufacturer = IDT
C
2 R556
5
12
15
Q3
Q2
Q1
Q0
(6)
22CLK_OSC1
J13
1
2
OSC1_CLK_SEL
2.5V_REG_HPS
R74
1.00K
CON2
10.0K
B
1V8
X4
CLK50_EN (16)
2
1V8
(9) CLK_ENET_FPGA_PHY
1
C115
C114
0.1uF
0.1uF
1V8
EN
VCC
GND
OUT
50MHz
U23
4
2
C361
CLKIN_50
1V8
C362
2.2uF
0.1uF
3
3
6
7
5
25Mhz
VDD
CLKIN
OE1
OE2
OE3
CLKOUT1
CLKOUT2
CLKOUT3
OE_OSC
GND
25Mhz
8 R72
9 R64
10
22 (16) CLK_50M_MAX
22 (9) CLK_50M_FPGA
4
1V8
1
SL18860DC
Manufacturer = Silicon Labs
PART_NUMBER = SL18860DC
(16) CLK_100M_MAX
100Mhz
(9) CLK_100M_FPGA
C391
C392
0.1uF
0.1uF
TP7
100Mhz
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
4
23
25
Title
Si5335
Manufacturer = Silicon Labs
PART_NUMBER = Si5335A-B02062-GM
8
CLK_DIFF2_N
100MHz
(9) CLK_BOT1
13
14
C484
1.00K
R71
18 (19) CLK_DUAL_ENET_PHY
17
10
9
CLK_DIFF2_P
9
1V8
1V8
14
13
8
0(8) PCIE_REFCLK_QL0_P
R253
0(8) PCIE_REFCLK_QL0_N
R254
125.0MHz
1V8_PLL
20
16
15
11
22
21
CLK_DIFF1_N
X5
1
2
2.5V_PLL1
1V8_PLL
8
9
10
CLK_DIFF1_P
7
Si5356 Programmable Oscillator Use Clock Control GUI (Defaults 25MHz,
25MHz,25MHz,25MHz, 100MHz, 100MHz,50MHz, 50MHz)
I2C Address 70 HEX
2.5V_REG_HPS
U35
4
(12,16) CLK125A_EN
Si5338A-CUSTOM
Manufacturer = Silicon Labs
PART_NUMBER = Si5338C-A01917-GM
B
C135
DIFF2
6
4
13
1
DNI
U29
12
I2C_SCL_MAX (8,10,16)
1V8
XIN/CLKIN
2.5V_REG_HPS
R436
1.00K CLK125A_EN
4
C101
DIFF1
Si52112
PART_NUMBER = SI52112-A1-GM2
Manufacturer = Silicon Laboratories
CLK125A_EN
L7
DNI
3
C89
2.5V_REG_HPS
DIFF1
XOUT
5
4
3
2
D
2.5V_PLL1
VDD
VDD2
3
14
8
I2C_SCL_MAX (8,10,16)
VCC
3
7
I2C_SDA_MAX (8,10,16)
OE
1
SI570_EN (12,16) 2
VDDQ0
VDDQ1
2.2uF
8
0.1uF
X1
VDD
C7
VSS0
VSS1
C11
PLL
SI570_EN
1.00K
I2C_SDA_MAX
DNI
I2C_SCL_MAX
DNI
R13
R7
R14
Size
B
Date:
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
10
of
1
41
E1
8
7
6
5
4
3
2
1
Cyclone V GX SoC Configuration
DNI
C463
DNI
U21G
R432
DNI
Cyclone V GX SoC Configuration
E
AD7
FPGA_CONFIG_D[15:0] (15,16)
U7
FPGA_DCLK (15,16)
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
FPGA_CONFIG_D8
FPGA_CONFIG_D9
FPGA_CONFIG_D10
FPGA_CONFIG_D11
FPGA_CONFIG_D12
FPGA_CONFIG_D13
FPGA_CONFIG_D14
FPGA_CONFIG_D15
D
AE6
AE5
AE8
AC7
AB8
AE9
AE12
AD9
AD11
AF10
AD10
AE11
AC9
AH4
AE7
AG3
TMS
TCK
TDI
TDO
Bank 3A
2.5V BANK
CLKUSR,DIFFIO_RX_B5p,DQ1B
DCLK
AS_DATA0,ASDO,DATA0
AS_DATA1,DATA1
AS_DATA2,DATA2
AS_DATA3,DATA3
nCSO,DATA4
DATA5,DIFFIO_TX_B2n
DATA6,DIFFIO_RX_B1n,DQ1B
DATA7,DIFFIO_TX_B2p,DQ1B
DATA8,DIFFIO_RX_B1p,DQ1B
DATA9,DIFFIO_TX_B4n,DQ1B
DATA10,DIFFIO_RX_B3n,DQSn1B
DATA11,DIFFIO_TX_B4p
DATA12,DIFFIO_RX_B3p,DQS1B
DATA13,DIFFIO_TX_B6n,DQ1B
DATA14,DIFFIO_RX_B5n,DQ1B
DATA15,DIFFIO_TX_B6p,DQ1B
2.5V_REG_FPGA
D
10K 10K 10K 10K
PR_READY,DIFFIO_TX_B8n,DQ1B
PR_DONE,DIFFIO_RX_B7n
PR_ERROR,DIFFIO_RX_B7p
Bank 5A
2.5V BANK
CPU_RESETn (16,23)
MAX_FPGA_MOSI
(16) MAX_FPGA_MOSI
C
MAX_FPGA_MISO
(16) MAX_FPGA_MISO
AD27
AE26
AD25
J5
F4
F3
FPGA_nCONFIG (16)
FPGA_nSTATUS (16)
FPGA_CONF_DONE (16)
USER I/O INTERFACES
PR_REQUEST,DIFFIO_TX_R1n,DQ1R
CvP_CONFDONE,DIFFIO_TX_R3n,DQ1R
CRC_ERROR,DIFFIO_RX_R2n
DEV_CLRn,DIFFIO_TX_R5n,DQ1R
DEV_OE,DIFFIO_TX_R5p
nPERSTL0,DIFFIO_RX_R6p,DQS1R
nPERSTR0,DIFFIO_RX_R6n,DQSn1R
INIT_DONE,DIFFIO_RX_R2p
nCEO,DIFFIO_TX_R3p,DQ1R
nCONFIG
nSTATUS
CONF_DONE
MSEL4
MSEL3
MSEL2
MSEL1
MSEL0
Bank 9A
2.5V BANK
2.5V_REG_FPGA
R397
10K
FPGA_nSTATUS
R411
10K
FPGA_CONF_DONE
R415
10K FPGA_nCONFIG
R414
10KJTAG_FPGA_TDI
G5
R448
V9
AC5
U8
AB9
R458
JTAG_FPGA_TMS (12)
JTAG_MUX_TCK(12,16,17)
JTAG_FPGA_TDI (12)
JTAG_FPGA_TDO (12)
E
R457
R433
R459
FPGA_DCLK
AG8
AF5
AF4
(16) FPGA_PR_READY
(16) FPGA_PR_DONE
(16) FPGA_PR_ERROR
AH28
AH29
AC25 MAX_FPGA_SSEL
(16) FPGA_PR_REQUEST
(16) FPGA_CvP_CONFDONE
MAX_FPGA_SSEL(16)
W21
W22
(3) PCIE_WAKEn
(3,4) PCIE_PERSTn
AJ29 MAX_FPGA_SCK
L9
L7
G6
K6
L8
C
MAX_FPGA_SCK (16)
(16) MSEL4
(16) MSEL3
(16) MSEL2
(16) MSEL1
(16) MSEL0
nCE
5CSXFC6D_F896
B
B
2.5V_REG_FPGA
OPEN
SW3
1
2
3
4
5
6
12
11
10
9
8
7
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
R306
R305
R304
R303
R302
1.00k
1.00k
1.00k
1.00k
1.00k
TDA06H0SB1
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
11
of
1
41
E1
8
7
2.5V_REG_HPS
R212
6
5
USB Blaster Programming Header
(uses JTAG mode only)
1.00k
4
2.5V_REG_HPS
JTAG
2.5V_REG_HPS
J23
USB_DISABLEn (25)
E
R209
0
2
4
6
8
10
1
(12,25) JTAG_TCK
JTAG_BLASTER_TDI
3
5
(12,25) JTAG_TMS
7
9 (12,25) JTAG_BLASTER_TDO
R210
Logic 0 = pin 10 <--> pin 9 (HPS Bypass)
Logic 1 = pin 10 <--> pin 2 (HPS Enable)
1.00k
HPS_JTAG_EN
R201
JTAG_MUX_HPS_TDI
R202
Populate R58 if you would like to
Master the JTAG chain through
HSMA
HPS_JTAG_EN
FPGA_JTAG_EN
HSMA_JTAG_EN
MAX_JTAG_EN
OPEN
HPS
Logic 0 = pin 6 <--> pin 7 (HPS Bypass)
Logic 1 = pin 6 <--> pin 4 (HPS Enable)
JTAG_MUX_TMS
2.5V_REG_HPS
JTAG Chain Control
8
7
6
5
JTAG_BLASTER_TDI
0
R40
2
IN1
COM1
NO1
NC1
1
(6,16) JTAG_TRST
(6,16,21) MICTOR_RSTn
SW4
DNI
2
R325
R324
R323
R322
HPS_JTAG_EN
1.00k
1.00k
1.00k
1.00k
1
When Pins 1 & 5 are:
LOW --> NC to/from COM = ON and NO to/from COM = OFF
HIGH --> NC to/from COM = OFF and NO to/from COM = ON
U7
1
1.00k
70247-1051
JTAG_BLASTER_TDO
1
2
3
4
3
TS5A23157 Switch Functions
3
4
5
NO2
JTAG_MUX_TDO
9
FPGA
2.5V_REG_HPS
8
C266
7
BP_HPS_TMSR25
E
0(11,12) JTAG_FPGA_TDI
R24
0
GND
V+
1
10
0
IN2
NC2
COM2
0.1uF
2.5V_REG_HPS
1.00k
6 (6,12) JTAG_HPS_TMS
Logic 0 = pin 10 <--> pin 9 (FPGA Bypass)
Logic 1 = pin 10 <--> pin 2 (FPGA Enable) TS5A23157
U8
TDA04H0SB1 ON = not-in-chain
OFF = in-chain
SW2
D
OPEN
8
7
6
5
1
2
3
4
CLK125A_EN
SI570_EN
FACTORY_LOAD
SECURITY_MODE
2.5V_REG_HPS
10.0K
10.0K
1V8
10.0K
10.0K
R317
R308
R307
R287
CLK125A_EN
SI570_EN
FACTORY_LOAD
SECURITY_MODE
(10,16) CLK125A_EN
(10,16) SI570_EN
(16) FACTORY_LOAD
(16) SECURITY_MODE
FPGA_JTAG_EN
JTAG_FPGA_TDO (11)
1
2
JTAG_MUX_TMS
3.3V
3
4
U16
(11,12,16,17) JTAG_MUX_TCK
JTAG_MUX_TCK
2
JTAG_MICTOR_TCK
(6,12) JTAG_MICTOR_TCK
3
FPGA_JTAG_EN
VCC
I0A
YA
4
(6) JTAG_HPS_TCK
JTAG_MUX_TMS
JTAG_MICTOR_TMS6
(6,12) JTAG_MICTOR_TMS
JTAG_MUX_HPS_TDI
C
5
JTAG_MUX_HPS_TDI
JTAG_MICTOR_TDO
(6,12) JTAG_MICTOR_TDO
11
10
I1A
I0B
YB
7(6,12) JTAG_HPS_TMS
JTAG_FPGA_TDI
14
JTAG_MICTOR_TDI
(6,12) JTAG_MICTOR_TDI
13
I0C
YC
9
Logic 0 = pin 6 <--> pin 7 (HSMA Bypass)
Logic 1 = pin 6 <--> pin 4 (HSMA Enable)
(6) JTAG_HPS_TDI
JTAG_MUX_TMS
I1C
I0D
YD
I1D
GND
E
12 (6) JTAG_HPS_TDO
1
15
3
4
5
MAX_JTAG_EN
881545-2
J6
3.3V
C40
C41
2.2uF
0.1uF
JTAG_HPS_SEL
1
2
JTAG_MAX_TDO(16)
CON2
Logic 0 = pin 6 <--> pin 7 (HSMBBypass)
Logic 1 = pin 6 <--> pin 4 (HSMB Enable)
MAX_JTAG_EN
U15
2
JTAG_MICTOR_TCK
3
(12,25) JTAG_TCK
(6,12) JTAG_MICTOR_TCK
JTAG_TMS
5
JTAG_MICTOR_TMS
6
JTAG_BLASTER_TDI
11
(12,25) JTAG_TMS
(6,12) JTAG_MICTOR_TMS
(25) JTAG_BLASTER_TDI
JTAG_MICTOR_TDI
(6,12) JTAG_MICTOR_TDI
10
0
(17) JTAG_HSMA_TDI
R26
0
IN2
NC2
COM2
8
C265
D
0.1uF
2.5V_REG_HPS
7
6
BP_FPGA_TMS
R27
1.00k
(11) JTAG_FPGA_TMS
TS5A23157
IN1
COM1
NO1
1
NC1
0
GND
NO2
IN2
V+
1
0
NC2
COM2
10
9
MAX
(16)
0 JTAG_MAX_TDI
R28
JTAG_HSMA_TDI
2.5V_REG_HPS
8
C264
0.1uF
2.5V_REG_HPS
7
BP_HSMA_TMS
R29
C
1.00k
6 (17) JTAG_HSMA_TMS
U10
1
2
3
4
3.3V
JTAG_TCK
V+
1
HSMA
(11,12) JTAG_FPGA_TDI
2.5V_REG_HPS
TS5A23157
Logic 0 = pin 10 <--> pin 9 (MAX II Bypass)
Logic 1 = pin 10 <--> pin 2 (MAX II Enable)
JTAG_MUX_TMS
16
NO2
9
XJ5
JTAG_HPS_SEL
1
IDTQS3VH257
Manufacturer = IDT
3.3V
PART_NUMBER = QS3VH257PAG
R43
1.00k JTAG_HPS_SEL
B
NC1
10
0
GND
I1B
S
8
5
JTAG_HSMA_TDO (17) 2
HSMA_JTAG_EN
(11,12) JTAG_FPGA_TDI
NO1
Logic 0 = pin 10 <--> pin 9 (HSMA Bypass)
Logic 1 = pin 10 <--> pin 2 (HSMA Enable) U9
HSMA_JTAG_EN
(12) JTAG_MUX_TMS
COM1
1
Logic 0 = pin 6 <--> pin 7 (FPGA Bypass)
Logic 1 = pin 6 <--> pin 4 (FPGA Enable)
TDA04H0SB1
16
IN1
5
IN1
COM1
NO1
NC1
GND
V+
NO2
IN2
NC2
COM2
10
9
MUX
(12)
0 JTAG_MUX_TDI
R30
JTAG_MAX_TDI
2.5V_REG_HPS
8
C263
7
BP_MAX_TMS
0.1uF
2.5V_REG_HPS
R31
1.00k
6 (16) JTAG_MAX_TMS
B
VCC
I0A
YA
4
JTAG_MUX_TCK
7
JTAG_MUX_TMS
TS5A23157
Manufacturer = Texas Instruments
PART_NUMBER = TS5A23157DGSR
JTAG_MUX_TCK(11,12,16,17)
I1A
I0B
YB
JTAG_MUX_TMS(12)
I1B
I0C
YC
JTAG_MUX_TDI
9
JTAG_MUX_TDI (12)
I1C
XJ6
JTAG_BLASTER_TDO
(12,25) JTAG_BLASTER_TDO
A
JTAG_MICTOR_TDO
(6,12) JTAG_MICTOR_TDO
14
13
I0D
YD
I1D
S
8
3.3V
R44
1.00k
JTAG_SEL
GND
E
JTAG_MUX_TDO
12
3.3V
JTAG_SEL
1
C38
C39
2.2uF
0.1uF
JTAG_SEL
15
IDTQS3VH257
Manufacturer = IDT
PART_NUMBER = QS3VH257PAG
Title
Size
CON2
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
881545-2
J7
1
2
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
12
of
1
41
E1
8
7
DDR3_FPGA_CLK_P
100, 1%
6
5
E
4
3
2
1024MB DDR3 (x32) - FPGA
DDR3_FPGA_CLK_N
R469
VTT_FPGA_DDR3
DDR3_FPGA_BA[2:0] (4)
VTT_FPGA_DDR3
DDR3_FPGA_DM[3:0] (4)
1
2
3
4
DDR3_FPGA_DQS_P[3:0] (4)
DDR3_FPGA_DQS_N[3:0] (4)
VTT_FPGA_DDR3
CN6
8
7
6
5
1
2
3
4
CN4
0.1uF
0.1uF
VTT_FPGA_DDR3
CN5
8
1
7
2
6
3
5
4
0.1uF
8
7
6
5
V31
V30
V32
V28
V10
V37
V18
V24
V20
DDR3_FPGA_A11
DDR3_FPGA_A1
DDR3_FPGA_BA1
DDR3_FPGA_A9
DDR3_FPGA_ODT
DDR3_FPGA_A14
DDR3_FPGA_BA2
DDR3_FPGA_A5
DDR3_FPGA_CKE
1
RN4A
4
RN4D
RN4G 7
2
RN5B
5
RN5E
8
RN5H
3
RN6C
RN6F
6
R472
16 51 V38
13 51 V33
10 51 V19
15 51 V36
12 51 V12
9 51 V15
14 51 V23
11 51
4.70K, 1%
V35
1
VTT_FPGA_DDR3 1.5V_REG_FPGA
DDR3_FPGA_A8
DDR3_FPGA_A4
DDR3_FPGA_A10
DDR3_FPGA_A13
DDR3_FPGA_CASn
DDR3_FPGA_CSn
DDR3_FPGA_A3
2
RN4B
5
RN4E
RN4H
8
3
RN5C
6
RN5F
1
RN6A
4
RN6D
RN6G 7
DDR3_FPGA_RESETn
2.00K
15 51
12 51
9 51
14 51
11 51
16 51
13 51
10 51
R497
V34
V29
V25
V17
V11
V16
V26
V27
DDR3_FPGA_A6
DDR3_FPGA_A12
DDR3_FPGA_A7
DDR3_FPGA_WEn
DDR3_FPGA_RASn
DDR3_FPGA_BA0
DDR3_FPGA_A0
DDR3_FPGA_A2
VTT_FPGA_DDR3
RN4C
RN4F
RN5A
RN5D
RN5G
RN6B
RN6E
RN6H
3
6
1
4
7
2
5
8
14
11
16
13
10
15
12
9
51
51
51
51
51
51
51
51
E
DDR3_FPGA_DQ[31:0] (4)
DDR3_FPGA_A[14:0] (4,9)
DDR3_FPGA_A0 N3
DDR3_FPGA_A1 P7
DDR3_FPGA_A2 P3
DDR3_FPGA_A3 N2
DDR3_FPGA_A4 P8
DDR3_FPGA_A5 P2
DDR3_FPGA_A6 R8
DDR3_FPGA_A7 R2
DDR3_FPGA_A8 T8
DDR3_FPGA_A9 R3
DDR3_FPGA_A10 L7
DDR3_FPGA_A11 R7
DDR3_FPGA_A12 N7
DDR3_FPGA_A13 T3
DDR3_FPGA_A14 T7
D
DDR3_FPGA_CKE K9
DDR3_FPGA_CLK_P J7
DDR3_FPGA_CLK_N K7
(4) DDR3_FPGA_CKE
(4) DDR3_FPGA_CLK_P
(4) DDR3_FPGA_CLK_N
DDR3_FPGA_DM2
DDR3_FPGA_DM3
(4) DDR3_FPGA_DM2
(4) DDR3_FPGA_DM3
DDR3_FPGA_CSn
L2
DDR3_FPGA_WEn L3
DDR3_FPGA_RASn J3
DDR3_FPGA_CASn K3
(4) DDR3_FPGA_CSn
(4) DDR3_FPGA_WEn
(4) DDR3_FPGA_RASn
(4) DDR3_FPGA_CASn
C
E7
D3
DDR3_FPGA_BA0 M2
DDR3_FPGA_BA1
N8
DDR3_FPGA_BA2 M3
DDR3_FPGA_RESETnT2
DDR3_FPGA_ODT K1
DDR3_FPGA_ZQ1
L8
VREF_FPGA_DDR3
H1
M8
R473
C590
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V_REG_FPGA
A1
A8
C1
C9
D2
E9
F1
H2
H9
(4) DDR3_FPGA_BA0
(4) DDR3_FPGA_BA1
(4) DDR3_FPGA_BA2
(4) DDR3_FPGA_RESETn
(4) DDR3_FPGA_ODT
B
1.5V_REG_FPGA
C568
A
2.2nF
U37
MT41K256M16HA-125:E
Manufacturer = Micron
PART_NUMBER = MT41K256M16HA-125:E
DDR3 Device
A0
DDR3_FPGA_DQ16
E3
A1
DQ0 F7
DDR3_FPGA_DQ21
A2
DQ1 F2
DDR3_FPGA_DQ17
A3
DQ2 F8
DDR3_FPGA_DQ19
A4
DQ3 H3 DDR3_FPGA_DQ20
A5
DQ4 H8 DDR3_FPGA_DQ18
A6
DQ5 G2 DDR3_FPGA_DQ22
A7
DQ6 H7 DDR3_FPGA_DQ23
A8
DQ7 D7 DDR3_FPGA_DQ24
A9
DQ8 C3 DDR3_FPGA_DQ26
A10/AP
DQ9 C8 DDR3_FPGA_DQ25
A11
DQ10 C2 DDR3_FPGA_DQ27
A12/BCn
DQ11 A7
DDR3_FPGA_DQ29
A13
DQ12 A2
DDR3_FPGA_DQ30
A14
DQ13 B8
DDR3_FPGA_DQ28
DQ14 A3
DDR3_FPGA_DQ31
CKE
DQ15
CK_P
DDR3_FPGA_DQS_P2
F3
CK_N
LDQS_P G3 DDR3_FPGA_DQS_N2
LDQS_N C7 DDR3_FPGA_DQS_P3
LDM
UDQS_P B7
DDR3_FPGA_DQS_N3
UDM
UDQS_N
CS
WE
RAS
CAS
NC1
NC2
NC3
NC4
NC5
BA0
BA1
BA2
RESETn
ODT
ZQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
U38
DDR3_FPGA_A0 N3
DDR3_FPGA_A1 P7
DDR3_FPGA_A2 P3
DDR3_FPGA_A3 N2
DDR3_FPGA_A4 P8
DDR3_FPGA_A5 P2
DDR3_FPGA_A6 R8
DDR3_FPGA_A7 R2
DDR3_FPGA_A8 T8
DDR3_FPGA_A9 R3
DDR3_FPGA_A10 L7
DDR3_FPGA_A11 R7
DDR3_FPGA_A12 N7
DDR3_FPGA_A13 T3
DDR3_FPGA_A14 T7
DDR3_FPGA_CKE K9
DDR3_FPGA_CLK_P J7
DDR3_FPGA_CLK_N K7
(4) DDR3_FPGA_DM0
(4) DDR3_FPGA_DM1
DDR3_FPGA_BA0 M2
DDR3_FPGA_BA1
N8
DDR3_FPGA_BA2 M3
DDR3_FPGA_RESETnT2
DDR3_FPGA_ODT K1
DDR3_FPGA_ZQ
L8
VREF_FPGA_DDR3
H1
M8
R471
C586
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V_REG_FPGA
A1
A8
C1
C9
D2
E9
F1
H2
H9
B1
B9
D1
D8
E2
E8
F9
G1
G9
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
C572 C585
C601
C571
C598
C569
C589
C583
C597
C570
C574
C587
2.2nF
2.2nF 2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
3300pF
3300pF
4.7nF
4.7nF
4.7nF
E7
D3
DDR3_FPGA_CSn
L2
DDR3_FPGA_WEn L3
DDR3_FPGA_RASn J3
DDR3_FPGA_CASn K3
J1
J9
L1
L9
M7
C602
DDR3_FPGA_DM0
DDR3_FPGA_DM1
DDR3 Device
A0
A1
DQ0
A2
DQ1
A3
DQ2
A4
DQ3
A5
DQ4
A6
DQ5
A7
DQ6
A8
DQ7
A9
DQ8
A10/AP
DQ9
A11
DQ10
A12/BCn
DQ11
A13
DQ12
A14
DQ13
DQ14
CKE
DQ15
CK_P
CK_N
LDQS_P
LDQS_N
LDM
UDQS_P
UDM
UDQS_N
CS
WE
RAS
CAS
NC1
NC2
NC3
NC4
NC5
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR3_FPGA_DQ0
DDR3_FPGA_DQ1
DDR3_FPGA_DQ2
DDR3_FPGA_DQ3
DDR3_FPGA_DQ4
DDR3_FPGA_DQ5
DDR3_FPGA_DQ6
DDR3_FPGA_DQ7
DDR3_FPGA_DQ8
DDR3_FPGA_DQ9
DDR3_FPGA_DQ10
DDR3_FPGA_DQ11
DDR3_FPGA_DQ12
DDR3_FPGA_DQ13
DDR3_FPGA_DQ14
DDR3_FPGA_DQ15
F3
G3
C7
B7
DDR3_FPGA_DQS_P0
DDR3_FPGA_DQS_N0
DDR3_FPGA_DQS_P1
DDR3_FPGA_DQS_N1
D
J1
J9
L1
L9
M7
C
B1
B9
D1
D8
E2
E8
F9
G1
G9
B
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
MT41K256M16HA-125:E
Manufacturer = Micron
PART_NUMBER = MT41K256M16HA-125:E
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
1.5V_REG_FPGA
Title
C600
C599
C603 C577
C596
C576
C579
C575
C578
C588
C584
0.01uF
0.01uF
0.01uF 0.1uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
0.47uF
0.47uF
Size
B
Date:
8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
13
of
1
41
E1
8
7
DDR3_HPS_CLK_P
100, 1%
DDR3_HPS_BA[2:0] (5)
5
3
2
VTT_HPS_DDR3
1
2
3
4
DDR3_HPS_DQS_P[4:0] (5)
4
1024MB DDR3 (x32 + ECC) - HPS
VTT_HPS_DDR3
DDR3_HPS_DM[4:0] (5)
E
6
DDR3_HPS_CLK_N
R428
DDR3_HPS_DQS_N[4:0] (5)
VTT_HPS_DDR3
CN2
8
7
6
5
1
2
3
4
0.1uF
VTT_HPS_DDR3
CN1
8
1
7
2
6
3
5
4
CN3
0.1uF
DDR3_HPS_A8
DDR3_HPS_A6
DDR3_HPS_A10
DDR3_HPS_A0
DDR3_HPS_A14
DDR3_HPS_A1
DDR3_HPS_RASn
DDR3_HPS_A7
DDR3_HPS_CKE
8
7
6
5
0.1uF
1
4
7
2
5
8
3
6
R420
RN1A
RN1D
RN1G
RN2B
RN2E
RN2H
RN3C
RN3F
16
13
10
15
12
9
14
11
51
51
51
51
51
51
51
51
4.70K, 1%
VTT_HPS_DDR3
DDR3_HPS_BA2
DDR3_HPS_A12
2
RN1B
5
RN1E
RN1H
8
DDR3_HPS_A13
3
RN2C
DDR3_HPS_CASn RN2F
6
DDR3_HPS_ODT
1
RN3A
DDR3_HPS_A3 RN3D
4
DDR3_HPS_A5 RN3G 7
DDR3_HPS_RESETn
2.00K
1
VTT_HPS_DDR3
1.5V_REG_HPS
DDR3_HPS_A4
DDR3_HPS_BA1
DDR3_HPS_A9
DDR3_HPS_A2
DDR3_HPS_A11
DDR3_HPS_CSn
DDR3_HPS_BA0
DDR3_HPS_WEn
15 51
12 51
9 51
14 51
11 51
16 51
13 51
10 51
R431
RN1C
RN1F
RN2A
RN2D
RN2G
RN3B
RN3E
RN3H
3
6
1
4
7
2
5
8
14
11
16
13
10
15
12
9
51
51
51
51
51
51
51
51
E
DDR3_HPS_DQ[39:0] (5)
DDR3_HPS_A[14:0] (5)
DDR3_HPS_A0
N3
DDR3_HPS_A1
P7
DDR3_HPS_A2
P3
DDR3_HPS_A3
N2
DDR3_HPS_A4
P8
DDR3_HPS_A5
P2
DDR3_HPS_A6
R8
DDR3_HPS_A7
R2
DDR3_HPS_A8
T8
DDR3_HPS_A9 R3
DDR3_HPS_A10 L7
DDR3_HPS_A11 R7
DDR3_HPS_A12 N7
DDR3_HPS_A13 T3
DDR3_HPS_A14 T7
D
DDR3_HPS_CKE
K9
DDR3_HPS_CLK_P J7
DDR3_HPS_CLK_N K7
(5) DDR3_HPS_CKE
(5) DDR3_HPS_CLK_P
(5) DDR3_HPS_CLK_N
1.5V_REG_HPS
DDR3_HPS_DM4
R452
240
E7
D3
DDR3_HPS_CSn
DDR3_HPS_WEn
DDR3_HPS_RASn
DDR3_HPS_CASn
L2
L3
J3
K3
(5) DDR3_HPS_CSn
(5) DDR3_HPS_WEn
(5) DDR3_HPS_RASn
(5) DDR3_HPS_CASn
C
DDR3_HPS_BA0
M2
DDR3_HPS_BA1
N8
DDR3_HPS_BA2
M3
DDR3_HPS_RESETn T2
DDR3_HPS_ODT
K1
DDR3_HPS_ZQ1
L8
VREF_HPS_DDR3
H1
M8
R447
C493
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V_REG_HPS
A1
A8
C1
C9
D2
E9
F1
H2
H9
(5) DDR3_HPS_BA0
(5) DDR3_HPS_BA1
(5) DDR3_HPS_BA2
(5) DDR3_HPS_RESETn
(5) DDR3_HPS_ODT
B
1.5V_REG_HPS
A
U30
MT41K256M16HA-125:E
Manufacturer = Micron
PART_NUMBER = MT41K256M16HA-125:E
DDR3 Device
A0
DDR3_HPS_DQ35
E3
A1
DQ0 F7
DDR3_HPS_DQ32
A2
DQ1 F2
DDR3_HPS_DQ34
A3
DQ2 F8
DDR3_HPS_DQ39
A4
DQ3 H3 DDR3_HPS_DQ36
A5
DQ4 H8 DDR3_HPS_DQ38
A6
DQ5 G2 DDR3_HPS_DQ37
A7
DQ6 H7 DDR3_HPS_DQ33
A8
DQ7 D7 R438
10.0K
A9
DQ8 C3 R462
10.0K
A10/AP
DQ9 C8 R439
10.0K
A11
DQ10 C2 R463
10.0K
A12/BCn
DQ11 A7 R441
10.0K
A13
DQ12 A2 R464
10.0K
A14
DQ13 B8 R440
10.0K
DQ14 A3 R465
10.0K
CKE
DQ15
CK_P
DDR3_HPS_DQS_P4
F3
CK_N
LDQS_P G3 DDR3_HPS_DQS_N4
LDQS_N C7
R450
240
LDM
UDQS_P B7
R451
240
UDM
UDQS_N
DDR3_HPS_A0
N3
DDR3_HPS_A1
P7
DDR3_HPS_A2
P3
DDR3_HPS_A3
N2
DDR3_HPS_A4
P8
DDR3_HPS_A5
P2
DDR3_HPS_A6
R8
DDR3_HPS_A7
R2
DDR3_HPS_A8
T8
DDR3_HPS_A9 R3
DDR3_HPS_A10 L7
DDR3_HPS_A11 R7
DDR3_HPS_A12 N7
DDR3_HPS_A13 T3
DDR3_HPS_A14 T7
DDR3_HPS_CKE
K9
DDR3_HPS_CLK_P J7
DDR3_HPS_CLK_N K7
1.5V_REG_HPS
CS
WE
RAS
CAS
NC1
NC2
NC3
NC4
NC5
BA0
BA1
BA2
RESETn
ODT
ZQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
J1
J9
L1
L9
M7
DDR3_HPS_DM2
DDR3_HPS_DM3
E7
D3
DDR3_HPS_CSn
DDR3_HPS_WEn
DDR3_HPS_RASn
DDR3_HPS_CASn
L2
L3
J3
K3
U22
MT41K256M16HA-125:E
Manufacturer = Micron
PART_NUMBER = MT41K256M16HA-125:E
DDR3 Device
A0
DDR3_HPS_DQ21
E3
A1
DQ0 F7
DDR3_HPS_DQ23
A2
DQ1 F2
DDR3_HPS_DQ20
A3
DQ2 F8
DDR3_HPS_DQ22
A4
DQ3 H3 DDR3_HPS_DQ16
A5
DQ4 H8 DDR3_HPS_DQ18
A6
DQ5 G2 DDR3_HPS_DQ17
A7
DQ6 H7 DDR3_HPS_DQ19
A8
DQ7 D7 DDR3_HPS_DQ29
A9
DQ8 C3 DDR3_HPS_DQ27
A10/AP
DQ9 C8 DDR3_HPS_DQ24
A11
DQ10 C2 DDR3_HPS_DQ31
A12/BCn
DQ11 A7
DDR3_HPS_DQ28
A13
DQ12 A2
DDR3_HPS_DQ30
A14
DQ13 B8
DDR3_HPS_DQ25
DQ14 A3
DDR3_HPS_DQ26
CKE
DQ15
CK_P
DDR3_HPS_DQS_P2
F3
CK_N
LDQS_P G3 DDR3_HPS_DQS_N2
LDQS_N C7 DDR3_HPS_DQS_P3
LDM
UDQS_P B7
DDR3_HPS_DQS_N3
UDM
UDQS_N
DDR3_HPS_BA0
M2
DDR3_HPS_BA1
N8
DDR3_HPS_BA2
M3
DDR3_HPS_RESETn T2
DDR3_HPS_ODT
K1
DDR3_HPS_ZQ2
L8
VREF_HPS_DDR3
H1
M8
R425
C285
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V_REG_HPS
A1
A8
C1
C9
D2
E9
F1
H2
H9
B1
B9
D1
D8
E2
E8
F9
G1
G9
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC1
NC2
NC3
NC4
NC5
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J1
J9
L1
L9
M7
DDR3_HPS_A0
N3
DDR3_HPS_A1
P7
DDR3_HPS_A2
P3
DDR3_HPS_A3
N2
DDR3_HPS_A4
P8
DDR3_HPS_A5
P2
DDR3_HPS_A6
R8
DDR3_HPS_A7
R2
DDR3_HPS_A8
T8
DDR3_HPS_A9 R3
DDR3_HPS_A10 L7
DDR3_HPS_A11 R7
DDR3_HPS_A12 N7
DDR3_HPS_A13 T3
DDR3_HPS_A14 T7
DDR3_HPS_CKE
K9
DDR3_HPS_CLK_P J7
DDR3_HPS_CLK_N K7
DDR3_HPS_DM0
DDR3_HPS_DM1
E7
D3
DDR3_HPS_CSn
DDR3_HPS_WEn
DDR3_HPS_RASn
DDR3_HPS_CASn
L2
L3
J3
K3
U14
MT41K256M16HA-125:E
Manufacturer = Micron
PART_NUMBER = MT41K256M16HA-125:E
DDR3 Device
A0
DDR3_HPS_DQ2
E3
A1
DQ0 F7
DDR3_HPS_DQ4
A2
DQ1 F2
DDR3_HPS_DQ7
A3
DQ2 F8
DDR3_HPS_DQ5
A4
DQ3 H3
DDR3_HPS_DQ3
A5
DQ4 H8
DDR3_HPS_DQ0
A6
DQ5 G2 DDR3_HPS_DQ6
A7
DQ6 H7
DDR3_HPS_DQ1
A8
DQ7 D7
DDR3_HPS_DQ10
A9
DQ8 C3
DDR3_HPS_DQ13
A10/AP
DQ9 C8
DDR3_HPS_DQ8
A11
DQ10 C2
DDR3_HPS_DQ12
A12/BCn
DQ11 A7
DDR3_HPS_DQ11
A13
DQ12 A2
DDR3_HPS_DQ15
A14
DQ13 B8
DDR3_HPS_DQ9
DQ14 A3
DDR3_HPS_DQ14
CKE
DQ15
CK_P
DDR3_HPS_DQS_P0
F3
CK_N
LDQS_P G3 DDR3_HPS_DQS_N0
LDQS_N C7
DDR3_HPS_DQS_P1
LDM
UDQS_P B7
DDR3_HPS_DQS_N1
UDM
UDQS_N
DDR3_HPS_BA0
M2
DDR3_HPS_BA1
N8
DDR3_HPS_BA2
M3
DDR3_HPS_RESETn T2
DDR3_HPS_ODT
K1
DDR3_HPS_ZQ
L8
VREF_HPS_DDR3
H1
M8
R372
C445
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V_REG_HPS
A1
A8
C1
C9
D2
E9
F1
H2
H9
B1
B9
D1
D8
E2
E8
F9
G1
G9
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
CS
WE
RAS
CAS
NC1
NC2
NC3
NC4
NC5
BA0
BA1
BA2
RESETn
ODT
ZQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C311
C283 C289 C518
C366
C549
C517
C364
C520
C443
C288
C420
C419
C491
C396
C324
C369
C495
C310
C447
C519
C545
C444
C325
C284
C365
C492
2.2nF
2.2nF 2.2nF 2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
3300pF
3300pF
4.7nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C
TP5
DDR3_HPS_DQ14
R390
33
+/-1%
B1
B9
D1
D8
E2
E8
F9
G1
G9
TP6
DDR3_HPS_DQ15
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
B
TP3
R389
33
+/-1%
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
1.5V_REG_HPS
Title
C547
C326
C446 C294
C367
C506
C546
C309
C418
C496
C287
C370
C497
C371
C286
C368
C494
C327
C448
C548
0.01uF
0.01uF
0.01uF 0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
Size
B
Date:
8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
2.2nF
DDR3 ECC TEST
TP4
VREFDQ
VREFCA
C328
J1
J9
L1
L9
M7
D
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
14
of
1
41
E1
8
7
6
5
4
3
2
1
FLASH, EPCQ
FM BUS
NOR PARALLEL FLASH
FM_D[15:0] (16)
EPCQ
FM_A[26:1] (16)
E
E
FLASH 512Mb (32M X 16)
U6
FM_A1
FM_A2
FM_A3
FM_A4
FM_A5
FM_A6
FM_A7
FM_A8
FM_A9
FM_A10
FM_A11
FM_A12
FM_A13
FM_A14
FM_A15
FM_A16
FM_A17
FM_A18
FM_A19
FM_A20
FM_A21
FM_A22
FM_A23
FM_A24
FM_A25
FM_A26
3.3V
C316
C315
0.1uF
0.1uF
C30
C31
0.1uF
0.1uF
U13
1
2
NC01
NC02
NC03
NC04
NC05
NC06
NC07
NC08
EPCQ256
Manufacturer = Altera
PART_NUMBER = EPCQ256SI16N
VCC
3
4
5
6
11
12
13
14
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
GND
U20
FPGA_AS_DATA0
FPGA_AS_DATA1
FPGA_AS_DATA2
FPGA_AS_DATA3
FPGA_nCSO
FPGA_AS_DATA0
15
FPGA_AS_DATA1
8
FPGA_AS_DATA2
9
FPGA_AS_DATA3
1
16(11,16) FPGA_DCLK
FPGA_nCSO
7
2
3
4
5
6
7
8
9
10
11
23
10
D
NC
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BE
GND
24
FPGA_CONFIG_D0 (11,16)
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
22
21
20
19
18
17
16
15
14
13
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
C
(11,16)
(11,16)
(11,16)
(11,16)
12
IDTQS3861
Manufacturer = IDT
PART_NUMBER = IDTQS3861QG
MAX_AS_CONF (16)
XJ1
9V_VPP
J5
FLASH_CLK (16)
1
2
881545-2
9V_VPP
FLASH_RESETn (16)
FLASH_CEn0 (16)
FLASH_OEn (16)
FLASH_WEn (16)
FLASH_ADVn (16)
FLASH_WPn
CON2
VPP
U4
C22
4.7uF
4.7K 3
R335
VIN
VOUT
ADJ/BYPASS
SHDN
GND
5
4
2
D13
LT1761_CSENSE
R333
1V8
D4
B4
F8
G8
F6
C6
A1
A2
VCC
A3
VCC
A4
A5
VCCQ
A6
VCCQ
A7
VCCQ
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
NC(64M)/A23
D13
NC(64M,128M)/A24
D14
NC/A25(512M)
D15
NC/A26(1G)
WAIT
CLK
GND
RESET#
GND
CE#
GND
OE#
GND
WE#
ADV#
RFU0
WP#
RFU1
RFU2
RFU3
1V8
A4
A6
H3
1V8
D5
D6
G4
F2
E2
G3
E4
E5
G5
G6
H7
FM_D0
FM_D1
FM_D2
FM_D3
FM_D4
FM_D5
FM_D6
FM_D7
E1
E3
F3
F4
F5
H5
G7
E7
FM_D8
FM_D9
FM_D10
FM_D11
FM_D12
FM_D13
FM_D14
FM_D15
D
(16) FLASH_RDYBSYn
F7
C
B2
H2
H4
H6
H1
G2
F1
E8
PC28F512P30BF
Manufacturer = Micron
PART_NUMBER = PC28F512P30BFA
C17
4.7uF
LT1761
PART_NUMBER = LT1761ES5-SD#PBF
Manufacturer = Linear Technology
B
E6
VPP
36K
CMDSH-3
R334
5.62k
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
VPP
12V
1
VPP
PC28FxxxP30B85
FLASH
5.0V
1V8
1V8
R363
R336
R326
R362
10K
10K
10K
10K
FLASH_WPn
FLASH_WEn
FLASH_RDYBSYn
1V8
B
C246
C247
C257
C253
C268
C267
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
FLASH_RESETn
- When using a single x16 flash device a word consists of 16 data
bits so addressing starts with FM_A1 mapped to address bit 1 in software.
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
15
of
1
41
E1
8
7
6
5
4
3
5M2210 System Controller
U19A
E
D
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
D3
C2
C3
E3
D2
E4
D1
E5
FPGA_CONFIG_D8
FPGA_CONFIG_D9
FPGA_CONFIG_D10
FPGA_CONFIG_D11
FPGA_CONFIG_D12
FPGA_CONFIG_D13
FPGA_CONFIG_D14
FPGA_CONFIG_D15
F3
E1
F4
F2
F1
F6
G2
G3
MAX_FPGA_MOSI
MAX_FPGA_MISO
MAX_AS_CONF
MAX_FPGA_SSEL
MAX_FPGA_SCK
G1
G4
H2
G5
H3
J1
H4
J2
USB_B2_CLK
CLK_100M_MAX
H5
J5
DIFFIO_L1P
DIFFIO_L1N
DIFFIO_L2P
DIFFIO_L2N
DIFFIO_L3P
DIFFIO_L3N
DIFFIO_L4P
DIFFIO_L4N
DIFFIO_L13P
DIFFIO_L13N
DIFFIO_L14P
DIFFIO_L14N
DIFFIO_L15P
DIFFIO_L15N
DIFFIO_L16P
DIFFIO_L16N
DIFFIO_L5P
DIFFIO_L5N
DIFFIO_L6P
DIFFIO_L6N
DIFFIO_L7P
DIFFIO_L7N
DIFFIO_L8P
DIFFIO_L8N
DIFFIO_L17P
DIFFIO_L17N
DIFFIO_L18P
DIFFIO_L18N
DIFFIO_L19P
DIFFIO_L19N
DIFFIO_L20P
DIFFIO_L20N
DIFFIO_L9P
DIFFIO_L21P
DIFFIO_L9N DIFFIO_L21N
DIFFIO_L10P
DIFFIO_L10N
IOB1_1
DIFFIO_L11P
IOB1_2
DIFFIO_L11N
IOB1_3
DIFFIO_L12P
IOB1_4
DIFFIO_L12N
IOB1_5
IOB1/CLK0
IOB1/CLK1
J4
K1
J3
K2
K5
L1
L2 0
K3 0
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_DCLK
SI571_EN
M1
M2
L4
L3
N1
M4
N2
M3
I2C_SCL_MAX
I2C_SDA_MAX
N3
P2
FPGA_CvP_CONFDONE
FPGA_PR_ERROR
HSMA_PRSNTn
E2
F5
H1
K4
L5
FPGA_PR_READY
FPGA_PR_REQUEST
FPGA_PR_DONE
CLK50_EN
CLK125A_EN
D4
B1
C5
C4
B4
D6
E6
B5
R552
(6,12) JTAG_TRST
R546
(6,12,21) MICTOR_RSTn
A5
D7
B6
E7
C8
B7
D8
A7
FPGA_nCONFIG
Si570_EN
M570_PCIE_JTAG_EN
B8
A8
A9
E9
B9
D9
A10
C9
DIFFIO_T13P
DIFFIO_T13N
DIFFIO_T14P
DIFFIO_T14N
DIFFIO_T15P
DIFFIO_T15N
DIFFIO_T16P
DIFFIO_T16N
DIFFIO_T5P
DIFFIO_T5N
DIFFIO_T6P
DIFFIO_T6N
DIFFIO_T7P
DIFFIO_T7N
DIFFIO_T8P
DIFFIO_T8N
DIFFIO_T17P
DIFFIO_T17N
DIFFIO_T18P
DIFFIO_T18N
E14
C14
C15
E13
E12
D15
F14
D16
FM_A8
FM_A9
FM_A10
FM_A11
FM_A12
FM_A13
FM_A14
FM_A15
F13
E15
E16
F15
G14
F16
G13
G15
FM_A16
FM_A17
FM_A18
FM_A19
FM_A20
FM_A21
FM_A22
FM_A23
G12
G16
H14
H15
H13
H16
J13
J16
CLK_50M_MAX
J12
H12
DIFFIO_R1P
DIFFIO_R1N
DIFFIO_R2P
DIFFIO_R2N
DIFFIO_R3P
DIFFIO_R3N
DIFFIO_R4P
DIFFIO_R4N
DIFFIO_R5P
DIFFIO_R5N
DIFFIO_R6P
DIFFIO_R6N
DIFFIO_R7P
DIFFIO_R7N
DIFFIO_R8P
DIFFIO_R8N
DIFFIO_R9P
DIFFIO_R9N
DIFFIO_R10P
DIFFIO_R10N
DIFFIO_R11P
DIFFIO_R11N
DIFFIO_R12P
DIFFIO_R12N
IOB3/CLK2
IOB3/CLK3
IOB2_8
IOB2_9
IOB2_10
IOB2_11
IOB2_12
IOB2_13
IOB2_14
IOB2_15
IOB2_16
IOB2_17
IOB2_18
IOB2_19
IOB2_20
E10 (26) OVERTEMP
A11(22) USB_RESET
HPS_RESETn
B11
A12
MAX_CONF_DONE
E11
B12
QSPI_RESETn
C11
PGM_SEL
B13
(15) FM_A[26:0]
DIFFIO_R17P
DIFFIO_R17N
DIFFIO_R18P
DIFFIO_R18N
DIFFIO_R19P
DIFFIO_R19N
DIFFIO_R20P
DIFFIO_R20N
DIFFIO_R21P
DIFFIO_R21N
DIFFIO_R22P
DIFFIO_R22N
IOB3_21
IOB3_22
IOB3_23
IOB3_24
IOB3_25
IOB3_26
IOB3_27
HPS_RESETn (6,21)
QSPI_RESETn (21)
FM_D0
FM_D1
FM_D2
FM_D3
FM_D4
FM_D5
FM_D6
FM_D7
L15
L12
M16
L13
M15
L14
N16
M13
FM_D8
FM_D9
FM_D10
FM_D11
FM_D12
FM_D13
FM_D14
FM_D15
R1
P4
T2
P5
R3
N5
P6
N6
R5
M6
T5
P7
R6
N7
M7
R7
N15
N14
P15
P14
FLASH_WEn
FLASH_CEn0
FLASH_OEn
FLASH_RDYBSYn
D13
D14
F11
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
F12
K12
M14
N13
FM_A24
FM_A25
FM_A26
USB_CFG2
USB_CFG3
USB_CFG4
USB_CFG5
USB_CFG6
USB_CFG7
USB_CFG8
USB_CFG9
P8
T7
N8
R8
T8
T9
R9
P9
MAX_RESETn
USB_CFG10
M9
M8
(15) FLASH_RESETn
(15) FLASH_CLK
(15) FLASH_ADVn
(10,12) CLK125A_EN
MAX_FPGA_SSEL(11)
(10) CLK50_EN
MAX_FPGA_SCK (11)
(10,12) Si570_EN
(8) SI571_EN
(11) MSEL0
(11) MSEL1
(11) MSEL2
(11) MSEL3
(11) MSEL4
PCIE_JTAG_EN
CPU_RESETn
SDI_TX_EN
SDI_RX_BYPASS
SDI_RX_EN
DIFFIO_B5P
DIFFIO_B5N
DIFFIO_B6P
DIFFIO_B6N
DIFFIO_B7P
DIFFIO_B7N
DIFFIO_B8P
DIFFIO_B8N
DIFFIO_B14P
DIFFIO_B14N
DIFFIO_B15P
DIFFIO_B15N
DIFFIO_B16P
DIFFIO_B16N
DIFFIO_B17P
DIFFIO_B17N
DIFFIO_B19P
DIFFIO_B19N
DIFFIO_B18P
DIFFIO_B18N
DIFFIO_B20P
DIFFIO_B20N
DIFFIO_B21P
DIFFIO_B21N
I2C_SDA_MAX
2.5V_REG_HPS
R419
R418
10K I2C_SCL_MAX
10K I2C_SDA_MAX
DIFFIO_B9P DIFFIO_B22P
DIFFIO_B9N DIFFIO_B22N
DIFFIO_B10P
IOB4_28
DIFFIO_B10N
IOB4_29
DIFFIO_B11P
IOB4_30
DIFFIO_B11N
IOB4_31
DIFFIO_B12P
IOB4_32
DIFFIO_B12N
IOB4_33
F7
G6
H7
H9
J10
J8
K11
L10
M10
R10
N10
T11
P10
R11
T12
N11
T13
R13
R12
P11
N12
R14
P12
T15
R16
P13
M11
M12
N9
R4
T10
T4
(7,20,26)
0 I2C_SCL
R424
(7,20,26)
0 I2C_SDA
R423
(4,17,23) HSMA_PRSNTn
MAX_FPGA_MOSI
MAX_FPGA_MISO
(8,10) I2C_SCL_MAX
(8,10) I2C_SDA_MAX
EXTRA_SIG1
SECURITY_MODE
M570_CLOCK
FACTORY_STATUS
FACTORY_REQUEST
EXTRA_SIG2
(25) TRST
(25) RST
USB_CFG0
USB_CFG11
USB_CFG1
DIFFIO_B13N/DEV_CLRn
DIFFIO_B13P/DEV_OE
A1
A16
B15
B2
G10
G7
G8
G9
K10
K7
K8
K9
R15
R2
T1
T16
T6
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
F10
G11
H10
H8
J7
J9
K6
L7
C1
H6
J6
P1
A14
A3
F8
F9
C
(15,16) MAX_AS_CONF
ON-BOARD USB BLASTER II
USB_CFG[11:0]
USB_CFG[11:0] (25)
EXTRA_SIG[2:0]
EXTRA_SIG[2:0] (25)
2.5V_REG_HPS
(4,25) USB_B2_CLK
PCIE_JTAG_EN
(25) M570_PCIE_JTAG_EN
(25) M570_CLOCK
(25) FACTORY_STATUS
(25) FACTORY_REQUEST
MAXV DIPSWITCH
CLK_SEL
1V8
C16
H11
J11
P16
B
(12) FACTORY_LOAD
(12) SECURITY_MODE
PUSH BUTTON INTERFACE
1.5V_REG_HPS
PGM_SEL
PGM_CONFIG
MAX_RESETn
L8
L9
T14
T3
PGM_SEL(23)
PGM_CONFIG (23)
MAX_RESETn(23)
LED INTERFACE
PGM_LED[2:0]
5M2210ZF256
Manufacturer = Altera Corporation
PART_NUMBER = 5M2210ZF256C4N
1.5V_REG_HPS
1V8
2.5V VCCIO
MAX_FPGA_MOSI(11)
MAX_FPGA_MISO(11)
(11,23) CPU_RESETn
1V8
MAX V
Power
PGM_LED[2:0] (23)
MAX_ERROR
MAX_LOAD
MAX_CONF_DONE
5M2210ZF256
Manufacturer = Altera Corporation
PART_NUMBER = 5M2210ZF256C4N
2.5V_REG_HPS
D
(15,16) MAX_AS_CONF
I2C_SCL_MAX
U19E
DIFFIO_B1P
DIFFIO_B1N
DIFFIO_B2P
DIFFIO_B2N
DIFFIO_B3P
DIFFIO_B3N
DIFFIO_B4P
DIFFIO_B4N
E
(15) FLASH_OEn
(15) FLASH_RDYBSYn
(10) CLK_50M_MAX
(10) CLK_100M_MAX
U19D
J14
J15
K16
K13
K15
K14
L16
L11
(11) FPGA_PR_DONE
(11) FPGA_PR_REQUEST
(11) FPGA_PR_READY
(11) FPGA_PR_ERROR
(11) FPGA_CvP_CONFDONE
(5,20) SDI_TX_EN
(5,20) SDI_RX_BYPASS
(5,20) SDI_RX_EN
FACTORY_LOAD
A2
MAX_ERROR
A4
MAX_LOAD
A6
B10
MSEL0
B3
MSEL1
C10
MSEL2
C12
MSEL3
C6
MSEL4
C7
D10
D11
D5
E8
(15) FLASH_WEn
(15) FLASH_CEn0
MAX_FPGA_SSEL
MAX_FPGA_SCK
A13 CLK_SEL
A15
MAX V
BANK4
DIFFIO_R13P
DIFFIO_R13N
DIFFIO_R14P
DIFFIO_R14N
DIFFIO_R15P
DIFFIO_R15N
DIFFIO_R16P
DIFFIO_R16N
(11) FPGA_nSTATUS
(11) FPGA_CONF_DONE
(11,15) FPGA_DCLK
(11) FPGA_nCONFIG
PGM_CONFIG
PGM_LED0
PGM_LED1
PGM_LED2
D12
B14
C13
B16
5M2210ZF256
Manufacturer = Altera Corporation
PART_NUMBER = 5M2210ZF256C4N
5M2210ZF256
Manufacturer = Altera Corporation
PART_NUMBER = 5M2210ZF256C4N
VCCINT
1V8
IOB2_6
IOB2_7
DIFFIO_T9P
DIFFIO_T9N
DIFFIO_T10P
DIFFIO_T10N
DIFFIO_T11P
DIFFIO_T11N
DIFFIO_T12P
DIFFIO_T12N
MAX V
BANK3
FM_A0
FM_A1
FM_A2
FM_A3
FM_A4
FM_A5
FM_A6
FM_A7
A
DIFFIO_T1P
DIFFIO_T1N
DIFFIO_T2P
DIFFIO_T2N
DIFFIO_T3P
DIFFIO_T3N
DIFFIO_T4P
DIFFIO_T4N
(11,12,17) JTAG_MUX_TCK
P3
L6 (12) JTAG_MAX_TDI
M5 (12) JTAG_MAX_TDO
N4 (12) JTAG_MAX_TMS
TCK
TDI
TDO
TMS
5M2210ZF256
Manufacturer = Altera Corporation
PART_NUMBER = 5M2210ZF256C4N
U19C
B
MAX V
BANK2
1
(15) FM_D[15:0]
(11,15) FPGA_CONFIG_D[15:0]
U19B
MAX V
BANK1
C
2
MAX_ERROR (23)
MAX_LOAD(23)
MAX_CONF_DONE (23)
1.5V VCCIO
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
C345
C322
C320
C304
C319
C318
C321
C337
C346
C305
C281
C282
C306
C323
C291
C394
C317
C395
C336
C393
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
16
of
1
41
E1
8
7
6
5
4
3
2
1
HSMC Port A
J12
HSMA_SDA (4)
JTAG_MUX_TCK(11,12,16)
JTAG_HSMA_TDO (12)
HSMA_CLK_OUT0 (9)
R694
D
38.3
C785
HSMA_D0
HSMA_D2
HSMA_TX_D_P0
HSMA_TX_D_N0
HSMA_TX_D_P1
HSMA_TX_D_N1
22pF
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_TX_D_P6
HSMA_TX_D_N6
C
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_TX_D_P11
HSMA_TX_D_N11
B
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_TX_D_P16
HSMA_TX_D_N16
12V
A
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
3.3V
C335
22uF
25V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
3.3V
C482
22uF
25V
BANK 1
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
ASP-122953-01
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
A
BANK 3
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
HSMA_TX_P3(8)
HSMA_TX_N3(8)
HSMA_TX_P2(8)
HSMA_TX_N2(8)
HSMA_TX_P1(8)
HSMA_TX_N1(8)
HSMA_TX_P0(8)
HSMA_TX_N0(8)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
(8) HSMA_RX_P3
20
(8) HSMA_RX_N3
22
(8) HSMA_RX_P2
24
(8) HSMA_RX_N2
(8) HSMA_RX_P1
26
28
(8) HSMA_RX_N1
30
(8) HSMA_RX_P0
32
(8) HSMA_RX_N0
34
(4) HSMA_SCL
36 (12) JTAG_HSMA_TMS
38 (12) JTAG_HSMA_TDI
40
(9) HSMA_CLK_IN0
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
HSMA_D1
HSMA_D3
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMA_RX_D_P8
HSMA_RX_D_N8
E
(4) HSMA_D[3:0]
(7) HSMA_TX_D_P[16:0]
(7) HSMA_TX_D_N[16:0]
(7) HSMA_RX_D_P[16:0]
(4,7) HSMA_CLK_OUT_P[2:1]
HSMA_RX_D_P1
HSMA_RX_D_N1
(4,7) HSMA_CLK_OUT_N[2:1]
(4,9) HSMA_CLK_IN_P[2:1]
HSMA_RX_D_P2
HSMA_RX_D_N2
(4,9) HSMA_CLK_IN_N[2:1]
HSMA_RX_D_P3
HSMA_RX_D_N3
(4,16,23) HSMA_PRSNTn
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMA_RX_D_P6
HSMA_RX_D_N6
C
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMA_RX_D_P11
HSMA_RX_D_N11
B
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMA_PRSNTn
12V
Title
Size
Date:
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
B
8
D
(7) HSMA_RX_D_N[16:0]
HSMA_RX_D_P0
HSMA_RX_D_N0
161
162
163
164
165
166
167
168
169
170
171
172
E
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
17
of
1
41
E1
8
7
6
5
4
3
2
10/100/1000 Ethernet - HPS
ETHERNET INTERFACE
ENET_HPS_TXD[3..0]
U11A
ENET_HPS_MDC 36
ENET_HPS_MDIO 37
E
ENET_HPS_LED2_LINK
ENET_HPS_RESETn 42
3.3V_REG_HPS
ENET_HPS_INTn
J2
13
YA
YK Yellow
TD0_P
CT0
TD0_N
18
19
TD2_P
CT2
TD2_N
GND_TAB
GND_TAB
OK
TD3_P
CT3
TD3_N
GK
GOA
Orange
D
15
17
R1
220
CT0
4
6
5
CT1
3
1
2
CT2
8
7
9
CT3
RESET_N
MDI_HPS_P0
MDI_HPS_N0
MDI_HPS_P1
MDI_HPS_N1
MDI_HPS_P2
MDI_HPS_N2
MDI_HPS_P3
MDI_HPS_N3
2
3
5
6
7
8
10
11
4.99K
ENET_HPS_RSET 48
16
3.3V_REG_HPS
TXRXP_A
TXRXM_A
TXRXP_B
TXRXM_B
TXRXP_C
TXRXM_C
TXRXP_D
TXRXM_D
17
15
220
DNI
3
C49
ENET_HPS_LED1_LINK
C48
CT0
0.01uF
CT1
DNI
Y1
25.00MHz
2
RXD0_MODE0
RXD1_MODE1
RXD2_MODE2
RXD3_MODE3
35
ENET_HPS_RX_CLK
24
ENET_HPS_GTX_CLK
25
ENET_HPS_TX_EN
33
ENET_HPS_RX_DV
22
21
20
19
ENET_HPS_TXD3
ENET_HPS_TXD2
ENET_HPS_TXD1
ENET_HPS_TXD0
ENET_HPS_RXD[3..0]
ENET_HPS_RXD[3..0] (6)
ENET_HPS_RX_CLK
ENET_HPS_RX_DV
ENET_HPS_MDIO
ENET_HPS_INTn
2.5V_REG_HPS
U28
1
2 A0
3 A1
4 A2
GND
ENET_HPS_RXD0
ENET_HPS_RXD1
ENET_HPS_RXD2
ENET_HPS_RXD3
32
31
28
27
ENET_HPS_GTX_CLK (6)
ENET_HPS_TX_EN (6)
ENET_HPS_MDC (6,18)
E
ENET_HPS_RESETn (18,21)
ENET_HPS_RX_CLK (6)
ENET_HPS_RX_DV (6)
ENET_HPS_MDIO (6,18)
ENET_HPS_INTn (6,18)
2.5V_REG_HPS
8
VCC 7
WP (6,23,27)
6
I2C_SCL_HPS
SCL (6,23,27)
5
I2C_SDA_HPS
SDA
24LC32A
PART_NUMBER = 24LC32A-I/SN
Manufacturer = Microchip Technology Inc.
D
CLK125_NDO_LED_MODE
41
LED1_PHYAD0
LED2_PHYAD1
3.3V_REG_HPS
46
45
1
4
0.01uF
TXD3
TXD2
TXD1
TXD0
CLK125_NDO_LED_MODE
ENET_HPS_LED1_LINK
ENET_HPS_LED2_LINK
ENET_L829-1J1T-43
C15
GTX_CLK
ISET
R2
C16
RX_CLK_PHYAD2
INT_N
RX_DV_CLK125_EN
R50
Green
C
MDC
MDIO
TX_EN
11
12
10
ENET_HPS_TXD[3..0] (6)
ENET_HPS_GTX_CLK
ENET_HPS_TX_EN
ENET_HPS_MDC
ENET_HPS_RESETn
MDI INTERFACE
TD1_P
CT1
TD1_N
14
38
1
XI
XO
3.3V_REG_HPS L1
KSZ9021RN
Manufacturer = Micrel
PART_NUMBER = KSZ9021RN
C21
C27
10uF
10uF
3.3V_AVDDH
3A, 30 Ohm FB
3.3V_REG_HPS
C26
22uF
L24
1.2V_AVDLL_PLL
C28
C23
2.2uF
0.1uF
C43
22uF
C58
C44
2.2uF
0.1uF
L4
3.3V_DVDDH
1.2V_AVDDL
C
1.2V_AVDLL_PLL
C13
0.01uF
CT2
C14
0.01uF
CT3
U11B
3.3V_AVDDH
47
12
1
3.3V_DVDDH
40
16
34
1.2V AVDLL_PLL
2.5V_REG_HPS
5.0V
49
13
29
U18
1
2
C52
4
10uF
OUT2
OUT1
SW
SHDN
10.0K
LTC3026
ADJ
PG
5
C47
1uF
1.2V_AVDLL_PLL
10
9
8
7
R56
R55
1.00K
3
11
2.5V_REG_HPS
R46
BST
GND
GND
6
B
IN1
IN2
AVDDL_PLL
LDO_O
AVDDH
AVDDH
AVDDH
AVDDL
AVDDL
DVDDH
DVDDH
DVDDH
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
P_GND
VSS_PS
VSS
44
43
1.2V_AVDDL
3A, 30 Ohm FB
C262
22uF
3A, 30 Ohm FB C59
22uF
9
4
C60
C61
2.2uF
0.1uF
L3
1.2V_DVDDL
18
14
39
30
26
23
1.2V_DVDDL
3A, 30 Ohm FB C56
22uF
KSZ9021RN
Manufacturer = Micrel
PART_NUMBER = KSZ9021RN
2.00K
C270
C261
2.2uF
0.1uF
C57
C55
2.2uF
0.1uF
Place near KSZ9021RN PHY
B
3.3V
C45
22uF
C46
2.2uF
R340
R339
R347
R364
R365
R368
R369
R378
R406
ENET_HPS_LED2_LINK
ENET_HPS_LED1_LINK
ENET_HPS_RXD3
ENET_HPS_RXD2
ENET_HPS_RXD1
ENET_HPS_RXD0
ENET_HPS_RX_DV
ENET_HPS_RX_CLK
CLK125_NDO_LED_MODE
DNI
DNI
4.70K, 1%
4.70K, 1%
4.70K, 1%
4.70K, 1%
DNI
4.70K, 1%
4.70K, 1%
R342
R341
R348
R366
R367
R370
R371
R379
R407
1.00k
1.00k
DNI
DNI
DNI
DNI
4.70K, 1%
DNI
DNI
3.3V_REG_HPS
R47
R42
R48
R49
4.70K, 1%
4.70K, 1%
4.70K, 1%
4.70K, 1%
(6,18) ENET_HPS_MDIO
(6,18) ENET_HPS_MDC
(6,18) ENET_HPS_INTn
(18,21) ENET_HPS_RESETn
BOOT-STRAPS
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
18
of
1
41
E1
8
7
6
5
4
3
2
1
10/100M Ethernet - FPGA
ENET2_RX_D0
ENET2_RX_D1
ENET2_RX_D2
ENET2_RX_D3
ENET2_RX_ERROR (5)
ENET2_RX_DV (5)
ENET2_RX_CLK (5)
ENET2_TX_CLK_FB (5)
R502
R523
ENET2_RX_D0
ENET2_RX_D1
ENET2_RX_D2
ENET2_RX_D3
ENET2_RX_ERROR
ENET2_RX_DV
ENET2_RX_CLK
DNI
4.70K, 1%
35
36
37
38
40
39
41
42
22
P1RXD0
P1RXD1
P1RXD2
P1RXD3
P1RXERR
P1RXDV
P1RXCLK
P1CRS
P1COL
33
34
CLK_DUAL_ENET_PHY (10)
80
1
ENET_DUAL_RESETn (4,21)
R540
R479
R512
R522
R238
0
DNI REG_FB
4.70K, 1%
4.70K, 1%
4.70K, 1%
DNI
R504
R503
ENET_DUAL_RESETn
P0TXERR_PHY
P1TXERR_PHY
ENET2_TX_CLK_FB
63
62
4.70K, 1%
4.70K, 1%
B
P1100BTLED
P1ACTLED
P1LINKED
MDIO
MDC
EXTRES
REGAGND
REGBGND1
REGBGND2
P0AGND
P1AGND
GNDIO
GND15
VSSAPLL
ENET_FPGA_MDIO (7)
ENET_FPGA_MDC (7)
79
13
2
4.70K, 1%
4.70K, 1%
4.70K, 1%
DR
ATP
TEST
3.3V
4.70K, 1%
P0100BTLED
P0ACTLED
P0LINKED
3.3V
R528
R533
R515
R720
P1RXP
P1RXN
REGOFF
RESETB
R237 DNI
R213
P1TXP
P1TXN
XCLK0
XCLK1
3.3V
C
P0RXP
P0RXN
15
16
ENET1_MDI_TX_P
ENET1_MDI_TX_N
17
18
ENET1_MDI_RX_P
ENET1_MDI_RX_N
7
6
ENET2_MDI_TX_P
ENET2_MDI_TX_N
5
4
ENET2_MDI_RX_P
ENET2_MDI_RX_N
64
68
69
ENET1_ACT_LED
ENET1_LINK_LED
12pF
C228
12pF
C225
12pF
C226
0.01uF
12pF
R236
10
GND
GND_TAB
GND_TAB
C230
0.01uF
Green
D
3.3V
P0TXERR(4,19)
R526
ENET1_LINK_LED
0
R276
ENET2_ACT_LED R273
220
220
3.3V
C
3.3V
61
65
67
ENET2_ACT_LED
ENET2_LINK_LED
12
R527
J33
12.4K
R226
10
R228
49.9
R227
49.9
R224
49.9
R223
49.9
R225
10
76
74
75
14
8
31
51
9
1
TD+
2
TCT
3
RD+
5
RCT
6
3.3V
4.70K, 1% ENET2_RX_D0
4.70K, 1% ENET2_RX_D1
ENET2_RX_CLK
DNI
4.70K, 1% ENET1_RX_ERROR
ENET2_RX_ERROR
DNI
4.70K, 1% ENET1_RX_CLK
4.70K, 1% ENET1_RX_DV
4.70K, 1% ENET2_RX_DV
ENET1_RX_D0
DNI
ENET1_RX_D1
DNI
R509
R501
R478
R488
R495
R490
R486
R500
R482
R484
DNI
DNI
4.70K, 1%
DNI
4.70K, 1%
DNI
DNI
DNI
4.70K, 1%
4.70K, 1%
C220
C222
C221
C218
C217
0.01uF
12pF
12pF
12pF
12pF
RD-
8
13
14
C219
0.01uF
R229
10
Yellow
TD-
4
Async mode by default
R508
R499
R477
R487
R494
R489
R485
R498
R481
R483
9
10
RD-
8
13
14
C224
YA
YK
RCT
6
ENET-7499011121A
5
C229
15
RD+
1V5_ECAT2
C227
Yellow
TD-
4
30
52
11
19
3
GND_TAB1
TCT
GA
GK
0_Ohms
uPD60620A
Manufacturer = Renesas
PART_NUMBER = UPD60620AGK-GAK-AX#YB1
ENET2_TX_CLK_FB
TD+
3
REG_FB
78
7
NC
1
GND
GND_TAB
GND_TAB
C223
0.01uF
Green
ENET-7499011121A
ENET2_RX_D[3..0] (5)
R232
10
2
0.01uF
P0TXP
P0TXN
R230
49.9
YA
YK
R514
DNI
P1TXD0
P1TXD1
P1TXD2
P1TXD3
P1TXERR
P1TXEN
P1TXCLK
R231
49.9
GA
GK
ENET2_TX_EN(5)
P1TXERR(4,19)
23
24
25
26
27
28
29
R218
R234
49.9
1
10uH
L22
72
73
R235
49.9
R233
10
GND_TAB2
D
ENET2_TX_D0
ENET2_TX_D1
ENET2_TX_D2
ENET2_TX_D3
P1TXERR_PHY
ENET2_TX_EN
ENET2_TX_CLK_FB
D32
2
J34
DNI
11
12
ENET2_TX_D0
ENET2_TX_D1
ENET2_TX_D2
ENET2_TX_D3
REGFB
VDD15_1
VDD15_2
VDDAPLL
P0VDDMEDIA
P1VDDMEDIA
32
50
66
40V
9
10
ENET2_TX_D[3..0] (5)
REGLX1
REGLX2
1V5_ECAT
GND_TAB1
ENET1_RX_ERROR (5)
ENET1_RX_DV (5)
ENET1_RX_CLK (5)
ENET1_TX_CLK_FB (5)
VDDIO1
VDDIO2
VDDIO3
P0RXD0
P0RXD1
P0RXD2
P0RXD3
P0RXERR
P0RXDV
P0RXCLK
P0CRS
P0COL
E
R217
GND_TAB2
ENET1_RX_D0
53
ENET1_RX_D1
54
ENET1_RX_D2
55
ENET1_RX_D3
56
ENET1_RX_ERROR
58
ENET1_RX_DV
57
ENET1_RX_CLK
59
60
R496
DNI
R524
4.70K, 1% 21
3.3V
1.5V_REG_HPS
B
11
12
ENET1_RX_D0
ENET1_RX_D1
ENET1_RX_D2
ENET1_RX_D3
REGBVDD1
REGBVDD2
REGAVDD
VCC33ESD
VDDACB
3.3V
16
P0TXD0
P0TXD1
P0TXD2
P0TXD3
P0TXERR
P0TXEN
P0TXCLK
ENET1_RX_D[3..0] (5)
220
3.3V
70
71
77
20
10
7
R480
DNI
43
44
45
46
47
48
49
15
ENET1_TX_EN(5)
P0TXERR(4,19)
ENET1_TX_D0
ENET1_TX_D1
ENET1_TX_D2
ENET1_TX_D3
P0TXERR_PHY
ENET1_TX_EN
ENET1_TX_CLK_FB
NC
E
ENET1_ACT_LED R275
U45
ENET1_TX_D0
ENET1_TX_D1
ENET1_TX_D2
ENET1_TX_D3
16
ENET1_TX_D[3..0] (5)
3.3V
P1TXERR(4,19)
R525
0
ENET2_LINK_LED
R274
220
BOOT-STRAPS
1.5V_REG_HPS
3.3V
PLACE NEAR R217
1V5_ECAT2
Place near uPD60620A PHY
Place near uPD60620A PHY
A
C112
4.7uF
C111
C110
C109
C108
C633
C632
C631
C630
C629
C628
C627
C626
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C614
22uF
25V
C645
C644
C643
C642
C641
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
C615
22uF
25V
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
19
of
1
41
E1
8
7
6
5
4
3
2
1
SDI Cable Driver, Equalizer, SMA Option and SMB
E
75 Ohm Impedance
3.3V_SDI
R91
750
L6
1
E
5.6nH
2
SDI_TXDRV_FILTER_P
75
R80
C81
4.7uF
J14
SDI_TXBNC_P
1
3.3V_SDI
Mini SMB
3.3V_SDI
4.7uF
SDI_TX_N (8) C90
U25
4.7uF
SDI_TXCAP_P
SDI_TXCAP_N
1
2
SDI_TX_RSET
10
4
SDI_TX_SD_HDn (5)
SDI_RSTI (5)
SDI_TX_EN (5,16)
D
0
R95
R96
R79
SDI_SDA
SDI_SCL
R78
3.3V_SDI
49.9
R443
R92
10K
10K
NC5
NC6
R76
16
13
RSTO
FAULT
(5) SDI_FAULT
D
R85
75
R75
10K
3
17
75
R81
L9
SDI Cable Driver, LMH0303SQx
Manufacturer = Texas Instruments
PART_NUMBER = LMH0303SQx
3.3V_SDI
SDI_SCL
SDI_SDA
C86
4.7uF
SDI_TXBNC_N
5.6nH
1
R86
2
SDI_TXDRV_FILTER_N
75
C85
R442
Right
Angle
CAD Note:
Route traces at
secondary side
V1
3.3V_SDI
VEE
CENTERPAD
75
SDI_TXDRV_P
SDI_TXDRV_N
12
11
SDO
SDO
RSTI
ENABLE
SDA
SCL
14
15
49.9
9
VCC
SD/HD
RREF
5
6
7
8
0
I2C_SCL (7,16,26)
I2C_SDA (7,16,26)
SDI
SDI
Cable
Driver
2
3
4
5
SDI_TX_P(8) C80
0
3.3V
3.3V_SDI
L5
0.01uF
120 ohm FB
C119
C75
C76
C104
0.1uF
0.1uF
220nF
220nF
C96
C
22uF
C
75 Ohm Impedance
L11
5.6nH
1
J17
1
2
SDI_IN_P1
SDI_IN_FILTER_P1
Mini SMB
3.3V_SDI
5
4
3
2
Right
Angle
75
R127
CAD Note:
Route traces at
secondary side
B
1.0UF
C120
75
R128
R97
1.0UF
37.4 C103
2
3
7
15
4
12
SDI_RX_CDn
3.3V_SDI
R94
3.3V_SDI
10K
From EPM2210
5
6
AEC
SDI_RX_BYPASS (5,16)
1.0UF
C97
SDI_RX_EN (5,16)
Read-Only (Auto-Mute)
14
8
R126
R93
0
0
3.3V_SDI
R98
A
CAD Note:
Overlap C188 & R286
U31
SDI_EQIN_P1
SDI_EQIN_N1
75
D17
SDI
SDI
BYPASS
CD
SPI_EN
AUTO_SLEEP
VCC1
VCC2
SDO
SDO
MUTE
MUTEref
SDO_P
11
10
SDO_N
AEC+
AECVEE1
VEE2
DAP
B
13
16
C117
C116
4.7UF
(8) SDI_RX_P
4.7UF
(8) SDI_RX_N
CAD Note:
Overlap C189 & R284
1
9
17
SDI Cable Equalizer, LMH0384SQ
Manufacturer = Texas Instruments
PART_NUMBER = LMH0384SQ
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Green_LED
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
E1
20
of
1
41
8
7
6
5
4
3
2
1
QSPI Flash & Reset Circuit
RESET CIRUIT
QSPI FLASH
E
D
E
D
3.3V
3.3V
U5
QSPI_IO0 (6)
QSPI_IO1 (6)
QSPI_IO2 (6)
QSPI_IO3 (6)
15
8
9
1
QSPI_CLK (6)
16
QSPI_SS0 (6)
7
3.3V
3.3V
0.1uF
C241
2
VCC
50ms pulse reset
DQ0 Hardware RESET#
DQ1
RESET
DQ2/VPP/W#
DNU2
DQ3/HOLD#
DNU3
DNU4
C
DNU5
DNU6
S#
DNU7
DNU8
C
R684
2.00K
QSPI_RESETn
3
4
5
6
11
12
13
14
U56
4
QSPI_RESETn (16)
R316
20.0K
3
S7
1
2
PB Switch
PB_COLD_RESETn
MR
GND
RESET
1
2
ADM811-3TARTZ-RL7
COLD_RESETn R315
100K
R314
0
USB_RESET IS ACTIVE HIGH AND IS INVERTED
THROUGH THE MAX II SYSTEM CONTROLLER
10
VSS
VCC
C
DNI
(24) RESET_HPS_UART_N
R319
N25Q512A83GSF40F
Manufacturer = Micron
PART_NUMBER = N25Q512A83GSF40F
0 (18) ENET_HPS_RESETn
R320
TP1
DNI
(4,19) ENET_DUAL_RESETn
R534
HPS_RESETn
HPS_RESETn (6,16)
Input only to CV device cold reset
3.3V
3.3V
B
0.1uF
B
C240
U55
3.3V
4
PLACE NEAR QSPI FLASH
R313
20.0K
3
C259
C258
4.7uF
S8
1
0.1uF
2
PB Switch
PB_WARM_RESETn
VCC
MR
GND
RESET
ADM811-3TARTZ-RL7
1
2
WARM_RESETnR312
100K
R311
4.70K, 1%
Input/output to CV device warm reset
MICTOR_RSTn
A
MICTOR_RSTn (6,12,16)
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Friday, September 12, 2014
2
Rev
(6XX-44184R)
Sheet
21
of
1
41
E1
8
7
6
5
4
3
2
1
USB 2.0 OTG , Micro SD Card
5.0V
USB_5.0V
U1
E
E
C1
5
1uF
USB_EXTVBUS
USB 2.0 OTG
3.3V
32
USB_RESET_PHY
U80
R11
12.0K
8
7
6
5
VBUS
DM
DP
ID
CLKOUT
NXT
DIR
STP
XO
XI
RBIAS
GND
GND
GND_FLAG
RESET
USB_RESET R8
3
10
4
8
7
5
USB_VBUS
USB_DM_N
USB_DP_P
USB_ID
27
28
USB_XO
USB_XI
R5
24MHz
R685
R692
J3
SD_CLK
5
SD_CMD
3
SD_DAT0
SD_DAT1
SD_DAT2
SD_CD_DAT3
7
8
1
2
C260
4.7uF
0.1uF
0.1uF
C251
0.1uF
DNI
R730
100, 1%
4
R730 is leakage path for 3.3V_SD
rail, share footprint with C6
9
10
11
12
6
B
ESD5V3U2U
316K
1
ESD5V3U2U D12
3
A
K1
2
K2
1
K1
2
A
ESD5V3U2U D10
3
A
K2
1
C6
0.1uF
TP8
SD_DAT2 (6)
SD_CD_DAT3 (6)
SD_DAT0 (6)
SD_DAT1 (6)
SD_CMD (6)
SD_CLK
SD_CLK (6)
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
0.1uF
Date:
6
C5
2.2uF
SD_DAT2
SD_CD_DAT3
SD_DAT0
SD_DAT1
SD_CMD
B
7
CAGE
CAGE
CAGE
CAGE
VSS
DAT0
DAT1
DAT2
CD/DAT3
C10
10uF
Micro SD / USB INTERFACE
C250
C248
4.7uF
VDD
CMD
C794
MicroSD_skt
USB_VDDA
C254
CLK
Size
8
30pF
3.3V_SD
R691
C245
K1
2
K2
0.1uF
R17
1M
Micro SD Card
3
D11
USB_VDD
0.1uF
D
1
2
3
4
5
30pF
C12
3 2 1
PLACE NEAR USB3300
0.1uF
X2
2
4
10.0K
5
USB_RESET
USB_CLK
USB_NXT
USB_DIR
USB_STP
USB_DATA[7..0]
R690
(16) USB_RESET
(6) USB_CLK
(6) USB_NXT
(6) USB_DIR
(6) USB_STP
(6) USB_DATA[7..0]
4
3.3V
C252
4.7uF
820,1%
C20
3.3V_SD
C255
4.7uF
J1
USB MICRO-AB
1
2
33
B
C256
C4
USB_CPEN
USB_EXTVBUS
C
10.0K
R722
1K
C793
0.1uF
C249
Current limit is set to 1.1 A
3.3V 3.3V 3.3V 3.3V
U81
FDMC8878
A
1uF
USB_5.0V
USB_RESET_PHY
0
C8
R15
100K
USB3300
Manufacturer = MICROCHIP
PART_NUMBER = USB3300-EZK
R9
10.0K
LTC1157CS8
R721
1.00k
29
15
26
30
25
16
6
CPEN
EXTVBUS
R689
NC1
NC2
GATE1 GATE2
GND
VS
IN1
IN2
REG_EN
10.0K
1
2
3
4
C
9
VDD1.8
VDD1.8
USB_RBIAS
3.3V
QSPI_RESETn (16)
1
6
8
9
3.3V
10.0K
QSPI_RESETn
14
11
12
13
ON
SETI
31
3
50ms pulse reset
USB_CLK
USB_NXT
USB_DIR
USB_STP
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
NC1
NC2
GND
EP
3.3V
1
R16
DNI
24
23
22
21
20
19
18
17
VDDA1.8
3.3V
USB_DATA0
USB_DATA1
USB_DATA2
USB_DATA3
USB_DATA4
USB_DATA5
USB_DATA6
USB_DATA7
FLAG
4
MAX14523AATA+T
PART_NUMBER = MAX14523AATA+T
Manufacturer = Maxim Integrated Products, Inc.
R84
121K
1%
R10
DNI
VDD3.3
VDD3.3
VDD3.3
VDD3.3
D
7
3
USB_VDDA
U2
10.0K
10.0K
10.0K
10.0K
10.0K
10.0K
10.0K
10.0K
2
DNI
USB_VDD
USB INTERFACE
R21
R36
R35
R34
R23
R22
R20
R19
R6
OUT
6
7
8
9
USB_5.0V
IN
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Friday, September 12, 2014
2
Rev
(6XX-44184R)
Sheet
22
of
1
41
E1
8
7
6
5
D34
R555
49.9
R549
49.9
R563
49.9
B1
B2
B4
E
2x16 LCD I2C
HEADER 3X1
R567
49.9
Green_LED
PGM_LED1
R568
49.9
I2C_SCL_DISP
I2C_SDA_DISP
D39
2.5V_REG_HPS
5.0V
Green_LED
PGM_LED2
R569
49.9
D
1
2
3
4
5
6
7
8
9
10
R430
10K
R429
10K
I2C_SCL_DISP
I2C_SDA_DISP
U24
7
8
1
2
VCC
3.3V
R435
DNI
J15
Green_LED
PGM_LED0
D40
HEADER 6X1
I2C ADDRESS: 0x50
Green_LED
5.0V
D41
1
Green_LED
MAX_LOAD
D38
MAX_CONF_DONE
2
Red_LED
MAX_ERROR
E
3
User I/O, RTC
3.3V
D36
4
VL
TRI_STATE
3
6
R434
0
(6,18,27)
I2C_SCL_HPS
5
VL_IO1 (6,18,27)
4
I2C_SDA_HPS
VL_IO2
VCCIO1
VCCIO2
GND
MAX3373
PART_NUMBER = MAX3373EEKA+T
Manufacturer = Maxim Integrated Products, Inc.
D
LCD_HEADER
I2C ADDRESS: 0x40
3.3V
S12
1
S11
1
S9
1
D9 Green_LED
HSMA_PRSNTn
R309
S10
1
R557
I2C_SDA_HPS R12
I2C_SCL_HPS R37
PGM_CONFIG
2
PB Switch
R564
PGM_SEL
2
PB Switch
R565
4.70K, 1%
MAX_RESETn
2
PB Switch
R337
4.70K, 1%
CPU_RESETn
2
PB Switch
R566
0
0
49.9
16
1
4.70K, 1%
15
13
12
11
10
VCC
VBACKUP
SDA
SCL
SQW/INT
NC5
NC6
NC7
NC8
NC9
NC10
GND
NC1
NC2
NC3
NC4
14
2
VBAT
R38
4.70K, 1% 3.3V
4
5
6
7
8
9
BT1
DS1339C
Manufacturer = Maxim
PART_NUMBER = DS1339C-33#
USER_LED_HPS[3..0]
49.9
C
D37 Green_LED
CVP_CONF_DONE
U3
3
0.1uF
1
2.5V_REG_FPGA
C29
2
2.5V_REG_HPS
C
USER_LED_HPS[3..0] (6)
4.70K, 1%
LED INTERFACE
PGM_LED[2:0]
PGM_LED[2:0] (16)
2.5V_REG_HPS
S4
1
S3
1
3.3V
D4
S2
Green_LED
1
USER_LED_HPS0
R282
49.9
S1
1
B
D3
Green_LED
USER_LED_HPS1
R283
49.9
R284
49.9
1
Green_LED
S5
1
D1
Green_LED
USER_LED_HPS3
R285
USER_PB_HPS0
2
PB Switch
R298
4.70K, 1%
USER_PB_HPS1
2
PB Switch
R299
4.70K, 1%
USER_PB_HPS2
2
PB Switch
R300
4.70K, 1%
USER_PB_HPS3
2
PB Switch
R301
4.70K, 1%
(16) MAX_ERROR
(16) MAX_LOAD
(16) MAX_CONF_DONE
HSMA_RX_LED
HSMA_TX_LED
(4,16,17) HSMA_PRSNTn
1.5V_REG_FPGA
S6
D2
USER_LED_HPS2
(4,9) USER_LED_FPGA[3:0]
USER_PB_FPGA0
2
PB Switch
R296
4.70K, 1%
USER_PB_FPGA1
2
PB Switch
R297
4.70K, 1%
PCIE_LED_X1
PCIE_LED_X4
(5) USER_DIPSW_HPS[3:0]
(5) USER_PB_HPS[3:0]
B
DIPSW INTERFACE
(4) USER_DIPSW_FPGA[3:0]
49.9
PUSH BUTTON INTERFACE
2.5V_REG_FPGA
D8
PGM_SEL
PGM_CONFIG
MAX_RESETn
Green_LED
USER_LED_FPGA0
R278
49.9
R279
49.9
PGM_SEL(16)
PGM_CONFIG (16)
MAX_RESETn(16)
3.3V
(4) USER_PB_FPGA[1:0]
D7
Green_LED
SW1
USER_LED_FPGA1
16
15
14
13
12
11
10
9
A
D6
USER_LED_FPGA2
D5
Green_LED
R280
49.9
R281
49.9
Green_LED
USER_LED_FPGA3
1
2
3
4
5
6
7
8
USER_DIPSW_HPS0
USER_DIPSW_HPS1
USER_DIPSW_HPS2
USER_DIPSW_HPS3
USER_DIPSW_FPGA0
USER_DIPSW_FPGA1
USER_DIPSW_FPGA2
USER_DIPSW_FPGA3
R288
R289
R290
R291
R292
R293
R294
R295
4.70K, 1%
4.70K, 1%
4.70K, 1%
4.70K, 1%
4.70K, 1%
4.70K, 1%
4.70K, 1%
4.70K, 1%
(11,16) CPU_RESETn
2.5V_REG_FPGA
Title
Size
B
TDA08H0SB1
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
23
of
1
41
E1
8
7
6
5
4
3
2
1
UART, CAN
UART
E
E
U17
3.3V
D
CON2
RESET_HPS_UART_N (21)
Green_LED
Green_LED
D14
D15
3.3V_USB_UART
R41
220
R350
220
18
UART_TX_LED
UART_RX_LED
22
21
10
11
9
R349
PWR_EN
10.0K
5V_USB_UART
R51
10.0K
NC1
NC2
NC3
NC4
NC5
NC6
CBUS0
CBUS1
CBUS2
CBUS3
CBUS4
OSCI
OSCO
J8
USB MINI-B
5V_USB_UART L2
DM_N
DP_P
15
14
742792780
R39
25
23
5
12
13
29
27
28
C32
C33
39pF
39pF
0
1
2
3
4
5
D
3.3V_USB_UART
VIO_USB_UART
5V_USB_UART
TP2
C42
C36
C51
C54
C37
C34
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
4.7uF
U12
TPD4S012DRYR
PART_NUMBER = TPD4S012DRYR
Manufacturer = Texas Instruments
26
20
17
4
24
33
RESET_HPS_UART_N
R45
RESET
DNI
6
7
881545-2
USBDM
USBDP
VIO_USB_UART
0
R53
4
1
2
3.3V_USB_UART
R52
6
3
1
2
5
J9
3V3OUT
VCCIO
19
16
1
VBUS
ID
D+
DGND
NC
XJ2
VCC
TXD
RXD
RTS
CTS
DTR
DSR
DCD
RI
TEST
GND3
GND2
GND1
AGND
EPAD_GND
30
2
32
8
31
6
7
3
UART_RX (6)
UART_TX(6)
4.70K, 1%
FT232R
Manufacturer = FTDI
PART_NUMBER = FT232RQ-REEL
C
C
3.3V
CAN BUS
C668
C666
0.1uF
2.2uF
J35
3
1
4
CAN_RS
8
VCC
D
R
RS
5
VREF
7
6
CANH
CANL
Place near SN65HVD230
R550
120
CANH_P
CANL_N
2
GND
CAN_VREF
61800925023
R539
DNI
R538
0
B
5
9
4
8
3
7
2
6
1
U50
(6) CAN_0_TX
(6) CAN_0_RX
3.3V
CAN_VREF
SN65HVD230
Manufacturer = Texas Instruments
PART_NUMBER = SN65HVD230Dx
10
11
B
C667
R272
DNI
0.1uF
RS = VCC -> Standby Mode
RS = GND -> High-Speed Mode
RS = Resistor to GND -> Slope Control
A
Title
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
24
of
1
41
E1
8
7
6
5
4
3
2
On-Board USB Blaster II
1
FPGA USB INTERFACE
USB_B2_DATA[7:0]
FX2_SDA
R531
USB_ADDR[1:0]
3.3V
VBUS_5V
FX2_D_N
FX2_D_P
R265
1
2
3
4
5
C216
0.1uF
100K
FX2_RESETn
R216
GND
2
VCC
RESET
MR
4
3
ADM811-3TARTZ-RL7
U53
3
1M
R277
GND
D+
D-
1
2
3.3V
TPD2EUSB30
Manufacturer = Texas Instruments
PART_NUMBER = TPD2EUSB30DRxx
4.7nF
U51
D1
D2
G1
A5
B5
C5
E7
E8
C239
D
E1
E2
4
Y5
3
2
1
USB_B2_CLK
24M_XTALIN
24M_XTALOUT
24.00MHz
C233
C234
12pF
12pF
G2
C1
C2
G8
G6
F8
F7
F6
C8
C7
C6
FX2_PA1
FX2_PA2
FX2_PA3
FX2_PA4
FX2_PA5
FX2_PA6
FX2_PA7
C
H2
F1
F2
H1
A4
B4
C4
D7
D8
VBUS_5V R561
10.0K
3.3V
AVCC
AVCC
RESET
SCL
SDA
VCC
VCC
VCC
VCC
VCC
VCC
WAKEUP
CTL0
CTL1
CTL2
DMINUS
DPLUS
RDY0
RDY1
IFCLK
XTALIN
XTALOUT
CLKOUT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RESERVED
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
AGND
AGND
GND
GND
GND
GND
GND
GND
B8
F3
G3
FX2_RESETn
FX2_SCL R553
FX2_SDA R551
B7
FX2_WAKEUP
H7
G7
H8
FX2_FLAGA
FX2_FLAGB
FX2_FLAGC
A1
B1
FX2_SLRDn
FX2_SLWRn
2.00K
2.00K
R562
C681
20.0K
0.1uF
IO_B1_B1
IO_B1_C1
IO_B1_C2
IO_B1_D1
IO_B1_D2
IO_B1_D3
IO_B1_E3
IO_B1_F1
IO_B1_F2
IO_B1_F3
IO_B1_G1
IO_B1_G2
IO_B1_G3
IO_B1_H1
IO_B1_H4
IO_B1_H7
JTAG_TX
D30
MAX_SDA
FX2_PB0
FX2_PB1
FX2_PB2
FX2_PB3
FX2_PB4
FX2_PB5
FX2_PB6
FX2_PB7
A8
A7
B6
A6
B3
A3
C3
A2
FX2_PD0
FX2_PD1
FX2_PD2
FX2_PD3
FX2_PD4
FX2_PD5
FX2_PD6
FX2_PD7
C_USB_MAX_TDI
C_USB_MAX_TCK
C_USB_MAX_TMS
C_USB_MAX_TDO
J7
H2
H3
J1
J2
IO1/DEV_OE
Green_LED
D31
Green_LED
D29
SC_RX
56.2
RESn_JTAG_TX
R517
56.2
RESn_SC_RX
R519
56.2
SC_TX
R520
56.2
M570_PCIE_JTAG_EN
IO1/GCLK0p
IO1/GCLK1p
IO2/GCLK2p
IO2/GCLK3p
K9
C675
C672
C682
C669
C671
C676
C680
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
USB_CFG[11:0]
USB_CFG[11:0] (16)
EXTRA_SIG[2:0]
EXTRA_SIG[2:0] (16)
D
USB_DISABLEn
M570_CLOCK
FACTORY_STATUS
FACTORY_REQUEST
C_USB_MAX_TCK
C_USB_MAX_TDI
C_USB_MAX_TDO
C_USB_MAX_TMS
FX2_RESETn
USB_B2_CLK
E2
FX2_PB7
E1
USB_CFG7
F8
M570_CLOCK
E10
USB_DISABLEn (12)
M570_CLOCK (16)
FACTORY_STATUS (16)
FACTORY_REQUEST (16)
R560
R558
R537
R559
FX2_PD0
FX2_PD2
FX2_PD3
FX2_PD1
0
0
0
0
JTAG INTERFACE
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
JTAG_TCK (12)
JTAG_TMS(12)
JTAG_BLASTER_TDI (12)
JTAG_BLASTER_TDO (12)
C
JTAG_TX
JTAG_RX
FACTORY_REQUEST
USB_CFG5
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
FACTORY_STATUS
SC_RX
SC_TX
USB_CFG4
EXTRA_SIG1
USB_CFG6
USB_B2_DATA0
USB_B2_DATA1
USB_B2_DATA2
USB_B2_DATA3
USB_B2_DATA4
A1
A2
A3
A4
A7
B8
D10
D9
A9
A10
B2
B3
B4
B5
B9
C9
C8
B7
C7
IO_B2_A1
IO_B2_A2
IO_B2_A3
IO_B2_A4
IO_B2_A7
IO_B2_B8
IO_B2_D10
IO_B2_D9
IO_B2_A9
IO_B2_A10
IO_B2_B2
IO_B2_B3
IO_B2_B4
IO_B2_B5
IO_B2_B9
IO_B2_C9
IO_B2_C8
IO_B2_B7
IO_B2_C7
IO_B2_C3
IO_B2_C4
IO_B2_A6
IO_B2_F10
IO_B2_F9
IO_B2_B10
IO_B2_E8
IO_B2_C10
IO_B2_D8
IO_B2_B6
IO_B2_E9
IO_B2_A8
IO_B2_A5
IO_B2_G8
IO_B2_G9
IO_B2_G10
IO_B2_H9
IO_B2_H10
IO_B2_J10
USB_CFG3
C3
M570_PCIE_JTAG_EN
C4
USB_B2_DATA7
A6
USB_B2_DATA5
F10
USB_B2_DATA6
F9
B10
RST
USB_CFG8
E8
C10
TRST
USB_FULL
D8
USB_EMPTY
B6
USB_CFG11
E9
USB_SCL
A8
USB_SDA
A5
EXTRA_SIG2
G8
USB_CFG10
G9
USB_CFG0
G10
V39
USB_CFG1
V43
H9
USB_CFG2
H10
V42
USB_CFG9
J10
EPM570GF100
PART_NUMBER = EPM570GF100C5N
Manufacturer = Altera Corporation
R544
R542
R545
R543
1.00k
1.00k
1.00k
1.00k
USB_SCL
USB_SDA
USB_FULL
USB_EMPTY
R541
1.00k
FACTORY_REQUEST
C_JTAG_TCK
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TDO
3.3V
0
0
0
0
1V8
U47A
R529
R530
R535
R536
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
DNI
JTAG_BLASTER_TDI
MAX II
POWER
C5
E6
F5
H5
D5
D7
E5
F6
G5
G7
GNDINT
GNDINT
GNDINT
GNDINT
VCCINT
VCCINT
VCCINT
VCCINT
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
C6
E7
F4
H6
3.3V
E4
G4
G6
1.5V_REG_HPS
D4
D6
F7
EPM570GF100
PART_NUMBER = EPM570GF100C5N
Manufacturer = Altera Corporation
PLACE NEAR MAX II (U14)
3.3V
1.5V_REG_HPS
(16) TRST
(16) RST
R321
1.00K C_USB_MAX_TCK 1
C_USB_MAX_TDO 3
1.00K C_USB_MAX_TMS 5
7
C_USB_MAX_TDI 9
1
3
5
7
9
B
1V8
C647
C648
C653
C655
C654
C661
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2.5V_REG_HPS
2
4
6
8
10
2
4
6
8
10
R211
Size
B
Date:
6
5
4
3
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
DNI
7
M570_PCIE_JTAG_EN (16)
3.3V
Green_LED
8
E
MAX V USB INTERFACE
MAX II
BANK 2
C677
R286
RESn_SC_TX
USB_FULL (4)
USB_EMPTY (4)
USB_SCL (4)
USB_SDA (4)
USB_B2_CLK (4,16)
USB_RESETn (4)
USB_OEn (4)
USB_RDn (4)
USB_WRn (4)
U47C
J38
Green_LED
D28
A
IO1/DEV_CLRn
TDI
TCK
TMS
TDO
1.5V_REG_HPS
R518
FX2_SLWRn
FX2_SLRDn
FX2_PD7
FX2_PD5
FX2_PA5
C_JTAG_TDO
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TCK
EPM570GF100
PART_NUMBER = EPM570GF100C5N
Manufacturer = Altera Corporation
PLACE NEAR CY7C68013A
RESn_JTAG_RX
FX2_PB1
FX2_PB3
FX2_SCL
FX2_PD6
FX2_PD4
H8
J3
J4
J5
J6
J8
J9
K1
K2
K3
K4
K5
K6
K7
K8
K10
MAX II
CONFIGURATION
1V8
JTAG_RX
IO_B1_H8
IO_B1_J3
IO_B1_J4
IO_B1_J5
IO_B1_J6
IO_B1_J8
IO_B1_J9
IO_B1_K1
IO_B1_K2
IO_B1_K3
IO_B1_K4
IO_B1_K5
IO_B1_K6
IO_B1_K7
IO_B1_K8
IO_B1_K10
U47D
3.3V
B
B1
C1
C2
D1
D2
D3
E3
F1
F2
F3
G1
G2
G3
H1
H4
H7
USB_FULL
USB_EMPTY
USB_SCL
USB_SDA
USB_B2_CLK
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
EPM570GF100
PART_NUMBER = EPM570GF100C5N
Manufacturer = Altera Corporation
CY7C68013A_VFBGA
Manufacturer = Cypress
PART_NUMBER = CY7C68013A-56BAXC
FX2_WAKEUP
FX2_PA2
FX2_FLAGC
FX2_PA7
FX2_FLAGA
FX2_PA3
FX2_PA4
EXTRA_SIG0
FX2_PB4
FX2_PA6
FX2_PB2
FX2_FLAGB
FX2_PB0
FX2_PA1
FX2_PB5
USB_DISABLEn
FX2_PB6
MAX II
BANK 1
B2
H3
F4
H4
G4
H5
G5
F5
H6
USB_ADDR[1:0]
U47B
U48
1
DNI
7
6
E
USB_B2_DATA[7:0] (4)
MAX_SDA
0
J37
USB MINI-B
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Monday, September 01, 2014
2
Rev
(6XX-44184R)
Sheet
25
of
1
41
E1
5
4
V48
1.1V_VCC_N
1
RSNS SNS
1.1V_VCC
1
RSNS SNS
1.1V_REG_VCC
1
D
RSNS SNS
1
RSNS SNS
1
2.5V_FPGA_P
1
RSNS SNS
TSENSE_FAN_CNTL
D
22_23_2021
Q1
1.5V_REG_FPGA
(16) OVERTEMP
2
FDV305N
B3
2.5V_FPGA
2
FAN_2pin_Conn
SENSE_PAD
V40
RSNS SNS
1
2
1.5V_FPGA
2
SENSE_PAD
V41
2.5V_FPGA_N
12V
J21
SENSE_PAD
V44
1.5V_FPGA_P
1
2
SENSE_PAD
V45
1.5V_FPGA_N
2
FPGA Power Monitor
2
SENSE_PAD
V49
1.1V_VCC_P
3
2.5V_REG_FPGA
2
SENSE_PAD
3.3V_PM_FPGA
R417
R416
10K
10K
SCL_PM
SDA_PM
SCL_PM
SDA_PM
(7,16,20)
0
I2C_SCL
0(7,16,20) I2C_SDA
12V
C
R88
R87
1K
1K
C92
0.1uF C93
0.1uF
R83
R82
1K
1K
C87
0.1uF C88
0.1uF
R77
R73
1K
1K
C77
0.1uF C82
0.1uF
R70
R69
1K
1K
C72
0.1uF C73
0.1uF
R68
R67
1K
1K
C70
R422
R421
C
U26
R66
R65
1K
1K
14
C68
0.1uF C71
0.1uF
0.1uF C69
0.1uF
2.5V_FPGA_V_P
2.5V_FPGA_V_N
2.5V_FPGA_I_P
2.5V_FPGA_I_N
1.5V_FPGA_V_P
1.5V_FPGA_V_N
1.5V_FPGA_I_P
1.5V_FPGA_I_N
1.1V_VCC_V_P
1.1V_VCC_V_N
1.1V_VCC_I_P
1.1V_VCC_I_N
B
36
37
42
43
46
47
48
49
52
53
62
63
64
1
2
3
SCL_PM
SDA_PM
PM2_ASEL0
PM2_ASEL1
PM_CNTL0
PM_CNTL1
PM_RSTn
28
27
32
33
30
31
22
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
23
24
25
26
PM_SHARE_CLK
21
19
65
3.3V_PM_FPGA
VIN_SNS
VSENSEP0
VSENSEM0
VSENSEP1
VSENSEM1
VSENSEP2
VSENSEM2
VSENSEP3
VSENSEM3
VSENSEP4
VSENSEM4
VSENSEP5
VSENSEM5
VSENSEP6
VSENSEM6
VSENSEP7
VSENSEM7
R104
10K
R108
10K
REFP
REFM
NC
VDACP0
VDACM0
VDACP1
VDACM1
VDACP2
VDACM2
VDACP3
VDACM3
VDACP4
VDACM4
VDACP5
VDACM5
VDACP6
VDACM6
VDACP7
VDACM7
SCL
SDA
ASEL0
ASEL1
CONTROL0
CONTROL1
WDI/RESET
VOUT_EN0
VOUT_EN1
VOUT_EN2
VOUT_EN3
VOUT_EN4
VOUT_EN5
VOUT_EN6
VOUT_EN7
FAULTB00
FAULTB01
FAULTB10
FAULTB11
SHARE_CLK
ALERTB
PWRGD
VPWR
VDD25
WP
E-PAD
GND pad
R107 R106 R105
10K
10K
10K
VIN_EN
LTC2978
VDD33_OUT
VDD33_IN
Manufacturer = Linear Technology
PART_NUMBER = LTC2978CUP#PBF
A
2.5V_FPGA_VDACP0
1.5V_FPGA_VDACP2
1.1V_FPGA_VDACP4
12
C481
0.1uf
34
35
13
39
38
40
41
44
45
50
51
55
54
56
57
59
58
60
61
2.5V_FPGA_VDACP0
SCL_PM
SDA_PM
1.5V_FPGA_VDACP2
PM_SHARE_CLK
PM_CNTL0
PM_CNTL1
PM_RSTn
4
5
6
7
8
9
10
11
2.5V_FPGA_RUN
29
20
15
18
2.5V_FPGA_VDACP0 (31)
1.5V_FPGA_VDACP2 (30)
1.1V_FPGA_VDACP4 (29)
SCL_PM (27)
SDA_PM (27)
PM_SHARE_CLK (27)
PM_CNTL0 (27,6)
PM_CNTL1 (27)
PM_RSTn(27)
1.1V_FPGA_VDACP4
PM_ALERTB
PM_PWRGD
PM_ALERTB(27)
PM_PWRGD (27)
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
B
2.5V_FPGA_RUN (31)
1.5V_FPGA_RUN
1.5V_FPGA_RUN (30)
1.1V_FPGA_RUN
1.1V_FPGA_RUN (29)
PM_ALERTB
PM_PWRGD
3.3V_PM_FPGA
16
17
C91
C98
C99
0.1uf
0.1uf
0.1uf
A
PM2_ASEL0
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
PM2_ASEL0
PM2_ASEL1
LTC2978
Address Select
PWRMON2 = 7'h5E
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Cyclone V SoC FPGA Development Kit Board
Size
B
Date:
5
4
3
2
Document Number 150-0321003-E1
Tuesday, September 02, 2014
Rev
E1
(6XX-44184R)
Sheet
1
26
of
41
5
4
V3
3.3V_HPS_N
1
RSNS SNS
1
2.5V_HPS_N
1
RSNS SNS
RSNS SNS
3.3V_REG_HPS
1
1.5V_HPS_N
1
1.5V_HPS_P
1
RSNS SNS
1
RSNS SNS
1
RSNS SNS
2
4
6
8
10
12
2
4
6
8
10
12
D
SDA_PM
SCL_PM
PM_ALERTB
2x6HDR
1.5V_HPS
1.5V_REG_HPS
2
3.3V_PM_HPS
1.1V_HPS
2
SENSE_PAD
V14
1.1V_HPS_P
1
3
5
7
9
11
2
SENSE_PAD
V13
1.1V_HPS_N
PM_CNTL1
2.5V_REG_HPS
SENSE_PAD
V6
RSNS SNS
J24
1
3
5
7
9
11
2
SENSE_PAD
V7
RSNS SNS
I2C Interface
2.5V_HPS
2
SENSE_PAD
V22
2.5V_HPS_P
1
2
SENSE_PAD
V21
D
2
HPS Power Monitor
3.3V_HPS
2
SENSE_PAD
V2
3.3V_HPS_P
3
1.1V_REG_HPS
R170 R171 R165 R162
10K
10K
10K
10K
2
R163 R164 R166 R167 R168 R169 R172 R173 R729
10K
10K
10K
10K
10K
10K
10K
10K
10K
SENSE_PAD
C
C
12V
B
R155
R154
1K
1K
C158 0.1uF C159 0.1uF
R150
R149
1K
1K
C143 0.1uF C144 0.1uF
R141
R131
1K
1K
C132 0.1uF C138 0.1uF
R119
R118
1K
1K
C127 0.1uF C128 0.1uF
R117
R116
1K
1K
C125 0.1uF C126 0.1uF
R115
R114
1K
1K
C123 0.1uF C124 0.1uF
R113
R112
1K
1K
C121 0.1uF C122 0.1uF
R139
R140
1K
1K
C137 0.1uF C136 0.1uF
14
1.1V_HPS_V_P
1.1V_HPS_V_N
1.1V_HPS_I_P
1.1V_HPS_I_N
1.5V_HPS_V_P
1.5V_HPS_V_N
1.5V_HPS_I_P
1.5V_HPS_I_N
2.5V_HPS_V_P
2.5V_HPS_V_N
2.5V_HPS_I_P
2.5V_HPS_I_N
3.3V_HPS_V_P
3.3V_HPS_V_N
3.3V_HPS_I_P
3.3V_HPS_I_N
PM_CNTL0
these GND connections to
each VSENSEMx pin
needs to be placed close
to a GND pin of the BGA!
SCL_PM
SDA_PM
PM1_ASEL0
R728 DNI PM1_ASEL1
PM_CNTL0_0
PM_CNTL1
PM_RSTn
0402
36
37
42
43
46
47
48
49
52
53
62
63
64
1
2
3
28
27
32
33
30
31
22
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
23
24
25
26
PM_SHARE_CLK
21
19
65
VIN_SNS
A
VIN_EN
LTC2978
VSENSEP0
VSENSEM0
VSENSEP1
VSENSEM1
VSENSEP2
VSENSEM2
VSENSEP3
VSENSEM3
VSENSEP4
VSENSEM4
VSENSEP5
VSENSEM5
VSENSEP6
VSENSEM6
VSENSEP7
VSENSEM7
REFP
REFM
NC
VDACP0
VDACM0
VDACP1
VDACM1
VDACP2
VDACM2
VDACP3
VDACM3
VDACP4
VDACM4
VDACP5
VDACM5
VDACP6
VDACM6
VDACP7
VDACM7
SCL
SDA
ASEL0
ASEL1
CONTROL0
CONTROL1
WDI/RESET
VOUT_EN0
VOUT_EN1
VOUT_EN2
VOUT_EN3
VOUT_EN4
VOUT_EN5
VOUT_EN6
VOUT_EN7
FAULTB00
FAULTB01
FAULTB10
FAULTB11
SHARE_CLK
ALERTB
PWRGD
VPWR
VDD25
WP
E-PAD
GND pad
VDD33_OUT
VDD33_IN
12
SCL_PM (26)
R474
0
39
38
40
41
44
45
50
51
55
54
56
57
59
58
60
61
1.1V_HPS_VDACP0
4
5
6
7
8
9
10
11
EN_1.1V_HPS
29
20
15
18
PM_ALERTB
PM_PWRGD
1.5V_HPS_VDACP2
PM_SHARE_CLK
PM_ALERTB
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
PM_CNTL0
PM_CNTL1
PM_CNTL0_0
2.5_HPS_VDACP4
PM_SHARE_CLK
PM_CNTL0
PM_CNTL1
PM_RSTn
3.3_HPS_VDACP6
EN_1.5V_HPS
EN_3.3V_HPS
3.3V_PM_HPS
16
17
PM_ALERTB
PM_PWRGD
PM_ALERTB(26)
PM_PWRGD (26)
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
EN_1.1V_HPS
EN_1.5V_HPS
EN_2.5V_HPS
EN_3.3V_HPS
EN_1.1V_HPS
EN_1.5V_HPS
EN_2.5V_HPS
EN_3.3V_HPS
1.1V_HPS_VDACP0
1.5V_HPS_VDACP2
2.5_HPS_VDACP4
3.3_HPS_VDACP6
1.1V_HPS_VDACP0 (35)
1.5V_HPS_VDACP2 (33)
2.5_HPS_VDACP4 (32)
3.3_HPS_VDACP6 (34)
B
(35)
(33)
(32)
(34)
A
C156 C157 C167
0.1uf
0.1uf
0.1uf
Altera Corporation, 101 Innovation Drive, San Jose, CA
SDA_PM (26)
Title
PM1_ASEL0
PM1_ASEL1
(6,18,23) I2C_SDA_HPS
Cyclone V SoC FPGA Development Kit Board
LTC2978
Address Select
PWRMON1 = 7'h5C
Size
B
Date:
5
PM_SHARE_CLK (26)
PM_CNTL0 (26,6)
PM_CNTL1 (26)
PM_RSTn(26)
EN_2.5V_HPS
SDA_PM
R475
0
(6,18,23) I2C_SCL_HPS
C580
0.1uf
34
35
13
PART_NUMBER = LTC2978CUP#011K-1PBF
Manufacturer = Linear Technology
SCL_PM
SDA_PM
SCL_PM
PM_RSTn
PM_PWRGD
U34
4
3
2
Document Number 150-0321003-E1
Tuesday, August 05, 2014
Rev
E1
(6XX-44184R)
Sheet
1
27
of
41
8
7
6
5
1
DC_INPUT
J22
CONN JACK PWR
2
1
3
E
2
RSNS SNS
SENSE_PAD V53
1
RSNS SNS
U44
FDMC8878
1
2
3
R705
332K
1
2
3
4
5
6
7
8
GATE
IN
1
6
4
7
OUT
VDD
GND
EP_GND
NC
R696
20.0K
LTC4357
47uF
35V
R703
4
R700 R698
U76
R704
140K
16
15
14
13
12
11
10
9
NC
SENSE+
VDD
SENSEUV
ISET
OV
IMON
TIMER
FB
INTVCC
/FLT
GND
PG
SOURCE GATE
10K
10
2
1
12V_ATX only:
SW5 = ON, 12V_SHDNn = LOW, 3.3V_SHDNn = HIGH;
12V_SHDNn_1 = 1.5V which is same with U78's UV
SW5 = OFF, 12V_SHDNn = 3.3V_SHDNn = LOW;
12V_SHDNn_1 = 0V which is less than U78's UV
DC_IN
5.0V
E
C196
5
4
D27
1
2
3
U77
FDMC8878
5
CSNL1206 R695 0.001
SENSE_PAD
U60
5
3
DC_INPUT only:
SW5 = ON, 12V_SHDNn = 3.3V_SHDNn = HIGH;
12V_SHDNn_1 = 2.38V which is larger than U78's UV
SW5 = OFF, 12V_SHDNn = 3.3V_SHDNn = LOW;
12V_SHDNn_1 = 0V which is less than U78's UV
There are totally 2x22uF+2x47uF buck cpas on DC_IN rail,
the value of C788 need to be set based on this.
2
C175
19V
DC Input
3
2
4
Power 1 - DC Input & 12V, 3.3V Output
V54
47uF
35V
C176
22uF
25V
Don't support both DC_INPUT and 12V_ATX case
C197
22uF
25V
SW5
SW SLIDE-4P2T
DC_INPUT
100K
150K
R267
20.0K
R548
1.00k
DC_INPUT
R268
12V_SHDNn
12V_ATX
R261 1M
R702
20.0K
LTC4218CGN
7
1
R270
8
9
2
3
10
4
3.3V_SHDNn
12V_ATX
R264
12V_REG
R726
11
12
5
6
100K
140K
100K
POWER LED
D35
BLUE LED
12V_SHDNn_1
R269
20.0K
12V_OR
R178
20.0K
There are totally 11x22uF buck cpas on 12V rail,
the value of C791 need to be set based on this.
12V_SHDNn
12V_OR
1
1
2
3
12V_ATX
2
V56
SENSE_PAD
RSNS SNS
V55
SENSE_PAD
R708 0.001
12V
C179
R179
20.0K
5
1000pF
1000pF
1
2
3
U79
FDMC8878
5
4
R180
169.0K
4
3
2
5
GATE
IN
1
6
4
7
OUT
VDD
GND
EP_GND
NC
LTC4357
LTC4218CDHC-12 1
2
12V_SHDNn_1
3
4
5
6
7
8
NC
SENSE+
VDD
SENSEUV
ISET
OV
IMON
TIMER
FB
INTVCC
/FLT
GND
PG
SOURCE GATE
17
Q8
FDMC8878
1
2
3
12V_REG
C185
C186
22pF
82pF
R707 10K
NC2
U62
5
16
15
14
13
12
11
10
9
R709
10
35
34
33
32
C194
BG1
VFB1
RUN2
ITEMP2
ILIM2
ITH2
TK/SS2
SENSE1+
SENSE1PGOOD1
5
1
2
3
31
RJK0301DPB
4
27
3
39
40
3.3V
1
1.5uH
Q2
V9
drain-tab
2
1
SNS RSNS
SENSE_PAD
LTC3855_S1P
LTC3855_S1N
R177
3.09K
R470
4.02K
C174
16
V8
C540
C564
100uF
6.3v
C192
100pF
FREQ
MODE/PLLIN
PHSASMD
CLKOUT
C
SENSE_PAD
R205 DIFFOUT
11.5K
CMDSH-3
D26
DC_IN
RJK0305DPB
SGND1
SGND2
PGND1
PGND2
NC
TG2
BOOST2
SW2
gnd-pad
R198
57.6K
BG2
VFB2
C180
Q4
21
C195 0.1uF
4
L23
2
19
RJK0301DPB
V46
4
5
VFB2
2
SNS RSNS
1
SENSE_PAD
52.3K
3.3V
DIFFOUT 12
10
11
SENSE2+
SENSE2-
DIFFOUT
DIFFP
DIFFN
PGOOD2
8
9
LTC3855_S2P
LTC3855_S2N
R199
C193
17 PG_12V
LTC3855EUJ
Manufacturer = Linear Technology
Manufacturer Part Num = LTC3855EUJ#PBF
U78
12V_REG
1
0.68uH
Q5
drain-tab
23
R193
2.55K
C210
22uF
25V
Q6
drain-tabRJK0305DPB
4
20
R192
22pF
330uF
10V
0.1uF
drain-tab
4
41
28
22
18
CSNL1206
B
13
36
15
6
7
SW1
RUN1
ITEMP1
ILIM1
ITH1
TK/SS1
2
INTVCC_1
1
RSNS SNS
2
C
38
37
14
2
1
29
2
3.3V_SHDNn
LTC4357
Q7
FDMC8878
BOOST1
4.7uF
L14
C181 0.1uF
RSNS SNS
NC
1
6
4
7
4
30
1
OUT
VDD
GND
EP_GND
TG1
0.1uF
3.92K
DNI
R200
R256
V47 215.0K
2
5
ATX-POWER_4P
GATE
IN
VIN
INTVCC
EXTVCC
RSNS SNS
3
2
4
C187
26
25
24
1
+12V
U59
R727
drain-tab
DC_IN
INTVCC_1
DNI
C166
22uF
25V
Q3
5
+12V
COM
RJK0305DPB
D
DC_INPUT
1
2
3
COM
3
D24
CMDSH-3
U43
R701
20.0K
5
2
3300pF
4
J20
1
0.1uF
C786
0.1uF
5
R697
20.0K
C788
1
2
3
5
C787
R724 140K
1
2
3
12V_ATX
INTVCC_1
5
1
2
3
R725
20.0K
DC_IN
1
2
3
MMBD1205
R699
1K
U41
FDMC8878
D
C664
C665
C663
68uF
25V
68uF
25V
68uF
25V
B
VFB2
R257
11.3K
SENSE_PAD
R206
100K
C789
3.3V
0.1uF
C790
4
U63
3
2
A
5
GATE
IN
NC
OUT
VDD
GND
EP_GND
1
6
4
7
R710
1K
R706
20.0K
0.1uF
R723
1.00k
Title
LTC4357
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
C791
0.01uF
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
28
of
1
41
E1
8
7
6
5
4
3
2
Power 2
1
1.1V_VCC
1.1V_VCCEL
L10
3A, 30 Ohm FB
E
E
1.1V_VCC
1.1V_REG_VCC
1.1V_REG_VCC
3.3V
R648
R589
10K
0402
0
0402
0402
2
1
R711
DNI 0402 1.1V_VCC_AVINO
R712
0
5
QFN-92
D
R678
DNI
1%
0402
DNI
IN-
4
12V
VOUT
V+
R681
0402
5
365K
C782
DNI
0402
1%
C
12V
R679
DNI
0402
0402
1
U74
CATHODE
RCLX
B
3
ANODE
46.4K
C778
1uF
0402
V50
R590
0402
1
DNI
R588
0402
2.26K 0402
DNI
IN+
(26) 1.1V_FPGA_RUN
R713
2
SENSE_PAD
AD8638ARJZ-REEL7
Analog Devices
AD8638ARJZ_SOT235
IN-
U75
DNI
Manufacturer = STmicro
PART_NUMBER = TS391ILT
TS391ILT_SOT23
12V
PART_NUMBER = EN23F2QI
Manufacturer = Enpirion
22.0K
200K
47nF
0402R662
C694
0402
R663
0402
12V
U73
3
RCLX
RSNS SNS
R676
DNI
0402
R677
DNI
1%
0402
R680
DNI
1%
0402
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
100K
R587
1.1V_VCC_AVINO
C
R675
DNI
0402
C781
IN+
1.1V_VCC_AVINO
C776
0.1uF
0402
R661
4.75K
C777
0.47uF
0402
0603
1uF C775
0402
1
SENSE_PAD
2
D
1.1V_VCC
V52
2
3
C769
22uF
1206
VCC-
C692
22uF
1206
1.1V_REG_VCC
V51
1
RSNS SNS
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0.001
4
C768
22uF
1206
NC24
NC23
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
R461
CSNL1206
C774
100uF
1206
1
C792
22uF
1206
PGND
PVIN17
PVIN16
PVIN15
PVIN14
PVIN13
PVIN12
PVIN11
PVIN10
PVIN9
PVIN8
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
AVINO
PG
BTMP
VDDB
BGND
S_IN
S_OUT
C706
47uF
1206
OUT
WSL0805
93
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
C697
47uF
1206
VCC+
0.003
PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
NC28
NC27
NC26
NC25
VOUT11
VOUT10
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
12V_VCC1V1
R667
U72
EN23F2QI
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TP18
POK
ENABLE
AVIN
AGND
M/S
VFB
EAIN
SS
RCLX
FQADJ
NC29
EN_PB
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
TP16
12V
C696
47uF
1206
1.1V_VCC
RSNS SNS
2
1.1V_REG_VCC
15K
TP14
R664
0402
R666
0201
1.21M
0
27pF C779
0402
REF
DNI
PART_NUMBER = LM431SCCMFX
Manufacturer = Fairchild Semiconductor
LM431S_SOT23
SENSE_PAD
200K
2
B
Place this SENSE PAD close to SOC
R665
0603
R590 and R665 resistors should be close to each other
1.1V_FPGA_VDACP4 (26)
R183
0402
Test_Pad_SMT
R595
240K
0402
A
Title
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Monday, September 01, 2014
2
Rev
(6XX-44184R)
Sheet
29
of
1
41
E1
8
7
6
5
4
3
2
1
Power 3 - 1.5V FPGA
E
E
12V
C707 22nF
0402
3.3V
R598
10K
0402
560
R600
4.75K
0402
1V5_FPGA_AVINO
C709 .22uF
0402
C708 1uF
0402
R507
0402
1.5V_REG_FPGA
1.5V_REG_FPGA R602
0603
0
0
R714
R603
0402
C714 27pF
0402
732K
0402
(26) 1.5V_FPGA_VDACP2
C712 1uF 1V5_FPGA_AVINO
0402
4.02K
147K
C713 47nF
0402
R604
20.0K
R506
R605
33.2K
0402
R607
147K
0402
R606
3K
0402
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
S_OUT
S_IN
BGND
VDDB
BTMP
PG
AVINO
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
PGNDTHRML
1.5V_FPGA_RUN
TP24
R668
POK
ENABLE
AVIN
AGND
AGND
VFB
EAOUT
SS
RCLX
FADJ
NC59
AGND
NC(SW)61
NC(SW)62
NC(SW)63
NC64
NC65
NC66
NC67
NC68
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
(26) 1.5V_FPGA_RUN
D
12V_1V5FPGA TP22
C711
22uF
1206
48
47
46
45
44
43
42
41
40
39
38
37
36
35
69
R601
100K
0402
R599
0402
PGND
PGND
PGND
PGND
PGND
PGND
NC(SW)28
NC(SW)27
NC26
NC25
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
NC15
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
12V
0.003
WSL0805
D
1.5V_REG_FPGA
R214
C715
47uF
0805
C716
47uF
0805
1.5V_FPGA
0.003
WSL2010
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C
U66 EN2342QI
PART_NUMBER = EN2342QI
Manufacturer = Enpirion
TP13
QFN-68
B
B
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
E1
30
of
1
41
8
7
6
5
4
3
2
1
Power 3 - 2.5V FPGA
2.5V_FPGA_FILT
2.5V_FPGA
L21
E
E
3A, 30 Ohm FB
Design Note:
DCR = 40m ohms
12V
C717 22nF
0402
3.3V
R657
10K
0402
560
R609
4.75K
0402
2V5_FPGA_AVINO
C718 1uF
0402
2.5V_FPGA_RUN
3.3V logic signal
2.5V_REG_FPGA
2.5V_REG_FPGA
R611
0603
0402
0
0
R715
R612
0402
4.02K
115K
C724 47pF R613
0402
0402
340K
(26) 2.5V_FPGA_VDACP0
C723 1uF 2V5_FPGA_AVINO
0402
C722 47nF
0402
18K
R521
0402
R616
48.7K
0402
R614
36.5K
0402
R615
10K
0402
12V
C720
22uF
1206
POK
ENABLE
AVIN
AGND
AGND
VFB
EAOUT
SS
RCLX
FADJ
NC59
AGND
NC(SW)61
NC(SW)62
NC(SW)63
NC64
NC65
NC66
NC67
NC68
PGND
PGND
PGND
PGND
PGND
PGND
NC(SW)28
NC(SW)27
NC26
NC25
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
NC15
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0.003
WSL0805
D
2.5V_REG_FPGA
R208
C725
47uF
0805
C726
47uF
0805
2.5V_FPGA
0.001
WSL2010
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
S_OUT
S_IN
BGND
VDDB
BTMP
PG
AVINO
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
PGNDTHRML
(26) 2.5V_FPGA_RUN
R532
TP25
R669
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
D
TP20
12V_2V5FPGA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
69
R610
100K
0402
C719 .22uF
0402
R608
0402
U67 EN2342QI
PART_NUMBER = EN2342QI
Manufacturer = Enpirion
TP15
QFN-68
B
B
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
E1
31
of
1
41
8
7
6
5
4
3
2
1
Power 3 - 2.5V HPS
2.5V_HPS_FILT
2.5V_HPS
E
E
L17
3A, 30 Ohm FB
Design Note:
DCR = 40m ohms
C727 22nF
0402
12V
R493
0402
10K
C729 .22uF
0402
R617
0402
560
R618
4.75K
0402
2V5_HPS_AVINO
C728 1uF
TP26
TP27
R670
D
0402
R716
R621
0603
0
R620
0402
C733 47nF
0402
18K
R491
0402
R625
48.7K
0402
R624
10K
0402
PGND
PGND
PGND
PGND
PGND
PGND
NC(SW)28
NC(SW)27
NC26
NC25
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
NC15
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WSL0805
2.5V_REG_HPS
2.5V_HPS
R176
C735
47uF
0805
C736
47uF
0805
0.001
WSL2010
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C
R623
36.5K
0402
POK
ENABLE
AVIN
AGND
AGND
VFB
EAOUT
SS
RCLX
FADJ
NC59
AGND
NC(SW)61
NC(SW)62
NC(SW)63
NC64
NC65
NC66
NC67
NC68
0.003
D
C730
22uF
1206
48
47
46
45
44
43
42
41
40
39
38
37
36
35
69
115K
C734 47pF 0402
R622
0402
340K
1%
(27) 2.5_HPS_VDACP4
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
C732 1uF 2V5_HPS_AVINO
0402
4.02K
S_OUT
S_IN
BGND
VDDB
BTMP
PG
AVINO
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
PGNDTHRML
2.5V_REG_HPS
2.5V_REG_HPS
0
R492
EN_2.5V_HPS
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
(27) EN_2.5V_HPS
2.5V_HPS_POK
(35) 2.5V_HPS_POK
RUN_2.5V_HPS
12V
12V_2V5HPS
0402
U68 EN2342QI
PART_NUMBER = EN2342QI
Manufacturer = Enpirion
TP17
QFN-68
B
B
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
E1
32
of
1
41
8
7
6
5
4
3
2
1
Power 3 - 1.5V & 1.5V HPS
E
E
12V
C737 22nF
0402
R659
10K
0402
R626
0402
560
R627
4.75K
0402
1V5_HPS_AVINO
C739 .22uF
0402
C738 1uF
0402
TP28
TP29
R671
R454
0
R717
0402
1.5V_REG_HPS
1.5V_REG_HPS
R629
0
C742 1uF 1V5_HPS_AVINO
0402
4.02K
R630
0603
147K
0402
C744 27pF
1.5V_HPS_POK
(35) 1.5V_HPS_POK
RUN_1.5V_HPS
R631
C773 47nF
0402
20.0K
0402
R455
(27) 1.5V_HPS_VDACP2
732K
R632
33.2K
0402
0402
R634
147K
0402
R633
3K
0402
POK
ENABLE
AVIN
AGND
AGND
VFB
EAOUT
SS
RCLX
FADJ
NC59
AGND
NC(SW)61
NC(SW)62
NC(SW)63
NC64
NC65
NC66
NC67
NC68
PGND
PGND
PGND
PGND
PGND
PGND
NC(SW)28
NC(SW)27
NC26
NC25
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
NC15
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0.003
WSL0805
D
1.5V_REG_HPS
R683
C745
47uF
0805
0.003
R134
WSL1206
C746
47uF
0805
1.5V_HPS
0.003
WSL2010
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
S_OUT
S_IN
BGND
VDDB
BTMP
PG
AVINO
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
PGNDTHRML
EN_1.5V_HPS
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
(27) EN_1.5V_HPS
C741
22uF
1206
48
47
46
45
44
43
42
41
40
39
38
37
36
35
69
D
12V
12V_1V5HPS
U69 EN2342QI
PART_NUMBER = EN2342QI
Manufacturer = Enpirion
TP19
QFN-68
B
B
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
E1
33
of
1
41
8
7
6
5
4
3
2
1
Power 3 - 3.3V HPS
E
E
C747 22nF
0402
R635
0402
560
3.3V
D
R637
100K
0402
12V
R446
10K
C749 .22uF
0402
TP30
0402
RUN_3.3V_HPS
C752 1uF 3V3_HPS_AVINO
0402
R638
0
0603
R639
100K
0402
C754 56pF
0402
(27) 3.3_HPS_VDACP6
R640
0402
215.0K
C753 47nF
0402
15K
R444
0402
C
R641
39.2K
0402
12V
C751
22uF
1206
POK
ENABLE
AVIN
AGND
AGND
VFB
EAOUT
SS
RCLX
FADJ
NC59
AGND
NC(SW)61
NC(SW)62
NC(SW)63
NC64
NC65
NC66
NC67
NC68
PGND
PGND
PGND
PGND
PGND
PGND
NC(SW)28
NC(SW)27
NC26
NC25
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
NC15
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WSL0805
3.3V_REG_HPS
3.3V_HPS
R90
C755
47uF
0805
D
0.003
C756
47uF
0805
0.001
WSL2010
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R643
29.4K
0402
R642
15K
0402
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TP31
12V_3V3HPS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
69
0
4.02K
S_OUT
S_IN
BGND
VDDB
BTMP
PG
AVINO
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
PGNDTHRML
R718
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
EN_3.3V_HPS R445
3.3V_REG_HPS
3.3V_REG_HPS
C748 1uF
0402
R672
0402
(27) EN_3.3V_HPS
R636
4.75K
0402
3V3_HPS_AVINO
U70 EN2342QI
PART_NUMBER = EN2342QI
Manufacturer = Enpirion
TP21
QFN-68
B
B
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
E1
34
of
1
41
8
7
6
5
4
3
2
Power - 1.1V_HPS, 5.0V, 1.8V
1
CAD Note:
Regulator input caps
Place near regulator controller
12V
E
E
C204
22uF
1210
C625
22uF
1210
C573
22uF
1210
C582
22uF
1210
12V
C757 22nF
3.3V
0402
R660
10K
0402
R644
560
0402
R645
4.75K
0402
1V1_HPS_AVINO
0402 .22uF
C759
C758 1uF
TP32
R646
100K
0402
48
47
46
45
44
43
42
41
40
39
38
37
36
35
69
R656
0603
0
R719
4.02K
0
R651
0402
C763 1uF 1V1_HPS_AVINO
0402
R649
0402
C765 18pF
0402
(27) 1.1V_HPS_VDACP0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
0402
174K
R650
0402
C764 47nF
0402
22.0K
1.07M
R654
365K
0402
R652
31.6K
0402
R653
1.5K
0402
PGND
PGND
PGND
PGND
PGND
PGND
NC(SW)28
NC(SW)27
NC26
NC25
VOUT9
VOUT8
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
NC15
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C177
2
5.0V
B
C162
0.1uF
L28
1
C766
47uF
0805
C168
22uF
3
6.5uH
R157
52.3K Isat = 6A
D21
DFLS230
2
1
FB_5.0V
C161
R156
10K
R153
VIN
BD
BOOST1 BOOST2
1
14
13
DNI
16.2K
11
10
SW1
SW2
DA1
DA2
FB1
FB2
RUN/SS1 RUN/SS2
SYNC
RT
C767
47uF
0805
0.001
WSL2010
C
TP23
12
6
Fsw=1.7MHz
2
1.1V_HPS
R161
5.0V
U36
4
22uF
D
1.1V_REG_HPS
U71 EN2342QI
PART_NUMBER = EN2342QI
Manufacturer = Enpirion
12V
QFN-68
WSL0805
Design Note:
0.001 ohm sense resistor
minimized IR drop @ 3A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C
POK
ENABLE
AVIN
AGND
AGND
VFB
EAOUT
SS
RCLX
FADJ
NC59
AGND
NC(SW)61
NC(SW)62
NC(SW)63
NC64
NC65
NC66
NC67
NC68
0.003
C762
22uF
1206
S_OUT
S_IN
BGND
VDDB
BTMP
PG
AVINO
PVIN7
PVIN6
PVIN5
PVIN4
PVIN3
PVIN2
PVIN1
PGNDTHRML
1.1V_REG_HPS
1.1V_REG_HPS
R647
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
EN_1.1V_HPS
12V
R673
D
(27) EN_1.1V_HPS
TP33
12V_1V1HPS
0402
GND
C148
0.1uF
5
L16
1V8
3.3V
1
B
2
6.5uH
7
8
9
D20
DFLS230
2
Run_1V8
C147
Isat = 6A
R144
12.4K
1
C149
22uF
R688
10K
0402
DNI
15
R143
10K
LT3509EDE
Manufacturer = Linear Technology
PART_NUMBER = LT3509EDE#x
R686
R687
Run_1V8
A
0 0402
0 0402
1.5V_HPS_POK
2.5V_HPS_POK
1.5V_HPS_POK (33)
2.5V_HPS_POK (32)
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
35
of
1
41
E1
8
7
6
5
4
3
2
1
Power 4 - Linear Regulators
E
E
2.5V_REG_FPGA
1.5V_REG_FPGA
R510
10.0K
C636
3.3V
C634
10.0K
10
7
9
VIN
EN
PGOOD
VREF_FPGA_DDR3
6
1uF
REFOUT
2
1
0.1uF
10.0K
R513
VTT_FPGA_DDR3
C635
VO
VOSNS
3
5
11
4
8
C613
VLDOIN
REFIN
GND_PAD
PGND
GND
R511
D
10uF
DDR3 FPGA VTT, VREF
U61
TPS51200
PART_NUMBER = TPS51200DRCx
Manufacturer = Texas Instruments, Inc.
10uF
C619
C618
C617
C616
C620
10uF
10uF
10uF
10uF
10uF
R516
10.0K
C646
R408
10.0K
C307
D
1000pF
1.5V_REG_HPS
C338
3.3V
VIN
EN
PGOOD
VREF_HPS_DDR3
6
1uF
C293
0.1uF
REFOUT
VLDOIN
REFIN
2
1
10.0K
R409
C
VTT_HPS_DDR3
C308
VO
VOSNS
3
5
11
4
8
C292
10.0K
10
7
9
GND_PAD
PGND
GND
R388
C
10uF
DDR3 HPS VTT, VREF
U58
10uF
C475
C442
C363
C339
C490
10uF
10uF
10uF
10uF
10uF
1000pF
TPS51200
PART_NUMBER = TPS51200DRCx
Manufacturer = Texas Instruments, Inc.
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
36
of
1
41
E1
8
7
6
5
4
3
2
1
Power 6 - Power & Temperature Monitor
E
E
D
D
C
C
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
37
of
1
41
E1
8
7
6
5
4
3
2
1
Power 7 - Cyclone V GX SoC Power
U21J
2.5V_FPGA
Cyclone V GX SoC Power
1.1V_VCC
E
M11
M13
M9
N10
N12
N14
P11
P13
R10
R12
R14
T11
T13
U10
U12
U14
V11
V13
V15
W10
W12
W14
Y11
Y13
Y9
U21
D
VCCPD3A
VCCPD3A
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD5A
VCCPD5A
VCCPD5B
VCCPD8A
VCCPD8A
VCCPD8A
VCCPD8A
VCCPD8A
VCCPGM
VCCPGM
VCCPGM
VCCBAT
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
F1
G2
AA7
AD15
E26
J15
C
DNU
DNU
DNU
DNU
DNU
DNU
VCC_AUX_SHARED
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
AA10
AC10
E
AB18
AB20
AC13
AC15
AC17
AC19
AD16
AE21
U21K
2.5V_FPGA
VREF_FPGA_DDR3
V22
V24
1.5V_FPGA
(2.5V)
U23
K11
K13
L10
L12
L14
1.5V_FPGA
J11
AA23
AB10
2.5V_FPGA_FILT
AB11
AB16
AD22
H10
J16
AC11
AD8
AF7
AG4
AD6
AB14
AD13
AE15
AJ13
AJ8
AK10
AJ15
AA17
AC21
AD18
AE25
AF22
AG19
AH16
AH26
AJ23
AK20
AK17
H9
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VREFB3AN0
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VREFB3BN0
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VREFB4AN0
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VREFB5AN0
VCCIO5B
VCCIO5B
VREFB5BN0
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VREFB8AN0
W23
AG29
AD28
AB24
AC24
AE30
AA27
AA29
J13
H6
G9
G14
F12
E5
D8
C11
B4
A7
B10
D
U21L
AA5
M6
N5
T6
U5
Y6
5CSXFC6D_F896
VCCL_GXBL
VCCL_GXBL
VCCL_GXBL
VCCH_GXBL
VCCH_GXBL
VCCH_GXBL
VCCE_GXBL
VCCE_GXBL
1.1V_VCCL
W5
R5
L5
1.5V_HPS
2.5V_VCCAUX_SHARED
L25
VREF_HPS_DDR3
B
2.5V_FPGA_FILT
V6
P6
AB6
3.3V_HPS
U16
T17
L18
R16
P19
P17
P15
L20
L16
T19
N20
M15
U18
2.5V_FPGA_FILT
3A, 30 Ohm FB
VCCE_GXBL
VCCE_GXBL
VCCE_GXBL
VCCE_GXBL
1.1V_HPS
5CSXFC6D_F896
2.5V_HPS
Cyclone V GX SoC
Transceiver & HPS Power
1.1V_VCCEL
2.5V_VCCAUX_SHARED
J21
N7
R7
V8
AA8
K9
Y22
Cyclone V GX SoC Power
2.5V_FPGA
D28
G29
H26
K24
K30
L27
M24
N21
G27
P23
P28
R25
T22
U19
V26
U30
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7B_HPS
VCCIO7B_HPS
VCCIO7C_HPS
VCCIO7D_HPS
VCCIO7D_HPS
VREFB7N0_HPS
F22
H21
C
G19
E20
D18
3.3V_HPS
E15
H16
E22
2.5V_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VREFB6AN0_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPs
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VREFB6BN0_HPS
VCCPD7B_HPS
VCCPD7D_HPS
VCCPD7C_HPS
VCCPD7A_HPS
VCCPLL_HPS
VCCRSTCLK_HPS
R23
R20
P21
N22
M21
K16
3.3V_HPS
B
J17
K18
K19
2.5V_HPS_FILT
L21
2.5V_HPS
J20
5CSXFC6D_F896
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
38
of
1
41
E1
8
7
6
5
4
3
2
1
Power 8 - Cyclone V GX SoC Ground
E
E
U21I
U21H
Cyclone V GX
SoC GND
J6
J22
D26
A26
A12
A17
A2
A22
A27
AA11
AA22
AA3
AA4
AA6
AA9
AB1
AB19
AB2
AB29
AB5
AB7
AC16
AC26
AC3
AC4
AC6
AC8
AD1
AD2
AD23
AD5
AE10
AE20
AE3
AE4
AF1
AF12
AF17
AF2
AF27
AF3
AG14
AG24
AG9
AH1
AH11
AH21
AH6
AJ18
AJ28
AJ3
AJ30
AK15
AK25
AK5
B14
B19
D
C
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Cyclone V GX
SoC GND
B24
B29
B9
C1
C16
C21
C26
C6
D13
D23
D3
E10
E25
E30
F17
F2
F27
F5
F7
G24
G3
G4
H1
H11
K5
L11
L13
L15
L17
L19
L22
L3
L4
L6
M1
M10
M12
M14
M16
M18
M2
M20
M29
M5
M7
M8
N11
N13
N15
N17
N19
N26
N3
N4
N6
N8
N9
P1
P10
P12
P14
P16
P18
P2
P20
P5
P7
R11
R13
R15
R17
T20
R3
R30
R4
R8
H2
H5
J18
J28
J3
J4
J8
K1
K10
K15
K2
K20
K25
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T7
U11
U13
U15
U17
U24
U29
U3
U4
U6
U9
V1
V10
V12
V14
V19
V2
V21
V5
V7
W11
W13
W18
W28
W3
W4
W6
W9
Y1
Y10
Y12
Y14
R6
Y15
Y2
Y20
Y25
Y30
Y5
Y7
Y8
U22
T18
T5
T27
T2
T16
T15
T14
T12
T10
T1
R9
D
C
B
5CSXFC6D_F896
5CSXFC6D_F896
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
39
of
1
41
E1
8
7
6
5
4
3
2
1
Decoupling
1.1V_vcc
1.1V_VCC
1.1V_VCCEL
C344
E
C314
DNI
2.5V
C559
DNI
2.5V
C334
C553
4.7uF
C560
330uF
2.5V
C290
C552
4.7uF
C561
DNI
2.5V
2.2uF
C562
DNI
2.5V
C554
1.0UF
C502
C439
C539
C501
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
C533
C530
C532
C536
C537
330uF
2.5V
C531
1.0UF
C535
C563
DNI
2.5V
C534
0.47uF
0.47uF
C280
DNI
2.5V
C269
DNI
2.5V
C303
C511
330uF
2.5V
100uF
6.3V
C417
22uF
4V
C390
4.7uF
C480
0.47uF
C358
C359
C440
0.22uF
0.1uF
47nF
C360
C479
C63
C435
C74
C389
C388
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
1.1V_VCCL
C416
C279
742792780
0.47uF
C67
C473
C462
4.7nF
22nF
22nF
22nF
C382
100uF
6.3V
1uF
C528
C437
2.5V_fpga
2.5V_FPGA
L26
1.1V_vccel
0.47uF
C385
C500
C357
0.22uF
0.1uF
47nF
C469
C471
C478
C423
C343
0.01uF
0.01uF
22nF
4.7nF
4.7nF
E
2.5V_fpga_filt
C538
2.5V_FPGA_FILT
C510
1.5V_vccio
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
1.5V_FPGA
0.1uF
C468
C550
D
C438
C526
C386
C424
C384
C383
C551
C521
C522
C523
C524
0.22uF
0.1uF
47nF
C410
330uF
2.5V
47nF
4.7uF
0.47uF
47nF
47nF
47nF
47nF
47nF
47nF
C406
C428
C430
C432
C458
C460
C525
C527
C470
C477
C529
47nF
47nF
47nF
47nF
47nF
47nF
0.01uF
0.01uF
0.01uF
22nF
22nF
C455
C457
C456
C431
C429
C433
C508
C454
C507
C499
C509
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
C476
100uF
6.3V
C356
1.0UF
0.47uF
C387
C355
0.1uF
47nF
D
2.5V_FPGA_FILT
C436
C414
C453
C472
C498
0.01uF
0.01uF
0.01uF
0.01uF
22nF
C783
1uF
22nF
22nF
22nF
22nF
22nF
C459
22nF
22nF
C409
C413
C404
C408
C412
C411
C407
22nF
22nF
22nF
22nF
22nF
22nF
22nF
C434
C415
C461
4.7nF
4.7nF
4.7nF
C405
22nF
1.5V_hps
C
2.5V_HPS
C
1.5V_HPS
2.5V_hps
C347
C449
1.1V_HPS
100uF
6.3V
C277
C278
100uF
6.3V
C380
C276
100uF
6.3V
0.47uF
2.2uF
C379
C381
0.22uF
0.1uF
C427
C425
C402
C401
C426
C403
47nF
47nF
22nF
22nF
22nF
22nF
B
C397
4.7uF
C452
0.47uF
C373
C421
C398
0.1uF
47nF
47nF
C329
330uF
2.5V
C450
C374
C451
C352
C377
C375
C422
0.01uF
0.01uF
0.01uF
0.01uF
22nF
22nF
22nF
C399
C400
4.7nF
4.7nF
4.7uF
C295
0.47uF
C296
C372
C312
0.22uF
0.1uF
47nF
C313
C330
C331
C350
C340
0.01uF
0.01uF
0.01uF
22nF
22nF
C348
C332
C333
C341
C349
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
B
2.5V_HPS_FILT
2.5V_VCCAUX_SHARED
SCREW2
STANDOFF1
SPACER1
SCREW4
STANDOFF2
SPACER2
SCREW1
SCREW5
STANDOFF3
SCREW6
STANDOFF4
2.5V_HPS_FILT
3.3V_HPS
C272
1.0UF
3.3v_HPS
C271
4.7uF
C274
100uF
6.3V
A
C273
1.0UF
C300
0.22uF
C299
C353
C378
C351
C354
0.01uF
0.01uF
0.01uF
4.7nF
4.7nF
Title
22nF
Size
B
Date:
7
6
5
C376
0.01uF
22nF
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
C342
8
C301
47nF
PCB1
47nF
C297
C302
10uF
SCREW3
C298
0.1uF
C275
4
3
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Tuesday, August 05, 2014
2
Rev
(6XX-44184R)
Sheet
40
of
1
41
E1
5
D
4
REV
DATE
PAGES
E1
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/11/2014
7/15/2014
8/01/2014
8/29/2014
9/12/2014
28
28
29-35
29
29-35
29
29
29
40
19
6,27
22
6
5,6
8
8
29
21, 25
22
3
2
1
DESCRIPTION
D
Add two Hot-Plug Controller circuit (LTC4218)
When 12V_ATX is using, auto disable LTC3855’ s 12 V_ RE G by S W5
Generate ENABLE signal using resistor divider circuit for all Enpirion parts
One more 22uF bulk cap for EN23F2QI PVIN rail
Replace EN23F0QI with EN23F2QI, EN2340QI with EN2342QI
Put option for pre-bias circuit on EN23F2QI CGND (EN_PB) pin
Changing switching frequency of EN23F2QI (R663=22K)
DNI external current limitation circuit of EN23F2QI
DNI some 330uF bulk decoupling caps for 1.1V_VCC rail, only use C559, C563 and C303
Change Dual Ethernet PHY to async mode by default with R720
HPS GPIO control the FPGA power management chip
Add hard reset SD card (power recycle)
Use jumper J39 to replace R32 resistor
Update 5CSXFC6D_F896 schematic symbol on HPS_GPI[13:0] and VCCRSTCLK_HPS
Move R137/R135 to the right side of R138/R136
Change R57 to 180K, change R58,R58 to 4.99K ohm
Change R588 to 46.4K for EN23F2QI parts which has data code U418 or higher
Replace U48/U55/U56 with ADM811-3T for longer delay
Replace R721 with 1K. Replace C6 with R730 100ohm resistor.
C
C
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
5
4
3
2
Cyclone V SoC FPGA Development Kit Board
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Document Number
150-0321003-E1
Friday, September 12, 2014
Rev
(6XX-44184R)
Sheet
1
41
of
41
E1
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