AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces

Implementing Multiple
Legacy DDR/DDR2 SDRAM
Controller Interfaces
Application Note 392
July 2007, v2.0
Introduction
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This application note details the steps for designing multiple legacy
DDR2 controllers into a single FPGA. After reading this application note
you should be able to understand important design considerations such
as PLL and DLL resource allocation, timing analysis, and debugging.
If you want to implement ALTMEMPHY based multiple controllers,
refer to AN 462: Implementing Multiple Memory Interfaces Using the
ALTMEMPHY Megafunction, as these will not be discussed here.
The multiple controller design flow is explained by showing an example
of a two controller design and a three controller design using the
DDR/DDR2 SDRAM controllers.
Design Details
■
Two independent controllers (Figure 1)
●
One on the top and the second on the bottom of the device
●
No resource sharing among the controllers
■
Three controllers (Figure 2)
●
Two on the top and another one on the bottom.
●
PLL and DLL resource sharing for the two interfaces on the top
of the device
This section explains the design specifications, such as memory
frequency, memory interface width, and the number of PLLs in the
controllers. These details are important to know up front, as they help
make it possible to achieve maximum performance by using the correct
device. The specifications are as follows:
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Altera Corporation
AN-392-2.0
Target device: EP2S90F1020C3
DDR2 Controller version: Quartus® II 6.1 and higher
Quartus II software: Version 6.1 and higher
Controller interface frequency: 266.67 MHz for all the controllers in
the design
Interface width: 32 bits for each controller
Number of PLLs: 2 (System PLL and feedback PLL) for each
controller in both designs.)
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Figure 1 shows the two controller implementation. In this design, each
controller has its own PLL and DLL resources.
Figure 1. Two-Controller Implementation
SDRAM Memory
System PLL
FPGA
DLL
PLL 5
DDR2 Controller
PLL11
PLL 12
DLL
PLL 6
Fedback PLL
Fedback PLL
DDR2 Controller
System PLL
SDRAM Memory
Figure 2 shows the three-controller implementation, in which DLL and
PLL resources are shared between two of the controllers.
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Preliminary
Refer to Figure 4 for details on which clock resources are shared
among the three controllers.
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Design Considerations
Figure 2. Three-Controller Implementation
SDRAM Memory
SDRAM Memory
PLL 11
(Fedback PLL)
DDR2 Controller
Top_left
DLL
DLL
PLL 5
(System
PLL)
PLL 6
(Fedback
PLL)
DDR2 Controller
Top_right
DDR2 Controller
Bottom_right
SDRAM Memory
Design
Considerations
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It is important that the designer knows which resources in an FPGA need
to be shared between the custom logic and the controllers. The following
design considerations apply to both two- and three-controller designs:
1.
One or more clock pairs (clk_to_sdram[] and
clk_to_sdram_n[]) from the FPGA to memory is available for
each interface.
2.
One system PLL and one feedback PLL are available for each
controller. The system PLL generates the system clock and the
feedback PLL generates the feedback clock in each controller.
Figure 3 shows the configuration Altera® recommends for closing
timing on legacy-based memory interfaces greater than 200 MHz.
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
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Refer to the section Appendix A, Resynchronization in the DDR and DDR2
SDRAM Controller Compiler User Guide to learn more about the
functionality of the feedback and system PLL.
Figure 3 shows a two-PLL read datapath implementation, including the
PLLs configured as system and feedback PLLs.
Figure 3. A DDR2 SDRAM Controller Using Both a Feedback and a System PLL
Optional, depending on setting of
"Insert intermediate resynchronization
registers."
Gclk - Global Clock
Rclk - Regional Clock
dq_capture
D
resynched_data
Q
D
feedback_resynched_data
Q
D
Q
inter_rdata
D
Q
User logic
dq
DLL
Gclk
Gclk
D
dqs
Q
D
dq_enable_reset
Q
D
Q
address/cmd
doing_rd_delayed
Q
D
Gclk
D
Q
dqs
clk2 (resync clock)
PLL 11 or PLL 12
clk0
(write clock) D
clk0 (fedback clock)
Rclk
Feedback
clock in
clk1 (postamble clock)
Q
dq
System
PLL
Gclk clk1
clk3
PLL 5 or PLL 6
Feedback
clock out
DLL Resource
Considerations
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Preliminary
The Stratix® II and Stratix II GX series of FPGA devices support one DLL
on the top and one DLL on the bottom of the FPGA. This requires that
memory controllers on the same side of the device operate at the same
frequency, because all the controllers must share the output from the
common DLL.
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PLL Resource Considerations
PLL Resource
Considerations
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PLL resources are critical because only a fixed number of PLL output taps
are available. You should be careful when choosing global and regional
clock resources, as they are limited in number and vary depending upon
the device. This section discusses what type of resource to use for
different clocks.
To learn more about the PLL resources, refer to the Enhanced PLLs and
Fast PLLs sections of the PLLs in Stratix II and Stratix II GX Devices
chapter in volume 2 of the Stratix II Device Handbook.
In a two-controller design, because the two controllers are independent,
the PLLs are instantiated by the IP tool bench and require no
modifications.
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If both the memory interfaces are at the same frequency, then the
PLL resources can be shared.
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If the data has to cross over boundaries that are clocked by
clocks coming out of two separate PLLs, proper data
synchronization care should be exercised.
In a three-controller design, the minimum number of PLL taps required
to drive all three controllers is 11. Table 1 describes the clocks required for
the three-controller example design.
Table 1. Clocks Required for Three-Controller Example Design
Clock Name
Description
# of Clocks
System clock
A single system clock drives all 3 controllers.
Write clock
A single write clock drives all 3 controllers.
1
Resynchronization clock
There is one resynchronization clock for each
controller. (1)
3
Feedback resynchronization
clocks
There is one feedback resynchronization clock for
each controller. (1)
3
Postamble clocks
There is one postamble clock for each controller. (1)
3
Total
1
11
Note to Table 1:
(1)
If two or more controllers share a resynchronization/feedback/postamble clock, you must place matching
constraints on the board trace delay and the board layout for the external memories. To overcome such constraints,
use three separate resynchronization/feedback/postamble clocks. The 11 PLL taps are chosen from three
enhanced PLLs, as shown in Figure 4.
The DLL reference clock for I/O banks 3 and 4 can only be driven by
enhanced PLL5 or by the dedicated clock input pins CLK[4-7] or CLK[1215] on the appropriate side of the device. The DLL reference clock for I/O
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
banks 7 and 8 can only be driven by enhanced PLL6 or by the dedicated
clock input pins on the appropriate side of the device. For example, if the
PLL input reference clock frequency is 100 MHz, and the required output
frequency is 266.67 MHz, the multiplication factor will be 8/3. In this
case, the DLL reference clock, which must have a frequency of 266 MHz,
cannot be driven by any of the dedicated clock input pins and therefore
must be driven by enhanced PLL5 or enhanced PLL6.
Do not use any feedback clocks to drive the DLL reference because
feedback clocks generally have a higher jitter due to the signal going offchip and then back on-chip. The system PLL must be PLL5 for the
controllers at the top and PLL6 for the controllers at the bottom.
Figure 4 shows the PLL resource usage in a three-controller design. The
figure also shows which PLL tap is used as a global/regional resource.
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PLL Resource Considerations
C4 resync_clk_2
R30
Enh PLL 6
C3 mem_clk_dedicated R31
C2 resync_clk_3
G14
C1 wr_clk(-90)
G13
R14
fb_resync_clk_3
C4
Co clk
G12
R15
postamble_clk_3
C5
C5 fb_resync_clk_1
R31
C4 postamble_clk_2
R30
C3
C2 postamble_clk_1
R26
Bank 7/Controller bottom_right
R29
B7_fb_clk_in
C5 resynch_clk_1
Enh PLL 12
Enh PLL 5
Enh PLL 11
Clock_src
B34_fb_clk_in
Bank 3/Controller top_left
Bank 4/Controller top_right
Figure 4. PLL Resource Allocation
C1
C0 fb_resync_clk_2
R24
Note to Figure 4:
(1)
mem_clk-dedicated is optional in FPGA designs but is required to drive the clk_to_sdram outputs in
HardCopy® II applications.
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Using three enhanced PLLs, as shown in Figure 4, requires the fewest
number of global routing resources. Table 2 describes the tradeoffs you
must consider before using fast PLLs or fewer enhanced PLLs in your
three-controller design.
Table 2. Tradeoffs Between Enhanced PLLs and Fast PLLs
PLL Possibilities
2 enhanced PLLs — Both
on the top
Comments
Only 4 chip-wide global signals can be driven from any side of the device. However,
the system clock, write clock, resynchronization clock, feedback resynchronization
clock, and postamble clock for the controller on the bottom of the chip all require
global clocks, which is 1 more than is available. This could still be accomplished by
sharing one of the resynchronization, feedback resynchronization, or postamble
clocks with another interface, but that would cause board layout restrictions. All
resynchronization, feedback resynchronization, and postamble clocks for the top
DDR interfaces must be dual-regional.
2 enhanced PLLs — 1 on If the system PLL is placed on the top with 2 DDR interfaces, the system clock,
the top and 1 on the bottom write clock, and resynchronization clock for the bottom interface must be driven
onto global networks, leaving 1 global network free on the top. The feedback PLL
would require all 4 bottom global networks to reach the DDR interfaces at the top.
If the system PLL is placed on the bottom with the single DDR interface, the system
clock, write clock, and 2 resynchronization clocks must be made global from the
bottom of the chip. The feedback PLL at the top would only need to drive 2 signals
globally from the top. Therefore, putting the feedback PLL on the same side of the
chip as the 2 DDR interfaces is a more desirable configuration.
2 enhanced PLLs and 1
fast PLL
The purpose of the feedback PLL is primarily to compensate for the variation of the
I/O buffer input and output delays. If you use a fast PLL for the feedback PLL, you
are using I/Os on the side of the chip and not on the top or bottom. Since those pins
have different characteristics, they will not track the variations as well. Fast PLLs
have only 4 output taps, so you need more than 1 of them to support 3 DDR
interfaces. Another concern is that a fast PLL requires a global network to drive
signals to the opposite side of the chip (that is, left to right or right to left), so you
may need to use a global signal to drive a signal that only needs to go to the top or
to the bottom. Depending on the number of memory interfaces, using a fast PLL as
the system PLL may still be feasible.
Table 3 shows that the system clock (clk), write clock (wr_clk) and the
resynchronization clock (resync_clk_3) are made global as
represented by Gclk. This is because the system clock and the write clock
have to drive all three controllers on both sides of the chip, and the
resynchronization clock (resync_clk_3) is made global as the signal
has to traverse from the top of the chip to the bottom of the chip to drive
the resynchronization registers of the bottom right controller.
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Instantiating DDR/DDR2 SDRAM Memory Controllers
Table 3. Clock Resource Types Note (1)
Enhanced
PLL #
Resource
Type
clk
11
Global
The clock drives the 3
controllers that are placed in
three quadrants.
write_clk
11
Global
The clock drives the 3
controllers that are placed in
three quadrants.
dedicated_resynch_or_capture_clk_bot
tom_right
11
Global
The signal has to traverse
across the quadrants.
mem_clk_dedicated
11
None
Only needed to drive
dedicated clock output pins.
Not required.
dedicated_resynch_or_capture_clk_top
_right
11
Regional
—
dedicated_resynch_or_capture_clk_top
_left
11
Regional
—
fedback_resynch_clk_top_left
5
Regional
—
dedicated_postamble_clk_top_left
5
Regional
—
dedicated_postamble_clk_top_right
5
Regional
—
fedback_resynch_clk_top_right
5
Regional
—
fedback_resynch_clk_bottom_right
6
Regional
—
dedicated_postamble_clk_bottom_right
6
Regional
—
Signals
Comments
Note to Table 3:
(1)
These settings for the regional and global clocks work when each of the controllers has a 32-bit or narrower DQ
interface. If the DQ interface exceeds 32 or 40 bits, it spans the entire top or bottom side of the chip. In that case,
dual-regional clocks must be used, because the interface is spread across two quadrants. The PLL routing
resources vary for each design, and the example design illustrates one case.
Instantiating
DDR/DDR2
SDRAM Memory
Controllers
This section explains how to generate controllers for the design. It is
important to go through the section thoroughly, as it explains the required
settings for achieving the proper timing with minimum iterations.
After creating the Quartus II project, generate DDR/DDR2 SDRAM
controllers using the MegaWizard® Plug-In Manager.
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You must invoke the MegaWizard Plug-In Manager each time
you generate a new controller under the same project.
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
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Refer to the DDR and DDR2 SDRAM Controller Compiler User Guide to
learn more about parameterizing and generating the SDRAM controller
using the MegaWizard Plug-In Manager.
When generating cores using the MegaWizard Plug-In Manager, four
pages are critical:
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MegaWizard Plug-In Manager Page 2a
IP Toolbench - Step 1: Parameterize - Controller Page
IP Toolbench - Step 1: Parameterize - Project Settings Page
IP Toolbench - Step 1: Parameterize - Manual Timings Page
MegaWizard Plug-In Manager Page 2a
Generate the controllers in separate directories. For example, if the design
has two controllers, one at the top and one at the bottom, generate the
DDR2 controller megafunctions at <quartus_project_dir>/top_ddr2.v and
<quartus_project_dir>/bottom_ddr2.v. This helps you avoid the clutter of
having all the files in one directory.
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When the controllers are generated in separate directories, the
PLLs are instantiated with the same names
(ddr_pll_stratixii and ddr_fb_pll_stratixii) for
both the controllers. Change the names of the PLL instantiations
so that they are not common to the two controllers in the design.
Also, when you regenerate the controller for any reasons, the
PLL files (ddr_pll_stratixii.v and ddr_fb_pll_stratixii.v) are
overwritten and you must repeat the name change process.
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When you generate the controllers, the MegaWizard Plug-In
Manager generates two PLLs: the system PLL and the feedback
PLL. The PLLs are instantiated in the file multiple_ddr2_top.v
under the directories top_right, top_left and bottom_right. For
the three-controller design, these PLLs are not used in the
top-level design and three separate PLLs are generated using the
MegaWizard Plug-In Manager to suit the design requirements.
Generate the PLLs under the directories pll_1_top, pll_2_top,
and pll_bottom. Refer to the top-level design file of the
three-controller design (multiple_ddr2_top.v) to see the PLL
instantiations along with their output connections.
Controller Page
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Preliminary
a.
Turn on DQS mode.
b.
Turn on Use fedback clock.
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Instantiating DDR/DDR2 SDRAM Memory Controllers
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When this option is enabled, the registers that capture data from
the DQ pins during reads are clocked by a delayed version of
DQS. Otherwise, a PLL-generated clock captures the data
(Stratix series only). DQS mode provides higher performance
than non-DQS mode. Non-DQS mode allows greater flexibility
for placing pins, because it allows DQ pins to be placed in the
side banks. Only the top and bottom banks support the circuitry
required to delay the DQS signals to capture the read data.
For more details about DQS and non-DQS mode, refer to AN 328:
Interfacing DDR2 SDRAM with Stratix II Devices.
c.
1
This register helps to achieve the required performance at
frequencies of 200 MHz. When this option is enabled, the wizard
inserts a pipeline register stage between the memory controller
and the command and address outputs. When this option is
turned on, an extra cycle of latency is added between the time at
which the local_read_req or local_write_req signal is
asserted at the local interface and the time address/command
appears at the memory interface.
d.
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Turn on Insert pipeline registers on address and command
outputs.
Turn on Clock address/command output registers on the
negative edge.
This option allows you to adjust the output timing of the address
and command signals to meet the setup and hold requirements
of the memory device. However, you must perform your own
timing analysis of address/command timing. Generally, turn on
this option, except for Stratix II designs operating at 200 MHz or
higher.
Project Settings Page
Prefix all pins on the device with appropriate names while generating the
respective controller. By doing this, the IP Toolbench prefixes the top level
pin names of the controller with the name given, as shown in Figure 5.
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Figure 5. Project Settings Page
For example in the case of a two-controller design:
a.
ddr2_bottom_
b. ddr2_top_
Turn off Update the example design PLLs, if PLL phases have to be
changed later and edited by using the PLL MegaWizard Plug-In Manager.
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Altera Corporation
Instantiating DDR/DDR2 SDRAM Memory Controllers
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If you turn on Update the example design PLLs option, PLL
and phase changes in the MegaWizard Plug-In Manager are
reflected automatically in the PLL settings and you do not need
to edit the phases with the PLL MegaWizard Plug-In Manager.
Manual Timings Page
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a.
Turn on Manual resynchronization control.
b.
Turn on Manual postamble control.
c.
Turn on Enable DQS postamble logic.
d.
Enter the appropriate Dedicated clock phase setting in both the
Resynchronization Options section, and Postamble Options
section as shown in Figure 6.
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Figure 6. Manual Timings Page
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Preliminary
Initially, you can input arbitrary numbers for the clock phases
and later change the values with the DTW timing analysis script.
Refer to the DDR/DDR2 SDRAM Controller Compiler User Guide for more
details about any of the page settings.
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RTL Code Modifications
RTL Code
Modifications
After generating the two or three controllers, you must stitch the
controllers together to create the top-level file. Figure 1 and Figure 2 show
the top-level design of the two- and three- controller designs. The
top-level files for both the two- and three- controller designs are provided
along with this document for reference, but must be copied and
customized by the designer.
Key modifications made to the top-level file (multiple_ddr2_top.v)
include:
1.
The pnf output from all the three controllers are named as separate
signals:
a. pnf_top_right
b. pnf_top_left
c. pnf_bottom_right
Quartus II
Compilation
2.
pnf_per_byte [0:7] is the OR of the signals
pnf_per_byte_top_right | pnf_per_byte_top_left |
pnf_per_byte_bottom_right
3.
test_complete is the OR of the signals test_complete =
test_complete_top_right | test_complete_top_left |
test_complete_bottom_right
4.
The PLL and DLL connections are as shown in Figure 1 and
Figure 2.
To achieve maximum performance, you must use the settings shown in
Table 4 in the Quartus II software:
Table 4. Key Settings for Maximum Performance in Quartus II (Part 1 of 2)
Page Name
Settings
Analysis and Synthesis
Settings
In the Optimization Technique section, select Speed.
Fitter Settings
In the Timing-driven compilation section, turn off the Optimize hold timing
option.
Turn off the Optimize fast-corner timing option.
In the Fitter Effort section, select Standard Fit (highest effort).
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Table 4. Key Settings for Maximum Performance in Quartus II (Part 2 of 2)
Page Name
Settings
Timing Analysis Settings
In the Timing analysis processing section, select Use TimeQuest Timing
Analyzer during compilation or Use Classic Timing Analyzer during
compilation. (1)
Note to Table 4:
(1)
Altera recommends that you use the TimeQuest Timing Analyzer.
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I/O Standard
Assignments
Refer to Step 4 of the Design Flow section Add other assignments for the
design in the DDR Timing Wizard User Guide for more details.
Source the constraints file auto_add_constraints.tcl to assign I/O
standards to the top-level pins in the design. This file gets created
automatically while generating the multiple controllers, and this file
contains references to the .tcl files of the controllers used in the design.
For the three-controller example, the auto_add_constraints.tcl file
references the following files:
top_right/add_constraints_for_ddr2_top_right.tcl
bottom_right/add_constraints_for_ddr2_bottom_right.tcl
top_left/add_constraints_for_ddr2_top_left.tcl
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I/O Location
Assignments
Refer to the DDR and DDR2 SDRAM Controller User Guide for more
information about compiling an example design.
Assign the top level pins such as address, data, and dqs signals to the
closest I/O bank. For example, assign the top level signals of the
top_right controller to I/O bank 3, the top_left controller signals to
I/O bank 4, and the bottom_right controller signals to I/O bank 7.
Assign clock_source to A16, ddr2_top_right_fedback_clk_in
to A17, and ddr2_bottom_right_fedback_clk_in to AM16.
1
These pins are chosen as they are dedicated clock input pins on
the same side of the device as the PLLs they are driving.
Assign all of the clk_to_sdram and sdram_n pins with the following
guidelines:
1.
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Preliminary
Dedicated clock pin pairs in the same bank as the memory interface
resides, for example:
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I/O Location Assignments
2.
a.
Bank3 = CLK14p/n and CLK15p/n
b.
Bank4 = CLK12p/n and CLK13p/n
c.
Bank7 = CLK6p/n and CLK7p/n
d.
Bank8 = CLK4p/n and CLK5p/n
Dedicated clock pin pairs on the same side of the device as the
memory interface resides, for example:
a.
Top Side = CLK12/13/14/15p and n
b.
PLL5_OUT[2..0]p and n
c.
PLL11_OUT[2..0]p and n
d.
Bottom Side = CLK4/5/6/7p and n
e.
PLL6_OUT[2..0]p and n
f.
PLL12_OUT[2..0]p and n
First look for suitable differential pin pairs in the same bank, then in the
same side as the controller resides.
Place the pins reset_n, test_complete, pnf, and
pnf_per_byte[7:0] to the side banks 5 and 6 as these signals should
not cause any timing closure issues.
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These pins should not be placed too far away from the respective
controllers because doing so can cause timing violations.
Figure 7 shows a chart summarizing the steps you have taken thus far to
implement a multiple memory interface controller.
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Figure 7. Steps to Implement Multiple-Memory Interface Controller
Create Quartus
Project
Generate the
Controllers
Create the Top
Level File
Add Constraints
Set Quartus II
Compilation
Settings
Assign Pins
Through Pin
Planner
The next step is to run the DTW (DDR timing wizard).
1
The timing analysis script (auto_verify_ddr_timing.tcl)
generated by the Quartus MegaWizard Plug-In Manager does
not work with multiple controllers when regional clocks are
used. Quartus II software generates the following error
messages:
Error: Evaluation of Tcl script
auto_verify_ddr_timing.tcl unsuccessful.
Error: Quartus II Shell was unsuccessful. 2 errors, 8
warnings
Error: Quartus II Full Compilation was unsuccessful. 2
errors, 774 warnings
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Running the DTW Script
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Running the
DTW Script
For this project, use DTW, as there are many advantages to using it. To
learn more about the DTW refer to the DDR Timing Wizard User Guide.
To run the DTW script, on the Tools menu, click Tcl Scripts. Select dtw.
Generate a separate *.dwz file for each of the controllers with separate
names. For example, the three files generated for a three controller design
are:
■
■
■
f
Compile the
Design
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DTW Timing
Analysis
top_right_ddr_settings.dwz
top_left_ddr_settings.dwz
bottom_right_ddr_settings.dwz
Refer to the DDR Timing Wizard User Guide for more information about
how to use the DTW timing analysis script.
The DTW script populates the design constraints in the form of an SDC
file, and this constraints file needs to be added to the design files before
compiling the design.
Refer to the DDR Timing Wizard User Guide for more information about
how to use the DTW timing analysis script.
Now that the design has been compiled with all the constraints, it is
necessary to check whether the timing has been met or not.
1
Refer to the DDR Timing Wizard User Guide for details about
using the DTW and also how to perform timing analysis.
The following steps are performed at the command prompt. The script
dtw_timing_analysis.tcl file is located in the Quartus II project directory.
quartus_sh -t dtw_timing_analysis.tcl -dwz_file
top_right_ddr_settings.dwz
quartus_sh -t dtw_timing_analysis.tcl -dwz_file
top_left_ddr_settings.dwz
quartus_sh -t dtw_timing_analysis.tcl -dwz_file
bottom_right_ddr_settings.dwz
After running the script, close and reopen the compilation report to
verify the timing analysis results.
The DTW script provides details about what to do next if the timing is not
met as shown in Figure 8.
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Figure 8. DTW Script Timing Details
Typically, cycle adjustment is necessary, as shown in Figure 9.
Figure 9. Cycle Adjustment
To achieve cycle adjustment, perform the following steps:
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DTW Timing Analysis
quartus_sh -t dtw_timing_analysis.tcl -dwz_file
top_right_ddr_settings.dwz -extract_tcos ignore
–read_side tq –auto_adjust_cycles
This step is done for the respective controller if the cycles need to be
adjusted. After running the DTW script, an indication of what you should
do next is provided in the Quartus II software.
After adjusting the cycles, the next step is to adjust the phase of all three
clocks. This can be done either in the IP Toolbench or by editing the
respective PLL settings.
Once the phase adjustment is done, the next step is to compile the design
with the new PLL phases.
quartus_sh -t dtw_timing_analysis.tcl -dwz_file
top_right_ddr_settings.dwz -extract_tcos no –read_side
tq –after_iptb import_and_compile
Repeat the previous step for all the controllers for which PLL phase
adjustment was done. If phase adjustment was done for all three
controllers, compilation can be done once and the timing analysis can be
done for the three controllers, as shown in the following example:
quartus_sh -t dtw_timing_analysis.tcl -dwz_file
top_right_ddr_settings.dwz -extract_tcos no –read_side
tq –after_iptb import_and_compile
quartus_sh -t dtw_timing_analysis.tcl -dwz_file
top_left_ddr_settings.dwz -extract_tcos no
quartus_sh -t dtw_timing_analysis.tcl -dwz_file
bottom_right_ddr_settings.dwz -extract_tcos no
In this case, compiling the design three times is avoided.
Altera Corporation
21
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Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Trouble-Shooting
Perform all the steps presented in the DTW script. If there are any
violations that relate to destination registers, they appear named
inter_rdata[*] as shown in “Violations Relating to Destination
Registers”.
Example 1–1. Violations Relating to Destination Registers
ddr2_bottom_right:ddr2_bottom_right_ddr_sdram|ddr2_bottom_right_auk_ddr_s
dram:ddr2_bottom_right_auk_ddr_sdram_inst|ddr2_bottom_right_auk_ddr_datap
ath:ddr_io|ddr2_bottom_right_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|int
er_rdata[5]
If you receive an inter_rdata[*] violation, under Manual Page
Settings, toggle the Insert intermediate synchronization registers
option. If the setting is on, turn it off, if it is off, turn it on. Figure 10 shows
this option turned on.
22
Preliminary
Altera Corporation
Conclusion
Figure 10. Insert Intermediate Resynchronization Registers Unchecked
Conclusion
Altera Corporation
As shown in this application note, there are multiple ways to create
multiple-controller designs using the DDR/DDR2 SDRAM controller.
This application note described the steps necessary to create and meet the
performance requirements for two types of multiple-controller designs. If
your designs are different than those described in this application note,
you must follow the guidelines and make appropriate changes wherever
necessary. Knowing the requirements and limitations for the
multiple-memory interface up front allows you to architect your system
better.
23
Preliminary
Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
Document
Revision History
Table 5 shows the revision history for this document.
Table 5. Document Revision History
Date and Document
Version
Changes Made
Summary of Changes
July 2007 v2.0
Rewrote introduction, removed the following sections
(and associated subsections) -- Set Up the Project,
Launch the DDR SDRAM Controller MegaCore
Function, Edit the Top- Level Design File, Add the
Constraints, Appendix. Replaced removed sections
with the following sections (sub sections not listed here,
see document) -- Design Details, Design
Considerations, DLL Resource Considerations, PLL
Resource Considerations, Instantiating DDR/DDR2
SDRAM Memory Controllers, RTL Code Modifications,
Quartus II Compilation, I/O Standard Assignments, I/O
Location Assignments, Running the DTW Script,
Compile the Design, DTW Timing Analysis, TroubleShooting, Conclusion.
Replaced all pictures with a new series of pictures.
—
August 2005 v1.0
Initial Release
—
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Technical Support:
www.altera.com/support/
Literature Services:
[email protected]
24
Preliminary
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arising out of the application or use of any information, product, or service described
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