- No category
Enpirion Power Datasheet EP53A8LQI/HQI 1A PowerSoC Voltage Mode Synchronous
Add to my manuals21 Pages
advertisement
Enpirion
®
Power Datasheet
EP53A8LQI/HQI 1A PowerSoC
Voltage Mode Synchronous
PWM Buck with Integrated Inductor
Description Features
The EP53A8LQI and EP53A8HQI are 1A PowerSoCs network. It enables a tiny solution footprint, low output
• Integrated Inductor Technology with integrated MOSFET switches, control,
• 3mm x 3mm x 1.1mm QFN Package compensation, and inductor in an advanced 3mm x
3mm QFN Package.
• Total Solution Footprint ~ 21mm
2
Integrated inductor ensures the complete power
• Low V
OUT
Ripple for IO Compatibility solution is fully characterized with the inductor
• High Efficiency, up to 94% carefully matched to the silicon and compensation
• V
OUT
Range 0.6V to V
IN
– 0.5V
• 1A Continuous Output Current ripple, low part-count, and high reliability, while maintaining high efficiency. The complete solution can be implemented in as little as 21mm
2
and operate from -40°C to 85°C ambient temperature range.
• 5 MHz Switching Frequency
• 3-pin VID for Glitch Free Voltage Scaling
The EP53A8xQI uses a 3-pin VID to easily select the
• Short Circuit and Over Current Protection output voltage setting. Output voltage settings are
• UVLO and Thermal Protection available in 2 optimized ranges providing coverage for typical V
OUT
settings.
• IC Level Reliability in a PowerSoC Solution
The VID pins can be changed on the fly for fast dynamic voltage scaling. EP53A8LQI further has the
Applications
• Portable Wireless and RF applications option to use an external voltage divider.
• Wireless Broad Band Data Cards
• Solid State Storage Applications
• Noise and Space Sensitive Applications
V
IN
4.7µF
0805
X7R
100
Ω
EP53A8xQI
PVIN VOUT
AVIN
ENABLE VSENSE
VS0
VS1
VS2
VFB
PGND AGND
V
OUT
10µF
0805
X7R
Efficiency vs. I
OUT
(V
IN
= 3.3V)
100
95
90
85
80
75
70
65
60
55
50
45
40
CONDITIONS
V
IN
= 3.3V
21mm
2
VOUT = 2.5V
0 0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
OUTPUT CURRENT (A)
Figure 2. Highest Efficiency in Smallest Solution Size Figure 1. Simplified Applications Circuit www.altera.com/enpirion
03651 July 15, 2015 Rev G
EP53A8LQI/EP53A8HQI
Ordering Information
Part Number
EP53A8LQI
EP53A8HQI
EVB-EP53A8xQI
Package Markings
AJXX
AMXX
T
A
(°C)
-40 to +85
-40 to +85
Package Description
16-pin (3mm x 3mm x 1.1mm) QFN
16-pin (3mm x 3mm x 1.1mm) QFN
QFN Evaluation Board
Packing and Marking Information
: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
16 15 16 15
NC(SW)
1
PGND
2
PGND
3
VFB
4
VSENSE
5
AGND
6
14
PVIN NC(SW)
1
PGND
2 13
AVIN
12
ENABLE
11
VS0
10
VS1
PGND
3
NC
4
VSENSE
5
9
VS2
AGND
6
7 8
14
PVIN
13
AVIN
12
ENABLE
11
VS0
10
VS1
9
VS2
7 8
Figure 3. EP53A8LQI Pin Out Diagram (Top View) Figure 4. EP53A8HQI Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN NAME FUNCTION
PIN NAME FUNCTION
1, 15, 16
2,3
4
5
6
7, 8
NC(SW)
NO CONNECT – These pins are internally connected to the common switching node of the internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage to the device.
PGND
VFB / NC
Power ground. Connect this pin to the ground electrode of the Input and output filter capacitors.
EP53A8LQI: Feedback pin for external divider option.
EP53A8HQI: No Connect
VSENSE Sense pin for preset output voltages. Refer to application section for proper configuration.
AGND
Analog ground. This is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider
VOUT Regulated Output Voltage. Refer to application section for proper layout and decoupling. www.altera.com/enpirion , Page 2
03651 July 15, 2015 Rev G
PIN
9, 10, 11
12
13
14
EP53A8LQA/EP53A8HQA
NAME FUNCTION
VS2,
VS1,
VS0
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
EP53A8LQI: Selects one of seven preset output voltages or an external resistor divider.
EP53A8HQI: Selects one of eight preset output voltages.
(Refer to section on output voltage select for more details.)
ENABLE Output Enable. Enable = logic high; Disable = logic low
AVIN Input power supply for the controller circuitry. Connect to PVIN through a 100 Ohm resistor.
PVIN Input Voltage for the MOSFET switches.
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
PARAMETER
Input Supply Voltage
Voltages on: ENABLE, V
SENSE
, V
SO
– V
S2
SYMBOL MIN MAX
V
IN
-0.3 6.0
-0.3 V
IN
+ 0.3
UNITS
V
V
Voltages on: V
FB
(EP53A8LQI)
Maximum Operating Junction Temperature
Storage Temperature Range
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C
ESD Rating (based on Human Body Mode)
T
J-ABS
T
STG
-0.3
-65
2.7
150
150
260
2000
V
°C
°C
°C
V
Recommended Operating Conditions
PARAMETER
Input Voltage Range
Operating Ambient Temperature
Operating Junction Temperature
SYMBOL MIN
V
IN
2.4
T
A
T
J
- 40
- 40
MAX
5.5
+85
+125
UNITS
V
°C
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient –0 LFM (Note 1)
Thermal Overload Trip Point
Thermal Overload Trip Point Hysteresis
SYMBOL
θ
JA
T
J-TP
TYP
80
+155
25
Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards.
UNITS
°C/W
°C
°C
Electrical Characteristics
NOTE: V
IN
=3.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at T
A
= 25°C.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Input
Voltage
V
IN
2.4 5.5 V
Under Voltage Lockout – V
IN
Rising
Under Voltage Lockout – V
IN
Falling
V
UVLO_R
V
UVLO_F
2.0
1.9
V
V www.altera.com/enpirion , Page 3
03651 July 15, 2015 Rev G
PARAMETER
Drop Out Resistance
SYMBOL
R
DO
TEST CONDITIONS
Input to Output Resistance
Output Voltage Range
V
OUT
EP53A8LQI (V
DO
= I
LOAD
X R
DO
)
EP53A8HQI
MIN TYP MAX UNITS
350 500 mΩ
0.6
1.8
EP53A8LQA/EP53A8HQA
Dynamic Voltage Slew
Rate
VID Preset V
Accuracy
OUT
Initial
VFB Pin Voltage (Load and Temperature)
V
∆V
V
SLEW
OUT
VFB
EP53A8HQI
EP53A8LQI
T
A
= 25
°C, V
IN
= 3.6V;
I
LOAD
= 100mA ;
0.8V ≤ V
OUT
≤ 3.3V
0A ≤ I
LOAD
≤ 1A
Starting Date Code: X501 or greater
Line Regulation
∆V
OUT_LINE
2.4V ≤ V
IN
≤ 5.5V; Load = 0A
Load Regulation
Temperature Variation
∆V
OUT_LOAD
0A ≤ I
LOAD
≤ 1A; V
IN
= 3.6V
∆V
OUT_TEMP
L
-40
° C ≤ T
A
≤ +85°C
Output Current Range I
OUT
Subject to de-rating
Shut-down Current
OCP Threshold I
I
SD
LIM
Enable = Low
2.4V ≤ V
0.6V ≤ V
IN
≤ 5.5V
OUT
≤ 3.3V
VS0-VS2, Pin Logic
Low
VS0-VS2, Pin Logic
High
VS0-VS2, Pin Input
Current
I
V
V
VSLO
VSHI
VSX
Note 1
Enable Pin Logic Low V
ENLO
Enable Pin Logic High V
ENHI
I
ENABLE
Enable Pin Current
Feedback Pin Input
Current
I
FB
Operating Frequency F
OSC
Soft Start Operation
Note 1
Note 1
Soft Start Slew Rate
Soft Start Rise Time
∆V
∆T
SS
SS
EP53A8HQI (VID only)
EP53A8LQI (VID only)
EP53A8LQI (VFB mode); Note 2
-2
0.588
0
1.25
0.0
1.4
1.4
170
Note 1: Parameter guaranteed by design and characterization.
Note 2: Measured from when V
IN
≥ V
UVLO_R
& ENABLE pin crosses its logic High threshold.
8
4
0.6
0.03
0.6
30
0.75
1.4
<100
<100
<100
5
8
4
225
V
IN
-V
DO
3.3
+2
0.612
1000
0.3
V
IN
0.4
280
V
V/ms
%
V
%/V
%/A ppm/
°C mA
µA
A
V
V nA
V
V nA nA
MHz
V/ms
µs www.altera.com/enpirion , Page 4
03651 July 15, 2015 Rev G
Typical Performance Curves
Efficiency vs. I
OUT
(V
IN
= 3.3V)
75
70
65
60
55
50
45
40
100
95
90
85
80
CONDITIONS
V
IN
= 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
0 0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
1.020
1.015
1.010
1.005
VIN = 5.0V
VIN = 3.3V
1.000
0.995
0.990
0.985
CONDITIONS
V
OUT
= 1.0V
0.980
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
1.520
1.515
1.510
1.505
1.500
1.495
VIN = 5.0V
VIN = 3.3V
1.490
1.485
CONDITIONS
V
OUT
= 1.5V
1.480
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
OUTPUT CURRENT (A)
EP53A8LQA/EP53A8HQA
Efficiency vs. I
OUT
(V
IN
= 5.0V)
95
90
85
80
75
70
65
60
55
50
45
40
35
CONDITIONS
V
IN
= 5V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
0 0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
1.220
1.215
1.210
1.205
VIN = 5.0V
VIN = 3.3V
1.200
1.195
1.190
1.185
CONDITIONS
V
OUT
= 1.2V
1.180
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
1.820
1.815
1.810
VIN = 5.0V
VIN = 3.3V
1.805
1.800
1.795
1.790
1.785
CONDITIONS
V
OUT
= 1.8V
1.780
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
OUTPUT CURRENT (A) www.altera.com/enpirion , Page 5
03651 July 15, 2015 Rev G
Typical Performance Curves (Continued)
Output Voltage vs. Output Current
2.520
2.515
2.510
2.505
VIN = 5.0V
VIN = 3.3V
2.500
2.495
2.490
2.485
CONDITIONS
V
OUT
= 2.5V
2.480
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
OUTPUT CURRENT (A)
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
2.5
Output Voltage vs. Input Voltage
3
LOAD = 0A
LOAD = 1A
CONDITIONS
V
OUT_NOM
= 1.0V
3.5
4 4.5
INPUT VOLTAGE (V)
5 5.5
1.520
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
2.5
Output Voltage vs. Input Voltage
3
LOAD = 0A
LOAD = 1A
CONDITIONS
V
OUT_NOM
= 1.5V
3.5
4 4.5
INPUT VOLTAGE (V)
5 5.5
EP53A8LQA/EP53A8HQA
Output Voltage vs. Output Current
3.320
3.315
3.310
3.305
3.300
3.295
3.290
3.285
VIN = 5.0V
CONDITIONS
V
OUT
= 3.3V
3.280
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
OUTPUT CURRENT (A)
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
2.5
Output Voltage vs. Input Voltage
3
LOAD = 0A
LOAD = 1A
CONDITIONS
V
OUT_NOM
= 1.2V
3.5
4 4.5
INPUT VOLTAGE (V)
5 5.5
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
2.5
Output Voltage vs. Input Voltage
3
LOAD = 0A
LOAD = 1A
CONDITIONS
V
OUT_NOM
= 1.8V
3.5
4 4.5
INPUT VOLTAGE (V)
5 5.5
www.altera.com/enpirion , Page 6
03651 July 15, 2015 Rev G
Typical Performance Curves (Continued)
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
3
Output Voltage vs. Input Voltage
3.5
LOAD = 0A
LOAD = 1A
CONDITIONS
V
OUT_NOM
= 2.5V
4 4.5
INPUT VOLTAGE (V)
5 5.5
Output Voltage vs. Temperature
1.030
1.020
CONDITIONS
V
IN
V
= 3.3V
OUT_NOM
= 1.0V
LOAD = 0A
LOAD = 1A
EP53A8LQA/EP53A8HQA
3.320
3.315
3.310
3.305
3.300
3.295
3.290
3.285
3.280
5
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 1A
5.1
CONDITIONS
V
OUT_NOM
= 3.3V
5.2
5.3
INPUT VOLTAGE (V)
5.4
5.5
Output Voltage vs. Temperature
1.030
1.020
CONDITIONS
V
IN
= 5.0V
V
OUT_NOM
= 1.0V
LOAD = 0A
LOAD = 1A
1.010
1.010
1.000
0.990
0.980
-40 -15 10 35 60
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
3.350
3.340
3.330
CONDITIONS
V
IN
V
= 5.0V
OUT_NOM
= 3.3V
LOAD = 0A
LOAD = 1A
85
3.320
3.310
3.300
3.290
3.280
-40 -15 10 35 60
AMBIENT TEMPERATURE (°C)
85
1.000
0.990
0.980
-40 -15 10 35 60
AMBIENT TEMPERATURE (°C)
85
Output Current De-rating
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VOUT = 1.0V
VOUT = 1.8V
VOUT = 2.5V
CONDITIONS
V
IN
T
θ
JMAX
JA
= 3.3V
= 125°C
= 80°C/W
No Air Flow
0.4
0.2
0.0
55 60 65 70 75 80 85 90 95 100 105
AMBIENT TEMPERATURE (°C) www.altera.com/enpirion , Page 7
03651 July 15, 2015 Rev G
Typical Performance Curves (Continued)
Output Current De-rating
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
VOUT = 1.0V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 5.0V
T
JMAX
= 125°C
θ
JA
= 80°C/W
No Air Flow
0.0
55 60 65 70 75 80 85 90 95 100 105
AMBIENT TEMPERATURE (°C)
EP53A8LQA/EP53A8HQA
www.altera.com/enpirion , Page 8
03651 July 15, 2015 Rev G
Typical Performance Characteristics
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5.0V
VOUT = 1.2V
IOUT = 1A
VOUT
(AC Coupled)
EP53A8LQA/EP53A8HQA
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 3.3V
IOUT = 1A
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1.2V
IOUT = 1A
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
IOUT = 1A
VOUT
(AC Coupled)
Enable Power Down Enable Power Up
ENABLE
ENABLE
CONDITIONS
VIN = 5.0V
VOUT = 3.3V
LOAD = 1A
VOUT
CONDITIONS
VIN = 5.0V
VOUT = 3.3V
LOAD = 1A
VOUT
www.altera.com/enpirion , Page 9
03651 July 15, 2015 Rev G
Typical Performance Characteristics (Continued)
Load Transient from 0 to 1A
EP53A8LQA/EP53A8HQA
Load Transient from 0 to 1A
CONDITIONS
VIN = 5V
VOUT = 1.2V
CONDITIONS
VIN = 5V
VOUT = 3.3V
VOUT
(AC Coupled)
VOUT
(AC Coupled)
LOAD
Load Transient from 0 to 1A
VOUT
(AC Coupled)
CONDITIONS
VIN = 3.7V
VOUT = 1.2V
LOAD
LOAD
Load Transient from 0 to 1A
VOUT
(AC Coupled)
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
LOAD
www.altera.com/enpirion , Page 10
03651 July 15, 2015 Rev G
Functional Block Diagram
EP53A8LQA/EP53A8HQA
PVIN
ENABLE
UVLO
Thermal Limit
Current Limit
Soft Start
(-)
(+)
PWM
Comp
Sawtooth
Generator
Logic
P-Drive
N-Drive
Compensation
Network
Error
Amp
(-)
(+)
Switch
DAC
VREF
Voltage
Select
AVIN AGND
Figure 5. Functional Block Diagram
VS0 VS1 VS2
Package Boundry
V
FB
NC(SW)
V
OUT
PGND
V
SENSE www.altera.com/enpirion , Page 11
03651 July 15, 2015 Rev G
Functional Description
Functional Overview
The EP53A8xQI requires only 2 small MLCC capacitors and an 0201 MLC resistor for a complete DC-DC converter solution. The device integrates MOSFET switches, PWM controller, Gate-drive, compensation, and inductor into a tiny 3mm x 3mm x 1.1mm QFN package. Advanced package design, along with the high level of integration, provides very low output ripple and noise. The EP53A8xQI uses voltage mode control for high noise immunity and load matching to advanced
≤90nm loads. A 3-pin VID allows the user to choose from one of 8 output voltage settings.
The EP53A8xQI comes with two VID output voltage ranges. The EP53A8HQI provides
V
OUT
settings from 1.8V to 3.3V, the
EP53A8LQI provides VID settings from 0.8V to
1.5V, and also has an external resistor divider option to program output setting over the 0.6V to V
IN
-0.5V range. The EP53A8xQI provides the industry’s highest power density of any 1A
DCDC converter solution.
The key enabler of this revolutionary integration is Altera’s proprietary power
MOSFET technology. The advanced MOSFET switches are implemented in deep-submicron
CMOS to supply very low switching loss at high switching frequencies and to allow a high level of integration. The semiconductor process allows seamless integration of all switching, control, and compensation circuitry.
The proprietary magnetics design provides high-density/high-value magnetics in a very small footprint. Altera Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range.
Protection features include under-voltage lockout (UVLO), over-current protection (OCP), short circuit protection, and thermal overload protection.
EP53A8LQA/EP53A8HQA
Integrated Inductor: Low-Noise Low-EMI
The EP53A8xQI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly simplifies the power supply design process. The inherent shielding and compact construction of the integrated inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board. Further, the package layout is optimized to reduce the electrical path length for the high di/dT input AC ripple currents that are a major source of radiated emissions from
DC-DC converters. The integrated inductor provides the optimal solution to the complexity, output ripple, and noise that plague low power
DCDC converter design.
Voltage Mode Control, High Bandwidth
The EP53A8xQI utilizes an integrated type III compensation network. Voltage mode control is inherently impedance matched to the sub
90nm process technology that is used in today’s advanced ICs. Voltage mode control also provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. The very high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance.
Soft Start
Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the “ENABLE” pin is asserted “high”. Digital control circuitry limits the V
OUT
ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor.
The EP53A8HQI has a soft-start slew rate that is twice that of the EP53A8LQI.
When the EP53A8LQI is configured in external resistor divider mode, the device has a fixed
VOUT ramp time. Therefore, the ramp rate will vary with the output voltage setting. Output voltage ramp time is given in the Electrical
Characteristics Table.
Excess bulk capacitance on the output of the device can cause an over-current condition at startup. Assuming no-load at startup, the www.altera.com/enpirion , Page 12
03651 July 15, 2015 Rev G
maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as:
EP53A8LQI:
C
OUT_TOTAL_MAX
= C
OUT_Filter
+ C
OUT_BULK
=
250uF
EP53A8HQI:
C
OUT_TOTAL_MAX
= C
OUT_Filter
+ C
OUT_BULK
=
125uF
EP53A8LQI (in external divider mode):
C
OUT_TOTAL_MAX
= 2.25x10
-4
/V
OUT
Farads
The nominal value for C
OUT
is 10uF. See the applications section for more details.
Over Current/Short Circuit Protection
The current limit function is achieved by sensing the current flowing through a sense P-
MOSFET which is compared to a reference current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on, pulling V
OUT
low. This condition is maintained for approximately 0.5mS and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat.
EP53A8LQA/EP53A8HQA
Under Voltage Lockout
During initial power up, an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states.
Enable
The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation.
NOTE: The ENABLE pin must not be left floating.
Thermal Shutdown
When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature, the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases by 25C°, the device will go through the normal startup process. www.altera.com/enpirion , Page 13
03651 July 15, 2015 Rev G
EP53A8LQA/EP53A8HQA
Application Information
V
IN
4.7µF
0805
X7R
100
Ω
EP53A8HQI
PVIN VOUT
AVIN
ENABLE
VS0
VSENSE
VS1
VS2
PGND AGND
V
OUT
10µF
0805
X7R
V
IN
4.7µF
0805
X7R
Figure 6. EP53A8HQI VID Application Circuit
100
Ω
EP53A8LQI
PVIN VOUT
AVIN
ENABLE
VS0
VSENSE
VS1
VFB
VS2
PGND AGND
V
OUT
10µF
0805
X7R
Figure 7. EP53A8LQI VID Application Circuit
Output Voltage Programming
The EP53A8xQI utilizes a 3-pin VID to program the output voltage value. The VID is available in two sets of output VID programming ranges.
The VID pins should be connected either to an external control signal, AVIN or to AGND to avoid noise coupling into the device.
The “Low” range is optimized for low voltage applications. It comes with preset VID settings ranging from 0.80V and 1.5V. This VID set also has an external divider option.
To specify this VID range, order part number
EP53A8LQI.
The “High” VID set provides output voltage settings ranging from 1.8V to 3.3V. This version does not have an external divider option. To specify this VID range, order part number EP53A8HQI.
Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected.
NOTE: The VID pins must not be left floating.
Table 1: EP53A8LQI VID Voltage Select Settings
VS2
0
0
1
1
0
0
1
1
VS1
0
0
0
1
1
1
0
1
VS0
0
1
1
0
0
1
0
1
VOUT
1.50
1.45
1.20
1.15
1.10
1.05
0.8
EXT
EP53A8L Low VID Range Programming
The EP53A8LQI is designed to provide a high degree of flexibility in powering applications that require low V
OUT
settings and dynamic voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to choose one of seven (7) preset output voltage settings, or the user can select an external voltage divider option. The VID pin settings can be changed on the fly to implement glitchfree voltage scaling.
Table 1 shows the VS2-VS0 pin logic states for
the EP53A8LQI and the associated output voltage levels. A logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate.
EP53A8LQI External Voltage Divider
The external divider option is chosen by connecting VID pins VS2-VS0 to V
IN
or a logic
“1” or “high”. The EP53A8LQI uses a separate www.altera.com/enpirion , Page 14
03651 July 15, 2015 Rev G
feedback pin, V
FB
, when using the external divider. V
SENSE
must be connected to V
OUT
as indicated in Figure 8.
The output voltage is selected by the following formula:
V
OUT
=
0 .
6
V
(
1
+
Ra
Rb
)
V
IN
4.7µF
0805
X7R
100
Ω
EP53A8LQI
PVIN VOUT
AVIN
VS0
VSENSE
VS1
VS2
VFB
ENABLE
PGND AGND
R
A
R
B
V
OUT
10µF
0805
X7R
Figure 8. EP53A8LQI External VOUT Setting
R a must be chosen as 237KΩ to maintain loop gain. Then R b
is given as:
R b
=
142
V
OUT
.
2
x
10
3
−
0 .
6
Ω
V
OUT
can be programmed over the range of
0.6V to (V
IN
– 0.5V).
NOTE: Dynamic Voltage Scaling is not allowed between internal preset voltages and external divider.
EP53A8HQI High VID Range
Programming
The EP53A8HQI V
OUT
settings are optimized for higher nominal voltages such as those required to power IO, RF, or IC memory. The preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage settings. The EP53A8HQI does not have an external divider option. As with the
EP53A8LQI, the VID pin settings can be changed while the device is enabled.
Table 2 shows the VS0-VS2 pin logic states for
the EP53A8HQI and the associated output voltage levels. A logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
EP53A8LQA/EP53A8HQA
pins can be either hardwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate.
These pins must not be left floating.
Table 2: EP53A8HQI VID Voltage Select Settings
VS2
0
1
1
1
0
1
0
0
0
1
1
0
1
VS1
0
0
1
1
0
1
0
1
VS0
0
1
0
VOUT
3.3
3.0
2.9
2.6
2.5
2.2
2.1
1.8
Power-Up/Down Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE) together during power up or power down meets these requirements
.
Pre-Bias Start-up
The EP53A8xQI supports startup into a prebiased output of up to 1.5V. The output of the
EP53A8xQI can be pre-biased with a voltage up to 1.5V when it is first enabled
.
Input Filter Capacitor
The input filter capacitor requirement is a
4.7µF 0603 low ESR MLCC capacitor. The input capacitor must use X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-mode DC-DC converter input filter applications.
Output Filter Capacitor
The output filter capacitor requirement is a minimum of 10µF 0805 MLCC. Ripple performance can be improved by using 2x10µF
0805 MLCC capacitors. www.altera.com/enpirion , Page 15
03651 July 15, 2015 Rev G
The maximum output filter capacitance next to the output pins of the device is 60µF low ESR
MLCC capacitance. V
OUT
has to be sensed at the last output filter capacitor next to the
EP53A8xQI.
Additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient separation between the V
OUT
Sense point and the bulk capacitance. The separation provides an inductance that isolates the control loop from the bulk capacitance.
Excess total capacitance on the output (Output
Filter + Bulk) can cause an over-current
EP53A8LQA/EP53A8HQA
condition at startup. Refer to the section on
Soft-Start for the maximum total capacitance on the output.
The output capacitor must use X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DC-DC converter output filter applications. www.altera.com/enpirion , Page 16
03651 July 15, 2015 Rev G
Thermal Considerations
Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. The Enpirion
PowerSoC helps alleviate some of those concerns.
The Enpirion EP53A8xQI DC-DC converter is packaged in a 3x3x1.1mm 16-pin QFN package.
The recommended maximum junction temperature for continuous operation is 125°C. Continuous operation above 125°C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of
155°C.
The following example and calculations illustrate the thermal performance of the EP53A8xQI.
Example:
V
IN
= 5V
V
OUT
= 3.3V
I
OUT
= 1A
First calculate the output power.
P
OUT
= 3.3V x 1A = 3.3W
Next, determine the input power based on the efficiency (η) shown in Figure 9.
Efficiency vs. I
OUT
(V
IN
= 5.0V)
95
90
85
80
75
70
65
60
55
50
45
40
35
CONDITIONS
V
IN
= 5V
86.5%
VOUT = 3.3V
0 0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
OUTPUT CURRENT (A)
Figure 9. Efficiency vs. Output Current
For V
IN
= 5V, V
OUT
= 3.3V at 1A
, η ≈ 86.5%
η = P
OUT
/ P
IN
= 86.5% = 0.865
P
IN
= P
OUT
/ η
EP53A8LQA/EP53A8HQA
P
IN
≈ 3.3W / 0.865 ≈ 3.815W
The power dissipation (P
D
) is the power loss in the system and can be calculated by subtracting the output power from the input power.
P
D
= P
IN
– P
OUT
≈ 3.815W – 3.3W ≈ 0.515W
With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (θ
JA
). The θ
JA
parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EP53A8xQI has a θ
JA
value of 80 ºC/W without airflow.
Determine the change in temperature (ΔT) based on P
D and θ
JA
.
ΔT = P
D x θ
JA
ΔT ≈ 0.515W x 80°C/W = 41.2°C ≈ 41°C
The junction temperature (T
J
) of the device is approximately the ambient temperature (T
A
) plus the change in temperature. We assume the initial ambient temperature to be 25°C.
T
J
= T
A
+ ΔT
T
J
≈ 25°C + 41°C ≈ 66°C
The maximum operating junction temperature
(T
JMAX
) of the device is 125°C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (T
AMAX
) allowed can be calculated.
T
AMAX
= T
JMAX
– P
D x θ
JA
≈ 125°C – 41°C ≈ 84°C
The maximum ambient temperature (before derating) the device can reach is 84°C given the input and output conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. www.altera.com/enpirion , Page 17
03651 July 15, 2015 Rev G
Layout Recommendations
Figure 10 shows critical components and layer
1 traces of a recommended minimum footprint
EP53A8LQI/EP53A8HQI layout with ENABLE tied to V
IN
. Alternate ENABLE configurations, and other small signal pins need to be connected and routed according to specific customer application. Please see the Gerber files on the Altera website www.altera.com/enpirion for exact dimensions and other layers. Please refer to
Figure 10 while reading the layout recommendations in this section.
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EP53A8xQI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EP53A8xQI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: Input and output grounds are separated until they connect at the PGND pins. The separation shown on Figure 10 between the input and output GND circuits helps minimize noise coupling between the converter input and output switching loops.
Recommendation 3: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors.
Please see the Gerber files on the Altera website www.altera.com/enpirion .
EP53A8LQA/EP53A8HQA
Figure 10. Top PCB Layer Critical Components and Copper for Minimum Footprint
Recommendation 4: Multiple small vias should be used to connect the ground traces under the device to the system ground plane on another layer for heat dissipation. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. It is preferred to put these vias under the capacitors along the edge of the
GND copper closest to the +V copper. Please see Figure 10. These vias connect the input/output filter capacitors to the GND plane and help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under C
IN
and C
OUT
, then put them just outside the capacitors along the
GND. Do not use thermal reliefs or spokes to connect these vias to the ground plane.
Recommendation 5: AVIN is the power supply for the internal small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 10 this connection is made with RAVIN at the input capacitor close to the V
IN
connection. www.altera.com/enpirion , Page 18
03651 July 15, 2015 Rev G
Recommended PCB Footprint
EP53A8LQA/EP53A8HQA
Figure 11. EP53A8xQI PCB Footprint (Top View) www.altera.com/enpirion , Page 19
03651 July 15, 2015 Rev G
Package and Mechanical
EP53A8LQA/EP53A8HQA
Figure 12. EP53A8LQI Package Dimensions (Bottom View) www.altera.com/enpirion , Page 20
03651 July 15, 2015 Rev G
EP53A8LQA/EP53A8HQA
Figure 13. EP53A8HQI Package Dimensions (Bottom View)
Packing and Marking Information
: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000 www.altera.com
© 2014 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com/enpirion , Page 21
03651 July 15, 2015 Rev G
advertisement
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Related manuals
advertisement
Table of contents
- 12 Functional Overview
- 12 Integrated Inductor: Low-Noise Low-EMI
- 12 Voltage Mode Control, High Bandwidth
- 12 Soft Start
- 13 Over Current/Short Circuit Protection
- 13 Under Voltage Lockout
- 13 Enable
- 13 Thermal Shutdown
- 14 Output Voltage Programming
- 14 EP53A8L Low VID Range Programming
- 14 EP53A8LQI External Voltage Divider
- 15 EP53A8HQI High VID Range Programming
- 15 Power-Up/Down Sequencing
- 15 During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. Tying PVIN and AVIN o...
- 15 Pre-Bias Start-up
- 15 Input Filter Capacitor
- 15 Output Filter Capacitor