steval-ime009v1 schematic

steval-ime009v1 schematic
5
4
3
2
1
DVDD VDDP HVP0 HVPCW
DATAOUT[0:15]
MCU_FPGA_PROG
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
FPGA_MCU_AWAKE
MCU_FPGA_SUSPEND
FLASH_C
FLASH_DQ0
FLASH_DQ1
FLASH_DQ2
FLASH_DQ3
FLASH_nS
FPGA_SPI_CCLK
FPGA_SPI_MOSI
FPGA_SPI_MISO1
FPGA_SPI_MISO2
FPGA_SPI_MISO3
FPGA_SPI_SEL
STM32_FLASH
+VFPGA_IO_3V3
USB_DP
USB_DM
USB_DISCONNECT
MCU_3V3
FLASH_3V3
MCU_FPGA_PROG
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
FPGA_MCU_AWAKE
MCU_FPGA_SUSPEND
+VFPGA_CORE_1V2
D
C
MCU_FPGA_GPIO[0:7]
DATAOUT[0:15]
DATAOUT2
DATAOUT3
THSD_EN
DATAOUT4
DATAOUT5
CK
DATAOUT6
DATAOUT7
CW
DATAOUT8
DATAOUT9
DATAOUT10
DATAOUT11
DATAOUT12
DATAOUT13
DATAOUT14
DATAOUT15
FPGA
IN1_0
IN1_1
HVP_CW
FPGA_GPIO[0:7]
DATAOUT0
DATAOUT1
HVP
MCU_FPGA_GPIO[0:7]
STHV800_BLK
VDDP
FPGA_BLK
DVDD
STM32_FLASH_BLK
IN2_0
IN2_1
D
IN3_0
IN3_1
IN4_0
IN4_1
IN5_0
IN5_1
IN6_0
IN6_1
IN7_0
IN7_1
C
IN8_0
IN8_1
DVDD VDDP VDDM HVP0 HVM0 HVPCW HVMCW
BOARD_POWER_BLK
HVMCW
+VFPGA_CORE_1V2
HVM
CW
HVM_CW
CK
VDDM
HVPCW
HVM0
HVP0
VDDM
VDDP
DVDD
USB_DP
USB_DM
USB_DISCONNECT
MCU_3V3
FLASH_3V3
THSD_EN
STHV800
B
B
+VFPGA_IO_3V3
VDDM
BOARD_POWER
HVM0
HVMCW
A
A
Title
STEVAL-IME009V1 STMicroelectronics
Size
Document Number
Custom STHV800 Ultrasould Pulser
Date:
5
4
3
Wednesday, June 18, 2014
2
Rev
1.02
Sheet
1
of
1
9
4
3
VBUS
DM
DP
4
5
6
7
8
9
D
R1
1M
2
3
USBDM
ID nc
GND
SHELL
SHELL
SHELL
SHELL
Grd 3.3V
D2
D3
J1
5
USB_DISCONNECT
4
DM
HVPCW 1
HVP0 2
3
HVPCW
HVP0
22000n 100V
USBUF02W6
USB_DISCONNECT
USBDM
USBDP
C3
4.7nF
USB_DISCONNECT
USB_DM
USB_DP
100V
DVDD
VDDP
DVDD
VDDP
C8 Details:
DigiKey (478-2552-2-ND) - AVX (TACL225M006XTA)
Package 0603
VDDM
16V
C7
1uF
3
C11
33nF
5
USB_3V3
GND
VOUT
J3
HVMCW
HVM0
3.3V Power Management
2
FLASH_3V3
3
EXT_3V3
4
SW1 Details:
SW1
RS 711-8329
KNITTER-SWITCH (MMS228T)
ON_1a
ON_1b
COM_1a
COM_1b
ON_2a
ON_2b
nc
nc
8
7
R124
56 D27
RED
FLASH_3V3
6
4
R125 56
Vin
SW
RED
C13
4u7
6.3V
EN
FB/Vo
ST1S12xx
GND
C12
4u7
6.3V
L1
2.2uH
3
+VFPGA_CORE_1V2
R2
R123
0
0
FPGA
D28
D1
SM2T3V3A
B
C4, C5, C6 Details:
Digikey (445-1436-2-ND) - TDK (C3225X5R1C226M)
Package 1210 - EIA 3225
1
3V3 Connector
J3 Details:
22000n 100V RS (193-0570)
Phoenix Contact
(Mfg Code MKDS 1.5/3-5.08)
C1, C2, C9, C10 Details:
Digikey (445-5217-2-ND) - TDK (CKG57NX7S2A226M)
Package 6.5mm x 5.5 mm
5
DVDD
1
2
NOT ASSEMBLY
HVMCW
HVM0
GND
5
C14
10u
10V
GND_POWER
GND_SHIELD
2
1
2
J41
1
2
3
GND_POWER
MMS228T
EXT_3V3
HVM
C10
MCU_3V3
MCU
+VFPGA_IO_3V3
C9
100V
100V
U3
J4
C
GND_POWER
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
D26
RED
HVMCW
HVM0
1
DVDD
VDDP
GND
VDDM
J2 Details
RS 2X(193-0564)
22000n 16V Phoenix Contact
(Mfg Code
16V
MKDS 1.5/2-5.08)
16V
22000n 100V
USB_3V3
1
2
3
4
USB ON
C8
2.2uF 6.3V
SOT23-5L
LV
C4
R90 56R
2
BYPS
VIN
4
1
C6
22000n 16V 22000n 16V
LDS3985M33R
INH
C
D
J1 Details
22000n 100V RS (193-0570)
100V
Phoenix Contact
(Mfg Code MKDS 1.5/3-5.08)
J2
C5
3V3
C2
VDDM
U2
HVPCW
HVP0
GND
GND_POWER
USB_5V
B
C1
C7 Details:
Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K)
Package 0402
RS (515-1995)
Molex (54819-0572)
HVP
- HIGH VOLTAGE
DM
DP
STHV800 Power Management
U1 SOTT323-6L
6 DP
1
D1
D4
USBDP
USB_miniB
CN1
1
2
3
1
+ HIGH VOLTAGE
USB
USB_5V
2
LOW POWER
5
A
A
J4 Details
Phoenix Contact (Mfg Code MPT 0.5/2-2.54)
RS (220-4260)
C12 and C13 Detail
TDK (C1608X5R0J475K) - Digikey (445-5178-2-ND)
Dimension 0603 - EIA 1608
C14 Detail
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
L1 Detail
TDK (VLF4012AT-2R2M1R5) - RS (614-3147)
Title
STEVAL-IME009V1 STMicroelectronics
Size
A
Date:
5
4
3
Document Number
STHV800 Demonstration Board
Tuesday, June 10, 2014
2
Rev
1.02
Sheet
2
of
1
9
5
4
D
3
2
1
D
+VFPGA_IO_3V3
U4A
R3
10K 0402
FPGA - Bank 0
J5
IO_0_L01N_VREF
IO_0_L01P_HSWAPEN
IO_0_L02N
IO_0_L02P
IO_0_L03N
IO_0_L03P
IO_0_L04N
IO_0_L04P
IO_0_L05N
IO_0_L05P
IO_0_L06N
IO_0_L06P
IO_0_L07N
IO_0_L07P
IO_0_L08N_VREF
IO_0_L08P
IO_0_L09N
IO_0_L09P
IO_0_L10N
IO_0_L10P
IO_0_L11N
IO_0_L11P
IO_0_L32N
IO_0_L32P
IO_0_L33N
IO_0_L33P
IO_0_L34N_GCLK18
IO_0_L34P_GCLK19
IO_0_L35N_GCLK16
IO_0_L35P_GCLK17
IO_0_L36N_GCLK14
IO_0_L36P_GCLK15
IO_0_L37N_GCLK12
IO_0_L37P_GCLK13
IO_0_L38N_VREF
IO_0_L38P
IO_0_L39N
IO_0_L39P
IO_0_L40N
IO_0_L40P
IO_0_L41N
IO_0_L41P
IO_0_L42N
IO_0_L42P
IO_0_L47N
IO_0_L47P
IO_0_L50N
IO_0_L50P
IO_0_L51N
IO_0_L51P
IO_0_L62N_VREF
IO_0_L62P
IO_0_L63N_SCP6
IO_0_L63P_SCP7
IO_0_L64N_SCP4
IO_0_L64P_SCP5
IO_0_L65N_SCP2
IO_0_L65P_SCP3
IO_0_L66N_SCP0
IO_0_L66P_SCP1
C
B
C4
D4
A2
B2
C6
D6
A3
B3
A4
B4
A5
C5
E6
F7
A6
B6
E8
E7
A7
C7
C8
D8
F8
G8
A8
B8
C9
D9
A9
B9
C11
D11
A10
C10
F9
G9
A11
B11
F10
G11
A12
B12
E11
F11
C12
D12
A13
C13
E12
F12
A14
B14
E13
F13
A15
C15
C14
D14
A16
B16
THSD_EN
HSWAPEN
Diff. pair
DATAOUT3
Diff. pair
DATAOUT4
Diff. pair
DATAOUT2
Diff. pair
DATAOUT1
Diff. pair
DATAOUT0
Diff. pair
DATAOUT5
Diff. pair
DATAOUT6
Diff. pair
DATAOUT7
Diff. pair
CK
THSD_EN
NOT ASSEMBLY
1
2
Jumper J5 is used to control I/O pullups during FPGA configuration.
Open (default) to float I/O output during FPGA configuration.
Set jumper 1:2 to enable I/O pullups during FPGA configuration.
JUMPER
HSWAPEN
J6
+VFPGA_IO_3V3
C15
100n 0402
C16
10uF 10V 0805
CK
CW
DATAOUT0
DATAOUT1
CK
DATAOUT[0:15]
DATAOUT9
DATAOUT13
DATAOUT10
DATAOUT14
DATAOUT6
DATAOUT15
DATAOUT7
DATAOUT8
DATAOUT5
DATAOUT11
THSD_EN
DATAOUT4
DATAOUT[0:15]
CW
C16 and C17 Details:
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
NOT ASSEMBLY
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
+VFPGA_IO_3V3
C
DATAOUT2
C17
10uF 10V 0805
C18
100n 0402
DATAOUT12
DATAOUT3
HEADER 17X2
STHV748 I/O CONNECTOR
Diff. pair
DATAOUT8
Diff. pair
DATAOUT9
Diff. pair
DATAOUT10
Diff. pair
DATAOUT11
Diff. pair
DATAOUT12
Diff. pair
DATAOUT13
Diff. pair
DATAOUT14
Diff. pair
DATAOUT15
Diff. pair
CW
IDLE_STATE0
IDLE_STATE1
HI_Z
B
Jumpers J35, J36 and J37 are used to set dataout output state.
+VFPGA_IO_3V3
Configure J35 and J36 to setup outputs idle state as follows:
00 - (J35 and J36 open) --> High-Z (default)
01 - (J35 closed and J36 open) --> Clamp/HVR_SW
11 - (J35 and J36 closed) --> High-Z
10 - (J35 open and J36 closed) --> Clamp
IDLE STATE
J35 1
J36 1
J37 1
2
2
2
Open J37 (default) to connect FPGA outputs
Close J37 to disconnect outputs (High-Z)
NOT ASSEMBLY
THESE JUMPERS
R120
10K 0402
R121
10K 0402
R122
10K 0402
FPGA DISCONNECT
A
A
XC6SLX16-2CSG324C
Title
STEVAL-IME0009V1 STMicroelectronics
Size
B
Date:
5
4
3
2
Document Number
STHV800 Demonstration Board
Wednesday, June 18, 2014
Rev
1.02
Sheet
1
3
of
9
5
4
3
2
66MHZ EXTERNAL OSCILLATOR
When using backup oscillator X1,
R126 have to be unmounted and R6
must be placed.
1
PUSHBUTTONS
+VFPGA_IO_3V3
+VFPGA_IO_3V3
+VFPGA_IO_3V3
R4
10K 0402
D
U4B
FPGA - Bank 1
B
IO_1_L01N_A24_VREF
IO_1_L01P_A25
IO_1_L29N_A22_M1A14
IO_1_L29P_A23_M1A13
IO_1_L30N_A20_M1A11
IO_1_L30P_A21_M1RESET
IO_1_L31N_A18_M1A12
IO_1_L31P_A19_M1CKE
IO_1_L32N_A16_M1A9
IO_1_L32P_A17_M1A8
IO_1_L33N_A14_M1A4
IO_1_L33P_A15_M1A10
IO_1_L34N_A12_M1BA2
IO_1_L34P_A13_M1WE
IO_1_L35N_A10_M1A2
IO_1_L35P_A11_M1A7
IO_1_L36N_A8_M1BA1
IO_1_L36P_A9_M1BA0
IO_1_L37N_A6_M1A1
IO_1_L37P_A7_M1A0
IO_1_L38N_A4_M1CLKN
IO_1_L38P_A5_M1CLK
IO_1_L39N_M1ODT
IO_1_L39P_M1A3
IO_1_L40N_GCLK10_M1A6
IO_1_L40P_GCLK11_M1A5
IO_1_L41N_GCLK8_M1CASN
IO_1_L41P_GCLK9_IRDY1_M1RASN
IO_1_L42N_GCLK6_TRDY1_M1LDM
IO_1_L42P_GCLK7_M1UDM
IO_1_L43N_GCLK4_M1DQ5
IO_1_L43P_GCLK5_M1DQ4
IO_1_L44N_A2_M1DQ7
IO_1_L44P_A3_M1DQ6
IO_1_L45N_A0_M1LDQSN
IO_1_L45P_A1_M1LDQS
IO_1_L46N_FOE_B_M1DQ3
IO_1_L46P_FCS_B_M1DQ2
IO_1_L47N_LDC_M1DQ1
IO_1_L47P_FWE_B_M1DQ0
IO_1_L48N_M1DQ9
IO_1_L48P_HDC_M1DQ8
IO_1_L49N_M1DQ11
IO_1_L49P_M1DQ10
IO_1_L50N_M1UDQSN
IO_1_L50P_M1UDQS
IO_1_L51N_M1DQ13
IO_1_L51P_M1DQ12
IO_1_L52N_M1DQ15
IO_1_L52P_M1DQ14
IO_1_L53N_VREF
IO_1_L53P
IO_1_L61N
IO_1_L61P
IO_1_L74N_DOUT_BUSY
IO_1_L74P_AWAKE
F16
F15
C18
C17
G14
F14
D18
D17
G13
H12
E18
E16
K13
K12
F18
F17
H14
H13
H16
H15
G18
G16
K14
J13
L13
L12
K16
K15
L16
L15
H18
H17
J18
J16
K18
K17
L18
L17
M18
M16
N18
N17
P18
P17
N16
N15
T18
T17
U18
U17
N14
M14
M13
L14
P16
P15
FPGA_PMOD1_P2
FPGA_PMOD1_P1
FPGA_PMOD1_P4
FPGA_PMOD1_P3
FPGA_PMOD1_P8
FPGA_PMOD1_P7
FPGA_PMOD1_P10
FPGA_PMOD1_P9
FPGA_PMOD2_P2
FPGA_PMOD2_P1
FPGA_PMOD2_P4
FPGA_PMOD2_P3
FPGA_PMOD2_P8
FPGA_PMOD2_P7
FPGA_PMOD2_P10
FPGA_PMOD2_P9
OE ST
VCC
GND
OUT
4
2
3
2
SEL_PROG_PB
START_PB
SW PUSHBUTTON-DPST
SW PUSHBUTTON-DPST
C22
100nF SW3
PROGRAM
D
START
U5
X1
1
C20
10nF
C21
100nF SW2
BACKUP OF U5
MCU_FPGA_OSC_EN
3
7
8
R7
1
FPGA_CLK_66MHZ
VCC
PDN
MCU_FPGA_OSC_EN
6
VCC
n/c
n/c
GND
OUT
GND
R6
10K NM
4
+VFPGA_IO_3V3
+VFPGA_IO_3V3
5
SW PUSHBUTTON-DPST
R8
10K 0402
33R2
SW5
FPGA RESET
DS1088LU-66
Place R7 (1%) close to the clock
source DS1088LU-66 device
66MHZ OSC
STOP_PB
FPGA_RESET
SW PUSHBUTTON-DPST
C
CTRL_LED1
CTRL_LED0
SEL_PROG_PB
FPGA_CLK_66MHZ
START_PB
C23
100nF SW4
C24
100nF
STOP
R9
10K 0402
PERIPHERRAL MODULE (PMOD)
+VFPGA_IO_3V3
STOP_PB
FPGA USER I/O
FPGA_RESET
J7
+VFPGA_IO_3V3
SW2, SW3, SW4, Details RS (378-6527)
FPGA_USER_IO_0
FPGA_USER_IO_1
FPGA_USER_IO_2
FPGA_USER_IO_3
FPGA_USER_IO_4
FPGA_USER_IO_5
FPGA_USER_IO_6
FPGA_USER_IO_7
FPGA_USER_IO_8
FPGA_USER_IO_9
FPGA_USER_IO_10
FPGA_USER_IO_11
FPGA_USER_IO_12
FPGA_USER_IO_13
FPGA_USER_IO_14
FPGA_USER_IO_15
CTRL_LED3
CTRL_LED2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
NOT ASSEMBLY
C25
100nF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
J8
FPGA_PMOD1_P1
FPGA_PMOD1_P3
FPGA_PMOD1_P7
FPGA_PMOD1_P9
FPGA_DOUT_BUSY
FPGA_AWAKE
C27
C28
100nF
10uF 10V 0805
1
3
5
7
9
11
CTRL LED
NOT ASSEMBLY
SX
2
4
6
8
10
12
FPGA_PMOD1_P2
FPGA_PMOD1_P4
R10
D2
CTRL_LED0
Near START button
FPGA_PMOD1_P8
FPGA_PMOD1_P10
56R 0402
GREEN
B
R11
D3
CTRL_LED1
C26, C27, C30 and C31 Detail
HEADER 6X2 TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
HEADER 16X2
TP1
TEST POINT
C26
10uF 10V 0805
PMOD1
1
C
C19
100nF
R126
10k
R5
10K 0402
Near STOP button
56R 0402
R12
+VFPGA_IO_3V3
IDLE state signal
56R 0402
C30
10uF 10V 0805
C31
10uF 10V 0805
D4
CTRL_LED2
+VFPGA_IO_3V3
FPGA_MCU_AWAKE
C29
100nF
GREEN
C32
100nF
R13
GREEN
IDLE
D5
ERROR signal
CTRL_LED3
XC6SLX16-2CSG324C
56R 0402
RED
ERROR
PMOD2
J9
FPGA_PMOD2_P1
FPGA_PMOD2_P3
A
Two right-angle, 12-pin (2 x 6 female) Peripheral
Module (PMOD) headers (J8, J9) are interfaced to the
FPGA, with each header providing 3.3 V power, ground,
and eight I/O's. These headers may be utilized as
general-purpose I/Os or may be used to interface to
PMODs. J6 and J8 are placed in close proximity (0'9"
-centers) on the PCB in order to support dual PMODs.
FPGA_PMOD2_P7
FPGA_PMOD2_P9
1
3
5
7
9
11
NOT ASSEMBLY
DX
2
4
6
8
10
12
FPGA_PMOD2_P2
FPGA_PMOD2_P4
RED LED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
GREEN LED
Kingbright KP2012SURC
RS: 466-3778
Farnell: 8529906
LED 0805
A
FPGA_PMOD2_P8
FPGA_PMOD2_P10
Title
STEVAL-IME009V1 STMicroelectronics
HEADER 6X2
Size
B
Date:
5
4
3
2
Document Number
STHV800 Demonstration Board
Wednesday, June 18, 2014
Rev
1.02
Sheet
1
4
of
9
5
4
3
2
PROGRAM SELECTOR LEDS
FPGA CONFIGURATION
U4C
1
FPGA - Bank 2
B
R17
2K43 0402
FPGA_SPI_MISO3
FPGA_SPI_MISO2
D7
PROG_LED8
YELLOW
R18
2K43 0402 DNP
MCU_FPGA_INIT_B
PROG 9
R20
D8
PROG_LED1
D9
PROG_LED9
YELLOW
68R 0402
MCU_FPGA_MODE1
FPGA_MODE1
YELLOW
68R 0402
PROG 10
PROG 2
R21
2K43 0402 DNP
R22
2K43 0402
R23
R24
D10
PROG_LED2
D11
PROG_LED10
68R 0402
68R 0402
YELLOW
YELLOW
PROG 11
PROG 3
R25
R26
D12
PROG_LED3
Configuration mode selection:
FPGA_MODE0 = Parallel (Low) or Serial (High)
FPGA_MODE1 = Master (Low) or Slave (High)
TP2
TEST POINT
YELLOW
68R 0402
YELLOW
PROG 12
PROG 4
R27
R28
D14
PROG_LED4
D15
PROG_LED12
68R 0402
YELLOW
68R 0402
PROG 13
R30
D16
PROG_LED5
D17
PROG_LED13
68R 0402
68R 0402
YELLOW
YELLOW
PROG 14
PROG 6
R31
R32
D18
PROG_LED6
SPI FLASH CTRL SIGNALS
C
YELLOW
PROG 5
R29
PROG_LED14
PROG_LED15
MCU_FPGA_GPIO6
MCU_FPGA_GPIO7
MCU_FPGA_GPIO4
MCU_FPGA_GPIO5
PROG_LED12
PROG_LED13
MCU_FPGA_GPIO2
MCU_FPGA_GPIO3
MCU_FPGA_GPIO0
MCU_FPGA_GPIO1
PROG_LED10
PROG_LED11
PROG_LED2
PROG_LED3
PROG_LED6
PROG_LED7
PROG_LED0
PROG_LED1
PROG_LED4
PROG_LED5
PROG_LED8
PROG_LED9
FPGA_SPI_SEL
FPGA_INIT_B
D13
PROG_LED11
68R 0402
When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory is
being cleared.
When held Low, the start of configuration is delayed.
During configuration, a Low on this output indicates that a configuration data
error has occurred.
D
YELLOW
68R 0402
PROG 1
R19
FPGA_INIT_B
FPGA_MODE0
FPGA_MODE1
D19
PROG_LED14
68R 0402
YELLOW
68R 0402
YELLOW
PROG 15
PROG 7
R33
R34
D20
PROG_LED7
D21
PROG_LED15
Place R38 close to the FPGA device
68R 0402
R38
TO CORRECT
J10
68R 0402
YELLOW
YELLOW
33R2 0402
CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
Kingbright KP-3216SYC
RS: 466-3942
LED 0805
FPGA_SPI_CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
MCU_FPGA_PROG
+VFPGA_IO_3V3
1
2
3
4
5
6
7
8
9
10
B
R39
NA 0402
C33
10uF 10V 0805
CON10 R127
56
MCU_FPGA_GPIO0
MCU_FPGA_GPIO1
MCU_FPGA_GPIO2
MCU_FPGA_GPIO3
MCU_FPGA_GPIO4
MCU_FPGA_GPIO5
MCU_FPGA_GPIO6
MCU_FPGA_GPIO7
C34
100nF
R40
NA 0402
EXT SPI
FLASH
D29
Place D29
close to J10
MCU_FPGA_GPIO[0:7]
GREEN
C33 Details:
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
A
Title
MCU_FPGA_GPIO[0:7]
STEVAL-IME009V1 STMicroelectronics
Size
B
Date:
5
R15
D6
68R 0402
R16
10K 0402
XC6SLX16-2CSG324C
A
R14
PROG_LED0
FPGA_SPI_MOSI
FPGA_SPI_MISO1
PROG 8
PROG 0
+VFPGA_IO_3V3
FPGA_MODE0
CCLK
SPI EXTERNAL PROGRAMMING HEADER
C
T15
R15
V16
U16
T13
R13
V15
U15
V14
T14
P12
N12
V13
U13
N11
M11
T11
R11
V12
T12
P11
N10
N9
M10
V11
U11
T10
R10
V10
U10
T8
R8
V9
T9
N8
M8
V8
U8
V7
U7
P8
N7
V6
T6
T7
R7
P7
N6
T5
R5
V5
U5
T3
R3
V4
T4
P6
N5
V3
U3
1
D
IO_2_L01N_M0_CMPMISO
IO_2_L01P_CCLK
IO_2_L02N_CMPMOSI
IO_2_L02P_CMPCLK
IO_2_L03N_MOSI_CSI_B_MISO0
IO_2_L03P_D0_DIN_MISO_MISO1
IO_2_L05N
IO_2_L05P
IO_2_L12N_D2_MISO3
IO_2_L12P_D1_MISO2
IO_2_L13N_D10
IO_2_L13P_M1
IO_2_L14N_D12
IO_2_L14P_D11
IO_2_L15N
IO_2_L15P
IO_2_L16N_VREF
IO_2_L16P
IO_2_L19N
IO_2_L19P
IO_2_L20N
IO_2_L20P
IO_2_L22N
IO_2_L22P
IO_2_L23N
IO_2_L23P
IO_2_L29N_GCLK2
IO_2_L29P_GCLK3
IO_2_L30N_GCLK0_USERCCLK
IO_2_L30P_GCLK1_D13
IO_2_L31N_GCLK30_D15
IO_2_L31P_GCLK31_D14
IO_2_L32N_GCLK28
IO_2_L32P_GCLK29
IO_2_L40N
IO_2_L40P
IO_2_L41N_VREF
IO_2_L41P
IO_2_L43N
IO_2_L43P
IO_2_L44N
IO_2_L44P
IO_2_L45N
IO_2_L45P
IO_2_L46N
IO_2_L46P
IO_2_L47N
IO_2_L47P
IO_2_L48N_RDWR_B_VREF
IO_2_L48P_D7
IO_2_L49N_D4
IO_2_L49P_D3
IO_2_L62N_D6
IO_2_L62P_D5
IO_2_L63N
IO_2_L63P
IO_2_L64N_D9
IO_2_L64P_D8
IO_2_L65N_CSO_B
IO_2_L65P_INIT_B
4
3
2
Document Number
STHV800 Demonstration Board
Wednesday, June 18, 2014
Rev
1.02
Sheet
1
5
of
9
5
D
4
3
2
1
D
U4D
FPGA - Bank 3
C
B
IO_3_L01N_VREF
IO_3_L01P
IO_3_L02N
IO_3_L02P
IO_3_L31N_VREF
IO_3_L31P
IO_3_L32N_M3DQ15
IO_3_L32P_M3DQ14
IO_3_L33N_M3DQ13
IO_3_L33P_M3DQ12
IO_3_L34N_M3UDQSN
IO_3_L34P_M3UDQS
IO_3_L35N_M3DQ11
IO_3_L35P_M3DQ10
IO_3_L36N_M3DQ9
IO_3_L36P_M3DQ8
IO_3_L37N_M3DQ1
IO_3_L37P_M3DQ0
IO_3_L38N_M3DQ3
IO_3_L38P_M3DQ2
IO_3_L39N_M3LDQSN
IO_3_L39P_M3LDQS
IO_3_L40N_M3DQ7
IO_3_L40P_M3DQ6
IO_3_L41N_GCLK26_M3DQ5
IO_3_L41P_GCLK27_M3DQ4
IO_3_L42N_GCLK24_M3LDM
IO_3_L42P_GCLK25_TRDY2_M3UDM
IO_3_L43N_GCLK22_IRDY2_M3CASN
IO_3_L43P_GCLK23_M3RASN
IO_3_L44N_GCLK20_M3A6
IO_3_L44P_GCLK21_M3A5
IO_3_L45N_M3ODT
IO_3_L45P_M3A3
IO_3_L46N_M3CLKN
IO_3_L46P_M3CLK
IO_3_L47N_M3A1
IO_3_L47P_M3A0
IO_3_L48N_M3BA1
IO_3_L48P_M3BA0
IO_3_L49N_M3A2
IO_3_L49P_M3A7
IO_3_L50N_M3BA2
IO_3_L50P_M3WE
IO_3_L51N_M3A4
IO_3_L51P_M3A10
IO_3_L52N_M3A9
IO_3_L52P_M3A8
IO_3_L53N_M3A12
IO_3_L53P_M3CKE
IO_3_L54N_M3A11
IO_3_L54P_M3RESET
IO_3_L55N_M3A14
IO_3_L55P_M3A13
IO_3_L83N_VREF
IO_3_L83P
N3
N4
P3
P4
M5
L6
U1
U2
T1
T2
P1
P2
N1
N2
M1
M3
L1
L2
K1
K2
L3
L4
J1
J3
H1
H2
K3
K4
K5
L5
H3
H4
K6
L7
G1
G3
J6
J7
F1
F2
H5
H6
E1
E3
F3
F4
D1
D2
G6
H7
D3
E4
F5
F6
C1
C2
C
FPGA BANK 3 NOT USED
B
XC6SLX16-2CSG324C
A
A
Title
STEVAL-IME0009V1 STMicroelectronics
Size
B
Date:
5
4
3
2
Document Number
STHV800 Demonstration Board
Wednesday, June 18, 2014
Rev
1.02
Sheet
1
6
of
9
5
4
3
+VFPGA_IO_3V3
+VFPGA_IO_3V3
8
7
6
5
4-Resistor Array
3.2x1.6mm
Not Assembly
D
D22
STTH102A
NOT ASSEMBLY
C36
C37
C38
C39
C40
C41
C42
C43
100uF 6.3V 1206
4.7uF 6.3V 0603
4.7uF 6.3V 0603
4.7uF 6.3V 0603
0.22uF 6.3V 0402
100uF 6.3V 1206
4.7uF 6.3V 0603
4.7uF 6.3V 0603
0.22uF 6.3V 0402
C44
C45
C46
C47
C48
C49
C50
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
1
2
3
4
R41 49R 0402
NOT ASSEMBLY
CON14A
Xilinx Parallel IV Connector
2.0mm 7x2 shrouded header
R43 49R 0402
A17
B18
D16
D15
TCK
TMS
TDO
TDI
NOT ASSEMBLY
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
R44 49R 0402
FPGA_TCK
FPGA_TMS
FPGA_TDO
FPGA_TDI
B1
B17
E14
E5
E9
G10
J12
K7
M9
P10
P14
P5
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
U4E
XC6SLX16-2CSG324C
NOT ASSEMBLY
G7
H11
H9
J10
J8
K11
K9
L10
L8
M12
M7
+VFPGA_IO_3V3
R42 49R 0402
NOT ASSEMBLY
C
SUSPEND & CMPCS_B
+VFPGA_IO_3V3
R45
FPGA - Power & Configuration
FPGA_CMP_CS_B
FPGA_PROG
FPGA_SUSPEND
FPGA_DONE
10K 0402
C62
100nF
CMPCS_B_2
PROGRAM_B_2
SUSPEND
DONE_2
1
2
3
4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
Header 3
74V1G32CTR
A18
B13
C3
D10
D5
B7
C16
G17
G2
G5
H10
H8
J11
J15
J4
E15
G12
K8
L11
L9
M17
M2
M6
N13
R1
R14
R18
R4
R9
T16
U12
U6
V1
V18
K10
J9
A1
3
R48
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
1
J12
XC6SLX16-3CSG324C
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
U6
5
B
P13
V2
R16
V17
R46
10K 0402
MCU_FPGA_SUSPEND
Jumper J12
1:2 to force
FPGA into
suspend mode.
2:3 (Default)
to allow MCU
to control
FPGA suspend
mode.
D
RESDIP4X1206
J11
NOT ASSEMBLY
2
4
6
8
10
12
14
To be placed
near U6
+VFPGA_CORE_1V2
C35
RN1
RESISTOR DIP 4
FPGA JTAG
1
3
5
7
9
11
13
1
+VFPGA_IO_3V3
+VFPGA_CORE_1V2
+VFPGA_IO_3V3
+VFPGA_CORE_1V2
FPGA JTAG
2
SUSPEND
10K 0402
R50
10K 0402
5
R49
10K 0402
To be placed
near U3
C73
100nF
U7
R51
56R
4
DONE
3
100uF 6.3V 1206
4.7uF 6.3V 0603
4.7uF 6.3V 0603
0.22uF 6.3V 0402
C55
C56
C57
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
C
+VFPGA_IO_3V3
P9
R12
R6
U14
U4
U9
C58
C59
C60
C61
100uF 6.3V 1206
4.7uF 6.3V 0603
4.7uF 6.3V 0603
0.22uF 6.3V 0402
C63
C64
C65
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
E2
G4
J2
J5
M4
R2
+VFPGA_IO_3V3
R47
0
C66
C67
C68
C69
100uF 6.3V 1206
4.7uF 6.3V 0603
4.7uF 6.3V 0603
0.22uF 6.3V 0402
C70
C71
C72
0.22uF 6.3V 0402
0.22uF 6.3V 0402
0.22uF 6.3V 0402
B
0805
C35, C40, C51, C58, C66 Details
C36, C37, C38, C41, C42, C52, C53, C59, C60, C67, C68 Details
Murata (GRM31CR60J107ME39L) - Digikey (490-4539-1-ND)
TDK (C1608X5R0J475K) - Digikey (445-5178-2-ND)
Dimension 1206 - EIA 3216
Dimension 0603 - EIA 1608
FPGA_PROG
2
RS (378-6527)
C54
+VFPGA_IO_3V3
1
MCU_FPGA_PROG
C53
E17
G15
J14
J17
M15
R17
DONE
+VFPGA_IO_3V3
C52
B10
B15
B5
D13
D7
E10
FPGA BANK 3
NOT USED
PROGRAM_B
C51
R52
330 0402
74LX1G08CTR
D23
GREEN
SW PUSHBUTTON-DPST
A
A
J13
1
2
RST1
FPGA PROG
Jumper J13 used to prevent FPGA from
programming from configuration source.
Set 1:2 to disable FPGA programming.
Open (default) to enable FPGA
programming.
FPGA_MCU_DONE
FPGA_DONE
Q1
2N7002
Title
STEVAL-IME009V1 STMicroelectronics
JUMPER
Size
B
FPGA PROG
DISABLE
Date:
5
4
3
2
Document Number
STHV800 Demonstration Board
Wednesday, June 18, 2014
Rev
1.02
Sheet
1
7
of
9
3
2
C80
R54
100
DVDD
VDDP
VDDM
C77
R55
100
C81
270p 100V 1206
1
270p 100V 1206
B2S J17
1
2
2
2
1
1
1
2
1
CW
8
HVM
CX4
CX5
C86
CK
XDCR_5
CW
XDCR_6
DFLS1200
D42
1
Jch5
DFLS1200
D41
220n
D40
DFLS1200
HVM_CW
220n 100V 0805
220n 100V 0805
D39
DFLS1200
1
BNC
Jch6
XDCR_7 BNC
11
13
14
2
1
Jch8
10
12
1 BNC
Jch7
BNC
DFLS1200
D45
D43
2
XDCR_8
2
9
DFLS1200
D44
DFLS1200
IN1_0
IN1_1
IN2_0
IN3_0
IN3_1
IN4_0
IN4_1
GND_PWR
LVOUT_1
LVOUT_2
1
2
3
43
44
45
47
48
49
50
51
52
53
54
55
HVP
STHV800
HVM
HVP
HVM
HVP
HVM
HVP
HVM_CW
HVP
XDCR_5
AGND
XDCR_6
VDDM
XDCR_7
VDDP
XDCR_8
D46
DFLS1200
15
CK
THSD_EN
2
THSD_EN
HVM
THSD
41
CW
40
DVDD
C83
J31
B2S
36
2
2
2
2
1
C111
270p 100V 1206
100
R61
100
R65
100
R63
C112
270p 100V 1206
C113
CX8
CX6
220n
220n 100V 0805
HVP
C95
220n
34
220n 100V 0805
C97
220n
33
C101
220n
C85
32
31
VDDM
30
VDDP
220n
C87
220n
29
THSD
J24
DVDD
THSD_EN
1
2
3
TP3
TEST POINT
CON3
R58
10k
B
THSD
R59
100k
B2S
2
C114 20p 1206
B2S J34
270p 100V 1206
270p 100V 1206
C116
100
R62
220n 100V 0805
35
J27
B2S
1
C89
CX7
IN8_1
IN8_0
IN7_1
IN7_0
IN6_1
IN6_0
IN5_1
IN5_0
J33
220n 100V 0805
220n 100V 0805
CX9
1
1
1
1
J28
B2S
HVP_CW
CX10
37 HVP
HVM
J32
B2S
C
38
HVP
B
220n
39
1
7
220n
HVP_CW
IN8_1
220n
DFLS1200
HVP
HVM
42
28
6
C91
IN8_0
220n
5
HVM
C90
IN7_1
D38
DFLS1200
C88
27
D37
CX3
26
IN8_1
CX2
DGND
IN6_1
CX1
XDCR_4
IN6_0
DFLS1200
D36
DVDD
24
D35
DFLS1200
XDCR_3
23
4
220n 100V 0805
220n 100V 0805
220n 100V 0805
CW
IN5_1
IN8_0
3
CK
XDCR_2
IN5_0
1
Jch4
XDCR_4
IN7_1
1 BNC
Jch3
BNC
STHV800
CK
22
BNC
2
BNC
XDCR_1
21
XDCR_3
1
GND_PWR
1
Jch2
XDCR_2
IN6_1
IN7_0
D32
DFLS1200
LVOUT_3
D34
1
Jch1
LVOUT_4
XDCR_1
IN6_0
20
IN8_1
IN5_1
LVOUT_8
IN8_0
DFLS1200
LVOUT_7
IN7_1
IN5_0
U8
DFLS1200
D31
DFLS1200
D33
19
IN7_0
J25
CON3
CK
IN4_1
18
C
20p 1206
HVM
LVOUT_6
IN6_1
IN4_0
LVOUT_5
IN6_0
C92
HVP
17
IN5_1
IN3_1
16
IN5_0
20p 1206
IN4_1
IN4_0
IN3_1
IN3_0
IN2_2
IN2_0
IN1_1
IN1_0
56
IN4_1
C76
2
B2S J14
GND_PWR
IN4_0
1
GND_PWR
IN3_1
J19
B2S
LVOUT_4
2
B2S J15
J21
B2S
1
J16, J17, J22, J23, J25, J26, J29 and J30 Details
Tyco Electronics (1-1337482-0) - RS (420-5401)
D
IN3_0
2
IN3_0
J20
B2S
20p 1206
LVOUT_3
Jlch3
BNC
1
IN2_1
2
IN2_1
IN2_0
2
IN2_0
IN1_1
2
IN1_1
J18
B2S
C75
C77, C80, C111, C112 Details
DigiKey (490-1462-2-ND) Murata (GRM188R72A271KA01D)
Jlch4
BNC
2
B2S J16
1
IN1_0
20p 1206
2
HVM
HVM_CW
IN1_0
C74
J16, J17, J22, J23, J25, J26, J29 and J30 Details
Tyco Electronics (1-1337482-0) - RS (420-5401)
LVOUT_2
2
46
HVM
HVM_CW
R64
100
IN2_1
D
C84
270p 100V 1206
IN7_0
DVDD
VDDP
VDDM
HVP
HVP_CW
1
Jlch2
BNC
R56
100
25
HVP
HVP_CW
LVOUT_1
2
1
Jlch1
BNC
270p 100V 1206
1
D1, D2, D3 ,D4, D5, D6, D7, D8
diode DFLS1200 rs-code 708-2324
2
4
2
5
2
C115 20p 1206
B2S J29
1
2
C117 20p 1206
B2S J30
1
2
C118 20p 1206
A
A
Jlch7
BNC
LVOUT_6
Jlch8
BNC
1
LVOUT_7
2
1
2
LVOUT_5
1
2
1
Jlch6
BNC
2
Jlch5
BNC
LVOUT_8
Title
STEVAL-IME009V1 STMicroelectronics
Size
A3
Date:
5
4
3
2
Document Number
STHV800 Demonstration Board
Wednesday, June 11, 2014
Rev
1.02
Sheet
1
8
of
9
5
4
SPI FLASH
3
Use J38 to enable/disable power for SPI flash device.
J38 must be open when using external spi flash device on
connecto J10. Default value closed.
FLASH_3V3
1
MCU_3V3
MCU_3V3
J38
2
1
2
FLASH_3V3
FLASH_3V3
FLASH DISABLE
R132
MCU_3V3
R128
MCU_3V3
Place near MCU
FLASH_DQ1
FLASH_DQ1
10
STM32_GPIO_0
11
STM32_GPIO_1
12
STM32_GPIO_2
13
STM32_GPIO_3
14
STM32_GPIO_4
15
STM32_GPIO_5
16
STM32_GPIO_6
17
STM32_GPIO_7
29
STM32_GPIO_8
30
STM32_GPIO_9
USB_DISCONNECT 31
32
DM_STM32
33
DP_STM32
4
N25Q032xSC
USB_DISCONNECT
USB_DM
USB_DP
3
4
2
C
RESET#
7
MCU_3V3
VDDA
BOOT0
BOOT1
C123 Details:
Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K)
Package 0402
C123
1uF 6.3V
C122
100nF
R66
4K7
9
44
20
R67
4K7
C119
100nF
C120
100nF
C121
100nF
D
RESET#
C125
100nF
48
36
24
1
2
VSS
DQ0
DQ1
C
nS
nW/Vpp/DQ2
nHOLD/DQ3
R133
10K
MCU_3V3
MCU
VCC
5
6
1
3
7
FLASH_DQ0
FLASH_C
FLASH_nS
FLASH_DQ2
FLASH_DQ3
C126
100nF
INT SPI FLASH
U9
FLASH_DQ0
FLASH_C
FLASH_nS
FLASH_DQ2
FLASH_DQ3
56
VDD_3
VDD_2
VDD_1
VBAT
4k7
0R - N/A
D30
RED
PA0-WKUP
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PB4 JNTRST
PB3 JTDO
PA15 JTDI
PA14 JTCK
PA13 JTMS
PC14-OSC32_IN
PC15-OSC32_OUT
PC13-Tamper-RTC
NRST
VDDA
BOOT0
PB2-BOOT1
STM32F103C8T6
U10
40
39
38
37
34
PB0
PB1
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
VSSA
VSS_1
VSS_2
VSS_3
4k7
R131
C124
100nF
4k7
PD0 OSC_IN
PD1 OSC_OUT
8
23
35
47
D
R130
8
R129
18
19
41
42
43
45
46
21
22
25
26
27
28
RST2
JNTRST
JTDO
JTDI
JTCK
JTMS
SW PUSHBUTTON-DPST
Not Assembly
RS (505-9186)
C&K (Y78B22110FP)
USER_LED1
USER_LED2
STM32_GPIO_10
STM32_GPIO_11
STM32_GPIO_12
STM32_GPIO_13
STM32_GPIO_14
FLASH_DQ3
FLASH_DQ2
FLASH_nS
FLASH_C
FLASH_DQ1
FLASH_DQ0
C
OSCILLATOR
Y1
OSCIN
5
6
MCU RESET
OSCIN
OSCOUT
OSCOUT
8MHz
8MHZ OSC
Murata (CSTCE8M00G55-R0)
DigiKey (490-1195-1-ND)
RS: 283-961
Farnell: 1615352
STM32F103
B
B
DOWNLOAD
OPTIONAL FPGA I/O
D24
R68 56R
USER_LED1
STM32_GPIO_0
STM32_GPIO_1
STM32_GPIO_2
STM32_GPIO_3
STM32_GPIO_4
STM32_GPIO_5
STM32_GPIO_6
STM32_GPIO_7
R69
R70
R71
R72
R73
R74
R75
R80
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
FPGA_GPIO0
FPGA_GPIO1
FPGA_GPIO2
FPGA_GPIO3
FPGA_GPIO4
FPGA_GPIO5
FPGA_GPIO6
FPGA_GPIO7
JTAG/SWD
FPGA_GPIO[0:7]
STM32_GPIO_8
STM32_GPIO_9
STM32_GPIO_10
STM32_GPIO_11
STM32_GPIO_12
STM32_GPIO_13
STM32_GPIO_14
R82
R83
R84
R85
R86
R88
R89
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
0R - N/A
FPGA_MCU_AWAKE
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
MCU_FPGA_PROG
MCU_FPGA_SUSPEND
RED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
FPGA_GPIO[0:7]
R76
10k
OPTIONAL FPGA CONFIGURATION SIGNALS
A
MCU_3V3
FPGA_MCU_AWAKE
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
MCU_FPGA_PROG
MCU_FPGA_SUSPEND
R77
10k
R78
10k
Male Connector 2x5
Pitch 1.27 mm
SAMTEC FTSH-105-01-F-D-K
R79
10k
2
JNTRST
JTMS
JTCK
JTDO
JTDI
RESET#
JP1 JUMPER
1
FLASH READY
MCU_3V3
D25
R81 56R
USER_LED2
J40
2
4
6
8
10
1
3
5
7
9
RED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
A
SWD/JTAG
R87
10k
MCU JTAG
Title
STEVAL-IME009V1 STMicroelectronics
Size
B
Date:
5
4
3
2
Document Number
STHV800 Demonstration Board
Wednesday, June 18, 2014
Rev
1.02
Sheet
1
9
of
9
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