64Mb N-die SDRAM Specification 54 TSOP-II with Lead-Free and Halogen-Free (RoHS compliant)

64Mb N-die SDRAM Specification 54 TSOP-II with Lead-Free and Halogen-Free (RoHS compliant)

K4S640832N

K4S641632N

Synchronous DRAM

64Mb N-die SDRAM Specification

54 TSOP-II with Lead-Free and Halogen-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

Synchronous DRAM

Table of Contents

1.0 FEATURES .................................................................................................................................... 4

2.0 GENERAL DESCRIPTION ............................................................................................................ 4

3.0 Ordering Information ................................................................................................................... 4

4.0 Package Physical Dimension ...................................................................................................... 5

5.0 FUNCTIONAL BLOCK DIAGRAM................................................................................................. 6

6.0 PIN CONFIGURATION................................................................................................................... 7

7.0 Input/Output Function Description ............................................................................................. 7

8.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................... 8

9.0 DC OPERATING CONDITIONS..................................................................................................... 8

10.0 CAPACITANCE............................................................................................................................ 8

11.0 DC CHARACTERISTICS ............................................................................................................ 9

12.0 AC OPERATING TEST CONDITIONS....................................................................................... 11

13.0 OPERATING AC PARAMETER................................................................................................. 11

14.0 AC CHARACTERISTICS ........................................................................................................... 12

15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS................................................................ 12

16.0 IBIS SPECIFICATION ................................................................................................................ 13

17.0 SIMPLIFIED TRUTH TABLE...................................................................................................... 15

2 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

Revision History

Revision

1.0

1.1

1.11

Month

December

December

March

Year

2007

2007

2008

- Release SPEC revision 1.0

- Revised ICC6 SPEC of lowpower

- Added Package pin out lead width

History

Synchronous DRAM

3 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM

1.0 FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock

• Burst read single-bit write operation

• DQM (x8) & L(U)DQM (x16) for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

• Lead-Free and Halogen-Free Package

• RoHS compliant

Synchronous DRAM

2.0 GENERAL DESCRIPTION

The K4S640832N / K4S641632N is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG

′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

3.0 Ordering Information

Part No.

K4S640832N-LC/L75

K4S641632N-LC/L50

K4S641632N-LC/L60

K4S641632N-LC/L75

Orgainization

8Mb x 8

4Mb x 16

Max Freq.

133MHz(CL=3)

200MHz(CL=3)

166MHz(CL=3)

133MHz(CL=3)

Interface

LVTTL

Package

54pin TSOP(II)

Lead-Free & Halogen-Free

Organization

8Mx8

4Mx16

Row Address

A0~A11

A0~A11

Column Address

A0-A8

A0-A7

Row & Column address configuration

4 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

4.0 Package Physical Dimension

#54 #28

Synchronous DRAM

Unit : mm

#1

(1.50)

22.22

±

0.10

(R 0

.15)

(R

0

.1

5)

(0.71)

0.80TYP

[0.80

±

0.08]

Detail A

NOTE

1. ( ) IS REFERENCE

2. [ ] IS ASS’Y OUT QUALITY

Detail A

Detail B

0.30

+0.10

- 0.05

Detail B

#27

(10

°)

(10

°)

0.35

+0.10

- 0.05

[

0.10 MAX

0.075 MAX

54Pin TSOP(II) Package Dimension

[

0.125

+0.075

- 0.035

(R

0

.2

5)

(R

0

.2

5)

0.25TYP

(0

° ∼ 8°)

5 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

5.0 FUNCTIONAL BLOCK DIAGRAM

Synchronous DRAM

Data Input Register

Bank Select

2M x 8 / 1M x 16

2M x 8 / 1M x 16

2M x 8 / 1M x 16

2M x 8 / 1M x 16

CLK

ADD

LCKE

LRAS LCBR

Column Decoder

Latency & Burst Length

LWE LCAS

Timing Register

Programming Register

LWCBR

CLK CKE CS RAS CAS WE

LDQM

L(U)DQM

*

Samsung Electronics reserves the right to change products or specification without notice.

LWE

LDQM

DQi

6 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

6.0 PIN CONFIGURATION

x16 x8

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

V

DDQ

N.C

DQ3

V

SSQ

N.C

V

DD

N.C

WE

V

DD

DQ0

V

DDQ

N.C

DQ1

V

SSQ

N.C

DQ2

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

V

DDQ

DQ5

DQ6

V

SSQ

DQ7

V

DD

LDQM

WE

V

DD

DQ0

V

DDQ

DQ1

DQ2

V

SSQ

DQ3

DQ4

21

22

23

24

17

18

19

20

25

26

27

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

34

33

32

31

38

37

36

35

30

29

28

42

41

40

39

46

45

44

43

50

49

48

47

54

53

52

51 x8

A9

A8

A7

A6

CLK

CKE

N.C

A11

A5

A4

V

SS

V

SS

DQ7

V

SSQ

N.C

DQ6

V

DDQ

N.C

DQ5

V

SSQ

N.C

DQ4

V

DDQ

N.C

V

SS

N.C/RFU

DQM x16

A9

A8

A7

A6

CLK

CKE

N.C

A11

A5

A4

V

SS

V

SS

DQ15

V

SSQ

DQ14

DQ13

V

DDQ

DQ12

DQ11

V

SSQ

DQ10

DQ9

V

DDQ

DQ8

V

SS

N.C/RFU

UDQM

Synchronous DRAM

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

7.0 Input/Output Function Description

CLK

CS

CKE

Pin Name

System clock

Chip select

Clock enable

Description

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A

0

~ A

11

BA

0

~ BA

1

RAS

CAS

WE

DQM

DQ

0

~

N

V

DD

/V

SS

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

V

DDQ

/V

SSQ

Data output power/ground

Row/column addresses are multiplexed on the same pins.

Row address : RA

0

~ RA

11

,

Column address : (x8 : CA

0

~ CA

8 , x16 : CA

0

~ CA

7

)

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data inputs/outputs are multiplexed on the same pins.

(x8 : DQ

0

~

7

), (x16 : DQ

0

~

15

)

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise immunity.

N.C/RFU

No connection

/reserved for future use

This pin is recommended to be left No Connection on the device.

7 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

Synchronous DRAM

8.0 ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to V

SS

Voltage on V

DD

supply relative to V

SS

Symbol

V

IN

, V

OUT

V

DD

, V

DDQ

Value

-1.0 ~ 4.6

-1.0 ~ 4.6

Storage temperature

Power dissipation

T

STG

P

D

-55 ~ +150

1

Short circuit current I

OS

50

Note :

Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Unit

V

V

°C

W mA

9.0 DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

SS

= 0V, T

A

= 0 to 70

°C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Symbol

V

DD

, V

DDQ

V

IH

V

IL

V

OH

V

OL

I

LI

Min

3.0

2.0

-0.3

2.4

-

-10

-

-

-

Typ

3.3

3.0

0

Max

3.6

V

DD

+0.3

0.8

-

0.4

10

Unit

V

V

V

V

V uA

Notes :

1. V

IH

(max) = 5.6V AC.The overshoot voltage duration is

≤ 3ns.

2. V

IL

(min) = -2.0V AC. The undershoot voltage duration is

≤ 3ns.

3. Any input 0V

≤ V

IN

≤ V

DDQ

.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Note

1

2

I

OH

= -2mA

I

OL

= 2mA

3

10.0 CAPACITANCE

Pin

Clock

RAS, CAS, WE, CS, CKE, DQM

Address

(x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15)

Symbol

C

CLK

C

IN

C

ADD

C

OUT

Min

2.5

2.5

2.5

4.0

Max

4.0

5.0

5.0

6.5

(V

DD

= 3.3V, T

A

= 23

°C, f = 1MHz)

Unit

pF pF pF pF

Note

8 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

11.0 DC CHARACTERISTICS (x8)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C for x8)

Parameter Symbol Test Condition

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

I

CC1

Burst length = 1

t

RC

≥ t

RC

(min)

I

O

= 0 mA

I

CC2

P CKE

≤ V

IL

(max), t

CC

= 10ns

I

CC2

PS CKE & CLK

≤ V

IL

(max), t

CC

=

I

I

CC2

CC2

N

NS

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

CC3

P CKE

≤ V

IL

(max), t

CC

= 10ns

I

CC3

PS CKE & CLK

≤ V

IL

(max), t

CC

=

I

CC3

CC3

N

NS

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

CC4

I

O

= 0 mA

Page burst

4Banks Activated

t

CCD

= 2CLKs

I

CC5 t

RC

≥ t

RC

(min)

I

CC6

CKE

≤ 0.2V

C

L

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S640832N-LC

4. K4S640832N-LL

5. Unless otherwise noted, input swing IeveI is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ)

Synchronous DRAM

Version

75

65

10

4

4

30

2

2

15

25

110

110

1

400

Unit

mA mA mA mA mA mA mA mA uA

Note

1

1

2

3

4

9 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

Synchronous DRAM

DC CHARACTERISTICS (x16)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C for x16 only)

Parameter Symbol Test Condition

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

CC1

Burst length = 1

t

RC

≥ t

RC

(min)

I

O

= 0 mA

I

CC2

P CKE

≤ V

IL

(max), t

CC

= 10ns

I

CC2

PS CKE & CLK

≤ V

IL

(max), t

CC

=

I

CC2

N

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

I

I

CC2

NS

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

CC3

P CKE

≤ V

IL

(max), t

CC

= 10ns

I

CC3

PS CKE & CLK

≤ V

IL

(max), t

CC

=

I

CC3

CC3

N

NS

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

CC4

I

O

= 0 mA

Page burst

4Banks Activated

t

CCD

= 2CLKs

I

CC5 t

RC

≥ t

RC

(min)

I

CC6

CKE

≤ 0.2V

C

L

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S641632N-LC

4. K4S641632N-LL

5. Unless otherwise noted, input swing IeveI is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ)

50

90

Version

60 75

80

2

2

15

10

4

4

30

25

65

130 120 110

130 120 110

1

400

Unit

mA mA mA mA mA mA mA mA uA

Note

1

1

2

3

4

10 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

12.0 AC OPERATING TEST CONDITIONS

Parameter

AC input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

See Fig. 2

Synchronous DRAM

(V

DD

= 3.3V

± 0.3V, T

A

= 0 to 70

°C)

Unit

V

V ns

V

Output

870

3.3V

1200

V

OH

(DC) = 2.4V, I

OH

= -2mA

V

OL

(DC) = 0.4V, I

OL

= 2mA

30pF

Output

Z0 = 50

Vtt = 1.4V

50

30pF

(Fig. 1) DC output load circuit (Fig. 2) AC output load circuit

13.0 OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Row active to row active delay

RAS to CAS delay

Row precharge time

Row active time

Parameter Symbol

50

10

15

15

40

75

15

20

20

45

Unit

t

RRD

(min) t

RCD

(min) t

RP

(min) t

RAS

(min) t

RAS

(max) t

RC

(min) t

RDL

(min)

42

100

60

2

60

12

18

18 ns ns ns ns us ns

CLK

Row cycle time

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

Col. address to col. address delay t

DAL

(min) t

CDL

(min) t

BDL

(min) t

CCD

(min)

55

2 CLK + tRP

1

1

1

65

-

CLK

CLK

CLK

Number of valid output data

CAS latency = 3

CAS latency = 2

2

1 ea

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Note

1, 6

2,5,6

5

2

2

3

4

1

1

1

1

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

6. t

RC

=t

RFC, t

RDL

= t

WR

.

11 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

Synchronous DRAM

14.0 AC CHARACTERISTICS

Parameter

CLK cycle time

CLK to valid output delay

Output data hold time

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time

CLK to output in Low-Z

CLK to output in Hi-Z

CAS latency=3

CAS latency=2

Symbol

t t t t t t t t t

CC

SAC

OH

CH

CL

SS

SH

SLZ

SHZ

50 (x16 only)

Min Max

2

-

-

-

5

-

2

2

1.5

1

1

-

-

1000

4.5

-

-

-

-

-

-

-

-

4.5

-

(AC operating conditions unless otherwise noted)

1

-

-

2.5

2.5

1.5

1

2.5

3

-

-

60 (x16 only)

Min Max

6

10

1000

-

-

5

6

-

5

6

-

-

-

-

1

-

-

2.5

2.5

1.5

0.8

3

3

-

-

Min

7.5

10

75

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

4. t

SS applies for address setup time

, clock enable setup time

, commend setup time and data setup time

t

SH applies for address holde time, clock enable hold time, commend hold time and data hold time

Max

1000

-

-

-

-

-

-

5.4

6

-

5.4

6

Unit Note

ns ns ns ns ns ns ns ns ns

1

1,2

2

3

3

3, 4

3, 4

2

15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter

Output rise time

Symbol

trh

Condition

Measure in linear

region : 1.2V ~ 1.8V

Min

1.37

Typ

Output fall time

Output rise time tfh trh

Measure in linear

region : 1.2V ~ 1.8V

Measure in linear

region : 1.2V ~ 1.8V

1.30

2.8

3.9

Output fall time tfh

Measure in linear

region : 1.2V ~ 1.8V

2.0

2.9

Notes :

1. Rise time specification based on 0pF + 50

Ω to V

SS

, use these values to design to.

2. Fall time specification based on 0pF + 50

Ω to V

DD

, use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to V

SS

.

Max

4.37

3.8

5.6

5.0

Unit

Volts/ns

Volts/ns

Volts/ns

Volts/ns

Notes

3

3

1,2

1,2

12 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

16.0 IBIS SPECIFICATION

I

OH

Characteristics (Pull-up)

Voltage

200MHz/133MHz

Min

(V)

3.45

3.30

3.00

2.70

2.50

1.95

1.80

1.65

1.50

1.40

1.00

0.20

I (mA)

-

-

-0.35

-3.75

-6.65

-13.75

-17.75

-20.55

-23.55

-26.2

-36.25

-46.5

200MHz/133MHz

Max

I (mA)

-1.68

-19.11

-51.87

-90.44

-107.31

-137.9

-158.34

-173.6

-188.79

-199.01

-241.15

-351.68

Synchronous DRAM

-300

-400

-500

-600

-100

-200

0

0 0.5

200MHz/133MHz Pull-up

1 1.5

2 2.5

3 3.5

Voltage

I

OH

Min (200MHz / 133MHz)

I

OH

Max (200MHz / 133MHz)

I

OL

Characteristics (Pull-down)

Voltage

(V)

3.45

3.30

3.00

1.95

1.80

1.65

1.50

1.40

1.00

0.85

0.65

0.40

200MHz/133MHz

Min

I (mA)

43.92

-

43.36

41.20

40.56

39.60

38.40

37.28

30.08

26.64

21.52

14.16

200MHz/133MHz

Max

I (mA)

155.82

-

153.72

148.40

146.02

141.75

136.08

131.39

105.84

93.66

75.25

49.14

200MHz/133MHz Pull-down

250

200

150

100

50

0

0 0.5

1 1.5

2

Voltage

2.5

I

OL

Min (200MHz / 133MHz)

3 3.5

I

OL

Max (200MHz / 133MHz)

13 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

V

DD

Clamp @ CLK, CKE, CS, DQM & DQ

V

DD

(V) I (mA)

2.0

2.2

2.4

2.6

1.2

1.4

1.6

1.8

0.7

0.8

0.9

1.0

0.0

0.2

0.4

0.6

1.34

3.02

5.06

7.35

9.83

12.48

15.30

18.31

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.23

V

SS

Clamp @ CLK, CKE, CS, DQM & DQ

V

SS

(V)

-2.6

I (mA)

-57.23

-1.2

-1.0

-0.9

-0.8

-0.7

-0.6

-2.4

-2.2

-2.0

-1.8

-1.6

-1.4

-0.4

-0.2

0.0

-45.77

-38.26

-31.22

-24.58

-18.37

-12.56

-7.57

-3.37

-1.75

-0.58

-0.05

0.0

0.0

0.0

0.0

Synchronous DRAM

20

15

10

5

0

0

Minimum V

DD

clamp current

(Referenced to V

DD

)

1

Voltage

2

I (mA)

3

-30

-40

-50

-60

-10

-20

0

-3

Minimum V

SS

clamp current

-2 -1 0

Voltage

I (mA)

14 of 15

Rev. 1.11 March 2008

K4S640832N

K4S641632N

Synchronous DRAM

17.0 SIMPLIFIED TRUTH TABLE

′t care, H=Logic high, L=Logic low)

Command

CKEn-1 CKEn CS RAS CAS WE DQM BA

0,1

A

10

/AP

A

11,

A

9

~ A

0

Note

Register H L L L L X OP code

Refresh

Mode register set

Auto refresh

Entry

Self refresh

Exit

H

L

H

X

H

L

H

X

L

L

H

L

L

H

X

L

L

H

X

H

H

H

X

H

X

X

X V

X

X

1,2

3

3

3

3

Bank active & row addr.

Read & column address

Auto precharge disable

Auto precharge enable

Write & column address

Auto precharge disable

Auto precharge enable

Burst stop

Precharge

Bank selection

All banks

H

H

H

H

X

X

X

X

L

L

L

L

H

H

H

L

L

L

H

H

H

L

L

L

X

X

X

X

V

V

V

X

L

H

Row address

L

H

Column address

L

H

Column address

X

X

4

4,5

4

4,5

6

Clock suspend or active power down

Precharge power down mode

DQM

No operation command

Entry

Exit

Entry

Exit

H

L

H

L

H

H

L

H

L

H

X

H

L

L

H

L

X

H

H

L

V

X

H

X

X

H

X

X

X

V

X

H

H

X

V

X

X

X

V

X

H

H

X

V

X

X

X

V

X

X

X

X

V

X

X

X

X

X

7

Notes :

1. OP Code : Operand code

A

0

~ A

11

& BA

0

~ BA

1

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA

0

~ BA

1

: Bank select addresses.

If both BA

0

and BA

1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

0

is "Low" and BA

1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA

0

is "High" and BA

1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA

0

and BA

1 are "High" at read, write, row active and precharge, bank D is selected.

If A

10

/AP is "High" at row precharge, BA

0

and BA

1

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t

RP

after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

15 of 15

Rev. 1.11 March 2008

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project