Renesas RX23T Group, RX62T Group microcontroller Application note

APPLICATION NOTE

RX23T Group, RX62T Group

Points of Difference Between RX23T Group and RX62T Group

R01AN2823EJ0110

Rev.1.10

Jan 14, 2016

Introduction

This application note is intended as a reference for confirming the points of difference between the I/O registers of the

RX23T Group and RX62T Group.

Target Device



RX23T Group 64-pin version, ROM capacity: 64 KB and 128 KB







When using this application note with other Renesas MCUs, careful evaluation is recommended after making modifications to comply with the alternate MCU.

Contents

1.

Comparison of Functions of RX23T Group and RX62T Group ........................................................ 2

2.

Comparative Overview of Functions ................................................................................................. 3

3.

Reference Documents..................................................................................................................... 54

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 1 of 55

RX23T Group, RX62T Group Points of Difference Between RX23T Group and RX62T Group

1. Comparison of Functions of RX23T Group and RX62T Group

A comparison of the functions of the RX23T Group and RX62T Group is provided below. For details of the functions, see 2., Comparative Overview of Functions, and 3., Reference Documents.

Table 1.1 is a comparative listing of the functions of the RX23T and RX62T.

Table 1.1 Comparison of Functions of RX23T and RX62T

Function

Operating Modes

Reset

Option-setting memory

Voltage detection circuit (LVD): RX62T, (LVDAb): RX23T

Clock generation circuit

Clock frequency accuracy measurement circuit (CAC)

Low power consumption function

Register write protection function

Interrupt controller (ICU): RX62T, (ICUb): RX23T







RX62T RX23T

Buses

Memory-protection unit (MPU)

Data transfer controller (DTC): RX62T, (DTCa): RX23T

I/O port

Multi-function pin controller (MPC)

Multi-function timer pulse unit 3 (MTU3): RX62T, (MTU3c): RX23T

Port output enable 3 (POE3): RX62T, (POE3b): RX23T

8-bit timer (TMR)

Compare match timer (CMT)

Watchdog timer (WDT)

Independent watchdog timer (IWDT): RX62T, (IWDTa): RX23T

Serial communications interface (SCIb): RX62T, (SCIg): RX23T

I

2

C bus interface (RIIC): RX62T, (RIICa): RX23T

CAN module (CAN)

Serial peripheral interface (RSPI): RX62T, (RSPIa): RX23T

LIN module (LIN)











CRC calculator (CRC)

12-bit A/D converter (S12ADA): RX62T, (S12ADE): RX23T

10-bit A/D converter (ADA)

D/A converter (DA) for generating comparator C reference voltage

Comparator C (CMPC)

Data operation circuit (DOC)

RAM









Flash memory

Note: : Function implemented,



: Function not implemented, : Differences exist between implementation of function on RX62T and RX23T.

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 2 of 55


2. Comparative Overview of Functions

2.1 Operating Modes

Table 2.1 shows a comparative listing of the operating mode registers.

Table 2.1 Comparative Listing of Operating Mode Registers

Register

MDMONR

MDSR

SYSCR0

Bit

MD0

MD

MD1

MDE

IROM

BOTS

ROME

KEY[7:0]

RX62T

MD0 pin status flag



MD1 pin status flag

MDE pin status flag

On-chip ROM startup status flag

Boot mode startup flag

On-chip ROM enable bit

SYSCR0 key code

RX23T



MD pin status flag













2.2 Resets

Table 2.2 shows a comparative listing of the reset specifications and Table 2.3 shows a comparative listing of the reset

registers.

Table 2.2 Comparative Listing of Reset Specifications

Reset Name

RES# pin reset

Power-on reset

Voltage monitoring reset

Deep software standby reset

Independent watchdog timer reset

Watchdog timer reset

Software reset

RX62T

Voltage input to the RES# pin is driven low.

VCC rises or falls

(voltage detection: VPOR).

VCC falls

(voltage detection: Vdet1 and

Vdet2).

Deep software standby mode is canceled by an interrupt.

The independent watchdog timer underflows.

The watchdog timer overflows.



RX23T

Voltage input to the RES# pin is driven low.

VCC rises

(voltage detection: VPOR).

VCC falls

(voltage detection: Vdet0 , Vdet1, and Vdet2).



The independent watchdog timer underflows or reflesh error .



Register settings

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 3 of 55


Table 2.3 Comparative Listing of Reset Registers

Register

RSTSR0

RSTSR1

RSTSR2

SWRR

RSTSR

RSTCSR

IWDTSR

Bit

PORF

LVD0RF

LVD1RF

LVD2RF

CWSF

IWDTRF

SWRF

SWRR[15:0]

PORF

LVD1F

LVD2F

DPSRSTF

RSTE

WOVF

CNTVAL[13:0]

UNDFF

RX62T





RX23T

Power-on reset detection flag

Voltage monitoring 0 reset detection flag











Cold/warm start determination flag

Independent watchdog timer reset detection flag





Power-on reset flag

Software reset detection flag

Software reset bits





LVD1 detection flag

LVD2 detection flag



Deep software standby reset flag



Reset enable bit

Watchdog timer overflow flag

Down counter bits

Underflow flag









R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 4 of 55


2.3 Voltage Detection Circuit

Table 2.4 shows a comparative listing of the voltage detection circuit specifications and Table 2.5 shows a comparative

listing of the voltage detection circuit registers.

Table 2.4 Comparative Listing of Voltage Detection Circuit Specifications

Item

VCC monitoring

Monitored voltage

Detection target

Voltage detection processing

Detection voltage

Monitor flag

Reset

Interrupt

RX62T (LVD)

Voltage

Monitoring 1

RX23T (LVDAb)

Voltage

Monitoring 2

Voltage

Monitoring 0

Voltage

Monitoring 1

Vdet1 Vdet2 Vdet0 Vdet1

Voltage falls lower than

Vdet1.







Voltage monitoring 1 reset



Voltage monitoring 1 interrupt






Vdet2.















Voltage

Monitoring 2

Vdet2


Vdet0.

Selectable from two levels using

OFS1.VDSEL[1:

0] bits.




Reset when

Vdet0 > VCC:

CPU operation restarts a fixed period of time after VCC >

Vdet0.



Voltage rises or falls past Vdet1.

Selectable from nine levels using

LVDLVLR.LVD1L

VL[3:0] bits.

LVD1SR.LVD1

MON flag:

Monitors if higher or lower than

Vdet1.

LVD1SR.LVD1

DET flag: Detects rise or fall past

Vdet1.


Reset when

Vdet1 > VCC:

Selectable between CPU operation restarts a fixed period of time after VCC >

Vdet1 and CPU operation restarts a fixed period of time after Vdet1

> VCC.


Selectable between nonmaskable interrupt and interrupt.

Interrupt request generated both when Vdet1 >

VCC and when

VCC > Vdet1, or one or the other.

Voltage rises or falls past Vdet2.

Selectable from four levels using

LVDLVLR.LVD2L

VL[1:0] bits.

LVD2SR.LVD2M

ON flag: Monitors if higher or lower than Vdet2.

LVD2SR.LVD2D

ET flag: Detects rise or fall past

Vdet2.


Reset when

Vdet2 > VCC:

Selectable between CPU operation restarts a fixed period of time after VCC >

Vdet2 and CPU operation restarts a fixed period of time after Vdet2

> VCC.


Selectable between nonmaskable interrupt and interrupt.

Interrupt request generated both when Vdet2 >

VCC and when

VCC > Vdet2, or one or the other.

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 5 of 55


Table 2.5 Comparative Listing of Voltage Detection Circuit Registers

Register

RSTSR

LVDKEYR

LVDCR

LVD1CR1

Bit

PORF

LVD1F

LVD2F

DPSRSTF

KEY[7:0]

RX62T (LVD)

Power-on reset flag

LVD1 detection flag

LVD2 detection flag


LVDCR key code

LVD1RI

LVD1E

LVD1 reset/interrupt select bit

LVD1 enable bit

LVD2RI LVD2 reset/interrupt select bit

LVD2E

LVD1IDTSEL

LVD2 enable bit



[1:0]

LVD1IRQSEL



LVD1SR

LVD2CR1

LVD2SR

LVCMPCR

LVDLVLR

LVD1CR0

LVD2CR0

LVD1DET

LVD1MON

LVD2IDTSEL

[1:0]

LVD2DET

LVD2MON

LVD1E

LVD2E

LVD1LVL[3:0]



LVD2LVL[3:0]

LVD1RIE

LVD1CMPE

LVD1RI

LVD1RN

LVD2RIE

LVD2CMPE

LVD2RI

LVD2RN







LVD2IRQSEL





























RX23T (LVDAb)



















Voltage monitoring 1 interrupt generation condition select bits

Voltage monitoring 1 interrupt type select bit

Voltage monitoring 1 voltage change detection flag

Voltage monitoring 1 signal monitor flag

Voltage monitoring 2 interrupt generation condition select bits

Voltage monitoring 2 interrupt type select bit

Voltage monitoring 2 voltage change detection flag

Voltage monitoring 2 signal monitor flag

Voltage detection 1 enable bit

Voltage detection 2 enable bit

Voltage detection 1 level select bits

(reference voltage when voltage falls)

Voltage detection 2 level select bits

(reference voltage when voltage falls)

Voltage monitoring 1 interrupt/reset enable bit

Voltage monitoring 1 circuit comparison result output enable bit voltage monitoring 1 circuit mode select bit voltage monitoring 1 reset negate select bit

Voltage monitoring 2 interrupt/reset enable bit

Voltage monitoring 2 circuit comparison result output enable bit voltage monitoring 2 circuit mode select bit voltage monitoring 2 reset negate select bit

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 6 of 55


2.4 Clock Generation Circuit

Table 2.6 shows a comparative listing of the clock generation circuit specifications and Table 2.7 shows a comparative

listing of the clock generation circuit registers.

Table 2.6 Comparative Listing of Clock Generation Circuit Specifications

Item

Uses

Operating frequencies

Main clock ocillator

PLL

RX62T





Generates the system clock (ICLK) supplied to the CPU, DTC,

ROM, and RAM.

MTU3, GPT,



Generates the peripheral module clocks

(PCLK) supplied to the peripheral modules.

IWDT-dedicated clock (IWDTCLK) supplied to the IWDT.



ICLK: 8 MHz to 100 MHz



PCLK: 8 MHz to 50 MHz



IWDTCLK: 125 kHz



Resonator frequency: 8 MHz to

12.5 MHz



External clock input frequency: 8 MHz to

12.5 MHz



Connectable resonator or additional circuit: Ceramic resonator, crystal resonator



Connection pins: EXTAL, XTAL



Oscillation stop detection function:

When main clock oscillation stop is detected, the system clock source is switched to an internally generated clock, and the MTU3 and GPT pins can be forcedly driven to high-impedance.



Input clock source: Main clock



Input frequency: 8 MHz to 12.5 MHz



Frequency multiplication ratio: 8



Oscillation frequency: 64 MHz to 100

MHz



RX23T



Generates the system clock (ICLK) supplied to the CPU, DTC, ROM, and

RAM.



Generates the peripheral module clocks

(PCLKA, PCLKB, and PCLKD) supplied to the peripheral modules.



Generates the IWDT-dedicated clock

(IWDTCLK) supplied to the IWDT.



Generates the FlashIF clock (FCLK) supplied to the FlashIF.



Generates the CAC clock (CACCLK) supplied to the CAC.



ICLK: 40 MHz (max.)



PCLKA: 40 MHz (max.)



PCLKB: 40 MHz (max.)



PCLKD: 40 MHz (max.)



FCLK: 1 MHz to 32 MHz (ROM)



CACCLK: Same frequency as each oscillator



IWDTCLK: 15 kHz



esonator frequency: 1 MHz to 20 MHz



External clock input frequency: 20 MHz

(max.)



Connectable resonator or additional circuit: Ceramic resonator, crystal resonator



Connection pins: EXTAL, XTAL



Oscillation stop detection function:

When main clock oscillation stop is detected, the system clock source is switched to LOCO , and MTU output can be forcedly driven to high-impedance.



Drive capacity switching function



Input clock source: Main clock



Input division ratio: Selectable among

1, 2, and 4



Input frequency: 4 MHz to 12.5 MHz



Frequency multiplication ratio:

Selectable from 4 to 10 (increments of

0.5)



Oscillation frequency: 24 MHz to 40

MHz

Oscillation frequency: 32 MHz High-speed onchip oscillator

(HOCO)

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 7 of 55


Item

Low-speed onchip oscillator

(LOCO)

IWDT-dedicated on-chip oscillator

Internal oscillator circuit used when main clock oscillator is stopped

RX62T



Oscillation frequency: 125 kHz

Oscillation frequency of internal oscillator circuit when oscillation stop detected:

0.5 MHz to 7.0 MHz

RX23T

Oscillation frequency: 4 MHz

Oscillation frequency: 15 kHz



R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 8 of 55


Table 2.7 Comparative Listing of Clock Generation Circuit Registers

Register

SCKCR

SCKCR3

PLLCR

PLLCR2

MOSCCR

LOCOCR

ILOCOCR

HOCOCR

HOCOWTCR

OSCOVFSR

OSTDCR

OSTDSR

MOSCWTCR

MOFCR

MEMWAIT

Bit RX62T RX23T

PCK[3:0] Peripheral module clock select bits



PCKA[3:0]



Peripheral module clock A (PCLKA) select bits

PCKB[3:0]



Peripheral module clock B (PCLKB) select bits

PCKD[3:0]



Peripheral module clock D (PCLKD) select bits

FCK[3:0]



CKSEL[2:0]



PLIDIV[1:0]



FlashIF clock (FCLK) select bits

Clock source select bits

PLL input frequency division ratio select bits

STC[5:0]



Frequency multiplication factor select bits

PLLEN

MOSTP

LCSTP

ILCSTP









PLL stop control bit

Main clock oscillator stop bit

LOCO stop bit

IWDT-dedicated on-chip oscillator stop bit

HCSTP



HSTS[2:0]



HOCO stop

High-Speed On-Chip Oscillator oscillation stabilization wait time

MOOVF



Main clock oscillation stabilization flag

PLOVF



PLL clock oscillation stabilization flag

HCOVF



HOCO clock oscillation stabilization flag

OSTDIE



Oscillation stop detection interrupt enable bit

OSTDF Oscillation stop detection flag

KEY[7:0]

OSTDF

OSTDCR key code



MSTS[4:0]





Oscillation stop detection flag

MODRV21



Main clock oscillator wait time setting bits

Main clock oscillator drive capability switch bit

MOSEL



MEMWAIT



Main clock oscillator switch bit

Memory wait cycle setting bit

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 9 of 55


2.5 Low Power Consumption Functions

Table 2.8 shows a comparative listing of the low power consumption functions and Table 2.9 shows a comparative

listing of the low power consumption function registers.

Table 2.8 Comparative Listing of Low Power Consumption Functions

Item

Reduction of power consumption by clock switching

Module stop function

Function for transition to low power consumption mode

Low power consumption modes

Operating power reduction function

RX62T

The frequency division ratio can be set independently for the system clock

(ICLK) and peripheral module clock

(PCLK).

Each peripheral module can be stopped independently.

It is possible to transition to a low power consumption mode in which the

CPU, peripheral modules, or oscillators are stopped.



Sleep mode



All-module clock stop mode



Software standby mode



Deep software standby mode



RX23T

The frequency division ratio can be set independently for the system clock

(ICLK), high-speed peripheral module clock (PCLKA), peripheral module clock (PCLKB), S12AD clock (PCLKD), and FlashIF clock (FCLK) .

Each peripheral module can be stopped independently.

It is possible to transition to a low power consumption mode in which the

CPU, peripheral modules, or oscillators are stopped.



Sleep mode



Software standby mode



Deep sleep mode



Power consumption can be reduced in normal operation, sleep mode, and deep sleep mode by selecting an appropriate operating power control mode according to the operating frequency and operating voltage.



Operating power control modes: 2



High-speed operating mode



Low-speed operating mode

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 10 of 55


Table 2.9 Comparative Listing of Low Power Consumption Function Registers

Register

SBYCR

MSTPCRA

Bit

STS[4:0]

MSTPA4

MSTPA5

MSTPA7

RX62T

Standby timer select bits





RX23T



8-bit timer 3 and 2 (unit 1) module stop setting bit

8-bit timer 1 and 0 (unit 0) module stop setting bit



MSTPA16

MSTPA17

MSTPA19

MSTPA23

General PWM timer module stop setting bit

12-bit A/D converter (unit 1) module stop setting bit

12-bit A/D converter (unit 0) module stop setting bit





12-bit A/D converter module stop setting bit

D/A converter (DA) for generating comparator C reference voltage module stop setting bit



MSTPCRB

MSTPCRC

MSTPA24

ACSE

MSTPB0

MSTPB6

MSTPB7

MSTPB10

MSTPB17

MSTPB21

MSTPB26

MSTPB29

MSTPB31

MSTPC19

10-bit A/D converter module stop setting bit

12-bit A/D converter control section module stop setting bit

All-module clock stop mode mode enable bit

CAN module stop setting bit



LIN module stop setting bit



Serial peripheral interface module stop setting bit

I

2

C bus interface module stop setting bit



Serial communication interface 2 module stop setting bit














DOC module stop setting bit

Comparator C module stop setting bit

Serial peropheral interface 0 module stop setting bit

I

2

C bus interface 0 module stop setting bit




DPSBYCR

DPSWCR

DPSIER

DSLPE

IOKEEP

DPSBY

DIRQ0E

DIRQ1E

DLVDE

DNMIE



I/O port retention bit

Deep software standby bit

WTSTS[5:0] Deep software standby waiting time setting bits

IRQ0 pin enable bit

IRQ1 pin enable bit

LVD deep standby cancel signal enable bit

NMI pin enable bit

Clock frequency accuracy measurement circuit module stop setting bit

Deep sleep mode enable bit















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Jan 14, 2016

Page 11 of 55

RX23T Group, RX62T Group

Register

DPSIFR

DPSIEGR

RSTSR

DPSBKRy

OPCCR

Bit

DIRQ0F

DIRQ1F

DLVDF

DNMIF

DIRQ0EG

DIRQ1EG

DNMIEG

PORF

LVD1F

LVD2F

DPSRSTF

OPCM[2:0]

OPCMTSF


RX62T

IRQ0 deep standby cancel flag

IRQ1 deep standby cancel flag

LVD deep standby cancel flag

NMI deep standby cancel flag

IRQ0 edge select bit

IRQ1 edge select bit

NMI edge select bit

Power-on reset flag

LVD1 detection flag

LVD2 detection flag


Deep software standby backup register











RX23T



















Operating power control mode select bits

Operating power control mode transition status flag

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Jan 14, 2016

Page 12 of 55


2.6 Interrupt Controller

Table 2.10 shows a comparative listing of the interrupt controller specifications and Table 2.11 shows a comparative

listing of the interrupt controller registers.

Table 2.10 Comparative Listing of Interrupt Controller Specifications

Item

Interrupt

Nonmaskable interrupts

Peripheral function interrupts

External pin interrupts

RX62T (ICU)



Interrupts from peripheral modules



Sources: 101



Interrupt detection: Edge detection/level detection

Edge detection or level detection is determined independently for each source of the connected peripheral modules.



Interrupts from pins IRQ0 to

IRQ7



Sources: 8



Interrupt detection: One detection method among low level, falling edge, rising edge, and rising and falling edges can be set for each source.

RX23T (ICUb)



Interrupts from peripheral modules



Sources: 76



Interrupt detection: Edge detection/level detection

Edge detection or level detection is determined independently for each source of the connected peripheral modules.



Interrupts from pins IRQ0 to

IRQ5



Sources: 6



Interrupt detection: One detection method among low level, falling edge, rising edge, and rising and falling edges can be set for each source.



Digital filter function: Supported



Interrupt generated by writing to a register.



Source: 1

Priority is specified by register settings.

Faster interrupt processing by the

CPU can be specified only for a single interrupt source.

Software interrupt



Interrupt generated by writing to a register.



Source: 1

Interrupt priority level

Fast interrupt function

Priority is specified by register settings.

Faster interrupt processing by the

CPU can be specified only for a single interrupt source.

DTC control DTC activation sources: 87

(78 peripheral function interrupts + 8 external pin interrupts + 1 software interrupt)

NMI pin interrupt



Interrupt from the NMI pin



Interrupt detection:

Falling edge/rising edge

DTC activation sources: 52

( 45 peripheral function interrupts + 6 external pin interrupts + 1 software interrupt)



Interrupt from the NMI pin



Interrupt detection:

Falling edge/rising edge



Digital filter function: Supported

Interrupt at oscillation stop detection Interrupt at oscillation stop detection Oscillation stop detection interrupt

IWDT underflow/refresh error









Interrupt at an underflow of the down counter or at the occurrence of a refresh error

Voltage monitoring interrupt of voltage monitoring circuit 1 (LVD1)

Voltage monitoring interrupt of voltage monitoring circuit 2 (LVD2)

Voltage monitoring interrupt

Interrupt during power voltage fall detection



R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 13 of 55


Item

Return from low power consumption modes


RX62T (ICU)



Sleep mode: Return is initiated by a non-maskable interrupt or any other interrupt source.



All-module clock stop mode:

Return is initiated by a nonmaskable interrupts, interrupt

IRQ7 to IRQ0, or WDT interrupt.



Software standby mode: Return is initiated by a non-maskable interrupt or interrupt IRQ7 to

IRQ0.

RX23T (ICUb)



Sleep mode: Return is initiated by a deep sleep mode , nonmaskable interrupt, or any other interrupt source.



Software standby mode: Return is initiated by a non-maskable interrupt or interrupt IRQ5 to

IRQ0.

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 14 of 55


Table 2.11 Comparative Listing of Interrupt Controller Registers

Register

IRQFLTE0

NMISR

NMIER

NMICLR

NMIFLTE

NMIFLTC

Bit

FLTEN0

FLTEN1

RX62T (ICU)





FLTEN2

FLTEN3







FLTEN4

FLTEN5



IRQFLTC0 FCLKSEL0[1:0]



FCLKSEL1[1:0]

FCLKSEL2[1:0]

FCLKSEL3[1:0]

FCLKSEL4[1:0]

FCLKSEL5[1:0]

IWDTST

LVDST

LVD1ST

LVD2ST

IWDTEN

LVDEN

LVD1EN

LVD2EN













IWDTCLR

LVD1CLR





LVD2CLR

NFLTEN





NFCLKSEL[1:0]



RX23T (ICUb)

IRQ0 digital filter enable bit






IRQ0 digital filter sampling clock setting bits






IWDT underflow/refresh error status flag



Voltage monitoring interrupt status flag







Voltage monitoring interrupt enable bit



Voltage monitoring 1 interrupt status flag

Voltage monitoring 2 interrupt status flag

IWDT underflow/refresh error enable bit





Voltage monitoring 1 interrupt enable bit

Voltage monitoring 2 interrupt enable bit

IWDT clear bit

LVD1 clear bit

LVD2 clear bit

NMI digital filter enable bit

NMI digital filter sampling clock setting bits

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2.7 Bus

Table 2.12 shows a comparative listing of the bus specifications and Table 2.13 shows a comparative listing of the bus

registers.

Table 2.12 Comparative Listing of Bus Specifications

Item RX62T

CPU bus Instruction bus



Connected to the CPU (for

Operand bus instructions).



Connected to the on-chip memory

(on-chip RAM and on-chip ROM).



Operates in synchronization with the system clock (ICLK).



Connected to the CPU (for operand).








Memory buses

Memory bus 1 Connected to the RAM.

Internal main buses

Internal peripheral buses

Memory bus 2 Connected to the ROM.

Internal main bus 1



Connected to the CPU.



Operates in synchronization with

Internal main bus 2 the system clock (ICLK).



Connected to the DTC.




Internal peripheral bus

1







Connected to peripheral modules

(interrupt controller and bus error monitoring section).



Operates in synchronization with


2 the system clock (ICLK).




(WDT, CMT, CRC, SCI, etc.)



Operates in synchronization with the peripheral module clock

(PCLK).


3


4


6






(MTU3, GPT ).






Connected to the on-chip ROM

(P/E) and data flash memory.




(PCLK).

RX23T



Connected to the CPU (for instructions).










Connected to the CPU (for operand).








Connected to the RAM.

Connected to the ROM.



Connected to the CPU.






Connected to the DTC.











( DTC , interrupt controller, and bus error monitoring section).







(modules other than those connected to internal peripheral buses 1, 3, and 4) .




(PCLKB) .




(CMPC).




(PCLKB).




(MTU3).




(PCLKA) .



Connected to the flash control module.



Operates in synchronization with the FlashIF clock (FCLK) .

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Table 2.13 Comparative Listing of Bus Registers

Register

BEREN

BERSR1

BUSPRI

Bit

TOEN

TO

BPRA[1:0]

RX62T







BPRO[1:0]

BPIB[1:0]

BPGB[1:0]

BPHB[1:0]

BPFB[1:0]











RX23T

Timeout detection enable bit

Timeout bit

Memory bus 1 (RAM) priority control bits

Memory bus 2 (ROM) priority control bits

Internal peripheral bus 1 priority control bits

Internal peripheral bus 2 and 3 priority control bits



2.8 Memory Protection Unit

Table 2.14 shows a comparative listing of the memory protection unit registers.

Table 2.14 Comparative Listing of Memory Protection Unit Registers

Register

MPESTS

Bit

IA

IMPER

RX62T

Instruction memory protection error generated bit



RX23T



DA

Instruction memory protection error generated bit



DMPER

Data memory protection error generated bit



Data memory protection error generated bit

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2.9 Data Transfer Controller

Table 2.15 shows a comparative overview of the data transfer controller and Table 2.16 shows a comparative listing of

the data transfer controller registers.

Table 2.15 Comparative Overview of Data Transfer Controller

Item RX62T (DTC)

Transfer modes



Normal transfer mode

A single activation leads to a single data transfer.



Repeat transfer mode


The transfer address is returned to the transfer start address after a number of data transfers corresponding to the repeat size.

The maximum repeat size is 256 data units.



Block transfer mode

A single activation leads to the transfer of a single block.

The maximum block size is 255 data units.

Transfer channels



Channel transfer corresponding to the interrupt source is possible (transferred by DTC activation request from the

ICU).



Data of multiple channels can be

Transfer space

Data transfer units

CPU interrupt requests transferred on a single activation source (chain transfer).



Either “executed when the counter is 0” or “always executed” can be selected for chain transfer.



16 MB in short-address mode

(areas from 0000 0000h to 007F

FFFFh and FF80 0000h to FFFF

FFFFh, excepting reserved areas)



4 GB in full-address mode

(area from 0000 0000h to FFFF FFFFh, excepting reserved areas)



1 data unit: 1 byte (8 bits), 1 word (16 bits), or 1 longword (32 bits)



Number of data units per block:

1 to 255



An interrupt request can be generated to the CPU on a DTC activation interrupt.



An interrupt request can be generated to the CPU after a single data transfer.



An interrupt request can be generated to the CPU after data transfer of a specified number of data units.

Read skip Transfer data read skip can be enabled.

RX23T (DTCa)



Normal transfer mode




Repeat transfer mode


The transfer address is returned to the transfer start address after a number of data transfers corresponding to the repeat size.

The maximum repeat size is 256 data units.



Block transfer mode

A single activation leads to the transfer of a single block.

The maximum block size is 256 data units.



Channel transfer corresponding to the interrupt source is possible (transferred by DTC activation request from the

ICU).



Data of multiple channels can be transferred on a single activation source (chain transfer).



Either “executed when the counter is 0” or “always executed” can be selected for chain transfer.



16 MB in short-address mode

(areas from 0000 0000h to 007F

FFFFh and FF80 0000h to FFFF

FFFFh, excepting reserved areas)



4 GB in full-address mode

(area from 0000 0000h to FFFF FFFFh, excepting reserved areas)



1 data unit: 1 byte (8 bits), 1 word (16 bits), or 1 longword (32 bits)



Number of data units per block:

1 to 256



An interrupt request can be generated to the CPU on a DTC activation interrupt.



An interrupt request can be generated to the CPU after a single data transfer.



An interrupt request can be generated to the CPU after data transfer of a specified number of data units.

Transfer data read skip can be enabled.

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Item RX62T (DTC)

Write-back skip

When “fixed” is selected as the transfer source address or transfer destination address, write-back skip execution is supported.


It is possible to specify the module stop state.

RX23T (DTCa)

When “fixed” is selected as the transfer source address or transfer destination address, write-back skip execution is supported.


Table 2.16 Comparative Listing of Data Transfer Controller Registers

Register

DTCVBR

Bit





RX62T (DTC)

DTC vector base address

(lower 12 bits)


(upper 20 bits)

RX23T (DTCa)


(lower 10 bits)


(lower 22 bits)

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2.10 I/O Ports

Table 2.17 shows a comparative listing of the I/O port registers.

Table 2.17 Comparative Listing of I/O Port Registers

Register

PDR

Bit

B0 to B7

RX62T



PODR

PIDR

B0 to B7

B0 to B7





PMR

ODR0

ODR1

PCR

DSCR

DDR

DR

PORT

ICR

B0 to B7



B0, B2, B4, B6



B0, B2, B4, B6



B0 to B7



B0 to B7

B0 to B7

B0 to B7

B0 to B7

B0 to B7

PFCMTU MTUS0

MTUS1

TCLKS[1:0]

PFDGPT

PFGSPI

GPTS

RSPCKE

MOSIE

MISOE

PFHSPI

PFJCAN

SSL0E

SSL1E

SSL2E

SSL3E

RSPIS[1:0]

CANE

CANS[1:0]

LINE PFKLIN

PFMPOE POE0E

POE8E

POE10E



Pn0 to Pn7 I/O select bits

Note: n = 1 to 3, 7, 9, A, B, D, E

Pn0 to Pn7 output data storage bits

Note: n = 1 to 3, 7, 9, A, B, D, E

Pn0 bit

Note: n = 1 to 4, 7, 9, A, B, D, E

Pn0 input buffer control bits

Note: n = 1 to 4, 7, 9, A, B, D

MTU3 pin select 0 bit

MTU3 pin select 1 bit

MTCLK pin select bits

GPT pin select bit

RSPCK output enable bit

MOSI output enable bit

MISO output enable bit

SSL0 output enable bit




RSPI pin select bits

CAN pin enable bit

CAN pin select bits

LIN pin enable bit

POE0# input enable bit









































RX23T

Pm0 to Pm7 direction control bits

Note: m = 0 to 4, 7, 9, A, B, D

Pm0 to Pm7 output data storage bits

Note: m = 0 to 4, 7, 9, A, B, D

Pm0 to Pm7 bits

Note: m = 0 to 4, 7, 9, A, B, D,

Pm0 to Pm7 pin mode control bits

Note: m = 0 to 3, 7, 9, A, B, D,

Pm0 to Pm3 output type select bits

Note: m = 0 to 3, 7, 9, A, B, D

Pm4 to Pm7 output type select bits

Note: m = 2, 3, 7, 9, A, B, D

Pm0 to Pm7 input pull-up resistor control bits

Note: m = 0 to 4, 7, 9, A, B, D

Pm0 to Pm7 drive capacity control bits

Note: m = 0 to 3, 7, 9, A, B, D







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2.11 Multi-Function Timer Pulse Unit 3

Table 2.18 shows a comparative overview of multi-function timer pulse unit 3 and Table 2.19 shows a comparative

listing of the multi-function timer pulse unit 3 registers.

Table 2.18 Comparative Overview of Multi-Function Timer Pulse Unit 3

Item RX62T (MTU3)

Pulse input/output

Maximum 24

Pulse input 3

Count clocks 6 to 8 clocks for each channel

(4 clocks for channel 5)

8 to 100 MHz

RX23T (MTU3c)

Maximum 16

3

11 clocks for each channel

(14 clocks for MTU0, 12 clocks for MTU1 and

MTU2, and 10 clocks for MTU5, and four clocks for MTU1 & MTU2 (LWA = 1))

Up to 40 MHz Opearting frequency

Available operations

[MTU0 to MTU4, MTU6, and MTU7 ]



Waveform output on compare match



Input capture function



Counter-clearing operation



Simultaneous writing to multiple timer counters (TCNT)



Simultaneous clearing on compare match or input capture



Simultaneous input and output to registers in synchronization with counter operations



Up to 12-phase PWM output in combination with synchronous operation

[MTU0, MTU3, MTU4, MTU6, and MTU7 ]

Buffer operation specifiable

[MTU1 and MTU2]



Phase counting mode can be specified independently.



Cascade connection operation available

[MTU3, MTU4, MTU6, and MTU7 ]



Through interlocked operation of

MTU3/MTU4 and MTU6/MTU7 , the positive and negative signals in six phases, for a total of 12 phases , can be output in complementary PWM and reset

PWM operation.



In complementary PWM mode, transfer of values from buffer registers to temporary registers is supported at peaks and troughs of the timer-counter values or when writing to the buffer registers

(MTU4.TGRD and MTU7.TGRD

).



Double-buffering is selectable in complementary PWM mode.

[MTU0 to MTU4]



Waveform output on compare match



Input capture function (noise filter setting available)



Counter-clearing operation



Simultaneous writing to multiple timer counters (TCNT)



Simultaneous clearing on compare match or input capture



Simultaneous input and output to registers in synchronization with counter operations



Up to 12-phase PWM output in combination with synchronous operation

[MTU0, MTU3, and MTU4]

Buffer operation specifiable

[MTU1 and MTU2]



Phase counting mode can be specified independently.



Cascade connection operation available

[MTU3 and MTU4]



Through interlocked operation of

MTU3/MTU4, the positive and negative signals in six phases, for a total of 6 phases, can be output in complementary

PWM and reset PWM operation.



In complementary PWM mode, transfer of values from buffer registers to temporary registers is supported at peaks and troughs of the timer-counter values or when writing to the buffer registers

(MTU4.TGRD).



Double-buffering is selectable in complementary PWM mode.

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Item

Available operations

Interrupt skipping function

RX62T (MTU3)

[MTU3 and MTU4]

Through interlocking with MTU0, a mode for driving AC synchronous motors (brushless

DC motors) by using complementary PWM output and reset PWM output can be enabled, allowing the selection between two types of waveform output (chopping or level).

[MTU5]

Support for operation as a dead-time compensation counter

In complementary PWM mode, interrupts at counter peaks and troughs and triggers to start conversion by the A/D converter can be skipped.

38

RX23T (MTU3c)

[MTU3 and MTU4]

Through interlocking with MTU0, a mode for driving AC synchronous motors (brushless

DC motors) by using complementary PWM output and reset PWM output can be enabled, allowing the selection between two types of waveform output (chopping or level).

[MTU5]

Support for operation as a dead-time compensation counter

In complementary PWM mode, interrupts at counter peaks and troughs and triggers to start conversion by the A/D converter can be skipped.

28 Interrupt sources

Buffer operation

Trigger generation


Automatic transfer of register data (transfer from the buffer register to the timer register)

A/D converter start triggers can be generated.

An A/D converter start request delaying function enables the A/D converter to be started at user-defined timing and to be synchronized with PWM output.


Automatic transfer of register data (transfer from the buffer register to the timer register)

A/D converter start triggers can be generated.

An A/D converter start request delaying function enables the A/D converter to be started at user-defined timing and to be synchronized with PWM output.


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Table 2.19 Comparative Listing of Multi-Function Timer Pulse Unit 3 Registers

Register

TCR2

TMDR2B

TMDR3

TSR

TSYCR

TCNTLW

TGRnLW

(n = A or B)

TCSYSTR

TRWERB

TOCR1B

TOCR2B

TOLBRB

TCNTSB

TCDRB

TCBRB

TDDRB

Bit

TPSC2[2:0]

PCB[1:0]

DRS

LWA

PHCKSEL

TGFA

TGFB

TGFC

TGFD

TCFV

TCFU

CE2B

CE2A

CE1B

CE1A

CE0D

CE0C

CE0B

CE0A





SCH7

SCH6

RWE

OLSP

OLSN

TOCS

TOCL

PSYE

OLS1P

OLS1N

OLS2P

OLS2N

OLS3P

OLS3N

BF[1:0]

OLS1P

OLS1N

OLS2P

OLS2N

OLS3P

OLS3N









RX62T (MTU3)





RX23T (MTU3c)

Timer prescaler select bits

Phase counting mode function

Double buffer select bit



 expansion control bits



Longword access control bit

External input phase clock select bit

Input capture/output compare flag A



Input capture/output compare flag B



Input capture/output compare flag C



Input capture/output compare flag D



Overflow flag



Underflow flag

Clear enable 2B bit

Clear enable 2A bit

Clear enable 1B bit

Clear enable 1A bit

Clear enable 0D bit

Clear enable 0C bit

Clear enable 0B bit



















Clear enable 0A bit





Timer longword counter

Timer longword general register

Synchronous start 7 bit

Synchronous start 6 bit

Read/write enable bit







Output level select P bit

Output level select N bit







TOC select bit

TOC register write protection bit



PWM synchronous output enable bit



Output level select 1P bit

Output level select 1N bit

















TOLBR buffer transfer timing select

 bits







Timer subcounter

Timer cycle data register

Timer cycle buffer register

Timer dead time data register





















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Register

TDERB

TBTERB

TWCRA

TWCRB

NFCRn

(n = 0 to 4, C)

NFCR5

TITMRB

TITCR1B

TITCNT1B

TITCR2B

TITCNT2B

TADSTRGR0

Bit

TDER

BTE[1:0]

RX62T (MTU3)

Dead time enable bit

Buffer transfer disable and interrupt skipping link setting bits

SCC

WRE

SCC

Synchronous clearing control bit

Waveform retain enable bit

Synchronous clearing control bit









CCE

NFAEN

NFBEN

NFCEN

NFDEN

NFCS[1:0]

Compare match clear enable bit













Noise filter A enable bit

Noise filter B enable bit

Noise filter C enable bit

Noise filter D enable bit

Noise filter clock select bits

NFUEN Noise filter U enable bit

NFVEN

NFWEN

NFCS[1:0]

TITM

T4VCOR[2:0]





TCIV4 interrupt skipping count

Noise filter V enable bit

Noise filter W enable bit




Interrupt skipping function select bit



 setting bits

RX23T (MTU3c)





T4VEN

T3ACOR[2:0]

T4VEN bit

TCIV3 interrupt skipping count setting bits





T3AEN

T4VCNT[2:0]

T3ACNT[2:0]

TRG4COR

[2:0]

T3AEN bit

TGIA4 interrupt counter bits

TGIA3 interrupt counter bits

TRG4AN/TRG4BN interrupt skipping count setting bits









TRG4CNT

[2:0]

TADSTRS0

[4:0]

TRG4AN/TRG4BN interrupt counter bits





A/D conversion start request select for ADSM0 pin output frame synchronization signal generation select bits

R01AN2823EJ0110_RX23T Rev.1.10

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2.12 Port Output Enable 3

Table 2.20 shows a comparative overview of port output enable 3 and Table 2.21 shows a comparative listing of the

port output enable 3 registers.

Table 2.20 Comparative Overview of Port Output Enable 3

Item

Target pins to be placed in high-impedance state

Conditions for highimpedance state

RX62T (POE3)



MTU output pins

MTU0 pins ( MTIOC0A-A,

MTIOC0A-B, MTIOC0B-A,

MTIOC0B-B, MTIOC0C, MTIOC0D)

MTU3 pins (MTIOC3B, MTIOC3D)

MTU4 pins (MTIOC4A, MTIOC4B,

MTIOC4C, MTIOC4D)

MTU6 pins (MTIOC6B, MTIOC6D)


MTIOC7C, MTIOC7D)



GPT output pins

GPT0 pins (GTIOC0A-A, GTIOC0B-

A, GTIOC0A-B, GTIOC0B-B)





GPT3 pins (GTIOC3A, GTIOC3B)



Change to input pin

When input is received on POE0#,

POE4#, POE8#, POE10#, or

POE11#



Shorting of output pins

When a match (short circuit) occurs between the output signal levels

(active level) over one or more cycles on the following combination of pins:

1. MTIOC3B and MTIOC3D

2. MTIOC4A and MTIOC4C





7. GTIOC0A-A and GTIOC0B-A





When a register setting is made



When clock generation circuit oscillation stop is detected



When comparator detection occurs in the comparator (S12ADA)

RX23T (POE3b)



MTU output pins


MTIOC0C, MTIOC0D)

MTU3 pin (MTIOC3B, MTIOC3D)

MTU4 pin (MTIOC4A, MTIOC4B,

MTIOC4C, MTIOC4D)



Change to input pin

When input is received on POE0#,

POE8#, or POE10#



Shorting of output pins

When a match (short circuit) occurs between the output signal levels

(active level) over one or more cycles on the following combination of pins:






When a register setting is made



When clock generation circuit oscillation stop is detected



When comparator detection occurs in the comparator (CMPC)

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Item

Functions


RX62T (POE3)



Each of the POE0#, POE4#,

POE8#, POE10#, and POE11# input pins can be set for falling edge, PCLK/8



16, PCLK/16



16, or PCLK/128



16 low-level sampling.



Pins for the MTU complementary

PWM output, MTU0 pins, and GPT pins can be placed in the highimpedance state by the POE0#,

POE4# , POE8#, POE10#, or

POE11# pin falling-edge or lowlevel sampling.




PWM output, MTU0 pins, and GPT pins can be placed in the highimpedance state when the oscillation-stop detection circuit in the clock pulse generator detects stopped oscillation.




PWM output or the GPT largecurrent output pins can be placed in the high-impedance state when output levels of the MTU complementary PWM output pins or the GPT large-current output pins are compared and simultaneous active-level output continues for one cycle or more.




PWM output, MTU0 pins, and GPT pins can be placed in the highimpedance state in response to comparator detection by the 12-bit

A/D converter (S12ADA).




PWM output, MTU0 pins, and GPT pins can be placed in the highimpedance state by modifying settings in the POE3 registers.



Interrupts can be generated by input-level sampling or output-level comparison results.

RX23T (POE3b)



Each of the POE0#, POE8#, and

POE10# input pins can be set for falling edge, PCLK/8



16, PCLK/16



16, or PCLK/128



16 low-level sampling.




PWM output and MTU0 pins can be placed in the high-impedance state by the POE0#, POE8#, or POE10# pin falling-edge or low-level sampling.




PWM output and MTU0 pins can be placed in the high-impedance state when oscillation stop is detected by the oscillation stop detection function of the clock generator.




PWM output can be placed in the high-impedance state when output levels of the MTU complementary

PWM output pins are compared and simultaneous active-level output continues for one cycle or more.




PWM output and MTU0 pins can be placed in the high-impedance state in response to comparator detection by the comparator (CMPC) .




PWM output and MTU0 pins can be placed in the high-impedance state by modifying the settings in the

POE3 registers.



Interrupts can be generated by input-level sampling or output-level comparison results.

R01AN2823EJ0110_RX23T Rev.1.10

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Table 2.21 Comparative Listing of Port Output Enable 3 Registers

Register

ICSR2

OCSR2

ICSR5

ICSR6

ALR1

SPOER

POECR1

Bit

POE4M[1:0]

PIE2

POE4F

OIE2

OCE2

OSF2

POE11M[1:0]

PIE5

POE11E

POE11F

OSTSTE

OSTSTF

OLSG0A

OLSG0B

OLSG1A

OLSG1B

OLSG2A

OLSG2B

MTUCH67HIZ

GPT01HIZ

GPT23HIZ

MTU0AZE

MTU0BZE

MTU0CZE

MTU0DZE

MTU0A1ZE

MTU0B1ZE

MTU0B2ZE

MTU0C1ZE

RX62T (POE3)

POE4 mode select bits

RX23T (POE3b)





Port interrupt enable bit

POE4 flag



Output short interrupt enable 2 bit



Output short high-impedance

 enable 2 bit

Output short flag 2

POE11 mode select bits

Port interrupt enable bit





POE11 high-impedance enable bit



POE11 flag







OSTST high-impedance enable



MTIOC3B/ GTIOC0A-A active level setting bit

MTIOC3D/ GTIOC0B-A active level setting bit

MTIOC4A/ GTIOC1A-A active level setting bit

MTIOC4C/ GTIOC1B-A active level setting bit

MTIOC4B/ GTIOC2A-A active level setting bit

MTIOC4D/ GTIOC2B-A active level setting bit

MTU6 and MTU7 output highimpedance enable bit

GPT0 and GPT1 output highimpedance enable bit

GPT2 and GPT3 output highimpedance enable bit

MTU CH0A high-impedance enable bit

MTU CH0B high-impedance enable bit

MTU CH0C high-impedance enable bit

MTU CH0D high-impedance enable bit







 bit

OSTST high-impedance flag

MTIOC3B active level setting bit

MTIOC3D active level setting bit

MTIOC4A active level setting bit

MTIOC4C active level setting bit

MTIOC4B active level setting bit

MTIOC4D active level setting bit







MTIOC0A PB3

MTIOC0B PB2

MTIOC0C PB1

MTIOC0D PB0

pin highimpedance enable bit




MTIOC0A P31 pin highimpedance enable bit

MTIOC0B P30 pin highimpedance enable bit

MTIOC0B P93 pin highimpedance enable bit

MTIOC0C P94 pin highimpedance enable bit

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Register

POECR2

POECR3

POECR4

POECR5


Bit

MTU7BDZE

MTU7ACZE

MTU6BDZE

MTU4BDZE

MTU4ACZE

RX62T (POE3)

MTU CH7BD high-impedance enable bit

MTU CH7AC high-impedance enable bit



MTU CH4AC high-impedance enable bit

MTU3BDZE

GPT0ABZE

GPT1ABZE

GPT2ABZE


GPT CH0AB high-impedance enable bit



GPT3ABZE GPT CH3AB high-impedance enable bit

CMADDMT34ZE MTU CH34 high-impedance

CFLAG add bit

IC2ADDMT34ZE MTU CH34 high-impedance

POE4F add bit


POE8F add bit


POE10F add bit


POE11F add bit


CFLAG add bit


POE0F add bit


POE8F add bit


POE10F add bit


POE11F add bit


CFLAG add bit

IC1ADDMT0ZE

IC2ADDMT0ZE

MTU CH0 high-impedance

POE0F add bit

MTU CH0 high-impedance

POE4F add bit


POE10F add bit


POE11F add bit

RX23T (POE3b)







MTIOC4B/4D high-impedance enable bit

MTIOC4A/4C high-impedance enable bit

MTIOC3B/3D high-impedance enable bit









MTU3 and MTU4 high-impedance

CFLAG add bit




POE8F add bit


POE10F add bit













MTU0 high-impedance CFLAG add bit

MTU0 high-impedance POE0F add bit



MTU0 high-impedance

POE10F add bit



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Register

POECR6

Bit RX62T (POE3)

CMADDGPT01ZE GPT CH01 high-impedance

CFLAG add bit

IC1ADDGPT01ZE GPT CH01 high-impedance

POE0F add bit


POE4F add bit


POE8F add bit


POE11F add bit

CMADDGPT23ZE GPT CH23 high-impedance

CFLAG add bit


POE0F add bit


POE4F add bit


POE8F add bit

POECMPFR


C0FLAG

POE10F add bit



RX23T (POE3b)





















C1FLAG

C2FLAG

C3FLAG

POECMPSEL POEREQ0

POEREQ1

POEREQ2

POEREQ3















Comparator channel 0 detection flag




Comparator channel 0 POE request enable bit




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2.13 Independent Watchdog Timer

Table 2.22 shows a comparative overview of the independent watchdog timer and Table 2.23 shows a comparative

listing of the independent watchdog timer registers.

Table 2.22 Comparative Overview of Independent Watchdog Timer

Item

Count source

Clock division ratio

Counter operation

Conditions for starting the counter

Conditions for stopping the counter

Window function

Reset output sources

Non-maskable interrupt sources

Reading the counter value

Output signals

(internal signals)

RX62T (IWDT)

IWDT-dedicated clock (IWDTCLK)

Division by 1, 16, 32, 64, 128, or 256

Counting down using a 14-bit downcounter



Counting is started by refreshing the counter (writing 00h and then FFh to the IWDTRR register).







Reset (The down-counter and other registers return to their initial values.)

A counter underflows is generated.

Down-counter underflow

The down-counter value can be read by reading the IWDTSR register.



Reset output

RX23T (IWDTa)

IWDT-dedicated clock (IWDTCLK)

Division by 1, 16, 32, 64, 128, or 256

Counting down using a 14-bit downcounter



Counting starts automatically after a reset (auto-start mode).



Counting is started (register start mode) by refreshing the counter

(writing 00h and then FFh to the

IWDTRR register).



Reset (The down-counter and other registers return to their initial values.)



A counter underflows or a refresh error is generated.

Counting restarts. (In auto-start mode, counting restarts automatically after a reset or after a non-maskable interrupt request is output. In register start mode, counting restarts after a refresh.)

Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods).






Refresh occurring outside the refresh-permitted period (refresh error)






Refresh occurring outside the refresh-permitted period (refresh error)

The down-counter value can be read by reading the IWDTSR register.



Reset output



Interrupt request output



Sleep mode count stop control output

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Item

Auto-start mode

(controlled by option function select register 0

(OFS0))

RX62T (IWDT)



Register start mode

(controlled by the IWDT registers)



Selecting the clock frequency division ratio after a refresh

(IWDTCR.CKS[3:0] bits)



Selecting the timeout period of the independent watchdog timer

(IWDTCR.TOPS[1:0] bits)

RX23T (IWDTa)



Selecting the clock frequency division ratio after a reset

(OFS0.IWDTCKS[3:0] bits)




(OFS0.IWDTTOPS[1:0] bits)



Selecting the window start position in the independent watchdog timer

(OFS0.IWDTRPSS[1:0] bits)



Selecting the window end position in the independent watchdog timer

(OFS0.IWDTRPES[1:0] bits)



Selecting reset output or interrupt request output

(OFS0.IWDTRSTIRQS bit)



Selecting the down-count stop function at transition to sleep mode, software standby mode, or deep sleep mode (OFS0.IWDTSLCSTP bit)



Selecting the clock frequency division ratio after a refresh

(IWDTCR.CKS[3:0] bits)




(IWDTCR.TOPS[1:0] bits)



Selecting the window start position in the independent watchdog timer

(IWDTCR.RPSS[1:0] bits)



Selecting the window end position in the independent watchdog timer

(IWDTCR.RPES[1:0] bits)



Selecting reset output or interrupt request output

(IWDTRCR.RSTIRQS bit)



Selecting the down-count stop function at transition to sleep mode, software standby mode, or deep sleep mode (IWDTCSTPR.SLCSTP bit)

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Table 2.23 Comparative Listing of Independent Watchdog Timer Registers

Register

IWDTCR

Bit

RPES[1:0]

RPSS[1:0]

RX62T (IWDT)





IWDTSR

IWDTRCR

REFEF

RSTIRQS







IWDTCSTPR SLCSTP

OFS0 IWDTSTRT



IWDTTOPS[1:0]



IWDTCKS[3:0]



IWDTRPES[1:0]

IWDTRPSS[1:0]

IWDTRSTIRQS

IWDTSLCSTP









RX23T (IWDTa)

Window end position select bits

Window start position select bits

Refresh error flag

Reset interrupt request select bit

Sleep mode count stop control bit

IWDT start mode select bit

IWDT timeout period select bits

IWDT clock frequency division ratio select bits

IWDT window end position select bits

IWDT window start position select bits

IWDT reset interrupt request select bit

IWDT sleep mode count stop control bit

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2.14 Serial Communication Interface

Table 2.24 shows a comparative overview of the serial communication interface and Table 2.25 shows a comparative

listing of the serial communication interface registers.

Table 2.24 Comparative Overview of Serial Communication Interface

Item

Serial communication modes

Transfer speed

Full-duplex communication

I/O pins

Data transfer

Interrupt sources


RX62T (SCIb)



Asynchronous



Clock synchronous



Smart card interface

Bit rate specifiable by on-chip baud rate generator.



Transmitter: Continuous transmission possible using double-buffer configuration.



Receiver: Continuous reception possible using double-buffer configuration.



SCI/SMCI I/O pins

SCK0, RXD0, TKD0, SCK1,

RXD1, TXD1, SCK2, RXD2, and

TKD2

Selectable between LSB-first or

MSB-first transfer.

Transmit end, transmit data empty, receive data full, or receive error

The module stop state can be specified for each channel.

RX23T (SCIg)



Asynchronous



Clock synchronous



Smart card interface



Simple I

2

C bus



Simple SPI bus

Bit rate specifiable by on-chip baud rate generator.



Transmitter: Continuous transmission possible using double-buffer configuration.



Receiver: Continuous reception possible using double-buffer configuration.



SCI I/O pins (asynchronous mode and clock synchronous mode)

SCK1, RXD1, TXD1,

CTS1#/RTS1#, SCK5, RXD5,

TXD5, and CTS5#/RTS5#



SCI I/O pins (simple I

2

C mode)

SSCL1, SSDA1, SSCL5, and

SSDA5



SCI I/O pins (simple SPI mode)

SCK1, SMISO1, SMOSI1,

SS1#, SCK5, SMISO5,

SMOSI5, and SS5#

Selectable between LSB-first or

MSB-first transfer.

Transmit end, transmit data empty, receive data full, receive error

Completion of generation of start condition, restart condition, or stop condition (simple I

2

C mode)

The module stop state can be specified for each channel.

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Item

Synchronous mode

Data length

Transmission stop bits

Parity

Receive error detection

Hardware flow control

Clock synchronous mode

Smart card interface mode

Simple I mode

2

C

Data type

Communication

RX62T (SCIb)

7 or 8 bits

1 or 2 bits

Even parity, odd parity, or no parity

Parity, overrun, and framing errors

Error processing An error signal can be transmitted automatically when a parity error is detected during reception.

Data can be retransmitted automatically when an error signal is received during transmission.

Both direct convention and inverse convention are supported.

 format

Operatin mode



RX23T (SCIg)

7, 8, or 9 bits

1 or 2 bits

Even parity, odd parity, or no parity

Parity, overrun, and framing errors

Double-speed mode

Multi-processor communication function

Noise cancellation

Data length

Receive error detection

Hardware flow control







Start bit detection

Selectable between low level and falling edge.

Break detection When a framing error occurs, a break can be detected by reading

Clock source the RXDn pin level directly.



An internal or external clock can be selected.

Serial communication among multiple processors

The signal paths from input on the

RXDn pins incorporate on-chip digital noise filters.

8 bits

Overrun error

The CTSn# and RTSn# pins can be used to control transmission and reception.

Selectable between low level and falling edge.

When a framing error occurs, a break can be detected by reading the RXDn pin level directly.



An internal or external clock can be selected.



Transfer rate clock input from the TMR can be used (SCI5).

Baud rate generator double-speed mode is selectable.

Serial communication among multiple processors


RXDn pins incorporate on-chip digital noise filters.

8 bits

Overrun error

The CTSn# and RTSn# pins can be used to control transmission and reception.

An error signal can be transmitted automatically when a parity error is detected during reception.

Data can be retransmitted automatically when an error signal is received during transmission.

Both direct convention and inverse convention are supported.

I

2

C bus format

Transfer speed

Noise canceler





Master (single-master operation only)

Fast mode is supported.


SSCLn and SSDAn pins incorporate on-chip digital noise filters, and the noise cancellation bandwidth is adjustable.

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Item

Simple SPI mode

Data length

Error detection

SS input pin function

Clock settings

Bit rate modulation function

RX62T (SCIb)











RX23T (SCIg)

8 bits

Overrun error

Applying a high-level signal to the

SSn# pin causes the output pins to enter the high-impedance state.

Selectable among four clock phase and clock polarity settings.

On-chip baud rate generator output correction can reduce errors.

Table 2.25 Comparative Listing of Serial Communication Interface Registers

Register

RDRH

RDRL

RDRHL

TDRH

TDRL

TDRHL

SSR

SCMR

MDDR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SPMR

Bit













RDRF

TDRE

CHR1

ACS0

BRME

BGDM

NFCS[2:0]

IICM

IICDL[4:0]

IICINTM

IICCSC





IICACKT

IICSTAREQ





IICRSTAREQ



IICSTPREQ

IICSTIF

RX62T (SCIb)













Receive data full flag

Transmit data empty flag





















IICSDAS[1:0]



IICSCLS[1:0]



IICACKR

SSE

CTSE

MSS

MFF

CKPOL

CKPH















RX23T (SCIg)

Receive data register H

Receive data register L

Receive data register HL

Transmit data register H

Transmit data register L

Transmit data register HL





Character length 1 bit

Modulation duty register

Asynchronous mode clock source select bit

Bit rate modulation enable bit

Baud rate generator double-speed mode select bit


Simple I

2

C mode select bit

SSDA output delay select bits

I 2 C interrupt mode select bit

Clock synchronization bit

ACK transmission data bit

Start condition generation bit

Restart condition generation bit

Stop condition generation bit

Issuing of start, restart, or stop condition completed flag

SSDA output select bits

SSCL output select bits

ACK reception data flag

SSn# pin function enable bit

CTS enable bit

Master slave select bit

Mode fault flag

Clock polarity select bit

Clock phase select bit

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2.15 I

2

C bus interface

Table 2.26 shows a comparative overview of the I

2

C bus interface and Table 2.27 shows a comparative listing of the I

2

C bus interface registers.

Table 2.26 Comparative Overview of I

2

C Bus Interface

Item

Communication format

Transfer speed

SCL clock

RX62T (RIIC)



I

2

C bus format or SMBus format



Selectable between master mode or slave mode.



Automatic securing of the various setup times, hold times, and bus-free times for the transfer rate

RX23T (RIICa)



I

2

C bus format or SMBus format



Selectable between master mode or slave mode.



Automatic securing of the various setup times, hold times, and bus-free times for the transfer rate

Fast mode is supported (up to 400 kbps). Fast mode is supported (up to 400 kbps).

For master operation, the duty cycle of the

SCL clock is selectable in the range from

4% to 96%.

For master operation, the duty cycle of the

SCL clock is selectable in the range from

4% to 96%.

Issuing and detection

Start, restart, and stop conditions are generated automatically. Start conditions conditions (including restart conditions) and stop conditions are detectable.

Slave addresses



Up to three different slave addresses can be set.



7-bit and 10-bit address formats are supported (along with the use of both at once).



General call addresses, device ID addresses, and SMBus host addresses are detectable.

Acknowledgement



For transmission, the acknowledge bit is loaded automatically.

Transfer of the next data for transmission can be suspended automatically on reception of a notacknowledge bit.



For reception, the acknowledge bit is transmitted automatically.

If a wait between the eighth and ninth clock cycles has been selected, software control of the value in the acknowledge field in response to the received value is possible.

Start, restart, and stop conditions are generated automatically. Start conditions

(including restart conditions) and stop conditions are detectable.



Up to three different slave addresses can be set.



7-bit and 10-bit address formats are supported (along with the use of both at once).



General call addresses, device ID addresses, and SMBus host addresses are detectable.



For transmission, the acknowledge bit is loaded automatically.

Transfer of the next data for transmission can be suspended automatically on reception of a notacknowledge bit.



For reception, the acknowledge bit is transmitted automatically.

If a wait between the eighth and ninth clock cycles has been selected, software control of the value in the acknowledge field in response to the received value is possible.

Wait function

SDA output delay function

For reception, the following wait periods can be obtained by holding the SCL clock at the low level:

Wait between the eighth and ninth clock cycles

Wait between the ninth and first clock cycles

Timing of the output of transmitted data, including the acknowledge bit, can be delayed.

For reception, the following wait periods can be obtained by holding the SCL clock at the low level:

Wait between the eighth and ninth clock cycles

Wait between the ninth and first clock cycles

Timing of the output of transmitted data, including the acknowledge bit, can be delayed.

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Item

Arbitration

Timeout detection function

Noise canceler

RX62T (RIIC)



Multi-master support

Operation to synchronize the SCL clock in cases of conflict with the SCL clock from another master is possible.

When issuing a start condition, loss of arbitration is detected by testing for non-matching of the signals for the

SDA line.

In master operation, loss of arbitration is detected by testing for non-matching of transmit data.



Loss of arbitration due to detection of a start condition while the bus is busy is detectable (to prevent the issuing of double start conditions).



Loss of arbitration in transfer of a notacknowledge bit due to the signals for the SDA line not matching is detectable.



Loss of arbitration due to non-matching of data is detectable in slave transmission.

The internal timeout function is capable of detecting long-interval stop of the SCL clock.

The interface incorporates digital noise filters for both the SCL and SDA inputs, and the bandwidth for noise cancellation by the filters is adjustable by software.

Interrupt sources Four sources



Communication error or event occurrence

Arbitration detection, NACK detection, timeout detection, start condition detection (including restart condition), stop condition detection



Receive data full (including matching with a slave address)



Transmit data empty (including matching with a slave address)



Transmit end


RIIC operating modes

Transition to module stop state can be specified.

Four

Master transmit mode, master receive mode, slave transmit mode, and slave receive mode

Table 2.27 Comparative Listing of I

2

C Bus Interface Registers

RX23T (RIICa)



Multi-master support

Operation to synchronize the SCL clock in cases of conflict with the SCL clock from another master is possible.

When issuing a start condition, loss of arbitration is detected by testing for non-matching of the signals for the

SDA line.

In master operation, loss of arbitration is detected by testing for non-matching of transmit data.



Loss of arbitration due to detection of a start condition while the bus is busy is detectable (to prevent the issuing of double start conditions).



Loss of arbitration in transfer of a notacknowledge bit due to the signals for the SDA line not matching is detectable.



Loss of arbitration due to non-matching of data is detectable in slave transmission.

The internal timeout function is capable of detecting long-interval stop of the SCL clock.

The interface incorporates digital noise filters for both the SCL and SDA inputs, and the bandwidth for noise cancellation by the filters is adjustable by software.

Four sources



Communication error or event occurrence

Arbitration detection, NACK detection, timeout detection, start condition detection (including restart condition), stop condition detection



Receive data full (including matching with a slave address)



Transmit data empty (including matching with a slave address)



Transmit end

Transition to module stop state can be specified.

Four

Master transmit mode, master receive mode, slave transmit mode, and slave receive mode

Register

ICMR2

TMOCNT

Bit

TMWE

RX62T (RIIC) RX23T (RIICa)

Timeout internal counter write enable bit



Timeout internal counter



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2.16 Serial Peripheral Interface

Table 2.28 shows a comparative overview of the serial peripheral interface and Table 2.29 shows a comparative listing

of the serial peripheral interface registers.

Table 2.28 Comparative Overview of Serial Peripheral Interface

Item RX62T (RSPI)

Number of channels

1 channel

RSPI transfer functions



Use of MOSI (master out/slave in),

MISO (master in/slave out), SSL (slave select), and RSPCK (RSPI clock) signals allows serial communication through SPI operation (4-wire method) or clock synchronous operation (3-wire method).



Transmit-only operation is available.



Serial communication is available in master and slave mode.



Switching of the polarity of RSPCK is supported.



Switching of the phase of RSPCK is supported.



Selectable between MSB-first and LSBData format

Bit rate first.



Transfer bit length is selectable among

8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits.



128-bit transmit/receive buffers



Up to four frames can be transferred in one round of transmission/reception

(with each frame consisting of up to 32 bits).



In master mode, the on-chip baud rate generator generates RSPCK by frequency-dividing PCLK (the division ratio ranges from 2 to 4096).



In slave mode, the minimum PCLK clock divided by 8 can be input as

RSPCK (the maximum frequency of

RSPCK is PCLK divided by 8).

Width at high level: 4 cycles of PCLK; width at low level: 4 cycles of PCLK



The transmit and receive buffers have a Buffer configuration double buffer configuration.



The transmit and receive buffers are each 128 bits in size.

Error detection



Mode fault error detection



Overrun error detection



Parity error detection

RX23T (RSPIa)

1 channel



Use of MOSI (master out/slave in),

MISO (master in/slave out), SSL (slave select), and RSPCK (RSPI clock) signals allows serial communication through SPI operation (4-wire method) or clock synchronous operation (3-wire method).



Transmit-only operation is available.



Communication mode: Full-duplex or transmit-only can be selected.



Switching of the polarity of RSPCK is supported.



Switching of the phase of RSPCK is supported.



Selectable between MSB-first and LSBfirst.



Transfer bit length is selectable among

8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits.



128-bit transmit/receive buffers



Up to four frames can be transferred in one round of transmission/reception

(with each frame consisting of up to 32 bits).



In master mode, the on-chip baud rate generator generates RSPCK by frequency-dividing PCLK (the division ratio ranges from 2 to 4096).



In slave mode, the minimum PCLK clock divided by 8 can be input as

RSPCK (the maximum frequency of

RSPCK is PCLK divided by 8).

Width at high level: 4 cycles of PCLK; width at low level: 4 cycles of PCLK



The transmit and receive buffers have a double buffer configuration.



The transmit and receive buffers are each 128 bits in size.



Mode fault error detection



Overrun error detection



Parity error detection

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Item

SSL control function

Control in master transfer

Interrupt sources

RX62T (RSPI)



Four SSL pins (SSLA0 to SSLA3) for each channel



In single-master mode, SSLA0 to

SSLA3 pins are output.



In multi-master mode: SSLA0 pin is input, and SSLA1 to SSLA3 pins are either output or unused.



In slave mode: SSLA0 pin is input, and

SSLA1 to SSLA3 pins are unused.



Controllable delay from SSL output assertion to RSPCK operation (RSPCK delay)

Setting range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)



Controllable delay from RSPCK stop to

SSL output negation (SSL negation delay)




Controllable wait for next-access SSL output assertion (next-access delay)




SSL polarity-change function



Transfers of up to eight commands can be performed sequentially in looped execution.



For each command, the following can be set: SSL signal value, bit rate,

RSPCK polarity/phase, transfer data length, LSB/MSB-first, burst, RSPCK delay, SSL negation delay, and nextaccess delay



A transfer can be initiated by writing to the transmit buffer.



The MOSI signal value when SSL is negated can be specified.

Interrupt sources:

Receive buffer full interrupt, transmit buffer empty interrupt, RSPI error interrupt (mode fault, overrun, parity error), RSPI idle interrupt (RSPI idle)

Other functions



Function for initializing the RSPI



Loopback mode function



RX23T (RSPIa)



Four SSL pins (SSLA0 to SSLA3) for each channel



In single-master mode, SSLA0 to

SSLA3 pins are output.



In multi-master mode: SSLA0 pin is input, and SSLA1 to SSLA3 pins are either output or unused.



In slave mode: SSLA0 pin is input, and

SSLA1 to SSLA3 pins are unused.



Controllable delay from SSL output assertion to RSPCK operation (RSPCK delay)




Controllable delay from RSPCK stop to

SSL output negation (SSL negation delay)




Controllable wait for next-access SSL output assertion (next-access delay)Setting range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)



SSL polarity-change function



Transfers of up to eight commands can be performed sequentially in looped execution.



For each command, the following can be set: SSL signal value, bit rate,

RSPCK polarity/phase, transfer data length, LSB/MSB-first, burst, RSPCK delay, SSL negation delay, and nextaccess delay



A transfer can be initiated by writing to the transmit buffer.



The MOSI signal value when SSL is negated can be specified.



RSPCK auto-stop function

Interrupt sources:

Receive buffer full interrupt, transmit buffer empty interrupt, RSPI error interrupt (mode fault, overrun, parity error), RSPI idle interrupt (RSPI idle)



Function for switching between CMOS output and open-drain output



Function for initializing the RSPI



Loopback mode function


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Table 2.29 Comparative Listing of Serial Peripheral Interface Registers

Register

SPDCR

SPCR2

Bit

SLSEL[1:0]

SCKASE

RX62T (RSPI)

SSL pin output select bits



RX23T (RSPIa)



RSPCK auto-stop function enable bit

2.17 12-Bit A/D Converter

Table 2.30 shows a comparative overview of the 12-bit A/D converter and Table 2.31 shows a comparative listing of

the 12-bit A/D converter registers.

Table 2.30 Comparative Overview of 12-Bit A/D Converter

Item RX62T (S12ADA)

Number of 2 units units

Input channels 8 channels (4 channels



2 units)

Extended

 analog function

Successive approximation method A/D conversion method

Resolution

Conversion time

A/D conversion clock

12 bits



1.0 µs per channel

(when operating with A/D conversion clock ADCLK = 50 MHz and AVCC0 =

4.0 V to 5.5 V)



2.0 µs per channel

(when operating with A/D conversion clock ADCLK = 25 MHz and AVCC0 =

3.0 V to 3.6 V)



Settable to PCLK divided by 1, 2, 4, or 8

(ADCSR.CKS[1:0]).

RX23T (S12ADE)

1 unit

10 channels

Internal reference voltage

Successive approximation method

12 bits



1.0 µs per channel

(when operating with A/D conversion clock ADCLK = 40 MHz)

Data register



10 registers for analog input



2 registers for self-diagnostics



The results of A/D conversion are stored in 12-bit A/D data registers.



Output with 12-bit accuracy supported for

A/D conversion results.



Settable to ICLK divided by 1, 2, 4, 8, 16,

32, or 64 ( SCKCR.PCKD[3:0] ).



Peripheral module clock PCLK and A/D conversion clock ADCLK can be set so that the frequency ratio is one of the following:

PCLK:ADCLK frequency ratio = 1:1, 1:2,

2:1, 4:1, 8:1

ADCLK is set using the clock generation circuit.



10 registers for analog input, 1 for A/Dconverted data duplication in double trigger mode, and 2 for A/D-converted data duplication during extended operation in double trigger mode



1 register for internal reference voltage



1 register for self-diagnostics



The results of A/D conversion are stored in 12-bit A/D data registers.



Output with 12-bit accuracy supported for

A/D conversion results.

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Item

Data register

Operating mode

RX62T (S12ADA)



Single mode: Analog inputs of one channel are converted only once.



Single-cycle scan mode: Analog inputs of up to four channels are converted only once.



Continuous scan mode: A/D conversion is performed repeatedly on the analog inputs of up to 4 channels.



2-channel scan mode: Channels in each unit are divided into two groups and the conversion startup source can be selected separately for each group.

RX23T (S12ADE)



The value obtained by adding up A/Dconverted results is stored as a value

(number of conversion accuracy bits + 2 bits/4 bits) in the A/D data registers in

A/D-converted value addition mode.



Double trigger mode (selectable in single scan and group scan modes): The first piece of A/D-converted analog-input data on one selected channel is stored in the data register for the channel, and the second piece is stored in the duplication register.



Extended operation in double trigger mode (available for specific triggers):

A/D-converted analog-input data on one selected channel is stored in the duplication register that is prepared for each type of trigger.



Single scan mode: A/D conversion is performed only once on the analog inputs of up to 10 channels arbitrarily selected. A/D conversion is performed only once on the internal reference voltage.



Continuous scan mode: A/D conversion is performed repeatedly on the analog inputs of up to 10 channels.



Group scan mode: Analog inputs of up to

10 user-selected channels are divided into group A and group B, and A/D conversion of the analog input selected on a group basis is performed only once.

The conditions for scanning start of group A and group B (synchronous trigger) can be selected independently, allowing A/D conversion of group A and group B to be started independently.



Group scan mode (when group A has priority): If a group A trigger is input during A/D conversion on group B, the

A/D conversion on group B is stopped and A/D conversion is performed on group A. Restart (rescan) of A/D conversion on group B after completion of A/D conversion on group A can be specified.

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Item

A/D conversion start conditions

Functions

Interrupt source


RX62T (S12ADA)



Software trigger



Synchronous trigger

Conversion start is triggered by multifunction timer pulse unit 3 (MTU3) or the general PWM timer (GPT).



Asynchronous trigger

A/D conversion can be externally triggered from the ADTRG0# pin for

S12AD0 and from the ADTRG1# pin for

S12AD1.



Channel-dedicated sample-and-hold function (3 channels)



Self-diagnostic function for 12-bit A/D converter



Input signal amplification function using programmable gain amplifier (3 channels per unit)



Window comparator function (3 channels per unit)



An interrupt request (S12ADI) can be generated on completion of A/D conversion in each unit.



A S12ADI interrupt can activate the data transfer controller (DTC).

RX23T (S12ADE)



Software trigger



Synchronous trigger

Conversion start is triggered by the multifunction timer pulse unit 3 (MTU3c) or the 8-bit timer (TMR) .



Asynchronous trigger

A/D conversion can be triggered by the

ADTRG0# pin.



Channel-dedicated sample-and-hold function (3 channels)



Variable sampling state count



Self-diagnostic function for 12-bit A/D converter



Selectable A/D-converted value adding mode or averaging mode



Analog input disconnection detection function (discharge function/precharge function)



Double trigger mode (duplication of A/D conversion data)



Automatic clear function for A/D data registers



In modes other than double trigger mode and group scan mode, an A/D scan end interrupt request (S12ADI) can be generated on completion of a single scan.



In double trigger mode, an A/D scan end interrupt request (S12ADI) can be generated on completion of a double scan.



In group scan mode, an A/D scan end interrupt request (S12ADI) can be generated on completion of a group A scan, whereas an A/D scan end interrupt request (GBADI) for group B can be generated on completion of a group B scan.



When double trigger mode is selected in group scan mode, an A/D scan end interrupt request (S12ADI) can be generated on completion of a double scan of group A, whereas an A/D scan end interrupt request (GBADI) specifically for group B can be generated on completion of a group B scan.



The S12ADI and GBADI interrupts can activate the data transfer controller

(DTC).

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Item

Interrupt source

RX62T (S12ADA)



An interrupt request (CMPI) can be generated when comparator detection occurs (can also be used for a POE source).


RX23T (S12ADE)



Table 2.31 Comparative Listing of 12-Bit A/D Converter Registers

Register

ADDBLDR

ADDBLDRA

ADDBLDRB

ADOCDR

ADCSR

ADANS

Bit

CKS[1:0]

DBLANS[4:0]

GBADIE

DBLE

PG000EN

RX62T (S12ADA)









Clock select bits





RX23T(S12ADE)

A/D data duplication register

A/D data duplication register A

A/D data duplication register B

A/D internal reference voltage data register



Double trigger channel select bits

Group B scan end interrupt enable bit

Double trigger mode select bit



PG001EN

PG002EN

PG000SEL

PG001SEL

PG002SEL

CH[1:0]



AN000 programmable gain amplifier enable bit



AN000 programmable gain amplifier select bit



Channel setting bits













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Register

ADANSA0

Bit

ANSA000

ADANSA1

ADANSB0

ADANSB1

ADADS0

ANSA101

ANSB000

ANSB001

ANSB002

ANSB003

ANSB004

ANSB005

ANSB006

ANSA001

ANSA002

ANSA003

ANSA004

ANSA005

ANSA006

ANSA007

ANSA100

ANSB007

ANSB100

ANSB101

ADS000

ADS001

ADS002

ADS003

ADS004


















































RX62T (S12ADA)



RX23T(S12ADE)

A/D conversion channel select select bits




















A/D-converted value addition/average channel select bits




A/D-converted value addition/average channel select

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Register

ADADS1

ADADC

ADCER

ADSTRGR

ADPG

ADCMPMD0

ADCMPMD1


Bit RX62T (S12ADA) RX23T(S12ADE)

bits

ADS005




ADS006




ADS007




ADS100




ADS101



A/D-converted value addition/average channel select

CEN000[1:0]

CEN001[1:0]

CEN002[1:0]

CEN100[1:0]

CEN101[1:0]

CEN102[1:0]

REFL[2:0]

AN000 comparator select bits






Internal voltage for comparator low reference voltage select bits bits

ADC[2:0]

AVEE

SHBYP





Dedicated sample-and-hold circuit select bit

PG002GAIN[3:0] AN002 programmable gain amplifier gain select bits

Addition count select bits

Average mode enable bit



ADPRC[1:0] A/D data register bit precision setting bits




ADIE2

TRSB[5:0]

2-channel scan interrupt select



ADIEW

ADSTRS0[4:0] select bit

Double trigger interrupt select bit



A/D start trigger group 0 select

 bits



A/D conversion start trigger for group B select bits



ADSTRS1[4:0] A/D start trigger group 1 select

TRSA[5:0] bits




A/D conversion start trigger select bits





















REFH[2:0] Internal voltage for comparator high reference voltage select bits



CSEL0 AN000 to AN002 comparator input select bit



VSELH0 AN000 to AN002 comparator high reference voltage select bit



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Register Bit

VSELL0

ADCMPNR0

ADCMPNR1

ADCMPFR

ADCMPSEL

ADEXICR

SEL002

SEL100

SEL101

SEL102

IE

POERQ

OCSAD

CSEL1

VSELH1

VSELL1

C000NR[3:0]

C001NR[3:0]

C002NR[3:0]

C100NR[3:0]

C101NR[3:0]

C102NR[3:0]

C000FLAG

C001FLAG

C002FLAG

C100FLAG

C101FLAG

C102FLAG

SEL000

SEL001

ADSHCR

OCSA

SSTSH[7:0]

SHANS[2:0]


RX62T (S12ADA)

AN000 to AN002 comparator low reference voltage select bit

RX23T(S12ADE)



AN100 to AN102 comparator input select bit



AN100 to AN102 comparator high reference voltage select bit



AN100 to AN102 comparator low reference voltage select bit



AN000 comparator noise cancellation filter mode select bits










AN002 comparator detection select bit







AN102 comparator noise

 cancellation filter mode select bits

AN000 comparator detection flag


















AN000 comparator detection

 select bit














Interrupt enable setting bit

POE request setting bit







Internal reference voltage A/Dconverted value addition/average mode select bit



Internal reference voltage A/D conversion select bit



Channel-dedicated sample-andhold circuit sampling time setting bits



Channel-dedicated sample-andhold circuit bypass select bits

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Register

ADDISCR

Bit

ADNDIS[4:0]

ADGSPCR PGS

GBRSCN

GBRP

ADHVREFCNT HVSEL

LVSEL












RX62T (S12ADA)



RX23T(S12ADE)

A/D disconnection detection assist setting bits

Group A priority control setting bit

Group B restart setting bit

Group B single scan continuous start bit

High-potential reference voltage select bit

Low-potential reference voltage select bit

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2.18 RAM

Table 2.32 shows a comparative overview of the RAM.

Table 2.32 Comparative Overview of RAM

Item

RAM capacity

RAM address

Access


RX62T

16 KB or 8 KB

0000 0000h to 0000 3FFFh (16 KB)

0000 0000h to 0000 1FFFh (8 KB)



Single-cycle access is possible for both reading and writing.



The on-chip RAM can be enabled or disabled.


RX23T

12 KB

0000 0000h to 0000 27FFh,

0000 4000h to 0000 4A7Fh (12 KB)



Single-cycle access is possible for both reading and writing.



The on-chip RAM can be enabled or disabled.


2.19 Flash Memory

Table 2.33 shows a comparative listing of the flash memory specifications and Table 2.34 shows a comparative listing

of the flash memory registers.

Table 2.33 Comparative Listing of Flash Memory Specifications

RX62T

Item

Flash Memory for Code Storage

Memory space User area:

256 KB, 128 KB, or

64 KB

Read cycle

Value after erase

Interrupt

Programming/ erasing method

High-speed read operation using 1 cycle of ICLK is supported.

Can be read as FFFF

FFFFh in 32-bit access.

A flash ready interrupt request (FRDYI) is generated upon completion of FCU command execution

(program, P/E suspend, blank check, peripheral clock notify).



Flash Memory for Data Storage

Data area:

32 KB or 8 KB

A read operation in word or byte units takes 3 cycles of PCLK.

Undetermined

A flash ready interrupt request (FRDYI) is generated upon completion of FCU command execution

(program, P/E suspend, lock bit read 2, peripheral clock notify).

RX23T

User area: Maximum 128 KB

No ROM wait cycles when ICLK



32 MHz, ROM wait cycle when ICLK

> 32 MHz

FFh

An interrupt (FRDYI) is generated upon completion of software command processing or forced stop processing .



Software commands



The following software commands are implemented:

Program, blank check, block erase, all-block erase



The following commands are implemented for programming the extra area:

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Item

Programming/ erasing method

Background operation

(BGO) function

Suspension and resumption functions

Units of programming and erasure

On-board programming

Off-board programming


RX62T

Flash Memory Flash Memory for Code Storage for Data Storage



On-chip dedicated sequencer (FCU) for programming of the ROM



Programming and erasing the ROM are handled by issuing commands to the FCU.



The ROM in the erased state can be read as

FFFF FFFFh in 32-bit access.



The CPU is able to execute program code from areas other than the ROM or data flash while the

ROM is being programmed or erased.



Execution of program code from the ROM is possible while the data flash memory is being programmed or erased.



The CPU is able to execute program code from the ROM when programming or erasure of the

ROM is suspended.



Programming and erasure of the ROM can be restarted (resumed) after suspension.



Unit of programming



Unit of programming for the user area: 256 bytes



Units of erasure for the user area: 4 KB

(8 blocks), 16 KB

(when the ROM size is 256 KB: 14 blocks, when the ROM size is 128 KB: 6 blocks, and when the ROM size is 64 KB:

2 blocks) for the data area: 8 or

128 bytes



Unit of erasure for the data area: 2 KB

(32 KB data flash: 16 blocks; 8 KB data flash: 4 blocks)

Programming in boot mode



The asynchronous serial interface (SCI1) is used.



The transfer rate is adjusted automatically.

RX23T









Unit of programming for the user area: 8 bytes



Unit of erasure for the user area:

2 KB

Programming in boot mode



The asynchronous serial interface (SCI1) is used.



The transfer rate is adjusted automatically.



FINE is used.

Programming by a routine for ROM/data flash programming within the user program



This allows ROM programming without resetting the system.

A PROM programmer can be used to program

 the user area.

Programming by a routine for

ROM/data flash programming within the user program

The user area can be programmed using a flash programmer compatible with this the RX23T

Group.

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Item

Softwarecontrolled protection function

Error protection function

ID code protection

RX62T

Flash Memory for Code Storage

The

FENTRYR.FENTRY0 bit,

FWEPROR.FLWE[1:0] bits, and lock bits can be used to prevent unintentional programming.

Flash Memory for Data Storage

The

FENTRYR.FENTRYD bit,

FWEPROR.FLWE[1:0] bits, and DFLREk and

DFLWEk registers, can be used to prevent unintentional programming (k = 0 or

1).

Prevents further programming or erasure after the detection of abnormal operation during programming or erasure.





This function can be used to prevent reading, writing, or erasing by the host.

ID codes can be used for control when connected to an on-chip debugging emulator.

RX23T

The FENTRYR.FENTRY0 bit used to prevent unintentional programming.



can be



Connection with the serial programmer in boot mode can be enabled or disabled using ID codes in boot mode.



ID codes can be used for control when connected to an on-chip debugging emulator.

This function is used to safely rewrite blocks 0 to 7.

Start-up program protection function

Area protection









This function enables rewriting only the selected blocks in the user area and disables writing to the other blocks during self-programming.

Table 2.34 Comparative Listing of Flash Memory Registers

Register

FMODR

FASTAT

FAEINT

Bit

FRDMD

DFLWPE

DFLRPE

DFLAE

CMDLK

ROMAE

DFLWPEIE

DFLRPEIE

DFLAEIE

CMDLKIE

ROMAEIE

RX62T

FCU read mode select bit

Data flash programming/erasure protection violation bit

Data flash read protection violation bit

Data flash access violation bit

FCU command lock bit

ROM access violation bit

Data flash programming/erasure protection violation interrupt enable bit

Data flash read protection violation interrupt enable bit

Data flash access violation interrupt enable bit

FCU command lock interrupt enable bit

ROM access violation interrupt enable bit

RX23T























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Register

FCURAME

FSTATR0

Bit

FCRME

KEY[7:0]

PRGSPD

ERERR

ERSSPD

PRGERR

SUSRDY

BCERR

ERSERR

EILGLERR

FSTATR1

FRDYIE

FENTRYR

FPROTR

FRESETR

FCMDR

FCPSR

FPESTAT

PCKAR

FWEPROR

DFLRE0

DFLRE1


RX62T

FCU RAM enable bit

Key code

Programming suspend status bit



Erasure suspend status bit

Programming error bit

Suspend ready bit



Erasure error bit



FRDY

FLOCKST

FRDY

FCUERR

EXRDY

FRDYIE

FENTRYD

FPROTCN

FPKEY[7:0]

FRKEY[7:0]

PCMDR[7:0]

CMDR[7:0]

Flash ready bit

Lock bit status bit



FCU error bit



Flash ready interrupt enable bit

Data flash P/E mode entry bit

Lock bit protection cancel bit

Key code

Key code

Precommand

Command

ESUSPMD Erasure suspend mode bit

PEERRST[7:0] P/E error status bits

PCKA[7:0]

FLWE[1:0]

Peripheral clock notification bits

Flash programming/erasure bits

DBRE00

DBRE01

DBRE02

DBRE03

DBRE04

DBRE05

DBRE06

DBRE07

DB00 block read enable bit








KEY[7:0]

DBRE08

DBRE09

DBRE10

DBRE11

DBRE12

DBRE13

DBRE14

DBRE15

KEY[7:0]

Key code









Key code

RX23T







Erase error flag



Program error flag



Blank check error flag

Extra area illegal command error flag





Flash ready flag





















































Extra area ready flag









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Register

DFLWE0

DFLWE1

Bit

DBWE00

DBWE01

DBWE02

DBWE03

DBWE04

DBWE05

DBWE06

DBWE07

KEY[7:0]

DBWE08

DBWE09

DBWE10

DBWE11

DBWE12

DBWE13

DBWE14

DBWE15

KEY[7:0]

DFLBCCNT BCSIZE

BCADR[7:0]

DFLBCSTAT BCST

FPR

FPSR

FPMCR

PERR

FMS0

FISR

FASR

FCR

RPDIS

FMS1

LVPE

FMS2

PCKA[4:0]

SAS[1:0]

EXS

CMD[3:0]

STOP

OPST






RX62T

DB00 block programming/erasure enable bit








Key code









Key code

Blank check size setting bit

Blank check address setting bits













Blank check status bit











RX23T











































Protection unlock register

Protect error flag

Flash operating mode select bit 0

ROM P/E disable bit


Low-voltage P/E mode enable bit


Peripheral clock notification bits

Start-up area select bits

Extra area select bit

Software command setting setting bits

Forced processing stop bit

Processing start bit

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 52 of 55


Register

FEXCR

FSARH

FSARL

FEARH

FEARL

FWBn

(n = 0 to 3)

FEAMH

Bit

CMD[2:0]

OPST










RX62T







RX23T

Software command setting bits

Processing start bit

Flash processing start address register H

Flash processing start address register L

Flash processing end address register H

Flash processing end address register L

Flash write buffer n register



FEAML

FSCMR

FAWSMR

FAWEMR

SASMF











Flash error address monitor register

H

Flash error address monitor register

L

Start-up area setting monitor flag

Flash access window start address monitor register

Flash access window end address monitor register

Unique ID register n UIDRn

(n = 0 to 3)

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 53 of 55


3. Reference Documents

User’s Manual: Hardware

RX62T Group, RX62G Group User’s Manual: Hardware Rev.2.00 (R01UH0034EJ0200)

(The latest version can be downloaded from the Renesas Electronics website.)

RX23T Group User’s Manual: Hardware Rev.1.10 (R01UH0520EJ0110)


Technical Update/Technical News


R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 54 of 55


Website and Support

Renesas Electronics Website http://www.renesas.com/

Inquiries http://www.renesas.com/contact/

All trademarks and registered trademarks are the property of their respective owners.

R01AN2823EJ0110_RX23T Rev.1.10

Jan 14, 2016

Page 55 of 55

Revision History

Rev.

1.00

1.01

1.10

Date

Aug. 4, 2015

Sep. 16, 2015

Dec. 7, 2015

Description

Page



3

7

9

Summary

First edition issued

2.2 Resets

Table 2.2 Comparative Listing of Reset Specifications

Power-on reset description for RX23T amended

2.4 Clock Generation Circuit

Table 2.6 Comparative Listing of Clock Generation Circuit

Specifications

Error in PLL input frequency for RX62T amended. Frequency multiplication ratio description added

2.5 Low Power Consumption Functions

Table 2.8 Comparative Listing of Low Power Consumption

Functions

RSTSR register bit symbol error amended

24

30

34

40

45 to 47

7

9

20

2.12 Port Output Enable 3

Table 2.20 Comparative Overview of Port Output Enable 3

Error related to GPT0 pins, target pins to be placed in highimpedance state, amended

2.13 Independent Watchdog Timer

Table 2.22 Comparative Overview of Independent Watchdog

Timer

Description of register start mode on RX62T added

2.14 Serial Communication Interface

Table 2.25 Comparative Listing of Serial Communication

Interface Registers

Errors in bit names in TDRH, TDRL, and TDRHL registers amended

2.17 12-Bit A/D Converter

Table 2.30 Comparative Overview of 12-Bit A/D Converter

Errors in description of operating modes of RX62T amended

2.19 Flash Memory

Table 2.33 Comparative Listing of Flash Memory

Specifications

Description of of RX62T interrupt amended

Description of on-board programming of RX62T and RX23T amended

Error in description of area protection amended



Specifications

High-Speed On-Chip Oscillator (HOCO) added



Registers

High-Speed On-Chip Oscillator Control Register (HOCO) added

High-Speed On-Chip Oscillator Wait Control Register

(HOCOWTCR) added

Oscillation Stabilization Flag Register (OSCOVFSR) HOCO clock oscillation stabilization flag added

2.10 I/O Ports

Table 2.17 Comparative Listing of I/O Port Registers

Open Drain Control Register 1 (ODR1) changed

A-1

Rev.

1.10

Date

Dec. 7, 2015

Description

Page Summary

21

40

44, 45

48

2.11 Multi-Function Timer Pulse Unit 3

Table 2.18 Comparative Overview of Multi-Function Timer

Pulse Unit 3

Description of of RX23T Count clock amended

2.16 Serial Peripheral Interface

Table 2.29 Comparative Listing of Serial Peripheral Interface

Registers

SPSR register deleted

2.17 12-Bit A/D Converter

Table 2.31 Comparative Listing of 12-Bit A/D Converter

Registers

ADANSA0 register bit symbol amended

ADANSB0 register bit symbol amended

ADANSA1 register bit symbol amended

ADANSB1 register bit symbol amended

ADADS0 register bit symbol amended

ADADS1 register bit symbol amended

2.18 RAM

Table 2.32 Comparative Overview of RAM

Description of of RX23T RAM capacity amended

Description of of RX23T RAM address amended

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.



The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.



The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.



The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become stable.

When switching the clock signal during program execution, wait until the target clock signal has stabilized.



When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal.

Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to a product with a different type number, confirm that the change will not lead to problems.



The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product.

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.

5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below.

"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations.

10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

SALES OFFICES

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.

2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.

Tel: +1-408-588-6000, Fax: +1-408-588-6130

Renesas Electronics Canada Limited

9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3

Tel: +1-905-237-2004

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K

Tel: +44-1628-585-100, Fax: +44-1628-585-900

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-6503-0, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.

Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

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Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333

Tel: +86-21-2226-0888, Fax: +86-21-2226-0999

Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2265-6688, Fax: +852 2886-9022

13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949

Tel: +65-6213-0200, Fax: +65-6213-0300

Renesas Electronics Malaysia Sdn.Bhd.

Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics India Pvt. Ltd.

No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India

Tel: +91-80-67208700, Fax: +91-80-67208777

12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141 http://www.renesas.com

© 2016 Renesas Electronics Corporation. All rights reserved.

Colophon 5.0

Renesas RX23T Group, RX62T Group microcontroller Application note

Assistant Bot

APPLICATION NOTE

Points of Difference Between RX23T Group and RX62T Group

Introduction

Target Device

Contents

1. Comparison of Functions of RX23T Group and RX62T Group

2. Comparative Overview of Functions

2.1 Operating Modes

2.2 Resets

2.3 Voltage Detection Circuit

2.4 Clock Generation Circuit

2.5 Low Power Consumption Functions

2.6 Interrupt Controller

2.7 Bus

2.8 Memory Protection Unit

2.9 Data Transfer Controller

2.10 I/O Ports

2.11 Multi-Function Timer Pulse Unit 3

2.12 Port Output Enable 3

2.13 Independent Watchdog Timer

2.14 Serial Communication Interface

2.15 I

C bus interface

2.16 Serial Peripheral Interface

2.17 12-Bit A/D Converter

2.18 RAM

2.19 Flash Memory

3. Reference Documents

Website and Support

Revision History

General Precautions in the Handling of MPU/MCU Products

Notice

Key Features

Frequently Answers and Questions

What are the key differences between the RX23T Group and RX62T Group microcontrollers?

What are the different operating modes available for both RX23T and RX62T microcontrollers?

What are the memory options available for both RX23T Group and RX62T Group microcontrollers?

Related manuals

Renesas

RX62T Group

Renesas

RX24T

Renesas

RX Family

Renesas

RX Family

Renesas

RX110 Group

Renesas

RX64M Group

Renesas

RZ/A1H Group

Renesas

RX62T

Renesas

RX23T

Renesas

RX62T Group

Renesas

RX62T Group

Renesas

RX600 RX62N

Table of contents